SN54LS490JD [MOTOROLA]
LS SERIES, ASYN NEGATIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, CDIP16, CERAMIC, DIP-16;
| 型号： | SN54LS490JD |
| 厂家： | 
MOTOROLA |
| 描述： | LS SERIES, ASYN NEGATIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, CDIP16, CERAMIC, DIP-16 计数器 |
| 文件： | 总5页 (文件大小：164K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54/74LS490
DUAL DECADE COUNTER
The SN54/74LS490 contains a pair of high-speed 4-stage ripple counters.
Each half of the SN54/74LS490 has individual Clock, Master Reset and Mas-
ter Set (Preset 9) inputs. Each section counts in the 8, 4, 2, 1 BCD code.
• Dual Version of SN54/74LS490
• Individual Asynchronous Clear and Preset to 9 for Each Counter
• Count Frequency — Typically 65 MHz
DUAL DECADE COUNTER
LOW POWER SCHOTTKY
• Input Clamp Diodes Limit High-Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
J SUFFIX
CERAMIC
CASE 620-09
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
PIN NAMES
LOADING (Note a)
D SUFFIX
SOIC
CASE 751B-03
HIGH
LOW
16
1
MS
MR
CP
Master Set (Set to 9) Input
Master Reset
Clock Input (Active LOW Going Edge)
Counter Outputs (Note b)
0.5 U.L.
0.5 U.L.
1.5 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
1.5 U.L.
Q –Q
0
5 (2.5) U.L.
3
ORDERING INFORMATION
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial
(74) Temperature Ranges.
SN54LSXXXJ
Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
LOGIC DIAGRAM (ONE HALF SHOWN)
TRUTH TABLE
OUTPUTS
COUNT
Q
Q
Q
Q
0
3
2
1
0
1
2
L
L
L
L
L
L
L
L
H
L
H
L
3
4
5
L
L
L
L
H
H
H
L
L
H
L
H
6
7
8
9
L
L
H
H
H
H
L
H
H
L
L
H
L
L
L
H
FAST AND LS TTL DATA
5-563
SN54/74LS490
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
V
CC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
T
A
Operating Ambient Temperature Range
54
74
– 55
0
25
25
125
70
°C
I
I
Output Current — High
Output Current — Low
54, 74
–0.4
mA
mA
OH
54
74
4.0
8.0
OL
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Min
Typ
Max
Symbol
Parameter
Input HIGH Voltage
Unit
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
V
2.0
V
IH
54
74
0.7
0.8
Guaranteed Input LOW Voltage for
All Inputs
V
V
V
Input LOW Voltage
V
IL
Input Clamp Diode Voltage
Output HIGH Voltage
–0.65
3.5
–1.5
V
V
V
V
V
= MIN, I = –18 mA
IN
IK
CC
54
74
2.5
2.7
= MIN, I
OH
= MAX, V = V
IN
CC
IH
OH
or V per Truth Table
IL
3.5
V
V
= V
CC
MIN,
= V or V
IL IH
54, 74
74
0.25
0.35
0.4
0.5
V
V
I
I
= 4.0 mA
= 8.0 mA
CC
IN
OL
V
OL
Output LOW Voltage
per Truth Table
OL
20
0.1
µA
V
V
= MAX, V = 2.7 V
IN
CC
I
I
Input HIGH Current
Input LOW Current
IH
mA
= MAX, V = 7.0 V
IN
CC
MS, MR
Clock
–0.4
–1.6
–100
26
mA
V
CC
= MAX, V = 0.4 V
IN
IL
I
I
Short Circuit Current (Note 1)
Power Supply Current
–20
mA
mA
V
V
= MAX
= MAX
OS
CC
CC
CC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC SET-UP REQUIREMENTS (T = 25°C, V
CC
= 5.0 V)
A
Limits
Typ
Symbol
Parameter
Any Pulse Width
MR or MS to Setup Time
Unit
ns
Test Conditions
= 5.0 V
Min
Max
t
t
20
25
W
V
CC
ns
s
FAST AND LS TTL DATA
5-564
SN54/74LS490
AC CHARACTERISTICS (T = 25°C)
A
Limits
Symbol
Parameter
Unit
Test Conditions
Min
Typ
Max
f
Maximum Clock Frequency
25
35
MHz
Figure 1
Figure 1
MAX
t
t
12
13
20
20
PLH
PHL
Propagation Delay, CP to Q
ns
ns
0
t
t
24
26
39
39
PLH
PHL
Propagation Delay, CP to Q or Q
Figure 3
1
3
V
C
= 5.0 V,
CC
= 15 pF
L
t
t
32
36
54
54
PLH
PHL
Propagation Delay, CP to Q
ns
ns
ns
Figure 2
Figure 2
Figure 2
2
t
Propagation Delay, MR to Output
Propagation Delay, MS to Output
24
39
PHL
t
t
24
20
39
36
PLH
PHL
AC WAVEFORMS
Figure 1
Figure 2
Figure 3
*The number of Clock Pulses required between the t
and t measurements can be determined from the Truth Table.
PLH
PHL
FAST AND LS TTL DATA
5-565
Case 751B-03 D Suffix
16-Pin Plastic
SO-16
-A-
16
1
9
8
P
C
-B-
R X 45°
G
-T-
J
M
F
D
°
°
°
°
K
Case 648-08 N Suffix
16-Pin Plastic
-A-
16
1
9
B
S
8
F
L
C
K
-T-
M
H
J
G
D
°
°
°
°
Case 620-09 J Suffix
16-Pin Ceramic Dual In-Line
-A-
16
9
-B-
1
8
L
C
-T-
K
M
N
E
J
F
G
D
°
°
°
°
FAST AND LS TTL DATA
5-566
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