SN54LS74J [MOTOROLA]
DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP; 双D型正边沿触发触发器
| 型号： | SN54LS74J |
| 厂家： | 
MOTOROLA |
| 描述： | DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP |
| 文件： | 总3页 (文件大小：77K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54/74LS74A
DUAL D-TYPE POSITIVE
EDGE-TRIGGERED FLIP-FLOP
The SN54/74LS74A dual edge-triggered flip-flop utilizes Schottky TTL cir-
cuitry to produce high speed D-type flip-flops. Each flip-flop has individual
clear and set inputs, and also complementary Q and Q outputs.
Information at input D is transferred to the Q output on the positive-going
edge of the clock pulse. Clock triggering occurs at a voltage level of the clock
pulse and is not directly related to the transition time of the positive-going
pulse. When the clock input is at either the HIGH or the LOW level, the D input
signal has no effect.
DUAL D-TYPE POSITIVE
EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
LOGIC DIAGRAM (Each Flip-Flop)
CASE 632-08
14
1
SET (S
)
D
4 (10)
Q
5 (9)
CLEAR (CD)
1 (13)
N SUFFIX
PLASTIC
CASE 646-06
CLOCK
3 (11)
14
Q
6 (8)
1
D
2 (12)
D SUFFIX
SOIC
CASE 751A-02
14
1
ORDERING INFORMATION
SN54LSXXJ
SN74LSXXN
SN74LSXXD
Ceramic
Plastic
SOIC
MODE SELECT — TRUTH TABLE
INPUTS
OUTPUTS
OPERATING MODE
S
D
S
D
D
Q
Q
Set
L
H
L
H
H
H
L
L
H
H
X
X
X
h
l
H
L
H
H
L
L
H
H
L
LOGIC SYMBOL
Reset (Clear)
*Undetermined
Load “1” (Set)
Load “0” (Reset)
4
10
H
S
S
D
D
5
6
9
8
2
3
D
Q
Q
12
11
D
Q
Q
* Both outputs will be HIGH while both S and C are LOW, but the output states are unpredictable
D
D
if S and C goHIGHsimultaneously. If the levels at the set and clear are near V maximumthen
D
D
IL
CP
CP
we cannot guarantee to meet the minimum level for V
.
OH
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
C
C
D
D
1
13
i, h (q) = Lower case letters indicate the state of the referenced input (or output) one set-up time
i, h (q) = prior to the HIGH to LOW clock transition.
V
= PIN 14
CC
GND = PIN 7
FAST AND LS TTL DATA
5-72
SN54/74LS74A
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
V
CC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
T
A
Operating Ambient Temperature Range
54
74
–55
0
25
25
125
70
°C
I
I
Output Current — High
Output Current — Low
54, 74
–0.4
mA
mA
OH
54
74
4.0
8.0
OL
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Min
Typ
Max
Symbol
Parameter
Input HIGH Voltage
Unit
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
V
IH
2.0
V
54
74
0.7
0.8
Guaranteed Input LOW Voltage for
All Inputs
V
V
V
Input LOW Voltage
V
IL
Input Clamp Diode Voltage
Output HIGH Voltage
–0.65
3.5
–1.5
V
V
V
V
V
= MIN, I = –18 mA
IN
IK
CC
54
74
2.5
2.7
= MIN, I
OH
= MAX, V = V
IN
CC
IH
OH
or V per Truth Table
IL
3.5
V
V
= V
CC
MIN,
= V or V
IL IH
54, 74
74
0.25
0.35
0.4
0.5
V
V
I
= 4.0 mA
= 8.0 mA
CC
IN
OL
OL
V
OL
Output LOW Voltage
I
per Truth Table
Input High Current
Data, Clock
Set, Clear
20
40
µA
mA
mA
V
CC
V
CC
V
CC
= MAX, V = 2.7 V
IN
I
I
IH
Data, Clock
Set, Clear
0.1
0.2
= MAX, V = 7.0 V
IN
Input LOW Current
Data, Clock
Set, Clear
–0.4
–0.8
= MAX, V = 0.4 V
IN
IL
I
I
Output Short Circuit Current (Note 1)
Power Supply Current
–20
–100
8.0
mA
mA
V
V
= MAX
= MAX
OS
CC
CC
CC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (T = 25°C, V
CC
= 5.0 V)
A
Limits
Typ
33
Min
Max
Symbol
Parameter
Unit
MHz
ns
Test Conditions
f
Maximum Clock Frequency
25
Figure 1
MAX
V
C
= 5.0 V
CC
= 15 pF
13
25
40
t
t
PLH
PHL
L
Clock, Clear, Set to Output
Figure 1
25
ns
AC SETUP REQUIREMENTS (T = 25°C)
A
Limits
Typ
Min
25
Max
Symbol
Parameter
Unit
ns
Test Conditions
Figure 1
t
Clock
W(H)
t
t
t
Clear, Set
25
ns
Figure 2
Figure 1
Figure 1
W(L)
20
ns
V
CC
= 5.0 V
Data Setup Time — HIGH
Data Setup Time — LOW
s
20
ns
Hold Time
5.0
ns
h
FAST AND LS TTL DATA
5-73
SN54/74LS74A
AC WAVEFORMS
1.3 V
1.3 V
D *
t
h(H)
t
h(L)
t
t
s(H)
s(L)
t
W(H)
t
W(L)
1.3 V
1.3 V
CP
Q
1
f
MAX
t
PHL
t
PLH
1.3 V
1.3 V
1.3 V
t
PHL
t
PLH
1.3 V
Q
*The shaded areas indicate when the input is permitted to change for predictable output performance.
Figure 1. Clock to Output Delays, Data
Set-Up and Hold Times, Clock Pulse Width
t
W
SET
1.3 V
1.3 V
t
W
CLEAR
1.3 V
1.3 V
t
t
PLH
PHL
1.3 V
1.3 V
Q
Q
t
t
PHL
PLH
1.3 V
1.3 V
Figure 2. Set and Clear to Output Delays,
Set and Clear Pulse Widths
FAST AND LS TTL DATA
5-74
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