SN74LS377D [MOTOROLA]
OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE; 八D触发器带使能; HEX D触发器带使能; 4位D触发器带使能
| 型号： | SN74LS377D |
| 厂家： | 
MOTOROLA |
| 描述： | OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE |
| 文件： | 总7页 (文件大小：253K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54/74LS377
SN54/74LS378
SN54/74LS379
OCTAL D FLIP-FLOP WITH ENABLE;
HEX D FLIP-FLOP WITH ENABLE;
4-BIT D FLIP-FLOP WITH ENABLE
OCTAL D FLIP-FLOP WITH
ENABLE; HEX D FLIP-FLOP
WITH ENABLE; 4-BIT D FLIP-FLOP
WITH ENABLE
The SN54/74LS377 is an 8-bit register built using advanced Low Power
Schottky technology. This register consists of eight D-type flip-flops with a
buffered common clock and a buffered common clock enable.
The SN54/74LS378 is a 6-Bit Register with a buffered common enable.
This device is similar to the SN54/74LS174, but with common Enable rather
than common Master Reset.
LOW POWER SCHOTTKY
The SN54/74LS379 is a 4-Bit Register with buffered common Enable. This
device is similar to the SN54/74LS175 but features the common Enable
rather then common Master Reset.
J SUFFIX
CERAMIC
• 8-Bit High Speed Parallel Registers
CASE 732-03
• Positive Edge-Triggered D-Type Flip Flops
• Fully Buffered Common Clock and Enable Inputs
• True and Complement Outputs
20
1
• Input Clamp Diodes Limit High Speed Termination Effects
N SUFFIX
PLASTIC
CASE 738-03
PIN NAMES
LOADING (Note a)
20
1
HIGH
LOW
E
Enable (Active LOW) Input
Data Inputs
Clock (Active HIGH Going Edge) Input
True Outputs (Note b)
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
D –D
CP
Q –Q
Q –Q
0
3
DW SUFFIX
SOIC
CASE 751D-03
20
0
0
3
3
1
Complemented Outputs (Note b)
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial
(74) Temperature Ranges.
J SUFFIX
CERAMIC
CASE 620-09
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
16
1
ORDERING INFORMATION
SN54LSXXXJ
Ceramic
SN74LSXXXN Plastic
SN74LSXXXDW SOIC
SN74LSXXXD SOIC
FAST AND LS TTL DATA
5-533
SN54/74LS377 • SN54/74LS378 • SN54/74LS379
CONNECTION DIAGRAM DIPS (TOP VIEW)
SN54/74LS377
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
SN54/74LS378
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
SN54/74LS379
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
FAST AND LS TTL DATA
5-534
SN54/74LS377 • SN54/74LS378 • SN54/74LS379
LOGIC DIAGRAMS
SN54/74LS377
SN54/74LS378
SN54/74LS379
FAST AND LS TTL DATA
5-535
SN54/74LS377 • SN54/74LS378 • SN54/74LS379
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
V
CC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
T
A
Operating Ambient Temperature Range
54
74
–55
0
25
25
125
70
°C
I
I
Output Current — High
Output Current — Low
54, 74
–0.4
mA
mA
OH
54
74
4.0
8.0
OL
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Input HIGH Voltage
Unit
Test Conditions
Min
Typ
Max
Guaranteed Input HIGH Voltage for
All Inputs
V
2.0
V
IH
54
74
0.7
0.8
Guaranteed Input LOW Voltage for
All Inputs
V
V
V
Input LOW Voltage
V
IL
Input Clamp Diode Voltage
Output HIGH Voltage
–0.65
3.5
–1.5
V
V
V
V
= MIN, I = –18 mA
IN
IK
CC
CC
54
74
2.5
2.7
V
= MIN, I
OH
= MAX, V = V
IN
IH
OH
or V per Truth Table
IL
3.5
V
V
= V
CC
MIN,
= V or V
IL IH
54, 74
74
0.25
0.35
0.4
0.5
V
V
I
I
= 4.0 mA
= 8.0 mA
CC
IN
OL
OL
V
Output LOW Voltage
Input HIGH Current
OL
per Truth Table
20
0.1
µA
mA
mA
mA
V
V
V
V
= MAX, V = 2.7 V
IN
CC
CC
CC
CC
I
IH
= MAX, V = 7.0 V
IN
I
I
Input LOW Current
–0.4
–100
= MAX, V = 0.4 V
IN
IL
Short Circuit Current (Note 1)
–20
= MAX
OS
LS377
LS378
LS379
28
22
15
I
Power Supply Current
mA
V
CC
= MAX, NOTE 1
CC
NOTE: With all inputs open and GND applied to all data and enable inputs, I
is measured after a momentary GND, then 4.5 V is applied to clock.
CC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (T = 25°C, V
CC
= 5.0 V)
A
Limits
Typ
Symbol
Parameter
Min
Max
Unit
Test Conditions
f
Maximum Clock Frequency
30
40
MHz
MAX
V
C
= 5.0 V
CC
= 15 pF
t
t
Propagation Delay,
Clock to Output
17
18
27
27
PLH
PHL
L
ns
AC SETUP REQUIREMENTS (T = 25°C, V
= 5.0 V)
A
CC
Limits
Typ
Symbol
Parameter
Any Pulse Width
Min
Max
Unit
ns
Test Conditions
t
t
20
20
10
25
5.0
W
Data Setup Time
ns
s
Inactive — State
Active — State
ns
V
CC
= 5.0 V
Enable Setup
Time
t
s
ns
t
Any Hold Time
ns
h
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time required
forthecorrectlogiclevel tobepresentatthelogicinputpriorto
the clock transition from LOW-to-HIGH in order to be recog-
nized and transferred to the outputs.
the clock transition from LOW-to-HIGH that the logic level
must be maintained at the input in order to ensure continued
recognition. A negative HOLD TIME indicates that the correct
logic level may be released prior to the clock transition from
LOW-to-HIGH and still be recognized.
HOLD TIME (t ) — is defined as the minimum time following
h
FAST AND LS TTL DATA
5-536
SN54/74LS377 • SN54/74LS378 • SN54/74LS379
TRUTH TABLE
E
CP
D
Q
Q
n
n
n
H
X
No
No
Change Change
L
L
H
L
H
L
L
H
L = LOW Voltage Level
H = HIGH Voltage Level
X = Immaterial
AC WAVEFORMS
SN54/74LS377
SN54/74LS378
Figure 1. Clock to Output Delays Clock Pulse
Width, Frequency, Setup and Hold Times Data
or Enable to Clock
Figure 2. Clock to Output Delays Clock Pulse
Width, Frequency, Setup and Hold Times Data
or Enable to Clock
SN54/74LS379
*The shaded areas indicate when the input is permitted to change for predictable output performance.
Figure 3. Clock to Output Delays Clock Pulse
Width, Frequency, Setup and Hold Times Data,
Enable to Clock
FAST AND LS TTL DATA
5-537
Case 751B-03 D Suffix
16-Pin Plastic
SO-16
-A-
16
1
9
8
P
C
-B-
R X 45°
G
-T-
J
M
F
D
°
°
°
°
K
Case 648-08 N Suffix
16-Pin Plastic
-A-
16
1
9
B
S
8
F
L
C
K
-T-
M
H
J
G
D
°
°
°
°
Case 620-09 J Suffix
16-Pin Ceramic Dual In-Line
-A-
16
9
-B-
1
8
L
C
-T-
K
M
N
E
J
F
G
D
°
°
°
°
FAST AND LS TTL DATA
5-538
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