SN74LSXXXN [MOTOROLA]
UNIVERSAL 4-BIT SHIFT REGISTER; UNIVERSAL 4位移位寄存器
| 型号： | SN74LSXXXN |
| 厂家： | 
MOTOROLA |
| 描述： | UNIVERSAL 4-BIT SHIFT REGISTER |
| 文件： | 总6页 (文件大小：223K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54/74LS195A
UNIVERSAL 4-BIT
SHIFT REGISTER
The SN54/74LS195A is a high speed 4-Bit Shift Register offering typical
shift frequencies of 39 MHz. It is useful for a wide variety of register and
counting applications. It utilizes the Schottky diode clamped process to
achieve high speeds and is fully compatible with all Motorola TTL products.
UNIVERSAL 4-BIT
SHIFT REGISTER
• Typical Shift Right Frequency of 39 MHz
• Asynchronous Master Reset
LOW POWER SCHOTTKY
• J, K Inputs to First Stage
• Fully Synchronous Serial or Parallel Data Transfers
• Input Clamp Diodes Limit High Speed Termination Effects
J SUFFIX
CERAMIC
CASE 620-09
CONNECTION DIAGRAM DIP (TOP VIEW)
16
1
NOTE:
N SUFFIX
PLASTIC
CASE 648-08
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
16
1
D SUFFIX
SOIC
CASE 751B-03
16
1
PIN NAMES
LOADING (Note a)
HIGH
LOW
ORDERING INFORMATION
PE
Parallel Enable (Active LOW) Input
Parallel Data Inputs
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
P
0
J
– P
3
SN54LSXXXJ
Ceramic
First Stage J (Active HIGH) Input
First Stage K (Active LOW) Input
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Parallel Outputs (Note b)
SN74LSXXXN Plastic
SN74LSXXXD SOIC
K
CP
MR
Q
Q
– Q
10 U.L. 5 (2.5) U.L.
10 U.L. 5 (2.5) U.L.
0
3
3
LOGIC SYMBOL
Complementary Last Stage Output (Note b)
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
FAST AND LS TTL DATA
5-366
SN54/74LS195A
LOGIC DIAGRAM
FUNCTIONAL DESCRIPTION
The Logic Diagram and Truth Table indicate the functional
characteristics of the LS195A 4-Bit Shift Register. Thedevice
is useful in a wide variety of shifting, counting and storage
applications. It performs serial, parallel, serial to parallel, or
parallel to serial data transfers at very high speeds.
pinstogether. WhenthePEinputisLOW, theLS195Aappears
as four common clocked D flip-flops. The data on the parallel
inputs P , P , P , P is transferred to the respective Q , Q ,
0
1
2
3
0
1
Q , Q outputs following the LOW to HIGH clock transition.
2
3
Shiftleftoperations(Q º Q )canbeachievedbytyingtheQ
n
Outputs to the P inputs and holding the PE input LOW.
n–1
3
2
The LS195A has two primary modes of operation, shift right
(Q º Q )andparallelloadwhicharecontrolledbythestateof
All serial and parallel data transfers are synchronous,
occurring after each LOW to HIGH clock transition. Since the
LS195A utilizes edge-triggering, there is no restriction on the
0
1
the Parallel Enable (PE) input. When the PE input is HIGH,
serialdataentersthefirstflip-flopQ viatheJandKinputsand
0
isshiftedonebitinthedirectionQ º Q º Q º Q following
activity of the J, K, P and PE inputs for logic operation —
0
1
2
3
n
each LOW to HIGH clock transition. The JK inputs provide the
flexibility of the JK type input for special applications, and the
simple D type input for general applications by tying the two
except for the set-up and release time requirements.
A LOW on the asynchronous Master Reset (MR) input sets
all Q outputs LOW, independent of any other input condition.
MODE SELECT — TRUTH TABLE
INPUTS
OUTPUTS
OPERATING MODES
MR
PE
J
K
P
n
Q
Q
Q
Q
Q
0
1
2
3
3
Asynchronous Reset
L
X
X
X
X
L
L
L
L
H
Shift, Set First Stage
Shift, Reset First
Shift, Toggle First Stage
Shift, Retain First Stage
H
H
H
H
h
h
h
h
h
I
h
I
h
I
I
X
X
X
X
H
L
q
0
q
0
q
0
q
0
q
1
q
1
q
1
q
1
q
2
q
2
q
2
q
2
q
2
q
2
q
2
q
2
q
0
0
h
q
Parallel Load
H
I
X
X
p
n
p
0
p
1
p
2
p
3
p
3
L = LOW voltage levels
H = HIGH voltage levels
X = Don’t Care
I = LOW voltage level one set-up time prior to the LOW to HIGH clock transition.
h = HIGH voltage level one set-up time prior to the LOW to HIGH clock transition.
p
(q ) = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW to
n
n
HIGH clock transition.
FAST AND LS TTL DATA
5-367
SN54/74LS195A
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
V
CC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
T
A
Operating Ambient Temperature Range
54
74
–55
0
25
25
125
70
°C
I
I
Output Current — High
Output Current — Low
54, 74
–0.4
mA
mA
OH
54
74
4.0
8.0
OL
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Min
Typ
Max
Symbol
Parameter
Input HIGH Voltage
Unit
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
V
2.0
V
IH
54
74
0.7
0.8
Guaranteed Input LOW Voltage for
All Inputs
V
V
V
Input LOW Voltage
V
IL
Input Clamp Diode Voltage
Output HIGH Voltage
–0.65
3.5
–1.5
V
V
V
V
V
= MIN, I = –18 mA
IN
IK
CC
54
74
2.5
2.7
= MIN, I
OH
= MAX, V = V
IN
CC
IH
OH
or V per Truth Table
IL
3.5
V
V
= V
CC
MIN,
= V or V
IL IH
54, 74
74
0.25
0.35
0.4
0.5
V
V
I
I
= 4.0 mA
= 8.0 mA
CC
IN
OL
V
Output LOW Voltage
Input HIGH Current
OL
per Truth Table
OL
20
0.1
µA
mA
mA
mA
mA
V
V
V
V
V
= MAX, V = 2.7 V
IN
CC
CC
CC
CC
CC
I
IH
= MAX, V = 7.0 V
IN
I
I
I
Input LOW Current
–0.4
–100
21
= MAX, V = 0.4 V
IN
IL
Short Circuit Current (Note 1)
Power Supply Current
–20
= MAX
= MAX
OS
CC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (T = 25°C)
A
Limits
Typ
Symbol
Parameter
Unit
Test Conditions
Min
Max
f
Maximum Clock Frequency
30
39
MHz
MAX
t
t
Propagation Delay,
Clock to Output
14
17
22
26
PLH
PHL
V
C
= 5.0 V
ns
ns
CC
= 15 pF
L
Propagation Delay,
MR to Output
t
19
30
PHL
AC SETUP REQUIREMENTS (T = 25°C)
A
Limits
Typ
Symbol
Parameter
CP Clock Pulse Width
MR Pulse Width
Unit
ns
Test Conditions
Min
16
12
25
15
25
Max
t
t
t
t
t
t
t
W
W
s
ns
PE Setup Time
ns
Data Setup Time
Recovery Time
ns
V
CC
= 5.0 V
s
ns
rec
rel
h
PE Release Time
Data Hold Time
10
ns
0
ns
FAST AND LS TTL DATA
5-368
SN54/74LS195A
DEFINITIONS OF TERMS
SETUP TIME(t ) —is defined as the minimum time required
s
recognition. A negative HOLD TIME indicates that the correct
logic level may be released prior to the clock transition from
LOW to HIGH and still be recognized.
for the correct logic level to be present at the logic input prior
to the clock transition from LOW to HIGH in order to be
recognized and transferred to the outputs.
RECOVERY TIME (t ) — is defined as the minimum time
rec
HOLD TIME (t ) — is defined as the minimum time following
h
the clock transition from LOW to HIGH that the logic level must
be maintained at the input in order to ensure continued
required between the end of the reset pulse and the clock
transitionfromLOWtoHIGHinordertorecognizeandtransfer
HIGH Data to the Q outputs.
AC WAVEFORMS
The shaded areas indicate when the input is permitted to change for predictable output performance.
Figure 1. Clock to Output Delays and
Clock Pulse Width
Figure 3. Setup (t ) and Hold (t ) Time for Serial Data
s
h
(J & K) and Parallel Data (P , P , P , P )
0
1
2
3
Figure 2. Master Reset Pulse Width, Master Reset
to Output Delay and Master Reset to Clock
Recovery Time
Figure 4. Setup (t ) and Hold (t ) Time for PE Input
s
h
FAST AND LS TTL DATA
5-369
Case 751B-03 D Suffix
16-Pin Plastic
SO-16
-A-
16
1
9
8
P
C
-B-
R X 45°
G
-T-
J
M
F
D
°
°
°
°
K
Case 648-08 N Suffix
16-Pin Plastic
-A-
16
1
9
B
S
8
F
L
C
K
-T-
M
H
J
G
D
°
°
°
°
Case 620-09 J Suffix
16-Pin Ceramic Dual In-Line
-A-
16
9
-B-
1
8
L
C
-T-
K
M
N
E
J
F
G
D
°
°
°
°
FAST AND LS TTL DATA
5-370
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