SPAKXC16Z1CFC25 [MOTOROLA]
Microcontroller, 16-Bit, 25MHz, HCMOS, PQFP132, PLASTIC, SMT-132;型号: | SPAKXC16Z1CFC25 |
厂家: | MOTOROLA |
描述: | Microcontroller, 16-Bit, 25MHz, HCMOS, PQFP132, PLASTIC, SMT-132 微控制器 |
文件: | 总200页 (文件大小:1383K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Order this document
by MC68HC16Z1TS/D Rev. 3
MOTOROLA
SEMICONDUCTOR
TECHNICAL DATA
MC68HC16Z1
Technical Summary
16-Bit Microcontroller
1 Introduction
The MC68HC16Z1 is a high-speed 16-bit control unit that is upwardly code compatible with M68HC11
controllers. It is a member of the M68300/68HC16 Family of modular microcontrollers.
M68HC16 controllers are built up from standard modules that interface through a common internal bus.
Standardization facilitates rapid development of devices tailored for specific applications.
The MC68HC16Z1 incorporates a true 16-bit central processing unit (CPU16), a system integration
module (SIM), an 8/10-bit analog-to-digital converter (ADC), a queued serial module (QSM), a general-
purpose timer (GPT), and a 2048-byte standby RAM (SRAM). These modules are interconnected by
the intermodule bus (IMB).
Maximum system clock for the MC68HC16Z1 is 16.78 MHz. A phase-locked loop circuit synthesizes
the clock from a frequency reference. Either a crystal (nominal frequency: 32.768 kHz) or an externally
generated signal can be used. System hardware and software support changes in clock rate during op-
eration. Because the MC68HC16Z1 is a fully static design, register and memory contents are not affect-
ed by clock rate changes.
High-density complementary metal-oxide semiconductor (HCMOS) architecture makes the basic power
consumption of the MC68HC16Z1 low. Power consumption can be minimized by stopping the system
clock. The M68HC16 instruction set includes a low-power stop (LPSTOP) command that efficiently im-
plements this capability.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
M
© MOTOROLA INC., 1992, 1996
Table 1 Ordering Information
Device
Package
132-PIN
PLASTIC
SURFACE
MOUNT
Temperature
Range (°C)
–40 to 85
Reference
Frequency
16.78 MHz
Shipping
Method
Order
Number
XC16Z1CFC16
SPAKXC16Z1CFC16
XC16Z1CFC20
SPAKXC16Z1CFC20
XC16Z1CFC25
SPAKXC16Z1CFC25
XC16Z1VFC16
SPAKXC16Z1VFC16
XC16Z1VFC20
SPAKXC16Z1VFC20
XC16Z1VFC25
SPAKXC16Z1VFC25
XC16Z1MFC16
SPAKXC16Z1MFC16
XC16Z1MFC20
SPAKXC16Z1MFC20
XC16Z1MFC25
SPAKXC16Z1MFC25
XC16Z1CFD16
36 PER TRAY
2 PER TRAY
36 PER TRAY
2 PER TRAY
36 PER TRAY
2 PER TRAY
36 PER TRAY
2 PER TRAY
36 PER TRAY
2 PER TRAY
36 PER TRAY
2 PER TRAY
36 PER TRAY
2 PER TRAY
36 PER TRAY
2 PER TRAY
36 PER TRAY
2 PER TRAY
10 PER TUBE
10 PER TUBE
10 PER TUBE
10 PER TUBE
10 PER TUBE
10 PER TUBE
10 PER TUBE
10 PER TUBE
10 PER TUBE
44 PER TRAY
2 PER TRAY
44 PER TRAY
2 PER TRAY
44 PER TRAY
2 PER TRAY
44 PER TRAY
2 PER TRAY
44 PER TRAY
2 PER TRAY
44 PER TRAY
2 PER TRAY
44 PER TRAY
2 PER TRAY
44 PER TRAY
2 PER TRAY
44 PER TRAY
2 PER TRAY
13 PER TUBE
13 PER TUBE
13 PER TUBE
13 PER TUBE
13 PER TUBE
13 PER TUBE
13 PER TUBE
13 PER TUBE
13 PER TUBE
20 MHz
25 MHz
–40 to 105
–40 to 125
16.78 MHz
20 MHz
25 MHz
16.78 MHz
20 MHz
25 MHz
132-PIN
MOLDED
CARRIER
RING
–40 to 85
–40 to 105
–40 to 125
–40 to 85
16.78 MHz
20 MHz
25 MHz
16.78 MHz
20 MHz
25 MHz
16.78 MHz
20 MHz
25 MHz
XC16Z1CFD20
XC16Z1CFD25
XC16Z1VFD16
XC16Z1VFD20
XC16Z1VFD25
XC16Z1MFD16
XC16Z1MFD20
XC16Z1MFD25
144-PIN
PLASTIC
SURFACE
MOUNT
16.78 MHz
XC16Z1CFV16
SPAKXC16Z1CFV16
XC16Z1CFV20
SPAKXC16Z1CFV20
XC16Z1CFV25
SPAKXC16Z1CFV25
XC16Z1VFV16
SPAKXC16Z1VFV16
XC16Z1VFV20
SPAKXC16Z1VFV20
XC16Z1VFV25
SPAKXC16Z1VFV25
XC16Z1MFV16
SPAKXC16Z1MFV16
XC16Z1MFV20
SPAKXC16Z1MFV20
XC16Z1MFV25
20 MHz
25 MHz
–40 to 105
–40 to 125
16.78 MHz
20 MHz
25 MHz
16.78 MHz
20 MHz
25 MHz
SPAKXC16Z1MFV25
XC16Z1CFM16
144-PIN
MOLDED
CARRIER
RING
–40 to 85
–40 to 105
–40 to 125
16.78 MHz
20 MHz
25 MHz
16.78 MHz
20 MHz
25 MHz
16.78 MHz
20 MHz
25 MHz
XC16Z1CFM20
XC16Z1CFM25
XC16Z1VFM16
XC16Z1VFM20
XC16Z1VFM25
XC16Z1MFM16
XC16Z1MFM20
XC16Z1MFM25
MOTOROLA
2
MC68HC16Z1
MC68HC16Z1TS/D
TABLE OF CONTENTS
Section
Page
1
Introduction
1
1.1
1.2
1.3
1.4
1.5
1.6
Features ......................................................................................................................................4
Pin Description ............................................................................................................................8
Signal Description .....................................................................................................................10
Internal Register Address Map ..................................................................................................13
Pseudolinear Memory Maps ......................................................................................................14
Intermodule Bus ........................................................................................................................15
2
CPU16
16
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Overview ...................................................................................................................................16
M68HC11 Compatibility .............................................................................................................16
Programmer's Model .................................................................................................................17
Data Types ................................................................................................................................19
Addressing Modes .....................................................................................................................19
Instruction Set ...........................................................................................................................20
Exceptions .................................................................................................................................39
3
System Integration Module
42
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
System Configuration and Protection ........................................................................................45
System Configuration ................................................................................................................45
System Protection .....................................................................................................................47
System Clock ............................................................................................................................49
External Bus Interface ...............................................................................................................53
Resets .......................................................................................................................................64
Interrupts ...................................................................................................................................67
Factory Test Block .....................................................................................................................69
4
Analog-to-Digital Converter Module
71
4.1
4.2
4.3
4.4
Analog Subsystem ....................................................................................................................71
Digital Control Subsystem .........................................................................................................71
Bus Interface Subsystem ..........................................................................................................71
ADC Registers ...........................................................................................................................73
5
Queued Serial Module
QSM Registers ..........................................................................................................................81
QSPI Submodule .......................................................................................................................85
SCI Submodule .........................................................................................................................92
80
5.1
5.2
5.3
6
Standby RAM Module
SRAM Register Block ................................................................................................................99
SRAM Registers ........................................................................................................................99
SRAM Operation .....................................................................................................................100
99
6.1
6.2
6.3
7
General-Purpose Timer Module
Capture/Compare Unit ............................................................................................................103
Pulse-Width Modulator ............................................................................................................105
GPT Registers .........................................................................................................................106
102
7.1
7.2
7.3
8
9
Electrical Characteristics
Summary of Changes
114
140
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
3
1.1 Features
• CPU16
— 16-Bit Architecture
— Full Set of 16-Bit Instructions
— Three 16-Bit Index Registers
— Two 16-Bit Accumulators
— Control-Oriented Digital Signal Processing Capability
— 1 Megabyte of Program Memory and 1 Megabyte of Data Memory
— High-Level Language Support
— Fast Interrupt Response Time
— Background Debugging Mode
— Fully Static Operation
• System Integration Module
— External Bus Support
— Programmable Chip-Select Outputs
— System Protection Logic
— Watchdog Timer, Clock Monitor, and Bus Monitor
— Two 8-Bit Dual Function Ports
— One 7-Bit Dual Function Port
— Phase-Locked Loop (PLL) Clock System
• 8/10-Bit Analog-to-Digital Converter
— Eight Channels, Eight Result Registers
— Eight Automated Modes
— Three Result Alignment Modes
— One 8-Bit Digital Input Port
• Queued Serial Module
— Enhanced Serial Communication Interface
— Queued Serial Peripheral Interface
— One 8-Bit Dual Function Port
• General-Purpose Timer
— Two 16-Bit Free-Running Counters with Prescaler
— Three Input Capture Channels
— Four Output Compare Channels
— One Input Capture/Output Compare Channel
— One Pulse Accumulator/Event Counter Input
— Two Pulse Width Modulation Outputs
— One 8-Bit Dual Function Port
— Two Optional Discrete Inputs
— Optional External Clock Input
• Standby RAM
— 1024-Byte Static RAM
— External Standby Voltage Supply Input
MOTOROLA
MC68HC16Z1
4
MC68HC16Z1TS/D
CHIP
PQS7/TXD
PQS6/PCS3
PQS5/PCS2
PQS4/PCS1
PQS3/SS/PCS0
PQS2/SCK
TXD
CSBOOT
BR/CS0
BG/CS1
BGACK/CS2
ADDR23/CS10
PC6/ADDR22/CS9
PC5/ADDR21/CS8
PC4/ADDR20/CS7
PC3/ADDR19/CS6
PC2/FC2/CS5
PC1/FC1/CS4
PC0/FC0/CS3
SELECTS
PCS3
PCS2
PCS1
PCS0
SCK
MOSI
MISO
CS[10:0]
PQS1/MOSI
PQS0/MISO
BR
BG
BGACK
FC2
FC1
FC0
GPT
SIM
QSM
PAI
PAI
PGP7/IC4/OC5/OC1
PGP6/OC4/OC1
PGP5/OC3/OC1
PGP4/OC2/OC1
PGP3/OC1
IC4/OC5/OC1
OC4/OC1
OC3/OC1
OC2/OC1
OC1
ADDR[23:0]
ADDR[18:0]
PGP2/IC3
IC3
PGP1/IC2
PGP0/IC1
IC2
IC1
EBI
SIZ1
SIZ0
AS
PE7/SIZ1
PE6/SIZ0
PE5/AS
PWMA
PWMB
PCLK
PWMA
PWMB
PCLK
DS
PE3
PE4/DS
AVEC
DSACK1
DSACK0
PE2/AVEC
PE1/DSACK1
PE0/DSACK0
V
V
DD
SS
IMB
PADA7/AN7
PADA6/AN6
PADA5/AN5
PADA4/AN4
PADA3/AN3
PADA2/AN2
PADA1/AN1
PADA0/AN0
DATA[15:0]
DATA[15:0]
R/W
RESET
HALT
BERR
ADC
SRAM
CPU16
IRQ[7:1]
PF7/IRQ7
PF6/IRQ6
PF5/IRQ5
PF4/IRQ4
PF3/IRQ3
PF2/IRQ2
PF1/IRQ1
PF0/MODCLK
CLKOUT
XTAL
V
V
RH
RL
V
V
DDA
SSA
MODCLK
V
V
STBY
STBY
CLOCK
EXTAL
XFC
V
BKPT/DSCLK
IPIPE1/DSI
DDSYN
TSC
TSTME
QUOT
TSTME/TSC
IPIPE0/DSO
TEST
FREEZE/QUOT
Z1 BLOCK
Figure 1 MC68HC16Z1 Block Diagram
MC68HC16Z1
MOTOROLA
MC68HC16Z1TS/D
5
18
19
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
BR/CS0
PC2/FC2/CS5
PC1/FC1/CS4
PQS7/TXD
ADDR1
ADDR2
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
V
V
V
DDE
SSE
DDE
V
SSE
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
PC0/FC0/CS3
CSBOOT
DATA0
DATA1
DATA2
DATA3
V
V
SSI
SSI
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
ADDR16
ADDR17
ADDR18
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
MC68HC16Z1
V
DDE
V
SSE
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
ADDR0
PE0/DSACK0
PE1/DSACK1
PE2/AVEC
PE4/DS
V
V
DDE
SSE
V
V
DDA
SSA
90
89
88
87
86
85
84
PADA0/AN0
PADA1/AN1
PADA2/AN2
PADA3/AN3
PADA4/AN4
PADA5/AN5
PE5/AS
V
V
RH
DDE
Z1 132-PIN QFP
Figure 2 MC68HC16Z1 132-Pin Package Pin Assignments
MOTOROLA
MC68HC16Z1
6
MC68HC16Z1TS/D
109
108
V
1
2
3
4
5
6
7
8
NC
BG/CS1
BGACK/CS2
SSE
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
PE6/SIZ0
PE7/SIZ1
R/W
PC3/ADDR19/CS6
PC4/ADDR20/CS7
PC5/ADDR21/CS8
PC6/ADDR22/CS9
ADDR23/CS10
PF0/MODCLK
PF1/IRQ1
PF2/IRQ2
PF3/IRQ3
PF4/IRQ4
PF5/IRQ5
PF6/IRQ6
PF7/IRQ7
BERR
V
V
9
DDE
SSE
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PCLK
PWMB
PWMA
PAI
HALT
RESET
PGP7/IC4/OC5/OC1
PGP6/OC4/OC1
PGP5/OC3/OC1
NC
IPIPE1/DSI
IPIPE0/DSO
BKPT/DSCLK
NC
TSTME/TSC
FREEZE/QUOT
CLKOUT
MC68HC16Z1
V
V
DDI
SSI
PGP4/OC2
PGP3/OC1
PGP2/IC3
PGP1/IC2
PGP0/IC1
V
SSE
V
XFC
NC
DDE
V
V
DDE
SSE
V
DDI
V
PQS0/MISO
PQS1/MOSI
PQS2/SCK
PQS3/SS/PCS0
PQS4/PCS1
PQS5/PCS2
PQS6/PCS3
RXD
SSI
EXTAL
V
XTAL
DDSYN
V
STBY
PADA7/AN7
PADA6/AN6
V
RLP
NC
NC
Z1 144-PIN QFP
Figure 3 MC68HC16Z1 144-Pin Package Pin Assignments
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
7
1.2 Pin Description
The following table shows MC68HC16Z1 pins and their characteristics. All inputs detect CMOS logic
levels. All inputs can be put in a high-impedance state, but the method of doing this differs depending
upon pin function. Refer to the table, MC68HC16Z1 Driver Types, for a description of output drivers. An
entry in the discrete I/O column of the MC68HC16Z1 Pin Characteristics table indicates that a pin has
an alternate I/O function. The port designation is given when it applies. Refer to the MC68HC16Z1 Block
Diagram for information about port organization.
Table 2 MC68HC16Z1 Pin Characteristics
Pin
Mnemonic
Output
Driver
Input
Synchronized
Input
Hysteresis
Discrete
I/O
Port
Designation
ADDR23/CS10/ECLK
ADDR[22:19]/CS[9:6]
ADDR[18:0]
A
A
Y
Y
Y
Y
N
N
N
N
O
O
—
I
—
C[6:3]
—
A
1
—
ADA[7:0]
AN[7:0]
AS
AVEC
B
B
Y
N
I/O
I/O
—
—
—
—
O
E5
Y
N
E2
BERR
B
Y
N
—
BG/CS1
B
—
Y
—
N
—
BGACK/CS2
BKPT/DSCKL
BR/CS0
B
—
—
B
Y
Y
—
Separate
—
Y
N
CLKOUT
CSBOOT
A
—
—
Y
—
—
N
—
—
—
B
—
1
AW
—
DATA[15:0]
DS
B
B
B
A
A
—
Y
Y
N
I/O
I/O
I/O
—
E4
E1
DSACK1
N
N
DSACK0
Y
E0
DSI/IPIPE1
DSO/IPIPE0
Y
Y
Separate
Separate
—
—
—
—
—
2
Special
—
EXTAL
FC[2:0]/CS[5:3]
FREEZE/QUOT
HALT
A
A
Y
—
Y
Y
Y
Y
Y
Y
N
—
N
Y
Y
Y
Y
N
O
C[2:0]
—
—
Bo
A
—
—
IC4/OC5
IC[3:1]
I/O
I/O
I/O
I/O
I/O
GP4
GP[7:5]
F[7:1]
QS0
F0
A
IRQ[7:1]
B
MISO
Bo
B
1
MODCLK
MOSI
Bo
A
Y
Y
Y
Y
Y
Y
I/O
I/O
I
QS1
OC[4:1]
GP[3:0]
Separate
3
—
PAI
3
—
Y
Y
I
Separate
PCLK
PCS0/SS
PCS[3:1]
Bo
Bo
A
Y
Y
I/O
I/O
O
QS3
Y
Y
QS[6:4]
Separate
4
—
—
PWMA, PWMB
MOTOROLA
MC68HC16Z1
8
MC68HC16Z1TS/D
Table 2 MC68HC16Z1 Pin Characteristics (Continued)
Pin
Mnemonic
Output
Driver
Input
Synchronized
Input
Hysteresis
Discrete
I/O
Port
Designation
R/W
RESET
RXD
A
Bo
—
Bo
B
Y
Y
N
Y
Y
Y
Y
—
N
Y
N
Y
N
Y
Y
—
—
—
—
—
—
—
SCK
I/O
I/O
—
QS2
E[7:6]
—
SIZ[1:0]
TSTME/TSC
TXD
—
Bo
—
I/O
—
QS7
—
5
V
RH
5
—
—
—
—
—
V
RL
2
—
—
—
—
—
—
Special
Special
—
—
XFC
2
XTAL
NOTES
1. DATA[15:0] are synchronized during reset only. MODCLK, MCCI and ADC pins are
synchronized only when used as input port pins.
2. EXTAL, XFC, and XTAL are clock reference connections.
3. PAI and PCLK can be used for discrete input, but are not part of an I/O port.
4. PWMA and PWMB can be used for discrete output, but are not part of an I/O port.
5. V and V are ADC reference voltage inputs.
RH
RL
Table 3 MC68HC16Z1 Power Connections
V
Standby RAM Power/Clock Synthesizer Power
Clock Synthesizer Power
STBY
V
DDSYN
V
V
/V
A/D Converter Power
DDA SSA
/V
External Periphery Power (Source and Drain)
Internal Module Power (Source and Drain)
SSE DDE
V
/V
SSI DDI
Table 4 MC68HC16Z1 Driver Types
Type
A
I/O
O
Description
Output-only signals that are always driven; no external pull-up required
Type A output with weak P-channel pull-up during reset
Aw
B
O
O
Three-state output that includes circuitry to pull up output before high impedance is es-
tablished, to ensure rapid rise time. An external holding resistor is required to maintain
logic level while the pin is in the high-impedance state.
Bo
O
Type B output that can be operated in an open-drain mode
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
9
1.3 Signal Description
Use the following tables as a quick reference to MC68HC16Z1 signal type and function.
Table 5 MC68HC16Z1 Signal Characteristics
Signal
Name
MCU
Module
Signal
Type
Active
State
ADDR[23:0]
AN[7:0]
AS
SIM
ADC
SIM
Bus
Input
—
—
Output
Input
0
AVEC
SIM
0
BERR
SIM
Input
0
BG
SIM
Output
Input
0
BGACK
BKPT
SIM
0
CPU16
SIM
Input
0
BR
Input
0
CLKOUT
CS[10:0]
CSBOOT
DATA[15:0]
DS
SIM
Output
Output
Output
Bus
—
SIM
0
SIM
0
SIM
—
SIM
Output
Input
0
DSACK[1:0]
DSCLK
DSI
SIM
0
CPU16
CPU16
CPU16
SIM
Input
Serial Clock
Input
(Serial Data)
DSO
Output
Input
(Serial Data)
EXTAL
FC[2:0]
FREEZE
HALT
—
—
SIM
Output
Output
Input/Output
Input
SIM
1
SIM
0
IC[4:1]
GPT
CPU16
CPU16
SIM
—
IPIPE0
IPIPE1
IRQ[7:1]
MISO
Output
Output
Input
—
—
0
QSM
SIM
Input/Output
Input
—
MODCLK
MOSI
—
QSM
GPT
ADC
GPT
SIM
Input/Output
Output
Input
—
OC[5:1]
PADA[7:0]
PAI
—
(Port)
—
Input
PC[6:0]
PE[7:0]
PF[7:0]
PGP[7:0]
PQS[7:0]
PCLK
Output
Input/Output
Input/Output
Input/Output
Input/Output
Input
(Port)
(Port)
(Port)
(Port)
(Port)
—
SIM
SIM
GPT
QSM
GPT
QSM
GPT
SIM
PCS[3:0]
PWMA, PWMB
QUOT
Input/Output
Output
Output
—
—
—
MOTOROLA
10
MC68HC16Z1
MC68HC16Z1TS/D
Table 5 MC68HC16Z1 Signal Characteristics (Continued)
Signal
Name
MCU
Module
Signal
Type
Active
State
R/W
RESET
RXD
SIM
SIM
Output
Input/Output
Input
1/0
0
QSM
QSM
SIM
—
—
—
0
SCK
Input/Output
Output
Input
SIZ[1:0]
SS
QSM
SIM
TSC
Input
—
0
TSTME
TXD
SIM
Input
QSM
ADC
Output
Input
—
—
V
RH
V
ADC
Input
—
RL
XFC
SIM
SIM
Input
—
—
XTAL
Output
Table 6 MC68HC16Z1 Signal Function
Signal Name
Address Strobe
Mnemonic
AS
Function
Indicates that a valid address is on the address bus
Requests an automatic vector during interrupt acknowledge
Indicates that a bus error has occurred
Autovector
AVEC
BERR
BG
Bus Error
Bus Grant
Indicates that the MCU has relinquished the bus
Indicates that an external device has assumed bus mastership
Signals a hardware breakpoint to the CPU
Bus Grant Acknowledge
Breakpoint
BGACK
BKPT
Bus Request
Chip Selects
Boot Chip Select
Address Bus
Address Bus
ADC Analog Input
System Clockout
Data Bus
BR
Indicates that an external device requires bus mastership
Select external devices at programmed addresses
Chip select for external boot start-up ROM
CS[10:0]
CSBOOT
ADDR[19:0] 20-bit address bus used by CPU16
ADDR[23:20] 4 MSB on IMB, test only, outputs follow ADDR19
AN[7:0]
Inputs to ADC MUX
System clock output
CLKOUT
DATA[15:0] 16-bit data bus
Data Strobe
DS
During a read cycle, indicates that an external device should place
valid data on the data bus. During a write cycle, indicates that valid
data is on the data bus
Halt
HALT
Suspend external bus activity
Interrupt Request Level
Data and Size Acknowledge
Peripheral Chip Select
Reset
IRQ[7:1]
Provides an interrupt priority level to the CPU
DSACK[1:0] Provide asynchronous data transfers and dynamic bus sizing
PCS[3:0]
RESET
TSTME
QSPI peripheral chip selects
System reset
Test Mode Enable
Hardware enable for SIM test mode
Serial I/O and clock for background debug mode
Development Serial In, Out,
Clock
DSI, DSO,
DSCLK
Crystal Oscillator
EXTAL, XTAL Connections for clock synthesizer circuit reference;
a crystal or an external oscillator can be used
Function Codes
FC[2:0]
Identify processor state and current address space
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
11
Table 6 MC68HC16Z1 Signal Function (Continued)
Signal Name
Mnemonic
FREEZE
PIPE[1:0]
MISO
Function
Freeze
Indicates that the CPU has entered background mode
Indicate instruction pipeline activity
Instruction Pipeline
Master In Slave Out
Serial input to QSPI in master mode;
serial output from QSPI in slave mode
Clock Mode Select
Master Out Slave In
MODCLK
MOSI
Selects the source and type of system clock
Serial output from QSPI in master mode;
serial input to QSPI in slave mode
Port ADA
PADA[7:0]
PC[6:0]
PE[7:0]
PF[7:0]
PGP[7:0]
PQS[7:0]
QUOT
R/W
ADC digital input port signals
SIM digital output port signals
SIM digital I/O port signals
Port C
Port E
Port F
SIM digital I/O port signals
Port GP
GPT digital I/O port signals
Port QS
QSM digital I/O port signals
Quotient Out
Read/Write
SCI Receive Data
QSPI Serial Clock
Provides the quotient bit of the polynomial divider
Indicates the direction of data transfer on the bus
Serial input to the SCI
RXD
SCK
Clock output from QSPI in master mode;
clock input to QSPI in slave mode
Size
SIZ[1:0]
SS
Indicates the number of bytes to be transferred during a bus cycle
Slave Select
Causes serial transmission when QSPI is in slave mode;
causes mode fault in master mode
Three-State Control
SCI Transmit Data
TSC
TXD
Places all output drivers in a high-impedance state
Serial output from the SCI
ADC Reference Voltage
V
Provide precise reference for A/D conversion
rh,Vrl
External Filter Capacitor
Crystal Oscillator
XFC
Connection for external phase-locked loop filter capacitor
EXTAL, XTAL Connections for clock synthesizer circuit reference;
a crystal or an external oscillator can be used
Function Codes
Freeze
FC[2:0]
FREEZE
PIPE[1:0]
MISO
Identify processor state and current address space
Indicates that the CPU has entered background mode
Indicate instruction pipeline activity
Instruction Pipeline
Master In Slave Out
Serial input to QSPI in master mode;
serial output from QSPI in slave mode
Clock Mode Select
Master Out Slave In
MODCLK
MOSI
Selects the source and type of system clock
Serial output from QSPI in master mode;
serial input to QSPI in slave mode
Port ADA
PADA[7:0]
PC[6:0]
PE[7:0]
PF[7:0]
PGP[7:0]
PQS[7:0]
QUOT
R/W
ADC digital input port signals
SIM digital output port signals
SIM digital I/O port signals
Port C
Port E
Port F
SIM digital I/O port signals
Port GP
GPT digital I/O port signals
Port QS
QSM digital I/O port signals
Quotient Out
Read/Write
SCI Receive Data
QSPI Serial Clock
Provides the quotient bit of the polynomial divider
Indicates the direction of data transfer on the bus
Serial input to the SCI
RXD
SCK
Clock output from QSPI in master mode;
clock input to QSPI in slave mode
Size
SIZ[1:0]
Indicates the number of bytes to be transferred during a bus cycle
MOTOROLA
12
MC68HC16Z1
MC68HC16Z1TS/D
Table 6 MC68HC16Z1 Signal Function (Continued)
Signal Name
Slave Select
Mnemonic
Function
SS
Causes serial transmission when QSPI is in slave mode;
causes mode fault in master mode
Three-State Control
SCI Transmit Data
TSC
TXD
Places all output drivers in a high-impedance state
Serial output from the SCI
ADC Reference Voltage
V
Provide precise reference for A/D conversion
rh,Vrl
External Filter Capacitor
XFC
Connection for external phase-locked loop filter capacitor
1.4 Internal Register Address Map
In the following figure, IMB ADDR[23:20] are represented by the letter Y. The value represented by Y
determines the base address of MCU module control registers. In the MC68HC16Z1, Y is equal to
M111, where M is the logic state of the module mapping (MM) bit in the system integration module con-
figuration register (SIMCR). Since the CPU16 uses only ADDR[19:0], and ADDR[23:20] follow the logic
state of ADDR19 when CPU driven, the CPU cannot access IMB addresses from $080000 to $F7FFFF.
In order for the MCU to function correctly, MM must be set (Y must equal $F). If M is cleared, internal
registers are mapped to base address $700000, and are inaccessible until a reset occurs. The SRAM
array is positioned by a base address register in the SRAM CTRL block. Unimplemented blocks are
mapped externally.
$YFF700
ADC
64 BYTES
$YFF73F
$YFF900
GPT
64 BYTES
$YFF93F
1K SRAM ARRAY
(MAPPED TO 1K BOUNDARY)
$YFFA00
SIM
128 BYTES
$YFFA7F
$YFFB00
$YFFB07
$YFFC00
SRAM CTRL
8 BYTES
QSM
512 BYTES
$YFFDFF
Z1 ADDRESS MAP
Figure 4 Internal Register Addresses
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
13
1.5 Pseudolinear Memory Maps
The following figures both show the complete CPU16 pseudolinear address space. Address space can
be split into physically distinct program and data spaces by decoding the MCU function code outputs.
The first figure shows the memory map of a system that has combined program and data spaces. The
second figure shows the memory map when MCU function code outputs are decoded. Reset and ex-
ception vectors are mapped into bank 0 and cannot be relocated. The CPU16 program counter, stack
pointer, and Z index register can be initialized to any address in pseudolinear memory, but exception
vectors are limited to 16-bit addresses — to access locations outside of bank 0 during exception handler
routines (including interrupt exceptions), a jump table must be used.
VECTOR VECTOR
ADDRESS NUMBER
TYPE OF
EXCEPTION
0000
0002
0004
0006
0008
000A
000C
000E
0010
0012–001C
001E
0020
0
RESET — INITIAL ZK, SK, AND PK $00000
RESET — INITIAL PC
RESET — INITIAL SP
RESET — INITIAL IZ (DIRECT PAGE)
BKPT (BREAKPOINT)
BERR (BUS ERROR)
SWI (SOFTWARE INTERRUPT)
ILLEGAL INSTRUCTION
DIVISION BY ZERO
UNASSIGNED, RESERVED
$00000 BANK 0
RESET AND
EXCEPTION VECTORS
4
5
6
7
8
$10000 BANK 1
$20000 BANK 2
$30000 BANK 3
$40000 BANK 4
$50000 BANK 5
$60000 BANK 6
$70000 BANK 7
9–E
F
UNINITIALIZED INTERRUPT
UNASSIGNED, RESERVED
10
11
12
13
14
15
16
17
18
0022
0024
0026
0028
LEVEL 1 INTERRUPT AUTOVECTOR
LEVEL 2 INTERRUPT AUTOVECTOR
LEVEL 3 INTERRUPT AUTOVECTOR
LEVEL 4 INTERRUPT AUTOVECTOR
LEVEL 5 INTERRUPT AUTOVECTOR
LEVEL 6 INTERRUPT AUTOVECTOR
LEVEL 7 INTERRUPT AUTOVECTOR
SPURIOUS INTERRUPT
002A
002C
002E
0030
0032–006E 19–37
0070–01FE 38–FF
UNASSIGNED, RESERVED
USER-DEFINED INTERRUPTS
$001FE
$FF700
ADC
1 MBYTE
PROGRAM
AND DATA
SPACE
$FF73F
$FF900
$80000
$90000
BANK 8
BANK 9
GPT
SIM
$FF93F
$FFA00
$A0000 BANK 10
$B0000 BANK 11
$C0000 BANK 12
$D0000 BANK 13
$E0000 BANK 14
$F0000 BANK 15
$FFA7F
$FFB00
$FFB07
SRAM
(CONTROL)
$FFC00
QSM
INTERNAL REGISTERS
$FFDFF
$FFFFF
Z1 MEM MAP (COMBINED)
Figure 5 Pseudolinear Addressing With Combined Program and Data Spaces
MOTOROLA
14
MC68HC16Z1
MC68HC16Z1TS/D
VECTOR VECTOR
ADDRESS NUMBER
TYPE OF
EXCEPTION
0000
0002
0004
0006
0
1
2
3
RESET — INITIAL ZK, SK, AND PK
RESET — INITIAL PC
RESET — INITIAL SP
RESET — INITIAL IZ (DIRECT PAGE)
$00000
$00006
$00000 BANK 0
$00008
RESET VECTORS
$10000 BANK 1
VECTOR VECTOR
ADDRESS NUMBER
TYPE OF
EXCEPTION
BANK 0
$00000
$00008
0008
000A
4
5
BKPT (BREAKPOINT)
BERR (BUS ERROR)
$00008
$20000 BANK 2
$30000 BANK 3
$40000 BANK 4
$50000 BANK 5
$60000 BANK 6
$70000 BANK 7
EXCEPTION VECTORS
000C
000E
0010
0012–001C
001E
0020
0022
0024
0026
0028
002A
002C
002E
0030
0032–006E 19–37
0070–01FE 38–FF
6
7
8
9–E
F
10
11
12
13
14
15
16
17
18
SWI (SOFTWARE INTERRUPT)
ILLEGAL INSTRUCTION
DIVISION BY ZERO
UNASSIGNED, RESERVED
UNINITIALIZED INTERRUPT
UNASSIGNED, RESERVED
LEVEL 1 INTERRUPT AUTOVECTOR
LEVEL 2 INTERRUPT AUTOVECTOR
LEVEL 3 INTERRUPT AUTOVECTOR
LEVEL 4 INTERRUPT AUTOVECTOR
LEVEL 5 INTERRUPT AUTOVECTOR
LEVEL 6 INTERRUPT AUTOVECTOR
LEVEL 7 INTERRUPT AUTOVECTOR
SPURIOUS INTERRUPT
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
$10000
$20000
$30000
$40000
$50000
$60000
$70000
$80000
$90000
$A0000
$B0000
$C0000
$D0000
$E0000
UNASSIGNED, RESERVED
USER-DEFINED INTERRUPTS
$001FE
1 MBYTE
PROGRAM
SPACE
$80000
$90000
BANK 8
BANK 9
$FF700
BANK 7
DATA
ADC
$FF73F
$FF900
SPACE
BANK 8
$A0000 BANK 10
$B0000 BANK 11
$C0000 BANK 12
$D0000 BANK 13
$E0000 BANK 14
BANK 9
GPT
SIM
$FF93F
$FFA00
BANK 10
BANK 11
BANK 12
BANK 13
BANK 14
$FFA7F
$FFB00
$FFB07
SRAM
(CONTROL)
$F0000 BANK 15
$FFFFF
$FFC00
$FFDFF
QSM
BANK 15
INTERNAL REGISTERS
$F0000
$FFFFF
Z1 MEM MAP (SEPARATED)
Figure 6 Pseudolinear Addressing With Separated Program and Data Spaces
1.6 Intermodule Bus
The intermodule bus (IMB) is a standardized bus developed to facilitate both design and operation of
modular microcontrollers. It contains circuitry to support exception processing, address space partition-
ing, multiple interrupt levels, and vectored interrupts. The standardized modules in the MC68HC16Z1
communicate with one another and with external components via the IMB. Although the full IMB sup-
ports 24 address and 16 data lines, the MC68HC16Z1 uses only 16 data lines and 20 address lines.
Because the CPU16 uses only 20 address lines, ADDR[23:20] are tied to ADDR19 when processor
driven. ADDR[23:20] are brought out to pins for test purposes.
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
15
2 CPU16
The CPU16 is a true 16-bit, high-speed device. It was designed to give M68HC11 users a path to higher
performance while maintaining maximum compatibility with existing systems.
2.1 Overview
Ease of programming is an important consideration when using a microcontroller. The CPU16 instruc-
tion set is optimized for high performance. There are two 16-bit general-purpose accumulators and
three 16-bit index registers. The CPU16 supports 8-bit (byte), 16-bit (word), and 32-bit (long-word) load
and store operations, as well as 16- and 32-bit signed fractional operations. Code development is sim-
plified by the background debugging mode.
CPU16 memory space includes a 1 Mbyte data space and a 1 Mbyte program space. Twenty-bit ad-
dressing and transparent bank switching are used to implement extended memory. In addition, most
instructions automatically handle bank boundaries.
The CPU16 includes instructions and hardware to implement control-oriented digital signal processing
functions with a minimum of interfacing. A multiply and accumulate unit provides the capability to mul-
tiply signed 16-bit fractional numbers and store the resulting 32-bit fixed point product in a 36-bit accu-
mulator. Modulo addressing supports finite impulse response filters.
Use of high-level languages is increasing as controller applications become more complex and control
programs become larger. These languages make rapid development of portable software possible. The
CPU16 instruction set supports high-level languages.
2.2 M68HC11 Compatibility
CPU16 architecture is a superset of M68HC11 CPU architecture. All M68HC11 CPU resources are
available in the CPU16. M68HC11 CPU instructions are either directly implemented in the CPU16, or
have been replaced by instructions with an equivalent form. The instruction sets are source code com-
patible, but some instructions are executed differently in the CPU16. These instructions are mainly re-
lated to interrupt and exception processing — M68HC11 CPU code that processes interrupts, handles
stack frames, or manipulates the condition code register must be rewritten.
CPU16 execution times and number of cycles for all instructions are different from those of the
M68HC11 CPU. As a result, cycle-related delays and timed control routines may be affected.
The CPU16 also has several new or enhanced addressing modes. M68HC11 CPU direct mode ad-
dressing has been replaced by a special form of indexed addressing that uses the new IZ register and
a reset vector to provide greater flexibility.
MOTOROLA
16
MC68HC16Z1
MC68HC16Z1TS/D
2.3 Programmer's Model
20
16 15
8 7
D
0
A
B
ACCUMULATORS A AND B
ACCUMULATOR D (A : B)
E
ACCUMULATOR E
INDEX REGISTER X
INDEX REGISTER Y
INDEX REGISTER Z
STACK POINTER
XK
YK
ZK
SK
PK
IX
IY
IZ
SP
PC
PROGRAM COUNTER
CCR
XK
PK
CONDITION CODE REGISTER
PC EXTENSION REGISTER
EK
YK
ZK
SK
ADDRESS EXTENSION REGISTER
STACK EXTENSION REGISTER
H
I
MAC MULTIPLIER REGISTER
MAC MULTIPLICAND REGISTER
35
16
AM (MSB)
AM (LSB)
MAC ACCUMULATORMSB [35:16]
MAC ACCUMULATOR LSB [15:0]
XMSK
YMSK
MAC XY MASK REGISTER
Accumulator A — 8-bit general-purpose register
Accumulator B — 8-bit general-purpose register
Accumulator D — 16-bit register formed by concatenating accumulators A and B
Accumulator E — 16-bit general-purpose register
Index Register X — 16-bit indexing register, addressing extended by XK field in K register
Index Register Y — 16-bit indexing register, addressing extended by YK field in K register
Index Register Z — 16-bit indexing register, addressing extended by ZK field in K register
Stack Pointer — 16-bit dedicated register, addressing extended by the SK register
Program Counter — 16-bit dedicated register, addressing extended by PK field in CCR
Condition Code Register — 16-bit register containing condition flags, interrupt priority mask,
and the program counter address extension field
K Register — 16-bit register made up of four 4-bit address extension fields
SK Register — 4-bit register containing the stack pointer address extension field
H Register — 16-bit multiply and accumulate input (multiplier) register
I Register — 16-bit multiply and accumulate input (multiplicand) register
MAC Accumulator — 36-bit multiply and accumulate result register
XMSK, YMSK — Determine which bits change when an offset is added
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
17
2.3.1 Condition Code Register
15
S
14
13
H
12
11
N
10
Z
9
8
7
6
5
4
3
2
1
0
MV
EV
V
C
INT
SM
PK
The condition code register can be considered as two functional blocks. The MSB, which corresponds
to the CCR in the M68HC11, contains the low-power stop control bit and processor status flags. The
LSB contains the interrupt priority field, the DSP saturation mode control bit, and the program counter
address extension field.
S — STOP Enable
0 = Stop clock when LPSTOP instruction is executed
1 = Perform NOP when LPSTOP instruction is executed
MV — Accumulator M overflow flag
Set when overflow into the accumulator M sign bit (AM35) has occurred
H — Half Carry Flag
Set when a carry from bit 3 in accumulators A or B occurs during BCD addition
EV — Extension Bit Overflow Flag
Set when an overflow into bit 31 of accumulator M has occurred
N — Negative Flag
Set when the MSB of a result register is set
Z — Zero Flag
Set when all bits of a result register are zero
V — Overflow Flag
Set when two's complement overflow occurs as the result of an operation
C — Carry Flag
Set when a carry or borrow occurs during arithmetic operation. Also used during shift and rotate oper-
ations to facilitate multiple word operations.
INT[2:0] — Interrupt Priority Mask
The value of this field ($0 to $7) specifies the CPU16 interrupt priority level.
SM — Saturate Mode Bit
When SM is set, if either EV or MV is set, data read from accumulator M using TMRT or TMET is given
maximum positive or negative value, depending on the state of the AM sign bit before overflow.
PK[3:0] — Program Counter Address Extension Field
This field is concatenated with the program counter to form a 20-bit pseudolinear address.
MOTOROLA
18
MC68HC16Z1
MC68HC16Z1TS/D
2.4 Data Types
The CPU16 supports the following data types:
• Bit data
• 8-bit (byte) and 16-bit (word) integers
• 32-bit long integers
• 16-bit and 32-bit signed fractions (MAC operations only)
• 20-bit effective address consisting of 16-bit page address plus 4-bit extension
A byte is 8 bits wide and can be accessed at any byte location. A word is composed of two consecutive
bytes, and is addressed at the lower byte. Instruction fetches are always accessed on word boundaries.
Word operands are normally accessed on word boundaries as well, but can be accessed on odd byte
boundaries, with a substantial performance penalty.
To be compatible with the M68HC11, misaligned word transfers and misaligned stack accesses are al-
lowed. Transferring a misaligned word requires two successive byte operations.
2.5 Addressing Modes
The CPU16 provides 10 types of addressing. Each type encompasses one or more addressing modes.
Six CPU16 addressing types are identical to M68HC11 addressing types.
All modes generate ADDR[15:0]. This address is combined with ADDR[19:16] from an extension field
to form a 20-bit effective address. Extension fields are part of a bank switching scheme that provides
the CPU16 with a 1 Mbyte address space. Bank switching is transparent to most instructions — AD-
DR[19:16] of the effective address change when an access crosses a bank boundary. However, it is
important to note that the value of the associated extension field is dependent on the type of instruction,
and usually does not change as a result of effective address calculation.
In the immediate modes, the instruction argument is contained in bytes or words immediately following
the instruction. The effective address is the address of the byte following the instruction. The AIS, AIX/
Y/Z, ADDD and ADDE instructions have an extended 8-bit mode where the immediate value is an 8-bit
signed number that is sign-extended to 16 bits, and then added to the appropriate register. Use of the
extended 8-bit mode decreases execution time.
Extended mode instructions contain ADDR[15:0] in the word following the opcode. The effective ad-
dress is formed by concatenating EK and the 16-bit extension.
In the indexed modes, registers IX, IY, and IZ, together with their associated extension fields, are used
to calculate the effective address. Signed 16-bit mode and signed 20-bit mode are extensions to the
M68HC11 indexed addressing mode.
For 8-bit indexed mode, an 8-bit unsigned offset contained in the instruction is added to the value
contained in the index register and its associated extension field.
For 16-bit mode, a 16-bit signed offset contained in the instruction is added to the value contained
in the index register and its associated extension field.
For 20-bit mode, a 20-bit signed offset is added to the value contained in the index register. This
mode is used for JMP and JSR instructions.
Inherent mode instructions use information available to the processor to determine the effective ad-
dress. Operands (if any) are system resources and are thus not fetched from memory.
Accumulator offset mode adds the contents of 16-bit accumulator E to one of the index registers and its
associated extension field to form the effective address. This mode allows use of index registers and
an accumulator within loops without corrupting accumulator D.
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
19
Relative modes are used for branch and long branch instructions. A byte or word signed two's comple-
ment offset is added to the program counter if the branch condition is satisfied. The new PC value, con-
catenated with the PK field, is the effective address.
Post-modified index mode is used with the MOVB and MOVW instructions. A signed 8-bit offset is add-
ed to index register X after the effective address formed by XK and IX is used.
In M68HC11 systems, direct mode can be used to perform rapid accesses to RAM or I/O mapped into
page 0 ($0000 to $00FF), but the CPU16 uses the first 512 bytes of page 0 for exception vectors. To
compensate for the loss of direct mode, the ZK field and index register Z have been assigned reset ini-
tialization vectors. By resetting the ZK field to a chosen page, and using 8-bit unsigned index mode with
IZ, a programmer can access useful data structures anywhere in the address map.
2.6 Instruction Set
The CPU16 has an 8-bit instruction set. It uses a prebyte to support a multipage opcode map. This ar-
rangement makes it possible to fetch an 8-bit operand simultaneously with a Page 0 opcode. If a pro-
gram makes maximum use of 8-bit offset indexed addressing mode, it will have a significantly smaller
instruction space.
The instruction set is based on that of the M68HC11, but the opcode map has been rearranged to max-
imize performance with a 16-bit data bus. All M68HC11 instructions are supported by the CPU16, al-
though they may be executed differently. Most M68HC11 code runs on the CPU16 following
reassembly. However, take into account changed instruction times, the interrupt mask, and the new in-
terrupt stack frame.
The CPU16 has a full range of 16-bit arithmetic and logic instructions, including signed and unsigned
multiplication and division. New instructions have been added to support extended addressing and dig-
ital signal processing.
The following table is a summary of the CPU16 instruction set. Because it is only affected by a few in-
structions, the LSB of the condition code register is not shown in the table — instructions that affect the
interrupt mask and PK field are noted.
MOTOROLA
20
MC68HC16Z1
MC68HC16Z1TS/D
Table 7 Instruction Set Summary
Mnemonic
Operation
Description
Address
Instruction
Opcode Operand Cycles
Condition Codes
Mode
INH
INH
INH
INH
INH
INH
S
—
—
—
—
—
—
MV
—
—
—
—
∆
H
∆
EV
—
—
—
—
∆
N
∆
Z
∆
V
∆
C
∆
ABA
ABX
ABY
ABZ
Add B to A
Add B to X
(A ) + (B)
A
370B
374F
375F
376F
3722
3723
—
—
—
—
—
—
2
2
2
2
2
4
(XK : IX) + (000 : B) XK : IX
(YK : IY) + (000 : B) YK : IY
(ZK : IZ) + (000 : B) ZK : IZ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Add B to Y
Add B to Z
ACE
ACED
Add E to AM[31:15]
(AM[31:15]) + (E)
(E : D) + (AM)
AM
AM
Add concatenated
E and D to AM
∆
∆
ADCA
ADCB
ADCD
Add with Carry to A
(A) + (M) + C
A
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
43
53
63
73
1743
1753
1763
1773
2743
2753
2763
ff
ff
ff
6
6
6
2
6
6
6
6
6
6
6
—
—
—
—
—
—
∆
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
ii
gggg
gggg
gggg
hh ll
—
E, X
E, Y
E, Z
—
—
Add with Carry to B
(B) + (M) + C
B
IND8, X
IND8, Y
IND8, Z
IMM8
E, X
E, Y
C3
D3
E3
ff
ff
ff
ii
—
—
—
gggg
gggg
gggg
hh ll
6
6
6
2
6
6
6
6
6
6
6
∆
F3
27C3
27D3
27E3
17C3
17D3
17E3
17F3
E, Z
IND16, X
IND16, Y
IND16, Z
EXT
Add with Carry to D (D) + (M : M + 1) + C
D
IND8, X
IND8, Y
IND8, Z
E, X
E, Y
E, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
83
93
A3
ff
ff
ff
—
—
6
6
6
6
6
6
4
6
6
6
6
—
2783
2793
27A3
37B3
37C3
37D3
37E3
37F3
—
jj kk
gggg
gggg
gggg
hh ll
ADCE
ADDA
Add with Carry to E (E) + (M : M + 1) + C
E
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
3733
3743
3753
3763
3773
jj kk
gggg
gggg
gggg
hh ll
4
6
6
6
6
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
Add to A
(A) + (M)
A
IND8, X
IND8, Y
IND8, Z
IMM8
E, X
E, Y
41
51
61
71
2741
2751
2761
1741
1751
1761
1771
ff
ff
ff
ii
—
—
—
gggg
gggg
gggg
hh ll
6
6
6
2
6
6
6
6
6
6
6
∆
E, Z
IND16, X
IND16, Y
IND16, Z
EXT
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
21
Table 7 Instruction Set Summary (Continued)
Mnemonic
Operation
Description
Address
Mode
Instruction
Condition Codes
Opcode Operand Cycles
S
MV
H
EV
N
Z
V
C
ADDB
Add to B
(B) + (M)
B
IND8, X
IND8, Y
IND8, Z
IMM8
E, X
E, Y
C1
D1
E1
ff
ff
ff
ii
—
—
—
gggg
gggg
gggg
hh ll
6
6
6
2
6
6
6
6
6
6
6
—
—
∆
—
∆
∆
∆
∆
F1
27C1
27D1
27E1
17C1
17D1
17E1
17F1
E, Z
IND16, X
IND16, Y
IND16, Z
EXT
ADDD
Add to D
(D) + (M : M + 1)
D
IND8, X
IND8, Y
IND8, Z
IMM8
E, X
E, Y
81
91
A1
FC
2781
2791
27A1
37B1
37C1
37D1
37E1
37F1
ff
ff
ff
ii
—
6
6
6
2
6
6
6
4
6
6
6
6
—
—
—
—
∆
∆
∆
∆
—
—
E, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
jjkk
gggg
gggg
gggg
hh ll
ADDE
Add to E
(E) + (M : M + 1)
E
IMM8
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
7C
ii
jj kk
gggg
gggg
gggg
hh ll
2
4
6
6
6
6
—
—
—
—
∆
∆
∆
∆
3731
3741
3751
3761
3771
ADE
ADX
ADY
ADZ
AEX
AEY
AEZ
AIS
Add D to E
Add D to X
Add D to Y
Add D to Z
Add E to X
Add E to Y
Add E to Z
(E) + (D)
(XK : IX) + («D)
(YK : IY) + («D)
(ZK : IZ) + («D)
(XK : IX) + («E)
(YK : IY) + («E)
(ZK : IZ) + («E)
E
INH
INH
INH
INH
INH
INH
INH
2778
37CD
37DD
37ED
374D
375D
376D
—
—
—
—
—
—
—
2
2
2
2
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
XK : IX
YK : IY
ZK : IZ
XK : IX
YK : IY
ZK : IZ
SK : SP
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Add Immediate Data to SK : SP + «IMM
SP
IMM8
IMM16
3F
373F
ii
jj kk
2
4
AIX
AIY
Add Immediate Value XK : IX + «IMM
to X
XK : IX
YK : IY
ZK : IZ
A
IMM8
IMM16
3C
373C
ii
jj kk
2
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
—
—
—
0
—
—
—
—
Add Immediate Value YK : IY + «IMM
to Y
IMM8
IMM16
3D
373D
ii
jj kk
2
4
AIZ
Add Immediate Value ZK : IZ + «IMM
to Z
IMM8
IMM16
3E
373E
ii
jj kk
2
4
ANDA
AND A
(A) • (M)
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
46
56
66
76
1746
1756
1766
1776
2746
2756
2766
ff
ff
ff
6
6
6
2
6
6
6
6
6
6
6
ii
gggg
gggg
gggg
hh ll
—
E, X
E, Y
E, Z
—
—
ANDB
AND B
(B) • (M)
B
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
C6
D6
E6
ff
ff
ff
6
6
6
2
6
6
6
6
6
6
6
—
—
—
—
∆
∆
0
—
F6
ii
17C6
17D6
17E6
17F6
27C6
27D6
27E6
gggg
gggg
gggg
hh ll
—
E, X
E, Y
E, Z
—
—
MOTOROLA
22
MC68HC16Z1
MC68HC16Z1TS/D
Table 7 Instruction Set Summary (Continued)
Mnemonic
Operation
Description
Address
Mode
Instruction
Condition Codes
Opcode Operand Cycles
S
MV
H
EV
N
Z
V
C
ANDD
AND D
(D) • (M : M + 1)
D
IND8, X
IND8, Y
IND8, Z
E, X
E, Y
E, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
86
96
A6
ff
ff
ff
—
—
6
6
6
6
6
6
4
6
6
6
6
—
—
—
—
∆
∆
0
—
2786
2796
27A6
37B6
37C6
37D6
37E6
37F6
—
jj kk
gggg
gggg
gggg
hh ll
ANDE
AND E
(E) • (M : M + 1)
E
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
3736
3746
3756
3766
3776
jj kk
gggg
gggg
gggg
hh ll
4
6
6
6
6
—
—
—
—
∆
∆
0
—
1
AND CCR
(CCR) • IMM16 CCR
IMM16
373A
jj kk
4
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
ANDP
ASL
Arithmetic Shift Left
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
04
14
24
1704
1714
1724
1734
ff
ff
ff
8
8
8
8
8
8
8
—
—
—
—
gggg
gggg
gggg
hh ll
ASLA
ASLB
ASLD
ASLE
ASLM
ASLW
Arithmetic Shift Left A
Arithmetic Shift Left B
Arithmetic Shift Left D
Arithmetic Shift Left E
INH
INH
INH
INH
INH
3704
3714
27F4
2774
27B6
—
—
—
—
—
2
2
2
2
4
—
—
—
—
—
—
—
—
—
—
∆
—
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
Arithmetic Shift Left
AM
—
∆
—
∆
Arithmetic Shift Left
Word
IND16, X
IND16, Y
IND16, Z
EXT
2704
2714
2724
2734
gggg
gggg
gggg
hh ll
8
8
8
8
—
—
ASR
Arithmetic Shift Right
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
0D
1D
2D
170D
171D
172D
173D
ff
ff
ff
8
8
8
8
8
8
8
—
—
—
—
∆
∆
∆
∆
gggg
gggg
gggg
hh ll
ASRA
ASRB
ASRD
ASRE
Arithmetic Shift Right A
Arithmetic Shift Right B
Arithmetic Shift Right D
Arithmetic Shift Right E
INH
INH
INH
INH
370D
371D
27FD
277D
—
—
—
—
2
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
23
Table 7 Instruction Set Summary (Continued)
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
Mode
Opcode Operand Cycles
S
MV
H
EV
N
Z
V
C
ASRM
Arithmetic Shift Right
AM
INH
27BA
—
4
—
—
—
∆
∆
—
—
∆
ASRW
Arithmetic Shift Right
Word
IND16, X
IND16, Y
IND16, Z
EXT
270D
271D
272D
273D
gggg
gggg
gggg
hh ll
8
8
8
8
—
—
—
—
∆
∆
∆
∆
4
Branch if Carry Clear
Clear Bit(s)
If C = 0, branch
REL8
B4
rr
6, 2
—
—
—
—
—
—
—
—
—
—
—
0
—
—
BCC
BCLR
(M) • (Mask)
M
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
08
18
28
mm gggg
mm gggg
mm gggg
mm hh ll
mm ff
8
8
8
8
8
8
8
∆
∆
38
1708
1718
1728
mm ff
mm ff
BCLRW
Clear Bit(s) Word
(M : M + 1) • (Mask)
M : M + 1
IND16, X
IND16, Y
IND16, Z
EXT
2708
2718
2728
2738
gggg
mmmm
gggg
mmmm
gggg
10
10
10
10
—
—
—
—
∆
∆
0
—
mmmm
hh ll
mmmm
4
Branch if Carry Set
Branch if Equal
If C = 1, branch
If Z = 1, branch
REL8
REL8
REL8
B5
B7
BC
rr
rr
rr
6, 2
6, 2
6, 2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BCS
4
BEQ
4
Branch if Greater Than
or Equal to Zero
If N V = 0, branch
BGE
BGND
Enter Background De-
bug Mode
If BDM enabled
enter BDM;
else, illegal instruction
INH
37A6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
Branch if Greater Than If Z + (N V) = 0, branch
Zero
REL8
REL8
BE
B2
rr
rr
6, 2
6, 2
BGT
4
Branch if Higher
If C + Z = 0, branch
—
—
—
—
—
—
—
—
—
—
—
0
—
—
BHI
BITA
Bit Test A
(A) • (M)
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
49
59
69
79
1749
1759
1769
1779
2749
2759
2769
ff
ff
ff
6
6
6
2
6
6
6
6
6
6
6
∆
∆
ii
gggg
gggg
gggg
hh ll
—
E, X
E, Y
E, Z
—
—
BITB
Bit Test B
(B) • (M)
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
C9
D9
E9
ff
ff
ff
6
6
6
2
6
6
6
6
6
6
6
—
—
—
—
∆
∆
0
—
F9
ii
17C9
17D9
17E9
17F9
27C9
27D9
27E9
gggg
gggg
gggg
hh ll
—
E, X
E, Y
E, Z
—
—
4
Branch if Less Than or If Z + (N V) = 1, branch
Equal to Zero
REL8
REL8
REL8
BF
B3
BD
rr
rr
rr
6, 2
6, 2
6, 2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BLE
4
Branch if Lower or
Same
If C + Z = 1, branch
BLS
4
Branch if Less Than
Zero
If N V = 1, branch
BLT
4
Branch if Minus
If N = 1, branch
If Z = 0, branch
REL8
REL8
BB
B6
rr
rr
6, 2
6, 2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BMI
4
Branch if Not Equal
BNE
MOTOROLA
24
MC68HC16Z1
MC68HC16Z1TS/D
Table 7 Instruction Set Summary (Continued)
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
Mode
Opcode Operand Cycles
S
MV
H
EV
N
Z
V
C
4
Branch if Plus
Branch Always
If N = 0, branch
If 1 = 1, branch
REL8
BA
rr
6, 2
—
—
—
—
—
—
—
—
BPL
BRA
REL8
B0
rr
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
Branch if Bit(s) Clear If (M) • (Mask) = 0, branch
IND8, X
IND8, Y
IND8, Z
IND16, X
CB
DB
EB
0A
mm ff rr
mm ff rr
mm ff rr
mm
10, 12
10, 12
10, 12
10, 14
BRCLR
gggg rrrr
mm
gggg rrrr
mm
gggg rrrr
mm hh ll
rrrr
IND16, Y
IND16, Z
EXT
1A
2A
3A
10, 14
10, 14
10, 14
BRN
Branch Never
If 1 = 0, branch
REL8
B1
rr
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
Branch if Bit(s) Set
If (M) • (Mask) = 0, branch
IND8, X
IND8, Y
IND8, Z
IND16, X
8B
9B
AB
0B
mm ff rr
mm ff rr
mm ff rr
mm
10, 12
10, 12
10, 12
10, 14
BRSET
gggg rrrr
mm
gggg rrrr
mm
gggg rrrr
mm hh ll
rrrr
IND16, Y
IND16, Z
EXT
1B
2B
3B
10, 14
10, 14
10, 14
BSET
Set Bit(s)
(M) • (Mask)
M
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
09
19
29
mm gggg
mm gggg
mm gggg
mm hh ll
mm ff
8
8
8
8
8
8
8
—
—
—
—
—
—
—
—
∆
∆
∆
∆
0
0
—
—
39
1709
1719
1729
mm ff
mm ff
BSETW
Set Bit(s) in Word
(M : M + 1) • (Mask)
M : M + 1
IND16, X
IND16, Y
IND16, Z
EXT
2709
2719
2729
2739
gggg
mmmm
gggg
mmmm
gggg
10
10
10
10
mmmm
hh ll
mmmm
BSR
Branch to Subroutine (PK : PC) − 2
PK : PC
SK : SP
REL8
36
rr
10
—
—
—
—
—
—
—
—
Push (PC)
(SK : SP) – 2
Push (CCR)
(SK : SP) – 2
(PK:PC) + Offset
SK : SP
PK:PC
4
Branch if Overflow
Clear
If V = 0, branch
REL8
B8
rr
6, 2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BVC
4
Branch if Overflow Set
If V = 1, branch
(A) – (B)
REL8
INH
B9
rr
6, 2
2
BVS
CBA
CLR
Compare A to B
Clear Memory
371B
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
$00
M
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
05
15
25
1705
1715
1725
1735
ff
ff
ff
4
4
4
6
6
6
6
0
1
0
0
gggg
gggg
gggg
hh ll
CLRA
CLRB
CLRD
CLRE
CLRM
Clear A
Clear B
Clear D
Clear E
Clear AM
$00
$00
A
B
INH
INH
INH
INH
INH
3705
3715
27F5
2775
27B7
—
—
—
—
—
2
2
2
2
2
—
—
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
—
—
0
0
0
1
1
0
0
0
0
$0000
D
0
1
0
0
$0000
E
0
1
0
0
$000000000
AM[32:0]
—
—
—
—
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
25
Table 7 Instruction Set Summary (Continued)
Mnemonic
Operation
Description
Address
Mode
Instruction
Condition Codes
Opcode Operand Cycles
S
MV
H
EV
N
Z
V
C
CLRW
Clear Memory Word
$0000
M : M + 1
IND16, X
IND16, Y
IND16, Z
EXT
2705
2715
2725
2735
gggg
gggg
gggg
hh ll
6
6
6
6
—
—
—
—
0
1
0
0
CMPA
CMPB
COM
Compare A to Memory
Compare B to Memory
One’s Complement
(A) – (M)
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
48
58
68
78
1748
1758
1768
1778
2748
2758
2768
ff
ff
ff
6
6
6
2
6
6
6
6
6
6
6
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
0
∆
∆
1
ii
gggg
gggg
gggg
hh ll
—
E, X
E, Y
E, Z
—
—
(B) – (M)
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
C8
D8
E8
ff
ff
ff
6
6
6
2
6
6
6
6
6
6
6
F8
ii
17C8
17D8
17E8
17F8
27C8
27D8
27E8
gggg
gggg
gggg
hh ll
—
E, X
E, Y
E, Z
—
—
$FF – (M)
M
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
00
10
20
1700
1710
1720
1730
ff
ff
ff
8
8
8
8
8
8
8
gggg
gggg
gggg
hh ll
COMA
COMB
COMD
COME
COMW
One’s Complement A
One’s Complement B
One’s Complement D
One’s Complement E
$FF – (A)
$FF – (B)
A
B
INH
INH
INH
INH
3700
3710
27F0
2770
—
—
—
—
2
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
0
0
0
0
0
1
1
1
1
1
$FFFF – (D)
$FFFF – (E)
D
E
One’s Complement
Word
$FFFF – M : M + 1
M : M + 1
IND16, X
IND16, Y
IND16, Z
EXT
2700
2710
2720
2730
gggg
gggg
gggg
hh ll
8
8
8
8
CPD
Compare D to Memory
(D) – (M : M + 1)
IND8, X
IND8, Y
IND8, Z
E, X
E, Y
E, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
88
98
A8
ff
ff
ff
—
—
6
6
6
6
6
6
4
6
6
6
6
—
—
—
—
∆
∆
∆
∆
2788
2798
27A8
37B8
37C8
37D8
37E8
37F8
—
jj kk
gggg
gggg
gggg
hh ll
CPE
CPS
Compare E to Memory
(E) – (M : M + 1)
(SP) – (M : M + 1)
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
3738
3748
3758
3768
3778
jjkk
gggg
gggg
gggg
hhll
4
6
6
6
6
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
Compare SP to
Memory
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
4F
5F
6F
174F
175F
176F
177F
377F
ff
ff
ff
6
6
6
6
6
6
6
4
gggg
gggg
gggg
hh ll
jj kk
IMM16
MOTOROLA
26
MC68HC16Z1
MC68HC16Z1TS/D
Table 7 Instruction Set Summary (Continued)
Mnemonic
Operation
Description
Address
Mode
Instruction
Condition Codes
Opcode Operand Cycles
S
MV
H
EV
N
Z
V
C
CPX
Compare IX to Memory
(IX) – (M : M + 1)
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
4C
5C
6C
174C
175C
176C
177C
377C
ff
ff
ff
6
6
6
6
6
6
6
4
—
—
—
—
∆
∆
∆
∆
gggg
gggg
gggg
hh ll
jj kk
IMM16
CPY
CompareIYtoMemory
(IY) – (M : M + 1)
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
4D
5D
6D
174D
175D
176D
177D
377D
ff
ff
ff
6
6
6
6
6
6
6
4
—
—
—
—
∆
∆
∆
∆
gggg
gggg
gggg
hh ll
jj kk
IMM16
CPZ
Compare IZ to Memory
(IZ) – (M : M + 1)
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
4E
5E
6E
174E
175E
176E
177E
377E
ff
ff
ff
6
6
6
6
6
6
6
4
—
—
—
—
∆
∆
∆
∆
gggg
gggg
gggg
hh ll
jj kk
IMM16
DAA
DEC
Decimal Adjust A
(A)
10
INH
3721
—
2
—
—
—
—
—
—
—
—
∆
∆
∆
∆
U
∆
Decrement Memory
(M) – $01
M
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
01
11
21
1701
1711
1721
1731
ff
ff
ff
8
8
8
8
8
8
8
∆
—
gggg
gggg
gggg
hh ll
DECA
DECB
DECW
Decrement A
Decrement B
(A) – $01
(B) – $01
A
B
INH
INH
3701
3711
—
—
2
2
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
∆
—
—
—
Decrement Memory
Word
(M : M + 1) – $0001
M : M + 1
IND16, X
IND16, Y
IND16, Z
EXT
2701
2711
2721
2731
gggg
gggg
gggg
hh ll
8
8
8
8
EDIV
Extended Unsigned
Divide
(E : D) / (IX)
INH
3728
—
24
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
Quotient
IX
Remainder
D
EDIVS
Extended Signed Di-
vide
(E : D) / (IX)
INH
3729
—
38
Quotient
IX
Remainder
ACCD
EMUL
EMULS
EORA
Extended Unsigned
Multiply
(E) (D)
(E) (D)
(A) (M)
E : D
INH
INH
3725
3726
—
—
10
8
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
—
—
0
∆
∆
Extended Signed Mul-
tiply
E : D
A
Exclusive OR A
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
44
54
64
74
1744
1754
1764
1774
2744
2754
2764
ff
ff
ff
6
6
6
2
6
6
6
6
6
6
6
—
ii
gggg
gggg
gggg
hh ll
—
E, X
E, Y
E, Z
—
—
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
27
Table 7 Instruction Set Summary (Continued)
Mnemonic
Operation
Description
Address
Mode
Instruction
Condition Codes
Opcode Operand Cycles
S
MV
H
EV
N
Z
V
C
EORB
Exclusive OR B
(B) (M)
B
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
C4
D4
E4
ff
ff
ff
6
6
6
2
6
6
6
6
6
6
6
—
—
—
—
∆
∆
0
—
F4
ii
17C4
17D4
17E4
17F4
27C4
27D4
27E4
gggg
gggg
gggg
hh ll
—
E, X
E, Y
E, Z
—
—
EORD
Exclusive OR D
(D) (M : M + 1)
D
IND8, X
IND8, Y
IND8, Z
E, X
E, Y
E, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
84
94
A4
ff
ff
ff
—
—
6
6
6
6
6
6
4
6
6
6
6
—
—
—
—
∆
∆
0
—
2784
2794
27A4
37B4
37C4
37D4
37E4
37F4
—
jjkk
gggg
gggg
gggg
hhll
EORE
Exclusive OR E
(E) (M : M + 1)
E
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
3734
3744
3754
3764
3774
jj kk
gggg
gggg
gggg
hh ll
4
6
6
6
6
—
—
—
—
∆
∆
0
—
FDIV
FMULS
IDIV
Fractional
Unsigned Divide
(D) / (IX)
Remainder
IX
D
INH
INH
INH
372B
3727
372A
—
—
—
22
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
0
∆
∆
∆
Fractional Signed
Multiply
(E) (D)
0
E : D[31:1]
D[0]
8
Integer Divide
(D) / (IX)
Remainder
IX;
D
22
—
∆
∆
INC
Increment Memory
(M) + $01
M
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
03
13
23
1703
1713
1723
1733
ff
ff
ff
8
8
8
8
8
8
8
—
gggg
gggg
gggg
hh ll
INCA
INCB
INCW
Increment A
Increment B
(A) + $01
(B) + $01
A
B
INH
INH
3703
3713
—
—
2
2
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
∆
—
—
—
Increment Memory
Word
(M : M + 1) + $0001
M : M + 1
IND16, X
IND16, Y
IND16, Z
EXT
2703
2713
2723
2733
gggg
gggg
gggg
hh ll
8
8
8
8
JMP
JSR
Jump
ea
PK : PC
IND20, X
IND20, Y
IND20, Z
EXT20
4B
5B
6B
7A
zg gggg
zg gggg
zg gggg
zb hh ll
8
8
8
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Jump to Subroutine
Push (PC)
(SK : SP) – 2
Push (CCR)
(SK : SP) – 2
ea
IND20, X
IND20, Y
IND20, Z
EXT20
89
99
A9
FA
zg gggg
zg gggg
zg gggg
zb hh ll
12
12
12
10
SK : SP
SK : SP
PK : PC
4
Long Branch if Carry
Clear
If C = 0, branch
REL16
REL16
3784
3785
rrrr
rrrr
6, 4
6, 4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LBCC
4
Long Branch if Carry
Set
If C = 1, branch
LBCS
4
Long Branch if Equal
If Z = 1, branch
If EV = 1, branch
If N V = 0, branch
REL16
REL16
REL16
3787
3791
378C
rrrr
rrrr
rrrr
6, 4
6, 4
6, 4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LBEQ
4
Long Branch if EV Set
LBEV
4
Long Branch if Greater
Than or Equal to Zero
LBGE
4
Long Branch if Greater If Z ✛ (N V) = 0, branch
REL16
378E
rrrr
6, 4
—
—
—
—
—
—
—
—
LBGT
Than Zero
MOTOROLA
28
MC68HC16Z1
MC68HC16Z1TS/D
Table 7 Instruction Set Summary (Continued)
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
Mode
Opcode Operand Cycles
S
MV
H
EV
N
Z
V
C
4
Long Branch if Higher
If C ✛ Z = 0, branch
REL16
3782
rrrr
6, 4
—
—
—
—
—
—
—
—
LBHI
4
Long Branch if Less If Z ✛ (N V) = 1, branch
Than or Equal to Zero
REL16
REL16
REL16
378F
rrrr
6, 4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LBLE
4
Long Branch if Lower
or Same
If C ✛ Z = 1, branch
3783
378D
rrrr
rrrr
6, 4
6, 4
LBLS
4
Long Branch if Less
Than Zero
If N V = 1, branch
LBLT
4
Long Branch if Minus
If N = 1, branch
If MV = 1, branch
If Z = 0, branch
REL16
REL16
REL16
378B
3790
3786
rrrr
rrrr
rrrr
6, 4
6, 4
6, 4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LBMI
4
Long Branch if MV Set
LBMV
4
Long Branch if Not
Equal
LBNE
4
Long Branch if Plus
If N = 0, branch
REL16
378A
rrrr
6, 4
—
—
—
—
—
—
—
—
LBPL
LBRA
LBRN
LBSR
Long Branch Always
Long Branch Never
If 1 = 1, branch
If 1 = 0, branch
Push (PC)
REL16
REL16
REL16
3780
3781
27F9
rrrr
rrrr
rrrr
6
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Long Branch to
Subroutine
10
(SK : SP) – 2
Push (CCR)
(SK : SP) – 2 SK : SP
SK : SP
(PK : PC) + Offset
PK : PC
4
Long Branch if
Overflow Clear
If V = 0, branch
REL16
REL16
3788
3789
rrrr
rrrr
6, 4
6, 4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∆
—
—
∆
—
—
0
—
—
—
LBVC
4
Long Branch if
Overflow Set
If V = 1, branch
LBVS
LDAA
LDAB
LDD
Load A
Load B
Load D
Load E
(M)
A
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
45
55
65
75
1745
1755
1765
1775
2745
2755
2765
ff
ff
ff
6
6
6
2
6
6
6
6
6
6
6
ii
gggg
gggg
gggg
hh ll
—
E, X
E, Y
E, Z
—
—
(M)
B
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
C5
D5
E5
ff
ff
ff
6
6
6
2
6
6
6
6
6
6
6
—
—
—
—
∆
∆
0
—
F5
ii
17C5
17D5
17E5
17F5
27C5
27D5
27E5
gggg
gggg
gggg
hh ll
—
E, X
E, Y
E, Z
—
—
(M : M + 1)
D
IND8, X
IND8, Y
IND8, Z
E, X
E, Y
E, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
85
95
A5
ff
ff
ff
—
—
6
6
6
6
6
6
4
6
6
6
6
—
—
—
—
∆
∆
0
—
2785
2795
27A5
37B5
37C5
37D5
37E5
37F5
—
jj kk
gggg
gggg
gggg
hh ll
LDE
(M : M + 1)
(M : M + 1)
E
E
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
3735
3745
3755
3765
3775
jj kk
gggg
gggg
gggg
hh ll
4
6
6
6
6
—
—
—
—
—
—
—
—
∆
∆
0
—
—
LDED
Load Concatenated
E and D
EXT
2771
hh ll
8
—
—
—
(M + 2 : M + 3)
D
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
29
Table 7 Instruction Set Summary (Continued)
Mnemonic
LDHI
Operation
Initialize H and I
Load SP
Description
Address
Instruction
Condition Codes
Mode
Opcode Operand Cycles
S
MV
H
EV
N
Z
V
C
(M : M + 1)
H R
EXT
27B0
—
8
—
—
—
—
—
—
—
—
X
(M : M + 1)
I R
SP
Y
LDS
(M : M + 1)
(M : M + 1)
(M : M + 1)
(M : M + 1)
If S
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
CF
DF
EF
17CF
17DF
17EF
17FF
37BF
ff
ff
ff
6
6
6
6
6
6
6
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
0
0
0
0
—
—
—
—
gggg
gggg
gggg
hh ll
jj kk
IMM16
LDX
LDY
LDZ
Load IX
Load IY
Load IZ
IX
IY
IZ
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
CC
DC
EC
17CC
17DC
17EC
17FC
37BC
ff
ff
ff
6
6
6
6
6
6
6
4
gggg
gggg
gggg
hh ll
jj kk
IMM16
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
CD
DD
ED
17CD
17DD
17ED
17FD
37BD
ff
ff
ff
6
6
6
6
6
6
6
4
gggg
gggg
gggg
hh ll
jj kk
IMM16
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
CE
DE
EE
17CE
17DE
17EE
17FE
37BE
ff
ff
ff
6
6
6
6
6
6
6
4
gggg
gggg
gggg
hh ll
jj kk
IMM16
LPSTOP
LSR
Low Power Stop
INH
27F1
—
4, 20
—
—
—
—
—
—
—
—
—
0
—
—
—
then STOP
else NOP
Logical Shift Right
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
0F
1F
2F
170F
171F
172F
173F
ff
ff
ff
8
8
8
8
8
8
8
∆
∆
∆
gggg
gggg
gggg
hh ll
LSRA
LSRB
LSRD
LSRE
LSRW
Logical Shift Right A
Logical Shift Right B
Logical Shift Right D
Logical Shift Right E
INH
INH
INH
INH
370F
371F
27FF
277F
—
—
—
—
2
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
Logical Shift Right
Word
IND16, X
IND16, Y
IND16, Z
EXT
270F
271F
272F
273F
gggg
gggg
gggg
hh ll
8
8
8
8
MOTOROLA
30
MC68HC16Z1
MC68HC16Z1TS/D
Table 7 Instruction Set Summary (Continued)
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
Mode
Opcode Operand Cycles
S
MV
H
EV
N
Z
V
C
MAC
Multiply and
Accumulate
Signed 16-Bit
Fractions
(HR) (IR)
E : D
AM
IX
IMM8
7B
xoyo
12
—
∆
—
∆
—
—
∆
—
(AM) + (E : D)
Qualified (IX)
Qualified (IY)
IY
(HR)
IZ
(M : M + 1)
HR
IR
X
(M : M + 1)
Y
MOVB
MOVW
Move Byte
Move Word
(M )
1
M
IXP to EXT
EXT to IXP
EXT to EXT
30
32
37FE
ff hh ll
ff hh ll
hh ll hh ll
8
8
10
—
—
—
—
—
—
—
—
∆
∆
∆
∆
0
0
—
—
2
(M : M + 1 )
M : M + 1
IXP to EXT
EXT to IXP
EXT to EXT
31
33
37FF
ff hh ll
ff hh ll
hh ll hh ll
8
8
10
1
2
MUL
NEG
Multiply
(A) (B)
D
INH
3724
—
10
—
—
—
—
—
—
—
—
—
—
—
∆
∆
Negate Memory
$00 – (M)
M
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
02
12
22
1702
1712
1722
1732
ff
ff
ff
8
8
8
8
8
8
8
∆
∆
∆
gggg
gggg
gggg
hh ll
NEGA
NEGB
NEGD
NEGE
NEGW
Negate A
Negate B
$00 – (A)
$00 – (B)
A
B
INH
INH
INH
INH
3702
3712
27F2
2772
—
—
—
—
2
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
Negate D
$0000 – (D)
$0000 – (E)
D
E
Negate E
Negate Memory Word
$0000 – (M : M + 1)
M : M + 1
IND16, X
IND16, Y
IND16, Z
EXT
2702
2712
2722
2732
gggg
gggg
gggg
hh ll
8
8
8
8
NOP
Null Operation
OR A
—
INH
274C
—
2
—
—
—
—
—
—
—
—
—
—
—
0
—
—
ORAA
(A) ✛ (M)
A
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
47
57
67
77
1747
1757
1767
1777
2747
2757
2767
ff
ff
ff
6
6
6
2
6
6
6
6
6
6
6
∆
∆
ii
gggg
gggg
gggg
hh ll
—
E, X
E, Y
E, Z
—
—
ORAB
OR B
(B) ✛ (M)
B
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
C7
D7
E7
ff
ff
ff
6
6
6
2
6
6
6
6
6
6
6
—
—
—
—
∆
∆
0
—
F7
ii
17C7
17D7
17E7
17F7
27C7
27D7
27E7
gggg
gggg
gggg
hh ll
—
E, X
E, Y
E, Z
—
—
ORD
OR D
(D) ✛ (M : M + 1)
D
IND8, X
IND8, Y
IND8, Z
E, X
E, Y
E, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
87
97
A7
ff
ff
ff
—
—
6
6
6
6
6
6
4
6
6
6
6
—
—
—
—
∆
∆
0
—
2787
2797
27A7
37B7
37C7
37D7
37E7
37F7
—
jj kk
gggg
gggg
gggg
hh ll
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
31
Table 7 Instruction Set Summary (Continued)
Mnemonic
Operation
Description
Address
Mode
Instruction
Condition Codes
Opcode Operand Cycles
S
MV
H
EV
N
Z
V
C
ORE
OR E
(E) ✛ (M : M + 1)
E
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
3737
3747
3757
3767
3777
jj kk
gggg
gggg
gggg
hh ll
4
6
6
6
6
—
—
—
—
∆
∆
0
—
1
OR Condition Code
Register
(CCR) ✛ IMM16
CCR
IMM16
373B
jj kk
4
∆
∆
∆
∆
∆
∆
∆
∆
ORP
PSHA
PSHB
PSHM
Push A
(SK : SP) + 1
Push (A)
SK : SP
INH
3708
—
4
—
—
—
—
—
—
—
—
(SK : SP) – 2
SK : SP
Push B
(SK : SP) + 1
SK : SP
INH
3718
34
—
ii
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Push (B)
(SK : SP) – 2
SK : SP
Push Multiple
Registers
For mask bits 0 to 7:
IMM8
4 + 2N
If mask bit set
Push register
Mask bits:
0 = D
1 = E
N =
number of
iterations
(SK : SP) – 2
SK : SP
2 = IX
3 = IY
4 = IZ
5 = K
6 = CCR
7 = (reserved)
PSHMAC
PULA
Push MAC State
Pull A
MAC Registers
Stack
INH
INH
27B8
3709
—
—
14
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(SK : SP) + 2
Pull (A)
SK : SP
(SK : SP) – 1
SK : SP
SK : SP
PULB
Pull B
(SK : SP) + 2
Pull (B)
INH
3719
35
—
ii
6
—
—
—
—
—
—
—
—
(SK : SP) – 1
SK : SP
1
Pull Multiple Registers
For mask bits 0 to 7:
IMM8
4+2(N+1)
∆
∆
∆
∆
∆
∆
∆
∆
PULM
Mask bits:
0 = CCR[15:4]
1 = K
N =
number of
iterations
If mask bit set
(SK : SP) + 2
SK : SP
Pull register
2 = IZ
3 = IY
4 = IX
5 = E
6 = D
7 = (reserved)
PULMAC
RMAC
Pull MAC State
Stack
MAC Registers
INH
27B9
FB
—
16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Repeating
Multiply and
Accumulate
Signed 16-Bit
Fractions
Repeat until (E) < 0
IMM8
xoyo
6 + 12
per
iteration
∆
∆
(AM) + (H) (I)
Qualified (IX)
Qualified (IY)
AM
IX;
IY;
H;
(M : M + 1)
X
(M : M + 1)
Y
I
(E) – 1
E
ROL
Rotate Left
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
0C
1C
2C
170C
171C
172C
173C
ff
ff
ff
8
8
8
8
8
8
8
—
—
—
—
∆
∆
∆
∆
gggg
gggg
gggg
hh ll
ROLA
ROLB
Rotate Left A
Rotate Left B
INH
370C
—
2
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
INH
371C
—
2
MOTOROLA
32
MC68HC16Z1
MC68HC16Z1TS/D
Table 7 Instruction Set Summary (Continued)
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
Mode
Opcode Operand Cycles
S
MV
H
EV
N
Z
V
C
ROLD
Rotate Left D
INH
27FC
—
—
2
—
—
—
—
∆
∆
∆
∆
ROLE
Rotate Left E
INH
277C
2
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
ROLW
Rotate Left Word
IND16, X
IND16, Y
IND16, Z
EXT
270C
271C
272C
273C
gggg
gggg
gggg
hh ll
8
8
8
8
ROR
Rotate Right
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
0E
1E
2E
170E
171E
172E
173E
ff
ff
ff
8
8
8
8
8
8
8
—
—
—
—
∆
∆
∆
∆
gggg
gggg
gggg
hh ll
RORA
RORB
RORD
RORE
RORW
Rotate Right A
Rotate Right B
Rotate Right D
Rotate Right E
Rotate Right Word
INH
INH
INH
INH
370E
371E
27FE
277E
—
—
—
—
2
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
IND16, X
IND16, Y
IND16, Z
EXT
270E
271E
272E
273E
gggg
gggg
gggg
hh ll
8
8
8
8
2
Return from Interrupt (SK : SP) + 2
Pull CCR
(SK : SP) + 2
Pull PC
SK : SP
INH
INH
INH
2777
27F7
370A
—
—
—
12
12
2
∆
∆
∆
∆
∆
∆
∆
∆
RTI
SK : SP
(PK : PC) – 6
PK : PC
3
Return from Subrou-
tine
(SK : SP) + 2
SK : SP
—
—
—
—
—
—
—
—
RTS
Pull PK
(SK : SP) + 2
Pull PC
SK : SP
(PK : PC) – 2
PK : PC
SBA
Subtract B from A
(A) – (B)
A
A
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
SBCA
Subtract with Carry
from A
(A) – (M) – C
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
42
52
62
72
1742
1752
1762
1772
2742
2752
2762
ff
ff
ff
6
6
6
2
6
6
6
6
6
6
6
ii
gggg
gggg
gggg
hh ll
—
E, X
E, Y
E, Z
—
—
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
33
Table 7 Instruction Set Summary (Continued)
Mnemonic
Operation
Description
Address
Mode
Instruction
Condition Codes
Opcode Operand Cycles
S
MV
H
EV
N
Z
V
C
SBCB
Subtract with Carry
from B
(B) – (M) – C
B
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
C2
D2
E2
ff
ff
ff
6
6
6
2
6
6
6
6
6
6
6
—
—
—
—
∆
∆
∆
∆
F2
ii
17C2
17D2
17E2
17F2
27C2
27D2
27E2
gggg
gggg
gggg
hh ll
—
E, X
E, Y
E, Z
—
—
SBCD
Subtract with Carry
from D
(D) – (M : M + 1) – C
D
IND8, X
IND8, Y
IND8, Z
E, X
E, Y
E, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
82
92
A2
ff
ff
ff
—
—
6
6
6
6
6
6
4
6
6
6
6
—
—
—
—
∆
∆
∆
∆
2782
2792
27A2
37B2
37C2
37D2
37E2
37F2
—
jj kk
gggg
gggg
gggg
hh ll
SBCE
Subtract with Carry
from E
(E) – (M : M + 1) – C
E
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
3732
3742
3752
3762
3772
jj kk
gggg
gggg
gggg
hh ll
4
6
6
6
6
—
—
—
—
∆
∆
∆
∆
SDE
Subtract D from E
Store A
(E) – (D)
(A)
E
INH
2779
—
2
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
STAA
M
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
4A
5A
6A
174A
175A
176A
177A
274A
275A
276A
ff
ff
ff
4
4
4
6
6
6
6
4
4
4
0
—
gggg
gggg
gggg
hh ll
—
—
—
STAB
Store B
Store D
Store E
(B)
M
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
CA
DA
EA
17CA
17DA
17EA
17FA
27CA
27DA
27EA
ff
ff
ff
4
4
4
6
6
6
6
4
4
4
—
—
—
—
∆
∆
0
—
gggg
gggg
gggg
hh ll
—
—
—
STD
(D)
M : M + 1
IND8, X
IND8, Y
IND8, Z
E, X
E, Y
E, Z
IND16, X
IND16, Y
IND16, Z
EXT
8A
9A
AA
278A
279A
27AA
37CA
37DA
37EA
37FA
ff
ff
ff
—
—
6
6
6
6
6
6
4
4
4
6
—
—
—
—
∆
∆
0
—
—
gggg
gggg
gggg
hh ll
STE
(E)
(E)
M : M + 1
IND16, X
IND16, Y
IND16, Z
EXT
374A
375A
376A
377A
gggg
gggg
gggg
hh ll
6
6
6
6
—
—
—
—
—
—
—
—
∆
∆
0
—
—
STED
Store Concatenated
D and E
M : M + 1
M + 2 : M + 3
EXT
2773
hh ll
8
—
—
—
(D)
MOTOROLA
34
MC68HC16Z1
MC68HC16Z1TS/D
Table 7 Instruction Set Summary (Continued)
Mnemonic
Operation
Description
Address
Mode
Instruction
Condition Codes
Opcode Operand Cycles
S
MV
H
EV
N
Z
V
C
STS
Store SP
(SP)
M : M + 1
M : M + 1
M : M + 1
M : M + 1
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
8F
9F
AF
178F
179F
17AF
17BF
ff
ff
ff
4
4
4
6
6
6
6
—
—
—
—
∆
∆
0
—
gggg
gggg
gggg
hh ll
STX
STY
Store IX
(IX)
(IY)
(IZ)
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
8C
9C
AC
178C
179C
17AC
17BC
ff
ff
ff
4
4
4
6
6
6
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
0
0
0
∆
—
—
—
∆
gggg
gggg
gggg
hh ll
Store IY
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
8D
9D
AD
178D
179D
17AD
17BD
ff
ff
ff
4
4
4
6
6
6
6
gggg
gggg
gggg
hh ll
STZ
Store Z
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
8E
9E
AE
178E
179E
17AE
17BE
ff
ff
ff
4
4
4
6
6
6
6
gggg
gggg
gggg
hh ll
SUBA
Subtract from A
(A) – (M)
A
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
40
50
60
70
1740
1750
1760
1770
2740
2750
2760
ff
ff
ff
6
6
6
2
6
6
6
6
6
6
6
ii
gggg
gggg
gggg
hh ll
—
E, X
E, Y
E, Z
—
—
SUBB
SUBD
SUBE
Subtract from B
Subtract from D
Subtract from E
(B) – (M)
B
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
C0
D0
E0
ff
ff
ff
6
6
6
2
6
6
6
6
6
6
6
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
F0
ii
17C0
17D0
17E0
17F0
27C0
27D0
27E0
gggg
gggg
gggg
hh ll
—
E, X
E, Y
E, Z
—
—
(D) – (M : M + 1)
D
IND8, X
IND8, Y
IND8, Z
E, X
E, Y
E, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
80
90
A0
ff
ff
ff
—
—
6
6
6
6
6
6
4
6
6
6
6
2780
2790
27A0
37B0
37C0
37D0
37E0
37F0
—
jj kk
gggg
gggg
gggg
hh ll
(E) – (M : M + 1)
E
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
3730
3740
3750
3760
3770
jj kk
gggg
gggg
gggg
hh ll
4
6
6
6
6
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
35
Table 7 Instruction Set Summary (Continued)
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
Mode
Opcode Operand Cycles
S
MV
H
EV
N
Z
V
C
SWI
Software Interrupt
(PK : PC) + 2
Push (PC)
(SK : SP) – 2 SK : SP
Push (CCR)
PK : PC
INH
3720
—
16
—
—
—
—
—
—
—
—
(SK : SP) – 2
$0
SK : SP
PK
SWI Vector
PC
SXT
Sign Extend B into A
If B7 = 1
INH
27F8
—
2
—
—
—
—
∆
∆
—
—
then A = $FF
else A = $00
TAB
TAP
Transfer A to B
Transfer A to CCR
Transfer B to A
Transfer B to EK
Transfer B to SK
Transfer B to XK
Transfer B to YK
Transfer B to ZK
Transfer D to E
(A)
(A[7:0])
(B)
(B)
B
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
3717
37FD
3707
27FA
379F
379C
379D
379E
277B
372F
—
—
—
—
—
—
—
—
—
—
2
4
2
2
2
2
2
2
2
2
—
∆
—
∆
—
∆
—
∆
∆
∆
∆
∆
0
∆
—
∆
CCR[15:8]
TBA
A
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
0
—
—
—
—
—
—
—
—
TBEK
TBSK
TBXK
TBYK
TBZK
TDE
EK
SK
XK
YK
ZK
E
—
—
—
—
—
∆
—
—
—
—
—
∆
—
—
—
—
—
0
(B)
(B)
(B)
(B)
(D)
TDMSK
Transfer D to
XMSK : YMSK
(D[15:8])
(D[7:0])
X MASK
Y MASK
—
—
—
1
Transfer D to CCR
(D)
CCR[15:4]
INH
372D
—
4
∆
∆
∆
∆
∆
∆
∆
∆
TDP
TED
Transfer E to D
(E)
D
INH
INH
27FB
27B1
—
—
2
4
—
—
—
0
—
—
—
0
∆
∆
0
—
—
TEDM
Transfer E and D to
AM[31:0]
(D)
(E)
AM[15:0]
AM[31:16]
—
—
—
Sign Extend AM
AM[35:32] = AM31
TEKB
TEM
Transfer EK to B
$0
(EK)
B[7:4]
B[3:0]
INH
INH
27BB
27B2
—
—
2
4
—
—
—
0
—
—
—
0
—
—
—
—
—
—
—
—
Transfer E to
AM[31:16]
(E)
$00
AM[31:16]
AM[15:0]
Sign Extend AM
Clear AM LSB
AM[35:32] = AM31
TMER
Transfer AM to E
Rounded
Rounded (AM)
If (SM • (EV ✛ MV))
Temp
INH
27B4
—
6
—
∆
—
∆
∆
∆
—
—
then Saturation
E
else Temp[31:16]
E
TMET
Transfer AM to E Trun-
cated
If (SM • (EV ✛ MV))
INH
INH
27B5
27B3
—
—
2
6
—
—
—
—
—
—
—
—
∆
∆
—
—
—
—
then Saturation
else AM[31:16]
E
E
TMXED
Transfer AM to
IX : E : D
AM[35:32]
AM35
IX[3:0]
IX[15:4]
—
—
AM[31:16]
AM[15:0]
E
D
TPA
Transfer CCR MSB to
A
(CCR[15:8])
A
INH
37FC
—
2
—
—
—
—
—
—
—
—
TPD
Transfer CCR to D
Transfer SK to B
(CCR)
D
INH
INH
372C
37AF
—
—
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TSKB
(SK)
$0
B[3:0]
B[7:4]
TST
Test for Zero or Minus
(M) – $00
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
06
16
26
1706
1716
1726
1736
ff
ff
ff
6
6
6
6
6
6
6
—
—
—
—
∆
∆
0
0
gggg
gggg
gggg
hh ll
TSTA
TSTB
TSTD
TSTE
Test A for
Zero or Minus
(A) – $00
(B) – $00
INH
INH
INH
INH
3706
3716
27F6
2776
—
—
—
—
2
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
0
0
0
0
0
0
0
0
Test B for
Zero or Minus
Test D for
Zero or Minus
(D) – $0000
(E) – $0000
Test E for
Zero or Minus
MOTOROLA
36
MC68HC16Z1
MC68HC16Z1TS/D
Table 7 Instruction Set Summary (Continued)
Mnemonic
Operation
Description
Address
Mode
Instruction
Condition Codes
Opcode Operand Cycles
S
MV
H
EV
N
Z
V
C
TSTW
Test for
Zero or Minus Word
(M : M + 1) – $0000
IND16, X
IND16, Y
IND16, Z
EXT
2706
2716
2726
2736
gggg
gggg
gggg
hh ll
6
6
6
6
—
—
—
—
∆
∆
0
0
TSX
TSY
Transfer SP to X
Transfer SP to Y
Transfer SP to Z
Transfer XK to B
(SK : SP) + 2
(SK : SP) + 2
(SK : SP) + 2
XK : IX
INH
INH
INH
INH
274F
275F
276F
37AC
—
—
—
—
2
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
YK : IY
ZK : IZ
TSZ
TXKB
$0
B[7:4]
B[3:0]
(XK)
TXS
TXY
Transfer X to SP
Transfer X to Y
Transfer X to Z
Transfer YK to B
(XK : IX) – 2
(XK : IX)
SK : SP
YK : IY
ZK : IZ
INH
INH
INH
INH
374E
275C
276C
37AD
—
—
—
—
2
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TXZ
(XK : IX)
TYKB
$0
B[7:4]
(YK)
B[3:0]
TYS
TYX
Transfer Y to SP
Transfer Y to X
Transfer Y to Z
Transfer ZK to B
(YK : IY) – 2
(YK : IY)
SK : SP
XK : IX
ZK : IZ
INH
INH
INH
INH
375E
274D
276D
37AE
—
—
—
—
2
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TYZ
(YK : IY)
TZKB
$0
(ZK)
B[7:4]
B[3:0]
TZS
TZX
Transfer Z to SP
Transfer Z to X
(ZK : IZ) – 2
(ZK : IZ)
SK : SP
XK : IX
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
376E
274E
275E
27F3
371A
277A
37CC
37DC
37EC
374C
375C
376C
—
—
—
—
—
—
—
—
—
—
—
—
2
2
2
8
2
2
2
2
2
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TZY
Transfer Z to Y
(ZK : IZ)
ZK : IY
WAI
Wait for Interrupt
Exchange A with B
Exchange D with E
Exchange D with X
Exchange D with Y
Exchange D with Z
Exchange E with X
Exchange E with Y
Exchange E with Z
WAIT
XGAB
XGDE
XGDX
XGDY
XGDZ
XGEX
XGEY
XGEZ
NOTES:
(A)
(D)
(D)
(D)
(D)
(E)
(E)
(E)
(B)
(E)
(IX)
(IY)
(IZ)
(IX)
(IY)
(IZ)
1. CCR[15:4] change according to results of operation. The PK field is not affected.
2. CCR[15:0] change according to copy of CCR pulled from stack.
3. PK field changes according to state pulled from stack. The rest of the CCR is not affected.
4. Cycle times for conditional branches are shown in "taken, not taken" order.
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
37
Table 8 Instruction Set Abbreviations and Symbols
A — Accumulator A
AM — Accumulator M
B — Accumulator B
CCR — Condition code register
D — Accumulator D
X — Register used in operation
M — Address of one memory byte
M +1 — Address of byte at M + $0001
M : M + 1 — Address of one memory word
(...) — Contents of address pointed to by IX
X
E — Accumulator E
(...) — Contents of address pointed to by IY
Y
EK — Extended addressing extension field
(...) — Contents of address pointed to by IZ
Z
IR — MAC multiplicand register
HR — MAC multiplier register
IX — Index register X
E, X — IX with E offset
E, Y — IY with E offset
E, Z — IZ with E offset
IY — Index register Y
EXT — Extended
IZ — Index register Z
EXT20 — 20-bit extended
K — Address extension register
PC — Program counter
IMM8 — 8-bit immediate
IMM16 — 16-bit immediate
PK — Program counter extension field
SK — Stack pointer extension field
SL — Multiply and accumulate sign latch
SP — Stack pointer
IND8, X — IX with unsigned 8-bit offset
IND8, Y — IY with unsigned 8-bit offset
IND8, Z — IZ with unsigned 8-bit offset
IND16, X — IX with signed 16-bit offset
IND16, Y — IY with signed 16-bit offset
IND16, Z — IZ with signed 16-bit offset
IND20, X — IX with signed 20-bit offset
IND20, Y — IY with signed 20-bit offset
IND20, Z — IZ with signed 20-bit offset
INH — Inherent
XK — Index register X extension field
YK — Index register Y extension field
ZK — Index register Z extension field
XMSK — Modulo addressing index register X mask
YMSK — Modulo addressing index register Y mask
S — Stop disable control bit
MV — AM overflow indicator
H — Half carry indicator
IXP — Post-modified indexed
REL8 — 8-bit relative
EV — AM extended overflow indicator
N — Negative indicator
Z — Zero indicator
REL16 — 16-bit relative
b — 4-bit address extension
ff — 8-bit unsigned offset
V — Two's complement overflow indicator
C — Carry/borrow indicator
IP — Interrupt priority field
gggg — 16-bit signed offset
hh — High byte of 16-bit extended address
ii — 8-bit immediate data
SM — Saturation mode control bit
PK — Program counter extension field
— — Bit not affected
∆ — Bit changes as specified
0 — Bit cleared
jj — High byte of 16-bit immediate data
kk — Low byte of 16-bit immediate data
ll — Low byte of 16-bit extended address
mm — 8-bit mask
mmmm — 16-bit mask
1 — Bit set
M — Memory location used in operation
R — Result of operation
rr — 8-bit unsigned relative offset
rrrr — 16-bit signed relative offset
xo — MAC index register X offset
yo — MAC index register Y offset
z — 4-bit zero extension
S — Source data
+ — Addition
• — AND
- — Subtraction or negation (2's complement)
+ — Inclusive OR (OR)
— Exclusive OR (EOR)
NOT — Complementation
: — Concatenation
•
— Multiplication
/ — Division
> — Greater
< — Less
— Transferred
= — Equal
— Exchanged
≥ — Equal or greater
≤ — Equal or less
≠ — Not equal
± — Sign bit; also used to show tolerance
« — Sign extension
% — Binary value
$ — Hexadecimal value
MOTOROLA
38
MC68HC16Z1
MC68HC16Z1TS/D
2.7 Exceptions
An exception is an event that preempts normal instruction process. Exception processing makes the
transition from normal instruction execution to execution of a routine that deals with an exception.
Each exception has an assigned vector that points to an associated handler routine. Exception process-
ing includes all operations required to transfer control to a handler routine, but does not include execu-
tion of the handler routine.
2.7.1 Exception Vectors
An exception vector is the address of a routine that handles an exception. Exception vectors are con-
tained in a data structure called the instruction vector table, which is located in the first 512 bytes of
bank 0.
All vectors, except the reset vector, consist of one word and reside in data space. The reset vector con-
sists of four words that reside in program space. There are 52 predefined or reserved vectors, and 200
user-defined vectors.
Each vector is assigned an 8-bit number. Vector numbers for some exceptions are generated by exter-
nal devices; others are supplied by the processor. There is a direct mapping of vector number to vector
table address. The CPU16 left shifts the vector number one place (multiplies by two) to convert it to an
address.
Table 9 Exception Vector Table
Vector
Number
Vector
Address
Address
Space
Type of
Exception
0
0000
0002
P
P
P
P
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
RESET — Initial ZK, SK, and PK
RESET — Initial PC
0004
RESET — Initial SP
0006
RESET — Initial IZ (Direct Page)
BKPT (Breakpoint)
4
5
0008
000A
BERR (Bus Error)
6
000C
SWI (Software Interrupt)
Illegal Instruction
7
000E
8
0010
Division by Zero
9 – E
F
0012 – 001C
001E
Unassigned, Reserved
Uninitialized Interrupt
10
0020
Unassigned, Reserved
Level 1 Interrupt Autovector
Level 2 Interrupt Autovector
Level 3 Interrupt Autovector
Level 4 Interrupt Autovector
Level 5 Interrupt Autovector
Level 6 Interrupt Autovector
Level 7 Interrupt Autovector
Spurious Interrupt
11
0022
12
0024
13
0026
14
0028
15
002A
16
002C
17
002E
18
0030
19 – 37
38 – FF
0032 – 006E
0070 – 01FE
Unassigned, Reserved
User-defined Interrupts
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
39
2.7.2 Exception Stack Frame
During exception processing, the contents of the program counter and condition code register are
stacked at a location pointed to by SK : SP. Unless it is altered during exception processing, the stacked
PK : PC value is the address of the next instruction in the current instruction stream, plus $0006. The
following figure shows the exception stack frame.
Low Address
High Address
SP After Exception Stacking
SP Before Exception Stacking
Condition Code Register
Program Counter
Figure 7 Exception Stack Frame
2.7.3 Exception Processing Sequence
Exception processing is performed in four distinct phases.
• Priority of all pending exceptions is evaluated, and the highest priority exception is processed first.
• Processor state is stacked, then the CCR PK extension field is cleared.
• An exception vector number is acquired and converted to a vector address.
• The content of the vector address is loaded into the PC, and the processor jumps to the exception
handler routine.
There are variations within each phase for differing types of exceptions. However, all vectors but reset
contain 16-bit addresses, and the PK field is cleared. Exception handlers must be located within bank
0, or vectors must point to a jump table.
2.7.4 Types of Exceptions
Exceptions can be generated either internally or externally. External exceptions which are defined as
asynchronous, include interrupts, bus errors (BERR), breakpoints (BKPT), and resets (RESET). Inter-
nal exceptions, which are defined as synchronous, include the software interrupt (SWI) instruction, the
background (BGND) instruction, illegal instruction exceptions, and the divide-by-zero exception. Refer
to 3 System Integration Module for more information about resets and interrupts.
Asynchronous exceptions occur without reference to CPU16 or IMB clocks, but exception processing
is synchronized. For all asynchronous exceptions but RESET, exception processing begins at the first
instruction boundary following recognition of an exception.
Synchronous exception processing is part of an instruction definition. Exception processing for synchro-
nous exceptions will always be completed, and the first instruction of the handler routine will always be
executed, before interrupts are detected.
Because of pipelining, the stacked return PK : PC value for asynchronous exceptions, other than RE-
SET, is equal to the address of the next instruction in the current instruction stream plus $0006. The
RTI instruction, which must terminate all exception handler routines, subtracts $0006 from the stacked
value in order to resume execution of the interrupted instruction stream. The value of PK : PC at the
time a synchronous exception executes is equal to the address of the instruction that causes the excep-
tion plus $0006. Since RTI always subtracts $0006 upon return, the stacked PK : PC must be adjusted
by the instruction that caused the exception so that execution will resume with the following instruction.
$0002 is added to the PK : PC value before it is stacked.
MOTOROLA
40
MC68HC16Z1
MC68HC16Z1TS/D
2.7.5 Multiple Exceptions
Each exception has a hardware priority based upon its relative importance to system operation. Asyn-
chronous exceptions have higher priorities than synchronous exceptions. Exception processing for mul-
tiple exceptions is done by priority, from lowest to highest. Note that priority governs the order in which
exception processing occurs, not the order in which exception handlers are executed.
Unless bus error, breakpoint, or reset occur during exception processing, the first instruction of all ex-
ception handler routines is guaranteed to execute before another exception is processed. Because in-
terrupt exceptions have higher priority than synchronous exceptions, the first instruction in an interrupt
handler is executed before other interrupts are sensed.
Bus error, breakpoint, and reset exceptions that occur during exception processing of a previous excep-
tion are processed before the first instruction of that exception's handler routine. The converse is not
true. If an interrupt occurs during BERR exception processing, for example, the first instruction of the
BERR handler is executed before interrupts are sensed. This permits the exception handler to mask
interrupts during execution.
2.7.6 RTI Instruction
The return-from-interrupt instruction (RTI) must be the last instruction in all exception handlers except
for the reset handler. RTI pulls the exception stack frame that was pushed onto the system stack during
exception processing, and restores processor state. Normal program flow resumes at the address of
the instruction that follows the last instruction executed before exception processing began.
RTI is not used in the reset handler because a reset initializes the stack pointer and does not create a
stack frame.
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
41
3 System Integration Module
The MC68HC16Z1 system integration module (SIM) consists of five functional blocks that control sys-
tem start-up, initialization, configuration, and the external bus.
SYSTEM CONFIGURATION
AND PROTECTION
CLKOUT
CLOCK SYNTHESIZER
CHIP SELECTS
EXTAL
MODCLK
UPPER ADDRESS
CHIP SELECTS
EXTERNAL BUS
RESET
EXTERNAL BUS INTERFACE
FACTORY TEST
TSTME
FREEZE/QUOT
SIM BLOCK
Figure 8 SIM Block Diagram
MOTOROLA
42
MC68HC16Z1
MC68HC16Z1TS/D
Table 10 SIM Address Map
Address
YFFA00
YFFA02
YFFA04
YFFA06
YFFA08
YFFA0A
YFFA0C
YFFA0E
YFFA10
YFFA12
YFFA14
YFFA16
YFFA18
YFFA1A
YFFA1C
YFFA1E
YFFA20
15
8 7
0
MODULE CONFIGURATION (SIMCR)
FACTORY TEST (SIMTR)
CLOCK SYNTHESIZER CONTROL (SYNCR)
UNUSED
RESET STATUS REGISTER (RSR)
MODULE TEST E (SIMTRE)
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
PORTE DATA (PORTE0)
PORTE DATA (PORTE1)
PORTE DATA DIRECTION (DDRE)
PORTE PIN ASSIGNMENT (PEPAR)
PORTF DATA (PORTF0)
PORTF DATA (PORTF1)
PORTF DATA DIRECTION (DDRF)
PORTF PIN ASSIGNMENT (PFPAR)
SYSTEM PROTECTION CONTROL
(SYPCR)
YFFA22
YFFA24
YFFA26
YFFA28
YFFA2A
YFFA2C
YFFA2E
YFFA30
YFFA32
YFFA34
YFFA36
YFFA38
YFFA3A
YFFA3C
YFFA3E
YFFA40
YFFA42
YFFA44
YFFA46
YFFA48
YFFA4A
YFFA4C
YFFA4E
YFFA50
YFFA52
YFFA54
YFFA56
YFFA58
YFFA5A
YFFA5C
PERIODIC INTERRUPT CONTROL (PICR)
PERIODIC INTERRUPT TIMING (PITR)
UNUSED
SOFTWARE SERVICE (SWSR)
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
TEST MODULE MASTER SHIFT A (TSTMSRA)
TEST MODULE MASTER SHIFT B (TSTMSRB)
TEST MODULE SHIFT COUNT (TSTSC)
TEST MODULE REPETITION COUNTER (TSTRC)
TEST MODULE CONTROL (CREG)
TEST MODULE DISTRIBUTED REGISTER (DREG)
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
PORT C DATA (PORTC)
UNUSED
CHIP-SELECT PIN ASSIGNMENT (CSPAR0)
CHIP-SELECT PIN ASSIGNMENT (CSPAR1)
CHIP-SELECT BASE BOOT (CSBARBT)
CHIP-SELECT OPTION BOOT (CSORBT)
CHIP-SELECT BASE 0 (CSBAR0)
CHIP-SELECT OPTION 0 (CSOR0)
CHIP-SELECT BASE 1 (CSBAR1)
CHIP-SELECT OPTION 1 (CSOR1)
CHIP-SELECT BASE 2 (CSBAR2)
CHIP-SELECT OPTION 2 (CSOR2)
CHIP-SELECT BASE 3 (CSBAR3)
CHIP-SELECT OPTION 3 (CSOR3)
CHIP-SELECT BASE 4 (CSBAR4)
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
43
Table 10 SIM Address Map
Address
YFFA5E
YFFA60
YFFA62
YFFA64
YFFA66
YFFA68
YFFA6A
YFFA6C
YFFA6E
YFFA70
YFFA72
YFFA74
YFFA76
YFFA78
YFFA7A
YFFA7C
YFFA7E
15
8 7
0
CHIP-SELECT OPTION 4 (CSOR4)
CHIP-SELECT BASE 5 (CSBAR5)
CHIP-SELECT OPTION 5 (CSOR5)
CHIP-SELECT BASE 6 (CSBAR6)
CHIP-SELECT OPTION 6 (CSOR6)
CHIP-SELECT BASE 7 (CSBAR7)
CHIP-SELECT OPTION 7 (CSOR7)
CHIP-SELECT BASE 8 (CSBAR8)
CHIP-SELECT OPTION 8 (CSOR8)
CHIP-SELECT BASE 9 (CSBAR9)
CHIP-SELECT OPTION 9 (CSOR9)
CHIP-SELECT BASE 10 (CSBAR10)
CHIP-SELECT OPTION 10 (CSOR10)
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
Y = M111 where M is the logic state of the modmap (MM) bit in the SIMCR
MOTOROLA
44
MC68HC16Z1
MC68HC16Z1TS/D
3.1 System Configuration and Protection
This functional block provides configuration control for the entire MC68HC16Z1. It also performs inter-
rupt arbitration, bus monitoring, and system test functions.
MODULE CONFIGURATION
AND TEST
RESET STATUS
HALT OR
RESET REQUEST
HALT MONITOR
BERR
BUS MONITOR
SPURIOUS INTERRUPT MONITOR
SOFTWARE OR
RESET REQUEST
CLOCK
SOFTWARE WATCHDOG TIMER
9
2
PRESCALER
IRQ [7:1]
PERIODIC INTERRUPT TIMER
SYS PROTECT BLOCK
Figure 9 System Configuration and Protection Block Diagram
3.2 System Configuration
The SIM controls M68HC16 configuration during normal operation and during internal testing.
MCR — Module Configuration Register
$YFFA00
15
14
13
12
0
11
10
0
9
0
8
0
7
6
5
0
4
0
3
1
2
1
1
0
EXOFF
FRZSW
FRZBM
SLVEN
SHEN
SUPV
MM
IARB
RESET:
0
0
0
0
DB11
0
1
1
0
0
1
1
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
45
The module configuration register controls system configuration. It can be read or written at any time,
except for the module mapping (MM) bit, which can be written once and must remain set.
EXOFF — External Clock Off
0 = The CLKOUT pin is driven from an internal clock source.
1 = The CLKOUT pin is placed in a high-impedance state.
FRZSW — Freeze Software Enable
0 = When FREEZE is asserted, the software watchdog and periodic interrupt timer counters con-
tinue to run.
1 = When FREEZE is asserted, the software watchdog and periodic interrupt timer counters are dis-
abled, preventing interrupts during software debug.
FRZBM — Freeze Bus Monitor Enable
0 = When FREEZE is asserted, the bus monitor continues to operate.
1 = When FREEZE is asserted, the bus monitor is disabled.
SLVEN — Factory Test Mode Enabled
This bit is a read-only status bit that reflects the state of DB11 during reset.
0 = IMB is not available to an external master.
1 = An external bus master has direct access to the IMB.
SHEN[1:0] — Show Cycle Enable
This field determines what the EBI does with the external bus during internal transfer operations. A
show cycle allows internal transfers to be externally monitored. The table below shows whether show
cycle data is driven externally, and whether external bus arbitration can occur. To prevent bus conflict,
external peripherals must not be enabled during show cycles.
SHEN
00
Action
Show cycles disabled, external arbitration enabled
Show cycles enabled, external arbitration disabled
Show cycles enabled, external arbitration enabled
01
10
11
Show cycles enabled, external arbitration enabled,
internal activity is halted by a bus grant
SUPV — Supervisor/Unrestricted Data Space
The SUPV bit places the SIM global registers in either supervisor data space or user data space. The
CPU16 in the MC68HC16Z1 operates only in supervisory mode. SUPV has no effect.
MM — Module Mapping
0 = Internal modules are addressed from $7FF000 – $7FFFFF.
1 = Internal modules are addressed from $FFF000 – $FFFFFF.
IMB address lines ADDR[23:20] follow the logic state of ADDR19 unless externally driven. MM corre-
sponds to IMB ADDR23. If it is cleared, the SIM maps IMB modules into address space $7FF000 –
$7FFFFF, which is inaccessible to the CPU. Modules remain inaccessible until reset occurs. MM can
be written once. Initialization software should set MM to logic level 1.
IARB[3:0] — Interrupt Arbitration Field
Each module that can generate interrupt requests has an interrupt arbitration (IARB) field. Arbitration
between interrupt requests of the same priority is performed by serial contention between IARB field bit
values. Contention must take place whenever an interrupt request is acknowledged, even when there
is only a single pending request. An IARB field must have a non-zero value for contention to take place.
If an interrupt request from a module with an IARB field value of %0000 is recognized, the CPU16 pro-
cesses a spurious interrupt exception. Because the SIM routes external interrupt requests to the
CPU16, the SIM IARB field value is used for arbitration between internal and external interrupts of the
same priority. The reset value of IARB for the SIM is %1111 (highest priority), and the reset IARB value
for all other modules is %0000, which prevents SIM interrupts from being discarded during initialization.
MOTOROLA
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MC68HC16Z1
MC68HC16Z1TS/D
3.3 System Protection
MC68HC16Z1 system protection includes a bus monitor, a HALT monitor, a spurious interrupt monitor,
and a software watchdog timer. These functions have been made integral to the microcontroller to re-
duce the number of external components in a complete control system.
The system protection control register controls system monitor functions, software watchdog clock
prescaling, and bus monitor timing. In operating mode, this register can be written only once following
power-on or reset, but can be read at any time. In test mode, it can be written at any time.
SYPCR — System Protection Control Register
$YFFA21
7
SWE
RESET:
1
6
5
4
3
2
1
0
0
0
SWP
SWT
HME
BME
BMT
MODCLK
0
0
0
0
SWE — Software Watchdog Enable
0 = Software watchdog disabled
1 = Software watchdog enabled
SWP — Software Watchdog Prescale
This bit controls the value of the software watchdog prescaler.
0 = Software watchdog clock not prescaled
1 = Software watchdog clock prescaled by 512
SWT[1:0] — Software Watchdog Timing
This field selects the divide ratio used to establish software watchdog time-out period. The following ta-
ble gives the ratio for each combination of SWP and SWT bits.
SWP
SWT
Ratio
9
0
00
2
11
0
0
0
1
1
1
1
01
10
11
00
01
10
11
2
13
2
15
2
18
2
20
2
22
2
24
2
HME — Halt Monitor Enable
0 = Disable halt monitor function
1 = Enable halt monitor function
BME — Bus Monitor External Enable
0 = Disable bus monitor function for an internal to external bus cycle.
1 = Enable bus monitor function for an internal to external bus cycle.
BMT[1:0] — Bus Monitor Timing
This field selects a bus monitor time-out period as shown in the following table.
BMT
00
Bus Monitor Time-out Period
64 System Clocks (CLK)
32 System Clocks (CLK)
16 System Clocks (CLK)
8 System Clocks (CLK)
01
10
11
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
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3.3.1 Bus Monitor
The internal bus monitor checks for excessively long response times during normal bus cycles
(DSACKx) and during IACK cycles (AVEC). The monitor asserts BERR if response time is excessive.
DSACKx and AVEC response times are measured in clock cycles. The maximum allowable response
time can be selected by setting the BMT field.
The monitor does not check DSACKx response on the external bus unless the CPU16 initiates the bus
cycle. The BME bit in the SYPCR enables the internal bus monitor for internal to external bus cycles. If
a system contains external bus masters, an external bus monitor must be implemented and the internal
to external bus monitor option must be disabled.
3.3.2 Halt Monitor
The halt monitor responds to an assertion of HALT on the internal bus. A flag in the reset status register
(RSR) indicates that the last reset was caused by the halt monitor. The halt monitor reset can be inhib-
ited by the HME bit in the SYPCR.
3.3.3 Spurious Interrupt Monitor
The spurious interrupt monitor issues BERR if no interrupt arbitration occurs during IACK cycle.
3.3.4 Software Watchdog
SWSR — Software Service Register
$YFFA27
7
6
0
5
0
4
0
3
0
2
0
1
0
0
0
0
RESET:
0
0
0
0
0
0
0
0
Register shown with read value
The software watchdog is controlled by SWE in SYPCR. Once enabled, the watchdog requires that a
service sequence be written to SWSR on a periodic basis. If servicing does not take place, the watchdog
times out and issues a reset. This register can be written at any time, but returns zeros when read.
Perform a software watchdog service sequence as follows:
• Write $55 to SWSR.
• Write $AA to SWSR.
Both writes must occur before time-out in the order listed, but any number of instructions can be exe-
cuted between the two writes.
Watchdog clock rate is affected by SWP and SWT in SYPCR. When SWT[1:0] are modified, a watchdog
service sequence must be performed before the new time-out period takes effect.
The reset value of SWP is affected by the state of the MODCLK pin on the rising edge of reset, as shown
in the following table.
MODCLK
SWP
0
1
1
0
Software watchdog time-out period is given in the following equation:
Time-out Period = Divide Count/EXTAL Frequency
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MC68HC16Z1
MC68HC16Z1TS/D
3.4 System Clock
The system clock in the SIM provides timing signals for the IMB modules and for an external peripheral
bus. Because the MC68HC16Z1 is a fully static design, register and memory contents are not affected
when clock rate changes. System hardware and software support changes in clock rate during opera-
tion.
The system clock signal can be generated in three ways. An internal phase-locked loop can synthesize
the clock from an internal frequency source, an external frequency source, or the clock signal can be
input from an external source.
Following is a block diagram of the clock submodule.
V
DDSYN
1
0.1µF
.01µF
2
2
XFC
22 pF
22 pF
330 k
10M
V
V
0.1µF
SSI
SSI
V
SSI
V
EXTAL
XTAL
XFC PIN
DDSYN
CRYSTAL
OSCILLATOR
PHASE
COMPARATOR
LOW-PASS
FILTER
VCO
W
Y
FEEDBACK DIVIDER
CLKOUT
X
SYSTEM CLOCK CONTROL
SYSTEM
CLOCK
1. Must be low-leakage capacitor (insulation resistance 30,000 MΩ or greater).
2. Capacitance based on a test circuit constructed with a DAISHINKU DMX-38 32.768-kHz crystal.
SYS CLOCK
BLOCK 32KHZ
Figure 10 System Clock Block Diagram
3.4.1 Clock Sources
The state of the clock mode (MODCLK) pin during reset determines clock source. When MODCLK is
held high during reset, the clock synthesizer generates a clock signal from either a crystal oscillator or
an external reference input. Clock synthesizer control register SYNCR determines operating frequency
and various modes of operation. When MODCLK is held low during reset, the clock synthesizer is dis-
abled, and an external system clock signal must be applied. When the synthesizer is disabled, SYNCR
control bits have no effect.
A reference crystal must be connected between the EXTAL and XTAL pins in order to use the internal
oscillator. A 32.768-kHz watch crystal is recommended — these crystals are readily available and inex-
pensive. MC68HC16Z1 clock synthesizer specifications are based upon a typical 32.768-kHz crystal.
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
49
If an external reference signal or an external system clock signal is applied through the EXTAL pin, the
XTAL pin must be left floating. External reference signal frequency must be less than or equal to max-
imum specified reference frequency. External system clock signal frequency must be less than or equal
to maximum specified system clock frequency.
When an external system clock signal is applied (PLL not used), duty cycle of the input is critical, espe-
cially at near maximum operating frequencies. The relationship between clock signal duty cycle and
clock signal period is expressed:
Minimum external clock period =
minimum external clock high/low time
50% – percentage variation of external clock input duty cycle
3.4.2 Clock Synthesizer Operation
A voltage controlled oscillator (VCO) generates the system clock signal. A portion of the clock signal is
fed back to a divider/counter. The divider controls the frequency of one input to a phase comparator.
The other phase comparator input is a reference signal, either from the internal oscillator or from an
external source. The comparator generates a control signal proportional to the difference in phase be-
tween its two inputs. The signal is low-pass filtered and used to correct VCO output frequency.
The synthesizer locks when VCO frequency is identical to reference frequency. Lock time is affected by
the filter time constant and by the amount of difference between the two comparator inputs. Whenever
comparator input changes, the synthesizer must re-lock. Lock status is shown by the SLOCK bit in SYN-
CR.
The MC68HC16Z1 does not come out of reset state until the synthesizer locks. Crystal type, character-
istic frequency, and layout of external oscillator circuitry affect lock time.
The low-pass filter requires an external low-leakage capacitor, typically 0.1 µF, connected between the
XFC and V
pins.
DDSYN
V
is used to power the clock circuits. A separate power source increases MCU noise immunity
DDSYN
and can be used to run the clock when the MCU is powered down. Use a quiet power supply as the
source, since PLL stability depends on the VCO, which uses this supply. Place adequate ex-
V
DDSYN
ternal bypass capacitors as close as possible to the V
pin to ensure stable operating frequency.
DDSYN
When the clock synthesizer is used, control register SYNCR determines operating frequency and vari-
ous modes of operation. Because the CPU16 in the MC68HC16Z1 operates only in supervisor mode,
SYNCR can be read or written at any time.
The SYNCR X bit controls a divide by two prescaler that is not in the synthesizer feedback loop. Setting
X doubles clock speed without changing VCO speed. There is no VCO relock delay. The SYNCR W bit
controls a 3-bit prescaler in the feedback divider. Setting W increases VCO speed by a factor of four.
The SYNCR Y field determines the count modulus for a modulo 64 down counter, causing it to divide
by a value of Y + 1. When either W or Y value changes, there is a VCO relock delay.
Clock frequency is determined by SYNCR bit settings as follows:
2W + X
F
= F
[4(Y + 1)(2
)]
SYSTEM
REFERENCE
In order for the device to perform correctly, the clock frequency selected by the W, X, and Y bits must
be within the limits specified for the MCU.
VCO frequency is determined by:
F
= F
(2 – X)
VCO
SYSTEM
The reset state of SYNCR ($3F00) produces a modulus-64 count — system frequency is 256 times ref-
erence frequency.
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MC68HC16Z1
MC68HC16Z1TS/D
3.4.3 Clock Control
The clock control circuits determine system clock frequency and clock operation under special circum-
stances, such as loss of synthesizer reference or low-power mode. Clock source is determined by the
logic state of the MODCLK pin during reset.
SYNCR — Clock Synthesizer Control Register
$YFFA04
15
W
14
X
13
12
11
10
9
8
7
6
0
5
0
4
3
2
1
0
Y
EDIV
SLIMP SLOCK
RSTEN STSIM STEXT
RESET:
0
0
1
1
1
1
1
1
0
0
0
U
U
0
0
0
When the on-chip clock synthesizer is used, system clock frequency is controlled by the bits in the upper
byte of SYNCR. Bits in the lower byte show status of or control operation of internal and external clocks.
Because the CPU16 always operates in supervisor mode, SYNCR can be read or written at any time.
W — Frequency Control (VCO)
This bit controls a prescaler tap in the synthesizer feedback loop. Setting the bit increases the VCO
speed by a factor of four. VCO relock delay is required.
X — Frequency Control Bit (Prescale)
This bit controls a divide by two prescaler that is not in the synthesizer feedback loop. Setting the bit
doubles clock speed without changing the VCO speed. There is no VCO relock delay.
Y[5:0] — Frequency Control (Counter)
The Y field controls the modulus down counter in the synthesizer feedback loop, causing it to divide by
a value of Y + 1. Values range from 0 to 63. VCO relock delay is required.
EDIV — E Clock Divide Rate
0 = ECLK frequency is system clock divided by 8.
1 = ECLK frequency is system clock divided by 16.
ECLK is an external M6800 bus clock available on pin ADDR23. Refer to 3.5.13 Chip Selects for more
information.
SLIMP — Limp Mode Flag
0 = External crystal is VCO reference.
1 = Loss of crystal reference.
When the on-chip synthesizer is used, loss of reference frequency causes SLIMP to be set. The VCO
continues to run using the base control voltage. Maximum limp frequency is maximum specified system
clock frequency. X-bit state affects limp frequency.
SLOCK — Synthesizer Lock Flag
0 = VCO is enabled, but has not locked.
1 = VCO has locked on the desired frequency (or system clock is external).
The MCU maintains reset state until the synthesizer locks, but SLOCK does not indicate synthesizer
lock status until after the user writes to SYNCR.
RSTEN — Reset Enable
0 = Loss of crystal causes the MCU to operate in limp mode.
1 = Loss of crystal causes system reset.
STSIM — Stop Mode System Integration Clock
0 = When LPSTOP is executed, the SIM clock is driven from the crystal oscillator and the VCO is
turned off to conserve power.
1 = When LPSTOP is executed, the SIM clock is driven from the VCO.
STEXT — Stop Mode External Clock
0 = When LPSTOP is executed, the CLKOUT signal is held negated to conserve power.
1 = When LPSTOP is executed, the CLKOUT signal is driven from the SIM clock, as determined by
the state of the STSIM bit.
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
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3.4.4 Periodic Interrupt Timer
The periodic interrupt timer (PIT) generates interrupts of specified priorities at specified intervals. Timing
for the PIT is provided by a programmable prescaler driven by the system clock.
PICR — Periodic Interrupt Control Register
$YFFA22
15
0
14
0
13
0
12
0
11
0
10
9
8
0
7
0
6
0
5
0
4
0
3
1
2
1
1
0
PIRQL
PIV
RESET:
0
0
0
0
0
0
0
1
1
This register contains information concerning periodic interrupt priority and vectoring. Bits [10:0] can be
read or written at any time. Bits [15:11] are unimplemented and always return zero.
PIRQL[2:0] — Periodic Interrupt Request Level
The following table shows what interrupt request level is asserted when a periodic interrupt is generat-
ed. If a PIT interrupt and an external IRQ of the same priority occur simultaneously, the PIT interrupt is
serviced first. The periodic timer continues to run when the interrupt is disabled.
PIRQL
000
001
010
011
100
101
110
111
Interrupt Request Level
Periodic Interrupt Disabled
Interrupt Request Level 1
Interrupt Request Level 2
Interrupt Request Level 3
Interrupt Request Level 4
Interrupt Request Level 5
Interrupt Request Level 6
Interrupt Request Level 7
PIV[7:0] — Periodic Interrupt Vector
The bits of this field contain the vector generated in response to an interrupt from the periodic timer.
When the SIM responds, the periodic interrupt vector is placed on the bus.
PITR — Periodic Interrupt Timer Register
$YFFA24
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
7
6
5
4
3
2
1
0
PTP
PITM
RESET:
0
0
0
0
0
0
0
MODCLK
0
0
0
0
0
0
0
0
PITR contains the count value for the periodic timer. A zero value turns off the periodic timer. This reg-
ister can be read or written at any time.
PTP — Periodic Timer Prescaler Control
1 = Periodic timer clock prescaled by a value of 512
0 = Periodic timer clock not prescaled
The reset state of PTP is the complement of the state of the MODCLK signal during reset.
PITM[7:0] — Periodic Interrupt Timing Modulus Field
This is an 8-bit timing modulus. The period of the timer can be calculated as follows:
PIT Period = [(PITM)(Prescaler)(4)]/EXTAL
where
PIT Period = Periodic interrupt timer period
PITM = Periodic interrupt timer register modulus (PITR[7:0])
EXTAL = Crystal frequency
Prescaler = 512 or 1 depending on the state of the PTP bit in the PITR
MOTOROLA
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MC68HC16Z1
MC68HC16Z1TS/D
3.5 External Bus Interface
The external bus interface (EBI) transfers information between the internal MCU bus and external de-
vices when the MC68HC16Z1 is operating in expanded modes. In fully expanded mode, the external
bus has 24 address lines and 16 data lines. In partially expanded mode, the external bus has 24 ad-
dress lines and 8 data lines. Because the CPU16 in the MC68HC16Z1 drives only 20 of the 24 IMB
address lines, ADDR[23:20] follow the output state of ADDR19.
The EBI provides dynamic sizing between 8-bit and 16-bit data accesses. It supports byte, word, and
long-word transfers. Ports are accessed through the use of asynchronous cycles controlled by the data
transfer (SIZ1 and SIZ0) and data size acknowledge pins (DSACK1 and DSACK0). In fully expanded
mode, both 8-bit and 16-bit data ports can be accessed; in partially expanded mode, only 8-bit ports
can be accessed. Multiple bus cycles may be required for a transfer to an 8-bit port.
Port width is the maximum number of bits accepted or provided during a bus transfer. External devices
must follow the handshake protocol described below. Control signals indicate the beginning of the cycle,
the address space, the size of the transfer, and the type of cycle. The selected device controls the length
of the cycle. Strobe signals, one for the address bus and another for the data bus, indicate the validity
of an address and provide timing information for data. The EBI operates in an asynchronous mode for
any port width.
To add flexibility and minimize the necessity for external logic, MCU chip select logic can be synchro-
nized with EBI transfers. Chip select logic can also provide internally-generated bus control signals for
these accesses. Refer to 3.5.13 Chip Selects for more information.
3.5.1 Bus Control Signals
The CPU initiates a bus cycle by driving the address, size, function code, and read/write outputs. At the
beginning of the cycle, size signals SIZ0 and SIZ1 are driven along with the function code signals. The
size signals indicate the number of bytes remaining to be transferred during an operand cycle. They are
valid while the address strobe (AS) is asserted. The following table shows SIZ0 and SIZ1 encoding. The
read/write (R/W) signal determines the direction of the transfer during a bus cycle. This signal changes
state, when required, at the beginning of a bus cycle, and is valid while AS is asserted. R/W only tran-
sitions when a write cycle is preceded by a read cycle or vice versa. The signal can remain low for two
consecutive write cycles.
Table 11 Size Signal Encoding
SIZ1
SIZ0
Transfer Size
Byte
0
1
1
0
1
0
1
0
Word
3 Byte
Long Word
3.5.2 Function Codes
Function code signals FC[2:0] are automatically generated by the CPU16. The function codes can be
considered address extensions that automatically select one of eight address spaces to which an ad-
dress applies. These spaces are designated as either user or supervisor, and program or data spaces.
Because the CPU16 always operates in supervisor mode (FC2 always = 1), address spaces 0 to 3 are
not used. Address space 7 is designated CPU space. CPU space is used for control information not
normally associated with read or write bus cycles. Function codes are valid while AS is asserted.
Table 12 CPU16 Address Space Encoding
FC2
1
FC1
0
FC0
0
Address Space
Reserved
1
0
1
Data Space
1
1
0
Program Space
CPU Space
1
1
1
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
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3.5.3 Address Bus
Address bus signals ADDR[19:0] define the address of the most significant byte to be transferred during
a bus cycle. The MCU places the address on the bus at the beginning of a bus cycle. The address is
valid while AS is asserted. Because the CPU16 in the MC68HC16Z1 does not drive ADDR[23:20],
these lines follow the logic state of ADDR19.
3.5.4 Address Strobe
AS is a timing signal that indicates the validity of an address on the address bus and the validity of many
control signals. It is asserted one-half clock after the beginning of a bus cycle.
3.5.5 Data Bus
Data bus signals DATA[15:0] comprise a bidirectional, non-multiplexed parallel bus that transfers data
to or from the MCU. A read or write operation can transfer 8 or 16 bits of data in one bus cycle. During
a read cycle, the data is latched by the MCU on the last falling edge of the clock for that bus cycle. For
a write cycle, all 16 bits of the data bus are driven, regardless of the port width or operand size. The
MCU places the data on the data bus one-half clock cycle after AS is asserted in a write cycle.
3.5.6 Data Strobe
Data strobe (DS) is a timing signal. For a read cycle, the MCU asserts DS to signal an external device
to place data on the bus. DS is asserted at the same time as AS during a read cycle. For a write cycle,
DS signals an external device that data on the bus is valid. The MCU asserts DS one full clock cycle
after the assertion of AS during a write cycle.
3.5.7 Bus Cycle Termination Signals
During bus cycles, external devices assert the data transfer and size acknowledge signals (DSACK1
and DSACK0). During a read cycle, the signals tell the MCU to terminate the bus cycle and to latch data.
During a write cycle, the signals indicate that an external device has successfully stored data and that
the cycle can end. These signals also indicate to the MCU the size of the port for the bus cycle just com-
pleted. (Refer to the discussion of dynamic bus sizing.)
The bus error (BERR) signal is also a bus cycle termination indicator and can be used in the absence
of DSACK1 and DSACK0 to indicate a bus error condition. It can also be asserted in conjunction with
these signals, provided it meets the appropriate timing requirements. The internal bus monitor can be
used to generate the BERR signal for internal and internal-to-external transfers. When BERR and HALT
are asserted simultaneously, the CPU16 takes a bus error exception.
Autovector signal (AVEC) can terminate external IRQ pin interrupt acknowledge cycles. AVEC indicates
that the MCU will internally generate a vector number to locate an interrupt handler routine. If it is con-
tinuously asserted, autovectors will be generated for all external interrupt requests. AVEC is ignored
during all other bus cycles.
3.5.8 Data Transfer Mechanism
The MCU architecture supports byte, word, and long-word operands, allowing access to 8- and 16-bit
data ports through the use of asynchronous cycles controlled by the data transfer and size acknowledge
inputs (DSACK1and DSACK0).
3.5.9 Dynamic Bus Sizing
The MCU dynamically interprets the port size of the addressed device during each bus cycle, allowing
operand transfers to or from 8- and 16-bit ports. During an operand transfer cycle, the slave device sig-
nals its port size and indicates completion of the bus cycle to the MCU through the use of the DSACK0
and DSACK1 inputs, as shown in the following table.
MOTOROLA
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MC68HC16Z1
MC68HC16Z1TS/D
Table 13 Effect of DSACK Signals
DSACK1
DSACK0
Result
Insert Wait States in Current Bus Cycle
Complete Cycle — Data Bus Port Size is 8 Bits
Complete Cycle — Data Bus Port Size is 16 Bits
Reserved
1
1
0
0
1
0
1
0
For example, if the MCU is executing an instruction that reads a long-word operand from a 16-bit port,
the MCU latches the 16 bits of valid data and then runs another bus cycle to obtain the other 16 bits.
The operation for an 8-bit port is similar, but requires four read cycles. The addressed device uses the
DSACK0 and DSACK1 signals to indicate the port width. For instance, a 16-bit device always returns
DSACK0 = 1 and DSACK1 = 0 for a 16-bit port, regardless of whether the bus cycle is a byte or word
operation.
Dynamic bus sizing requires that the portion of the data bus used for a transfer to or from a particular
port size be fixed. A 16-bit port must reside on data bus bits [15:0] and an 8-bit port must reside on data
bus bits [15:8]. This minimizes the number of bus cycles needed to transfer data and ensures that the
MCU transfers valid data.
The MCU always attempts to transfer the maximum amount of data on all bus cycles. For a word oper-
ation, it is assumed that the port is 16 bits wide when the bus cycle begins. Operand bytes are desig-
nated as shown in the following figure. OP0 is the most significant byte of a long-word operand, and
OP3 is the least significant byte. The two bytes of a word-length operand are OP0 (most significant) and
OP1. The single byte of a byte-length operand is OP0.
Operand
Byte Order
31
24
23
16
15
8
7
0
Long Word
Three Byte
Word
OP0
OP1
OP0
OP2
OP1
OP0
OP3
OP2
OP1
OP0
Byte
Figure 11 Operand Byte Order
3.5.10 Operand Alignment
The data multiplexer establishes the necessary connections for different combinations of address and
data sizes. The multiplexer takes the two bytes of the 16-bit bus and routes them to their required po-
sitions. Positioning of bytes is determined by the size and address outputs. SIZ1 and SIZ0 indicate the
remaining number of bytes to be transferred during the current bus cycle. The number of bytes trans-
ferred is equal to or less than the size indicated by SIZ1 and SIZ0, depending on port width.
ADDR0 also affects the operation of the data multiplexer. During an operand transfer, ADDR[23:1] in-
dicate the word base address of the portion of the operand to be accessed, and ADDR0 indicates the
byte offset from the base. Bear in mind the fact that ADDR[23:20] follow the state of ADDR19 in the
MC68HC16Z1.
3.5.11 Misaligned Operands
CPU16 processor architecture uses a basic operand size of 16 bits. An operand is misaligned when it
overlaps a word boundary. This is determined by the value of ADDR0. When ADDR0 = 0 (an even ad-
dress), the address is on a word and byte boundary. When ADDR0 = 1 (an odd address), the address
is on a byte boundary only. A byte operand is aligned at any address; a word or long-word operand is
misaligned at an odd address.
MC68HC16Z1
MC68HC16Z1TS/D
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In the MC68HC16Z1, the largest amount of data that can be transferred by a single bus cycle is an
aligned word. If the MCU transfers a long-word operand via a 16-bit port, the most significant operand
word is transferred on the first bus cycle and the least significant operand word on a following bus cycle.
The CPU16 can perform misaligned word transfers. This capability makes it software compatible with
the MC68HC11 CPU. The CPU16 treats misaligned long-word transfers as two misaligned word trans-
fers.
3.5.12 Operand Transfer Cases
The following table summarizes how operands are aligned for various types of transfers. OPn entries
are portions of a requested operand that are read or written during a bus cycle and are defined by SIZ1,
SIZ0, and ADDR0 for that bus cycle.
Table 14 Operand Alignment
Transfer Case
SIZ1 SIZ0 ADDR0 DSACK1 DSACK0 DATA DATA
[15:8]
[7:0]
(OP0)
(OP0)
OP0
Byte to 8-Bit Port
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
X
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
0
X
X
0
OP0
Byte to 16-Bit Port (Even)
OP0
Byte to 16-Bit Port (Odd)
(OP0)
OP0
Word to 8-Bit Port (Aligned)
Word to 8-Bit Port (Misaligned)
Word to 16-Bit Port (Aligned)
Word to 16-Bit Port (Misaligned)
(OP1)
(OP0)
OP1
0
OP0
X
X
0
OP0
(OP0)
OP0
OP0
2
(OP1)
3 Byte to 8-Bit Port (Aligned)
2
1
1
1
1
1
1
1
0
1
1
0
0
0
X
X
OP0
OP0
(OP0)
OP1
3 Byte to 8-Bit Port (Misaligned)
3
3 Byte to 16-Bit Port (Aligned)
2
(OP0)
OP0
3 Byte to 16-Bit Port (Misaligned)
Long Word to 8-Bit Port (Aligned)
0
1
0
0
0
1
1
1
0
0
OP0
OP0
(OP1)
(OP0)
3
Long Word to 8-Bit Port (Misaligned)
Long Word to 16-Bit Port (Aligned)
0
1
0
0
0
1
0
0
X
X
OP0
OP1
OP0
3
(OP0)
Long Word to 16-Bit Port (Misaligned)
NOTES:
1. Operands in parentheses are ignored by the CPU16 during read cycles.
2. Three-byte transfer cases occur only as a result of a long word to byte transfer.
3. The CPU16 treats misaligned long-word transfers as two misaligned word transfers.
3.5.13 Chip Selects
Typical microcontrollers require additional hardware to provide external chip select signals. Twelve in-
dependently programmable chip selects provide fast two-cycle access to external memory or peripher-
als. Address block sizes of two Kbytes to one Mbyte can be selected. However, because ADDR[23:20]
= ADDR19 in the CPU16, 512-Kbyte blocks are the largest usable size.
Chip select assertion can be synchronized with bus control signals to provide output enable, read/write
strobes, or interrupt acknowledge signals. Logic can also generate DSACK signals internally. A single
DSACK generator is shared by all circuits. Multiple chip selects assigned to the same address and con-
trol must have the same number of wait states.
Chip selects can also be synchronized with the ECLK signal available on ADDR23.
When a memory access occurs, chip select logic compares address space type, address, type of ac-
cess, transfer size, and interrupt priority (in the case of interrupt acknowledge) to parameters stored in
chip select registers. If all parameters match, the appropriate chip select signal is asserted. Select sig-
nals are active low. Refer to the following block diagram of a single chip-select circuit.
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MC68HC16Z1
MC68HC16Z1TS/D
1 OF 12
INTERNAL
SIGNALS
BASE ADDRESS REGISTER
ADDRESS COMPARATOR
OPTION COMPARE
ADDRESS
TIMING
AND
CONTROL
PIN
BUS CONTROL
OPTION REGISTER
PIN
ASSIGNMENT
REGISTER
PIN
DATA
REGISTER
AVEC
GENERATOR
DSACK
GENERATOR
AVEC
DSACK
CHIP SEL BLOCK
Figure 12 Chip-Select Circuit Block Diagram
Because initialization software usually resides in a peripheral memory device controlled by the chip-se-
lect circuits, a CSBOOT register provides default reset values to support bootstrap operation.
If a chip select function is given the same address as a microcontroller module or memory array, an
access to that address goes to the module or array and the chip select signal is not asserted.
Each chip select pin can have two or more functions. Chip select configuration out of reset is determined
by operating mode. In all modes, the boot ROM select signal is automatically asserted out of reset. In
single-chip mode, all chip select pins except CS10 and CS0 are configured for alternate functions or
discrete output. In expanded modes, appropriate pins are configured for chip select operation, but chip
select signals cannot be asserted until a transfer size is chosen. In fully expanded mode, data bus pins
can be held low to enable alternate functions for chip select pins.
The following table lists allocation of chip-selects and discrete outputs on the pins of the MCU.
Pin
CSBOOT
BR
Chip Select
CSBOOT
CS0
Discrete Outputs
—
—
BG
CS1
—
BGACK
FC0
CS2
—
CS3
PC0
PC1
PC2
PC3
PC4
PC5
PC6
ECLK
FC1
CS4
FC2
CS5
ADDR19
ADDR20
ADDR21
ADDR22
ADDR23
CS6
CS7
CS8
CS9
CS10
MC68HC16Z1
MC68HC16Z1TS/D
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3.5.13.1 Chip-Select Registers
Pin assignment registers (CSPAR) determine functions of chip select pins. Pin assignment registers
also determine port size (8- or 16-bit) for dynamic bus allocation.
A pin data register (PORTC) latches discrete output data.
Blocks of addresses are assigned to each chip select function. Block sizes of 2 Kbytes to 1 Mbyte can
be selected by writing values to the appropriate base address register (CSBAR). However, because the
logic state of ADDR20 is always the same as the state of ADDR19 in the MC68HC16Z1, the largest
usable block size is 512 Kbytes. Address blocks for separate chip select functions can overlap.
Chip select option registers (CSOR) determine timing of and conditions for assertion of chip select sig-
nals. Eight parameters, including operating mode, access size, synchronization, and wait state insertion
can be specified.
Initialization code often resides in a peripheral memory device controlled by the chip select circuits. A
set of special chip select functions and registers (CSORBT, CSBARBT) is provided to support bootstrap
operation.
3.5.13.2 Pin Assignment Registers
The pin assignment registers contain pairs of bits that determine the function of pins in other chip-select
registers. Alternate functions of the associated pins are shown in parentheses.
CSPAR0 — Chip-Select Pin Assignment Register 0
$YFFA44
15
0
14
0
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CS5 (FC2)
CS4 (FC1)
CS3 (FC0)
CS2 (BGACK)
CS1 (BG)
CS0 (BR)
CSBOOT
RESET:
0
0
DB2
1
DB2
1
DB2
1
DB1
1
6
DB1
1
DB1
1
1
DB0
Bits [15:14] — Not Used
These bits always read zero; write has no effect.
CSPAR1 — Chip-Select Pin Assignment Register 1
$YFFA46
15
0
14
0
13
0
12
0
11
0
10
0
9
8
7
5
4
3
2
1
0
CS10
(ADDR23)
CS9
(ADDR22)
CS8
(ADDR21)
CS7
(ADDR20)
CS6
(ADDR19)
RESET:
0
0
0
0
0
0
DB7
1
DB6
1
DB5
1
DB4
1
DB3
1
Bits [15:10] — Not Used
These bits always read zero; write has no effect.
The following table shows pin assignment register encoding.
Bit Pair
00
Description
Discrete Output
Default Function
01
10
Chip Select (8-Bit Port)
Chip Select (16-Bit Port)
11
A pin programmed as a discrete output drives an external signal to the value specified in the port C data
register (PORTC), with the following exceptions:
1. No discrete output function is available on pins BR, BG, or BGACK.
2. ADDR23 provides the ECLK output rather than a discrete output signal.
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MC68HC16Z1
MC68HC16Z1TS/D
When a pin is programmed for discrete output or default function, internal chip-select logic still functions
and can be used to generate DSACK or AVEC internally on an address match.
Port size is determined when a pin is assigned as a chip select. When a pin is assigned to an 8-bit port,
the chip select is asserted at all addresses within the block range. If a pin is assigned to a 16-bit port,
the upper/lower byte field of the option register selects the byte with which the chip select is associated.
The notation DB# in a CSPAR reset block indicates that a bit goes to the logic level of that data bus pin
on reset. Either default function (01) or chip-select function (11) can be encoded. Because of internal
pull-up, DB pins are driven to logic level one by a weak pull-up during reset. Encoding is for chip-select
function unless a data line is held low during reset. Note that bus loading can overcome the weak pull-
up, and hold pins low during reset. Because ADDR[23:20] follow the state of ADDR19 in the CPU16,
DB[7:4] have limited use.
3.5.13.3 Base Address Registers
A base address is the starting address for the block enabled by a given chip select. Block size deter-
mines the extent of the block above the base address. Each chip select has an associated base register
so that an efficient address map can be constructed for each application.
CSBARBT — Chip-Select Base Address Register Boot ROM
$YFFA48
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1
0
ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR
BLKSZ
23*
RESET:
0
22*
0
21*
0
20*
0
19
0
18
0
17
0
16
0
15
0
14
0
13
0
12
0
11
0
1
1
CSBAR[10:0] — Chip-Select Base Address Registers
$YFFA4C–$YFFA74
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADDR
23*
ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR
BLKSZ
22*
21*
20*
19
18
17
16
15
14
13
12
11
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
*ADDR[23:20] follow the state of ADDR19 in the MC68HC16Z1. ADDR[23:20] must match ADDR19 for the chip
select to be active.
BLKSZ — Block Size Field
This field determines the size of the block that must be enabled by the chip select. The following table
shows bit encoding for the base address registers block size field.
Block Size Field
Block Size
2 K
Address Lines Compared
ADDR[23:11]
000
001
010
011
100
101
110
111
8 K
ADDR[23:13]
16 K
ADDR[23:14]
64 K
ADDR[23:16]
128 K
256 K
512 K
512 K
ADDR[23:17]
ADDR[23:18]
ADDR[23:19]
ADDR[23:20]
ADDR[23:20] is at the same logic level as ADDR19 during normal operation.
MC68HC16Z1
MC68HC16Z1TS/D
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ADDR[15:3] — Base Address Field
This field sets the starting address of a particular address space. The address compare logic uses only
the most significant bits to match an address within a block. The value of the base address must be a
multiple of block size. Base address register diagrams show how base register bits correspond to ad-
dress lines.
Because ADDR20 = ADDR19 in the CPU16, maximum block size is 512 Kbytes. Because ADDR[23:20]
follow the logic state of ADDR19, addresses from $080000 to $F7FFFF are inaccessible. Blocks can
be based above this dead zone, but the effect of ADDR19 must be considered.
3.5.13.4 Option Registers
The option registers contain eight fields that determine timing of and conditions for assertion of chip-
select signals and make the chip selects useful for generating peripheral control signals. All bits in the
base address register and the option register must be satisfied to assert a chip-select signal. The bits
must also be satisfied to provide DSACK or autovector support.
CSORBT — Chip-Select Option Register Boot ROM
$YFFA4A
15
14
13
12
11
10
9
8
7
0
6
1
5
1
4
1
3
0
2
1
0
MODE
BYTE
R/W
STRB
DSACK
SPACE
IPL
AVEC
RESET:
0
1
1
1
1
0
1
1
0
0
0
CSOR[10:0] — Chip-Select Option Registers
$YFFA4E–$YFFA76
15
14
13
12
11
10
9
8
0
7
6
0
5
0
4
0
3
0
2
1
0
MODE
BYTE
R/W
STRB
DSACK
SPACE
IPL
AVEC
RESET:
0
0
0
0
0
0
0
0
0
0
0
The option register for CSBOOT, which is CSORBT, contains special reset values that support boot-
strap operations from peripheral memory devices.
The following bit descriptions apply to both CSORBT and CSOR[10:0] option registers.
MODE — Asynchronous/Synchronous Mode
0 = Asynchronous mode selected (chip select assertion determined by internal or external bus con-
trol signals)
1 = Synchronous mode selected (chip select assertion synchronized with ECLK signal)
In asynchronous mode, the chip select is asserted synchronized with AS or DS.
BYTE — Upper/Lower Byte Option
This field is used only when the chip-select 16-bit port option is selected in the pin assignment register.
The following table lists upper/lower byte options.
Byte
00
Description
Disable
01
Lower Byte
Upper Byte
Both Bytes
10
11
If an interrupting device does not provide a vector number, an autovector acknowledge must be gener-
ated. The bus cycle is terminated by asserting AVEC. This can be done either by asserting the AVEC
pin or by generating AVEC internally, using the chip select option register.
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MC68HC16Z1
MC68HC16Z1TS/D
R/W — Read/Write
This field causes a chip select to be asserted only for a read, only for a write, or for both read and write.
Refer to the following table for options available.
R/W
00
Description
Reserved
01
Read Only
Write Only
Read/Write
10
11
STRB — Address Strobe/Data Strobe
1 = Data strobe
0 = Address strobe
This bit controls the timing for assertion of a chip select in asynchronous mode. Selecting address
strobe causes chip select to be asserted synchronized with address strobe. Selecting data strobe caus-
es chip select to be asserted synchronized with data strobe.
DSACK — Data Strobe Acknowledge
This field specifies the source of DSACK in asynchronous mode. It also allows the user to adjust bus
timing with internal DSACK generation by controlling the number of wait states that are inserted to op-
timize bus speed in a particular application. The following table shows the DSACK field encoding. The
fast termination encoding (1110) is used for two-cycle access to external memory.
The DSACK field is not used in synchronous mode because a bus cycle is only performed as a syn-
chronous operation. When a match condition occurs on a chip select programmed for synchronous op-
eration, the chip select signals the EBI that an E-clock cycle is pending.
DSACK
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Description
No Wait States
1 Wait State
2 Wait States
3 Wait States
4 Wait States
5 Wait States
6 Wait States
7 Wait States
8 Wait States
9 Wait States
10 Wait States
11 Wait States
12 Wait States
13 Wait States
Fast Termination
External DSACK
SPACE — Address Space
Use this option field to select an address space for the chip-select logic. The CPU16 normally operates
in supervisor space, but interrupt acknowledge must take place in CPU space.
Space Field
Address Space
CPU Space
00
01
10
11
User Space
Supervisor Space
Supervisor/User Space
MC68HC16Z1
MC68HC16Z1TS/D
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IPL — Interrupt Priority Level
If the space field is set for CPU space (00), chip-select logic can be used for interrupt acknowledge.
During an IACK cycle, the priority level on address lines ADDR[3:1] is compared to the value in the IPL
field. If the values are the same, a chip select can be asserted, provided that other option register con-
ditions are met. The following table shows IPL field encoding.
IPL
000
001
010
011
100
101
110
111
Description
Any Level
IPL1
IPL2
IPL3
IPL4
IPL5
IPL6
IPL7
This field only affects the response of chip selects and does not affect interrupt recognition by the CPU.
Any level means that chip select is asserted regardless of the level of the IACK cycle.
AVEC — Autovector Enable
1 = Autovector enabled
0 = External interrupt vector enabled
This field selects one of two methods of acquiring an interrupt vector during the IACK cycle. It is not
usually used in conjunction with a chip-select pin. If the chip select is configured to trigger on an IACK
cycle (SPACE = 00) and the AVEC field is set to one, the chip select automatically generates an AVEC
in response to the IACK cycle. Otherwise, the vector must be supplied by the requesting device.
The AVEC bit must not be used in synchronous mode, as autovector response timing can vary because
of ECLK synchronization.
PORTC — Port C Data Register
$YFFA41
7
6
5
4
3
2
1
0
0
RESET:
0
PC6
PC5
PC4
PC3
PC2
PC1
PC0
1
1
1
1
1
1
1
The data register controls the state of pins programmed as discrete outputs. When a pin is assigned as
a discrete output, the value in this register appears at the output. PC[6:0] correspond to CS[9:3]. This
is a read/write register. Bit 7 is not used. Writing to this bit has no effect; it always reads zero.
3.5.14 General-Purpose Input/Output
SIM pins can be configured as two general-purpose I/O ports, E and F. The following paragraphs de-
scribe registers that control the ports.
PORTE — Port E Data Register
$YFFA11, $YFFA13
7
PE7
RESET:
U
6
5
4
3
2
1
0
PE6
PE5
PE4
PE3
PE2
PE1
PE0
U
U
U
U
U
U
U
A write to the port E data register is stored in the internal data latch and, if any port E pin is configured
as an output, the value stored for that bit is driven on the pin. A read of the port E data register (PORTE)
returns the value at the pin only if the pin is configured as a discrete input. Otherwise, the value read is
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MC68HC16Z1
MC68HC16Z1TS/D
the value stored in the register. Port E is a single register that can be accessed in two locations. It can
be read or written at any time.
DDRE — Port E Data Direction Register
$YFFA15
7
DDE7
RESET:
0
6
5
4
3
2
1
0
DDE6
DDE5
DDE4
DDE3
DDE2
DDE1
DDE0
0
0
0
0
0
0
0
The bits in this register control the direction of the pin drivers when the pins are configured as I/O. Any
bit in this register set to one configures the corresponding pin as an output. Any bit in this register
cleared to zero configures the corresponding pin as an input.This register can be read or written at any
time.
PEPAR — Port E Pin Assignment Register
$YFFA17
7
6
5
4
3
2
1
0
PEPA7
(SIZ1)
PEPA6
(SIZ0)
PEPA5
(AS)
PEPA4
(DS)
PEPA3
PEPA2
(AVEC)
PEPA1
DSACK1
PEPA0
DSACK0
RESET:
DB8
DB8
DB8
DB8
DB8
DB8
DB8
DB8
The bits in this register control the function of each port E pin. Any bit set to one defines the correspond-
ing pin as a bus control signal, with the function shown in the register diagram. Any bit cleared to zero
defines the corresponding pin as an I/O pin, controlled by PORTE and DDRE.
Data bus bit 8 controls the state of this register following reset. If DB8 is set to one during reset, the
register is set to $FF, which defines all port E pins as bus control signals. If DB8 is cleared to zero during
reset, this register is set to $00, defining all port E pins as I/O pins.
NOTE
PE3 is not connected to a pin. PEPA3 returns 1 when read; DDE3 and PE3 bits
can be read and written, but have no function.
PORTF — Port F Data Register
$YFFA19, $YFFA1B
7
PF7
6
5
4
3
2
1
0
PF6
PF5
PF4
PF3
PF2
PF1
PF0
RESET:
U
U
U
U
U
U
U
U
The write to the port F data register is stored in the internal data latch, and if any port F pin is configured
as an output, the value stored for that bit is driven on the pin. A read of the port F data register (PORTF)
returns the value at the pin only if the pin is configured as a discrete input. Otherwise, the value read is
the value stored in the register. Port F is a single register that can be accessed in two locations. It can
be read or written at any time.
DDRF — Port F Data Direction Register
$YFFA1D
7
DDF7
RESET:
0
6
5
4
3
2
1
0
DDF6
DDF5
DDF4
DDF3
DDF2
DDF1
DDF0
0
0
0
0
0
0
0
The bits in this register control the direction of the pin drivers when the pins are configured as I/O. Any
bit in this register set to one configures the corresponding pin as an output. Any bit in this register
cleared to zero configures the corresponding pin as an input.
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
63
PFPAR — Port F Pin Assignment Register
$YFFA1F
7
6
5
4
3
2
1
0
PFPA7
(IRQ7)
PFPA6
(IRQ6)
PFPA5
(IRQ5)
PFPA4
(IRQ4)
PFPA3
(IRQ3)
PFPA2
(IRQ2)
PFPA1
(IRQ1)
PFPA0
(MODCLK)
RESET:
DB9
DB9
DB9
DB9
DB9
DB9
DB9
DB9
The bits in this register control the function of each port F pin. Any bit set to one defines the correspond-
ing pin to be an interrupt request input as defined in the register diagram. Any bit cleared to zero defines
the corresponding pin as an I/O pin, controlled by the port F data and data direction registers. The MOD-
CLK signal has no function after reset.
Data bus bit 9 controls the state of this register following reset. If DB9 is set to one during reset, the
register is set to $FF, which defines all port F pins as interrupt request inputs. If DB9 is cleared to zero
during reset, this register is set to $00, defining all port F pins as I/O pins.
3.6 Resets
Reset procedures handle system initialization and recovery from catastrophic failure. The
MC68HC16Z1 performs resets with a combination of hardware and software. The system integration
module determines whether a reset is valid, asserts control signals, performs basic system configura-
tion and boot ROM selection based on hardware mode-select inputs, then passes control to the CPU16.
Reset occurs when an active low logic level on the RESET pin is clocked into the SIM. Resets are gated
by the CLKOUT signal. Asynchronous resets are assumed to be catastrophic. An asynchronous reset
can occur on any clock edge. Synchronous resets are timed to occur at the end of bus cycles. If there
is no clock when RESET is asserted, reset does not occur until the clock starts. Resets are clocked in
order to allow completion of write cycles in progress at the time RESET is asserted.
Reset is the highest-priority CPU16 exception. Any processing in progress is aborted by the reset ex-
ception, and cannot be restarted. Only essential tasks are performed during reset exception processing.
Other initialization tasks must be accomplished by the exception handler routine.
RSR — Reset Status Register
$YFFA07
7
6
5
4
3
0
2
1
0
EXT
POW
SW
HLT
LOC
SYS
TST
The reset status register contains a bit for each reset source in the MCU. A bit set to one indicates what
type of reset has occurred. When multiple reset sources occur at the same time, more than one bit in
RSR can be set. The reset status register is updated by the reset control logic when the MCU comes
out of reset. This register can be read at any time. A write has no effect.
EXT — External Reset
Reset was caused by an external signal.
POW — Power-Up Reset
Reset was caused by the power-up reset circuit.
SW — Software Watchdog Reset
Reset was caused by the software watchdog circuit.
HLT — Halt Monitor Reset
Reset was caused by the system protection submodule halt monitor.
LOC — Loss of Clock Reset
Reset was caused by loss of clock submodule frequency reference. This reset can only occur if the
RSTEN bit in the clock submodule is set and the VCO is enabled.
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MC68HC16Z1
MC68HC16Z1TS/D
SYS — System Reset
Reset was caused by a CPU RESET instruction. Because the CPU16 has no RESET instruction, this
bit is not used on the MC68HC16Z1 and always reads zero.
TST — Test Submodule Reset
Reset was caused by the test submodule.
3.6.1 Reset Mode Selection
The logic states of certain data bus pins during reset determine SIM operating configuration. In addition,
the state of the MODCLK pin determines system clock source and the state of the pin determines what
happens during subsequent breakpoint assertions. The following table is a summary of reset mode se-
lection options.
Table 15 Reset Mode Selection
Mode Select Pin
Default Function
(Pin Left High)
Alternate Function
(Pin Pulled Low)
DATA0
DATA1
CSBOOT 16-Bit
CS0
CSBOOT 8-Bit
BR
CS1
BG
CS2
BGACK
FC0
DATA2
CS3
CS4
FC1
CS5
FC2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
CS6
ADDR19
ADDR[20:19]
ADDR[21:19]
ADDR[22:19]
ADDR[23:19]
PORTE
CS7–CS6
CS8–CS6
CS9–CS6
CS10–CS6
DSACK0, DSACK1,
AVEC, DS, AS,
SIZE
DATA9
IRQ7–IRQ1
MODCLK
PORTF
DATA11
DATA14
MODCLK
BKPT
Test Mode Disabled
ROM STOP = 0 (Enabled)
VCO = System Clock
Background Mode Disabled
Test Mode Enabled
ROM STOP = 1 (Disabled)
EXTAL = System Clock
Background Mode Enabled
MC68HC16Z1
MC68HC16Z1TS/D
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3.6.2 MCU Module Pin Function During Reset
Generally, module pins default to port functions, and input/output ports are set to input state.This is ac-
complished by disabling pin functions in the appropriate control registers, and by clearing the appropri-
ate port data direction registers. Refer to individual module sections in this manual for more information.
The following table is summary of module pin function out of reset.
Table 16 Module Pin Functions
Module
Pin Mnemonic
Function
ADC
PADA[7:0]/AN[7:0]
DISCRETE INPUT
REFERENCE VOLTAGE
V
RH
V
REFERENCE VOLTAGE
RL
CPU
GPT
DSI/IPIPE1
DSO/IPIPE0
BKPT/DSCLK
PGP7/IC4/OC5
PGP[6:3]/OC[4:1]
PGP[2:0]/IC[3:1]
PAI
DSI/IPIPE1
DSO/IPIPE0
BKPT/DSCLK
DISCRETE INPUT
DISCRETE INPUT
DISCRETE INPUT
DISCRETE INPUT
DISCRETE INPUT
DISCRETE OUTPUT
DISCRETE INPUT
DISCRETE INPUT
DISCRETE INPUT
DISCRETE INPUT
DISCRETE INPUT
DISCRETE INPUT
RXD
PCLK
PWMA, PWMB
PQS7/TXD
QSM
PQS[6:4]/PCS[3:1]
PQS3/PCS0/SS
PQS2/SCK
PQS1/MOSI
PQS0/MISO
RXD
3.6.3 Reset Timing
The RESET input must be asserted for a specified minimum period in order for reset to occur. External
RESET assertion can be delayed internally for a period equal to the longest bus cycle time (or the bus
monitor time-out period) in order to protect write cycles from being aborted by reset. While RESET is
asserted, SIM pins are either in an inactive, high impedance state or are driven to their inactive states.
When an external device asserts RESET for the proper period, reset control logic clocks the signal into
an internal latch. The control logic drives the RESET pin low for an additional 512 CLKOUT cycles after
it detects that the RESET signal is no longer being externally driven, to guarantee this length of reset
to the entire system.
If an internal source asserts a reset signal, the reset control logic asserts RESET for a minimum of 512
cycles. If the reset signal is still asserted at the end of 512 cycles, the control logic continues to assert
RESET until the internal reset signal is negated.
After 512 cycles have elapsed, the reset input pin goes to an inactive, high-impedance state for 10 cy-
cles. At the end of this 10-cycle period, the reset input is tested. When the input is at logic level one,
reset exception processing begins. If, however, the reset input is at logic level zero, the reset control
logic drives the pin low for another 512 cycles. At the end of this period, the pin again goes to high-
impedance state for 10 cycles, then it is tested again. The process repeats until RESET is released.
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MC68HC16Z1TS/D
3.6.4 Power-On Reset
When the SIM clock synthesizer is used to generate system clocks, power-on reset involves special cir-
cumstances related to application of system and clock synthesizer power. Regardless of clock source,
voltage must be applied to clock synthesizer power input pin VDDSYN, in order for the MCU to operate.
The following discussion assumes that VDDSYN is applied before and during reset — this minimizes crys-
tal start-up time. When VDDSYN is applied at power-on, start-up time is affected by specific crystal param-
eters and by oscillator circuit design. VDD ramp-up time also affects pin state during reset.
During power-on reset, an internal circuit in the SIM drives the IMB internal and external reset lines. The
circuit releases the internal reset line as VDD ramps up to the minimum specified value, and SIM pins
are initialized. When VDD reaches minimum value, the clock synthesizer VCO begins operation, and
clock frequency ramps up to limp mode frequency. The external RESET signal remains asserted until
the clock synthesizer PLL locks and 512 CLKOUT cycles elapse.
The SIM clock synthesizer provides clock signals to the other MCU modules. After the clock is running
and the internal reset signal is asserted for four clock cycles, these modules reset. VDD ramp time and
VCO frequency ramp time determine how long the four cycles take. Worst case is approximately 15 mil-
liseconds. During this period, module port pins may be in an indeterminate state. While input-only pins
can be put in a known state by means of external pull-up resistors, external logic on input/output or out-
put-only pins must condition the lines during this time. Active drivers require high-impedance buffers or
isolation resistors to prevent conflict.
3.6.4.1 Use of Three State Control Pin
Asserting the three-state control (TSC) input causes the MCU to put all output drivers in an inactive,
high-impedance state. The signal must remain asserted for 10 clock cycles in order for drivers to
change state. There are certain constraints on use of TSC during power-up reset:
When the internal clock synthesizer is used (MODCLK held high during reset), synthesizer ramp-
up time affects how long the 10 cycles take. Worst case is approximately 20 milliseconds from TSC
assertion.
When an external clock signal is applied (MODCLK held low during reset), pins go to high-imped-
ance state as soon after TSC assertion as 10 clock pulses have been applied to the EXTAL pin.
When TSC assertion takes effect, internal signals are forced to values that can cause inadvertent mode
selection. Once the output drivers change state, the MCU must be powered down and restarted before
normal operation can resume.
3.7 Interrupts
Interrupt recognition and servicing involve complex interaction between the central processing unit, the
system integration module, and a device or module requesting interrupt service.
The CPU16 provides for eight levels of interrupt priority (0–7), seven automatic interrupt vectors, and
200 assignable interrupt vectors. All interrupts with priorities less than seven can be masked by the in-
terrupt priority (IP) field in the condition code register. The CPU16 handles interrupts as a type of asyn-
chronous exception.
Interrupt recognition is based on the states of interrupt request signals IRQ[7:1] and the IP mask value.
Each of the signals corresponds to an interrupt priority. IRQ1 has the lowest priority, and IRQ7 has the
highest priority.
The IP field consists of three bits (CCR[7:5]). Binary values %000 to %111 provide eight priority masks.
Masks prevent an interrupt request of a priority less than or equal to the mask value (except for IRQ7)
from being recognized and processed. When IP contains %000, no interrupt is masked. During excep-
tion processing, the IP field is set to the priority of the interrupt being serviced.
Interrupt request signals can be asserted by external devices or by microcontroller modules. Request
lines are connected internally by means of a wired NOR — simultaneous requests of differing priority
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
67
can be made. Internal assertion of an interrupt request signal does not affect the logic state of the cor-
responding MCU pin.
External interrupt requests are routed to the CPU16 via the external bus interface and SIM interrupt con-
trol logic — the CPU treats external interrupt requests as though they come from the SIM.
External IRQ[6:1] are active-low level-sensitive inputs. External is an active-low transition-sensitive in-
put — it requires both an edge and a voltage level for validity.
IRQ[6:1] are maskable.IRQ7 is nonmaskable. The IRQ7 input is transition-sensitive in order to prevent
redundant servicing and stack overflow. A nonmaskable interrupt is generated each time IRQ7 is as-
serted, and each time the priority mask changes from %111 to a lower number while IRQ7 is asserted.
Interrupt requests are sampled on consecutive falling edges of the system clock. Interrupt request input
circuitry has hysteresis — to be valid, a request signal must be asserted for at least two consecutive
clock periods. Valid requests do not cause immediate exception processing, but are left pending. Pend-
ing requests are processed at instruction boundaries or when exception processing of higher-priority
exceptions is complete.
The CPU16 does not latch the priority of a pending interrupt request. If an interrupt source of higher
priority makes a service request while a lower priority request is pending, the higher priority request is
serviced. If an interrupt request of equal or lower priority than the current IP mask value is made, the
CPU does not recognize the occurrence of the request in any way.
3.7.1 Interrupt Acknowledge and Arbitration
Interrupt acknowledge bus cycles are generated during exception processing. When the CPU16 de-
tects one or more interrupt requests of a priority higher than the interrupt priority mask value, it performs
a CPU space read from address $FFFFF : [IP] : 1.
The CPU space read cycle performs two functions: it places a mask value corresponding to the highest
priority interrupt request on the address bus, and it acquires an exception vector number from the inter-
rupt source. The mask value also serves two purposes: it is latched into the CCR IP field in order to
mask lower-priority interrupts during exception processing, and it is decoded by modules that have re-
quested interrupt service to determine whether the current interrupt acknowledge cycle pertains to
them.
Modules that have requested interrupt service decode the IP value placed on the address bus at the
beginning of the interrupt acknowledge cycle, and if their requests are at the specified IP level, respond
to the cycle. Arbitration between simultaneous requests of the same priority is performed by means of
serial contention between module interrupt arbitration (IARB) field bit values.
Each module that can make an interrupt service request, including the SIM, has an IARB field in its con-
figuration register. An IARB field can be assigned a value from %0001 (lowest priority) to %1111 (high-
est priority). A value of %0000 in an IARB field causes the CPU16 to process a spurious interrupt
exception when an interrupt from that module is recognized.
Because the EBI manages external interrupt requests, the SIM IARB value is used for arbitration be-
tween internal and external interrupt requests. The reset value of IARB for the SIM is %1111, and the
reset IARB value for all other modules is %0000. Initialization software must assign different IARB val-
ues in order to implement an arbitration scheme.
Each module must have a unique IARB value. When two or more IARB fields have the same nonzero
value, the CPU16 interprets multiple vector numbers simultaneously, with unpredictable consequences.
Arbitration must always take place, even when a single source requests service. This point is important
for two reasons: the CPU interrupt acknowledge cycle is not driven on the external bus unless the SIM
wins contention, and failure to contend causes an interrupt acknowledge bus cycle to be terminated by
a bus error, which causes a spurious interrupt exception to be taken.
When arbitration is complete, the dominant module must place an interrupt vector number on the data
bus and terminate the bus cycle. In the case of an external interrupt request, because the interrupt ac-
MOTOROLA
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MC68HC16Z1
MC68HC16Z1TS/D
knowledge cycle is transferred to the external bus, an external device must decode the mask value and
respond with a vector number, then generate bus cycle termination signals. If the device does not re-
spond in time, a spurious interrupt exception is taken.
The periodic interrupt timer (PIT) in the SIM can generate internal interrupt requests of specific priority
at predetermined intervals. By hardware convention, PIT interrupts are serviced before external inter-
rupt service requests of the same priority. Refer to 3.4.4 Periodic Interrupt Timer for more information.
3.7.2 Interrupt Processing Summary
A summary of the interrupt processing sequence follows. When the sequence begins, a valid interrupt
service request has been detected and is pending.
• The CPU finishes higher priority exception processing or reaches an instruction boundary.
• Processor state is stacked, then the CCR PK extension field is cleared.
• The interrupt acknowledge cycle begins:
— FC[2:0] are driven to %111 (CPU space) encoding.
— The address bus is driven as follows. ADDR[23:20] = %1111; ADDR[19:16] = %1111, which
indicates that the cycle is an interrupt acknowledge CPU space cycle; ADDR[15:4] =
%11111111111; ADDR[3:1] = the priority of the interrupt request being acknowledged; and
ADDR0 = %1.
— Request priority is latched into the CCR IP field from the address bus.
• Modules or external peripherals that have requested interrupt service decode the priority value in
ADDR[3:1]. If request priority is the same as the priority value in the address, IARB contention
takes place. When there is no contention, the spurious interrupt monitor asserts, and a spurious
interrupt exception is processed.
• After arbitration, the interrupt acknowledge cycle can be completed in one of three ways:
— The dominant interrupt source supplies a vector number and signals appropriate to the access.
The CPU16 acquires the vector number.
— The signal is asserted (the signal can be asserted by the dominant interrupt source or the pin
can be tied low), and the CPU16 generates an autovector number corresponding to interrupt
priority.
— The bus monitor asserts and the CPU16 generates the spurious interrupt vector number.
• The vector number is converted to a vector address.
• The content of the vector address is loaded into the PC, and the processor transfers control to the
exception handler routine.
3.8 Factory Test Block
The test submodule supports scan-based testing of the various MCU modules. It is integrated into the
SIM to support production test.
3.8.1 Test Registers
Test submodule registers are intended for Motorola use. Register names and addresses are provided
to indicate that these addresses are occupied.
SIMTR — System Integration Test Register
SIMTRE — System Integration Test Register (E Clock)
TSTMSRA — Master Shift Register A
TSTMSRB — Master Shift Register B
TSTSC — Test Module Shift Count
$YFFA02
$YFFA08
$YFFA30
$YFFA32
$YFFA34
$YFFA36
$YFFA38
$YFFA3A
TSTRC — Test Module Repetition Count
CREG — Test Submodule Control Register
DREG — Distributed Register
MC68HC16Z1
MC68HC16Z1TS/D
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MC68HC16Z1
MC68HC16Z1TS/D
4 Analog-to-Digital Converter Module
The ADC is a unipolar, successive-approximation converter with eight modes of operation. It has se-
lectable 8- or 10-bit resolution. Accuracy is ±1 count (1 LSB) in 8-bit mode and ± 2.5 counts (2.5 LSB)
in 10-bit mode. Monotonicity is guaranteed in both modes. With a 16.78-MHz clock, the ADC can per-
form an 8-bit single conversion (4-clock sample) in 8 microseconds, a 10-bit single conversion in 9 mi-
croseconds.
ADC functions can be grouped into three subsystems: an analog front end, a digital control section, and
a bus interface. A block diagram of the converter appears on the following page.
4.1 Analog Subsystem
The analog front end consists of a multiplexer, input sample buffer amplifier, a resistor-capacitor array,
and a high-gain comparator. The multiplexer selects one of eight internal or eight external signal sourc-
es for conversion. The resistor capacitor (RC) array performs two functions. It acts as a sample/hold
circuit, and it provides the digital-to-analog comparison output necessary for successive approximation
conversion. The comparator indicates whether each successive output of the RC array is higher or low-
er than the sampled input.
4.2 Digital Control Subsystem
The digital control section includes conversion sequence control logic, channel and reference select
logic, successive approximation register, eight result registers, a port data register, and control/status
registers. It controls the multiplexer and the output of the RC array during the sample and conversion
periods, stores the results of comparison in the successive-approximation register, then transfers the
result to a result register.
4.3 Bus Interface Subsystem
The bus interface contains logic necessary to interface the ADC to the intermodule bus. The ADC is
designed to act as a slave device on the bus. The interface must respond with appropriate bus cycle
termination signals and must supply appropriate interface timing to the other submodule.
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
71
V
V
DDA
SSA
SUPPLY
V
V
RH
RL
REFERENCE
RC DAC ARRAY
AND
COMPARATOR
PADA7/AN7
PADA6/AN6
PADA5/AN5
PADA4/AN4
PADA3/AN3
PADA2/AN2
PADA1/AN1
PADA0/AN0
ANALOG
MUX
AND SAMPLE
BUFFER
AMPLIFIER
SAR
RESERVED
RESERVED
RESERVED
RESERVED
MODE
AND
TIMING
CONTROL
RESULT 0
RESULT 1
RESULT 2
RESULT 3
RESULT 4
RESULT 5
RESULT 6
RESULT 7
INTERNAL
CONNECTIONS
V
V
RH
RL
(V – V )/2
RH RL
RESERVED
PORT ADA
DATA
REGISTER
CLK SELECT/
PRESCALE
ADC BUS INTERFACE UNIT
INTERMODULE BUS (IMB)
Z1 ADC BLOCK
Figure 13 Analog-to-Digital Converter Block Diagram
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MC68HC16Z1
MC68HC16Z1TS/D
Table 17 ADC Address Map
Address
$YFF700
$YFF702
$YFF704
$YFF706
$YFF708
$YFF70A
$YFF70C
$YFF70E
$YFF710
$YFF712
$YFF714
$YFF716
$YFF718
$YFF71A
$YFF71C
$YFF71E
$YFF720
$YFF722
$YFF724
$YFF726
$YFF728
$YFF72A
$YFF72C
$YFF72E
$YFF730
$YFF732
$YFF734
$YFF736
$YFF738
$YFF73A
$YFF73C
$YFF73E
15
8
7
0
MODULE CONFIGURATION (ADCMCR)
FACTORY TEST (ADTEST)
(RESERVED)
PORT ADA DATA (PORTADA)
(RESERVED)
ADC CONTROL 0 (ADCTL0)
ADC CONTROL 1 (ADCTL1)
ADC STATUS (ADSTAT)
RIGHT-JUSTIFIED UNSIGNED RESULT 0 (RJURR0)
RIGHT-JUSTIFIED UNSIGNED RESULT 1 (RJURR1)
RIGHT-JUSTIFIED UNSIGNED RESULT 2 (RJURR2)
RIGHT-JUSTIFIED UNSIGNED RESULT 3 (RJURR3)
RIGHT-JUSTIFIED UNSIGNED RESULT 4 (RJURR4)
RIGHT-JUSTIFIED UNSIGNED RESULT 5 (RJURR5)
RIGHT-JUSTIFIED UNSIGNED RESULT 6 (RJURR6)
RIGHT-JUSTIFIED UNSIGNED RESULT 7 (RJURR7)
LEFT-JUSTIFIED SIGNED RESULT 0 (LJSRR0)
LEFT-JUSTIFIED SIGNED RESULT 1 (LJSRR1)
LEFT-JUSTIFIED SIGNED RESULT 2 (LJSRR2)
LEFT-JUSTIFIED SIGNED RESULT 3 (LJSRR3)
LEFT-JUSTIFIED SIGNED RESULT 4 (LJSRR4)
LEFT-JUSTIFIED SIGNED RESULT 5 (LJSRR5)
LEFT-JUSTIFIED SIGNED RESULT 6 (LJSRR6)
LEFT-JUSTIFIED SIGNED RESULT 7 (LJSRR7)
LEFT-JUSTIFIED UNSIGNED RESULT 0 (LJURR0)
LEFT-JUSTIFIED UNSIGNED RESULT 1 (LJURR1)
LEFT-JUSTIFIED UNSIGNED RESULT 2 (LJURR2)
LEFT-JUSTIFIED UNSIGNED RESULT 3 (LJURR3)
LEFT-JUSTIFIED UNSIGNED RESULT 4 (LJURR4)
LEFT-JUSTIFIED UNSIGNED RESULT 5 (LJURR5)
LEFT-JUSTIFIED UNSIGNED RESULT 6 (LJURR6)
LEFT-JUSTIFIED UNSIGNED RESULT 7 (LJURR7)
Y = M111, where M is the logic state of the modmap (MM) bit in the SIMCR
4.4 ADC Registers
ADCMCR — ADC Module Configuration Register
$YFF700
15
14
13
12
8
7
6
0
STOP
FRZ
NOT USED
SUPV
NOT USED
RESET:
1
0
0
0
Use the module configuration register to initialize the ADC.
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
73
STOP — STOP Mode
0 = Normal operation
1 = Low-power operation
STOP places the ADC in low-power state by disabling the ADC clock and powering down the analog
circuitry. Setting STOP aborts any conversion in progress. STOP is set to logic level one at reset and
can be cleared to logic level zero by the CPU.
Clearing STOP enables normal ADC operation. However, because analog circuitry bias current has
been turned off, there is a period of recovery before output stabilization.
FRZ[1:0] — Freeze 1
Use the FRZ field to determine ADC response to assertion of the IFREEZE signal. The following table
shows possible responses.
FRZ
00
Response
Ignore IFREEZE
01
Reserved
10
Finish conversion, then freeze
Freeze immediately
11
SUPV — Supervisor/Unrestricted
0 = Unrestricted access
1 = Supervisor access
SUPV defines access to assignable ADC registers. Because the CPU16 in the MC68HC16Z1 operates
in supervisor mode only, this bit has no effect.
ADTEST — ADC Test Register
$YFF702
ADTEST is used with the SIM test register for factory test of the ADC.
PORTADA — Port ADA Data Register
$YFF706
15
11
NOT USED
10
9
8
7
0
PORTADA
RESET:
0
0
0
0
0
0
0
0
INPUT DATA
Port A is an input port that shares pins with the A/D converter inputs.
PORTADA [7:0]
A read of PORTADA[7:0] returns the logic level of the port A pins. If the input is not an appropriate volt-
age (outside the defined levels), the read will be indeterminate. Use of a port A pin for digital input does
not preclude its use as an analog input.
ADCTL0 — A/D Control Register 0
$YFF70A
15
8
7
6
5
4
3
2
1
0
NOT USED
RESET:
RES10
STS
PRS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Use ADCTL0 to select ADC clock source and to set up prescaling. Writes to it have immediate effect.
RES10 — 10-Bit Resolution
0 = 8-bit conversion
1 = 10-bit conversion
Conversion results are appropriately aligned in result registers to reflect conversion status.
MOTOROLA
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MC68HC16Z1
MC68HC16Z1TS/D
STS[1:0] — Sample Time Select Field
Total conversion time depends on initial sample time, transfer time, final sample time, and resolution
time. Initial sample time is fixed at two clocks. Transfer time is fixed at two clocks. Resolution time is
fixed at 10 ADC clock cycles for an 8-bit conversion and 12 ADC clock cycles for a 10-bit conversion.
Final sample time is determined by the value in the STS field, as shown in the following table.
STS[1:0]
Final Sample Time
2 A/D Clock Periods
4 A/D Clock Periods
8 A/D Clock Periods
16 A/D Clock Periods
00
01
10
11
PRS[4:0] — Prescaler Rate Selection Field
ADC clock is generated from system clock using a modulo counter and a divide-by-two circuit. The bi-
nary value of this field is the counter modulus. System clock is divided by the PRS value plus one, then
sent to the divide-by-two circuit, as shown in the following table.
PRS[4:0]
00000
00001
00010
...
Divisor Value
Max. System Clock
Min. System Clock
RESERVED
—
—
4
8 MHz
12 MHz
...
2 MHz
3 MHz
...
6
...
11101
11110
11111
60
62
64
120 MHz
124 MHz
128 MHz
30 MHz
31 MHz
32 MHz
ADCTL1 — A/D Control Register 1
$YFF70C
15
8
0
7
0
6
5
4
3
2
1
0
NOT USED
SCAN MULT S8CM
CD
CC
CB
CA
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Use ADCTL1 to initiate A/D conversion, or to select conversion modes and conversion channel. It can
be written or read at any time. A write to ADCTL1 initiates a conversion sequence. If a conversion se-
quence is already in progress, a write to ADCTL1 aborts it and resets the SCF and CCF flags in the A/
D status register.
SCAN — Scan Mode Selection Bit
0 = Single conversion sequence
1 = Continuous conversion
Length of conversion sequence(s) is determined by S8CM.
MULT — Multichannel Conversion Bit
0 = Conversion sequence(s) run on single channel (channel selected by [CD:CA])
1 = Sequential conversion of a block of four or eight channels (block selected by [CD:CA])
Length of conversion sequence(s) is determined by S8CM.
S8CM — Select Eight-Conversion Sequence Mode
0 = Four-conversion sequence
1 = Eight-conversion sequence
This bit determines the number of conversions in a conversion sequence.
[CD:CA] — Channel Selection Field
Use the bits in this field to select an input or block of inputs for A/D conversion.
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
75
The following table is a summary of the operation of S8CM and [CD:CA] when MULT is cleared (single-
channel mode). Number of conversions per channel is determined by SCAN.
S8CM
CD
0
CC
0
CB
0
CA
0
Input
AN0
Result Register
RSLT[0:3]
RSLT[0:3]
RSLT[0:3]
RSLT[0:3]
RSLT[0:3]
RSLT[0:3]
RSLT[0:3]
RSLT[0:3]
RSLT[0:3]
RSLT[0:3]
RSLT[0:3]
RSLT[0:3]
RSLT[0:3]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
AN1
0
0
1
0
AN2
0
0
1
1
AN3
0
1
0
0
AN4
0
1
0
1
AN5
0
1
1
0
AN6
0
1
1
1
AN7
1
0
0
0
RESERVED
RESERVED
RESERVED
RESERVED
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
V
RH
0
0
1
1
1
1
0
1
1
0
V
RSLT[0:3]
RSLT[0:3]
RL
(V
V
) / 2
RH – RL
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
TEST/RESERVED
AN0
RSLT[0:3]
RSLT[0:7]
RSLT[0:7]
RSLT[0:7]
RSLT[0:7]
RSLT[0:7]
RSLT[0:7]
RSLT[0:7]
RSLT[0:7]
RSLT[0:7]
RSLT[0:7]
RSLT[0:7]
RSLT[0:7]
RSLT[0:7]
AN1
AN2
AN3
AN4
AN5
AN6
AN7
RESERVED
RESERVED
RESERVED
RESERVED
V
RH
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
V
RSLT[0:7]
RSLT[0:7]
RSLT[0:7]
RL
(V
V
) / 2
RH – RL
TEST/RESERVED
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MC68HC16Z1
MC68HC16Z1TS/D
The following table is a summary of the operation of S8CM and [CD:CA] when MULT is set (multi-chan-
nel mode). Number of conversions per channel is determined by SCAN. Channel numbers are given in
order of conversion.
S8CM
CD
CC
CB
CA
Input
AN0
Result Register
RSLT0
RSLT1
RSLT2
RSLT3
RSLT0
RSLT1
RSLT2
RSLT3
RSLT0
RSLT1
RSLT2
RSLT3
RSLT0
0
0
0
X
X
AN1
AN2
AN3
0
0
0
0
1
1
1
0
1
X
X
X
X
X
X
AN4
AN5
AN6
AN7
RESERVED
RESERVED
RESERVED
RESERVED
V
RH
V
RSLT1
RSLT2
RL
(V
V
) / 2
RH – RL
TEST/RESERVED
AN0
RSLT3
RSLT0
RSLT1
RSLT2
RSLT3
RSLT4
RSLT5
RSLT6
RSLT7
RSLT0
RSLT1
RSLT2
RSLT3
RSLT4
1
0
X
X
X
AN1
AN2
AN3
AN4
AN5
AN6
AN7
1
1
X
X
X
RESERVED
RESERVED
RESERVED
RESERVED
V
RH
V
RSLT5
RSLT6
RSLT7
RL
(V
V
) / 2
RH – RL
TEST/RESERVED
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
77
ADSTAT — ADC Status Register
$YFF70E
15
14
11
10
0
8
0
7
0
0
SCF
NOT USED
CCTR
0
CCF
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
ADSTAT contains information related to the status of a conversion sequence.
SCF — Sequence Complete Flag
0 = Sequence not complete
1 = Sequence complete
SCF is set at the end of the conversion sequence when SCAN is cleared, and at the end of the first
conversion sequence when SCAN is set. SCF is cleared when ADCTL1 is written and a new conversion
sequence begins.
CCTR[2:0] — Conversion Counter Field
This field reflects the contents of the conversion counter pointer in either four or eight count conversion
sequence. The value corresponds to the number of the next result register to be written, and thus indi-
cates which channel is being converted.
CCF[7:0] — Conversion Complete Field
Each bit in this field corresponds to an A/D result register (CCF7 to RSLT7, etc.). A bit is set when con-
version for the corresponding channel is complete, and remains set until the result register is read. A
bit is cleared when the register is read.
RSLT[0:7] — A/D Result Registers
$YFF710–$YFF73E
The result registers store data after conversion is complete. Each register can be read from three dif-
ferent addresses in the register block. Data format depends on the address from which the data is read.
RJURR — Unsigned Right-Justified Format
$YFF710–$YFF71E
Conversion result is unsigned right-justified data. Bits [9:0] are used for 10-bit resolution, bits [7:0] are
used for 8-bit conversion (bits [9:8] are zero). Bits [15:10] always return zero when read.
LJSRR — Signed Left-Justified Format
$YFF720–$YFF72E
Conversion result is signed left-justified data. Bits [15:6] are used for 10-bit resolution, and bits [15:8]
are used for 8-bit conversion (bits [7:6] are zero). Although the ADC is unipolar, it is assumed that the
zero point is halfway between low and high reference when this format is used. For positive input, bit
15 = 0. For negative input, bit 15 = 1. Bits [5:0] always return zero when read.
LJURR — Unsigned Left-Justified Format
$YFF730–$YFF73E
Conversion result is unsigned left-justified data. Bits [15:6] are used for 10-bit resolution, and bits [15:8]
are used for 8-bit conversion (bits [7:6] are zero). Bits [5:0] always return zero when read.
MOTOROLA
78
MC68HC16Z1
MC68HC16Z1TS/D
MC68HC16Z1
MOTOROLA
79
MC68HC16Z1TS/D
5 Queued Serial Module
The QSM contains two serial interfaces, the queued serial peripheral interface (QSPI) and the serial
communication interface (SCI).
The QSPI provides easy peripheral expansion or interprocessor communication through a full-duplex,
synchronous, three-line bus: data in, data out, and a serial clock. Four programmable peripheral-select
pins provide addressability for up to 16 peripheral devices. A self-contained RAM queue allows up to
16 serial transfers of 8–16 bits each, or transmission of a 256-bit data stream without CPU intervention.
A special wraparound mode supports continuous sampling of a serial peripheral, with automatic QSPI
RAM updating, which makes the interface to A/D converters more efficient.
The SCI provides a standard nonreturn to zero (NRZ) mark/space format. It operates in either full- or
half-duplex mode. There are separate transmitter and receiver enable bits and dual data buffers. A
modulus-type baud rate generator provides rates from 64 to 524 kbaud with a 16.78-MHz system clock.
Word length of either 8 or 9 bits is software selectable. Optional parity generation and detection provide
either even or odd parity check capability. Advanced error detection circuitry catches glitches of up to
1/16 of a bit time in duration. Wake-up functions allow the CPU to run uninterrupted until meaningful
data is available.
Refer to the following block diagram of the QSM.
PQS0/MISO
PQS1/MOSI
PQS2/SCK
PQS3/SS/PCS0
PQS4/PCS1
PQS5/PCS2
PQS6/PCS3
QSPI
PORT QS
INTERFACE
LOGIC
IMB
PQS7/TXD
RXD
SCI
QSM BLOCK
Figure 14 QSM Block Diagram
MOTOROLA
80
MC68HC16Z1
MC68HC16Z1TS/D
Table 18 QSM Address Map
Address
$YFFC00
$YFFC02
$YFFC04
$YFFC06
$YFFC08
$YFFC0A
$YFFC0C
$YFFC0E
$YFFC10
$YFFC12
$YFFC14
$YFFC16
$YFFC18
$YFFC1A
$YFFC1C
$YFFC1E
15
8
7
0
QSM MODULE CONFIGURATION (QSMCR)
QSM TEST (QTEST)
QSM INTERRUPT LEVEL (QILR)
QSM INTERRUPT VECTOR (QIVR)
RESERVED
SCI CONTROL 0 (SCCR0)
SCI CONTROL 1 (SCCR1)
SCI STATUS (SCSR)
SCI DATA (SCDR)
RESERVED
RESERVED
RESERVED
PQS PIN ASSIGNMENT (PQSPAR)
PQS DATA (PORTQS)
PQS DATA DIRECTION (DDRQS)
SPI CONTROL 0 (SPCR0)
SPI CONTROL 1 (SPCR1)
SPI CONTROL 2 (SPCR2)
SPI CONTROL 3 (SPCR3)
SPI STATUS (SPSR)
$YFFC20–
$YFFCFF
RESERVED
$YFFD00–
$YFFD1F
RECEIVE RAM (RR[0:F])
TRANSMIT RAM (TR[0:F])
COMMAND RAM (CR[0:F])
$YFFD20–
$YFFD3F
$YFFD40–
$YFFD4F
Y = M111, where M is the logic state of the modmap (MM) bit in the SIMCR
The following table is a summary of the functions of the QSM pins when they are not configured for gen-
eral-purpose I/O. The QSM data direction register (DDRQS) designates each pin (except RXD) as input
or output.
Pin
Mode
Master
Slave
Pin Function
Serial Data Input to QSPI
Serial Data Output from QSPI
Serial Data Output from QSPI
Serial Data Input to QSPI
Clock Output from QSPI
Clock Input to QSPI
MISO
Master
Slave
MOSI
SCK
Master
Slave
QSPI Pins
Master
Input: Assertion Causes Mode Fault
Output: Selects Peripherals
PCS0/SS
Slave
Master
Slave
Input: Selects the QSPI
Output: Selects Peripherals
None
PCS[3:1]
TXD
RXD
Transmit
Receive
Serial Data Output from SCI
Serial Data Input to SCI
SCI Pins
5.1 QSM Registers
There are four types of QSM registers: QSM global registers, QSM pin control registers, QSPI submod-
ule registers, and SCI submodule registers. The QSPI and SCI registers are defined in separate sec-
tions below. Writes to unimplemented register bits have no meaning or effect, and reads from
unimplemented bits always return a logic zero value.
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
81
The modmap (MM) bit in the system integration module configuration register (SIMCR) defines the most
significant bit (ADDR23) of the address, shown in each register figure as Y. This bit, concatenated with
the rest of the address given, forms the absolute address of each register. Because the CPU16 in the
MC68HC16Z1 drives only ADDR[19:0], ADDR[23:20] follow the logic state of ADDR19, and Y must
equal $F. Refer to the SIM section of this technical summary for more information about how the state
of MM affects the system.
5.1.1 Global Registers
The QSM global registers contain system parameters used by both the QSPI and the SCI submodules.
These registers contain the bits and fields used to configure the QSM.
QSMCR — QSM Configuration Register
$YFFC00
15
14
13
12
0
11
0
10
0
9
0
8
0
7
6
0
5
0
4
0
3
2
1
0
0
0
STOP
FRZ1
FRZ0
SUPV
IARB
RESET:
0
0
0
0
0
0
0
0
1
0
0
0
0
0
The QSMCR contains parameters for the QSM/CPU/intermodule bus (IMB) interface.
STOP — Stop Enable
0 = Normal QSM clock operation
1 = QSM clock operation stopped
STOP places the QSM in a low-power state by disabling the system clock in most parts of the module.
QSMCR is the only register guaranteed to be readable while STOP is asserted. The QSPI RAM is not
readable. However, writes to RAM or any register are guaranteed to be valid while STOP is asserted.
STOP can be negated by the CPU and by reset.
The system software must stop each submodule before asserting STOP to avoid complications at re-
start and to avoid data corruption. The SCI submodule receiver and transmitter should be disabled, and
the operation should be verified for completion before asserting STOP. The QSPI submodule should be
stopped by asserting the HALT bit in SPCR3 and by asserting STOP after the HALTA flag is set.
FRZ1 — Freeze 1
0 = Ignore the FREEZE signal on the IMB
1 = Halt the QSPI (on a transfer boundary)
FRZ1 determines what action is taken by the QSPI when the FREEZE signal of the IMB is asserted.
FREEZE is asserted whenever the CPU enters the background mode.
FRZ0 — Freeze 0
Reserved
Bits [12:8] — Not Implemented
SUPV — Supervisor/Unrestricted
0 = User access
1 = Supervisor access (MC68HC16Z1 default)
SUPV defines the assignable QSM registers as either supervisor-only data space or unrestricted data
space. Because the CPU16 in the MC68HC16Z1 operates in supervisor mode only, this bit has no ef-
fect.
Bits [6:4] — Not Implemented
IARB — Interrupt Arbitration Identification Number
Each module that generates interrupts must have an IARB field. In this field, each module has a unique
value that is used to arbitrate for the IMB when modules generate simultaneous interrupts of the same
priority. Refer to the SIM section of this summary for more information.
MOTOROLA
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MC68HC16Z1
MC68HC16Z1TS/D
QTEST — QSM Test Register
$YFFC02
QTEST is used during factory test of the QSM. Accesses to QTEST must be made while the MCU is in
test mode.
QILR — QSM Interrupt Levels Register
$YFFC04
15
0
14
0
13
12
11
10
9
8
8
0
ILQSPI
ILSCI
QIVR
RESET:
0
0
0
0
0
0
0
0
QILR determines the priority level of interrupts requested by the QSM and the vector used when an in-
terrupt is acknowledged.
ILQSPI — Interrupt Level for QSPI
ILQSPI determines the priority of QSPI interrupts. This field must be given a value between $0 (inter-
rupts disabled) to $7 (highest priority).
ILSCI — Interrupt Level of SCI
ILSCI determines the priority of SCI interrupts. This field must be given a value between $0 (interrupts
disabled) to $7 (highest priority).
If ILQSPI and ILSCI are the same (nonzero) value, and both submodules simultaneously request inter-
rupt service, QSPI has priority.
QIVR — QSM Interrupt Vector Register
$YFFC05
15
8
7
6
5
4
3
2
1
0
QILR
INTV
RESET:
0
0
0
0
1
1
1
1
At reset, QIVR is initialized to $0F, which corresponds to the uninitialized interrupt vector in the excep-
tion table. This vector is selected until QIVR is written. A user-defined vector ($40–$FF) should be writ-
ten to QIVR during QSM initialization.
After initialization, QIVR determines which two vectors in the exception vector table are to be used for
QSM interrupts. The QSPI and SCI submodules have separate interrupt vectors adjacent to each other.
Both submodules use the same interrupt vector with the least significant bit (LSB) determined by the
submodule causing the interrupt.
The value of INTV0 used during an IACK cycle is supplied by the QSM. During an IACK, INTV[7:1] are
driven on DATA[7:1] IMB lines. DATA0 is negated for an SCI interrupt and asserted for a QSPI interrupt.
Writes to INTV0 have no meaning or effect. Reads of INTV0 return a value of one.
5.1.2 Pin Control Registers
The QSM uses nine pins, eight of which form a parallel port (PORTQS) on the MCU. Although these
pins are used by the serial subsystems, any pin can alternately be assigned as general-purpose input/
output (I/O) on a pin-by-pin basis.
Pins used for general-purpose I/O must not be assigned to the QSPI by register PQSPAR. To avoid
driving incorrect data, the first byte to be output must be written before DDRQS is configured. DDRQS
must then be written to determine the direction of data flow and to output the value contained in register
PORTQS. Subsequent data for output is written to PORTQS.
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
83
PORTQS — Port QS Data Register
$YFFC15
15
8
7
6
5
4
3
2
1
0
RESERVED
DATA7
(TXD)
DATA6
(PCS3)
DATA5
(PCS2)
DATA4
(PCS1)
DATA3
(PCS0/
SS)
DATA2
(SCK)
DATA1
(MOSI)
DATA0
(MISO)
RESET:
0
0
0
0
0
0
0
0
PORTQS is the port QS data register. Writes to PORTQS affect pins defined as outputs. Reads of
PORTQS return data present on the pins.
PQSPAR — Port QS Pin Assignment Register
$YFFC16
15
0
14
13
12
11
10
0
9
8
7
0
PCS3 PCS2 PCS1
PCS0/
SS
MOSI
MISO
DDRQS
RESET:
0
0
0
0
0
0
0
0
PQSPAR determines whether certain pins are used by the QSPI submodule, or whether they are avail-
able for general-purpose I/O. Pins designated for general-purpose I/O are controlled by DDRQS and
PORTQS. PQSPAR does not affect operation of the SCI submodule. Bits 15 and 10 are not implement-
ed.
PCS[3:1] — Peripheral Chip Selects
PCS0/SS — Peripheral Chip Select 0/Slave Select
MOSI — Master Out Slave In
MISO — Master In Slave Out
0 = Used for general-purpose I/O
1 = Used by QSPI submodule
DDRQS — Port QS Data Direction Register
$YFFC17
15
8
7
6
5
4
3
2
1
0
PQSPAR
TXD
PCS3 PCS2 PCS1
PCS0/
SS
SCK
MOSI
MISO
RESET:
0
0
0
0
0
0
0
0
DDRQS determines whether a general-purpose I/O pin is an input or an output. During reset, all QSM
pins are configured as general-purpose inputs.
TXD — Transmit Data
0 = Input
1 = Output
This bit determines the direction of the TXD pin only when the SCI transmitter is disabled. When the
SCI transmitter is enabled, the TXD pin is an output.
All of the following bits determine the corresponding QSPI port pin operation to be input or output.
PCS[3:1] — Peripheral Chip Selects
PCS0/SS — Peripheral Chip Select 0/Slave Select
SCK — Serial Clock
MOSI — Master Out Slave In
MISO — Master In Slave Out
0 = Input
1 = Output
MOTOROLA
84
MC68HC16Z1
MC68HC16Z1TS/D
5.2 QSPI Submodule
The QSPI submodule communicates with external devices through a synchronous serial bus. The QSPI
is fully compatible with the serial peripheral interface (SPI) systems found on other Motorola products.
Refer to the following block diagram of the QSPI.
QUEUE CONTROL
BLOCK
4
QUEUE
POINTER
COMPARATOR
DONE
END QUEUE
POINTER
80-BYTE
QSPI RAM
ADDRESS
REGISTER
4
CONTROL
LOGIC
STATUS
REGISTER
CONTROL
REGISTERS
CHIP SELECT
COMMAND
4
4
DELAY
COUNTER
M
S
MSB
LSB
8/16-BIT SHIFT REGISTER
Rx/Tx DATA REGISTER
MOSI
MISO
PROGRAMMABLE
LOGIC ARRAY
M
S
PCS0/SS
PCS [3:1]
3
BAUD RATE
GENERATOR
SCK
QSPI BLOCK
Figure 15 QSPI Block Diagram
5.2.1 QSPI Pins
Seven pins are associated with the QSPI. When not needed for a QSPI application, they can be con-
figured as general-purpose I/O pins.
Refer to the following table for QSPI input and output pins and their functions.
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
85
Pin Names
Master In Slave Out
Mnemonics
Mode
Function
MISO
Master
Slave
Serial Data Input to QSPI
Serial Data Output from QSPI
Master Out Slave In
Serial Clock
MOSI
SCK
Master
Slave
Serial Data Output from QSPI
Serial Data Input to QSPI
Master
Slave
Clock Output from QSPI
Clock Input to QSPI
Peripheral Chip Selects
Slave Select
PCS[3:0]
SS
Master
Select Peripherals
Master
Slave
Causes Mode Fault
Initiates Serial Transfer
5.2.2 QSPI Registers
The programmer's model for the QSPI submodule consists of the QSM global and pin control registers,
four QSPI control registers, one status register, and the 80-byte QSPI RAM.
Registers and RAM can be read and written by the CPU. The four control registers must be initialized
before the QSPI is enabled to insure defined operation. SPCR1 should be written last because it con-
tains QSPI enable bit SPE. Asserting this bit starts the QSPI. The QSPI control registers are reset to a
defined state and can then be changed by the CPU. Reset values are shown below each register.
Refer to the following memory map of the QSPI.
Address
$YFFC18
$YFFC1A
$YFFC1C
$YFFC1E
$YFFC1F
$YFFD00
$YFFD20
$YFFD40
Name
SPCR0
SPCR1
SPCR2
SPCR3
SPSR
RAM
Usage
QSPI Control Register 0
QSPI Control Register 1
QSPI Control Register 2
QSPI Control Register 3
QSPI Status Register
QSPI Receive Data (16 Words)
QSPI Transmit Data (16 Words)
QSPI Command Control (8 Words)
RAM
RAM
Writing a different value into any control register except SPCR2 while the QSPI is enabled disrupts op-
eration. SPCR2 is buffered to prevent disruption of the current serial transfer. After completion of the
current serial transfer, the new SPCR2 values become effective.
Writing the same value into any control register except SPCR2 while the QSPI is enabled has no effect
on QSPI operation. Rewriting NEWQP in SPCR2 causes execution to restart at the designated location.
SPCR0 — QSPI Control Register 0
$YFFC18
15
MSTR
RESET:
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WOMQ
BITS
CPOL CPHA
SPBR
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
SPCR0 contains parameters for configuring the QSPI before it is enabled. The CPU can read and write
this register. The QSM has read-only access.
MOTOROLA
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MC68HC16Z1
MC68HC16Z1TS/D
MSTR — Master/Slave Mode Select
0 = QSPI is a slave device and only responds to externally generated serial data.
1 = QSPI is system master and can initiate transmission to external SPI devices.
MSTR configures the QSPI for either master or slave mode operation. This bit is cleared on reset and
may only be written by the CPU.
WOMQ — Wired-OR Mode for QSPI Pins
0 = Outputs have normal MOS drivers.
1 = Pins designated for output by DDRQS have open-drain drivers.
WOMQ allows the wired-OR function to be used on QSPI pins, regardless of whether they are used as
general-purpose outputs or as QSPI outputs. WOMQ affects the QSPI pins whether the QSPI is en-
abled or disabled.
BITS — Bits Per Transfer
In master mode, when BITSE in a command is set, the BITS field determines the number of data bits
transferred. When BITSE is cleared, eight bits are transferred. Reserved values default to eight bits.
BITSE is not used in slave mode.
The following table shows the number of bits per transfer.
BITS
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Bits per Transfer
16
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
8
9
10
11
12
13
14
15
CPOL — Clock Polarity
0 = The inactive state value of SCK is logic level zero.
1 = The inactive state value of SCK is logic level one.
CPOL is used to determine the inactive state value of the serial clock (SCK). It is used with CPHA to
produce a desired clock/data relationship between master and slave devices.
CPHA — Clock Phase
0 = Data is captured on the leading edge of SCK and changed on the following edge of SCK.
1 = Data is changed on the leading edge of SCK and captured on the following edge of SCK.
CPHA determines which edge of SCK causes data to change and which edge causes data to be cap-
tured. CPHA is used with CPOL to produce a desired clock/data relationship between master and slave
devices. CPHA is set at reset.
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
87
SPBR — Serial Clock Baud Rate
The QSPI uses a modulus counter to derive SCK baud rate from the MCU system clock. Baud rate is
selected by writing a value from 2 to 255 into the SPBR field. The following equation determines the
SCK baud rate:
SCK Baud Rate = System Clock/(2SPBR)
or
SPBR = System Clock/(2SCK)(Baud Rate Desired)
where SPBR equals {2, 3, 4,..., 255}
Giving SPBR a value of zero or one disables the baud rate generator. SCK is disabled and assumes its
inactive state value. No serial transfers occur. At reset, BAUD is initialized to a 2.1-MHz SCK frequency.
SPCR1 — QSPI Control Register 1
$YFFC1A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SPE
DSCKL
DTL
RESET:
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
SPCR1 contains parameters for configuring the QSPI before it is enabled. The CPU can read and write
this register, but the QSM has read access only, except for SPE, which is automatically cleared by the
QSPI after completing all serial transfers, or when a mode fault occurs.
SPE — QSPI Enable
0 = QSPI is disabled. QSPI pins can be used for general-purpose I/O.
1 = QSPI is enabled. Pins allocated by PQSPAR are controlled by the QSPI.
DSCKL — Delay before SCK
When the DSCK bit in command RAM is set, this field determines the length of delay from PCS valid to
SCK transition. PCS can be any of the four peripheral chip-select pins. The following equation deter-
mines the actual delay before SCK:
PCS to SCK Delay = [DSCKL/System Clock]
where DSCKL equals {1, 2, 3,..., 127}.
When a queue entry's DSCK equals zero, then DSCKL is not used. Instead, the PCS valid-to-SCK tran-
sition is one-half SCK period.
DTL — Length of Delay after Transfer
When the DT bit in command RAM is set, this field determines the length of delay after serial transfer.
The following equation is used to calculate the delay:
Delay after Transfer = [(32DTL)/System Clock]
where DTL equals {1, 2, 3,..., 255}.
A zero value for DTL causes a delay-after-transfer value of 8192/System Clock.
If DT equals zero, a standard delay is inserted.
Standard Delay after Transfer = [17/System Clock]
Delay after transfer can be used to provide a peripheral deselect interval. A delay can also be inserted
between consecutive transfers to allow serial A/D converters to complete conversion.
SPCR2 — QSPI Control Register 2
$YFFC1C
15
14
13
12
0
11
10
ENDQP
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
SPIFIE
WREN
WRTO
NEWQP
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
MOTOROLA
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MC68HC16Z1
MC68HC16Z1TS/D
SPCR2 contains QSPI configuration parameters. Although the CPU can read and write this register, the
QSM has read access only. Writes to SPCR2 are buffered. A write to SPCR2 that changes a bit value
while the QSPI is operating is ineffective on the current serial transfer, but becomes effective on the
next serial transfer. Reads of SPCR2 return the current value of the register, not of the buffer.
SPIFIE — SPI Finished Interrupt Enable
0 = QSPI interrupts disabled
1 = QSPI interrupts enabled
SPIFIE enables the QSPI to generate a CPU interrupt upon assertion of the status flag SPIF.
WREN — Wrap Enable
0 = Wraparound mode disabled
1 = Wraparound mode enabled
WREN enables or disables wraparound mode.
WRTO — Wrap To
When wraparound mode is enabled, after the end of queue has been reached, WRTO determines
which address the QSPI executes.
Bit 12 — Not Implemented
ENDQP — Ending Queue Pointer
This field contains the last QSPI queue address.
Bits [7:4] — Not Implemented
NEWQP — New Queue Pointer Value
This field contains the first QSPI queue address.
SPCR3 — QSPI Control Register 3
$YFFC1E
15
14
0
13
0
12
0
11
0
10
9
8
7
0
0
RESET:
0
LOOPQ
HMIE
HALT
SPSR
0
0
0
0
0
0
0
SPCR3 contains QSPI configuration parameters. The CPU can read and write SPCR3, but the QSM
has read-only access.
Bits [15:11] — Not Implemented
LOOPQ — QSPI Loop Mode
0 = Feedback path disabled
1 = Feedback path enabled
LOOPQ controls feedback on the data serializer for testing.
HMIE — HALTA and MODF Interrupt Enable
0 = HALTA and MODF interrupts disabled
1 = HALTA and MODF interrupts enabled
HMIE controls CPU interrupts caused by the HALTA status flag or the MODF status flag in SPSR.
HALT — Halt
0 = Halt not enabled
1 = Halt enabled
When HALT is asserted, the QSPI stops on a queue boundary. It is in a defined state from which it can
later be restarted.
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
89
SPSR — QSPI Status Register
$YFFC1F
15
8
7
6
5
4
0
3
0
2
0
1
0
SPCR3
SPIF
MODF
HALTA
CPTQP
RESET:
0
0
0
0
0
0
SPSR contains QSPI status information. Only the QSPI can assert the bits in this register. The CPU
reads this register to obtain status information and writes it to clear status flags.
SPIF — QSPI Finished Flag
0 = QSPI not finished
1 = QSPI finished
SPIF is set after execution of the command at the address in ENDQP.
MODF — Mode Fault Flag
0 = Normal operation
1 = Another SPI node requested to become the network SPI master while the QSPI was enabled
in master mode (SS input taken low).
MODF is asserted by the QSPI when the QSPI is the serial master (MSTR = 1) and the SS input pin is
negated by an external driver.
HALTA — Halt Acknowledge Flag
0 = QSPI not halted
1 = QSPI halted
HALTA is asserted when the QSPI halts in response to CPU assertion of HALT.
Bit 4 — Not Implemented
CPTQP — Completed Queue Pointer
CPTQP points to the last command executed. It is updated when the current command is complete.
When the first command in a queue is executing, CPTQP contains either the reset value ($0) or a point-
er to the last command completed in the previous queue.
5.2.3 QSPI RAM
The QSPI contains an 80-byte block of dual-access static RAM that is used by both the QSPI and the
CPU. The RAM is divided into three segments: receive data RAM, transmit data RAM, and command
control RAM. Receive data is information received from a serial device external to the MCU. Transmit
data is information stored by the CPU for transmission to an external peripheral. Command control data
is used to perform the transfer.
Refer to the following illustration of the organization of the RAM.
MOTOROLA
90
MC68HC16Z1
MC68HC16Z1TS/D
D00
RR0
RR1
RR2
D20
TR0
TR1
TR2
D40
CR0
CR1
CR2
RECEIVE
RAM
TRANSMIT
RAM
COMMAND
RAM
RRD
RRE
RRF
TRD
TRE
TRF
CRD
CRE
CRF
D1E
D3E
D4F
QSPI RAM MAP
WORD
WORD
BYTE
Figure 16 QSPI RAM Address Map
Once the CPU has set up the queue of QSPI commands and enabled the QSPI, the QSPI can operate
independently of the CPU. The QSPI executes all of the commands in its queue, sets a flag indicating
that it is finished, and then either interrupts the CPU or waits for CPU intervention. It is possible to ex-
ecute a queue of commands repeatedly without CPU intervention.
RR[0:F] — Receive Data RAM
$YFFD00
Data received by the QSPI is stored in this segment. The CPU reads this segment to retrieve data from
the QSPI. Data stored in receive RAM is right-justified. Unused bits in a receive queue entry are set to
zero by the QSPI upon completion of the individual queue entry. The CPU can access the data using
byte, word, or long-word addressing.
The CPTQP value in SPSR shows which queue entries have been executed. The CPU uses this infor-
mation to determine which locations in receive RAM contain valid data before reading them.
TR[0:F] — Transmit Data RAM
$YFFD20
Data that is to be transmitted by the QSPI is stored in this segment. The CPU usually writes one word
of data into this segment for each queue command to be executed.
Information to be transmitted must be written to transmit data RAM in a right-justified format. The QSPI
cannot modify information in the transmit data RAM. The QSPI copies the information to its data serial-
izer for transmission. Information remains in transmit RAM until overwritten.
CR[0:F] — Command RAM
$YFFD40
7
6
5
4
3
2
1
0
CONT
BITSE
DT
DSCK
PCS3
PCS2
PCS1
PCS0*
—
—
—
—
—
—
—
—
CONT
BITSE
DT
DSCK
PCS3
PCS2
PCS1
PCS0*
COMMAND CONTROL
PERIPHERAL CHIP SELECT
*The PCS0 bit represents the dual-function PCS0/SS.
Command RAM consists of 16 bytes that are divided into two fields. The peripheral chip-select field en-
ables peripherals for transfer. The command control field provides transfer options. Command RAM is
used by the QSPI when in master mode. The CPU writes one byte of control information to this segment
for each QSPI command to be executed. The QSPI cannot modify information in command RAM. A
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
91
maximum of 16 commands can be in the queue. Queue execution by the QSPI proceeds from the ad-
dress in NEWQP through the address in ENDQP (both of these fields are in SPCR2).
CONT — Continue
0 = Control of chip selects returned to PORTQS after transfer is complete.
1 = Peripheral chip selects remain asserted after transfer is complete.
BITSE — Bits per Transfer Enable
0 = 8 bits
1 = Number of bits set in BITS field of SPCR0
DT — Delay after Transfer
The QSPI provides a variable delay at the end of serial transfer to facilitate the interface with peripherals
that have a latency requirement. The delay between transfers is determined by the SPCR1 DTL field.
DSCK — PCS to SCK Delay
0 = PCS valid to SCK transition is one-half SCK.
1 = SPCR1 DSCKL field specifies delay from PCS valid to SCK.
PCS[3:0] — Peripheral Chip Select
Use peripheral chip-select bits to select an external for serial data transfer. More than one peripheral
chip select can be activated at a time, and more than one peripheral chip can be connected to each
PCS pin, provided that proper fanout is observed.
SS — Slave Mode Select
Initiates slave mode serial transfer. If SS is taken low when the QSPI is in master mode, a mode fault
will be generated.
5.2.4 Operating Modes
The QSPI operates in either master or slave mode. Master mode is used when the MCU originates data
transfers. Slave mode is used when an external device initiates serial transfers to the MCU through the
QSPI. Switching between the modes is controlled by MSTR in SPCR0. Before entering either mode,
appropriate QSM and QSPI registers must be properly initialized.
In master mode, the QSPI executes a queue of commands defined by control bits in each command
RAM queue entry. Chip-select pins are activated, data is transmitted from transmit data RAM and re-
ceived into receive data RAM.
In slave mode, operation proceeds in response to SS pin activation by an external bus master. Opera-
tion is similar to master mode, but no peripheral chip selects are generated, and the number of bits
transferred is controlled in a different manner. When the QSPI is selected, it automatically executes the
next queue transfer to exchange data with the external device correctly.
Although the QSPI inherently supports multimaster operation, no special arbitration mechanism is pro-
vided. A mode fault flag (MODF) indicates a request for SPI master arbitration. System software must
provide arbitration. Note that unlike previous SPI systems, MSTR is not cleared by a mode fault being
set, nor are the QSPI pin output drivers disabled. The QSPI and associated output drivers must be dis-
abled by clearing SPE in SPCR1.
5.3 SCI Submodule
The SCI submodule is used to communicate with external devices through an asynchronous serial bus.
The SCI is fully compatible with the SCI systems found on other Motorola MCUs, such as the M68HC11
and M68HC05 Families.
MOTOROLA
92
MC68HC16Z1
MC68HC16Z1TS/D
5.3.1 SCI Pins
There are two unidirectional pins associated with the SCI. The SCI controls the transmit data (TXD) pin
when enabled, whereas the receive data (RXD) pin remains a dedicated input pin to the SCI. TXD is
available as a general-purpose I/O pin when the SCI transmitter is disabled. When used for I/O, TXD
can be configured either as input or output, as determined by QSM register DDRQS.
The following table shows SCI pins and their functions.
Pin Names
Mnemonics
Mode
Function
Receive Data
RXD
Receiver Disabled
Receiver Enabled
Not Used
Serial Data Input to SCI
Transmit Data
TXD
Transmitter Disabled General-Purpose I/O
Transmitter Enabled Serial Data Output from SCI
5.3.2 SCI Registers
The SCI programming model includes QSM global and pin control registers, and four SCI registers.
There are two SCI control registers, one status register, and one data register. All registers can be read
or written at any time by the CPU.
Changing the value of SCI control bits during a transfer operation may disrupt operation. Before chang-
ing register values, allow the transmitter to complete the current transfer, then disable the receiver and
transmitter. Status flags in register SCSR may be cleared at any time.
SCCR0 — SCI Control Register 0
$YFFC08
15
0
14
0
13
0
12
11
10
9
8
7
6
5
4
3
2
1
0
SCBR
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
SCCR0 contains a baud rate selection parameter. Baud rate must be set before the SCI is enabled. The
CPU can read and write this register at any time.
Bits [15:13] — Not Implemented
SCBR — Baud Rate
SCI baud rate is programmed by writing a 13-bit value to SCBR. The baud rate is derived from the MCU
system clock by a modulus counter.
The SCI receiver operates asynchronously. An internal clock is necessary to synchronize with an in-
coming data stream. The SCI baud rate generator produces a receiver sampling clock with a frequency
16 times that of the expected baud rate of the incoming data. The SCI determines the position of bit
boundaries from transitions within the received waveform, and adjusts sampling points to the proper po-
sitions within the bit period. Receiver sampling rate is always 16 times the frequency of the SCI baud
rate, which is calculated as follows:
SCI Baud Rate = System Clock/(32SCBR)
or
SCBR = System Clock(32SCK)(Baud Rate desired)
where SCBR is in the range {1, 2, 3, ..., 8191}
Writing a value of zero to BR disables the baud rate generator.
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
93
SCCR1 — SCI Control Register 1
$YFFC0A
15
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LOOPS
WOMS
ILT
PT
PE
M
WAKE
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SCCR1 contains SCI configuration parameters. The CPU can read and write this register at any time.
The SCI can modify RWU in some circumstances. In general, interrupts enabled by these control bits
are cleared by reading SCSR, then reading (receiver status bits) or writing (transmitter status bits)
SCDR.
Bit 15 — Not Implemented
LOOPS — Loop Mode
0 = Normal SCI operation, no looping, feedback path disabled
1 = Test SCI operation, looping, feedback path enabled
LOOPS controls a feedback path on the data serial shifter. When loop mode is enabled, SCI transmitter
output is fed back into the receive serial shifter. TXD is asserted (idle line). Both transmitter and receiver
must be enabled before entering loop mode.
WOMS — Wired-OR Mode for SCI Pins
0 = If configured as an output, TXD is a normal CMOS output.
1 = If configured as an output, TXD is an open-drain output.
WOMS determines whether the TXD pin is an open-drain output or a normal CMOS output. This bit is
used only when TXD is an output. If TXD is used as a general-purpose input pin, WOMS has no effect.
ILT — Idle-Line Detect Type
0 = Short idle-line detect (start count on first one)
1 = Long idle-line detect (start count on first one after stop bit(s))
PT — Parity Type
0 = Even parity
1 = Odd parity
When parity is enabled, PT determines whether parity is even or odd for both the receiver and the trans-
mitter.
PE — Parity Enable
0 = SCI parity disabled
1 = SCI parity enabled
PE determines whether parity is enabled or disabled for both the receiver and the transmitter. If the re-
ceived parity bit is not correct, the SCI sets the PF error flag in SCSR.
When PE is set, the most significant bit (MSB) of the data field is used for the parity function, which re-
sults in either seven or eight bits of user data, depending on the condition of M bit. The following table
lists the available choices.
M
0
0
1
1
PE
0
Result
8 Data Bits
1
7 Data Bits, 1 Parity Bit
9 Data Bits
0
1
8 Data Bits, 1 Parity Bit
M — Mode Select
0 = SCI frame: 1 start bit, 8 data bits, 1 stop bit (10 bits total)
1 = SCI frame: 1 start bit, 9 data bits, 1 stop bit (11 bits total)
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94
MC68HC16Z1
MC68HC16Z1TS/D
WAKE — Wake-up by Address Mark
0 = SCI receiver awakened by idle-line detection
1 = SCI receiver awakened by address mark (last bit set)
TIE — Transmit Interrupt Enable
0 = SCI TDRE interrupts inhibited
1 = SCI TDRE interrupts enabled
TCIE — Transmit Complete Interrupt Enable
0 = SCI TC interrupts inhibited
1 = SCI TC interrupts enabled
RIE — Receiver Interrupt Enable
0 = SCI RDRF interrupt inhibited
1 = SCI RDRF interrupt enabled
ILIE — Idle-Line Interrupt Enable
0 = SCI IDLE interrupts inhibited
1 = SCI IDLE interrupts enabled
TE — Transmitter Enable
0 = SCI transmitter disabled (TXD pin may be used as I/O)
1 = SCI transmitter enabled (TXD pin dedicated to SCI transmitter)
The transmitter retains control of the TXD pin until completion of any character transfer that was in
progress when TE is cleared.
RE — Receiver Enable
0 = SCI receiver disabled (status bits inhibited)
1 = SCI receiver enabled
RWU — Receiver Wakeup
0 = Normal receiver operation (received data recognized)
1 = Wakeup mode enabled (received data ignored until awakened)
Setting RWU enables the wakeup function, which allows the SCI to ignore received data until awakened
by either an idle line or address mark (as determined by WAKE). When in wakeup mode, the receiver
status flags are not set, and interrupts are inhibited. This bit is cleared automatically (returned to normal
mode) when the receiver is awakened.
SBK — Send Break
0 = Normal operation
1 = Break frame(s) transmitted after completion of current frame
SBK provides the ability to transmit a break code from the SCI. If the SCI is transmitting when SBK is
set, it will transmit continuous frames of zeros after it completes the current frame, until SBK is cleared.
If SBK is toggled (one to zero in less than one frame interval), the transmitter sends only one or two
break frames before reverting to idle line or beginning to send data.
SCSR — SCI Status Register
$YFFC0C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOT USED
TDRE
TC
RDRF
RAF
IDLE
OR
NF
FE
PF
RESET:
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
SCSR contains flags that show SCI operational conditions. These flags can be cleared either by hard-
ware or by a special acknowledgment sequence. The sequence consists of SCSR read with flags set,
followed by SCDR read (write in the case of TDRE and TC). A long-word read can consecutively access
both SCSR and SCDR. This action clears receive status flag bits that were set at the time of the read,
but does not clear TDRE or TC flags.
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
95
If an internal SCI signal for setting a status bit comes after the CPU has read the asserted status bits,
but before the CPU has written or read register SCDR, the newly set status bit is not cleared. SCSR
must be read again with the bit set. Also, SCDR must be written or read before the status bit is cleared.
Reading either byte of SCSR causes all 16 bits to be accessed. Any status bit already set in either byte
will be cleared on a subsequent read or write of register SCDR.
TDRE — Transmit Data Register Empty Flag
0 = Register TDR still contains data to be sent to the transmit serial shifter.
1 = A new character can now be written to register TDR.
TDRE is set when the byte in register TDR is transferred to the transmit serial shifter. If TDRE is zero,
transfer has not occurred and a write to TDR will overwrite the previous value. New data is not trans-
mitted if TDR is written without first clearing TDRE.
TC — Transmit Complete Flag
0 = SCI transmitter is busy
1 = SCI transmitter is idle
TC is set when the transmitter finishes shifting out all data, queued preambles (mark/idle line), or
queued breaks (logic zero). The interrupt can be cleared by reading SCSR when TC is set and then by
writing the transmit data register (TDR) of SCDR.
RDRF — Receive Data Register Full Flag
0 = Register RDR is empty or contains previously read data.
1 = Register RDR contains new data.
RDRF is set when the content of the receive serial shifter is transferred to the RDR. If one or more errors
are detected in the received word, flag(s) NF, FE, and/or PF are set within the same clock cycle.
RAF — Receiver Active Flag
0 = SCI receiver is idle
1 = SCI receiver is busy
RAF indicates whether the SCI receiver is busy. It is set when the receiver detects a possible start bit
and is cleared when the chosen type of idle line is detected. RAF can be used to reduce collisions in
systems with multiple masters.
IDLE — Idle-Line Detected Flag
0 = SCI receiver did not detect an idle-line condition.
1 = SCI receiver detected an idle-line condition.
IDLE is disabled when RWU in SCCR1 is set. IDLE is set when the SCI receiver detects the idle-line
condition specified by ILT in SCCR1. If cleared, IDLE will not set again until after RDRF is set. RDRF
is set when a break is received, so that a subsequent idle line can be detected.
OR — Overrun Error Flag
0 = RDRF is cleared before new data arrives.
1 = RDRF is not cleared before new data arrives.
OR is set when a new byte is ready to be transferred from the receive serial shifter to the RDR, and
RDRF is still set. Data transfer is inhibited until OR is cleared. Previous data in RDR remains valid, but
data received during overrun condition (including the byte that set OR) is lost.
NF — Noise Error Flag
0 = No noise detected on the received data
1 = Noise occurred on the received data
NF is set when the SCI receiver detects noise on a valid start bit, on any data bit, or on a stop bit. It is
not set by noise on the idle line or on invalid start bits. Each bit is sampled three times. If none of the
three samples are the same logic level, the majority value is used for the received data value, and NF
is set. NF is not set until an entire frame is received and RDRF is set.
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96
MC68HC16Z1
MC68HC16Z1TS/D
FE — Framing Error Flag
1 = Framing error or break occurred on the received data.
0 = No framing error on the received data.
FE is set when the SCI receiver detects a zero where a stop bit was to have occurred. FE is not set until
the entire frame is received and RDRF is set. A break can also cause FE to be set. It is possible to miss
a framing error if RXD happens to be at logic level one at the time the stop bit is expected.
PF — Parity Error Flag
1 = Parity error occurred on the received data
0 = No parity error on the received data
PF is set when the SCI receiver detects a parity error. PF is not set until the entire frame is received and
RDRF is set.
SCDR — SCI Data Register
$YFFC0E
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
7
6
5
4
3
2
1
0
R8/T8 R7/T7 R6/T6 R5/T5 R4/T4 R3/T3 R2/T2 R1/T1 R0/T0
RESET:
0
0
0
0
0
0
0
U
U
U
U
U
U
U
U
U
SCDR contains two data registers at the same address. RDR is a read-only register that contains data
received by the SCI serial interface. The data comes into the receive serial shifter and is transferred to
RDR. TDR is a write-only register that contains data to be transmitted. The data is first written to TDR,
then transferred to the transmit serial shifter, where additional format bits are added before transmis-
sion. R[7:0]/T[7:0] contain either the first eight data bits received when SCDR is read, or the first eight
data bits to be transmitted when SCDR is written. R8/T8 are used when the SCI is configured for 9-bit
operation. When it is configured for 8-bit operation, they have no meaning or effect.
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
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MOTOROLA
98
MC68HC16Z1
MC68HC16Z1TS/D
6 Standby RAM Module
This module contains a one Kbyte array of fast (two bus cycle) static RAM, which is especially useful
for system stacks and variable storage. SRAM can be mapped to any one Kbyte boundary in the ad-
dress map, but must not overlap the module control registers (overlap makes the registers inaccessi-
ble). Data can be read/written in bytes, words or long words. SRAM is powered by V
in normal
DD
operation. During power-down, SRAM contents are maintained by power from the V
input. Power
STBY
switching between sources is automatic. An address map of the SRAM control registers follows.
Table 19 SRAM Address Map
Address
$YFFB00
$YFFB02
$YFFB04
$YFFB06
$YFFB08
15
8
7
0
RAM MODULE CONFIGURATION REGISTER (RAMMCR)
RAM TEST REGISTER (RAMTST)
RAM ARRAY BASE ADDRESS REGISTER HIGH (RAMBAH)
RAM ARRAY BASE ADDRESS REGISTER LOW (RAMBAL)
RESERVED
Y = M111, where M is the logic state of the modmap (MM) bit in the SIMCR
6.1 SRAM Register Block
There are four SRAM control registers: the RAM module configuration register (RAMMCR), the RAM
test register (RAMTST), and the RAM array base address registers (RAMBAH/RAMBAL).
There is an 8-byte minimum register block size for the module. Unimplemented register addresses are
read as zeros. Writes have no effect.
6.2 SRAM Registers
The CPU16 in the MC68HC16Z1 operates only in supervisory mode. Access to the SRAM array is con-
trolled by the RASP field in RAMMCR. SRAM responds to both program and data space accesses
based on the value in the RASP field in RAMMCR. This allows code to be executed from RAM, and
permits the use of program counter relative addressing mode for operand fetches from the array.
RAMMCR — RAM Module Configuration Register
$YFFB00
15
11
9
8
7
6
5
4
3
2
1
0
STOP
0
0
0
RLCK
0
RASP
NOT USED
RESET:
1
0
0
0
0
0
1
1
Use RAMMCR to determine whether the RAM is in STOP mode or normal mode. It can also determine
in which space the array resides, and controls access to the base array registers. Reads of unimple-
mented bits always return zeros. Writes do not affect unimplemented bits.
STOP — Stop Control
0 = RAM array operates normally.
1 = RAM array enters low-power stop mode.
This bit controls whether the RAM array is in stop mode or normal operation. Reset state is one, leaving
the array configured for LPSTOP operation. In stop mode, the array retains its contents, but cannot be
read or written by the CPU. Because the CPU16 operates in supervisor mode, this bit can be read or
written at any time.
RLCK — RAM Base Address Lock
0 = SRAM base address registers are writable from IMB
1 = SRAM base address registers are locked
RLCK defaults to zero on reset. It can be written to one once.
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
99
RASP[1:0] — RAM Array Space Field
This field limits access to the SRAM array in microcontrollers that support separate user and supervisor
operating modes. Because the CPU16 operates in supervisor mode only, RASP1 has no effect.
RASP
X0
Space
Program and Data
Program
X1
RAMTST — RAM Test Register
$YFFB02
RAMTST is for factory test only. Reads of this register return zeros and writes have no effect.
RAMBAH — Array Base Address Register High
$YFFB04
15
14
13
12
11
10
9
8
0
7
6
5
4
3
2
1
0
NOT USED
ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR
23*
22*
21*
20*
19
18
17
16
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
*ADDR[23:20] is at the same logic level as ADDR19 during internal CPU master operation. ADDR[23:20] must
match ADDR19 for the chip select to be active.
RAMBAL — Array Base Address Register Low
$YFFB06
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADDR
15
ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR
14
0
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RAMBAH and RAMBAL specify an SRAM base address in the system memory map. They can only be
written while the SRAM is in low-power mode (RAMMCR STOP = 1, the default out of reset) and the
base address lock is disabled (RAMMCR RLCK = 0, the default out of reset). This prevents accidental
remapping of the array. Because the CPU16 drives ADDR[23:20] with the value of ADDR19, the value
in the ADDR[23:20] fields must match the value in the ADDR19 field for the array to be accessible.
6.3 SRAM Operation
There are five operating modes.
The RAM module is in normal mode when powered by V . The array can be accessed by byte, word,
DD
or long word. A byte or aligned word (high-order byte is at an even address) access only takes one bus
cycle or two system clocks. A long word or misaligned word access requires two bus cycles.
Standby mode is intended to preserve RAM contents when V is removed. SRAM contents are main-
DD
tained by a power source connected to the V
pin. The standby voltage is referred to as V . Cir-
SB
STBY
cuitry within the SRAM module switches to the higher of V or V with no loss of data. When SRAM
DD
SB
is powered from the V
pin, access to the array is not guaranteed. If standby operation is not desired,
STBY
connect the V
pin to V
.
STBY
SS
Reset mode allows the CPU to complete the current bus cycle before resetting. When a synchronous
reset occurs while a byte or word SRAM access is in progress, the access will be completed. If reset
occurs during the first word access of a long-word operation, only the first word access will be complet-
ed. If reset occurs during the second word access of a long word operation, the entire access will be
completed. Data being read from or written to the RAM may be corrupted by asynchronous reset.
Test mode is used for factory testing of the RAM array.
Writing the STOP bit of RAMMCR causes the SRAM module to enter stop mode. The RAM array is dis-
abled which, if necessary, allows external logic to decode SRAM addresses but all data is retained. If
V
falls below V , internal circuitry switches to V , as in standby mode. Exit the stop mode by clear-
DD
SB SB
ing the STOP bit.
MOTOROLA
100
MC68HC16Z1
MC68HC16Z1TS/D
MC68HC16Z1
MOTOROLA
101
MC68HC16Z1TS/D
7 General-Purpose Timer Module
The GPT is a simple, yet flexible 11-channel timer used in systems where a moderate degree of external
visibility and control is required. The GPT consists of two nearly independent submodules, the compare/
capture unit, and the pulse-width modulator. Refer to the following block diagram of the GPT.
PGP3/OC1
PGP0/IC1
PGP1/IC2
PGP2/IC3
PGP4/OC2/OC1
PGP5/OC3/OC1
PGP6/OC4/OC1
PGP7/IC4/OC5/OC1
CAPTURE/COMPARE UNIT
PULSE ACCUMULATOR
PRESCALER
PAI
PCLK
PWMA
PWMB
PWM UNIT
BUS INTERFACE
IMB
GPT BLOCK
Figure 17 GPT Block Diagram
GPT input capture/output compare pins are bidirectional and can be used to form an 8-bit parallel port.
The pulse-width modulator outputs can be used as general-purpose outputs. The PAI and PCLK inputs
can be used as general-purpose inputs.
MOTOROLA
102
MC68HC16Z1
MC68HC16Z1TS/D
Table 20 GPT Address Map
Address
$YFF900
$YFF902
$YFF904
$YFF906
$YFF908
$YFF90A
$YFF90C
$YFF90E
$YFF910
$YFF912
$YFF914
$YFF916
$YFF918
$YFF91A
$YFF91C
$YFF91E
$YFF920
$YFF922
$YFF924
$YFF926
$YFF928
$YFF92A
$YFF92C
15
8
7
0
GPT MODULE CONFIGURATION (GPTMCR)
(RESERVED FOR TEST)
INTERRUPT CONFIGURATION (ICR)
PGP DATA DIRECTION (DDRGP)
OC1 ACTION MASK (OC1M)
PGP DATA (PORTGP)
OC1 ACTION DATA (OC1D)
TIMER COUNTER (TCNT)
PA CONTROL (PACTL)
PA COUNTER (PACNT)
INPUT CAPTURE 1 (TIC1)
INPUT CAPTURE 2 (TIC2)
INPUT CAPTURE 3 (TIC3)
OUTPUT COMPARE 1 (TOC1)
OUTPUT COMPARE 2 (TOC2)
OUTPUT COMPARE 3 (TOC3)
OUTPUT COMPARE 4 (TOC4)
INPUT CAPTURE 4/OUTPUT COMPARE 5 (TI4/O5)
TIMER CONTROL 1 (TCTL1)
TIMER MASK 1 (TMSK1)
TIMER FLAG 1 (TFLG1)
TIMER CONTROL 2 (TCTL2)
TIMER MASK 2 (TMSK2)
TIMER FLAG 2 (TFLG2)
FORCE COMPARE (CFORC)
PWM CONTROL A (PWMA)
PWM CONTROL C (PWMC)
PWM CONTROL B (PWMB)
PWM COUNT (PWMCNT)
PWMA BUFFER (PWMBUFA) PWMB BUFFER (PWMBUFB)
GPT PRESCALER (PRESCL)
RESERVED
$YFF92E–
$YFF93F
Y = M111, where M is the logic state of the modmap (MM) bit in the SIMCR
7.1 Capture/Compare Unit
The capture/compare unit features three input capture channels, four output compare channels, and
one input capture/output compare channel (function selected by control register). These channels share
a 16-bit free-running counter (TCNT), which derives its clock from seven stages of a 9-stage prescaler
or from external clock input PCLK. This section also contains one pulse accumulator channel. The pulse
accumulator logic includes its own 8-bit counter and can operate in either event counting mode or gated
time accumulation mode. The following block diagrams show GPT compare/capture functions and the
prescaler.
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
103
SYSTEM
CLOCK
PRESCALER–DIVIDE BY
4, 8, 16, 32, 64, 128, OR 256
TCNT (HI)
TCNT (LO)
TOI
9
16-BIT FREE-RUNNING
COUNTER
TOF
1 OF 8 SELECT
CPR2 CPR1 CPR0
PCLK
INTERRUPT
REQUESTS
16-BIT TIMER BUS
TMSK1
IC1I
PIN
FUNCTIONS
TFLG1
1
2
3
4
5
6
7
8
PGP0/
IC1
16-BIT LATCH CLK
IC1F
BIT-0
BIT-1
BIT-2
TIC1 (HI)
TIC1 (LO)
IC2I
IC3I
PGP1/
IC2
16-BIT LATCH CLK
IC2F
TIC2 (HI)
TIC2 (LO)
PGP2/
IC3
16-BIT LATCH CLK
IC3F
TIC3 (HI)
TIC3 (LO)
OC1I
OC2I
OC3I
OC4I
I4/O5I
CFORC
FOC1
=
16-BIT COMPARATOR
TOC1 (HI)
OC1F
OC2F
OC3F
OC4F
TOC1 (LO)
PGP3/
OC1
BIT-3
BIT-4
BIT-5
BIT-6
BIT-7
=
16-BIT COMPARATOR
TOC2 (HI)
PGP4/
OC2/
OC1
TOC2 (LO)
FOC2
FOC3
FOC4
FOC5
=
16-BIT COMPARATOR
TOC3 (HI)
PGP5/
OC3/
OC1
TOC3 (LO)
=
16-BIT COMPARATOR
TOC4 (HI)
PGP6/
OC4/
OC1
TOC4 (LO)
=
OC5
I4/O5F
16-BIT COMPARATOR
PGP7/
IC4/
OC5/
OC1
TI4/O5 (HI) TI4/O5 (LO)
16-BIT LATCH CLK
IC4
PARALLEL
PORT PIN
CONTROL
FORCE
OUTPUT
COMPARE
STATUS
FLAGS
INTERRUPT
ENABLES
I4/O5
16 CC BLOCK
Figure 18 GPT Compare/Capture Block Diagram
MOTOROLA
104
MC68HC16Z1
MC68HC16Z1TS/D
SYSTEM CLOCK
DIVIDER
÷512
TO PULSE ACCUMULATOR
TO PULSE ACCUMULATOR
TO PULSE ACCUMULATOR
EXT
CPR2 CPR1 CPR0
÷256
÷128
÷64
÷32
÷16
÷8
TO CAPTURE/
COMPARE
TIMER
SELECT
÷4
EXT
÷128
÷64
÷32
÷16
÷8
TO
PWM UNIT
SELECT
÷4
÷2
EXT
PCLK
PIN
SYNCHRONIZER AND
DIGITAL FILTER
PPR2 PPR1 PPR0
GPT PRESCALER BLOCK
Figure 19 Prescaler Block Diagram
7.2 Pulse-Width Modulator
The pulse-width modulation submodule has two output pins. The outputs are periodic waveforms con-
trolled by a single frequency whose duty cycles can be independently selected and modified by user
software. Each PWM can be independently programmed to run in fast or slow mode. The PWM unit has
its own 16-bit free-running counter, which is clocked by an output of the nine-stage prescaler (the same
prescaler used by the compare/capture unit) or by the clock input pin, PCLK.
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
105
16-BIT DATA BUS
PWMA REGISTER
PWMB REGISTER
16-BIT
PWMBUFA REGISTER PWMBUFB REGISTER
COMPARATOR A
COMPARATOR B
R
LATCH
S
R
LATCH
S
PWMB
PIN
PWMA
PIN
F1A
BIT
F1B
BIT
ZERO DETECTOR
ZERO DETECTOR
SFA
BIT
SFB
BIT
MULTIPLEXER A
MULTIPLEXER B
0–14
16-BIT COUNTER
16-BIT TIMER BUS
FROM
PRESCALER CLOCK
16 PWM BLOCK
Figure 20 PWM Unit Block Diagram
7.3 GPT Registers
GPTMCR — GPT Module Configuration Register
$YFF900
15
STOP
RESET:
0
14
13
12
11
10
0
9
0
8
0
7
6
0
5
0
4
0
3
2
1
0
FRZ1
FRZ0
STOPP
INCP
SUPV
IARB3 IARB2 IARB1 IARB0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
The GPTMCR contains parameters for configuring the GPT.
MOTOROLA
106
MC68HC16Z1
MC68HC16Z1TS/D
STOP — Stop Clocks
0 = Internal clocks not shut down
1 = Internal clocks shut down
FRZ1 — Not implemented at this time
FRZ0 — FREEZE Response
0 = Ignore FREEZE
1 = FREEZE the current state of the GPT
STOPP — Stop Prescaler
0 = Normal operation
1 = Stop prescaler and pulse accumulator from incrementing. Ignore changes to input pins.
INCP — Increment Prescaler
0 = Has no meaning
1 = If STOPP is asserted, increment prescaler once and clock input synchronizers once.
SUPV — Supervisor/Unrestricted Data Space
0 = Registers with access controlled by SUPV are unrestricted (FC2 is a don't care).
1 = Registers with access controlled by SUPV are restricted when FC2 = 1.
Because the CPU16 in the MC68HC16Z1 operates in supervisor mode only (FC2 is always logic level
one), this bit has no effect.
IARB[3:0] — Interrupt Arbitration Identification
To enable interrupt arbitration, system software must set this field to a value between $F–$1; $F is the
highest priority. This field is initialized to $0 during reset. If the CPU recognizes a GPT interrupt request
while IARB = $0, a spurious interrupt exception is taken.
MTR — GPT Module Test Register (Reserved)
$YFF902
This address is currently unused and returns zeros if read. It is reserved for GPT factory test.
ICR — GPT Interrupt Configuration Register
$YFF904
15
14
13
12
11
0
10
9
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
IPA
IPL
IVBA
RESET:
0
0
0
0
0
0
0
0
0
0
0
IPA — Interrupt Priority Adjust
Specifies which GPT interrupt source is given highest internal priority
IPL — Interrupt Priority Level
Specifies the priority level of interrupts generated by the GPT.
IVBA — Interrupt Vector Base Address
Most significant nibble of interrupt vector numbers generated by the GPT.
DDRGP/PORTGP — Port GP Data Direction Register/Port GP Data Register
$YFF906
15
8
7
0
DDRGP
PORTGP
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
When GPT pins are used as an 8-bit port, DDRGP determines whether pins are input or output and
PORTGP holds the 8-bit data.
DDRGP[7:0] — Port GP Data Direction Register
0 = Input only
1 = Output
When PORTGP is used for general-purpose I/O, each bit in the DDRGP determines whether the cor-
responding PORTGP bit is input or output.
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
107
OC1M/OC1D — OC1 Action Mask Register/OC1 Action Data Register
$YFF908
15
14
13
12
11
10
0
9
0
8
0
7
6
5
4
0
3
0
2
0
1
0
0
0C1M
0C1D
0
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
All OC outputs can be controlled by the action of OC1. OC1M contains a mask that determines which
pins are affected. OC1D determines what the outputs are.
OC1M[5:1] — OC1 Mask Field
0 = Corresponding output compare pin is not affected by OC1 compare.
1 = Corresponding output compare pin is affected by OC1 compare.
OC1M[5:1] correspond to OC[5:1].
OC1D[5:1] — OC1 Data Field
0 = If OC1 mask bit is set, clear the corresponding output compare pin on OC1 match.
1 = If OC1 mask bit is set, set the corresponding output compare pin on OC1 match.
OC1D[5:1] correspond to OC[5:1].
TCNT — Timer Counter Register
$YFF90A
TCNT is the 16-bit free-running counter associated with the input capture, output compare, and pulse
accumulator functions of the GPT module.
PACTL/PACNT — Pulse Accumulator Control Register/Counter
$YFF90C
15
PAIS
RESET:
U
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PAEN PAMOD
PEDGE PCLKS I4/O5
PACLK
PULSE ACCUMULATOR COUNTER
0
0
0
U
0
0
0
0
0
0
0
0
0
0
0
PACTL enables the pulse accumulator and selects either event counting or gated mode. In event count-
ing mode, PACNT is incremented each time an event occurs. In gated mode, it is incremented by an
internal clock.
PAIS — PAI Pin State (Read Only)
PAEN — Pulse Accumulator System Enable
0 = Pulse accumulator disabled
1 = Pulse accumulator enabled
PAMOD — Pulse Accumulator Mode
0 = External event counting
1 = Gated time accumulation
PEDGE — Pulse Accumulator Edge Control
The effects of PEDGE and PAMOD are shown in the following table.
PAMOD
PEDGE
Effect
0
0
1
1
0
1
0
1
PAI Falling Edge Increments Counter
PAI Rising Edge Increments Counter
Zero on PAI Inhibits Counting
One on PAI Inhibits Counting
PCLKS — PCLK Pin State (Read Only)
MOTOROLA
108
MC68HC16Z1
MC68HC16Z1TS/D
I4/O5 — Input Capture 4/Output Compare 5
0 = Output compare 5 enabled
1 = Input capture 4 enabled
PACLK[1:0] — Pulse Accumulator Clock Select (Gated Mode)
PACLK[1:0]
Pulse Accumulator Clock Selected
00
01
10
11
System Clock Divided by 512
Same Clock Used to Increment TCNT
TOF Flag from TCNT
External Clock, PCLK
PACNT — Pulse Accumulator Counter
Eight-bit read/write counter used for external event counting or gated time accumulation.
TIC[1:3] — Input Capture Registers 1–3
$YFF90E, $YFF910, $YFF912
The input capture registers are 16-bit read-only registers which are used to latch the value of TCNT
when a specified transition is detected on the corresponding input capture pin. They are reset to $FFFF.
TOC[1:4] — Output Compare Registers 1–4
$YFF914, $YFF916, $YFF918, $YFF91A
The output compare registers are 16-bit read/write registers which can be used as output waveform
controls or as elapsed time indicators. For output compare functions, they are written to a desired match
value and compared against TCNT to control specified pin actions. They are reset to $FFFF.
TI4/O5 — Input Capture 4/Output Compare 5 Register
$YFF91C
This register serves either as input capture register 4 or output compare register 5, depending on the
state of I4/O5 in PACTL.
TCTL1/TCTL2 — Timer Control Registers 1–2
$YFF91E
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OM5
OL5
OM4
OL4
OM3
OL3
OM2
OL2
EDGE4
EDGE3
EDGE2
EDGE1
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TCTL1 determines output compare mode and output logic level. TCTL2 determines the type of input
capture to be performed.
OM/OL[5:2] — Output Compare Mode Bits and Output Compare Level Bits
Each pair of bits specifies an action to be taken when output comparison is successful.
OM/OL[5:2]
Action Taken
Timer Disconnected from Output Logic
Toggle OCx Output Line
00
01
10
11
Clear OCx Output Line to 0
Set OCx Output Line to 1
EDGE[4:1] — Input Capture Edge Control Bits
Each pair of bits configures input sensing logic for the corresponding input capture.
EDGE[4:1]
Configuration
Capture Disabled
00
01
10
11
Capture on Rising Edge Only
Capture on Falling Edge Only
Capture on Any (Rising or Falling) Edge
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
109
TMSK1/TMSK2 — Timer Interrupt Mask Registers 1–2
$YFF920
15
14
13
12
11
10
9
8
7
6
0
5
4
3
2
0
0
I4/O5I
OCI
ICI
TOI
PAOVI
PAII
CPROUT
CPR
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TMSK1 enables OC and IC interrupts. TMSK2 controls pulse accumulator interrupts and TCNT func-
tions.
I4/O5I — Input Capture 4/Output Compare 5 Interrupt Enable
0 = IC4/OC5 interrupt disabled
1 = IC4/OC5 interrupt requested when I4/O5F flag in TFLG1 is set
OCI[4:1] — Output Compare Interrupt Enable
0 = OC interrupt disabled
1 = OC interrupt requested when OC flag set
OCI[4:1] correspond to OC[4:1].
ICI[3:1] — Input Capture Interrupt Enable
0 = IC interrupt disabled
1 = IC interrupt requested when IC flag set
ICI[3:1] correspond to IC[3:1].
TOI — Timer Overflow Interrupt Enable
0 = Timer overflow interrupt disabled
1 = Interrupt requested when TOF flag is set
PAOVI — Pulse Accumulator Overflow Interrupt Enable
0 = Pulse accumulator overflow interrupt disabled
1 = Interrupt requested when PAOVF flag is set
PAII — Pulse Accumulator Input Interrupt Enable
0 = Pulse accumulator interrupt disabled
1 = Interrupt requested when PAIF flag is set
CPROUT — Compare/Capture Unit Clock Output Enable
0 = Normal operation for OC1 pin
1 = TCNT clock driven out OC1 pin
CPR[2:0] — Timer Prescaler/PCLK Select Field
This field selects one of seven prescaler taps or PCLK to be TCNT input.
CPR[2:0]
System Clock
Divide-by Factor
000
001
010
011
100
101
110
111
4
8
16
32
64
128
256
PCLK
MOTOROLA
110
MC68HC16Z1
MC68HC16Z1TS/D
TFLG1/TFLG2 — Timer Interrupt Flag Registers 1–2
$YFF922
15
I4/O5F
RESET:
0
14
13
12
11
10
9
8
7
6
0
5
4
3
0
2
0
1
0
0
0
OCF
ICF
TOF
PAOVF
PAIF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
These registers show condition flags that correspond to various GPT events. If the corresponding inter-
rupt enable bit in TMSK1/TMSK2 is set, an interrupt occurs.
I4/O5F — Input Capture 4/Output Compare 5 Flag
When I4/O5 in PACTL is 0, this flag is set each time TCNT matches the value in TOC5. When I4/O5 in
PACTL is 1, the flag is set each time a selected edge is detected at the I4/O5 pin.
OCF[4:1] — Output Compare Flags
An output compare flag is set each time TCNT matches the corresponding TOC register. OCF[4:1] cor-
respond to OC[4:1].
ICF[3:1] — Input Capture Flags
A flag is set each time a selected edge is detected at the corresponding input capture pin. ICF[3:1] cor-
respond to IC[3:1].
TOF — Timer Overflow Flag
This flag is set each time TCNT advances from a value of $FFFF to $0000.
PAOVF — Pulse Accumulator Overflow Flag
This flag is set each time the pulse accumulator counter advances from a value of $FF to $00.
PAIF — Pulse Accumulator Flag
In event counting mode, this flag is set when an active edge is detected on the PAI pin. In gated time
accumulation mode, PAIF is set at the end of the timed period.
CFORC/PWMC — Compare Force Register/PWM Control Register
$YFF924
15
11
10
0
9
8
7
6
4
3
2
1
0
FOC
FPWMA FPWMB PPROUT
PPR
0
SFA
SFB
F1A
F1B
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Setting a bit in CFORC causes a specific output on OC or PWM pins. PWMC sets PWM operating con-
ditions.
FOC[5:1] — Force Output Compare
0 = Has no meaning
1 = Causes pin action programmed for corresponding OC pin, but the OC flag is not set.
FOC[5:1] correspond to OC[5:1].
FPWMA — Force PWMA Value
0 = Normal PWMA operation
1 = The value of F1A is driven out on the PWMA pin, regardless of the state of PPROUT.
FPWMB — Force PWMB Value
0 = Normal PWMB operation
1 = The value of F1B is driven out on the PWMB pin.
PPROUT — PWM Clock Output Enable
0 = Normal PWM operation on PMWA
1 = TCNT clock driven out PWMA pin
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
111
PPR[2:0] — PWM Prescaler/PCLK Select
This field selects one of seven prescaler taps or PCLK to be PWMCNT input.
PPR[2:0]
System Clock
Divide-by Factor
000
001
010
011
100
101
110
111
2
4
8
16
32
64
128
PCLK
SFA — PWMA Slow/Fast Select
0 = PWMA period is 256 PWMCNT increments long.
1 = PWMA period is 32768 PWMCNT increments long.
SFB — PWMB Slow/Fast Select
0 = PWMB period is 256 PWMCNT increments long.
1 = PWMB period is 32768 PWMCNT increments long.
The following table shows the effects of SF settings on PWM frequency (16.78-MHz system clock).
PPR[2:0]
000
Prescaler Tap
Div 2 = 8.39 MHz
Div 4 = 4.19 MHz
Div 8 = 2.10 MHz
Div 16 = 1.05 MHz
Div 32 = 524 kHz
Div 64 = 262 kHz
Div 128 = 131 kHz
PCLK
SFA/B = 0
32.8 kHz
16.4 kHz
8.19 kHz
4.09 kHz
2.05 kHz
1.02 kHz
512 Hz
SFA/B = 1
256 Hz
001
128 Hz
010
64.0 Hz
32.0 Hz
16.0 Hz
8.0 Hz
011
100
101
110
4.0 Hz
111
PCLK/256
PCLK/32768
F1A — Force Logic Level One on PWMA
0 = Force logic level zero output on PWMA pin
1 = Force logic level one output on PWMA pin
F1B — Force Logic Level One on PWMB
0 = Force logic level zero output on PWMB pin
1 = Force logic level one output on PWMB pin
PWMA/PWMB — PWM Registers A/B
$YFF926, $YFF927
These registers are associated with the pulse-width value of the PWM output on the corresponding
PWM pin. A value of $00 loaded into one of these registers results in a continuously low output on the
corresponding pin. A value of $80 results in a 50% duty cycle output. Maximum value ($FF) selects an
output that is high for 255/256 of the period.
PWMCNT — PWM Count Register
PWMCNT is the 16-bit free-running counter associated with the PWM functions of the GPT module.
PWMBUFA/B — PWM Buffer Registers A/B $YFF92A, $YFF92B
$YFF928
These read-only registers contain values associated with the duty cycles of the corresponding PWM.
Reset state is $0000.
PRESCL — GPT Prescaler
$YFF92C
The 9-bit prescaler value can be read from bits [8:0] at this address. Bits [15:9] always read as zeros.
Reset state is $0000.
MOTOROLA
112
MC68HC16Z1
MC68HC16Z1TS/D
MC68HC16Z1
MOTOROLA
113
MC68HC16Z1TS/D
8 Electrical Characteristics
This section contains electrical specification tables and reference timing diagrams.
Table 21 Maximum Ratings
Rating
Symbol
Value
Unit
1,2,5
V
–0.3 to + 6.5
V
Supply Voltage
DD
1,2,3,4,5
V
–0.3 to +6.5
V
in
Input Voltage
Instantaneous Maximum Current
mA
1,4,5,6
I
25
Single pin limit (applies to all pins)
Operating Maximum Current
D
µΑ
°C
°C
4,5,6,7
I
–500 to 500
Digital input disruptive current
– 0.3 ≤ V ≤ V + 0.3
iD
V
SS
IN
DD
Operating Temperature Range
MC68HC16Z1 “C” Suffix
MC68HC16Z1 “V” Suffix
MC68HC16Z1 “M” Suffix
T
TL to TH
–40 to 85
–40 to 105
–40 to 125
A
Storage Temperature Range
T
–55 to 150
stg
1. Permanent damage can occur if maximum ratings are exceeded. Exposure to voltages or currents in excess of
recommended values affects device reliability. Device modules may not operate normally while being exposed
to electrical extremes.
2. Although sections of the device contain circuitry to protect against damage from high static voltages or electrical
fields, take normal precautions to avoid exposure to voltages higher than maximum-rated voltages
3. ll pins except TSTME/TSC.
4. All functional non-supply pins are internally clamped to V . All functional pins except EXTAL, TSTME/TSC, and
SS
XFC are internally clamped to V
.
DD
5. This parameter is periodically sampled rather than 100% tested.
6. Power supply must maintain regulation within operating V range during instantaneous and operating maxi-
DD
mum current condition.
7. Total input current for all digital input-only and all digital input/output pins must not exceed 10 mA. Exceeding
this limit can cause disruption of normal operation.
Table 22 Thermal Characteristics
Characteristic
Thermal Resistance
Symbol
Value
Unit
Θ
38
°C/W
JA
Plastic 132-Pin Surface Mount
Plastic 144-Pin Surface Mount
The average chip-junction temperature (T ) in C can be obtained from:
J
Θ
T = T + (P
)
(1)
J
A
D
JA
where
T
Θ
P
P
P
= Ambient Temperature, °C
= Package Thermal Resistance, Junction-to-Ambient, °C/W
= P +P
A
JA
D
INT
I/O
= I
ς
, Watts — Chip Internal Power
INT
I/O
DD × DD
= Power Dissipation on Input and Output Pins — User Determined
and can be neglected. An approximate relationship between P and T
For most applications P < P
I/O
INT
D
J
(if P is neglected) is:
I/O
P = K ÷ (T + 273°C)
(2)
(3)
D
J
Solving equations 1 and 2 for K gives:
K = P + (T + 273°C) + Θ × Π
D
2
D
A
JA
where K is a constant pertaining to the particular part. K can be determined from
equation (3) by measuring P (at equilibrium) for a known T . Using this value of
D
A
K, the values of P and T can be obtained by solving equations (1) and (2)
D
J
iteratively for any value of T .
A
MOTOROLA
114
MC68HC16Z1
MC68HC16Z1TS/D
Table 23 Clock Control Timing
(V and V
= 5.0 Vdc ±10%, V = 0 Vdc, T = T to T ,
DD
DDSYN
SS
A
L
H
32.768 kHz reference)
Characteristic
Symbol
Min
Max
Unit
PLL Reference Frequency Range
f
25
50
kHz
ref
1
dc
16.78
16.78
System Frequency
On-Chip PLL Frequency
f
0.131
MHz
sys
External Clock Operation
dc
—
16
20
2
t
ms
lpll
PLL Lock Time
3
f
MHz
limp
Limp Mode Clock Frequency
SYNCR X bit = 0
SYNCR X bit = 1
—
—
f
max/2
sys
f
max
sys
4,5
C
%
CLKOUT Stability
Short term
Long term
stab
–1.0
–0.5
1.0
0.5
1. All internal registers retain data at 0 Hz.
2. Assumes that stable V is applied, that an external filter capacitor with a value of 0.1 µF is attached to the
DDSYN
XFC pin, and that the crystal oscillator is stable. Lock time is measured from power-up to RESET release. This
specification also applies to the period required for PLL lock after changing the W and Y frequency control bits
in the synthesizer control register (SYNCR) while the PLL is running, and to the period required for the clock to
lock after LPSTOP.
3. Determined by the initial control voltage applied to the on-chip VCO. The X bit in SYNCR controls a divide by
two scaler on the system clock output.
4. Short-term CLKOUT stability is the average deviation from programmed frequency measured over a 2 µs interval
at maximum f . Long-term CLKOUT stability is the average deviation from programmed frequency measured
sys
over a 1 ms interval at maximum f . Stability is measured with a stable external clock applied — variation in
sys
crystal oscillator frequency is additive to this figure.
5. This parameter is periodically sampled rather than 100% tested.
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
115
Table 24 DC Characteristics
(V and V
= 5.0 Vdc ± 10%, V = 0 Vdc, T = T to T )
DD
DDSYN
SS
A
L
H
Characteristic
Symbol
Min
Max
V + 0.3
DD
Unit
Input High Voltage
Input Low Voltage
V
0.7 (ς
)
V
IH
DD
V
V
– 0.3 0.2 (ς )
DD
V
V
IL
SS
1,9
V
0.5
–2.5
—
HYS
Input Hysteresis
2
I
2.5
µA
in
Input Leakage Current
V =V or V
All input-only pins except ADC pins
in
DD
SS
2
I
µA
High Impedance (Off-State) Leakage Current
V =V or V
OZ
–2.5
– 0.2
DD
2.5
—
All input/output and output pins
in
DD
SS
2,3
V
V
V
V
V
V
V
CMOS Output High Voltage
OH
I
= –10.0 µA
Group 1, 2, 4 input/output and all output pins
OH
2
V
—
0.2
—
CMOS Output Low Voltage
= 10.0 µA
OL
I
Group 1, 2, 4 input/output and all output pins
Group 1, 2, 4 input/output and all output pins
OL
2,3
V
– 0.8
DD
Output High Voltage
=–0.8 mA
OH
I
OH
2
V
Output Low Voltage
OL
—
—
—
0.4
0.4
0.4
I
I
I
= 1.6 mA Group 1 I/O Pins, CLKOUT, FREEZE/QUOT, IPIPE0
OL
OL
OL
= 5.3 mA
= 12 mA
Group 2 and Group 4 I/O Pins, CSBOOT, BG/CS
Group 3
Three State Control Input High Voltage
V
1.6 (V )
DD
9.1
V
IHTSC
5
I
µA
MSP
Data Bus Mode Select Pull-up Current
—
–15
–120
—
V = V
DATA[15:0]
DATA[15:0]
in
IL
V = V
in
IH
6
V
Supply Current
DD
I
—
—
—
110
350
5
mA
µA
mA
4
DD
RUN
S
IDD
IDD
LPSTOP, 32.768 kHz crystal, VCO Off (STSIM = 0)
LPSTOP (External clock input frequency = maximum f
)
S
sys
Clock Synthesizer Operating Voltage
V
4.5
5.5
V
DDSYN
6
V
Supply Current
DDSYN
I
I
—
—
—
—
1
5
150
100
mA
mA
µA
DDSYN
DDSYN
32.768 kHz crystal, VCO on, maximum f
sys
External Clock, maximum f
sys
S
I
LPSTOP, 32.768 kHz crystal, VCO off (STSIM = 0)
IDDSYN
µA
32.768 kHz crystal, V powered down
DD
DDSYN
7
V
V
RAM Standby Voltage
SB
0.0
3.0
5.5
5.5
Specified V applied
DD
V
= V
SS
DD
7
RAM Standby Current
Specified V applied
I
–2.5
—
2.5
50
µA
µA
SB
SB
DD
I
V
= V
SS
DD
8
P
—
605
mW
pF
Power Dissipation
D
in
2,9
C
—
—
10
20
Input Capacitance
All input-only pins except ADC pins
All input/output pins
2
Load Capacitance
—
—
—
—
90
pF
Group 1 I/O Pins and CLKOUT, FREEZE/QUOT, IPIPE0
Group 2 I/O Pins and CSBOOT, BG/CS
Group 3 I/O pins
C
100
130
200
L
Group 4 I/O pins
MOTOROLA
116
MC68HC16Z1
MC68HC16Z1TS/D
NOTES:
1. Applies to:
Port ADA [7:0] — AN[7:0]
Port E [7:4] SIZ[1:0], AS, DS
Port F [7:0] IRQ[7:1], MODCLK
Port GP [7:0] — IC4/OC5/OC1, IC[3:1], OC[4:1]/OC1
Port QS [7:0] — TXD, PCS[3:1],ÊPCS0/SS, SCK, MOSI, MISO
BKPT/DSCLK, DSI/IPIPE1, PAI, PCLK, RESET, RXD, TSTME/TSC
2. Input-Only Pins: TSTME/TSC, BKPT/DSCLK, PAI, PCLK, RXD
Output-Only Pins: CSBOOT, BG/CS1, CLKOUT, FREEZE/QUOT, DS0/IPIPE0, PWMA, PWMB
Input/Output Pins:
Group 1:
Port GP [7:0] — IC4/OC5/OC1, IC[3:1], OC[4:1]/OC1
DATA[15:0], DSI/IPIPE1
Group 2:
Port C [6:0] — ADDR[22:19]/CS[9:6], FC[2:0]/CS[5:3]
Port E [7:0] —SIZ[1:0], AS, DS, AVEC, DSACK[1:0]
Port F [7:0] — IRQ[7:1], MODCLK
Port QS [7:3] — TXD, PCS[3:1],ÊPCS0/SS
ADDR23/CS10/ECLK, ADDR[18:0], R/W, BERR, BR/CS0, BGACK/CS2
HALT, RESET
Group 3:
Group4:
MISO, MOSI, SCK
3. Does not apply to HALT and RESET because they are open drain pins. Does not apply to Port QS [7:0] (TXD,
PCS[3:1],ÊPCS0/SS, SCK, MOSI, MISO) in wired-OR mode.
4. Current measured with system clock frequency of 16.78 MHz, all modules active.
5. Use of an active pulldown device is recommended.
6.Total operating current is the sum of the appropriate V supply and V
supply currents.
DD
DDSYN
7.The SRAM module will not switch into standby mode as long as V does not exceed V by more than 0.5 Volt.
SB
DD
The SRAM array cannot be accessed while the module is in standby mode.
8. Power dissipation measured with system clock frequency of 16.78 MHz, all modules active. Power dissipation is
calculated using the following expression:
P
Maximum V (Ι
+ I
)
D =
DD DDSYN
DD
9. This parameter is periodically sampled rather than 100% tested.
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
117
Table 25 AC Timing
(V and V
= 5.0 Vdc ± 10%, V = 0 Vdc, T = T to T )
DD
DDSYN
SS
A
L
H
Num
Characteristic
Symbol
Min
Max
Unit
2
Frequency of Operation (32.768 kHz crystal)
f
0.13
16.78
MHz
F1
1
Clock Period
t
59.6
476
64
24
236
32
—
—
—
0
—
—
—
—
—
—
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
1A
ECLK Period
t
t
Ecyc
Xcyc
3
External Clock Input Period
Clock Pulse Width
1B
2, 3
t
CW
2A, 3A ECLK Pulse Width
t
ECW
3
External Clock Input High/Low Time
CLKOUT Rise and Fall Time
t
XCHL
2B, 3B
4, 5
t
Crf
4A, 5A Rise and Fall Time (All Outputs except CLKOUT)
4B, 5B External Clock Input Rise and Fall Time
t
8
rf
t
5
XCrf
6
7
8
9
Clock High to ADDR, FC, SIZE Valid
t
29
59
—
25
15
—
29
—
—
—
—
—
59
—
29
29
—
—
29
—
—
—
—
—
80
—
55
—
90
50
29
CHAV
Clock High to ADDR, DATA, FC, SIZE High Impedance
Clock High to ADDR, FC, SIZE, Invalid
Clock Low to AS, DS, CS Asserted
t
0
CHAZx
CHAZn
t
0
t
t
2
CLSA
STSA
AVSA
CLSN
4
AS to DS or CS Asserted (Read)
–15
15
2
9A
11
12
ADDR, FC, SIZE Valid to AS, CS, (and DS Read) Asserted
Clock Low to AS, DS, CS Negated
t
t
13
AS, DS, CS Negated to ADDR, FC, SIZE Invalid (Address Hold)
AS, CS Width Asserted
t
15
100
45
40
40
—
15
0
SNAI
14
t
SWA
14A
14B
DS, CS Width Asserted (Write)
t
SWAW
t
SWDW
AS, CS Width Asserted (Fast Cycle)
5
AS, DS, CS Width Negated
t
SN
15
16
17
18
20
21
22
23
24
25
26
27
27A
28
Clock High to AS, DS, R/W High Impedance
AS, DS, CS Negated to R/W High
t
CHSZ
SNRN
CHRH
t
Clock High to R/W High
t
Clock High to R/W Low
t
t
t
0
CHRL
RAAA
RASA
R/W High to AS, CS Asserted
15
70
—
15
15
15
5
R/W Low to DS, CS Asserted (Write)
Clock High to Data Out Valid
t
CHDO
Data Out Valid to Negating Edge of AS, CS
DS, CS Negated to Data Out Invalid (Data Out Hold)
Data Out Valid to DS, CS Asserted (Write)
Data In Valid to Clock Low (Data Setup)
Late BERR, HALT Asserted to Clock Low (Setup Time)
AS, DS Negated to DSACKx, BERR, HALT, AVEC Negated
DS, CS Negated to Data In Invalid (Data In Hold)
DS, CS Negated to Data In High Impedance
CLKOUT Low to Data In Invalid (Fast Cycle Hold)
CLKOUT Low to Data In High Impedance
DSACKx Asserted to Data In Valid
t
DVASN
t
SNDOI
t
DVSA
t
DICL
t
20
0
BELCL
t
SNDN
6
t
0
29
SNDI
SHDI
6, 7
t
—
15
—
—
—
29A
6
t
CLDI
30
6
t
CLDH
30A
8
t
DADI
31
33
Clock Low to BG Asserted/Negated
t
CLBAN
MOTOROLA
118
MC68HC16Z1
MC68HC16Z1TS/D
Table 25 AC Timing (Continued)
(V and V
= 5.0 Vdc ± 10%, V = 0 Vdc, T = T to T )
DD
DDSYN
SS
A
L
H
Num
Characteristic
BR Asserted to BG Asserted
Symbol
Min
Max
Unit
9
t
1
—
t
t
t
t
35
BRAGA
cyc
cyc
cyc
cyc
37
39
BGACK Asserted to BG Negated
BG Width Negated
t
1
2
2
GAGN
t
—
—
—
—
—
GH
39A
46
BG Width Asserted
t
1
GA
R/W Width Asserted (Write or Read)
R/W Width Asserted (Fast Write or Read Cycle)
t
150
90
5
ns
ns
ns
RWA
46A
47A
t
RWAS
Asynchronous Input Setup Time
t
AIST
BR, BGACK, DSACKx, BERR, AVEC, HALT
47B
Asynchronous Input Hold Time
t
15
—
0
—
30
—
28
—
29
—
—
—
—
—
—
—
10
40
40
10
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AIHT
10
DSACKx Asserted to BERR, HALT Asserted
Data Out Hold from Clock High
t
48
DABA
DOCH
53
54
t
Clock High to Data Out High Impedance
R/W Asserted to Data Bus Impedance Change
Clock Low to Data Bus Driven (Show Cycle)
Data Setup Time to Clock Low (Show Cycle)
Data Hold from Clock Low (Show Cycle)
BKPT Input Setup Time
t
—
40
0
CHDH
55
t
RADC
70
t
SCLDD
71
t
15
10
15
10
20
0
SCLDS
t
SCLDH
72
73
t
BKST
BKHT
74
BKPT Input Hold Time
t
75
Mode Select Setup Time
t
t
cyc
MSS
76
Mode Select Hold Time
t
ns
MSH
11
77
t
4
t
RSTA
RSTR
cyc
cyc
RESET Assertion Time
12
78
t
—
3
t
RESET Rise Time
13
100
101
102
103
104
105
t
t
ns
ns
ns
ns
ns
ns
CHP1A
CHP2A
CLKOUT High to Phase 1 Asserted
13
3
CLKOUT High to Phase 2 Asserted
13
t
—
—
—
—
P1VSA
Phase 1 Valid to AS or DS Asserted
13
t
P2VSN
Phase 2 Valid to AS or DS Negated
13
t
SAP1A
SNP2N
AS or DS Valid to Phase 1 Asserted
13
t
AS or DS Negated to Phase 2 Negated
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
119
NOTES:
1. All AC timing is shown with respect to 20% V and 70% V levels unless otherwise noted.
DD
DD
2. Minimum system clock frequency is four times the crystal frequency, subject to specified limits.
3. Minimum external clock high and low times are based on a 50% duty cycle. The minimum allowable t
period
Xcyc
will be reduced when the duty cycle of the external clock signal varies. The relationship between external clock
input duty cycle and minimum t is expressed:
Xcyc
Minimum t
period = minimum t
/ (50% – external clock input duty cycle tolerance).
Xcyc
XCHL
To achieve maximum operating frequency (f ) while using an external clock input, adjust clock input duty cycle
sys
to obtain a 50% duty cycle on CLKOUT.
4. Specification 9A is the worst-case skew between AS and DS or CS. The amount of skew depends on the relative
loading of these signals. When loads are kept within specified limits, skew will not cause AS and DS to fall out-
side the limits shown in specification 9.
5. If multiple chip selects are used, CS width negated (specification 15) applies to the time from the negation of a
heavily loaded chip select to the assertion of a lightly loaded chip select. The CS width negated specification
between multiple chip selects does not apply to chip selects being used for synchronous ECLK cycles.
6. Hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT on fast
cycle reads. The user is free to use either hold time.
7. Maximum value is equal to (t / 2) + 25 ns.
cyc
8. If the asynchronous setup time (specification 47A) requirements are satisfied, the DSACKx low to data setup
time (specification 31) and DSACKx low to BERR low setup time (specification 48) can be ignored. The data
must only satisfy the data-in to clock low setup time (specification 27) for the following clock cycle. BERR must
satisfy only the late BERR low to clock low setup time (specification 27A) for the following clock cycle.
9. To ensure coherency during every operand transfer, BG is not asserted in response to BR until after all cycles
of the current operand transfer are complete.
10. In the absence of DSACKx, BERR is an asynchronous input using the asynchronous setup time (specification
47A).
11. After external RESET negation is detected, a short transition period (approximately 2 t ) elapses, then the SIM
cyc
drives RESET low for 512 t
.
cyc
12. External logic must pull RESET high during this period in order for normal MCU operation to begin.
13. Eight pipeline states are multiplexed into IPIPE[1:0]. The multiplexed signals have two phases.
14. Address access time = (2.5 + WS) t – t
– t
cyc
CHAV
DICL
Chip select access time = (2 + WS) t – t
– t
DICL
cyc
CLSA
Where: WS = number of wait states. When fast termination is used (2 clock bus) WS = –1.
MOTOROLA
120
MC68HC16Z1
MC68HC16Z1TS/D
Table 26 Background Debugging Mode Timing
(V = 5.0 Vdc ± 10%, V = 0 Vdc, T = T to T )
DD
SS
A
L
H
Num
Characteristic
Symbol
Min
Max
Unit
B0
DSI Input Setup Time
DSI Input Hold Time
DSCLK Setup Time
DSCLK Hold Time
DSO Delay Time
t
15
—
ns
DSISU
B1
B2
B3
B4
B5
B6
B7
B8
B9
t
10
15
10
—
2
—
—
—
25
—
50
50
50
—
ns
ns
ns
ns
DSIH
t
DSCSU
t
DSCH
DSOD
t
DSCLK Cycle Time
t
t
cyc
DSCCYC
CLKOUT High to FREEZE Asserted/Negated
CLKOUT High to IPIPE1 High Impedance
CLKOUT High to IPIPE1 Valid
t
—
—
—
1
ns
ns
ns
FRZAN
t
IFZ
t
IF
DSCLO
DSCLK Low Time
t
t
cyc
NOTES:
1. All AC timing is shown with respect to 20% V and 70% V levels unless otherwise noted.
DD
DD
Table 27 ECLK Bus Timing
(V = 5.0 Vdc ± 10%, V = 0 Vdc, T = T to T )
DD
SS
A
L
H
Num
Characteristic
Symbol
Min
Max
Unit
2
ECLK Low to Address Valid
t
—
60
ns
E1
EAD
EAH
E2
E3
E4
E5
E6
E7
E8
E9
ECLK Low to Address Hold
ECLK Low to CS Valid (CS delay)
ECLK Low to CS Hold
t
10
—
15
30
30
15
—
0
—
150
—
—
—
—
60
—
1
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
ECSD
ECSH
ECSN
EDSR
EDHR
CS Negated Width
Read Data Setup Time
Read Data Hold Time
t
ECLK Low to Data High Impedance
CS Negated to Data Hold (Read)
t
EDHZ
ECDH
t
E10 CS Negated to Data High Impedance
E11 ECLK Low to Data Valid (Write)
E12 ECLK Low to Data Hold (Write)
E13 CS Negated to Data Hold (Write)
3
t
—
—
5
t
t
ECDZ
cyc
cyc
t
t
t
2
EDDW
EDHW
ECHW
—
—
—
—
1/2
ns
ns
ns
ns
0
Address Access Time (Read)
t
386
296
—
E14
E15
EACC
4
Chip Select Access Time (Read)
t
EACS
E16 Address Setup Time
t
t
cyc
EAS
NOTES:
1. All AC timing is shown with respect to 20% V and 70% V levels unless otherwise noted.
DD
DD
2. When previous bus cycle is not an ECLK cycle, the address may be valid before ECLK goes low.
3. Address access time = t
– t
– t
Ecyc
EAD
EDSR
4. Chip select access time = t
– t
– t
Ecyc
ECSD EDSR
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
121
Table 28 QSPI Timing
(V = 5.0 Vdc ± 10%, V = 0 Vdc, T = T to T , 200 pF load on all QSPI pins)
DD
SS
A
L
H
Num
Function
Symbol
Min
Max
Unit
Operating Frequency
Master
Slave
f
op
DC
DC
1/4
1/4
System Clock Frequency
System Clock Frequency
1
2
Cycle Time
Master
Slave
t
qcyc
4
4
510
—
t
t
cyc
cyc
Enable Lead Time
Master
Slave
t
lead
2
2
128
—
t
t
cyc
cyc
3
4
Enable Lag Time
Master
Slave
t
lag
—
2
1/2
—
SCK
t
cyc
Clock (SCK) High or Low Time
Master
t
sw
2 t
–
255 t
—
ns
ns
cyc
cyc
2
Slave
60
2 t – n
cyc
5
Sequential Transfer Delay
Master
t
td
17
13
8192
—
t
cyc
Slave (Does Not Require Deselect)
t
cyc
6
7
Data Setup Time (Inputs)
Master
Slave
t
su
30
20
—
—
ns
ns
Data Hold Time (Inputs)
Master
Slave
t
hi
0
20
—
—
ns
ns
8
9
Slave Access Time
t
—
—
1
2
t
a
cyc
cyc
Slave MISO Disable Time
t
t
dis
10 Data Valid (after SCK Edge)
t
v
Master
Slave
—
—
50
50
ns
ns
11 Data Hold Time (Outputs)
t
ho
Master
Slave
0
0
—
—
ns
ns
12 Rise Time
Input
t
—
—
2
30
µσ
νσ
ri
Output
t
ro
13 Fall Time
Input
t
—
—
2
30
µσ
νσ
fi
Output
t
fo
NOTES:
1. All AC timing is shown with respect to 20% V and 70% V levels unless otherwise noted.
DD
DD
2. In formula, n = External SCK rise + External SCK fall time.
MOTOROLA
122
MC68HC16Z1
MC68HC16Z1TS/D
Table 29 ADC Maximum Ratings
Num
Parameter
Symbol
Min
Max
Unit
1
Analog Supply
V
– 0.3
6.5
V
DDA
2
3
4
5
6
7
8
Internal Digital Supply
Reference Supply
V
– 0.3
– 0.3
– 0.1
– 6.5
– 6.5
– 6.5
– 15
6.5
6.5
0.1
6.5
6.5
6.5
15
V
V
DDI
V
, V
RL
RH
V
V
V
V
Differential Voltage
Differential Voltage
V
V
V
SS
SSI – SSA
V
V
V
DD
DDI – DDA
Differential Voltage
V
V
V
REF
REF
RH – RL
to V
Differential Voltage
V
V
V
DDA
RH – DDA
1, 2, 3, 4
I
µA
NA
Disruptive Input Current
– 0.3 ≤ V
V
≤ V
+ 2
SSA
INA
DDA
5, 3
9
I
– 500
500
µA
MA
Maximum Input Current
V
– 1 ≤ V
≤ V
+ 3.5
SSA
INA
DDA
1. Below disruptive current conditions, the channel being stressed will have conversion values of $3FF for analog
inputs greater than V and $000 for values less than V . This assumes that V ≤ V and V ≥ V due
RH
RL
RH
DDA
RL
SSA
to the presence of the sample amplifier. Other channels are not affected by non-disruptive conditions.
2. Input signals with large slew rates or high frequency noise components cannot be converted accurately. These
signals also interfere with conversion of other channels.
3. This parameter is periodically sampled rather than 100% tested.
4. Applies to single pin only.
5. Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions
within the limit do not affect device reliability or cause permanent damage.
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
123
Table 30 ADC DC Electrical Characteristics (Operating)
(V = 0 Vdc, ADCLK = 2.1 MHz, T within operating temperature range)
SS
A
Num
Parameter
Symbol
Min
Max
Unit
1
1
V
4.5
5.5
V
Analog Supply
DDA
1
2
3
4
5
6
7
V
4.5
5.5
1.0
1.0
V
mV
V
DDI
Internal Digital Supply
V
V
Differential Voltage
Differential Voltage
V
V
– 1.0
– 1.0
SS
DD
SSI – SSA
V
V
DDI – DDA
2,3
V
V
V / 2
DDA
V
RL
SSA
Reference Voltage Low
2,3
V
V
/ 2
V
DDA
V
RH
DDA
Reference Voltage High
3
V
V
RH – RL
4.5
5.5
V
V
Differential Voltage
REF
2
8
9
V
V
V
DDA
V
V
Input Voltage
INDC
SSA
Input High, Port ADA
V
0.7 (V
)
V
+ 0.3
IH
DDA
DDA
10 Input Low, Port ADA
V
V
– 0.3
0.2 (V )
DDA
V
IL
SSA
4
15
I
—
1.0
mA
µA
µA
nA
pF
pF
DDA
Analog Supply Current
16 Analog Supply Current, LPSTOP
17 Reference Supply Current
S
—
—
—
—
—
TBD
250
250
10
DDA
REF
OFF
I
I
5
18
Input Current, Off Channel
19 Total Input Capacitance, Not Sampling
20 Total Input Capacitance, Sampling
C
C
INN
15
INS
1. Refers to operation over full temperature and frequency range.
2. To obtain full-scale, full-range results, V ≤ V ≤ V ≤ V ≤ V
DDA.
SSA
RL
INDC
RH
3. Accuracy tested and guaranteed at V
V
≤ 5.0 V ± 10%.
RH – RL
4. Current measured at maximum system clock frequency with ADC active.
5. Maximum leakage occurs at maximum operating temperature. Current decreases by approximately one-
half for each 10° C decrease from maximum temperature.
Table 31 ADC AC Characteristics (Operating)
(V and V
= 5.0 Vdc ± 10%, V = 0 Vdc, T within operating temperature range)
DD
DDA
SS
A
Num
Parameter
Symbol
Min
Max
Unit
1
IMB Clock Frequency
ADC Clock Frequency
F
2.0
16.78
MHz
ICLK
2
3
4
5
F
0.5
7.62
8.58
—
2.1
—
MHz
µs
ADCLK
1
T
CONV
CONV
8-bit Conversion Time (16 ADC Clocks)
1
T
—
µs
10-bit Conversion Time (18 ADC Clocks)
Stop Recovery Time
T
10
µs
SR
1. Assumes 2.1 MHz ADC clock and selection of minimum sample time (2 ADC clocks).
MOTOROLA
124
MC68HC16Z1
MC68HC16Z1TS/D
Table 32 ADC Conversion Characteristics (Operating)
(V and V
= 5.0 Vdc ± 10%, V = 0 Vdc, T = T to T , ADCLK = 2.1 MHz)
DD
DDA
SS
A
L
H
Num
Parameter
Symbol
Min
Typ
Max
Unit
1
1
1 Count
—
20
—
—
—
5
—
mV
8-bit Resolution
2
2
3
4
5
6
7
8
9
DNL
INL
–.5
–1
.5
Counts
Counts
Counts
mV
8-bit Differential Nonlinearity
2
1
8-bit Integral Nonlinearity
2,3
AE
–1
1
8-bit Absolute Error
1
1 Count
DNL
INL
—
—
10-bit Resolution
2
–1
—
—
—
20
1
Counts
Counts
Counts
k∫
10-bit Differential Nonlinearity
2
–2
2
10-bit Integral Nonlinearity
2,4
AE
–2.5
—
2.5
10-bit Absolute Error
5
R
See Note 5
S
Source Impedance at Input
1. V – V ≥ 5.12 V; V
– V
= 5.12 V
RH
RL
DDA
SSA
2. At V
= 5.12 V, one 10-bit count = 5 mV and one 8-bit count = 20 mV.
REF
3. 8-bit absolute error of 1 count (20 mV) includes 1/2 count (10 mV) inherent quantization error and 1/2 count
(10 mV) circuit (differential, integral, and offset) error.
4. 10-bit absolute error of 2.5 counts (12.5 mV) includes 1/2 count (2.5 mV) inherent quantization error and 2
counts (10 mV) circuit (differential, integral, and offset) error.
5. Maximum source impedance is application-dependent. Error resulting from pin leakage depends on junction
leakage into the pin and on leakage due to charge-sharing with internal capacitance. In the following expres-
sions, expected error in result value due to leakage is expressed in voltage (V ).
errx
Error from junction leakage is a function of external source impedance and input leakage current:
V
= R × Ι
errj
S OFF
where I
is a function of operating temperature. (See Table A–10, note 4).
OFF
Charge-sharing leakage is a function of ADC clock speed, number of channels scanned, and source imped-
ance:
For 10-bit conversion, V
=.25 pF × V
× R ADCLK ÷ (9 × number of channels)
err10
DDA S ×
For 8-bit conversion, V
=.25 pF × V
× R × ADCLK ÷ (8 × number of channels)
err8
DDA S
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
125
TIMING DIAGRAMS
1
4
2
3
CLKOUT
5
16 CLKOUT TIM
NOTE: Timing shown with respect to 20% and 70% V
.
DD
Figure 21 CLKOUT Output Timing Diagram
1B
4B
2B
3B
EXTAL
5B
16 EXT CLK INPUT TIM
NOTE: Timing shown with respect to 20% and 70% V . Pulse width shown with respect to 50% V
.
DD
DD
Figure 22 External Clock Input Timing Diagram
1A
4A
2A
3A
ECLK
5A
16 ECLK OUTPUT TIM
NOTE: Timing shown with respect to 20% and 70% V
.
DD
Figure 23 ECLK Output Timing Diagram
MOTOROLA
126
MC68HC16Z1
MC68HC16Z1TS/D
S0
S1
6
S2
S3
S4
S5
8
CLKOUT
A20–A23
FC0–FC2
SIZ0, SIZ1
AS
11
14
15
13
9
DS
9A
12
CS
18
21
20
R/W
46
DSACK0
DSACK1
D0–D15
BERR
47A
28
29
31
27
29A
48
73
27A
HALT
74
BKPT
47A
47B
ASYNCHRONOUS
INPUTS
100
101
PHASE 1
105
IPIPE0
IPIPE1
PHASE 2
102
104
103
16 RD CYC TIM
Figure 24 Read Cycle Timing Diagram
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
127
S0
S1
6
S2
S3
S4
S5
8
CLKOUT
ADDR[23:20]
FC[2:0]
SIZ0, SIZ1
AS
11
14
15
13
9
DS
9
12
CS
20
22
14A
17
R/W
46
DSACK0
DSACK1
DATA[15:0]
BERR
47A
28
25
55
54
26
53
23
48
27A
HALT
73
74
BKPT
100
101
105
IPIPE0
IPIPE1
PHASE 1
PHASE 2
102
104
103
16 WR CYC TIM
Figure 25 Write Cycle Timing Diagram
MOTOROLA
128
MC68HC16Z1
MC68HC16Z1TS/D
S0
S41
S42
S43
8
S0
S1
S2
CLKOUT
6
ADDR[23:20]
18
R/W
20
AS
12
70
9
15
DS
71
72
DATA[15:0]
27A
BKPT
100
101
105
PHASE 1
IPIPE0
IPIPE1
PHASE 1
PHASE 2
104
PHASE 2
102
103
START OF
EXTERNAL CYCLE
SHOW CYCLE
16 SHW CYC TIM
Figure 26 Show Cycle Timing Diagram
77
78
RESET
75
DATA[15:0],
MODCLK,
BKPT
76
16 RST/MODE SEL TIM
Figure 27 Data Bus Mode Select Timing Diagram
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
129
S0
S1
S2
S3
S4
S5
S98
A5
A5
A2
CLKOUT
ADDR[23:0]
DATA[15:0]
7
AS
DS
16
R/W
DSACK0
DSACK1
47A
BR
BG
39A
35
33
33
BGACK
37
100
PHASE 1
102
101
IPIPE0
IPIPE1
PHASE 2
104
103
105
16 BUS ARB TIM
Figure 28 Bus Arbitration Timing Diagram — Active Bus Case
MOTOROLA
130
MC68HC16Z1
MC68HC16Z1TS/D
A0
A5
A5
A2
A3
A0
CLKOUT
ADDR[23:0]
DATA[15:0]
AS
47A
47A
BR
BG
35
37
47A
33
33
BGACK
16 BUS ARB TIM IDLE
Figure 29 Bus Arbitration Timing Diagram — Idle Bus Case
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
131
S0
S1
S4
S5
S0
CLKOUT
8
6
ADDR[23:0]
FC[2:0]
SIZ[1:0]
AS
14B
12
9
DS
CS
20
18
46A
R/W
30
30A
27
DATA[15:0]
29A
73
29
BKPT
74
100
101
IPIPE0
IPIPE1
PHASE 1
102
PHASE 2
105
104
103
Figure 30 Fast Termination Read Cycle Timing Diagram
MOTOROLA
132
MC68HC16Z1
MC68HC16Z1TS/D
S0
S1
S4
S5
S0
CLKOUT
6
8
ADDR[23:0]
FC[1:0]
SIZ[1:0]
14B
AS
DS
9
12
CS
20
46A
R/W
24
18
23
DATA[15:0]
27A
25
BKPT
100
101
105
IPIPE0
IPIPE1
PHASE 1
PHASE 2
103
102
104
Figure 31 Fast Termination Write Cycle Timing Diagram
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
133
CLKOUT
ECLK
2A
3A
1A
R/W
E1
E2
ADDR[23:0]
E5
E3
E14
E13
E4
CS
E6
E15
E9
DATA[15:0]
READ
E7
WRITE
E8
E11
E10
DATA[15:0]
WRITE
E12
HC16 E CYCLE TIM
NOTE: Shown with ECLK = system clock/8 — EDIV bit in clock synthesizer control register (SYNCR) = 0.
Figure 32 ECLK Timing Diagram
MOTOROLA
134
MC68HC16Z1
MC68HC16Z1TS/D
S0
S1
S2
S3
S4
S5
S0
S1
S2
S3
S4
S5
CLKOUT
8
6
6
ADDR[23:0]
FC[2:0]
SIZ[1:0]
14
11
11
14
13
AS
DS
15
9
9
9
12
17
17
21
12
CS
20
18
14A
18
46
R/W
46
25
29
55
DATA[15:0]
29A
53
23
27
54
16 CHIP SEL TIM
NOTE: AS and DS timing shown for reference only.
Figure 33 Chip Select Timing Diagram
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
135
CLKOUT
FREEZE
B3
B2
BKPT/DSCLK
B9
B5
B1
B0
IPIPE1/DSI
IPIPE0/DSO
B4
16 BDM SER COM TIM
Figure 34 Background Debugging Mode Timing Diagram — Serial Communication
CLKOUT
B6
B6
FREEZE
B11
B7
B10
IPIPE1/DSI
B8
16 BDM FRZ TIM
Figure 35 Background Debugging Mode Timing Diagram —Freeze Assertion
MOTOROLA
136
MC68HC16Z1
MC68HC16Z1TS/D
3
2
PCS[3:0]
OUTPUT
5
13
12
SCK
CPOL=0
OUTPUT
4
1
SCK
CPOL=1
OUTPUT
12
6
4
13
7
MISO
INPUT
MSB IN
DATA
LSB IN
MSB IN
11
10
LSB OUT
MOSI
OUTPUT
MSB OUT
DATA
PORT DATA
12
MSB OUT
PD
13
16 QSPI MAST CPHA0
Figure 36 QSPI Timing Master, CPHA = 0
3
2
PCS[3:0]
OUTPUT
5
13
12
1
SCK
CPOL=0
OUTPUT
4
1
7
SCK
CPOL=1
OUTPUT
12
4
13
6
MISO
INPUT
DATA
DATA
LSB IN
MSB
MSB
MSB IN
11
10
LSB OUT
MOSI
OUTPUT
MSB OUT
PORT DATA
12
PORT DATA
13
16 QSPI MAST CPHA1
Figure 37 QSPI Timing Master, CPHA = 1
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
137
3
2
SS
INPUT
5
13
12
SCK
CPOL=0
INPUT
4
1
SCK
CPOL=1
INPUT
12
4
13
11
10
11
8
9
MISO
OUTPUT
MSB OUT
DATA
LSB OUT
PD
13
MSB OUT
MSB IN
7
6
MOSI
INPUT
MSB IN
DATA
LSB IN
16 QSPI SLV CPHA0
Figure 38 QSPI Timing Slave, CPHA = 0
SS
INPUT
5
1
13
4
12
SCK
CPOL=0
INPUT
4
3
2
SCK
CPOL=1
INPUT
12
13
11
10
9
10
8
SLAVE
LSB OUT
MISO
OUTPUT
PD
MSB OUT
DATA
DATA
PD
12
7
6
MOSI
INPUT
MSB IN
LSB IN
16 QSPI SLV CPHA1
Figure 39 QSPI Timing Slave, CPHA = 1
MOTOROLA
138
MC68HC16Z1
MC68HC16Z1TS/D
MC68HC16Z1
MOTOROLA
139
MC68HC16Z1TS/D
9 Summary of Changes
This is a partial revision. Most of the publication remains the same, but the following changes were
made to improve it. Typographical errors that do not affect content are not annotated.
Page 2
Ordering information. All currently available options added.
Block diagram revised. All pin functions shown, port mnemonics changed.
Pinout diagram revised. All pin functions shown, port mnemonics changed.
144-pin diagram added.
Page 5
Page 6
Page 7
Pages 8-9
Pages 10-12
Pages 13-16
Page 17
Corrected port assignments, new notes, changed B driver description.
Corrected port assignments, new notes, changed B driver description.
Revised register map, new pseudolinear maps.
Added XMSK, YMSK registers to diagram.
SIM memory map standardized.
Page 41
Page 45
Expanded IARB field description.
Pages 48-49
Page 51
Expanded system clock description.
Expanded and relocated PIT description.
Page 65
New information concerning PE3.
Pages 66-69
Pages 70-72
Page 75
New resets section.
New interrupts section.
ADC memory map standardized, result register mnemonics added.
Changed ADC I/O port register mnemonics to reflect port name.
Changed prescaler rate selection values.
Pages 76 &77
Page 77
Page 83
QSM memory map standardized.
Pages 83 & 86
Page 94
Changed QSM I/O port register mnemonics to reflect port name.
New QSPI RAM diagram.
Pages 90 & 91
Page 97
Changed SPI BR field mnemonic to SPBR.
Changed SCI BR field mnemonic to SCBR.
SRAM memory map added.
Page 102
Page 106
Pages 106 & 110
Pages 118-145
GPT memory map standardized.
Changed GPT I/O port register mnemonics to reflect port name.
New electrical characteristics section.
MOTOROLA
140
MC68HC16Z1
MC68HC16Z1TS/D
NOTES
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
141
NOTES
MOTOROLA
142
MC68HC16Z1
MC68HC16Z1TS/D
NOTES
MC68HC16Z1
MC68HC16Z1TS/D
MOTOROLA
143
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not
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M
MC68HC16Z1TS/D
MOTOROLA
Order this document by: M68HC16ZEC20/D
SEMICONDUCTOR
TECHNICAL DATA
M68HC16 Z Series
Technical Supplement
20.97 MHz Electrical Characteristics
Devices in the M68HC16 Modular Microcontroller Family are built up from a selection of standard
functional modules. Microcontrollers in the M68HC16 Z Series contain the same central processing
unit (CPU16) and system integration module (SIM), and thus have similar electrical characteristics.
M68HC16 devices that operate at clock frequencies of 20.97 MHz are now available. This publica-
tion contains a new electrical characteristics appendix that supplements the MC68HC16Z1 User's
Manual (MC68HC16Z1UM/AD) and the MC68HC16Z2 User's Manual (MC68HC16Z2UM/AD).
The supplement contains the following updated specifications:
Table
Page
Maximum Ratings ......................................................................................................2
Typical Ratings ..........................................................................................................3
Thermal Characteristics .............................................................................................3
Clock Control Timing .................................................................................................4
DC Characteristics .....................................................................................................5
AC Timing ..................................................................................................................8
Background Debugging Mode Timing .....................................................................19
ECLK Bus Timing ....................................................................................................20
QSPI Timing ............................................................................................................21
ADC Maximum Ratings ...........................................................................................24
ADC DC Electrical Characteristics (Operating) .......................................................25
ADC AC Characteristics (Operating) .......................................................................26
ADC Conversion Characteristics (Operating) ..........................................................26
© MOTOROLA INC, 1995
Table A–1 Maximum Ratings
Num
Rating
1,2,3
Symbol
Value
Unit
V
1
– 0.3 to + 6.5
V
Supply Voltage
1,2,3,4,5,7
DD
VIN
ID
2
3
– 0.3 to + 6.5
25
V
Input Voltage
Instantaneous Maximum Current
mA
1,3,5,6
Single Pin Limit (all pins)
Operating Maximum Current
Digital Input Disruptive Current
3,5,6,7,8
IiD
4
– 500 to 500
µA
V
– 0.3 V
NEGCLMAP
POSCLAMP
V
V
+ 0.3
DD
Operating Temperature Range
C Suffix
TL to TH
– 40 to 85
TA
5
6
°C
°C
Tstg
Storage Temperature Range
– 55 to 150
NOTES:
1. Permanent damage can occur if maximum ratings are exceeded. Exposure to voltag-
es or currents in excess of recommended values affects device reliability. Device mod-
ules may not operate normally while being exposed to electrical extremes.
2. Although sections of the device contain circuitry to protect against damage from high
static voltages or electrical fields, take normal precautions to avoid exposure to voltag-
es higher than maximum-rated voltages.
3. This parameter is periodically sampled rather than 100% tested.
4. All pins except TSC.
5. Input must be current limited to the value specified. To determine the value of the re-
quired current-limiting resistor, calculate resistance values for positive and negative
clamp voltages, then use the larger of the two values.
6. Power supply must maintain regulation within operating V
neous and operating maximum current.
range during instanta-
DD
7. All functional non-supply pins are internally clamped to V . All functional pins except
SS
EXTAL and XFC are internally clamped to V
.
DD
8. Total input current for all digital input-only and all digital input/output pins must not ex-
ceed 10 mA. Exceeding this limit can cause disruption of normal operation.
MOTOROLA
M68HC16ZEC20/D
2
Table A–2 Typical Ratings
Num
Rating
Symbol
Value
Unit
V
1
Supply Voltage
5.0
V
DD
T
A
2
3
4
Operating Temperature
25
°C
V
Supply Current
DD
RUN
mA
µA
mA
113
125
3.75
I
DD
LPSTOP, VCO off
LPSTOP, External clock, max f
sys
V
Clock Synthesizer Operating Voltage
Supply Current
5.0
V
DDSYN
V
DDSYN
VCO on, maximum f
1.0
5.0
100
50
mA
mA
µA
sys
I
5
External Clock, maximum f
sys
DDSYN
LPSTOP, VCO off
µA
V
powered down
DD
RAM Standby Current
Normal RAM operation
Standby operation
I
6
7
7.0
40
µA
µA
SB
P
D
Power Dissipation
570
mW
Table A–3 Thermal Characteristics
Num
Characteristic
Symbol
Value
Unit
1
Thermal Resistance
Θ
1
Plastic 132-Pin Surface Mount
Plastic 144-pin Surface Mount
38
49
°C/W
JA
NOTES:
1. The average chip-junction temperature (T ) in C can be obtained from (1):
J
TJ = TA + (PD ΘJA
)
where:
T = Ambient Temperature, °C
A
Θ
= Package Thermal Resistance, Junction-to-Ambient, °C/W
JA
P = P
+ P
I/O
D
INT
P
P
= I × V , Watts — Chip Internal Power
= Power Dissipation on Input and Output Pins — User Determined
INT DD
I/O
DD
For most applications P < P
and can be neglected. An approximate relationship between
I/O
INT
P
and T (if P is neglected) is (2):
D
J
I/O
PD = K + (TJ + 273°C)
Solving equations (1) and (2) for K gives (3):
2
K = P + (TA + 273°C) + ΘJA × PD
D
Where K is a constant pertaining to the particular part. K can be determined from equation (3) by
measuring P (at equilibrium) for a known T . Using this value of K, the values of P and T
D
A
D
J
can be obtained by solving equations (1) and (2) iteratively for any value of T .
A
M68HC16ZEC20/D
MOTOROLA
3
Table A–4 Clock Control Timing
(V and V
= 5.0 Vdc ± 5%, V = 0 Vdc, T = T to T )
DD
DDSYN
SS
A
L
H
Num
Characteristic
Symbol
Minimum
Maximum
Unit
1
PLL Reference Frequency Range
MC68HC16Z1
f
1
20
50
kHz
ref
3.2
5.2
MHz
MC68HC16Z2
dc
2
20.97
20.97
20.97
20.97
System Frequency
4 (f
)
ref
Slow On-Chip PLL System Frequency
Fast On-Chip PLL System Frequency
External Clock Operation
f
2
MHz
sys
4 (f ) /128
ref
dc
—
—
1,3,5,6,7
t
3
4
20
ms
PLL Lock Time
lpll
4
f
2 (f max)
sys
VCO Frequency
MHz
VCO
Limp Mode Clock Frequency
SYNCR X bit = 0
f
f
max /2
max
5
6
—
—
MHz
%
sys
limp
f
SYNCR X bit = 1
sys
1,5,6,7,8
CLKOUT Jitter
J
–1.0
–0.5
1.0
0.5
Short term (5 µs interval)
Long term (500 µs interval)
clk
NOTES:
1. The base configuration of the MC68HC16Z1 requires a 32.768 kHz crystal reference, and the
base configuration of the M68HC16Z2 requires a 4.194 MHz crystal reference. Both devices can
be ordered with either reference as a mask option.
2. All internal registers retain data at 0 Hz.
3. Assumes that stable V
measured from the time V
is applied, and that the crystal oscillator is stable. Lock time is
DDSYN
and V
are valid until RESET is released. This specification
DD
DDSYN
also applies to the period required for PLL lock after changing the W and Y frequency control
bits in the synthesizer control register (SYNCR) while the PLL is running, and to the period re-
quired for the clock to lock after LPSTOP.
4. Internal VCO frequency (f
) is determined by SYNCR W and Y bit values.
VCO
The SYNCR X bit controls a divide-by-two circuit that is not in the synthesizer feedback loop.
When X = 0, the divider is enabled, and f
When X = 1, the divider is disabled, and f
= f
= f
÷ 4.
÷ 2.
sys
VCO
sys
VCO
X must equal one when operating at maximum specified f
.
sys
5. This parameter is periodically sampled rather than 100% tested.
6. Assumes that a low-leakage external filter network is used to condition clock synthesizer input
voltage. Total external resistance from the XFC pin due to external leakage must be greater than
15 M Ω to guarantee this specification. Filter network geometry can vary depending upon operat-
ing environment.
7. Proper layout procedures must be followed to achieve specifications.
8. Jitter is the average deviation from the programmed frequency measured over the specified in-
terval at maximum f . Measurements are made with the device powered by filtered supplies
sys
and clocked by a stable external clock signal. Noise injected into the PLL circuitry via V
DDSYN
and V
SS
and variation in crystal oscillator frequency increase the J percentage for a given in-
clk
terval. When jitter is a critical constraint on control system operation, this parameter should be
measured during functional testing of the final system.
MOTOROLA
M68HC16ZEC20/D
4
Table A–5 DC Characteristics
(V and V
= 5.0 Vdc ± 5%, V = 0 Vdc, T = T to T
)
H
DD
DDSYN
SS
A
L
Num
Characteristic
Symbol
Min Max
0.7 (V ) V + 0.3
DD
Unit
V
V
1
2
3
Input High Voltage
Input Low Voltage
IH
DD
V
V
– 0.3 0.2 (V
)
V
IL
SS
0.5
DD
1,2
V
—
V
Input Hysteresis
HYS
3,16
Input Leakage Current
I
4
5
6
7
8
–2.5
2.5
2.5
—
µA
µA
V
in
V
= V
or V
in
DD
SS
4,16
High Impedance (Off-State) Leakage Current
= V or V
I
–2.5
OZ
V
in
DD SS
5,6,16
CMOS Output High Voltage
= –10.0 µA
V
V
V
–0.2
DD
OH
I
OH
CMOS Output Low Voltage
= 10.0 µA
7,16
V
—
0.2
—
V
OL
I
OL
Output High Voltage
= –0.8 mA
6,7,16
V
–0.8
DD
V
OH
I
OH
7,16
Output Low Voltage
I
I
I
= 1.6 mA
= 5.3 mA
= 12 mA
OL
OL
OL
—
—
—
0.4
0.4
0.4
V
9
V
OL
V
1.6 (V )
DD
10 Three State Control Input High Voltage
8,9
9.1
V
IHTSC
Data Bus Mode Select Pull-up Current
V
= V
IMSP
—
–15
–120
—
µA
11
in
in
IL
V
= V
IH
10,11,12
Supply Current
MC68HC16Z1V
DD
—
—
—
140
350
5
mA
µA
mA
Run, crystal reference
LPSTOP, crystal reference, VCO Off (STSIM = 0)
LPSTOP, external clock input = max f
I
12
DD
sys
10,11,12
MC68HC16Z2 V
DD
Supply Current
—
—
—
140
2
10
mA
mA
mA
Run, crystal reference
LPSTOP, crystal reference, VCO Off (STSIM = 0)
LPSTOP, external clock input = max f
I
12A
DD
sys
V
13 Clock Synthesizer Operating Voltage
4.75
5.25
V
DDSYN
M68HC16ZEC20/D
MOTOROLA
5
Table A–5 DC Characteristics (Continued)
(V and V
= 5.0 Vdc ± 5%, V = 0 Vdc, T = T to T
)
H
DD
DDSYN
SS
A
L
Num
Characteristic
Symbol
Min
Max
Unit
6,12
MC68HC16Z1 V
DDSYN
Supply Current
VCO on, crystal reference, maximum f
—
—
—
—
2
6
150
100
mA
mA
µA
sys
I
14
External Clock, maximum f
sys
DDSYN
LPSTOP, crystal reference, VCO off (STSIM = 0)
powered down
µA
V
DD
6,12
Supply Current
MC68HC16Z2 V
DDSYN
VCO on, crystal reference, maximum f
—
—
—
—
2.5
8.75
2
mA
mA
mA
mA
sys
I
14A
External Clock, maximum f
sys
DDSYN
LPSTOP, crystal reference, VCO off (STSIM = 0)
powered down
2
V
DD
RAM Standby Voltage
Specified V applied
13
V
15
16
0.0
3.0
5.25
5.25
V
DD
SB
V
= V
SS
DD
11
MC68HC16Z1RAM Standby Current
Normal RAM operation
14
V
> V – 0.5 V
DD
DD
SB
—
—
—
10
3
50
µA
mA
µA
I
SB
Transient condition
V
V
− 0.5 V ≥ V
≥ V + 0.5 V
SB
SS
13
Standby operation
V
< V + 0.5 V
DD
SS
11
MC68HC16Z2RAM Standby Current
14
Normal RAM operation
V
> V – 0.5 V
—
—
—
10
3
100
µA
mA
µA
DD
DD
SB
I
16A
SB
Transient condition
− 0.5 V ≥ V
≥ V + 0.5 V
SS
SB
13
Standby operation
V
< V + 0.5 V
SS
DD
15
P
D
17 MC68HC16Z1 Power Dissipation
—
—
766
831
mW
mV
15
MC68HC16Z2 Power Dissipation
P
D
17A
MOTOROLA
M68HC16ZEC20/D
6
Table A–5 DC Characteristics (Continued)
(V and V
= 5.0 Vdc ± 5%, V = 0 Vdc, T = T to T
)
H
DD
DDSYN
SS
A
L
Num
Characteristic
Symbol
Min
Max
Unit
3,16
Input Capacitance
All input-only pins except ADC pins
All input/output pins
C
in
18
—
—
10
20
pF
16
Load Capacitance
—
—
—
—
90
Group 1 I/O Pins, CLKOUT, FREEZE/QUOT, IPIPE0
Group 2 I/O Pins and CSBOOT, BG/CS
Group 3 I/O Pins
C
L
19
100
130
200
pF
Group 4 I/O Pins
NOTES:
1. Applies to:
Port ADA[7:0] — AN[7:0]
Port E[7:4] — SIZ[1:0], AS, DS
Port F[7:0] — IRQ[7:1], MODCLK
Port GP[7:0] — IC4/OC5/OC1, IC[3:1], OC[4:1]/OC1
Port QS[7:0] — TXD, PCS[3:1], PCS0/SS, SCK, MOSI, MISO
BKPT/DSCLK, DSI/IPIPE1, PAI, PCLK, RESET, RXD, TSC
EXTAL (when PLL enabled)
2. This parameter is periodically sampled rather than 100% tested.
3. Applies to all input-only pins except ADC pins.
4. Applies to all input/output and output pins
5. Does not apply to HALT and RESET because they are open drain pins. Does not apply to Port QS[7:0] (TXD,
PCS[3:1], PCS0/SS, SCK, MOSI, MISO) in wired-OR mode.
6. Applies to Group 1, 2, 4 input/output and all output pins
7. Applies to Group 1, 2, 3, 4 input/output pins, BG/CS, CLKOUT, CSBOOT, FREEZE/QUOT, and IPIPE0
8. Applies to DATA[15:0]
9. Use of an active pulldown device is recommended.
10. Total operating current is the sum of the appropriate I , I
, and I
SB
values, plus I values in-
. I
DD DDSYN
DDA DD
clude supply currents for device modules powered by V
and V
pins.
DDE DDI
11. Current measured at maximum system clock frequency, all modules active.
12. The base configuration of the MC68HC16Z1 requires a 32.768 kHz crystal reference, and the base configu-
ration of the M68HC16Z2 requires a 4.194 MHz crystal reference. Both devices can be ordered with either
crystal reference as a mask option.
13. The SRAM module will not switch into standby mode as long as V
0.5 volts. The SRAM array cannot be accessed while the module is in standby mode.
does not exceed V
by more than
SB
DD
14. When V is more than 0.3 V greater than V , current flows between the V
and V
pins, which
DD
SB DD STBY
causes standby current to increase toward the maximum transient condition specification. System noise on
the V and V pin can contribute to this condition.
DD STBY
15. Power dissipation measured at specified system clock frequency, all modules active. Power dissipation can
be calculated using the expression:
P
= Maximum V
(I
+ I
+ I ) + Maximum V
(I
pins.
)
D
DD DD
DDSYN
SB DDA DDA
I
includes supply currents for all device modules powered by V
and V
DDI
DD
16. Input-Only Pins: EXTAL, TSC, BKPT/DSCLK, PAI, PCLK, RXD
DDE
Output-Only Pins: CSBOOT, BG/CS1, CLKOUT, FREEZE/QUOT, DS0/IPIPE0, PWMA, PWMB
Input/Output Pins:
Group 1: Port GP[7:0] — IC4/OC5/OC1, IC[3:1], OC[4:1]/OC1
DATA[15:0], DSI/IPIPE1
Group 2: Port C[6:0] — ADDR[22:19]/CS[9:6], FC[2:0]/CS[5:3]
Port E[7:0] — SIZ[1:0], AS, DS, AVEC, DSACK[1:0]
Port F[7:0] — IRQ[7:1], MODCLK
Port QS[7:3] — TXD, PCS[3:1], PCS0/SS, ADDR23/CS10/ECLK
ADDR[18:0], R/W, BERR, BR/CS0, BGACK/CS2
Group 3: HALT, RESET
Group 4: MISO, MOSI, SCK
M68HC16ZEC20/D
MOTOROLA
7
Table A–6 AC Timing
1
(V and V
= 5.0 Vdc ± 5%, V = 0 Vdc, T = T to T
)
H
DD
DDSYN
SS
A
L
Num
Characteristic
Symbol
Min
Max Unit
2
Frequency of Operation
4 (f
)
F1
f
20.97 MHz
ref
MC68HC16Z1
MC68HC16Z2
4 (f )/128 20.97
ref
t
1
Clock Period
47.7
381
47.7
18.8
183
23.8
—
—
—
—
—
—
—
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
t
1A
1B
ECLK Period
Ecyc
3
t
External Clock Input Period
Xcyc
t
2, 3 Clock Pulse Width
2A, 3A ECLK Pulse Width
CW
t
ECW
3
External Clock Input High/Low Time
t
2B, 3B
XCHL
t
4, 5 CLKOUT Rise and Fall Time
Crf
t
4A, 5A Rise and Fall Time (All Outputs except CLKOUT)
—
8
rf
4
t
4B, 5B External Clock Input Rise and Fall Time
—
5
XCrf
t
6
7
Clock High to ADDR, FC, SIZE Valid
0
23
47
—
23
10
—
23
—
—
—
—
—
47
—
23
23
—
—
23
—
—
—
CHAV
t
Clock High to ADDR, Data, FC, SIZE, High Impedance
Clock High to ADDR, FC, SIZE, Invalid
0
CHAZx
t
8
0
CHAZn
t
9
Clock Low to AS, DS, CS Asserted
0
CLSA
5
t
9A
11
12
13
14
AS to DS or CS Asserted (Read)
-10
10
2
STSA
t
ADDR, FC, SIZE Valid to AS, CS, (and DS Read) Asserted
Clock Low to AS, DS, CS Negated
AVSA
t
CLSN
t
AS, DS, CS Negated to ADDR, FC SIZE Invalid (Address Hold)
AS, CS (and DS Read) Width Asserted
10
80
36
32
32
—
SNAI
t
SWA
t
14A DS, CS Width Asserted (Write)
SWAW
t
14B AS, CS (and DS Read) Width Asserted (Fast Cycle)
6
SWDW
t
15
16
17
18
20
21
22
23
24
25
26
AS, DS, CS Width Negated
SN
t
Clock High to AS, DS, R/W High Impedance
AS, DS, CS Negated to R/W High
Clock High to R/W High
CHSZ
t
10
0
SNRN
t
CHRH
t
Clock High to R/W Low
0
CHRL
t
R/W High to AS, CS Asserted
10
54
—
RAAA
t
R/W Low to DS, CS Asserted (Write)
Clock High to Data Out Valid
RASA
t
CHDO
t
Data Out Valid to Negating Edge of AS, CS (Fast Write Cycle)
DS, CS Negated to Data Out Invalid (Data Out Hold)
Data Out Valid to DS, CS Asserted (Write)
10
10
10
DVASN
t
SNDOI
t
DVSA
MOTOROLA
M68HC16ZEC20/D
8
Table A–6 AC Timing (Continued)
1
(V and V
= 5.0 Vdc ± 5%, V = 0 Vdc, T = T to T
)
H
DD
DDSYN
SS
A
L
Num
Characteristic
Symbol
Min
5
Max Unit
t
27
Data In Valid to Clock Low (Data Setup)
—
—
60
—
48
—
72
46
23
—
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
DICL
t
27A Late BERR, HALT Asserted to Clock Low (Setup Time)
15
0
BELCL
t
28
29
AS, DS Negated to DSACK[1:0], BERR, HALT, AVEC Negated
SNDN
7
t
DS, CS Negated to Data In Invalid (Data In Hold)
0
SNDI
7, 8
t
29A
30
—
10
—
—
—
1
DS, CS Negated to Data In High Impedance
SHDI
7
t
CLKOUT Low to Data In Invalid (Fast Cycle Hold)
CLDI
7
t
30A
31
CLKOUT Low to Data In High Impedance
CLDH
9
t
DSACK[1:0] Asserted to Data In Valid
DADI
t
33
Clock Low to BG Asserted/Negated
CLBAN
10
t
t
t
t
t
35
BR Asserted to BG Asserted
BRAGA
cyc
cyc
cyc
cyc
ns
t
37
BGACK Asserted to BG Negated
BG Width Negated
1
GAGN
t
39
2
—
—
—
—
GH
t
39A BG Width Asserted
1
GA
t
46
R/W Width Asserted (Write or Read)
115
70
RWA
t
46A R/W Width Asserted (Fast Write or Read Cycle)
ns
RWAS
Asynchronous Input Setup Time
47A
t
5
—
ns
AIST
BR, BGACK, DSACK[1:0], BERR, AVEC, HALT
t
47B Asynchronous Input Hold Time
11
12
—
0
—
30
—
23
—
23
—
—
—
—
—
—
—
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AIHT
t
48
53
54
55
70
71
72
73
74
75
76
77
78
DSACK[1:0] Asserted to BERR, HALT Asserted
Data Out Hold from Clock High
DABA
t
DOCH
t
Clock High to Data Out High Impedance
R/W Asserted to Data Bus Impedance Change
Clock Low to Data Bus Driven (Show Cycle)
Data Setup Time to Clock Low (Show Cycle)
Data Hold from Clock Low (Show Cycle)
BKPT Input Setup Time
—
32
0
CHDH
t
RADC
t
SCLDD
t
10
10
10
10
20
0
SCLDS
t
SCLDH
t
BKST
t
BKPT Input Hold Time
BKHT
t
t
Mode Select Setup Time (DATA[15:0], MODCLK, BKPT)
Mode Select Hold Time (DATA[15:0], MODCLK, BKPT)
MSS
cyc
ns
t
MSH
12
t
t
RESET Assertion Time
4
RSTA
cyc
cyc
13,14
t
t
—
RESET Rise Time
RSTR
M68HC16ZEC20/D
MOTOROLA
9
Table A–6 AC Timing (Continued)
1
(V and V
= 5.0 Vdc ± 5%, V = 0 Vdc, T = T to T
)
H
DD
DDSYN
SS
A
L
Num
Characteristic
Symbol
Min
3
Max Unit
15
t
100 CLKOUT High to Phase 1 Asserted
40
40
—
—
—
—
ns
ns
ns
ns
ns
ns
CHP1A
15
CLKOUT High to Phase 2 Asserted
t
101
102
103
104
105
3
CHP2A
15
15
t
10
10
10
10
Phase 1 Valid to AS or DS Asserted
P1VSA
t
Phase 2 Valid to AS or DS Asserted
P2VSN
15
AS or DS Valid to Phase 1 Negated
t
SAP1N
15
AS or DS Negated to Phase 2 Negated
t
SNP2N
NOTES:
1. All AC timing is shown with respect to 20% V
and 70% V
levels unless otherwise noted.
DD
DD
2. The base configuration of the MC68HC16Z1 requires a 32.768 kHz crystal reference, and the base con-
figuration of the M68HC16Z2 requires a 4.194 MHz crystal reference. Both devices can be ordered with
either crystal reference as a mask option.
3. When an external clock is used, minimum high and low times are based on a 50% duty cycle. The mini-
mum allowable t
between external clock input duty cycle and minimum t
Xcyc
period is reduced when the duty cycle of the external clock varies. The relationship
is expressed:
/ (50% – external clock input duty cycle tolerance).
Xcyc
Minimum t
period = minimum t
Xcyc
XCHL
4. Parameters for an external clock signal applied while the internal PLL is disabled (MODCLK pin held low
during reset). Does not pertain to an external reference applied while the PLL is enabled (MODCLK pin
held high during reset). When the PLL is enabled, the clock synthesizer detects successive transitions of
the reference signal. If transitions occur within the correct clock period, rise/fall times and duty cycle are
not critical.
5. Specification 9A is the worst-case skew between AS and DS or CS. The amount of skew depends on the
relative loading of these signals. When loads are kept within specified limits, skew will not cause AS and
DS to fall outside the limits shown in specification 9.
6. If multiple chip selects are used, CS width negated (specification 15) applies to the time from the nega-
tion of a heavily loaded chip select to the assertion of a lightly loaded chip select. The CS width negated
specification between multiple chip selects does not apply to chip selects being used for synchronous
ECLK cycles.
7. Hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT
on fast cycle reads. The user is free to use either hold time.
8. Maximum value is equal to (t
/ 2) + 25 ns.
cyc
9. If the asynchronous setup time (specification 47A) requirements are satisfied, the DSACK[1:0] low to data
setup time (specification 31) and DSACK[1:0] low to BERR low setup time (specification 48) can be ig-
nored. The data must only satisfy the data-in to clock low setup time (specification 27) for the following
clock cycle. BERR must satisfy only the late BERR low to clock low setup time (specification 27A) for the
following clock cycle.
10. To ensure coherency during every operand transfer, BG is not asserted in response to BR until after all
cycles of the current operand transfer are complete.
11. In the absence of DSACK[1:0], BERR is an asynchronous input using the asynchronous setup time
(specification 47A).
12. After external RESET negation is detected, a short transition period (approximately 2) t
elapses, then
cyc
the SIM drives RESET low for 512 t
.
cyc
13. External assertion of the RESET input can overlap internally-generated resets. To insure that an exter-
nal reset is recognized in all cases, RESET must be asserted for at least 590 CLKOUT cycles.
14. External logic must pull RESET high during this period in order for normal MCU operation to begin.
15. Eight pipeline states are multiplexed into IPIPE[1:0]. The multiplexed signals have two phases.
16.Address access time = (2.5 + WS) t
Chip select access time = (2 + WS) t
Where: WS = number of wait states. When fast termination is used (2 clock bus) WS = –1.
– t
– t
– t
– t
cyc
cyc
CHAV
CLSA
DICL
DICL
MOTOROLA
M68HC16ZEC20/D
10
1
2
3
4
CLKOUT
5
16 CLKOUT TIM
16 EXT CLK INPUT TIM
16 ECLK OUTPUT TIM
Figure A–1 CLKOUT Output Timing Diagram
1B
2B
3B
4B
EXTAL
5B
NOTE: TIMING SHOWN WITH RESPECT TO 20% AND 70% V
.
DD
.
PULSE WIDTH SHOWN WITH RESPECT TO 50% V
DD
Figure A–2 External Clock Input Timing Diagram
1A
2A
3A
4A
ECLK
5A
NOTE: TIMING SHOWN WITH RESPECT TO 20% AND 70% V
DD.
Figure A–3 ECLK Output Timing Diagram
M68HC16ZEC20/D
MOTOROLA
11
S0
S1
S2
S3
S4
S5
CLKOUT
8
6
ADDR[23:0]
FC[2:0]
SIZ[1:0]
14
16
11
AS
DS
CS
13
9
9A
12
20
18
21
R/W
46
DSACK0
47A
31
28
DSACK1
29
DATA[15:0]
27
29A
BERR
HALT
48
27A
BKPT
47A
47B
ASYNCHRONOUS
INPUTS
105
100
101
IPIPE0
IPIPE1
PHASE 1
104
PHASE 2
103
102
16 RD CYC TIM
Figure A–4 Read Cycle Timing Diagram
MOTOROLA
M68HC16ZEC20/D
12
S0
S1
S2
S3
S4
S5
CLKOUT
6
8
ADDR[23:20]
FC[2:0]
SIZ[1:0]
11
14
15
AS
DS
13
9
9
12
CS
22
20
14A
17
R/W
46
DSACK0
47A
28
DSACK1
55
25
DATA[15:0]
23
26
54
53
BERR
HALT
48
27A
73
74
BKPT
101
100
102
105
IPIPE0
IPIPE1
PHASE 1
104
PHASE 2
103
16 WR CYC TIM
Figure A–5 Write Cycle Timing Diagram
M68HC16ZEC20/D
MOTOROLA
13
S0
S1
S4
S5
S0
CLKOUT
8
6
ADDR[23:0]
FC[2:0]
SIZ[1:0]
AS
14B
12
9
DS
CS
20
18
46A
R/W
30
30A
27
DATA[15:0]
29A
73
29
BKPT
74
100
101
IPIPE0
IPIPE1
PHASE 1
102
PHASE 2
105
104
103
16 FAST RD CYC TIM
Figure A–6 Fast Termination Read Cycle Timing Diagram
MOTOROLA
M68HC16ZEC20/D
14
S0
S1
S4
S5
S0
CLKOUT
6
8
ADDR[23:0]
FC[1:0]
SIZ[1:0]
14B
AS
DS
9
12
CS
20
46A
R/W
24
18
23
DATA[15:0]
27A
25
BKPT
100
101
105
IPIPE0
IPIPE1
PHASE 1
PHASE 2
103
102
104
16 FAST WR CYC TIM
Figure A–7 Fast Termination Write Cycle Timing Diagram
M68HC16ZEC20/D
MOTOROLA
15
S0
S1
S2
S3
S4
S5
S98
A5
A5
A2
CLKOUT
ADDR[23:0]
DATA[15:0]
7
AS
DS
16
R/W
DSACK0
DSACK1
47A
BR
BG
39A
35
33
33
BGACK
37
100
PHASE 1
102
101
IPIPE0
IPIPE1
PHASE 2
104
103
105
16 BUS ARB TIM
Figure A–8 Bus Arbitration Timing Diagram — Active Bus Case
MOTOROLA
M68HC16ZEC20/D
16
A0
A5
A5
A2
A3
A0
CLKOUT
ADDR[23:0]
DATA[15:0]
AS
47A
47A
BR
BG
35
37
47A
33
33
BGACK
16 BUS ARB TIM IDLE
Figure A–9 Bus Arbitration Timing Diagram — Idle Bus Case
S0
S41
S42
S43
S0
S1
S2
CLKOUT
6
8
ADDR[23:0]
R/W
18
20
AS
9
12
15
DS
71
72
70
74
DATA[15:0]
73
BKPT
100
101
PHASE 1
102
IPIPE0
PHASE 2
105
PHASE 1
PHASE 2
IPIPE1
104
103
SHOW CYCLE
START OF EXTERNAL CYCLE
NOTE:
Show cycles can stretch during clock phase S42 when bus accesses take longer than two cycles due to IMB module wait-state insertion.
16 SHW CYC TIM
Figure A–10 Show Cycle Timing Diagram
M68HC16ZEC20/D
MOTOROLA
17
S0
S1
S2
S3
S4
S5
S0
S1
S2
S3
S4
S5
CLKOUT
8
6
6
ADDR[23:0]
FC[2:0]
SIZ[1:0]
14
11
11
14
13
AS
DS
15
9
9
9
12
17
17
21
12
CS
20
18
14A
18
46
R/W
46
25
29
55
DATA[15:0]
29A
53
23
27
54
16 CHIP SEL TIM
Figure A–11 Chip-Select Timing Diagram
77
78
RESET
75
DATA[15:0],
MODCLK,
BKPT
76
16 RST/MODE SEL TIM
Figure A–12 Reset and Mode Select Timing Diagram
Table A–7 Background Debugging Mode Timing
1
(V and V
= 5.0 Vdc ± 5%, V = 0 Vdc, T = T to T
)
SS A L H
DD
DDSYN
Characteristic
Num
Symbol
Min
Max
Unit
t
B0 DSI Input Setup Time
15
—
ns
DSISU
MOTOROLA
M68HC16ZEC20/D
18
Table A–7 Background Debugging Mode Timing
1
(V and V
= 5.0 Vdc ± 5%, V = 0 Vdc, T = T to T
)
SS A L H
DD
DDSYN
Characteristic
Num
Symbol
Min
10
15
10
—
Max
—
Unit
ns
t
B1 DSI Input Hold Time
B2 DSCLK Setup Time
B3 DSCLK Hold Time
B4 DSO Delay Time
B5 DSCLK Cycle Time
DSIH
t
—
ns
DSCSU
t
—
ns
DSCH
t
25
—
ns
DSOD
t
t
2
DSCCYC
cyc
t
B6 CLKOUT Low to FREEZE Asserted/Negated
B7 CLKOUT High to IPIPE1 High Impedance
B8 CLKOUT High to IPIPE1 Valid
—
50
50
50
—
ns
ns
ns
FRZAN
t
—
IPZ
t
—
IP
t
t
B9 DSCLK Low Time
1
DSCLO
cyc
t
t
B10 IPIPE1 High Impedance to FREEZE Asserted
TBD
TBD
—
IPFA
cyc
t
t
B11 FREEZE Negated to IPIPE[0:1] Active
NOTES:
—
FRIP
cyc
1. All AC timing is shown with respect to 20% V
and 70% V
levels unless otherwise noted.
DD
DD
CLKOUT
FREEZE
B3
B2
BKPT/DSCLK
B9
B5
B1
B0
IPIPE1/DSI
B4
IPIPE0/DSO
16 BDM SER COM TIM
Figure A–13 BDM Serial Communication Timing Diagram
CLKOUT
FREEZE
B6
B6
B11
B7
B10
IPIPE1/DSI
B8
16 BDM FRZ TIM
Figure A–14 BDM Freeze Assertion Timing Diagram
M68HC16ZEC20/D
MOTOROLA
19
Table A–8 ECLK Bus Timing
1
(V and V
= 5.0 Vdc ± 5%, V = 0 Vdc, T = T to T )
DD
DDSYN
SS
A
L
H
Num
Characteristic
Symbol
Min
—
10
—
10
25
25
5
Max
48
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
t
E1 ECLK Low to Address Valid
E2 ECLK Low to Address Hold
E3 ECLK Low to CS Valid (CS Delay)
E4 ECLK Low to CS Hold
EAD
tEAH
tECSD
tECSH
tECSN
tEDSR
tEDHR
tEDHZ
tECDH
tECDZ
120
—
E5 CS Negated Width
—
E6 Read Data Setup Time
—
E7 Read Data Hold Time
—
E8 ECLK Low to Data High Impedance
E9 CS Negated to Data Hold (Read)
E10 CS Negated to Data High Impedance
—
0
48
—
t
—
1
cyc
t
tEDDW
tEDHW
tEACC
tEACS
tEAS
E11 ECLK Low to Data Valid (Write)
E12 ECLK Low to Data Hold (Write)
—
10
2
cyc
—
—
—
—
ns
ns
ns
3
E13 Address Access Time (Read)
308
236
1/2
4
E14 Chip-Select Access Time (Read)
t
E15 Address Setup Time
cyc
NOTES:
1. All AC timing is shown with respect to 20% V
and 70% V
levels unless otherwise noted.
DD
DD
2. When previous bus cycle is not an ECLK cycle, the address may be valid before ECLK goes low.
3. Address access time = t
– t
– t
.
Ecyc
EAD
EDSR
4. Chip select access time = t
– t
– t
.
Ecyc
ECSD
EDSR
CLKOUT
ECLK
2A
3A
1A
R/W
E1
E2
ADDR[23:0]
E5
E3
E14
E13
E4
CS
E6
E15
E9
DATA[15:0]
READ
E7
WRITE
E8
E11
E10
DATA[15:0]
WRITE
E12
HC16 E CYCLE TIM
Figure A–15 ECLK Timing Diagram
MOTOROLA
M68HC16ZEC20/D
20
Table A–9 QSPI Timing
1
(V and V
= 5.0 Vdc ± 5%, V = 0 Vdc, T = T to T
, 200 pF load on all QSPI pins)
DD
DDSYN
SS
A
L
H
Num
Function
Symbol
Min
Max
Unit
Operating Frequency
Master
Slave
f
f
1
DC
DC
1/4
1/4
sys
op
f
sys
Cycle Time
Master
Slave
t
t
t
2
3
4
5
4
4
510
—
cyc
cyc
qcyc
Enable Lead Time
Master
Slave
t
t
t
2
2
128
—
cyc
cyc
lead
Enable Lag Time
Master
Slave
t
SCK
—
2
1/2
—
lag
t
cyc
Clock (SCK) High or Low Time
Master
2 t
cyc
2 t
cyc
– 60
– n
t
255 t
cyc
ns
ns
sw
2
Slave
—
Sequential Transfer Delay
Master
Slave (Does Not Require Deselect)
t
t
6
7
17
13
8192
—
cyc
td
t
cyc
Data Setup Time (Inputs)
Master
Slave
t
30
20
—
—
ns
ns
su
Data Hold Time (Inputs)
Master
Slave
t
8
9
0
20
—
—
ns
ns
hi
t
t
t
Slave Access Time
—
—
1
2
a
cyc
cyc
t
10 Slave MISO Disable Time
Data Valid (after SCK Edge)
dis
t
11
Master
Slave
—
—
50
50
ns
ns
v
Data Hold Time (Outputs)
Master
Slave
t
12
0
0
—
—
ns
ns
ho
Rise Time
Input
Output
t
13
14
—
—
2
30
µs
ns
ri
t
ro
Fall Time
Input
Output
t
—
—
2
30
µs
ns
fi
t
fo
NOTES:
1. All AC timing is shown with respect to 20% V
and 70% V
levels unless otherwise noted.
DD
DD
2. For high time, n = External SCK rise time; for low time, n = External SCK fall time.
M68HC16ZEC20/D
MOTOROLA
21
3
2
PCS[3:0]
OUTPUT
5
13
12
SCK
CPOL=0
OUTPUT
4
1
SCK
CPOL=1
OUTPUT
12
6
4
13
7
MISO
INPUT
MSB IN
DATA
LSB IN
MSB IN
11
10
LSB OUT
MOSI
OUTPUT
MSB OUT
DATA
PORT DATA
12
MSB OUT
PD
13
16 QSPI MAST CPHA0
Figure A–16 QSPI Timing — Master, CPHA = 0
3
2
PCS[3:0]
OUTPUT
5
13
12
1
SCK
CPOL=0
OUTPUT
4
1
7
SCK
CPOL=1
OUTPUT
12
4
13
6
MISO
INPUT
DATA
DATA
LSB IN
MSB
MSB
MSB IN
11
10
LSB OUT
MOSI
OUTPUT
MSB OUT
PORT DATA
12
PORT DATA
13
16 QSPI MAST CPHA1
Figure A–17 QSPI Timing — Master, CPHA = 1
MOTOROLA
M68HC16ZEC20/D
22
3
2
SS
INPUT
5
13
12
SCK
CPOL=0
INPUT
4
1
SCK
CPOL=1
INPUT
12
4
13
11
10
11
8
9
MISO
OUTPUT
MSB OUT
DATA
LSB OUT
PD
13
MSB OUT
MSB IN
7
6
MOSI
INPUT
MSB IN
DATA
LSB IN
16 QSPI SLV CPHA0
Figure A–18 QSPI Timing — Slave, CPHA = 0
SS
INPUT
5
1
13
4
12
SCK
CPOL=0
INPUT
4
3
2
SCK
CPOL=1
INPUT
12
13
11
10
9
10
8
SLAVE
LSB OUT
MISO
OUTPUT
PD
MSB OUT
DATA
DATA
PD
12
7
6
MOSI
INPUT
MSB IN
LSB IN
16 QSPI SLV CPHA1
Figure A–19 QSPI Timing — Slave, CPHA = 1
M68HC16ZEC20/D
MOTOROLA
23
Table A–10 ADC Maximum Ratings
Num
Parameter
Symbol
Min
–0.3
–0.3
–0.3
–0.1
–6.5
–6.5
–6.5
–6.5
Max
6.5
6.5
6.5
0.1
6.5
6.5
6.5
6.5
Unit
V
V
1
2
3
4
5
6
7
8
Analog Supply
DDA
V
Internal Digital Supply, with reference to V
V
SSI
DDI
V
, V
Reference Supply, with reference to V
V
SSI
RH RL
V
V
–V
SSA
V
V
V
V
V
Differential Voltage
Differential Voltage
Differential Voltage
V
SS
DD
SSI
–V
DDA
V
DDI
V
–V
RL
V
REF
RH
V
–V
to V
Differential Voltage
Differential Voltage
V
RH
RL
DDA
RH
DDA
SSA
V
–V
NA
to V
V
SSA
RL
1 2 3 4 5 6 7
, , , , , ,
Disruptive Input Current
V
V
–0.3 V
8 V
I
9
–500
500
µA
NEGCLAMP
POSCLAMP
8
1,5,6,
K
K
10
11
2000
500
—
—
—
—
Positive Overvoltage Current Coupling Ratio
P
1,5,6
,8
Negative Overvoltage Current Coupling Ratio
N
3,4,6
Maximum Input Current
V
V
–0.3 V
8 V
I
12
–25
25
mA
NEGCLAMP
POSCLAMP
MA
NOTES:
1. Below disruptive current conditions, a stressed channel will store the maximum conversion value for
analog inputs greater than V and the minimum conversion value for inputs less than V . This as-
RH RL
RL SSA
are not affected by non-disruptive conditions
sumes that V
≤ V
and V ≥ V
due to the presence of the sample amplifier. Other channels
RH
DDA
2. Input signals with large slew rates or high frequency noise components cannot be converted accurate-
ly. These signals also interfere with conversion of other channels.
3. Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transi-
tions within the limit do not affect device reliability or cause permanent damage.
4. Input must be current limited to the value specified. To determine the value of the required current-lim-
iting resistor, calculate resistance values using positive and negative clamp values, then use the larger
of the calculated values.
5. This parameter is periodically sampled rather than 100% tested.
6. Applies to single pin only.
7. The values of external system components can change the maximum input current value, and affect
operation. A voltage drop may occur across the external source impedances of the adjacent pins, im-
pacting conversions on these adjacent pins. The actual maximum may need to be determined by test-
ing the complete design.
8. Current coupling is the ratio of the current induced from overvoltage (positive or negative, through an
external series coupling resistor), divided by the current induced on adjacent pins. A voltage drop may
occur across the external source impedances of the adjacent pins, impacting conversions on these ad-
jacent pins
MOTOROLA
M68HC16ZEC20/D
24
Table A–11 ADC DC Electrical Characteristics (Operating)
(VSS = 0 Vdc, ADCLK = 2.1 MHz, T = T to T )
A
L
H
Num
Parameter
Symbol
Min
Max
5.5
5.5
1.0
1.0
Unit
V
1
V
1
2
3
4
5
6
4.5
4.5
Analog Supply
Internal Digital Supply
DDA
1
V
V
DDI
V
V
V
V
Differential Voltage
Differential Voltage
– 1.0
– 1.0
mV
V
–
–
SS
DD
SSI
SSA
V
V
DDI
DDA
2,3
2,3
V
V
V
/ 2
DDA
V
Reference Voltage Low
RL
SSA
V
V
/ 2
V
DDA
V
Reference Voltage High
RH
DDA
4.5
V
3
V
V
RL
7
8
9
V
REF
Differential Voltage
5.5
V
V
V
V
–
RH
V
2
V
DDA
Input Voltage
INDC
SSA
V
0.7 (V
)
V
+ 0.3
DDA
Input High, Port ADA
IH
DDA
V
V
0.3
0.2 (V
)
10 Input Low, Port ADA
IL
SSA –
DDA
Analog Supply Current
4
I
11
—
—
1.0
mA
Normal Operation
Low-power stop
DDA
200
250
150
10
µA
I
I
12 Reference Supply Current
—
—
—
—
µA
nA
pF
pF
REF
5
13
Input Current, Off Channel
OFF
C
14 Total Input Capacitance, Not Sampling
INN
C
15 Total Input Capacitance, Sampling
NOTES:
15
I
NS
1. Refers to operation over full temperature and frequency range.
2. To obtain full-scale, full-range results, V ≤ V ≤ V ≤ V
≤ V
DDA.
SSA RL RH
INDC
3. Accuracy tested and guaranteed at V
– V = 5.0 V ± 5%.
RH
RL
4. Current measured at maximum system clock frequency with ADC active.
5. Maximum leakage occurs at maximum operating temperature. Current decreases by approximately
one-half for each 10°C decrease from maximum temperature.
M68HC16ZEC20/D
MOTOROLA
25
Table A–12 ADC AC Characteristics (Operating)
(VDD and VDDA = 5.0 Vdc ± 5%, VSS = 0 Vdc, TA within operating temperature range)
Num
Parameter
ADC Clock Frequency
Symbol
Min
Max
Unit
f
1
0.5
2.1
MHz
ADCLK
1
8-bit Conversion Time
f
= 1.0 MHz
= 2.1 MHz
t
2
15.2
7.6
—
µs
ADCLK
CONV
f
K
ADCL
1
10-bit Conversion Time
f
= 1.0 MHz
= 2.1 MHz
t
3
4
17.1
8.6
—
µs
µs
ADCLK
ADCLK
CONV
f
t
Stop Recovery Time
—
10
SR
NOTES:
1. Conversion accuracy varies with f
rate. Reduced conversion accuracy occurs at maximum.
ADCLK
Table A–13 ADC Conversion Characteristics (Operating)
(VDD and VDDA = 5.0 Vdc ± 5%, VSS = 0 Vdc, TA = TL to TH,
0.5 MHz ≤ f
≤ 1.0 MHz, 2 clock input sample time)
ADCLK
Num
Parameter
Symbol
1 Count
DNL
Min
—
Typical
20
Max
—
0.5
1
Unit
1
1
2
3
4
mV
8-bit Resolution
8-bit Differential Nonlinearity
8-bit Integral Nonlinearity
–0.5
–1
—
Counts
Counts
Counts
INL
—
2
AE
–1
—
1
8-bit Absolute Error
1
5
6
7
8
9
1 Count
DNL
INL
—
5
—
0.5
2.0
2.5
—
mV
10-bit Resolution
3
–0.5
–2.0
–2.5
—
—
—
—
20
Counts
Counts
Counts
kΩ
10-bit Differential Nonlinearity
3
10-bit Integral Nonlinearity
3,4
AE
10-bit Absolute Error
5
R
S
Source Impedance at Input
NOTES:
1. At V
–V = 5.12 V, one 10-bit count = 5 mV and one 8-bit count = 20 mV.
RL
RH
2. 8-bit absolute error of 1 count (20 mV) includes 1/2 count (10 mV) inherent quantization error and 1/2
count (10 mV) circuit (differential, integral, and offset) error.
3. Conversion accuracy varies with f
rate. Reduced conversion accuracy occurs at maximum f
ADCLK
AD-
. Assumes that minimum sample time (2 ADC Clocks) is selected.
CLK
4. 10-bit absolute error of 2.5 counts (12.5 mV) includes 1/2 count (2.5 mV) inherent quantization error
and 2 counts (10 mV) circuit (differential, integral, and offset) error.
5. Maximum source impedance is application-dependent. Error resulting from pin leakage depends on
junction leakage into the pin and on leakage due to charge-sharing with internal capacitance.
Error from junction leakage is a function of external source impedance and input leakage current. Ex-
pected error in result value due to junction leakage is expressed in voltage (V
):
ERRJ
V
= R X I
OFF
ERRJ
S
where I
OFF
is a function of operating temperature, as shown in Table A–11.
Charge-sharing leakage is a function of input source impedance, conversion rate, change in voltage
between successive conversions, and the size of the decoupling capacitor used. Error levels are best
determined empirically. In general, continuous conversion of the same channel may not be compatible
with high source impedance.
MOTOROLA
M68HC16ZEC20/D
26
IDEAL TRANSFER CURVE
8-BIT TRANSFER CURVE
(NO CIRCUIT ERROR)
A
C
B
0
20
40
INPUT IN mV, V – V = 5.120 V
60
RH
RL
A – +1/2 COUNT (10 mV) INHERENT QUANTIZATION ERROR
B – CIRCUIT-CONTRIBUTED +10mV ERROR
– + 20 mV ABSOLUTE ERROR (ONE 8-BIT COUNT)
C
ADC 8-BIT ACCURACY
Figure A–20 8-Bit ADC Conversion Accuracy
IDEAL TRANSFER CURVE
10-BIT TRANSFER CURVE
(NO CIRCUIT ERROR)
C
B
A
0
20
40
INPUT IN mV, V – V = 5.120 V
60
RH
RL
– +.5 COUNT (2.5 mV) INHERENT QUANTIZATION ERROR
A
B – CIRCUIT-CONTRIBUTED +10 mV ERROR
C – +12.5 mV ABSOLUTE ERROR (2.5 10-BIT COUNTS)
ADC 10-BIT ACCURACY
Figure A–21 10-Bit ADC Conversion Accuracy
M68HC16ZEC20/D
MOTOROLA
27
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
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applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not
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MOTOROLA
Order this document by: M68HC16ZEC25/D
SEMICONDUCTOR
TECHNICAL DATA
MC68HC16Z1
Technical Supplement
25.17 MHz Electrical Characteristics
Devices in the M68HC16 Modular Microcontroller Family are built up from a selection of standard
functional modules. Published electrical characteristics for MC68HC16Z1 devices are based on
a16.78 MHz system clock. New products that operate at clock frequencies of 25.17 MHz are now
available. This supplement consists of a new electrical characteristics appendix (Appendix A) that
supplements those published in the MC68HC16Z1 User's Manual (MC68HC16Z1UM/AD).
The supplement contains the following updated specifications:
Table
Page
Maximum Ratings ......................................................................................................2
Typical Ratings ..........................................................................................................3
Thermal Characteristics .............................................................................................3
Clock Control Timing .................................................................................................4
DC Characteristics .....................................................................................................5
AC Timing .................................................................................................................7
Background Debugging Mode Timing ....................................................................18
ECLK Bus Timing ...................................................................................................19
QSPI Timing ............................................................................................................20
ADC Maximum Ratings ...........................................................................................23
ADC DC Electrical Characteristics (Operating) .......................................................24
ADC AC Characteristics (Operating) ......................................................................24
ADC Conversion Characteristics (Operating) ..........................................................25
© MOTOROLA INC, 1995
Table A–1 Maximum Ratings
Num
Rating
1, 2, 3
Symbol
Value
Unit
V
1
– 0.3 to + 6.5
V
DD
Supply Voltage
1, 2, 3, 4, 5,7
V
2
3
– 0.3 to + 6.5
25
V
IN
Input Voltage
Instantaneous Maximum Current
I
mA
D
1, 3, 5, 6
Single Pin Limit (all pins)
Operating Maximum Current
Digital Input Disruptive Current
3, 5, 6, 7, 8
Ii
4
– 500 to 500
µA
D
V
– 0.3 V
NEGCLMAP
V
V
+ 0.3
POSCLAMP
DD
Operating Temperature Range
“C” Suffix
“V” Suffix
TL to TH
– 40 to 85
– 40 to 105
– 40 to 125
T
A
5
6
°C
°C
“M” Suffix
T
Storage Temperature Range
– 55 to 150
stg
NOTES:
1. Permanent damage can occur if maximum ratings are exceeded. Exposure to voltag-
es or currents in excess of recommended values affects device reliability. Device mod-
ules may not operate normally while being exposed to electrical extremes.
2. Although sections of the device contain circuitry to protect against damage from high
static voltages or electrical fields, take normal precautions to avoid exposure to voltag-
es higher than maximum-rated voltages.
3. This parameter is periodically sampled rather than 100% tested.
4. All pins except TSC.
5. Input must be current limited to the value specified. To determine the value of the re-
quired current-limiting resistor, calculate resistance values for positive and negative
clamp voltages, then use the larger of the two values.
6. Power supply must maintain regulation within operating V
neous and operating maximum current.
range during instanta-
DD
7. All functional non-supply pins are internally clamped to V . All functional pins except
SS
EXTAL and XFC are internally clamped to V
.
DD
8. Total input current for all digital input-only and all digital input/output pins must not ex-
ceed 10 mA. Exceeding this limit can cause disruption of normal operation.
MOTOROLA
M68HC16ZEC25/D
2
Table A–2 Typical Ratings
Num
Rating
Symbol
Value
Unit
V
DD
1
Supply Voltage
5.0
V
T
A
2
Operating Temperature
25
°C
V
Supply Current
DD
RUN
mA
µA
mA
113
125
3.75
I
3
4
DD
LPSTOP, VCO off
LPSTOP, External clock, max f
sys
V
Clock Synthesizer Operating Voltage
Supply Current
5.0
V
DDSYN
V
DDSYN
VCO on, maximum f
1.0
5.0
100
50
mA
mA
µA
sys
I
5
External Clock, maximum f
LPSTOP, VCO off
DDSYN
sys
µA
V
DD
powered down
V
6
7
8
RAM Standby Voltage
3.0
V
SB
RAM Standby Current
Normal RAM operation
Standby operation
ISB
7.0
40
µA
µA
P
D
Power Dissipation
570
mW
Table A–3 Thermal Characteristics
Num
Characteristic
Symbol
Value
Unit
°C/W
1
Thermal Resistance
Θ
1
Plastic 132-Pin Surface Mount
Plastic 144-Pin Surface Mount
38
49
JA
NOTES:
1. The average chip-junction temperature (TJ) in C can be obtained from (1):
TJ = TA + (PD ΘJA
)
where:
T = Ambient Temperature, °C
A
Θ
= Package Thermal Resistance, Junction-to-Ambient, °C/W
JA
P = P
+ P
D
INT
= I
I/O
× V , Watts — Chip Internal Power
P
P
INT DD
DD
= Power Dissipation on Input and Output Pins — User Determined
I/O
For most applications P
< P and can be neglected. An approximate relation-
INT
I/O
ship between P and T (if P is neglected) is (2):
D
J
I/O
PD = K + (TJ + 273°C)
Solving equations (1) and (2) for K gives (3):
K = PD + (TA + 273°C) + ΘJA × PD2
Where K is a constant pertaining to the particular part. K can be determined from
equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of
K, the values of PD and TJ can be obtained by solving equations (1) and (2) itera-
tively for any value of TA.
M68HC16ZEC25/D
MOTOROLA
3
Table A–4 Clock Control Timing
1
(V and V
= 5.0 Vdc ± 5%, V = 0 Vdc, T = T to T , Stable External Reference
)
DD
DDSYN
SS
A
L
H
Num
Characteristic
Symbol
Minimum
25
Maximum
Unit
f
ref
1
PLL Reference Frequency Range
50
kHz
2
dc
0.131
dc
25.17
25.17
25.17
System Frequency
f
2
MHz
sys
On-Chip PLL System Frequency
External Clock Operation
3,5,6,7
t
3
4
—
—
20
ms
lpll
PLL Lock Time
4
f
2 (f
f
max)
sys
VCO Frequency
MHz
VCO
Limp Mode Clock Frequency
SYNCR X bit = 0
SYNCR X bit = 1
f
max /2
5
6
—
—
MHz
%
sys
limp
f
max
sys
5,6,7,8
CLKOUT Jitter
J
–1.0
–0.5
1.0
0.5
Short term (5 µs interval)
Long term (500 µs interval)
clk
NOTES:
1. Tested with a 32.768 kHz reference.
2. All internal registers retain data at 0 Hz.
3. Assumes that stable V is applied, and that the crystal oscillator is stable. Lock time is
DDSYN
measured from the time V
and V
are valid until RESET is released. This specifica-
DD
DDSYN
tion also applies to the period required for PLL lock after changing the W and Y frequency
control bits in the synthesizer control register (SYNCR) while the PLL is running, and to the
period required for the clock to lock after LPSTOP.
4. Internal VCO frequency (f ) is determined by SYNCR W and Y bit values.
VCO
The SYNCR X bit controls a divide-by-two circuit that is not in the synthesizer feedback loop.
When X = 0, the divider is enabled, and f
When X = 1, the divider is disabled, and f
= f
= f
÷ 4.
÷ 2.
sys
VCO
sys
VCO
X must equal one when operating at maximum specified f
.
sys
5. This parameter is periodically sampled rather than 100% tested.
6. Assumes that a low-leakage external filter network is used to condition clock synthesizer in-
put voltage. Total external resistance from the XFC pin due to external leakage must be
greater than 15 M Ω to guarantee this specification. Filter network geometry can vary de-
pending upon operating environment.
7. Proper layout procedures must be followed to achieve specifications.
8. Jitter is the average deviation from the programmed frequency measured over the specified
interval at maximum f . Measurements are made with the device powered by filtered sup-
sys
plies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via
V
and V
and variation in crystal oscillator frequency increase the J percentage
DDSYN
SS
clk
for a given interval. When jitter is a critical constraint on control system operation, this param-
eter should be measured during functional testing of the final system.
MOTOROLA
M68HC16ZEC25/D
4
Table A–5 DC Characteristics
(V and V
= 5.0 Vdc ± 5%, V = 0 Vdc, T = T to T
)
DD
DDSYN
SS
A
L
H
Num
Characteristic
Symbol
Min
Max
V + 0.3
DD
Unit
V
V
IH
0.7 (V
)
1
2
Input High Voltage
Input Low Voltage
DD
V
IL
V
– 0.3 0.2 (V
)
DD
V
SS
0.5
1, 2
V
3
4
—
V
HYS
Input Hysteresis
3,16
Input Leakage Current
I
in
– 2.5
2.5
2.5
—
µA
V
in
= V
DD
or V
SS
4,16
High Impedance (Off-State) Leakage Current
I
5
6
7
8
– 2.5
µA
V
OZ
V
in
= V or V
DD SS
5,6,16
CMOS Output High Voltage
= –10.0 µA
V
OH
V
– 0.2
DD
I
OH
6,16
CMOS Output Low Voltage
= 10.0 µA
V
OL
—
0.2
—
V
I
OL
5,6,16
Output High Voltage
= –0.8 mA
V
OH
V
–0.8
DD
V
I
OH
7,16
Output Low Voltage
I
I
I
= 1.6 mA
= 5.3 mA
= 12 mA
—
—
—
0.4
0.4
0.4
OL
OL
OL
V
OL
9
V
V
1.6 (V )
DD
10 Three State Control Input High Voltage
8,9
9.1
V
IHTSC
Data Bus Mode Select Pull-up Current
I
11
V
= V
—
–15
–120
—
µA
MSP
in
in
IL
V
= V
IH
10,11, 12
Supply Current
V
DD
—
—
—
140
350
5
mA
µA
µA
Run
I
12
DD
LPSTOP, crystal reference, VCO Off (STSIM = 0)
LPSTOP, external clock input frequency = maximum f
sys
V
13 Clock Synthesizer Operating Voltage
6,12
4.75
5.25
V
DDSYN
V
Supply Current
DDSYN
Crystal reference, VCO on, maximum f
sys
External clock input, maximum f
sys
Crystal reference, LPSTOP, VCO off (STSIM = 0)
—
—
—
—
2
7
150
100
mA
mA
µA
I
14
DDSYN
µA
Crystal reference, V
powered down
DD
13
RAM Standby Voltage
Specified V
DD
applied
V
15
16
0.0
3.0
5.25
5.25
V
SB
V
= V
SS
DD
10
RAM Standby Current
Normal RAM operation
14
V
> V – 0.5 V
DD
SB
—
—
—
10
3
50
µA
mA
µA
I
SB
Transient condition
V
SB
− 0.5 V ≥ V
≥ V + 0.5 V
DD
SS
13
Standby operation
V
< V + 0.5 V
SS
DD
15, 16
P
D
17
18
—
766
mW
pF
Power Dissipation
2, 16
Input Capacitance
C
in
—
—
10
20
All input-only pins except ADC pins
All input/output pins
M68HC16ZEC25/D
MOTOROLA
5
Table A–5 DC Characteristics (Continued)
(V and V
= 5.0 Vdc ± 5%, V = 0 Vdc, T = T to T
)
DD
DDSYN
SS
A
L
H
Num
Characteristic
Symbol
Min
Max
Unit
16
Load Capacitance
Group 1 I/O Pins, CLKOUT, FREEZE/QUOT, IPIPE0
Group 2 I/O Pins and CSBOOT, BG/CS
Group 3 I/O Pins
—
—
—
—
90
C
L
19
100
130
200
pF
Group 4 I/O Pins
NOTES:
1. Applies to:
Port ADA[7:0] — AN[7:0]
Port E[7:4] — SIZ[1:0], AS, DS
Port F[7:0] — IRQ[7:1], MODCLK
Port GP[7:0] — IC4/OC5/OC1, IC[3:1], OC[4:1]/OC1
Port QS[7:0] — TXD, PCS[3:1], PCS0/SS, SCK, MOSI, MISO
BKPT/DSCLK, DSI/IPIPE1, PAI, PCLK, RESET, RXD, TSC
EXTAL (when PLL enabled)
2. This parameter is periodically sampled rather than 100% tested.
3. Applies to all input-only pins except ADC pins.
4. Applies to all input/output and output pins
5. Does not apply to HALT and RESET because they are open drain pins. Does not apply to Port QS[7:0]
(TXD, PCS[3:1], PCS0/SS, SCK, MOSI, MISO) in wired-OR mode.
6. Applies to Group 1, 2, 4 input/output and all output pins
7. Applies to Group 1, 2, 3, 4 input/output pins, BG/CS, CLKOUT, CSBOOT, FREEZE/QUOT, and IPIPE0
8. Applies to DATA[15:0]
9. Use of an active pulldown device is recommended.
10. Total operating current is the sum of the appropriate I , I
, and I
SB
values, plus I
. I
val-
DD DDSYN
DDA DD
ues include supply currents for device modules powered by V
and V
DDE DDI
pins.
11. Current measured at maximum system clock frequency, all modules active.
12. Tested with a 32.768 kHz crystal reference.
13. The SRAM module will not switch into standby mode as long as V
SB
does not exceed V
DD
by more
than 0.5 volts. The SRAM array cannot be accessed while the module is in standby mode.
14. When V is more than 0.3 V greater than V , current flows between the V and V
pins, which
SB DD STBY DD
causes standby current to increase toward the maximum transient condition specification. System noise
on the V and V pin can contribute to this condition.
DD STBY
15. Power dissipation measured at specified system clock frequency, all modules active. Power dissipation
can be calculated using the expression:
P
= Maximum V
(I
+ I
DDSYN
+ I ) + Maximum V )
(I
D
DD DD
SB DDA DDA
I
includes supply currents for all device modules powered by V
DDE
and V pins.
DD
16. Input-Only Pins: EXTAL, TSC, BKPT/DSCLK, PAI, PCLK, RXD
DDI
Output-Only Pins: CSBOOT, BG/CS1, CLKOUT, FREEZE/QUOT, DS0/IPIPE0, PWMA, PWMB
Input/Output Pins:
Group 1: Port GP[7:0] — IC4/OC5/OC1, IC[3:1], OC[4:1]/OC1
DATA[15:0], DSI/IPIPE1
Group 2: Port C[6:0] — ADDR[22:19]/CS[9:6], FC[2:0]/CS[5:3]
Port E[7:0] — SIZ[1:0], AS, DS, AVEC, DSACK[1:0]
Port F[7:0] — IRQ[7:1], MODCLK
Port QS[7:3] — TXD, PCS[3:1], PCS0/SS, ADDR23/CS10/ECLK
ADDR[18:0], R/W, BERR, BR/CS0, BGACK/CS2
Group 3: HALT, RESET
Group 4: MISO, MOSI, SCK
MOTOROLA
M68HC16ZEC25/D
6
Table A–6 AC Timing
1
(V and V
= 5.0 Vdc ± 5%, V = 0 Vdc, T = T to T
)
H
DD
DDSYN
SS
A
L
Num
F1 Frequency of Operation
Clock Period
1A ECLK Period
Characteristic
Symbol
Min
Max
Unit
2
4 (f
)
f
25.166 MHz
ref
39.7
318
39.7
15
t
1
—
—
—
—
—
—
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
t
Ecyc
3
t
1B External Clock Input Period
2, 3 Clock Pulse Width
Xcyc
t
CW
t
2A, 3A ECLK Pulse Width
155
ECW
3
t
2B, 3B
19.8
—
—
—
0
XCHL
External Clock Input High/Low Time
t
4, 5 CLKOUT Rise and Fall Time
Crf
t
rf
4A, 5A Rise and Fall Time (All Outputs except CLKOUT)
8
4
t
4B, 5B External Clock Input Rise and Fall Time
4
XCrf
t
6
7
8
9
Clock High to ADDR, FC, SIZE Valid
19
39
—
19
15
—
19
—
—
—
—
—
39
—
19
19
—
—
19
—
—
—
CHAV
t
Clock High to ADDR, Data, FC, SIZE, High Impedance
Clock High to ADDR, FC, SIZE, Invalid
0
CHAZx
t
0
CHAZn
t
Clock Low to AS, DS, CS Asserted
5
2
CLSA
t
9A AS to DS or CS Asserted (Read)
–10
8
STSA
t
11 ADDR, FC, SIZE Valid to AS, CS, (and DS Read) Asserted
12 Clock Low to AS, DS, CS Negated
AVSA
t
2
CLSN
t
13 AS, DS, CS Negated to ADDR, FC SIZE Invalid (Address Hold)
14 AS, CS (and DS Read) Width Asserted
8
SNAI
t
65
25
22
22
—
10
0
SWA
t
14A DS, CS Width Asserted (Write)
SWAW
t
14B AS, CS (and DS Read) Width Asserted (Fast Cycle)
SWDW
6
t
15 AS, DS, CS Width Negated
SN
t
16 Clock High to AS, DS, R/W High Impedance
17 AS, DS, CS Negated to R/W High
18 Clock High to R/W High
CHSZ
t
SNRN
t
CHRH
t
20 Clock High to R/W Low
0
CHRL
t
21 R/W High to AS, CS Asserted
10
40
—
7
RAAA
t
22 R/W Low to DS, CS Asserted (Write)
23 Clock High to Data Out Valid
RASA
t
CHDO
t
24 Data Out Valid to Negating Edge of AS, CS (Fast Write Cycle)
25 DS, CS Negated to Data Out Invalid (Data Out Hold)
26 Data Out Valid to DS, CS Asserted (Write)
DVASN
t
5
SNDOI
t
8
DVSA
M68HC16ZEC25/D
MOTOROLA
7
Table A–6 AC Timing (Continued)
1
(V and V
= 5.0 Vdc ± 5%, V = 0 Vdc, T = T to T
)
SS A L H
DD
DDSYN
Num
Characteristic
Symbol
Min
5
Max
—
Unit
ns
t
27 Data In Valid to Clock Low (Data Setup)
DICL
t
27A Late BERR, HALT Asserted to Clock Low (Setup Time)
10
0
—
ns
BELCL
t
28 AS, DS Negated to DSACK[1:0], BERR, HALT, AVEC Negated
50
—
ns
SNDN
7
t
29 DS, CS Negated to Data In Invalid (Data In Hold)
0
ns
SNDI
7, 8
t
29A
—
8
45
—
ns
ns
SHDI
DS, CS Negated to Data In High Impedance
7
t
30
CLDI
CLKOUT Low to Data In Invalid (Fast Cycle Hold)
7
t
30A
—
—
—
1
60
35
19
—
2
ns
ns
ns
CLDH
CLKOUT Low to Data In High Impedance
9
t
31 DSACK[1:0] Asserted to Data In Valid
DADI
t
33 Clock Low to BG Asserted/Negated
CLBAN
10
t
t
35 BR Asserted to BG Asserted
BRAGA
cyc
t
t
37 BGACK Asserted to BG Negated
39 BG Width Negated
1
GAGN
cyc
t
t
2
—
—
—
—
GH
cyc
t
t
39A BG Width Asserted
1
GA
cyc
t
46 R/W Width Asserted (Write or Read)
46A R/W Width Asserted (Fast Write or Read Cycle)
90
55
ns
ns
RWA
t
RWAS
Asynchronous Input Setup Time
47A
t
5
—
ns
AIST
BR, BGACK, DSACK[1:0], BERR, AVEC, HALT
t
47B Asynchronous Input Hold Time
10
—
0
—
27
—
23
—
19
—
—
—
—
—
—
—
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AIHT
11
t
48 DSACK[1:0] Asserted to BERR, HALT Asserted
DABA
t
53 Data Out Hold from Clock High
DOCH
t
54 Clock High to Data Out High Impedance
55 R/W Asserted to Data Bus Impedance Change
70 Clock Low to Data Bus Driven (Show Cycle)
71 Data Setup Time to Clock Low (Show Cycle)
72 Data Hold from Clock Low (Show Cycle)
73 BKPT Input Setup Time
—
25
0
CHDH
t
RADC
t
SCLDD
t
8
SCLDS
t
8
SCLDH
t
10
10
20
0
BKST
t
74 BKPT Input Hold Time
BKHT
t
t
75 Mode Select Setup Time (DATA[15:0], MODCLK, BKPT)
76 Mode Select Hold Time (DATA[15:0], MODCLK, BKPT)
MSS
cyc
t
ns
MSH
12
t
t
77 RESET Assertion Time
4
RSTA
cyc
13,14
t
t
78
—
RSTR
cyc
RESET Rise Time
MOTOROLA
M68HC16ZEC25/D
8
Table A–6 AC Timing (Continued)
1
(V and V
= 5.0 Vdc ± 5%, V = 0 Vdc, T = T to T
)
SS A L H
DD
DDSYN
Num
Characteristic
Symbol
Min
Max
Unit
15
t
100 CLKOUT High to Phase 1 Asserted
3
34
ns
CHP1A
15
t
101
3
9
9
9
9
34
—
—
—
—
ns
ns
ns
ns
ns
CHP2A
CLKOUT High to Phase 2 Asserted
15
15
t
102
P1VSA
Phase 1 Valid to AS or DS Asserted
Phase 2 Valid to AS or DS Asserted
t
103
104
105
P2VSN
15
AS or DS Valid to Phase 1 Negated
t
SAP1N
15
AS or DS Negated to Phase 2 Negated
t
SNP2N
NOTES:
1. All AC timing is shown with respect to 20% V
and 70% V
levels unless otherwise noted.
DD
DD
2. Minimum system clock frequency is four times the crystal frequency, subject to specified limits.
3. When an external clock is used, minimum high and low times are based on a 50% duty cycle. The mini-
mum allowable t period is reduced when the duty cycle of the external clock varies. The relationship
Xcyc
between external clock input duty cycle and minimum t
is expressed:
Xcyc
/ (50% – external clock input duty cycle tolerance).
Minimum t
Xcyc
period = minimum t
XCHL
4. Parameters for an external clock signal applied while the internal PLL is disabled (MODCLK pin held
low during reset). Does not pertain to an external VCO reference applied while the PLL is enabled
(MODCLK pin held high during reset). When the PLL is enabled, the clock synthesizer detects succes-
sive transitions of the reference signal. If transitions occur within the correct clock period, rise/fall times
and duty cycle are not critical.
5. Specification 9A is the worst-case skew between AS and DS or CS. The amount of skew depends on
the relative loading of these signals. When loads are kept within specified limits, skew will not cause AS
and DS to fall outside the limits shown in specification 9.
6. If multiple chip selects are used, CS width negated (specification 15) applies to the time from the nega-
tion of a heavily loaded chip select to the assertion of a lightly loaded chip select. The CS width negated
specification between multiple chip selects does not apply to chip selects being used for synchronous
ECLK cycles.
7. Hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT
on fast cycle reads. The user is free to use either hold time.
8. Maximum value is equal to (t
cyc
/ 2) + 25 ns.
9. If the asynchronous setup time (specification 47A) requirements are satisfied, the DSACK[1:0] low to
data setup time (specification 31) and DSACK[1:0] low to BERR low setup time (specification 48) can be
ignored. The data must only satisfy the data-in to clock low setup time (specification 27) for the following
clock cycle. BERR must satisfy only the late BERR low to clock low setup time (specification 27A) for
the following clock cycle.
10. To ensure coherency during every operand transfer, BG is not asserted in response to BR until after all
cycles of the current operand transfer are complete.
11. In the absence of DSACK[1:0], BERR is an asynchronous input using the asynchronous setup time
(specification 47A).
12. After external RESET negation is detected, a short transition period (approximately 2 t ) elapses,
cyc
then the SIM drives RESET low for 512 tcyc.
13. External assertion of the RESET input can overlap internally-generated resets. To insure that an exter-
nal reset is recognized in all cases, RESET must be asserted for at least 590 CLKOUT cycles.
14. External logic must pull RESET high during this period in order for normal MCU operation to begin.
15. Eight pipeline states are multiplexed into IPIPE[1:0]. The multiplexed signals have two phases.
16.Address access time = (2.5 + WS) t
Chip select access time = (2 + WS) t
– t
– t
– t
cyc
cyc
CHAV
CLSA
DICL
– t
DICL
Where: WS = number of wait states. When fast termination is used (2 clock bus) WS = –1.
M68HC16ZEC25/D
MOTOROLA
9
1
2
3
4
CLKOUT
5
NOTE: TIMING SHOWN WITH RESPECT TO 20% AND 70% V
DD
16 CLKOUT TIM
16 EXT CLK INPUT TIM
16 ECLK OUTPUT TIM
Figure A–1 CLKOUT Output Timing Diagram
1B
2B
3B
4B
EXTAL
5B
NOTE: TIMING SHOWN WITH RESPECT TO 20% AND 70% V
DD
PULSE WIDTH SHOWN WITH RESPECT TO 50% V
DD
Figure A–2 External Clock Input Timing Diagram
1A
2A
3A
4A
ECLK
5A
NOTE: TIMING SHOWN WITH RESPECT TO 20% AND 70% V
DD
Figure A–3 ECLK Output Timing Diagram
MOTOROLA
M68HC16ZEC25/D
10
S0
S1
S2
S3
S4
S5
CLKOUT
8
6
ADDR[23:0]
FC[2:0]
SIZ[1:0]
14
16
11
AS
DS
CS
13
9
9A
12
20
18
21
R/W
46
DSACK0
47A
31
28
DSACK1
29
DATA[15:0]
27
29A
BERR
HALT
48
27A
BKPT
47A
47B
ASYNCHRONOUS
INPUTS
105
100
101
IPIPE0
IPIPE1
PHASE 1
104
PHASE 2
103
102
16 RD CYC TIM
Figure A–4 Read Cycle Timing Diagram
M68HC16ZEC25/D
MOTOROLA
11
S0
S1
S2
S3
S4
S5
CLKOUT
6
8
ADDR[23:20]
FC[2:0]
SIZ[1:0]
11
14
15
AS
DS
13
9
9
12
CS
22
20
14A
17
R/W
46
DSACK0
47A
28
DSACK1
55
25
DATA[15:0]
23
26
54
53
BERR
HALT
48
27A
73
74
BKPT
101
100
102
105
IPIPE0
IPIPE1
PHASE 1
104
PHASE 2
103
16 WR CYC TIM
Figure A–5 Write Cycle Timing Diagram
MOTOROLA
M68HC16ZEC25/D
12
S0
S1
S4
S5
S0
CLKOUT
8
6
ADDR[23:0]
FC[2:0]
SIZ[1:0]
AS
14B
12
9
DS
CS
20
18
46A
R/W
30
30A
27
DATA[15:0]
29A
73
29
BKPT
74
100
101
IPIPE0
IPIPE1
PHASE 1
102
PHASE 2
105
104
103
16 FAST RD CYC TIM
Figure A–6 Fast Termination Read Cycle Timing Diagram
M68HC16ZEC25/D
MOTOROLA
13
S0
S1
S4
S5
S0
CLKOUT
6
8
ADDR[23:0]
FC[1:0]
SIZ[1:0]
14B
AS
DS
9
12
CS
20
46A
R/W
24
18
23
DATA[15:0]
27A
25
BKPT
100
101
105
IPIPE0
IPIPE1
PHASE 1
PHASE 2
103
102
104
16 FAST WR CYC TIM
Figure A–7 Fast Termination Write Cycle Timing Diagram
MOTOROLA
M68HC16ZEC25/D
14
S0
S1
S2
S3
S4
S5
S98
A5
A5
A2
CLKOUT
ADDR[23:0]
DATA[15:0]
7
AS
DS
16
R/W
DSACK0
DSACK1
47A
BR
BG
39A
35
33
33
BGACK
37
100
PHASE 1
102
101
IPIPE0
IPIPE1
PHASE 2
104
103
105
16 BUS ARB TIM
Figure A–8 Bus Arbitration Timing Diagram — Active Bus Case
M68HC16ZEC25/D
MOTOROLA
15
A0
A5
A5
A2
A3
A0
CLKOUT
ADDR[23:0]
DATA[15:0]
AS
47A
47A
BR
BG
35
37
47A
33
33
BGACK
16 BUS ARB TIM IDLE
Figure A–9 Bus Arbitration Timing Diagram — Idle Bus Case
S0
S41
S42
S43
S0
S1
S2
CLKOUT
6
8
ADDR[23:0]
R/W
18
20
AS
9
12
15
DS
71
72
70
74
DATA[15:0]
73
BKPT
100
101
PHASE 1
102
IPIPE0
PHASE 2
105
PHASE 1
PHASE 2
IPIPE1
104
103
SHOW CYCLE
START OF EXTERNAL CYCLE
NOTE:
Show cycles can stretch during clock phase S42 when bus accesses take longer than two cycles due to IMB module wait-state insertion.
16 SHW CYC TIM
Figure A–10 Show Cycle Timing Diagram
MOTOROLA
M68HC16ZEC25/D
16
S0
S1
S2
S3
S4
S5
S0
S1
S2
S3
S4
S5
CLKOUT
8
6
6
ADDR[23:0]
FC[2:0]
SIZ[1:0]
14
11
11
14
13
AS
DS
15
9
9
9
12
17
17
21
12
CS
20
18
14A
18
46
R/W
46
25
29
55
DATA[15:0]
29A
53
23
27
54
16 CHIP SEL TIM
Figure A–11 Chip-Select Timing Diagram
77
78
RESET
75
DATA[15:0],
MODCLK,
BKPT
76
16 RST/MODE SEL TIM
Figure A–12 Reset and Mode Select Timing Diagram
M68HC16ZEC25/D
MOTOROLA
17
Table A–7 Background Debugging Mode Timing
1
(V and V
= 5.0 Vdc ± 5%, V = 0 Vdc, T = T to T
)
SS A L H
DD
DDSYN
Characteristic
Num
Symbol
Min
10
5
Max
—
Unit
ns
t
B0 DSI Input Setup Time
B1 DSI Input Hold Time
B2 DSCLK Setup Time
B3 DSCLK Hold Time
B4 DSO Delay Time
B5 DSCLK Cycle Time
DSISU
t
—
ns
DSIH
t
10
5
—
ns
DSCSU
t
—
ns
DSCH
t
—
20
—
ns
DSOD
t
t
2
DSCCYC
cyc
t
B6 CLKOUT High to FREEZE Asserted/Negated
B7 CLKOUT High to IPIPE1 High Impedance
B8 CLKOUT High to IPIPE1 Valid
—
20
20
20
—
ns
ns
ns
FRZAN
t
—
IPZ
t
—
IP
t
t
B9 DSCLK Low Time
1
DSCLO
cyc
t
t
B10 IPIPE1 High Impedance to FREEZE Asserted
TBD
TBD
—
IPFA
cyc
t
t
B11 FREEZE Negated to IPIPE[0:1] Active
NOTES:
—
FRIP
cyc
1. All AC timing is shown with respect to 20% V
and 70% V
levels unless otherwise noted.
DD
DD
CLKOUT
FREEZE
B3
B2
BKPT/DSCLK
B9
B5
B1
B0
IPIPE1/DSI
B4
IPIPE0/DSO
16 BDM SER COM TIM
Figure A–13 BDM Serial Communication Timing Diagram
CLKOUT
FREEZE
B6
B6
B11
B7
B10
IPIPE1/DSI
B8
16 BDM FRZ TIM
Figure A–14 BDM Freeze Assertion Timing Diagram
MOTOROLA
M68HC16ZEC25/D
18
Table A–8 ECLK Bus Timing
1
(V and V
= 5.0 Vdc ± 5%, V = 0 Vdc, T = T to T
)
H
DD
DDSYN
SS
A
L
Num
Characteristic
Symbol
Min
—
10
—
10
20
25
5
Max
40
—
100
—
—
—
—
40
—
1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
t
E1 ECLK Low to Address Valid
E2 ECLK Low to Address Hold
E3 ECLK Low to CS Valid (CS Delay)
E4 ECLK Low to CS Hold
EAD
t
EAH
t
ECSD
t
ECSH
t
E5 CS Negated Width
ECSN
t
E6 Read Data Setup Time
EDSR
t
E7 Read Data Hold Time
EDHR
t
E8 ECLK Low to Data High Impedance
E9 CS Negated to Data Hold (Read)
E10 CS Negated to Data High Impedance
E11 ECLK Low to Data Valid (Write)
E12 ECLK Low to Data Hold (Write)
—
0
EDHZ
t
ECDH
t
t
—
—
5
ECDZ
cyc
t
t
2
EDDW
cyc
t
—
—
—
1/2
ns
ns
ns
EDHW
3
t
E13 Address Access Time (Read)
255
195
—
EACC
4
t
E14 Chip-Select Access Time (Read)
EACS
t
t
E15 Address Setup Time
EAS
cyc
NOTES:
1. All AC timing is shown with respect to 20% V
and 70% V
levels unless otherwise noted.
DD
DD
2. When previous bus cycle is not an ECLK cycle, the address may be valid before ECLK goes low.
3. Address access time = t
Ecyc
– t
– t
.
EAD
EDSR
4. Chip select access time = t
– t
– t
.
Ecyc
ECSD
EDSR
CLKOUT
ECLK
2A
3A
1A
R/W
E1
E2
ADDR[23:0]
E5
E3
E14
E13
E4
CS
E6
E15
E9
DATA[15:0]
READ
E7
WRITE
E8
E11
E10
DATA[15:0]
WRITE
E12
HC16 E CYCLE TIM
Figure A–15 ECLK Timing Diagram
M68HC16ZEC25/D
MOTOROLA
19
Table A–9 QSPI Timing
1
(V and V
= 5.0 Vdc ± 5%, V = 0 Vdc, T = T to T
, 200 pF load on all QSPI pins)
DD
DDSYN
SS
A
L
H
Num
Function
Symbol
Min
Max
Unit
Operating Frequency
Master
Slave
f
1
DC
DC
1/4
1/4
System Clock Frequency
System Clock Frequency
op
Cycle Time
Master
Slave
t
t
2
3
4
5
4
4
510
—
cyc
qcyc
t
cyc
Enable Lead Time
Master
Slave
t
t
t
2
2
128
—
cyc
lead
cyc
Enable Lag Time
Master
Slave
t
SCK
—
2
1/2
—
lag
t
cyc
Clock (SCK) High or Low Time
Master
2 t
cyc
2 t
cyc
– 30
– n
t
sw
255 t
cyc
ns
ns
2
Slave
—
Sequential Transfer Delay
Master
Slave (Does Not Require Deselect)
t
t
6
7
17
13
8192
—
cyc
td
t
cyc
Data Setup Time (Inputs)
Master
Slave
t
su
20
20
—
—
ns
ns
Data Hold Time (Inputs)
t
8
9
Master
Slave
0
20
—
—
ns
ns
hi
t
t
t
Slave Access Time
—
—
1
2
a
cyc
cyc
t
10 Slave MISO Disable Time
Data Valid (after SCK Edge)
dis
t
v
11
Master
Slave
—
—
50
50
ns
ns
Data Hold Time (Outputs)
t
12
Master
Slave
0
0
—
—
ns
ns
ho
Rise Time
Input
Output
t
13
14
—
—
2
30
µs
ns
ri
t
ro
Fall Time
Input
Output
t
—
—
2
30
µs
ns
fi
t
fo
NOTES:
1. All AC timing is shown with respect to 20% V
and 70% V
levels unless otherwise noted.
DD
DD
2. For high time, n = External SCK rise time; for low time, n = External SCK fall time.
MOTOROLA
M68HC16ZEC25/D
20
3
2
PCS[3:0]
OUTPUT
5
13
12
SCK
CPOL=0
OUTPUT
4
1
SCK
CPOL=1
OUTPUT
12
6
4
13
7
MISO
INPUT
MSB IN
DATA
LSB IN
MSB IN
11
10
LSB OUT
MOSI
OUTPUT
MSB OUT
DATA
PORT DATA
12
MSB OUT
PD
13
16 QSPI MAST CPHA0
Figure A–16 QSPI Timing — Master, CPHA = 0
3
2
PCS[3:0]
OUTPUT
5
13
12
1
SCK
CPOL=0
OUTPUT
4
1
7
SCK
CPOL=1
OUTPUT
12
4
13
6
MISO
INPUT
DATA
DATA
LSB IN
MSB
MSB
MSB IN
11
10
LSB OUT
MOSI
OUTPUT
MSB OUT
PORT DATA
12
PORT DATA
13
16 QSPI MAST CPHA1
Figure A–17 QSPI Timing — Master, CPHA = 1
M68HC16ZEC25/D
MOTOROLA
21
3
2
SS
INPUT
5
13
12
SCK
CPOL=0
INPUT
4
1
SCK
CPOL=1
INPUT
12
4
13
11
10
11
8
9
MISO
OUTPUT
MSB OUT
DATA
LSB OUT
PD
13
MSB OUT
MSB IN
7
6
MOSI
INPUT
MSB IN
DATA
LSB IN
16 QSPI SLV CPHA0
Figure A–18 QSPI Timing — Slave, CPHA = 0
SS
INPUT
5
1
13
4
12
SCK
CPOL=0
INPUT
4
3
2
SCK
CPOL=1
INPUT
12
13
11
10
9
10
8
SLAVE
LSB OUT
MISO
OUTPUT
PD
MSB OUT
DATA
DATA
PD
12
7
6
MOSI
INPUT
MSB IN
LSB IN
16 QSPI SLV CPHA1
Figure A–19 QSPI Timing — Slave, CPHA = 1
MOTOROLA
M68HC16ZEC25/D
22
Table A–10 ADC Maximum Ratings
Num
Parameter
Symbol
Min
–0.3
–0.3
–0.3
–0.1
–6.5
–6.5
–6.5
–6.5
Max
6.5
6.5
6.5
0.1
6.5
6.5
6.5
6.5
Unit
V
V
DDA
1
2
3
4
5
6
7
8
Analog Supply
Internal Digital Supply, with reference to V
V
V
SSI
DDI
Reference Supply, with reference to V
V
, V
V
V
SSI
RH
RL
V
V
V
V
V
Differential Voltage
Differential Voltage
Differential Voltage
V
V
V
SS
DD
SSI – SSA
V
V
DDI – DDA
V
V
V
REF
RH – RL
to V
Differential Voltage
Differential Voltage
V
V
V
RH
RL
DDA
RH – DDA
to V
V
V
V
SSA
RL – SSA
1 2 3 4 5 6 7
, , , , ,
,
Disruptive Input Current
I
9
–500
500
µA
V
V
–0.3 V
8 V
NA
NEGCLAMP
POSCLAMP
8
1, 5, 6,
K
10
11
2000
500
—
—
—
—
Positive Overvoltage Current Coupling Ratio
Negative Overvoltage Current Coupling Ratio
P
1, 5, 6, 8
K
N
3, 4, 6
Maximum Input Current
I
12
–25
25
mA
V
V
–0.3 V
8 V
MA
NEGCLAMP
POSCLAMP
NOTES:
1. Below disruptive current conditions, a stressed channel will store the maximum conversion value for
analog inputs greater than V and the minimum conversion value for inputs less than V . This as-
RH RL
sumes that V
≤ V
and V ≥ V
due to the presence of the sample amplifier. Other channels
RH
DDA
RL SSA
are not affected by non-disruptive conditions
2. Input signals with large slew rates or high frequency noise components cannot be converted accurate-
ly. These signals also interfere with conversion of other channels.
3. Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transi-
tions within the limit do not affect device reliability or cause permanent damage.
4. Input must be current limited to the value specified. To determine the value of the required current-lim-
iting resistor, calculate resistance values using positive and negative clamp values, then use the larger
of the calculated values.
5. This parameter is periodically sampled rather than 100% tested.
6. Applies to single pin only.
7. The values of external system components can change the maximum input current value, and affect
operation. A voltage drop may occur across the external source impedances of the adjacent pins, im-
pacting conversions on these adjacent pins. The actual maximum may need to be determined by test-
ing the complete design.
8. Current coupling is the ratio of the current induced from overvoltage (positive or negative, through an
external series coupling resistor), divided by the current induced on adjacent pins. A voltage drop may
occur across the external source impedances of the adjacent pins, impacting conversions on these ad-
jacent pins
M68HC16ZEC25/D
MOTOROLA
23
Table A–11 ADC DC Electrical Characteristics (Operating)
(VSS = 0 Vdc, ADCLK = 2.1 MHz, T = T to T )
A
L
H
Num
Parameter
Symbol
Min
Max
5.5
5.5
1.0
1.0
Unit
V
1
V
1
2
3
4
5
6
4.5
4.5
Analog Supply
Internal Digital Supply
DDA
1
V
V
DDI
V
Differential Voltage
Differential Voltage
V
V
V
– 1.0
– 1.0
mV
V
SS
DD
SSI – SSA
V
V
DDI – DDA
2 3
,
V
V
V
/ 2
DDA
V
Reference Voltage Low
Reference Voltage High
RL
SSA
2, 3
V
V
/ 2
V
DDA
V
RH
DDA
4.5
V
3
V
V
7
8
9
5.5
V
V
REF
Differential Voltage
RH – RL
2
V
V
DDA
V
V
V
Input Voltage
Input High, Port ADA
INDC
SSA
V
IH
0.7 (V
)
V
+ 0.3
DDA
DDA
V
V
0.3
0.2 (V
)
10 Input Low, Port ADA
IL
SSA –
DDA
Analog Supply Current
4
I
11
—
—
1.0
mA
Normal Operation
Low-power stop
DDA
200
250
150
10
µA
I
12 Reference Supply Current
—
—
—
—
µA
nA
pF
pF
REF
5
I
13
Input Current, Off Channel
OFF
C
14 Total Input Capacitance, Not Sampling
INN
C
15 Total Input Capacitance, Sampling
NOTES:
15
INS
1. Refers to operation over full temperature and frequency range.
2. To obtain full-scale, full-range results, V ≤ V ≤ V ≤ V
≤ V
DDA.
SSA
RL
INDC
RH
3. Accuracy tested and guaranteed at V
– V = 5.0 V ± 5%.
RH
RL
4. Current measured at maximum system clock frequency with ADC active.
5. Maximum leakage occurs at maximum operating temperature. Current decreases by approximately
one-half for each 10°C decrease from maximum temperature.
Table A–12 ADC AC Characteristics (Operating)
(VDD and VDDA = 5.0 Vdc ± 5%, VSS = 0 Vdc, TA within operating temperature range)
Num
Parameter
ADC Clock Frequency
Symbol
Min
Max
Unit
f
1
0.5
2.1
MHz
adclk
1
8-bit Conversion Time
t
2
F
F
= 1.0 MHz
= 2.1 MHz
15.2
7.6
—
µs
conv
ADCLK
ADCLK
1
10-bit Conversion Time
t
3
4
17.1
8.6
—
µs
µs
F
= 1.0 MHz
= 2.1 MHz
conv
ADCLK
ADCLK
F
t
Stop Recovery Time
—
10
sr
NOTES:
1. Conversion accuracy varies with f
rate. Reduced conversion accuracy occurs at maximum.
adclK
MOTOROLA
M68HC16ZEC25/D
24
Table A–13 ADC Conversion Characteristics (Operating)
(VDD and VDDA = 5.0 Vdc ± 5%, VSS = 0 Vdc, TA = TL to TH,
0.5 MHz ≤ fadclk ≤ 1.0 MHz, 2 clock input sample time)
Num
Parameter
Symbol
Min
Typ
Max
Unit
1
1
1 Count
—
20
—
mV
8-bit Resolution
2
3
8-bit Differential Nonlinearity
8-bit Integral Nonlinearity
DNL
INL
–0.5
–1
—
—
0.5
1
Counts
Counts
2
4
5
6
7
8
9
AE
1 Count
DNL
INL
–1
—
—
5
1
Counts
mV
8-bit Absolute Error
1
—
10-bit Resolution
3
–0.5
–2.0
–2.5
—
—
—
—
20
0.5
2.0
2.5
—
Counts
Counts
Counts
kΩ
10-bit Differential Nonlinearity
3
10-bit Integral Nonlinearity
3, 4
AE
10-bit Absolute Error
5
R
S
Source Impedance at Input
NOTES:
1. At V
–V = 5.12 V, one 10-bit count = 5 mV and one 8-bit count = 20 mV.
RL
RH
2. 8-bit absolute error of 1 count (20 mV) includes 1/2 count (10 mV) inherent quantization error and 1/2
count (10 mV) circuit (differential, integral, and offset) error.
3. Conversion accuracy varies with f
adclk
rate. Reduced conversion accuracy occurs at maximum F
AD-
. Assumes that minimum sample time (2 ADC Clocks) is selected.
CLK
4. 10-bit absolute error of 2.5 counts (12.5 mV) includes 1/2 count (2.5 mV) inherent quantization error
and 2 counts (10 mV) circuit (differential, integral, and offset) error.
5. Maximum source impedance is application-dependent. Error resulting from pin leakage depends on
junction leakage into the pin and on leakage due to charge-sharing with internal capacitance.
Error from junction leakage is a function of external source impedance and input leakage current. In
the following expression, expected error in result value due to junction leakage (V ) is expressed:
errj
V
= R X I
OFF
errj
S
where I
OFF
is a function of operating temperature, as shown in table A-11.
Charge-sharing leakage is a function of input source impedance, conversion rate, change in voltage
between successive conversions, and the size of the decoupling capacitor used. Error levels are best
determined empirically. In general, continuous conversion of the same channel may not be compatible
with high source impedance.
M68HC16ZEC25/D
MOTOROLA
25
IDEAL TRANSFER CURVE
8-BIT TRANSFER CURVE
(NO CIRCUIT ERROR)
A
C
B
0
20
40
INPUT IN mV, V – V = 5.120 V
60
RH
RL
A – +1/2 COUNT (10 mV) INHERENT QUANTIZATION ERROR
B – CIRCUIT-CONTRIBUTED +10mV ERROR
– + 20 mV ABSOLUTE ERROR (ONE 8-BIT COUNT)
C
ADC 8-BIT ACCURACY
Figure A–20 8-Bit ADC Conversion Accuracy
IDEAL TRANSFER CURVE
10-BIT TRANSFER CURVE
(NO CIRCUIT ERROR)
C
B
A
0
20
40
INPUT IN mV, V – V = 5.120 V
60
RH
RL
– +.5 COUNT (2.5 mV) INHERENT QUANTIZATION ERROR
A
B – CIRCUIT-CONTRIBUTED +10 mV ERROR
C – +12.5 mV ABSOLUTE ERROR (2.5 10-BIT COUNTS)
ADC 10-BIT ACCURACY
Figure A–21 10-Bit ADC Conversion Accuracy
MOTOROLA
M68HC16ZEC25/D
26
NOTES
M68HC16ZEC25/D
MOTOROLA
27
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