MP2319GJ_技术文档

MP2319

3A, 18V, 650kHz, High-Efficiency,

Synchronous, Step-Down Converter

in 8-Pin TSOT23

DESCRIPTION

FEATURES

The MP2319 is

a

fully-integrated, high-



Wide 4.5V to 18V Operating Input Range

3A Output Current

105mΩ/57mΩ Low R_DS(ON)Internal Power

MOSFETs

Output Adjustable from 0.8V

EN Shutdown Output Discharge

Internal Soft Start

High-Efficiency Synchronous Mode

Operation

frequency, synchronous, rectified, step-down,

switch-mode converter with internal power

MOSFETs. The MP2319 offers a very compact

solution that achieves 3A of continuous output

current with excellent load and line regulation

over a wide input range. The MP2319 has

synchronous mode operation for higher

efficiency over the output current load range.



Constant-on-time control operation provides a

very fast transient response, easy loop design,

and very tight output regulation.



Fixed 650kHz Switching Frequency

EN and Power Good for Power Sequencing

Over-Current Protection (OCP) and Hiccup

Thermal Shutdown

Auto-Retry Over-Voltage Protection (OVP)

Available in a TSOT23-8 Package

Full protection features include short-circuit

protection (SCP), over-current protection (OCP),

under-voltage protection (UVP), over-voltage

protection (OVP), and thermal shutdown.

APPLICATIONS

The MP2319 requires a minimal number of



Security Cameras

Portable Devices, xDSL Devices

Digital Set-Top Boxes

Flat-Panel Televisions and Monitors

General Purposes

readily

available,

standard,

external

components and is available in a space-saving,

8-pin, TSOT23 package.

All MPS parts are lead-free, halogen-free, and adhere to the RoHS

directive. For MPS green status, please visit the MPS website under

Quality Assurance. “MPS” and “The Future of Analog IC Technology” are

registered trademarks of Monolithic Power Systems, Inc.

TYPICAL APPLICATION

R4

10Ω

VIN

4.5V-18V

IN

BST

SW

C4

0.1µ

F

C1

22µF

L1

2.2µH

MP2319

VOUT

3.3V/3A

EN

PG

EN

PG

C2

22µFx2

R1

30k

FB

R3

1K

VCC

R2

9.53k

C3

0.1µF

GND

MP2319 Rev.1.0

6/29/2016

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1

MP2319 – 18V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER

ORDERING INFORMATION

Part Number*

Package

Top Marking

MP2319GJ

TSOT23-8

See Below

* For Tape & Reel, add suffix –Z (e.g. MP2319GJ–Z)

TOP MARKING

APV: Product code of MP2319GJ

Y: Year code

PACKAGE REFERENCE

TOP VIEW

PG

IN

FB

1

8

7

VCC

EN

2

3

4

SW

GND

6

5

BST

TSOT23-8

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MP2319 – 18V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER

ABSOLUTE MAXIMUM RATINGS ⁽¹⁾

V_IN................................................ -0.3V to +22V

V_SW.... -0.6V (-5V < 10ns) to +22V (23V < 10ns)

V_BST..................................................V_SW+ 5.5V

V_EN................................................................ V_IN

All other pins............................... -0.3V to +5.5V

Thermal Resistance ⁽⁴⁾θ_JA

TSOT23-8 ............................ 100......55 ... °C/W

θ_JC

NOTES:

1) Exceeding these ratings may damage the device.

2) The maximum allowable power dissipation is a function of the

maximum junction temperature T_J(MAX), the junction-to-

ambient thermal resistance θ_JA, and the ambient temperature

T_A. The maximum allowable continuous power dissipation at

any ambient temperature is calculated by P_D(MAX) = (T_J

(MAX)-T_A)/θ_JA. Exceeding the maximum allowable power

dissipation produces an excessive die temperature, causing

the regulator to go into thermal shutdown. Internal thermal

shutdown circuitry protects the device from permanent

damage.

(2)

Continuous power dissipation (T_A= +25°C)

……………………………………………….1.25W

Junction temperature...............................150°C

Lead temperature ....................................260°C

Storage temperature..................-65°C to 150°C

3) The device is not guaranteed to function outside of its

operating conditions.

4) Measured on JESD51-7, 4-layer PCB.

Recommended Operating Conditions ⁽³⁾

Supply voltage (V_IN) ........................ 4.5V to 18V

Output voltage (V_OUT)...................... 0.8V to 12V

Operating junction temp...........-40°C to +125°C

MP2319 Rev.1.0

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MP2319 – 18V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER

ELECTRICAL CHARACTERISTICS

V_IN= 12V, T_J= -40°C to +125°C⁽⁵⁾, unless otherwise noted. Typical value is based on the average

value when T_J= 25°C.

Parameter

Symbol Condition

Min

Typ

Max

Units

Supply Current

Supply current (shutdown)

Supply current (quiescent)

MOSFET

I_IN

I_q

V_EN= 0V

1.2

5

µA

V_EN= 2V, V_FB= 0.9V

270

350

HS switch on resistance

LS switch on resistance

Switch leakage

HS_RDS(ON)V_{BST - SW}= 5V

LS_RDS(ON)V_CC= 5V

105

57

mΩ

µA

SW_LKGV_EN= 0V, V_SW= 12V/0V

1

Current Limit and ZCD

Valley current limit

ZCD

I_{LIMIT_VY}Duty = 40%

I_ZCD

2.8

3.5

50

A

mA

Switching Frequency and Minimum On/Off Timer

Switching frequency

Minimum on time⁽⁶⁾

Minimum off time⁽⁶⁾

Reference and Soft Start

Feedback voltage

Fs

510

650

55

790

kHz

ns

T_{On MIN}

T_{Off MIN}

90

ns

V_FB

I_FB

T_J= 25°C

792

788

800

10

808

812

50

mV

nA

Feedback voltage

T_J= -40°C to +125°C

V_FB= 820mV

Feedback current

Soft-start period

t_SS

V_OUT= 10% to 90%

0.8

ms

Enable (EN) and UVLO

EN rising threshold

V_{EN RISING}

V_{EN _Hys}

R_{EN_PD}

1.22

3.4

1.285

140

1.35

4.3

V

EN falling hysteresis

EN pull-down resistor

mV

MΩ

1.1

V_INunder-voltage lockout

threshold rising

INUV_Vth

3.85

670

V

V_INunder-voltage lockout

threshold hysteresis

INUV_HYS

mV

VCC

VCC regulator

VCC load regulation

OVP

V_CC

5

V

I_CC= 5mA

3

%

OVP rising threshold

OVP falling threshold

V_{OVP1_RISE}

V_{OVP_FALL}

1.18

1.22

1.26

V_REF

1.025

1.065

1.105

MP2319 Rev.1.0

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MP2319 – 18V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER

ELECTRICAL CHARACTERISTICS (continued)

V_IN= 12V, T_J= -40°C to +125°C⁽⁵⁾, unless otherwise noted. Typical value is based on the average

value when T_J= 25°C.

Parameter

Symbol Condition

Min

Typ

Max

Units

Power Good

Power good UV rising

threshold

PG_{vth_Hi}

PG_{vth_Lo}

0.875

0.77

0.915

0.81

0.955

0.85

V_FB

Power good UV falling

threshold

Power good OV rising

threshold

PG_{vth_Hi_OV}

PG_{vth_Lo_OV}

1.025

1.18

1.065

1.22

1.105

1.26

Power good OV falling

threshold

Power good low to high delay

Power good high to low delay

PG_Td

56

40

µs

Power good sink current

capability

V_PG

Sink 4mA

0.4

10

V

Power good leakage current

I_{PG_LEAK}V_PG= 5V

2.5

μA

Thermal Protection

Thermal shutdown⁽⁶⁾

Thermal hysteresis⁽⁶⁾

NOTES:

T_SD

150

20

°C

T_{SD_HYS}

5) Not tested in production. Guaranteed by over-temperature correlation.

6) Guaranteed by design and characterization test.

MP2319 Rev.1.0

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MP2319 – 18V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER

TYPICAL PERFORMANCE CHARACTERISTICS

V_IN= 12V, V_OUT= 3.3V, L = 2.2µH, T_A= 25°C, unless otherwise noted.

MP2319 Rev.1.0

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MP2319 – 18V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

V_IN= 12V, V_OUT= 3.3V, L = 2.2µH, T_A= 25°C, unless otherwise noted.

MP2319 Rev.1.0

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MP2319 – 18V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

V_IN= 12V, V_OUT= 3.3V, L = 2.2µH, T_A= 25°C, unless otherwise noted.

MP2319 Rev.1.0

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MP2319 – 18V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

V_IN= 12V, V_OUT= 3.3V, L = 2.2µH, T_A= 25°C, unless otherwise noted.

MP2319 Rev.1.0

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MP2319 – 18V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER

PIN FUNCTIONS

Package

Pin #

Name Description

Power good output. The output of PG is an open drain that goes high if the output voltage

is within a nominal output window.

1

PG

Supply voltage. The MP2319 operates from a 4.5V to 18V input rail. C1 is needed to

decouple the input rail. Connect IN using wide PCB traces.

2

3

4

IN

SW

Switch output. Connect SW using wide PCB traces.

System ground. GND is the reference ground of the regulated output voltage. GND requires

careful consideration during PCB layout. Connect GND with copper traces and vias.

GND

Bootstrap. Connect a capacitor between SW and BS to form a floating supply across the

5

BST high-side switch driver. Place a 10Ω resistor between the SW and BST cap to reduce SW

voltage spikes.

Enable. Set EN = 1 to enable the MP2319. When floating, EN is pulled down to GND by an

internal 1.1MΩ resistor, and the MP2319 is disabled.

6

7

8

EN

Internal bias supply. Decouple VCC with a 0.1µF to 0.22µF capacitor. The capacitor should

not exceed 0.22µF. The VCC capacitor should be placed close to VCC and GND.

VCC

Feedback. FB sets the output voltage when connected to the tap of an external resistor

divider that is connected between the output and GND.

FB

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MP2319 – 18V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER

BLOCK DIAGRAM

VIN

5V LDO

VCC

EN

BST

REG

BST

Reference

HS

Driver

HSG

OV_TH

UV_TH

LSG

Logic

Control

SW

On Timer

Error

Amplifier

PWM

Comparator

HSG

LSG

LS

Driver

FB

Ramp

ZCD

Valley

Current

Limit &

ZCD

xLIM

GND

OV Detect

Comparator

OV_TH

UV_TH

PG

UV Detect

Comparator

Figure 1: Functional Block Diagram

MP2319 Rev.1.0

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MP2319 – 18V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER

Heavy-Load Operation

OPERATION

Continuous conduction mode (CCM) occurs

The MP2319 is fully integrated, synchronous,

rectified, step-down, switch-mode converter.

Constant-on-time (COT) control is employed to

provide a fast transient response and ease loop

stabilization. Figure 2 shows the simplified ramp

compensation block in the MP2319.

when the output current is high, and the

inductor current is always above zero amps

(see Figure 3). When V_FBis below V_EAO, the

HS-FET is turned on for a fixed interval

determined by the one-shot on-timer. When the

HS-FET is turned off, the LS-FET is turned on

until the next period.

At the beginning of each cycle, the high-side

MOSFET (HS-FET) is turned on when the

feedback voltage (V_FB) is below the reference

voltage (V_REF), which indicates insufficient

output voltage. The on period is determined by

both the output voltage and input voltage to

make the switching frequency fairly constant

over the input voltage range.

After the on period elapses, the HS-FET is

turned off or enters an off state. It is turned on

again when V_FBdrops below V_REF. By repeating

this operation, the converter regulates the

output voltage. The integrated low-side

MOSFET (LS-FET) is turned on when the HS-

FET is in its off state to minimize conduction

loss. There is a dead short between the input

and GND if both the HS-FET and LS-FET are

turned on at the same time. This is called a

shoot-through. To prevent a shoot-through, a

dead time (DT) is generated internally between

HS-FET off and LS-FET on, or LS-FET off and

HS-FET on.

Figure 3: Heavy-Load Operation

In CCM operation, the switching frequency is

fairly constant. This is called pulse-width

modulation (PWM) mode.

Light-Load Operation

When the MP2319 works in pulse-frequency

modulation (PFM) and light-load operation, the

MP2319 reduces the switching frequency

automatically to maintain high efficiency, and

the inductor current drops almost to zero. When

the inductor current reaches zero, the LS-FET

driver goes into tri-state (Hi-Z) (see Figure 4).

Therefore, the output capacitors discharge

slowly to GND through R1 and R2. This

operation improves the device efficiency greatly

when the output current is low.

Internal compensation is applied for COT

control to provide a more stable operation, even

when ceramic capacitors are used as output

capacitors.

This

internal

compensation

improves jitter performance without affecting

the line or load regulation.

T_ONis constant

V_IN

REF

L

VOUT

On

Logic

FB

Timer

Control

V_SW

SW

RAMP

R_ESR

Cout

R1

R2

V_OUT

I_L

I_OUT

PWM

RAMP

GENERATOR

V_RAMP

V_EAO

Figure 2: Simplified Ramp Compensation Block

Figure 4: Light-Load Operation

MP2319 Rev. 1.0

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MP2319 – 18V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER

Light-load operation is also called skip mode

Power Good (PG) Indicator

because the HS-FET does not turn on as

frequently as it does in heavy-load conditions.

The frequency at which the HS-FET turns on is

a function of the output current. As the output

current increases, the time period that the

current modulator regulates becomes shorter,

and the HS-FET turns on more frequently. The

switching frequency increases in turn. The output

current reaches critical levels when the current

modulator time is zero, and can be determined

with Equation (1):

The MP2319 uses a power good (PG) output to

indicate whether the output voltage of the

module is ready or not. PG is an open-drain

output. Connect PG to VCC or another voltage

source through a pull-up resistor (e.g.: 100kΩ).

When input voltage is applied, PG is pulled

down to GND before the internal V_SS> 1V. After

V_SS> 1V, when V_FBis above 91.5% of V_REF, PG

is pulled high after a 56µs delay. During normal

operation, PG is pulled low when V_FBdrops

below 81% of V_REFafter a 40µs delay.

(VIN  VOUT) VOUT

2LFSW  VIN

When UVLO or OTP occurs, PG is pulled low

immediately. When over-current (OC) occurs,

PG is pulled low when V_FBdrops below 81% of

V_REFafter a 40µs delay. PG is pulled low to

indicate output over-voltage when V_FBrises

above 122% of V_REFafter a 40µs delay. If V_FB

falls below 105% after over-voltage protection

(OVP), PG is pulled high after a 56µs delay.

I_OUT



(1)

The device reverts to PWM mode once the

output current exceeds the critical level.

Afterward, the switching frequency remains

fairly constant over the output current range.

Enable (EN)

Over-Current Protection (OCP) and Short-

Circuit Protection (SCP)

EN is a digital control pin that turns the

regulator on and off. Drive EN high to turn on

the regulator; drive EN low to turn off the

regulator. When floating, EN is pulled down to

GND by an internal 1.1MΩ resistor. EN can be

connected directly to V_IN. EN supports an 18V

input range.

The MP2319 has a valley limit control. During

the LS-FET on state, the inductor current is

monitored. When the sensed inductor current

reaches the valley current limit, the LS limit

comparator (shown in Figure 1) turns over, and

the MP2319 enters over-current protection

(OCP) mode. The HS-FET waits until the

inductor current falls below the valley current

limit before turning on again. Meanwhile, the

output voltage drops until V_FBis below the

under-voltage (UV) threshold, typically 50%

below the reference. Once UV is triggered, the

MP2319 enters hiccup mode to restart the part

periodically.

Under-Voltage Lockout (UVLO)

Under-voltage lockout (UVLO) protects the chip

from operating at an insufficient supply voltage.

The MP2319 UVLO comparator monitors the

output voltage of the internal regulator (VCC).

The UVLO rising threshold is about 3.85V,

while its falling threshold is 3.18V consistently.

Internal Soft Start (SS)

Soft start (SS) prevents the converter output

voltage from overshooting during start-up.

When the chip starts up, the internal circuitry

generates a soft-start voltage (SS) that ramps

up from 0V to 1.2V. When SS is lower than

REF, SS overrides REF so the error amplifier

uses SS as the reference. When SS exceeds

REF, the error amplifier uses REF as the

reference. The SS time is set to 0.8ms

internally.

During OCP, the device attempts to recover

from the over-current fault with hiccup mode.

The MP2319 disables the output power stage,

discharges the soft-start cap, and then tries to

soft-start automatically. If the over-current

condition still remains after the soft-start ends,

the MP2319 repeats this operation cycle until

the over-current condition is removed, and then

the output rises back to regulation levels. OCP

is a non-latch protection.

MP2319 Rev.1.0

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13

MP2319 – 18V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER

Over-Voltage Protection (OVP)

Thermal Shutdown

The MP2319 monitors the resistor-divided

feedback voltage to detect over-voltage (OV).

When the feedback voltage rises higher than

122% of the target voltage, the controller enters

a dynamic regulation period. During this period,

the LS-FET is on until the LS current drops to

-2.5A. This discharges the output to keep it

within the normal range. If the OV still remains,

the LS-FET turns on again after a 400ns delay.

The MP2319 exits this regulation period when

the feedback voltage is decreased below

106.5% of the reference voltage.

Thermal shutdown prevents the chip from

operating at exceedingly high temperatures.

When the silicon die temperature exceeds

150°C, the entire chip shuts down. When the

temperature falls below its lower threshold

(typically 130°C), the chip is enabled again.

Floating Driver and Bootstrap Charging

An external bootstrap capacitor powers the

floating power MOSFET driver. This floating

driver has its own UVLO protection with a rising

threshold of 2.2V and a hysteresis of 150mV.

V_INregulates the bootstrap capacitor voltage

through D1, M1, R4, C4, L1, and C2 internally

(see Figure 5). If V_IN- V_SWexceeds 5V, U2

regulates M1 to maintain a 5V BST voltage

across C4.

Under-Voltage Lockout (UVLO)

The MP2319 has under-voltage lockout

protection (UVLO). When the input voltage is

higher than the UVLO rising threshold voltage,

the MP2319 powers up. The MP2319 shuts off

when the input voltage is lower than the UVLO

falling threshold voltage. UVLO is a non-latch

protection.

Pre-Bias Start-Up

The MP2319 has been designed for monotonic

start-up into pre-biased loads. If the output is

pre-biased to a certain voltage during start-up,

the BST voltage is refreshed and charged, and

the voltage on the soft-start capacitor is

charged as well. If the BST voltage exceeds its

rising threshold voltage, and the soft-start

capacitor voltage exceeds the sensed output

voltage at FB, the part begins working normally.

Figure 5: Internal Bootstrap Charger Start-Up

and Shutdown Circuit

If both V_INand EN exceed their respective

thresholds, the chip starts up. The reference

block starts first, generating stable reference

voltages and currents, and then the internal

regulator is enabled. The regulator provides a

stable supply for the remaining circuits.

Output Discharge

The MP2319 has a discharge function that

provides an active discharge path for the

external output capacitor. The function is active

when the part is in the EN off state. When EN is

off, the HS-FET turns off, and the LS-FET turns

on to discharge V_OUT. When the LS-FET current

reaches -1A, the LS-FET turns off. After a

400ns delay, the LS-FET turns on again. This

behavior repeats until FB low occurs.

Three events can shut down the chip: EN low,

V_INlow, and thermal shutdown. The shutdown

procedure starts by blocking the signaling path

initially to avoid any fault triggering. The COMP

voltage (V_COMP) and the internal supply rail are

then pulled down. The floating driver is not

subject to this shutdown command.

MP2319 Rev. 1.0

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14

MP2319 – 18V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER

The inductance value can be calculated with

Equation (3):

APPLICATION INFORMATION

Setting the Output Voltage

V_OUT

_SW I_L

V_OUT

The external resistor divider is used to set the

output voltage (see the Typical Application on

page 1). Refer to Table 1 to choose R1. R2 can

then be calculated with Equation (2):

(3)

L 

(1

)

F

V

IN

Where ∆I_Lis the peak-to-peak inductor ripple

current.

R1

The inductor should not saturate under the

maximum inductor peak current, which can be

calculated with Equation (4):

R2 

(2)

V

OUT

 1

0.8V

V_OUT

I_LP I_OUT



(1

)

(4)

The feedback circuit is shown in Figure 6.

2F_SWL

V

IN

V_OUT

Selecting the Input Capacitor

The input current to the step-down converter is

discontinuous and therefore requires

capacitor to supply AC current to the step-down

converter while maintaining the DC input

voltage. Ceramic capacitors are recommended

for best performance and should be placed as

close to V_INas possible. Capacitors with X5R

and X7R ceramic dielectrics are recommended

because they are fairly stable with temperature

fluctuations.

MP2319

R1

a

R3

C6

FB

R2

Figure 6: Feedback Network

Table 1 lists the recommended resistor values

for common output voltages.

The capacitors must also have a ripple current

rating greater than the maximum input ripple

current of the converter. The input ripple current

can be estimated with Equation (5):

Table 1: Resistor Selection for Common Output

Voltages

V_OUT(V) R1 (kΩ) R2 (kΩ) R3 (kΩ) C6 (pF)

1

30

120

60.4

24

14

9.53

5.76

1

100

V_OUT

1.2

1.8

2.5

3.3

5

(5)

I_CIN I_OUT



(1

)

V

IN

The worst-case condition occurs at V_IN= 2V_OUT

shown in Equation (6):

,

I_OUT

Selecting the Inductor

I_CIN



(6)

2

The inductor is necessary to supply constant

current to the output load while being driven by

the switched input voltage. An inductor with a

larger value results in less ripple current and a

lower output ripple voltage. However, the

larger-value inductor also has a larger physical

footprint, higher series resistance, and lower

saturation current. A good rule for determining

the inductance value is to design the peak-to-

peak ripple current in the inductor to be in the

range of 30% to 40% of the maximum output

current. The peak inductor current should be

below the maximum switch current limit.

For simplification, choose an input capacitor

with an RMS current rating greater than half of

the maximum load current.

The input capacitance value determines the

input voltage ripple of the converter. If there is

an input voltage ripple requirement in the

system, choose the input capacitor that meets

the specification.

MP2319 Rev.1.0

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15

MP2319 – 18V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER

The input voltage ripple can be estimated with

PCB Layout Guidelines

Equation (7):

Efficient layout of the switching power supplies

is critical for proper function and stable

operation. Poor layout design can result in poor

line or load regulation and stability issues. To

I_OUT

F C_IN

V_OUT

V 



(1

)

(7)

IN

V

SW

IN

The worst-case condition occurs at V_IN= 2V_OUT

shown in Equation (8):

,

achieve

better

performances,

it

is

recommended to use two-layer boards. Figure

7 shows the top and bottom layers. For best

results, refer to Figure 7 and follow the

guidelines below.

I_OUT

4 F_SWC_IN

1

V 



(8)

IN

Selecting the Output Capacitor

1) Place the high current paths (GND, IN, and

SW) very close to the device with short,

direct, and wide traces.

The output capacitor is required to maintain the

DC output voltage. Ceramic or POSCAP

capacitors are recommended. The output

voltage ripple can be estimated with Equation

(9):

2) Keep the input capacitor as close to IN and

GND as possible.

3) Place the external feedback resistors next

to FB.

V_OUT

V

1

(1 ^OUT)(R_ESR



(9)

)

V_OUT



F_SWL

V

8F_SWC_OUT

IN

4) Keep the switching node (SW) short and

away from the feedback network.

For ceramic capacitors, the impedance at the

switching frequency is dominated by the

capacitance. The output voltage ripple is mainly

caused by the capacitance. For simplification,

the output voltage ripple can be estimated with

Equation (10):

GND

C4

SW

C3

R5

V_OUT

C1B

L 1

(10)

R7

R6

V_OUT



(1

)

8F ²LC_OUT

V

C1A

C 1

SW

IN

For POSCAP capacitors, the ESR dominates

the impedance at the switching frequency. For

simplification, the output ripple can be

approximated with Equation (11):

Vin

C 2

Vout

C 2A

GND

V_OUT

V

V_OUT



(1 ^OUT)R_ESR(11)

F_SWL

V

IN

Besides the output ripple, a larger output

capacitor can also achieve a better load

transient response. Maximum output capacitor

limitations should be considered in design

applications, also. If the output capacitor value

is too high, the output voltage cannot reach the

design value during the soft-start time and fails

to regulate. The maximum output capacitor

value (C_{o_max}) can be limited approximately with

Equation (20):

GND

VCC

BST

SW

EN /SYNC

VOUT_SENSE

GND

C_{O_MAX} (I_{LIM_ AVG}I_OUT)T / V_OUT(20)

ss

Where I_{LIM_AVG}is the average start-up current

during the soft-start period, and T_ssis the soft-

start time.

Figure 7: Sample Board Layout

MP2319 Rev. 1.0

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16

MP2319 – 18V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER

Design Example

Table 2 shows a design example when ceramic

capacitors are applied.

Table 2: Design Example

V_IN

V_OUT

I_OUT

12V

3.3V

3A

The detailed application schematics are shown

in Figure 8 through Figure 13. The typical

performance and waveforms are shown in the

Typical Characteristics section. For more

devices applications, please refer to the related

evaluation board datasheet.

MP2319 Rev. 1.0

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17

MP2319 – 18V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER

TYPICAL APPLICATION CIRCUITS

R4

10Ω

12V

VIN

IN

BST

SW

C4

0.1µ

F

C1A

22µF

C1

NS

C1B

0.1µF

L1

3.3µH

MP2319

VOUT

5V/3A

R6

0Ω

EN

PG

EN

PG

C2

22µF

C2A

22µF

C6

100pF

R1

30k

R5

100K

FB

R7

NS

VCC

R3

1K

R2

5.76k

C3

0.1µF

GND

Figure 8: Typical Application Circuit 12V_IN, 5V_OUT/3A

R4

10Ω

12V

VIN

IN

BST

SW

C4

0.1µ

F

C1A

22µF

C1

NS

C1B

0.1µF

L1

2.2µH

MP2319

VOUT

3.3V/3A

R6

0Ω

EN

PG

EN

PG

C2

22µF

C2A

22µF

C6

100pF

R1

30k

R5

100K

FB

R7

NS

VCC

R3

1K

R2

9.53k

C3

0.1µF

GND

Figure 9: Typical Application Circuit 12V_IN, 3.3V_OUT/3A

R4

10Ω

12V

VIN

IN

BST

SW

C4

0.1µ

F

C1A

22µF

C1

NS

C1B

0.1µF

L1

2.2µH

MP2319

VOUT

2.5V/3A

R6

0Ω

EN

PG

EN

PG

C2

22µF

C2A

22µF

C6

100pF

R1

30k

R5

100K

FB

R7

NS

VCC

R3

1K

R2

14k

C3

0.1µF

GND

Figure 10: Typical Application Circuit 12V_IN, 2.5V_OUT/3A

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18

MP2319 – 18V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER

TYPICAL APPLICATION CIRCUITS (continued)

R4

10Ω

12V

VIN

IN

BST

C4

0.1µ

F

C1A

22µF

C1

NS

C1B

0.1µF

L1

2.2µH

MP2319

VOUT

1.8V/3A

R6

0Ω

SW

EN

PG

EN

PG

C2

22µF

C2A

22µF

C6

100pF

R1

30k

R5

100K

FB

R7

NS

VCC

R3

1K

R2

24k

C3

0.1µF

GND

Figure 11: Typical Application Circuit 12V_IN, 1.8V_OUT/3A

R4

10Ω

12V

VIN

IN

BST

SW

C4

0.1µ

F

C1A

22µF

C1

NS

C1B

0.1µF

L1

1µH

MP2319

VOUT

1.2V/3A

R6

0Ω

EN

PG

EN

PG

C2

22µF

C2A

22µF

C6

100pF

R1

30k

R5

100K

FB

R7

NS

VCC

R3

1K

R2

60.4k

C3

0.1µF

GND

Figure 12: Typical Application Circuit 12V_IN, 1.2V_OUT/3A

R4

10Ω

12V

VIN

IN

BST

SW

C4

0.1µ

F

C1A

22µF

C1

NS

C1B

0.1µF

L1

1µH

MP2319

VOUT

1V/3A

R6

0Ω

EN

PG

EN

PG

C2

22µF

C2A

22µF

C6

100pF

R1

30k

R5

100K

FB

R7

NS

VCC

R3

1K

R2

120k

C3

0.1µF

GND

Figure 13: Typical Application Circuit 12V_IN, 1V_OUT/3A

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19

MP2319 – 18V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER

PACKAGE INFORMATION

TSOT23-8

See note 7

EXAMPLE

TOP MARK

IAAAA

PIN 1 ID

RECOMMENDED LAND PATTERN

TOP VIEW

SEATING PLANE

SEE DETAIL ''A''

FRONT VIEW

SIDE VIEW

NOTE:

1) ALL DIMENSIONS ARE IN MILLIMETERS.

2) PACKAGE LENGTH DOES NOT INCLUDE MOLD

FLASH, PROTRUSION OR GATE BURR.

3) PACKAGE WIDTH DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

4) LEAD COPLANARITY (BOTTOM OF LEADS

AFTER FORMING) SHALL BE 0.10 MILLIMETERS

MAX.

DETAIL ''A''

5) JEDEC REFERENCE IS MO-193, VARIATION BA.

6) DRAWING IS NOT TO SCALE.

7) PIN 1 IS LOWER LEFT PIN WHEN READING TOP

MARK FROM LEFT TO RIGHT, (SEE EXAMPLE TOP

MARK)

NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third

party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not

assume any legal responsibility for any said applications.

MP2319 Rev. 1.0

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20


型号：	MP2319GJ
厂家：	MONOLITHIC POWER SYSTEMS
描述：	3A, 18V, 650kHz, High-Efficiency, Synchronous, Step-Down Converter in 8-Pin TSOT23
文件：	总20页 (文件大小：1141K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MP2319GJ [MPS]

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