MP2321GD [MPS]
19V, 2A, 40uA IQ, High-Efficiency, Constant-On-Time, Step-Down Converter in a QFN (2mmx3mm) Package;
| 型号： | MP2321GD |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | 19V, 2A, 40uA IQ, High-Efficiency, Constant-On-Time, Step-Down Converter in a QFN (2mmx3mm) Package |
| 文件： | 总24页 (文件大小：4203K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MP2321
19V, 2A, 40µA IQ, High-Efficiency,
Constant-On-Time, Step-Down Converter
in a QFN (2mmx3mm) Package
The Future of Analog IC Technology
DESCRIPTIONꢀ
FEATURES
The MP2321 is a fully-integrated, high-efficiency,
synchronous, step-down, switch-mode converter
with 40μA of quiescent current. The MP2321
achieves 2A of continuous output current over a
wide input supply range with excellent load and line
regulation and can operate with high efficiency over
a wide output current load range. The MP2321 is
optimized for battery-operated applications and
applications requiring high light-load efficiency.
4V to 19V Operating Input Range
2A Output Current
40μA Quiescent Current
Output Adjustable from 0.6V
110mΩ/40mΩ High-Side/Low-Side RDS(ON)
for Internal Power MOSFETs
Power Good Indicator
Programmable Soft-Start Time
Forced PWM or Auto PFM/PWM Mode
Selectable
With constant-on-time (COT) control, the MP2321
provides very fast transient response, easy loop
design, and very tight output regulation.
Programmable Switching Frequency
Thermal Shutdown
Short-Circuit Protection: Hiccup Mode
Available in
Package
Full protection features include short-circuit
protection (SCP), over-current protection (OCP),
under-voltage protection (UVP), and thermal
shutdown.
a
QFN-14 (2mmx3mm)
The MP2321 requires a minimal number of readily
available, standard, external components and is
available in a space-saving QFN-14 (2mmx3mm)
package.
APPLICATIONS
Tablet PCs
Solid State Drives
Gaming
Battery-Operated Applications
All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For
MPS green status, please visit the MPS website under Quality Assurance.
“MPS” and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.
ꢀ
TYPICAL APPLICATION
100
90
80
70
60
50
40
30
20
10
0
0.001 0.01
0.1
1
10
MP2321 Rev. 1.0
10/26/2016
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1
MP2321 – 19V, 2A, LOW IQ, STEP-DOWN CONVERTER
ORDERING INFORMATION
Part Number*
Package
Top Marking
MP2321GD
QFN-14 (2mmx3mm)
See Below
* For Tape & Reel, add suffix –Z (e.g. MP2321GD–Z)
TOP MARKING
AQD: Product code of MP2321GD
Y: Year code
LLL: Lot number
PACKAGE REFERENCE
TOP VIEW
QFN-14 (2mmx3mm)
MP2321 Rev. 1.0
10/26/2016
www.MonolithicPower.com
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2
MP2321 – 19V, 2A, LOW IQ, STEP-DOWN CONVERTER
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE
Thermal Resistance (6)
θJA
θJC
QFN-14 (2mmx3mm)............. 70....... 15... °C/W
ABSOLUTE MAXIMUM RATINGSꢀ(1)ꢀ
VIN............................................................. +21V
VSW.................................... -0.3V (-5V < 10ns) to
VIN + 0.3V (23V < 10ns)
NOTES:
1) Exceeding these ratings may damage the device
2) For details on EN’s ABS max rating, please refer to the
Enable Control section on page 15.
3) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-to-
ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation produces an excessive die temperature, causing
the regulator to go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
V
BST ...................................................... VSW + 6V
(2)
All other pins..............................-0.3V to +6V
(3)
Continuous power dissipation
QFN-14 (2mmx3mm)................................. 1.8W
Junction temperature............................. +150°C
Lead temperature .................................. +260°C
Storage temperature................ -65°C to +150°C
4) The device is not guaranteed to function outside of its
operating conditions.
5) For details on DMAX, see the High Duty Cycle Condition
section on page 13.
Recommended Operating Conditionsꢀ(4)ꢀ
Supply voltage (VIN)...........................4V to 19V
6) Measured on JESD51-7, 4-layer PCB.
(5)
Output voltage (VOUT)........ 0.6V to VIN * DMAX
Operating junction temp. (TJ)... -40°C to +125°C
MP2321 Rev. 1.0
10/26/2016
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MP2321 – 19V, 2A, LOW IQ, STEP-DOWN CONVERTER
ELECTRICAL CHARACTERISTICS
VIN = 12V, TJ = -40°C to +125°C (7), typical value is tested at TJ = +25°C, unless otherwise
noted.
Parameters
Symbol Condition
Min
Typ
Max
Units
Supply current (shutdown)
IIN
VEN = 0V
0.1
1
μA
VEN = 5V, VFB = 0.7V,
TJ = 25°C
Supply current (quiescent)
IQ
40
3.7
200
55
μA
V
VIN under-voltage lockout
threshold rising
INUVVth
3.5
3.9
VIN under-voltage lockout
threshold hysteresis
INUVHYS
mV
HS switch on resistance
LS switch on resistance
Switch leakage
HSRDS(ON)
LSRDS(ON)
SWLKG
110
40
0
mꢀ
mꢀ
μA
VEN = 0V, VSW = 0V or 12V
1
6
6
Duty = 40%, TJ = -40°C to
+125°C
2.7
3
4
High-side MOSFET current limit
ILIMIT
A
Duty = 40%, TJ = 25°C
PWM mode, sink current
4
Low-Side MOSFET current limit
One-shot on timer (8)
ILIMIT
TON
1.5
A
R
REQ = 180k from
230
90
ns
FREQ/MODE to GND
Minimum on time (8)
Minimum off time
TON_min
ns
ns
TOFF min
150
600
600
10
TJ = -40°C to +125°C
TJ = 25°C
591
594
609
606
50
Feedback voltage
VFB
mV
Feedback current
Soft-start current
IFB
ISS
VFB = 700mV
nA
μA
V
4
8
11
EN input high voltage
EN input low voltage
1.6
0.4
V
VEN = 2V
VEN = 0V
2
EN input current
IEN
μA
0
Power good UV rising threshold
PGUVVth Hi
0.9
0.85
1.3
1.1
140
VFB
VFB
VFB
VFB
μs
Power good UV falling threshold PGUVVth Lo
Power good OV rising threshold PGOVVth Hi
Power good OV falling threshold PGOVVth Lo
1.2
1
1.4
1.2
Power good delay
PGTd
Power good sink current
capability
VPG
Sink 1mA
0.4
50
V
Power good leakage current
Thermal shutdown (8)
IPG LEAK
TSD
VPG = 3.3V
nA
°C
150
20
Thermal shutdown hysteresis (8)
TSD_HYS
°C
NOTES:
7) Not tested in production. Guaranteed by over-temperature correlation.
8) Not tested in production. Guaranteed by design and engineering sample characterization test.
MP2321 Rev. 1.0
10/26/2016
www.MonolithicPower.com
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4
MP2321 – 19V, 2A, LOW IQ, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 12V, VOUT = 1.2V, L = 2.2μH, TA = 25°C, unless otherwise noted.
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
0.001 0.01
0.1
1
10
0.001 0.01
0.1
1
10
0.001 0.01
0.1
1
10
50
45
40
35
30
25
20
0.3
0.2
0.4
0.3
0.2
0.1
0
0.1
0.0
-0.1
-0.2
-0.3
-0.4
-0.1
-0.2
-0.3
4
6
8
10 12 14 16 18 20
0
0.5
1.0
1.5
2.0
4
5 6 7 8 9101112131415161718 19
VIN UVLO vs. Temperature
15
14
13
12
11
10
9
3.9
3.8
3.7
3.6
3.5
3.4
3.3
1.2
1
0.8
0.6
0.4
0.2
0
8
7
6
5
4
5 6 7 8 9101112131415161718 19
-40 -15 10 35 60 85 110 135
-40 -10
20
50
80 110 140
MP2321 Rev. 1.0
10/26/2016
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5
MP2321 – 19V, 2A, LOW IQ, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 1.2V, L = 2.2μH, TA = 25°C, unless otherwise noted.
MP2321 Rev. 1.0
10/26/2016
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MP2321 – 19V, 2A, LOW IQ, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 1.2V, L = 2.2μH, TA = 25°C, unless otherwise noted.
V
/AC
V
/AC
OUT
20mV/div.
OUT
20mV/div.
V
/AC
OUT
50mV/div.
V
/AC
V
/AC
IN
IN
50mV/div.
50mV/div.
V
/AC
IN
100mV/div.
V
V
SW
SW
10V/div.
10V/div.
V
SW
10V/div.
I
L
2A/div.
I
I
L
L
2A/div.
2A/div.
V
V
V
OUT
OUT
OUT
500mV/div.
500mV/div.
500mV/div.
V
V
V
IN
IN
IN
10V/div.
10V/div.
10V/div.
PG
PG
PG
5V/div.
SW
20V/div.
5V/div.
SW
10V/div.
5V/div.
SW
10V/div.
V
V
V
I
I
L
L
5A/div.
5A/div.
V
V
V
OUT
OUT
OUT
500mV/div.
500mV/div.
500mV/div.
V
V
V
IN
IN
IN
10V/div.
10V/div.
10V/div.
PG
PG
PG
5V/div.
SW
10V/div.
5V/div.
SW
10V/div.
5V/div.
SW
10V/div.
V
V
V
I
I
L
L
5A/div.
5A/div.
I
L
5A/div.
MP2321 Rev. 1.0
10/26/2016
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MP2321 – 19V, 2A, LOW IQ, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 1.2V, L = 2.2μH, TA = 25°C, unless otherwise noted.
MP2321 Rev. 1.0
10/26/2016
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8
MP2321 – 19V, 2A, LOW IQ, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 1.2V, L = 2.2μH, TA = 25°C, unless otherwise noted.
MP2321 Rev. 1.0
10/26/2016
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MP2321 – 19V, 2A, LOW IQ, STEP-DOWN CONVERTER
PIN FUNCTIONS
Package
Pin #
Name
Description
System ground. GND is the reference ground for the regulated output voltage. GND
requires special consideration during PCB layout.
1, 12
2, 13
GND
SW
Switch output. Connect SW using wide PCB traces.
Supply voltage. The MP2321 operates from a 4V to 19V input rail. A capacitor (C1) is
needed to decouple the input rail. Use wide PCB traces and multiple vias to make the
connection.
3, 14
VIN
Frequency set during CCM operation. Connect a resistor to VIN to set the switching
frequency and operate the MP2321 in forced PWM mode. Connect a resistor to GND to
set the switching frequency and operate the MP2321 in auto PFM/PWM mode. Do not
float FREQ/MODE.
4
FREQ/MODE
Power good output. The output of PG is an open drain that goes high if the FB voltage
is within 90% to 110% of VREF. There is a 140µs delay when PG goes high.
5
6
PG
SS
Soft start. Connect a capacitor across SS and GND to set the soft-start time to avoid
start-up inrush current.
Feedback. FB sets the output voltage when connected to the tap of an external resistor
divider connected between the output and GND.
7
FB
Internal ramp adjust. Connect a capacitor from VOUT to CR to adjust the internal ramp
amplitude. This can be used to improve transient performance.
8
CR
Enable. Set EN = 1 to enable the MP2321. For automatic start-up, connect EN to VIN
with a pull-up resistor.
9
EN
Bootstrap. Connect a capacitor between SW and BST to form a floating supply across
the high-side switch driver.
10
11
BST
VCC
Internal bias supply. VCC is an internal 5V LDO output. Decouple VCC with a 1µF
ceramic capacitor placed as close to VCC as possible.
MP2321 Rev. 1.0
10/26/2016
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MP2321 – 19V, 2A, LOW IQ, STEP-DOWN CONVERTER
BLOCK DIAGRAM
ꢀ
Figure 1: Functional Block Diagram
MP2321 Rev. 1.0
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10/26/2016
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MP2321 – 19V, 2A, LOW IQ, STEP-DOWN CONVERTER
auto PWM or pulse-frequency modulation (PFM)
mode.
OPERATION
PWM Operation
The MP2321 is a fully-integrated, synchronous,
rectified, step-down, switch-mode converter.
The MP2321 uses constant-on-time (COT)
control to provide fast transient response and
easy loop compensation. Figure 2 shows the
simplified ramp compensation block.
At the beginning of each cycle, the high-side
MOSFET (HS-FET) turns on whenever the
ramp voltage (VRamp) is lower than the error
amplifier output voltage (VEAO), which indicates
insufficient output voltage. The input voltage
and the frequency-set resistor determine the
high-side MOSFET turn-on time (TON). After the
on period elapses, the HS-FET enters the off
state. By cycling HS-FET between the on and
off states, the converter regulates the output
voltage. The integrated low-side MOSFET (LS-
FET) turns on when the HS-FET is off to
minimize conduction loss. Shoot-through occurs
when the HS-FET and LS-FET are both turned
on at the same time, causing a dead short
between the input and GND. Shoot-through
reduces efficiency dramatically. The MP2321
prevents shoot-through by generating a dead-
time (DT) internally between HS-FET off and
LS-FET on, and LS-FET off and HS-FET on.
The MP2321 enters either heavy-load operation
or light-load operation depending on the output
current.
Figure 3: Mode Selection
Switching Frequency
The MP2321 uses constant-on-time (COT)
control. There is no dedicated oscillator in the
IC. The input voltage is forward fed into the on-
time one-shot timer through the frequency
resistor. The duty ratio is kept as VOUT/VIN, and
the switching frequency is fairly constant over
the input voltage range. The approximate
typical switching frequency can be determined
with Equation (1):
106
F (KHz)
(1)
SW
V (V)
IN
Ton (ns)
VOUT (V)
TON is slightly different in forced PWM mode
and auto PFM/PWM mode. Approximate the
typical TON value in forced PWM mode with
Equation (2):
14.5RFREQ(k)
(2)
TDELAY _PWM(ns)
TON_PWM
V (V) 0.4
IN
Approximate the typical TON value in auto
PFM/PWM mode with Equation (3):
13RFREQ(k)
TON_PFM
TDELAY _PFM(ns)(3)
V (V) 0.4
IN
Where TDELAY_PWM and TDELAY_PFM are the
comparator delay. The typical values are
approximately 15ns and 10ns, respectively.
Figure 2: Simplified Ramp Compensation Block
MODE Selection
Connect a resistor (R6) from FREQ/MODE to
VIN to set the switching frequency and operate
the MP2321 in forced pulse-width modulation
(PWM) mode (see Figure 3). Connect a resistor
(R7) from FREQ/MODE to GND to set the
switching frequency and operate the MP2321 in
When the MP2321 enters continuous
conduction mode (CCM), the duty ratio changes
slightly from light load to full load due to the
power loss. The frequency changes slightly
from light load to full load, even in CCM.
Because of the minimum on time and minimum
off time, the switching frequency is limited.
MP2321 Rev. 1.0
10/26/2016
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12
MP2321 – 19V, 2A, LOW IQ, STEP-DOWN CONVERTER
The maximum frequency can be calculated by
Equation (4) and Equation (5). Choose the
lower value of the two as the maximum
frequency:
106
FSW-max (KHz)
(4)
V (V)
IN
Ton-min (ns)
VOUT (V)
6
(V (V)-V (V))10
IN
OUT
FSW-max (KHz)
(5)
T
off-min(ns)V (V)
IN
Figure 5: Light-Load Operation
Where the Ton-min typical value is 90ns, and
the Toff-min typical value is 150ns. For example,
if VIN = 12V, and VOUT = 1.2V, then the
maximum frequency is about 1.1MHz. The
MP2321 is optimized to operate at a high
switching frequency with high efficiency. High
switching frequency allows small LC filter
components to be used to save system PCB
space.
Light-load operation is also called skip mode
because the HS-FET does not turn on as
frequently as it does in heavy-load condition.
The frequency at which the HS-FET turns on is
a function of the output current. As the output
current increases, the time period that the
current modulator regulates becomes shorter,
and the HS-FET turns on more frequently. The
switching frequency increases in turn. The output
current reaches critical levels when the current
modulator time is zero, and can be determined
with Equation (6):
Forced PWM Operation
When the MP2321 works in forced PWM mode,
the MP2321 enters CCM, where the HS-FET
and LS-FET repeat the on/off operation, even if
the inductor current goes to zero or a negative
value. The switching frequency (FSW) is fairly
constant. Figure 4 shows the timing diagram
during this operation.
(VIN VOUT) VOUT
2LFSW VIN
IOUT
(6)
The device resumes PWM mode once the
output current exceeds the critical level.
Afterward, the switching frequency remains
fairly constant over the output current range.
TON is constant
VIN
VSW
IL
High Duty Cycle Condition
Whenever VRAMP drops
below VEAO, the HS-FET
is turned ON
IOUT
The MP2316 extends the on time when the
output voltage loses regulation when the input
voltage is close to the output voltage. The
switching frequency drops correspondingly to
achieve a larger duty cycle to keep the output
regulated.
VRAMP
VEAO
HS-FET
Driver
LS-FET
Driver
Figure 4: Forced PWM Operation
Light-Load Operation
Floating Driver and Bootstrap Charging
An external bootstrap capacitor powers the
floating power MOSFET driver. This floating
driver has its own UVLO protection. This
UVLO’s rising threshold is 2.2V with a
hysteresis of 150mV. The bootstrap capacitor
voltage is regulated internally by VIN through
D1, M1, Cb, L1, and C2A (see Figure 6). If VIN
- VSW exceeds 5V, U1 regulates M1 to maintain
a 5V BST voltage across Cb.
When the MP2321 works in auto PFM/PWM
mode and during light-load operation, the
MP2321 automatically reduces the switching
frequency to maintain high efficiency, and the
inductor current drops almost to zero. When the
inductor current reaches zero, the LS-FET
driver goes into tri-state (high-Z). Therefore, the
output capacitors discharge slowly to GND
through LS-FET, R1, and R2. This operation
greatly improves device efficiency when the
output current is low (see Figure 5).
MP2321 Rev. 1.0
10/26/2016
www.MonolithicPower.com
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13
MP2321 – 19V, 2A, LOW IQ, STEP-DOWN CONVERTER
Table 1 below lists recommended Cr values for
different output voltages. The recommended Cr
value in Table 1 is based on a 500kHz
switching frequency, selected output inductor,
and 22µF output capacitors.
Table 1: Cr Selection for Common Output
Voltages
Cr (pF)
VOUT (V) L (μH)
VIN = 12V
82
VIN = 5V
82
Figure 6: Bootstrap Charging Circuit
1.0
1.2
1.5
1.8
2.5
3.3
5
2.2
2.2
3.3
3.3
3.3
4.7
4.7
100
120
120
150
150
100
100
82
56
Ramp with Small ESR Output Capacitor
When the output capacitors are ceramic, the
ESR ripple is not high enough to stabilize the
system, so external ramp compensation is
needed.
56
56
56 (9)
NOTE:
9) When VOUT = 5V, VIN should be higher than 6V.
The Cr value may vary with a different input
voltage, output voltage, output inductor, output
capacitor, and frequency set. If the design spec
is not the same as shown in Table 1, the Cr
value must be adjusted accordingly. Refer to
Equation (9) as a design guide.
Figure 7: Simplified External Ramp Circuit in
PWM Mode with Small ESR Capacitor
In skip mode, the stability is determined mainly
by the VEAO ripple. A VRamp value chosen in
PWM operation is reasonable for skip mode.
Figure 7 shows simplified external ramp
compensation for PWM mode. Chose the
external ramp (Cr) to meet the condition in
Equation (7):
Soft Start (SS)
The MP2321 employs a soft start (SS)
mechanism to ensure smooth output ramping
during power up. When EN goes high, an
internal current source (8μA) charges up the SS
capacitor. The SS capacitor voltage takes over
the REF voltage to the PWM comparator. The
output voltage smoothly ramps up with the SS
1
1
RFB
5
(7)
2F Cr
sw
Where RFB is set to 90kꢀ internally. Then
calculate IRamp with Equation (8):
(8)
IRramp = ICr + IRFB ICr
voltage. Once the SS voltage rises above VREF
,
it continues to ramp up until the REF voltage
takes over. At this point, the soft start finishes,
and the MP2321 enters steady state operation.
The SS capacitor value can be determined with
Equation (10):
Vramp on the VCR can be estimated with Equation
(9):
V Vout
in
V
T
(9)
ramp
on
Rramp Cr
Where RRamp is set to 900kꢀ internally.
T (ms)Iss(uA)
ss
(10)
Css(nF)
VREF(V)
As shown in Equation (9), if there is instability in
PWM mode, Cr can be reduced. If Cr cannot be
reduced further due to limitation from Equation
(7), then add an external resistor between SW
and CR to reduce the equivalent RRamp. Set
VRamp to about 20mV - 40mV for stable PWM
operation.
If the output capacitance is large, do not set the
SS time to be too short. Otherwise, the current
limit can be easily reached during SS. A
minimum value of 4.7nF is recommended if the
output capacitance is larger than 330μF.
MP2321 Rev. 1.0
10/26/2016
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14
MP2321 – 19V, 2A, LOW IQ, STEP-DOWN CONVERTER
Enable (EN) Control
Pre-Bias Start-Up
The MP2321 is designed for monotonic start-up
into pre-biased loads. If the output is pre-biased
to a certain voltage during start-up, the BST
voltage is refreshed and charged, and the
voltage on the soft-start capacitor is charged as
well. If the BST voltage exceeds its rising
threshold voltage, and the soft-start capacitor
voltage exceeds the sensed output voltage at
FB, the MP2321 begins working.
EN is a digital control pin that turns the
regulator on and off. Drive EN high to turn on
the regulator; drive EN low to turn off the
regulator. An internal 1Mꢀ resistor from EN to
GND allows EN to be floated to shut down the
chip.
EN is clamped internally using a 6.5V series
Zener diode. Connect the EN input through a
pull-up resistor to the voltage on VIN. The pull-
up resistance must be large enough to limit the
EN current below 100µA. For example, with
12V connected to VIN, RPULLUP ≥ (12V - 6.5V) ÷
100µA = 55kꢀ.
Power Good (PG)
PG is an open drain output. PG requires a pull-
up resistor (e.g.: 100kꢀ). PG is pulled to GND
before SS is ready. After the FB voltage
reaches 90% of VREF, PG is pulled high after a
140μs delay. When the FB voltage drops below
85% of VREF, PG is pulled low. If the FB voltage
rises above 130% of VREF, PG is pulled low.
Connecting EN to a voltage source directly
without a pull-up resistor requires limiting the
amplitude of the voltage below 6V to prevent
damage to the Zener diode.
After the FB voltage falls back to 110% of VREF
,
Under-Voltage Lockout (UVLO) Protection
PG is pulled high after a 140μs delay.
The MP2321 has under-voltage lockout
protection (UVLO). When the input voltage is
higher than the UVLO rising threshold voltage,
the MP2321 powers up. The MP2321 shuts off
when the input voltage is lower than the UVLO
falling threshold voltage. This is a non-latch
protection.
Over-Current Protection (OCP) and Short-
Circuit Protection (SCP)
The MP2321 has a cycle-by-cycle over-current
limit control. During HS-FET on, the inductor
current is monitored. When the sensed inductor
current reaches the peak current limit, the HS
limit comparator is triggered. The MP2321
enters over-current protection (OCP) mode
immediately, turns the HS-FET off, and turns
the LS-FET on. Meanwhile, the output voltage
drops until VFB is below the under-voltage (UV)
threshold, typically 50% below the reference.
Once UV is triggered, the MP2321 enters
hiccup mode to restart the part periodically.
Thermal Shutdown
The MP2321 employs thermal shutdown by
monitoring the junction temperature of the IC
internally. If the junction temperature exceeds
the threshold value (typically 150°C), the
converter shuts off. This is a non-latch
protection. There is a hysteresis of about 20°C.
Once the junction temperature drops below
130°C, the MP2321 starts up.
During OCP, the device attempts to recover
from the over-current fault with hiccup mode. In
hiccup mode, the chip disables the output
power stage, discharges the soft-start capacitor,
and attempts to soft start again automatically. If
the over-current condition still remains after the
soft start ends, the device repeats this
operation cycle until the over-current condition
is removed and the output rises back to the
regulation level. OCP is a non-latch protection.
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15
MP2321 – 19V, 2A, LOW IQ, STEP-DOWN CONVERTER
Vo106
SW (kHz) V
APPLICATION INFORMATION
Setting the Output Voltage
TDelay _PWM(ns) V 0.4
ꢀ(12)ꢀ
IN
F
IN
R6(k)
14.5
The external resistor divider is used to set the
output voltage. First, choose a value for R2. R2
should be chosen reasonably, since a small R2
leads to considerable quiescent current loss,
but a large R2 makes the FB noise sensitive.
Then R1 can be determined with Equation (11):
Where TDelay_PWM is about 15ns.
VOUT VREF
R1
R2
VREF
(11)
Where VREF is 0.6V, typically. The feedback
circuit is shown in Figure 8.
Figure 9: R6 vs. Forced PWM Mode Switching
Frequency
Set the auto PFM/PWM mode switching
frequency by connecting a resistor (R7) from
FREQ/MODE pin to ground and leaving R6 not
stuffed (NS) (see Figure 10). Determine R7 with
Equation (13):
Figure 8: Feedback Network
Vo106
FSW (kHz) V
TDelay _PFM(ns) V 0.4
Table 2 lists recommended resistor values for
common output voltages.
IN
IN
(13)
R7(k)
13
Table 2: Resistor Selection for Common Output
Voltages (10)
Where TDelay_PFM is about 10ns.
VOUT (V)
1.0
R1 (kΩ)
27
R2 (kΩ)
40.2
1.2
1.5
1.8
2.5
40.2
60.4
80.6
127
40.2
40.2
40.2
40.2
3.3
182
40.2
5
294
40.2
NOTE:
10) The feedback resistors in Table 2 are optimized for 500kHz of
switching frequency. The detailed schematics are shown in
the typical application circuit section.
Setting the Frequency
Figure 10: R7 vs. Auto PFM/PWM Mode
Switching Frequency
Set forced PWM mode switching frequency by
connecting a resistor (R6) from VIN to
FREQ/MODE and leaving R7 not stuffed (NS)
(see Figure 9). Refer to the MODE Selection
section on page 12 for more detail.
Equation (12) and Equation (13) show the
typical switching frequency calculation formulas.
The actually frequency changes slightly at
different load currents and different input
voltages.
ꢀDetermine
R6
with
Equation
(12):
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MP2321 – 19V, 2A, LOW IQ, STEP-DOWN CONVERTER
Selecting the Inductor
For simplification, choose an input capacitor
An inductor is necessary to supply constant
current to the output load while being driven by
the switched input voltage. An inductor with a
larger value results in less ripple current and
lower output ripple voltage. However, a larger
inductor also has a larger physical footprint,
higher series resistance, and lower saturation
current. A good rule for determining the
inductance value is to design the peak-to-peak
ripple current in the inductor to be 30% to 40%
of the maximum output current and the peak
inductor current to be below the maximum
switch current limit. The inductance value can
be calculated with Equation (14):
with an RMS current rating greater than half of
the maximum load current.
The input capacitance value determines the
input voltage ripple of the converter. If there is
an input voltage ripple requirement in the
system, choose an input capacitor that meets
the specification.
The input voltage ripple can be estimated with
Equation (18):
IOUT
SW CIN
VOUT
VOUT
(18)
V
(1
)
IN
F
V
V
IN
IN
The worst-case condition occurs at VIN = 2VOUT
shown in Equation (19):
,
VOUT
SW IL
VOUT
(14)
L
(1
)
F
V
IN
IOUT
4 FSW CIN
1
(19)
V
IN
Where ∆IL is the peak-to-peak inductor ripple
current.
Selecting the Output Capacitor
The inductor should not saturate under the
maximum inductor peak current. The peak
inductor current can be calculated with
Equation (15):
The output capacitor is required to maintain the
DC output voltage. Ceramic or POSCAP
capacitors are recommended. The output
voltage ripple can be estimated with Equation
(20):
VOUT
VOUT
(15)
ILP IOUT
(1
)
2FSW L
V
IN
VOUT
V
1
(1 OUT )(RESR
(20)
)
VOUT
Selecting the Input Capacitor
The input current to the step-down converter is
discontinuous and therefore requires
FSW L
V
8FSW COUT
IN
In the case of ceramic capacitors, the
impedance at the switching frequency is
dominated by the capacitance. The output
voltage ripple is caused mainly by the
capacitance. For simplification, the output
voltage ripple can be estimated with Equation
(21):
a
capacitor to supply AC current to the step-down
converter while maintaining the DC input
voltage. Ceramic capacitors are recommended
for the best performance and should be placed
as close to VIN as possible. Capacitors with
X5R and X7R ceramic dielectrics are
recommended because they are fairly stable
with temperature fluctuations.
VOUT
VOUT
(21)
VOUT
(1
)
8F 2 LCOUT
V
SW
IN
The output voltage ripple caused by the ESR is
very small. Therefore, an external ramp is
needed to stabilize the system. The external
ramp can be generated through the capacitor
Cr.
The capacitors must also have a ripple current
rating greater than the maximum input ripple
current of the converter. The input ripple current
can be estimated with Equation (16):
VOUT
VOUT
(16)
ICIN IOUT
(1
)
In the case of POSCAP capacitors, the ESR
dominates the impedance at the switching
frequency. For simplification, the output ripple
can be approximated with Equation (22):
V
V
IN
IN
The worst-case condition occurs at VIN = 2VOUT
shown in Equation (17):
,
IOUT
VOUT
V
(1 OUT )RESR
(22)
(17)
ICIN
VOUT
2
FSW L
V
IN
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17
MP2321 – 19V, 2A, LOW IQ, STEP-DOWN CONVERTER
A larger output capacitor can also achieve a
PCB Layout Guidelines
better load transient response, but the
maximum output capacitor limitation should
also be considered in the design application. If
the output capacitor value is too high, the
output voltage cannot reach the design value
during the soft-start time and fails to regulate.
Efficient layout of the switching power supplies
is critical for stable operation. A poor layout
design can result in poor line or load regulation
and stability issues. For best results, refer to
Figure 12 and follow the guidelines below.
1. Place the high current paths (GND, IN, and
SW) very close to the device with short,
direct, and wide traces.
The maximum output capacitor value (Co_max
)
can be limited approximately with Equation (23):
(23)
CO _MAX (ILIM_ AVG IOUT ) Tss / VOUT
2. Place the input capacitor as close to IN and
GND as possible.
Where ILIM_AVG is the average start-up current
during the soft-start period, and Tss is the soft-
start time.
3. Place the mode/frequency circuit close to
the part.
External Bootstrap Diode
4. Place the external feedback resistors next
to FB.
The BST voltage may become insufficient in
particular conditions. In this case, an external
bootstrap diode can be added to enhance the
efficiency of the regulator and help prevent BST
voltage insufficiency in light-load PFM operation.
BST voltage insufficiency is more likely to occur
at either of the following conditions:
5. Keep the switching node (SW) short and
away from the feedback network.
For better performances, it is recommended to
use four-layer boards. Figure 12 shows the top
and bottom layers (Inner 1 and Inner 2 are both
GND).
VIN is low
VOUT
VIN
Duty cycle is large: D =
> 65%
GND
R3
In these cases, if the BST voltage is insufficient,
the output ripple voltage may become
extremely large at light-load condition or show
poor efficiency at heavy-load condition. Add an
external BST diode from VCC to BST (see
Figure 11).
Rb
R1
R2
Cb
C4
C3
R5
sw
L
R6
R7
C1
C1A
C1B
C2A
C2B
VOUT
GND
VIN
Figure 11: Optional External Bootstrap Diode
The recommended external BST diode is
IN4148.
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MP2321 – 19V, 2A, LOW IQ, STEP-DOWN CONVERTER
Figure 12: Sample Board Layout
Design Example
Table 3 shows a design example when ceramic
capacitors are applied.
Table 3: Design Example
VIN
VOUT
IOUT
12V
1.2V
2A
The detailed application schematic is shown in
Figure 13 through Figure 19. The typical
performance and waveforms are shown in the
Typical Characteristics section. For more
devices applications, please refer to the related
evaluation board datasheet.
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MP2321 – 19V, 2A, LOW IQ, STEP-DOWN CONVERTER
TYPICAL APPLICATION CIRCUITS
Figure 13: VIN = 12V, VOUT = 1.0V, IOUT = 2A, FS = 500kHz
NOTE: Use R6 = 130kꢀ to set forced PWM. Use R7 = 147kꢀ to set auto PFM/PWM. The recommended R6 and R7 values are based on
Equation (12) and Equation (13) and optimized according to test results.
Figure 14: VIN = 12V, VOUT = 1.2V, IOUT = 2A, FS = 500kHz
NOTE: Use R6 = 158kꢀ to set forced PWM. Use R7 = 180kꢀ to set auto PFM/PWM. The recommended R6 and R7 values are based on
Equation (12) and Equation (13) and optimized according to test results.
MP2321 Rev. 1.0
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MP2321 – 19V, 2A, LOW IQ, STEP-DOWN CONVERTER
TYPICAL APPLICATION CIRCUITS (continued)
Figure 15: VIN = 12V, VOUT = 1.5V, IOUT = 2A, FS = 500kHz
NOTE: Use R6 = 196kꢀ to set forced PWM. Use R7 = 220kꢀ to set auto PFM/PWM. The recommended R6 and R7 values are based on
Equation (12) and Equation (13) and optimized according to test results.
Figure 16: VIN = 12V, VOUT = 1.8V, IOUT = 2A, FS = 500kHz
NOTE: Use R6 = 243kꢀ to set forced PWM. Use R7 = 255kꢀ to set auto PFM/PWM. The recommended R6 and R7 values are based on
Equation (12) and Equation (13) and optimized according to test results.
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MP2321 – 19V, 2A, LOW IQ, STEP-DOWN CONVERTER
TYPICAL APPLICATION CIRCUITS (continued)
Figure 17: VIN = 12V, VOUT = 2.5V, IOUT = 2A, FS = 500kHz
NOTE: Use R6 = 348kꢀ to set forced PWM. Use R7 = 360kꢀ to set auto PFM/PWM. The recommended R6 and R7 values are based on
Equation (12) and Equation (13) and optimized according to test results.
Figure 18: VIN = 12V, VOUT = 3.3V, IOUT = 2A, FS = 500kHz
NOTE: Use R6 = 453kꢀ to set forced PWM. Use R7 = 499kꢀ to set auto PFM/PWM. The recommended R6 and R7 values are based on
Equation (12) and (13) and optimized according to test results.
MP2321 Rev. 1.0
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MP2321 – 19V, 2A, LOW IQ, STEP-DOWN CONVERTER
TYPICAL APPLICATION CIRCUITS (continued)
Figure 19 : VIN = 12V, VOUT = 5V, IOUT = 2A, FS = 500kHz
NOTE: Use R6 = 715kꢀ to set forced PWM. Use R7 = 787kꢀ to set auto PFM/PWM. The recommended R6 and R7 values are based on
Equation (12) and Equation (13) and optimized according to test results.
MP2321 Rev. 1.0
10/26/2016
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MP2321 – 19V, 2A, LOW IQ, STEP-DOWN CONVERTER
QFN-14 (2mmx3mm)
PACKAGE INFORMATION
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) EXPOSED PADDLE SIZE DOES NOT
INCLUDE MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10
MILLIMETERS MAX.
4) JEDEC REFERENCE IS MO-220.
5) DRAWING IS NOT TO SCALE.
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP2321 Rev. 1.0
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24
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