MP2324GJ [MPS]
High Efficiency 2A, 24V, 500kHz Synchronous Step-Down Converter;
| 型号： | MP2324GJ |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | High Efficiency 2A, 24V, 500kHz Synchronous Step-Down Converter |
| 文件： | 总17页 (文件大小：1032K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MP2324
High Efficiency 2A, 24V, 500kHz
Synchronous Step-Down Converter
DESCRIPTION
FEATURES
The MP2324 is a high frequency synchronous
rectified step-down switch mode converter with
built in internal power MOSFETs. It offers a
very compact solution to achieve 2A continuous
output current over a wide input supply range
with excellent load and line regulation. The
MP2324 has synchronous mode operation for
higher efficiency over output current load range.
Wide 4.5V to 24V Operating Input Range
120mΩ/50mΩ Low Rds(on) Internal Power
MOSFETs
Low Quiescent Current
High Efficiency Synchronous Mode
Operation
Fixed 500kHz Switching Frequency
Frequency Sync from 200kHz to 2MHz
External Clock
Power Save Mode at light load
Internal Soft Start
Power Good Indicator
OCP Protection and Hiccup
Thermal Shutdown
Current mode operation provides fast transient
response and eases loop stabilization.
Full protection features include OCP and
thermal shut down.
The MP2324 requires a minimum number of
readily available standard external components
and is available in a space saving 8-pin
TSOT23 package.
Output Adjustable from 0.8V
Available in an 8-pin TSOT-23 package
APPLICATIONS
Notebook Systems and I/O Power
Digital Set Top Boxes
Flat Panel Television and Monitors
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Products, Quality Assurance page.
“MPS” and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
MP2324 Rev. 1.0
12/4/2013
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MP2324 – 24V, 2A SYNC STEP-DOWN CONVERTER
ORDERING INFORMATION
Part Number*
Package
Top Marking
MP2324GJ
TSOT23-8
AHV
* For Tape & Reel, add suffix –Z (e.g. MP2324GJ–Z);
PACKAGE REFERENCE
TSOT23-8
ABSOLUTE MAXIMUM RATINGS (1)
Thermal Resistance (4)
TSOT23-8…………………...…….100…..55..°C/W
θJA θJC
VIN............................................... –0.3V to +28V
VSW .......–0.3V (-5V<10ns) to +28V (30V <10ns)
VBST ...................................................... VSW+6V
All Other Pins................................. -0.3V to +6V
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-to-
ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation will cause excessive die temperature, and the
regulator will go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
(2)
Continuous Power Dissipation (TA=+25°C) ...
................................................................1.25W
Junction Temperature..............................150°C
Lead Temperature ...................................260°C
Storage Temperature.................-65°C to 150°C
Recommended Operating Conditions (3)
Supply Voltage VIN .............................4.5 to 24V
Output Voltage VOUT................. 0.8V to VIN*DMAX
Operating Junction Temp (TJ)..-40°C to +125°C
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
MP2324 Rev. 1.0
12/4/2013
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MP2324 – 24V, 2A SYNC STEP-DOWN CONVERTER
ELECTRICAL CHARACTERISTICS
VIN = 12V, TA = 25°C, unless otherwise noted.
Parameter
Symbol Condition
Min
Typ
5.5
180
120
50
Max
Units
μA
Supply Current (Shutdown)
Supply Current (Quiescent)
HS Switch On Resistance
LS Switch On Resistance
Switch Leakage
IIN
Iq
VEN = 0V
VEN = 2V, VFB = 1V
130
240
μA
HSRDS-ON VBST-SW=5V
LSRDS-ON VCC=5V
mΩ
mΩ
μA
SWLKG VEN = 0V, VSW =12V
1
Current Limit (5)
ILIMIT
fSW
Duty Cycle=40%
VFB=750mV
3
4
A
Oscillator Frequency
Fold-back Frequency
Maximum Duty Cycle
Minimum On Time (5)
Sync Frequency Range
Feedback Voltage
420
500
0.5
95
620
kHz
fSW
%
fFB
VFB=200mV
DMAX
TON_MIN
fSYNC
VFB
VFB=750mV
90
60
ns
0.2
2
MHz
mV
nA
TA=25ºC
783
791
10
799
50
Feedback Current
IFB
VFB=820mV
EN Rising Threshold
EN Hysteresis
VEN_RISING
VEN_HYS
1.2
80
1.4
150
1.6
220
V
mV
VEN=2V
VEN=0
1.5
2
2.5
μA
EN Input Current
IEN
0
50
14
nA
μs
EN Turn Off Delay
ENTd-off
6
10
0.9
Power Good Rising Threshold
PGVTH-Hi
VFB
Power Good Falling Threshold PGVTH-LO
0.85
40
VFB
Power Good Delay
PGTd
VPG
μs
Power Good Sink Current
Capability
Sink 1mA
0.4
1
V
μA
V
Power Good Leakage Current
IPG-LEAK
INUVVth
VIN Under Voltage Lockout
Threshold-Rising
3.7
3.9
4.1
VIN Under Voltage Lockout
Threshold-Hysteresis
INUVHYS
VCC
550
650
750
mV
VCC Regulator
4.65
0
4.9
1
5.15
3
V
%
VCC Load Regulation
ICC=5mA
Soft-Start Period
TSS
0.8
1.5
150
20
2.2
ms
ºC
ºC
Thermal Shutdown(5)
Thermal Hysteresis(5)
Notes:
5) Guaranteed by design
MP2324 Rev. 1.0
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MP2324 – 24V, 2A SYNC STEP-DOWN CONVERTER
TYPICAL CHARACTERISTICS
VIN = 12V, VOUT = 3.3V, L = 6.5μH, TA = 25°C, unless otherwise noted.
MP2324 Rev. 1.0
12/4/2013
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MP2324 – 24V, 2A SYNC STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 12V, VOUT = 3.3V, L = 6.5μH, TA = 25°C, unless otherwise noted.
MP2324 Rev. 1.0
12/4/2013
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MP2324 – 24V, 2A SYNC STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, L = 6.5µH, TA = 25°C, unless otherwise noted.
MP2324 Rev. 1.0
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MP2324 – 24V, 2A SYNC STEP-DOWN CONVERTER
PIN FUNCTIONS
Package
Pin #
Name Description
Power Good Output. The output of this pin is an open drain. It’s pulled up to Vcc by
external resistor when the output voltage exceeds 90% of the normal voltage. There is a
1
PG
IN
40μs delay between FB≥90% to the PG pin goes high.
Supply Voltage. The IN pin supplies power for internal MOSFET and regulator. The
MP2324 operates from a +4.5V to +24V input rail. Requires a low-ESR, and low
inductance capacitor (C1) to decouple the input rail. Place the input capacitor very close to
this pin and connect it with wide PCB traces and multiple vias.
2
Switch Output. Connect to the inductor and bootstrap capacitor. This pin is driven up to
VIN by the high-side switch during the PWM duty cycle ON time. The inductor current
drives the SW pin negative during the OFF time. The ON resistance of the low-side switch
and the internal body diode fixes the negative voltage. Connect using wide PCB traces and
multiple vias.
3
4
SW
System Ground. This pin is the reference ground of the regulated output voltage.
For this reason care must be taken in PCB layout. Suggested to be connected to GND with
copper and vias.
GND
Bootstrap. A capacitor and a 20Ω resistor connected between SW and BST pins are
required to form a floating supply across the high-side switch driver.
5
6
7
BST
EN/SYNC
VCC
EN=1 to enable the MP2324. External clock can be applied to EN pin for changing
switching frequency. For automatic start-up, connect EN pin to VIN with a 100kΩ resistor.
Bias Supply. Decouple with 0.1μF-0.22μF cap. And the capacitance should be no more
than 0.22μF
Feedback. An external resistor divider from the output to GND, tapped to the FB pin, sets
the output voltage. To prevent current limit run away during a short circuit fault condition
the frequency fold-back comparator lowers the oscillator frequency when the FB voltage is
below 400mV.
8
FB
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MP2324 – 24V, 2A SYNC STEP-DOWN CONVERTER
FUNCTION BLOCK DIAGRAM
Figure 1: Functional Block Diagram
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MP2324 – 24V, 2A SYNC STEP-DOWN CONVERTER
OPERATION
Under the light load condition, the value of
VCOMP is low. When VCOMP is less than VAAM and
VFB is less than VREF, VCOMP ramps up until it
exceeds VAAM. During this time, the internal
clock is blocked, thus the MP2324 skips some
pulses for PFM (Pulse Frequency Modulation)
mode and achieves the light load power save.
The MP2324 is a high frequency synchronous
rectified step-down switch mode converter with
built in internal power MOSFETs. It offers a
very compact solution to achieve 2A continuous
output current over a wide input supply range
with excellent load and line regulation.
The MP2324 operates in a fixed frequency,
peak current control mode to regulate the
output voltage. A PWM cycle is initiated by the
internal clock. The integrated high-side power
MOSFET is turned on and remains on until its
current reaches the value set by the COMP
voltage. When the power switch is off, it
remains off until the next clock cycle starts. If, in
95% of one PWM period, the current in the
power MOSFET does not reach the COMP set
current value, the power MOSFET will be
forced to turn off.
4
33k
Figure 2: Simplified AAM Control Logic
For VIN=12V, VOUT=3.3V, L=4.9μH, the inductor
peak current set internally is about 500mA at
light load. The AAM voltage internally is varied
with duty cycle for keeping the inductor peak
current constant.
Internal Regulator
Most of the internal circuitries are powered from
the 5V internal regulator. This regulator takes
the VIN input and operates in the full VIN range.
When VIN is greater than 5.0V, the output of
the regulator is in full regulation. When VIN is
lower than 5.0V, the output decreases, a 0.1uF
ceramic capacitor for decoupling purpose is
required.
Error Amplifier
The error amplifier compares the FB pin voltage
with the internal 0.8V reference (REF) and
outputs a COMP voltage, which is used to
control the power MOSFET current. The
optimized internal compensation network
minimizes the external component counts and
simplifies the control loop design.
Figure 3: AAM Selection for Common Output
Voltages (VIN=4.5V-24V)
Enable/SYNC Control
Power Save Mode for Light Load Condition
EN is a digital control pin that turns the
regulator on and off. Drive EN high to turn on
the regulator, drive it low to turn it off. There is
an internal 1MEG resistor from EN to GND thus
EN can be floated to shut down the chip. Also
EN pin voltage was clamped to around 6.5V by
an internal zener-diode. Please use large
enough pull up resistor connecting between VIN
and EN to limit the EN input current which
The
MP2324
has
AAM
(Advanced
Asynchronous Modulation) power-save mode
for light load. Under the heavy load condition,
the VCOMP is higher than VAAM. When the clock
goes high, the high-side power MOSFET turns
on and remains on until VILsense reaches the
value set by the COMP voltage. The internal
clock resets every time when VCOMP is higher
than VAAM
.
MP2324 Rev. 1.0
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MP2324 – 24V, 2A SYNC STEP-DOWN CONVERTER
should be less than 100uA. Generally, around
100k resistor should be large enough for all the
applications.
periodically restart the part. This protection
mode is especially useful when the output is
dead-short to ground. The average short circuit
current is greatly reduced to alleviate the
thermal issue and to protect the regulator. The
MP2324 exits the hiccup mode once the over
current condition is removed.
The chip can be synchronized to external clock
range from 200kHz up to 2MHz through this pin
2ms right after output voltage is set, with the
internal clock rising edge synchronized to the
external clock rising edge. EN synchronize logic
high voltage should higher than 2V. EN
synchronize logic low voltage should lower than
400mV. EN logic high pulse width must less
than 1.6µs. Otherwise the internal clock may
come and turn on high side MOSFET again. EN
logic low pulse width must less than 6µs,
otherwise MP2324 may EN shutdown.
Thermal Shutdown
Thermal shutdown is implemented to prevent
the chip from operating at exceedingly high
temperatures. When the silicon die temperature
is higher than 150°C, it shuts down the whole
chip. When the temperature is lower than its
lower threshold, typically 130°C, the chip is
enabled again.
Power Good Indicator
Floating Driver and Bootstrap Charging
The floating power MOSFET driver is powered
by an external bootstrap capacitor. This floating
driver has its own UVLO protection. This
UVLO’s rising threshold is 2.2V with a
hysteresis of 150mV. The bootstrap capacitor
voltage is regulated internally by VIN through
D1, R5, C5, L1 and C2 (Figure 4). If (VIN-VSW)
is more than 5V, U1 will regulate M1 to maintain
a 5V BST voltage across C5.
The MP2324 has an open drain pin for power
good indicator. When FB pin is higher than 90%
of regulation voltage, PG pin is pulled up to
VCC by the external resistor. If FB pin voltage
drop down to 85% of the regulation voltage, PG
pin is pulled down to ground by an internal
MOS FET.
Under-Voltage Lockout (UVLO)
Under-voltage lockout (UVLO) is implemented
to protect the chip from operating at insufficient
supply voltage. The MP2324 UVLO comparator
monitors the output voltage of the internal
regulator, VCC. The UVLO rising threshold is
about 3.9V while its falling threshold is
consistent 3.25V.
R5
5
Internal Soft-Start
The soft start is implemented to prevent the
converter output voltage from overshooting
during start up. When the chip starts, the
internal circuitry generates a soft-start voltage
(SS) ramping up from 0V. The soft-start period
lasts until the voltage on the soft-start capacitor
exceeds the reference voltage of 0.8V. At this
point the reference voltage takes over. The soft-
start time is internally set to be around 1.5ms.
Figure 4: Internal Bootstrap Charging Circuit
Startup and Shutdown
If both VIN and EN are higher than their
appropriate thresholds, the chip starts. The
reference block starts first, generating stable
reference voltage and currents, and then the
internal regulator is enabled. The regulator
provides stable supply for the remaining
circuitries.
Over-Current-Protection and Hiccup
The MP2324 has cycle-by-cycle over current
limit when the inductor current peak value
exceeds the set current limit threshold.
Meanwhile, output voltage starts to drop until
FB is below the Under-Voltage (UV) threshold,
typically 50% below the reference. Once a UV
is triggered, the MP2324 enters hiccup mode to
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MP2324 – 24V, 2A SYNC STEP-DOWN CONVERTER
Three events can shut down the chip: EN low,
VIN low and thermal shutdown. In the shutdown
procedure, the signaling path is first blocked to
avoid any fault triggering. The COMP voltage
and the internal supply rail are then pulled
down. The floating driver is not subject to this
shutdown command.
MP2324 Rev. 1.0
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MP2324 – 24V, 2A SYNC STEP-DOWN CONVERTER
APPLICATION INFORMATION
COMPONENT SELECTION
Setting the Output Voltage
Choose inductor current to be approximately
30% of the maximum load current. The
maximum inductor peak current is:
The external resistor divider is used to set the
output voltage (see Typical Application on page
1). The feedback resistor R1 also sets the
feedback loop bandwidth with the internal
IL
2
IL(MAX) ILOAD
Under light load conditions below 100mA, larger
inductance is recommended for improved
efficiency.
compensation
capacitor
(see
Typical
Application on page 1). R2 is then given by:
R1
Selecting the Input Capacitor
R2
V
OUT
1
The input current to the step-down converter is
discontinuous, therefore a capacitor is required
to supply the AC current to the step-down
converter while maintaining the DC input
voltage. Use low ESR capacitors for the best
performance. Ceramic capacitors with X5R or
X7R dielectrics are highly recommended
because of their low ESR and small
temperature coefficients. For most applications,
a 22µF capacitor is sufficient.
0.8V
The T-type network is highly recommended, as
Figure 5 shows.
Figure 5: T-type Network
Since the input capacitor (C1) absorbs the input
switching current it requires an adequate ripple
current rating. The RMS current in the input
capacitor can be estimated by:
Table 1 lists the recommended T-type resistors
value for common output voltages.
Table 1—Resistor Selection for Common
Output Voltages
VOUT
VOUT
IC1 ILOAD
1
VOUT(V) R1(kΩ) R2(kΩ) Rt (kΩ) L (µH) Cf (µF)
V
V
IN
IN
1
20.5
20.5
40.2
40.2
40.2
40.2
76.8
39.2
31.6
18.7
12.7
7.5
100
100
56
2.2
2.2
4.7
4.7
6.5
6.5
15
15
15
15
15
15
The worse case condition occurs at VIN =
2VOUT, where:
1.2
1.8
2.5
3.3
5
ILOAD
56
IC1
2
33
For simplification, choose the input capacitor
whose RMS current rating greater than half of
the maximum load current.
33
Selecting the Inductor
A 1µH to 22µH inductor with a DC current rating
of at least 25% percent higher than the
maximum load current is recommended for
most applications. For highest efficiency, the
inductor DC resistance should be less than
15mΩ. For most designs, the inductance value
can be derived from the following equation.
The input capacitor can be electrolytic, tantalum
or ceramic. When using electrolytic or tantalum
capacitors, a small, high quality ceramic
capacitor, i.e. 0.1μF, should be placed as close
to the IC as possible. When using ceramic
capacitors, make sure that they have enough
capacitance to provide sufficient charge to
prevent excessive voltage ripple at input. The
input voltage ripple caused by capacitance can
be estimated by:
VOUT (V VOUT
)
IN
L1
V IL fOSC
IN
Where ΔIL is the inductor ripple current.
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MP2324 – 24V, 2A SYNC STEP-DOWN CONVERTER
ILOAD
VOUT
VOUT
V
1
IN
RBST
fS C1
VIN
V
IN
Selecting the Output Capacitor
MP2324
The output capacitor (C2) is required to
maintain the DC output voltage. Ceramic,
tantalum, or low ESR electrolytic capacitors are
recommended. Low ESR capacitors are
preferred to keep the output voltage ripple low.
The output voltage ripple can be estimated by:
Figure 6: Add Optional External
Bootstrap Diode to Enhance Efficiency
VOUT
VOUT
V
1
The recommended external BST diode is
IN4148, and the BST cap is 0.1μF─1μF.
VOUT
1
R
ESR
fS L1
8 fS C2
IN
PC Board Layout (6)
PCB layout is very important to achieve stable
operation. Please follow these guidelines and
take Figure 7 as reference.
Where L1 is the inductor value and RESR is the
equivalent series resistance (ESR) value of the
output capacitor.
In the case of ceramic capacitors, the
impedance at the switching frequency is
dominated by the capacitance. The output
voltage ripple is mainly caused by the
capacitance. For simplification, the output
voltage ripple can be estimated by:
1) Keep the connection of input ground and
GND pin as short and wide as possible.
2) Keep the connection of input capacitor and
IN pin as short and wide as possible.
3) Ensure all feedback connections are short
and direct. Place the feedback resistors and
compensation components as close to the chip
as possible.
VOUT
8 fS2 L1 C2
VOUT
ΔVOUT
1
V
IN
In the case of tantalum or electrolytic capacitors,
the ESR dominates the impedance at the
switching frequency. For simplification, the
output ripple can be approximated to:
4) Route SW away from sensitive analog areas
such as FB.
Notes:
6) The recommended layout is based on the Figure 8 Typical
Application circuit on the next page.
VOUT
VOUT
ΔVOUT
1
RESR
fS L1
VIN
The characteristics of the output capacitor also
affect the stability of the regulation system. The
MP2324 can be optimized for a wide range of
capacitance and ESR values.
External Bootstrap Diode
An external bootstrap diode may enhance the
efficiency of the regulator, the applicable
conditions of external BST diode are:
VOUT is 5V or 3.3V;
VOUT
Duty cycle is high: D=
>65%
VIN
In these cases, an external BST diode is
recommended from the VCC pin to BST pin, as
shown in Figure 6.
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MP2324 – 24V, 2A SYNC STEP-DOWN CONVERTER
Design Example
GND
Below is a design example following the
application guidelines for the specifications:
C4
SW
Table 2: Design Example
C5
VIN
VOUT
IO
19V
5V
2A
R5
The detailed application schematics are shown
in Figures through 13. The typical
performance and circuit waveforms have been
shown in the Typical Performance
R4
L1
C1
8
C1A
Characteristics section. For more device
applications, please refer to the related
Evaluation Board Datasheets.
Vin
C2
Vout
C2A
GND
VOUT
GND
VCC
EN/SYNC
BST
SW
GND
Figure 7: Sample Board Layout
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MP2324 – 24V, 2A SYNC STEP-DOWN CONVERTER
TYPICAL APPLICATION CIRCUITS
U1
R3
20
IN
BST
C1A
22uF
C1
0.1uF
C4
L1
0.1uF
6.5uH
VCC
5V/2A
C5
0.1uF
SW
R5
100k
C2
C2A
22uF 22uF
MP2324
PG
EN
C3
15pF
R4
100k
R6
33k
FB
GND
R1
40.2k
R2
7.5k
Figure 8: Vo=5V, Io=2A
U1
R3
20
IN
BST
C1A
22uF
C1
0.1uF
C4
0.1uF
L1
6.5uH
VCC
3.3V/2A
C5
0.1uF
SW
R5
100k
C2
C2A
22uF 22uF
MP2324
PG
EN
C3
15pF
R4
100k
R6
33k
FB
GND
R1
40.2k
R2
12.7k
Figure 9: Vo=3.3V, Io=2A
U1
R3
20
IN
BST
C1A
22uF
C1
0.1uF
C4
0.1uF
L1
4.7uH
VCC
2.5V/2A
C5
0.1uF
MP2324 SW
R5
100k
C2
C2A
22uF 22uF
PG
EN
C3
15pF
R4
100k
R6
56k
FB
GND
R1
40.2k
R2
18.7k
Figure 10: Vo=2.5V, Io=2A
MP2324 Rev. 1.0
12/4/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
15
MP2324 – 24V, 2A SYNC STEP-DOWN CONVERTER
U1
R3
20
IN
BST
C1A
22uF
C1
0.1uF
C4
L1
0.1uF
4.7uH
VCC
1.8V/2A
C5
0.1uF
MP2324 SW
R5
100k
C2
C2A
22uF 22uF
PG
EN
C3
15pF
R4
100k
R6
56k
FB
GND
R1
40.2k
R2
31.6k
Figure 11: Vo=1.8V, Io=2A
U1
R3
20
IN
BST
C1A
22uF
C1
0.1uF
C4
0.1uF
L1
2.2uH
VCC
1.2V/2A
C5
0.1uF
MP2324 SW
R5
100k
C2
C2A
22uF 22uF
PG
EN
C3
15pF
R4
100k
R6
100k
FB
GND
R1
20.5k
R2
39.2k
Figure 12: Vo=1.2V, Io=2A
U1
R3
20
IN
BST
C1A
22uF
C1
0.1uF
C4
0.1uF
L1
2.2uH
VCC
1V/2A
C5
0.1uF
SW
R5
100k
C2
C2A
22uF 22uF
MP2324
PG
EN
C3
15pF
R4
100k
R6
100k
FB
GND
R1
20.5k
R2
76.8k
Figure 13: Vo=1V, Io=2A
MP2324 Rev. 1.0
12/4/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
16
MP2324 – 24V, 2A SYNC STEP-DOWN CONVERTER
PACKAGE INFORMATION
TSOT23-8
See note 7
EXAMPLE
TOP MARK
IAAAA
PIN 1 ID
RECOMMENDED LAND PATTERN
TOP VIEW
SEATING PLANE
SEE DETAIL ''A''
FRONT VIEW
SIDE VIEW
NOTE:
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD
FLASH, PROTRUSION OR GATE BURR.
3) PACKAGE WIDTH DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
4) LEAD COPLANARITY (BOTTOM OF LEADS
AFTER FORMING) SHALL BE 0.10 MILLIMETERS
MAX.
DETAIL ''A''
5) JEDEC REFERENCE IS MO-193, VARIATION BA.
6) DRAWING IS NOT TO SCALE.
7) PIN 1 IS LOWER LEFT PIN WHEN READING TOP
MARK FROM LEFT TO RIGHT, (SEE EXAMPLE TOP
MARK)
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP2324 Rev. 1.0
12/4/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
17
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