MP38894DN-LF [MPS]
Switching Regulator, Current-mode, 6.5A, 600kHz Switching Freq-Max, PDSO8, ROHS COMPLIANT, MS-012BA, SOIC-8;
| 型号： | MP38894DN-LF |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | Switching Regulator, Current-mode, 6.5A, 600kHz Switching Freq-Max, PDSO8, ROHS COMPLIANT, MS-012BA, SOIC-8 开关 光电二极管 输出元件 |
| 文件： | 总10页 (文件大小：397K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MP38894
4.5A, 42V, 420kHz Step-Down Converter
with Synchronizable Gate Driver
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MP38894 is a monolithic step-down switch
mode converter with a built in internal power
MOSFET. It achieves 4.5A continuous output
current over a wide input supply range with
excellent load and line regulation.
•
•
•
•
•
Wide 4.5V to 42V Operating Input Range
4.5A Continuous Output Current
±1.5% Vfb Accuracy
100mΩ Internal Power MOSFET Switch
Synchronizable Gate Driver Delivers up to
95% Efficiency
Current mode operation provides fast transient
response and eases loop stabilization.
•
•
•
Fixed 420kHz Frequency
Synchronizable up to 1.5MHz
Cycle-by-Cycle Over Current Protection with
Hiccup retry
Fault condition protection includes cycle-by-cycle
current limiting and thermal shutdown.
The MP38894 requires a minimum number of
readily available standard external components
and is available in an 8-pin SOIC package with
exposed pad.
•
•
•
Thermal Shutdown
Output Adjustable from 0.8V to 15V
Stable with Low ESR Output Ceramic
Capacitors
•
Available in a Thermally Enhanced 8-Pin
SOIC Package
APPLICATIONS
•
•
•
•
Digital Set Top Boxes
Personal Video Recorders
Broadband Communications
Flat Panel Television and Monitors
“MPS” and “The Future of Analog IC Technology” are Registered Trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
8
3
7
2
V
IN
BST
IN
1
4
6
SW
BG
FB
VCC
M2
EN/SYNC
OFF ON
GND
5
MP38894 Rev.1.0
9/28/2009
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2009 MPS. All Rights Reserved.
1
MP38894 – 4.5A, 42V, 420KHZ STEP-DOWN WITH SYNCHRONIZABLE GATE DRIVER
PACKAGE REFERENCE
ABSOLUTE MAXIMUM RATINGS (1)
Supply Voltage VIN....................................... 45V
VSW.........................–0.3V(-5V for <10ns) to 46V
VBST – VSW ...................................................... 6V
All Pins...........................................–0.3V to +6V
Junction Temperature...............................150°C
Lead Temperature....................................260°C
Storage Temperature ..............–65°C to +150°C
TOP VIEW
SW
BST
VCC
BG
1
2
3
4
8
7
6
5
IN
EN/SYNC
FB
Recommended Operating Conditions (2)
Supply Voltage VIN........................... 4.5V to 42V
Output Voltage VOUT ........................ 0.8V to 15V
Operating Temperature .............–40°C to +85°C
GND
EXPOSED PAD
ON BACKSIDE
Thermal Resistance (3)
θJA
θJC
SOIC8E ..................................50...... 10... °C/W
Part Number*
MP38894DN
Package
Temperature
Notes:
SOIC8E
–40°C to +85°C
1) Exceeding these ratings may damage the device.
2) The device is not guaranteed to function outside of its
operating conditions.
For Tape & Reel, add suffix –Z (eg. MP38894DN–Z)
For RoHS Compliant Packaging, add suffix –LF
(eg. MP38894DN–LF–Z)
*
3) Measured on JESD51-7, 4-layer PCB.
ELECTRICAL CHARACTERISTICS
VIN = 12V, TA = +25°C, unless otherwise noted.
Parameters
Symbol Condition
Min
Typ
Max
Units
V
nA
mΩ
μA
A
kHz
kHz
%
ns
V
mV
V
V
Feedback Voltage
VFB
IFB
0.796 0.808 0.820
4.5V ≤ VIN ≤ 42V
VFB = 0.8V
Feedback Current
10
100
Switch On Resistance (4)
Switch Leakage
RDS(ON)
VEN = 0V, VSW = 0V
Duty=40%
VFB = 0.6V
0.1
6.5
420
115
90
100
4.10
880
10
Current Limit (4)
IO-MAX
fSW
Oscillator Frequency
Fold-back Frequency
Maximum Duty Cycle
Minimum On Time (4)
Under Voltage Lockout Threshold Rising
Under Voltage Lockout Threshold Hysteresis
EN Input Low Voltage
EN Input High Voltage
240
25
85
600
205
VFB = 0V
VFB = 0.6V
tON
3.90
2
4.30
0.4
VEN = 2V
2
0.1
300
1.5
5.0
1
0.9
150
5.0
1
EN Input Current
μA
VEN = 0V
Sync Frequency Range (Low)
Sync Frequency Range (High)
Enable Turnoff Delay
Supply Current (Shutdown)
Supply Current (Quiescent)
Thermal Shutdown
BG Driver Bias Supply Voltage
Gate Driver Sink Impedance (4)
Gate Driver Source Impedance (4)
Gate Drive Current Sense Trip Threshold
FSYNCL
FSYNCH
TOFF
kHz
MHz
μs
μA
mA
°C
V
Ω
Ω
mV
VEN = 0V
VEN = 2V, VFB = 1V
10
1.1
VCC
RSINK
RSOURCE
VSW
ICC = 5mA
4.5
4
20
Note:
4) Guaranteed by design.
MP38894 Rev.1.0
9/28/2009
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2009 MPS. All Rights Reserved.
2
MP38894 – 4.5A, 42V, 420KHZ STEP-DOWN WITH SYNCHRONIZABLE GATE DRIVER
PIN FUNCTIONS
Pin #
Name
Description
1
SW
Switch Output.
Bootstrap. This capacitor is needed to drive the power switch’s gate above the supply
voltage. It is connected between SW and BS pins to form a floating supply across the power
switch driver.
2
BST
3
4
VCC
BG
BG Driver Bias Supply. Decouple with a 1µF ceramic capacitor.
Gate Driver Output. Connect this pin to the gate of the synchronous MOSFET.
Ground. This pin is the voltage reference for the regulated output voltage. For this reason
care must be taken in its layout. This node should be placed outside of the M2 to C1 ground
path to prevent switching current spikes from inducing voltage noise into the part.
5
GND
Feedback. An external resistor divider from the output to GND, tapped to the FB pin sets
the output voltage. To prevent current limit run away during a short circuit fault condition the
frequency foldback comparator lowers the oscillator frequency when the FB voltage is
below 250mV.
6
FB
7
8
EN/SYNC On/Off Control and External Frequency Synchronization Input.
Supply Voltage. The MP38894 operates from a +4.5V to +42V unregulated input. C1 is
IN
needed to prevent large voltage spikes from appearing at the input.
MP38894 Rev.1.0
9/28/2009
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2009 MPS. All Rights Reserved.
3
MP38894 – 4.5A, 42V, 420KHZ STEP-DOWN WITH SYNCHRONIZABLE GATE DRIVER
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 12V, VOUT = 3.3V, L = 4.3µH, TA = +25ºC, unless otherwise noted.
0
Case Temperature Rise
vs. Output Current
Operating Range
Load Regulation
10
1
MP38894 Rev.1.0
9/28/2009
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2009 MPS. All Rights Reserved.
4
MP38894 – 4.5A, 42V, 420KHZ STEP-DOWN WITH SYNCHRONIZABLE GATE DRIVER
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 12V, VOUT = 3.3V, L =4.3µH, TA = +25ºC, unless otherwise noted. (continued)
MP38894 Rev.0.9
9/28/2009
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2009 MPS. All Rights Reserved.
5
MP38894 – 4.5A, 42V, 420KHZ STEP-DOWN WITH SYNCHRONIZABLE GATE DRIVER
OPERATION
IN
CURRENT SENSE
D
AMPLIFIER
+
- -
REGULATOR
BST
REGULATOR
EN/SYNC
OSCILLATOR
420KHz
Q
Q
DRIVER
S
+
--
R
R
SW
V
CC
CURRENT
LIMIT
V
CC
COMPARATOR
REFERENCE
VCC
+
DRIVER
BG
+
--
--
FB
PWM
COMP
ERROR
AMPLIFIER
COMPARATOR
GND
Figure 1—Functional Block Diagram
fixed frequency,
Error Amplifier
The MP38894 is
a
synchronous, step-down switching regulator
with an integrated high-side power MOSFET
and a gate driver for a low-side external
MOSFET. It achieves 4.5A continuous output
current over a wide input supply range with
excellent load and line regulation. It provides a
single highly efficient solution with current mode
control for fast loop response and easy
compensation.
The error amplifier compares the FB pin voltage
with the internal 0.8V reference (REF) and
outputs a current proportional to the difference
between the two. This output current is then
used to charge or discharge the internal
compensation network to form the COMP
voltage, which is used to control the power
MOSFET current. The optimized internal
compensation network minimizes the external
component counts and simplifies the control
loop design.
The MP38894 operates in a fixed frequency,
peak current control mode to regulate the
output voltage. A PWM cycle is initiated by the
internal clock. The integrated high-side power
MOSFET is turned on and remains on until its
current reaches the value set by the COMP
voltage. When the power switch is off, it
remains off until the next clock cycle starts. If, in
90% of one PWM period, the current in the
power MOSFET does not reach the COMP set
current value, the power MOSFET will be
forced to turn off.
Internal Regulator
Most of the internal circuitries are powered from
the 5V internal regulator. This regulator takes
the VIN input and operates in the full VIN range.
When VIN is greater than 5.0V, the output of
the regulator is in full regulation. When VIN is
lower than 5.0V, the output decreases. Since
this internal regulator provides the bias current
for the bottom gate driver that requires
significant amount of current depending upon
the external MOSFET selection, a 1µF ceramic
capacitor for decoupling purpose is required.
MP38894 Rev.1.0
9/28/2009
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2009 MPS. All Rights Reserved.
6
MP38894 – 4.5A, 42V, 420KHZ STEP-DOWN WITH SYNCHRONIZABLE GATE DRIVER
Enable/Synch Control
Thermal Shutdown
The MP38894 has a dedicated Enable/Synch
control pin (EN/SYNC). By pulling it high or low,
the IC can be enabled and disabled by EN. Tie
EN to VIN for automatic start up. To disable the
part, EN must be pulled low for at least 5µs.
Thermal shutdown is implemented to prevent
the chip from operating at exceedingly high
temperatures. When the silicon die temperature
is higher than 150°C, it shuts down the whole
chip. When the temperature is lower than its
lower threshold, typically 140°C, the chip is
enabled again.
The MP38894 can be synchronized to external
clock range from 300KHz up to 1.5MHz through
the EN/SYNC pin. The internal clock rising
edge is synchronized to the external clock rising
edge.
Floating Driver and Bootstrap Charging
The floating power MOSFET driver is powered
by an external bootstrap capacitor. This floating
driver has its own UVLO protection. This
UVLO’s rising threshold is 2.2V with a
hysteresis of 150mV. The bootstrap capacitor
voltage is regulated internally by VIN through D1,
M3, C4, L1 and C2 (Figure 2). If (VIN-VSW) is
more than 5V, U2 will regulate M3 to maintain a
5V BST voltage across C4.
Under-Voltage Lockout (UVLO)
Under-voltage lockout (UVLO) is implemented
to protect the chip from operating at insufficient
supply
voltage.
The
MP38894
UVLO
comparator monitors the output voltage of the
internal regulator, VCC. The UVLO rising
threshold is about 4.1V while its falling
threshold is a consistent 3.2V.
D1
Internal Soft-Start
V
IN
The soft-start is implemented to prevent the
converter output voltage from overshooting
during startup. When the chip starts, the
internal circuitry generates a soft-start voltage
(SS) ramping up from 0V to 1.2V. When it is
lower than the internal reference (REF), SS
overrides REF so the error amplifier uses SS as
the reference. When SS is higher than REF,
REF regains control.
M3
+
--
BST
+
--
U2
5V
C4
V
OUT
SW
L1
C2
Over-Current-Protection (OCP)
Figure 2—Internal Bootstrap Charging
The MP38894 has cycle-by-cycle over current
limit when the inductor current peak value
exceeds the set current limit threshold.
Meanwhile, output voltage starts to drop until
FB is below the Under-Voltage (UV) threshold,
typically 30% below the reference. Once a
output UV is triggered, the MP38894 enters
hiccup mode, which is especially useful to
ensure system safety under fault condition. The
MP38894 exits the hiccup mode once the EN or
input power is re-cycled.
Circuit
Startup and Shutdown
If both VIN and EN are higher than their
appropriate thresholds, the chip starts. The
reference block starts first, generating stable
reference voltage and currents, and then the
internal regulator is enabled. The regulator
provides stable supply for the remaining
circuitries.
Three events can shut down the chip: EN low,
VIN low and thermal shutdown. In the shutdown
procedure, the signaling path is first blocked to
avoid any fault triggering. The COMP voltage
and the internal supply rail are then pulled down.
The floating driver is not subject to this
shutdown command.
MP38894 Rev.1.0
9/28/2009
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2009 MPS. All Rights Reserved.
7
MP38894 – 4.5A, 42V, 420KHZ STEP-DOWN WITH SYNCHRONIZABLE GATE DRIVER
APPLICATION INFORMATION
The schematic on the front page shows a typical
MP38894 application. The IC can provide up to
4.5A output current at a nominal output voltage
of 3.3V. For proper thermal performance, the
exposed pad of the device must be soldered
down to the printed circuit board.
Synchronous MOSFET
The external synchronous MOSFET is used to
freewheel the inductor current when the internal
high-side switch is off. It significantly reduces
the power loss compared against a Schottky
rectifier.
Setting the Output Voltage
Table 2 lists example synchronous MOSFETs
and manufacturers.
The external resistor divider is used to set the
output voltage (see the schematic on front
page). The feedback resistor R1 also sets the
feedback loop bandwidth with the internal
compensation capacitor (see Figure 1). Choose
R1 to be around 40.2kꢀ for optimal transient
response. R2 is then given by:
Table 2—Synchronous MOSFET Selection
Guide
Part No.
Si7370
Manufacture
Vishay
Si4470
Vishay
R1
R2 =
AM4417
Analog Power
VOUT
− 1
Selecting the Input Capacitor
0.8V
The input capacitor (C1) reduces the surge
current drawn from the input and the switching
noise from the device. The input capacitor
impedance at the switching frequency should
be less than the input source impedance to
prevent high frequency switching current from
passing to the input. Ceramic capacitors with
Table 1—Resistor Selection for Common
Output Voltages
VOUT (V)
1.8
R1 (kΩ)
40.2 (1%)
40.2 (1%)
40.2 (1%)
40.2 (1%)
R2 (kΩ)
32.4 (1%)
19.1 (1%)
13 (1%)
2.5
3.3
5
X5R
or
X7R
dielectrics
are
highly
7.68 (1%)
recommended because of their low ESR and
small temperature coefficients. For 4.5A output
applications, a 22µF capacitor is sufficient.
Selecting the Inductor
A 1µH to 10µH inductor with a DC current rating
of at least 25% higher than the maximum load
current is recommended for most applications.
For highest efficiency, the inductor DC
resistance should be less than 15mꢀ. For most
designs, the inductance value can be derived
from the following equation.
Selecting the Output Capacitor
The output capacitor (C2) keeps output voltage
small and ensures regulation loop stability. The
output capacitor impedance should be low at
the switching frequency. Ceramic capacitors
with X5R or X7R dielectrics are recommended.
VOUT × (VIN − VOUT
VIN × ΔIL × fOSC
)
L =
Where ΔIL is the inductor ripple current.
Choose inductor ripple current to be approximately
30% of the maximum load current, 4.5A. The
maximum inductor peak current is:
ΔIL
IL(MAX) = ILOAD
+
2
Under light load conditions below 100mA, larger
inductance is recommended for improving
efficiency.
MP38894 Rev.1.0
9/28/2009
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2009 MPS. All Rights Reserved.
8
MP38894 – 4.5A, 42V, 420KHZ STEP-DOWN WITH SYNCHRONIZABLE GATE DRIVER
PCB Layout Guide
PCB layout is very important to achieve stable
operation. Please follow these guidelines and
take Figure3 for references.
1) Keep the path of switching current short
and minimize the loop area formed by Input
cap, high-side and low-side MOSFETs.
2) Keep the connection of low-side MOSFET
between SW pin and input power ground
as short and wide as possible.
3) Ensure all feedback connections are short
and direct. Place the feedback resistors
and compensation components as close to
the chip as possible.
4) Route SW away from sensitive analog
areas such as FB.
5) Connect IN, SW, and especially GND
respectively to a large copper area to cool
the chip to improve thermal performance
and long-term reliability.
Bottom Layer
Figure 3—PCB Layout
External Bootstrap Diode
An external bootstrap diode may enhance the
efficiency of the regulator, the applicable
conditions of external BST diode are:
z
z
VOUT=5V or 3.3V; and
Duty cycle is high: D=
VOUT
VIN
>65%
In these cases, an external BST diode is
recommended from the output of the voltage
regulator to BST pin, as shown in Fig.4
External BST Diode
IN4148
BST
CBST
MP38894
5V or 3.3V
SW
L
COUT
Figure 4—Add Optional External Bootstrap
Diode to Enhance Efficiency
Top Layer
The recommended external BST diode is
IN4148, and the BST cap is 0.1~1µF.
MP38894 Rev.1.0
9/28/2009
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2009 MPS. All Rights Reserved.
9
MP38894 – 4.5A, 42V, 420KHZ STEP-DOWN WITH SYNCHRONIZABLE GATE DRIVER
PACKAGE INFORMATION
SOIC8E (EXPOSED PAD)
0.189(4.80)
0.197(5.00)
0.124(3.15)
0.136(3.45)
8
5
0.150(3.80)
0.157(4.00)
0.228(5.80)
0.244(6.20)
0.089(2.26)
0.101(2.56)
PIN 1 ID
1
4
TOP VIEW
BOTTOM VIEW
SEE DETAIL "A"
0.051(1.30)
0.067(1.70)
SEATING PLANE
0.000(0.00)
0.006(0.15)
0.0075(0.19)
0.0098(0.25)
0.013(0.33)
0.020(0.51)
SIDE VIEW
0.050(1.27)
BSC
FRONT VIEW
0.010(0.25)
0.020(0.50)
x 45o
GAUGE PLANE
0.010(0.25) BSC
0.050(1.27)
0.024(0.61)
0.063(1.60)
0.016(0.41)
0.050(1.27)
0o-8o
DETAIL "A"
0.103(2.62)
0.213(5.40)
NOTE:
1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN
BRACKET IS IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH
OR PROTRUSIONS.
0.138(3.51)
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.004" INCHES MAX.
5) DRAWING CONFORMS TO JEDEC MS-012, VARIATION BA.
6) DRAWING IS NOT TO SCALE.
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP38894 Rev. 1.0
9/28/2009
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2009 MPS. All Rights Reserved.
10
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