MP5403B [MPS]
Mini PMIC with Dual 4A/5A Peak Bucks, One 2A Load Switch, and Input Power Supervisory;
| 型号： | MP5403B |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | Mini PMIC with Dual 4A/5A Peak Bucks, One 2A Load Switch, and Input Power Supervisory 集成电源管理电路 |
| 文件： | 总23页 (文件大小：1641K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MP5403B
Mini PMIC with Dual 4A/5A Peak Bucks,
One 2A Load Switch, and
Input Power Supervisory
DESCRIPTION
FEATURES
The MP5403B is
a
monolithic power
Up to 6V Operating Input Range
Low IQ: 85µA for Two Switchers Total
Two Buck Converters
o Peak 5A with 55mΩ/20mΩ RDS(ON)
o Peak 4A with 65mΩ/22mΩ RDS(ON)
o 1.5MHz Switching Frequency
o 180° Interleaving Operation
o 100% Duty Cycle
o Load Switch Mode by Pulling FB Low
o Latch-Off Short-Circuit Protection (SCP)
o Internal Soft Start (SS) and Output
Discharge
o Optimized Light-Load Efficiency
One Load Switch with 20mΩ RDS(ON)
o 3A with 20mΩ RDS(ON)
o Soft Start (SS) and Output Discharge
o Over-Current Protection (OCP)
EN and Power Good (PG) for Power
Sequencing
Input Power Good (PG) Indicator with
Adjustable Threshold and Delay
Thermal Shutdown
management unit containing two high-efficiency,
step-down, switching converters and a load
switch. The two regulators supply peak currents
up to 5A and 4A separately, and the load switch
supplies up to 3A of load current with an
extremely low RDS(ON). With an input range of up
to 6V, the MP5403B is ideal for powering ASIC
and SOC for solid-state drives (SSD) and other
compact power systems.
The peak-current-mode control scheme with
pulse-skip mode operation provides the two
switchers with fast transient response, high light-
load efficiency, and a minimal number of
capacitors by using an interleaving PWM clock
between the two switchers. The 3A load switch
with a low 20mΩ on resistance provides flexible
system configuration.
A full set of enable control pins and power good
open-drain
indicators
allow
for
easy
implementation of the start-up and shutdown
sequences.
Available in a UTQFN-20 (2.5mmx3mm)
Package
Full protection features include over-current
protection (OCP) and thermal shutdown.
APPLICATIONS
The MP5403B requires a minimal number of
readily available, standard, external components
and is available in a small UTQFN-20
(2.5mmx3mm) package.
Solid-State Drives (SSD)
Portable Instruments
Battery-Powered Devices
All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive.
For MPS green status, please visit the MPS website under Quality
Assurance. “MPS” and “The Future of Analog IC Technology” are registered
trademarks of Monolithic Power Systems, Inc.
MP5403B Rev. 1.0
12/5/2017
www.MonolithicPower.com
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© 2017 MPS. All Rights Reserved.
1
MP5403B – DUAL BUCK AND ONE LOAD SWITCH PMIC
TYPICAL APPLICATION
VSUS
PFL
CDELAY
Output Voltage 1
L1
L2
SW1
FB1
Peak 5A
R6
R5
C1A
C1B
R1
R2
PFL_ADJ
Input Voltage
VIN1 MP5403B
Output Voltage 2
Peak 4A
C1
C2
SW2
FB2
R3
R4
VIN2
VIN3
EN1
EN2
EN3
Output Voltage 3
3A DC
VOUT3
PG1
PG2
PG3
C2A
GND, AGND
MP5403B Rev. 1.0
12/5/2017
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2
MP5403B – DUAL BUCK AND ONE LOAD SWITCH PMIC
ORDERING INFORMATION
Part Number*
Package
Top Marking
MP5403BGQBU
UTQFN-20 (2.5mmx3mm)
See Below
* For Tape & Reel, add suffix –Z (e.g. MP5403BGQBU–Z)
TOP MARKING
AWF: Product code of MP5403BGQBU
Y: Year code
WW: Week code
LLL: Lot number
PACKAGE REFERENCE
TOP VIEW
20
19
18
CDELAY
PFL_ADJ
VIN1
PG3
PG2
1
2
3
4
5
6
7
17
16
15 PG1
AGND
GND
SW1
VSUS
SW2
EN3
14
13
12
11
VIN2
FB1
8
9
10
UTQFN-20 (2.5mmx3mm)
MP5403B Rev. 1.0
12/5/2017
www.MonolithicPower.com
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MP5403B – DUAL BUCK AND ONE LOAD SWITCH PMIC
ABSOLUTE MAXIMUM RATINGS (1)
Supply voltage (VIN1/2/3)............................... 6.5V
VSW1/2.................................-0.3V (-5V for <10ns)
to 6.5V (10V for <10ns)
Thermal Resistance
θJA
θJC
UTQFN-20 (2.5mmx3mm)
(4)
EV5403-QB-02A ............... 35........ 7.... °C/W
(5)
JESD51-7 .......................... 60....... 13... °C/W
All other pins..................................-0.3V to 6.5V
Continuous power dissipation (TA = +25°C)
NOTES:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-to-
ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation produces an excessive die temperature, causing
the regulator to go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
(2)(4)
........................................................... 3.5W
Junction temperature ................................150°C
Lead temperature .....................................260°C
Storage temperature................ -65°C to +150°C
Recommended Operating Conditions (3)
Supply voltage (VIN1)..........................2.7V to 6V
Supply voltage (VIN2) (if VIN1 > UVLO).................
...........................................................2.0V to 6V
Supply voltage (VIN3) (if VIN1 > UVLO)
3) The device is not guaranteed to function outside of its operating
conditions.
4) Measured on EV5403-QB-02A, 4-layer PCB.
5) Measured on JESD51-7, 4-layer PCB.
...........................................................0.5V to 6V
Supply voltage (VIN3) (If VIN1 < UVLO)
...........................................................2.7V to 6V
Output voltage (VOUT1/2).................. 0.6V to VIN1/2
Output voltage (VOUT3)...................................VIN3
Operating junction temp. (TJ)... -40°C to +125°C
MP5403B Rev. 1.0
12/5/2017
www.MonolithicPower.com
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© 2017 MPS. All Rights Reserved.
4
MP5403B – DUAL BUCK AND ONE LOAD SWITCH PMIC
ELECTRICAL CHARACTERISTICS
VIN1/2 = 3.6V, VIN3 = 3.6V, TJ = -40°C to 125°C(7), typical value tested at TJ = 25°C unless otherwise
noted.
Parameters
Symbol
Condition
Min
Typ
Max
Units
For Buck Regulators (VIN1 provides control voltage if VIN3 is lower than 2.7V)
Input voltage range
VIN1
For VIN1
2.7
2.3
6
V
V
Under-voltage lockout threshold
rising
VIN1_UVLO_R For VIN1
2.5
2.65
Under-voltage lockout threshold
hysteresis
VIN1_UVLO_H For VIN1
250
mV
V
Input voltage range for rail 2
VIN2
VIN1 > VIN1_UVLO_R
2
6
VIN2 under-voltage lockout
threshold rising
VIN2_UVLO_R For VIN2
1.8
1.85
V
VIN2 under-voltage lockout
threshold hysteresis
VIN2_UVLO_H For VIN2
300
mV
μA
μA
Supply current (shutdown)
ISD
VEN1/2/3 = 0V, TJ = 25°C
1
VEN1/2 = 2V, VEN3 = 0V,
VFB1/2 =1V
Supply current (quiescent)
IQ1+Q2
85
55
20
65
22
110
High-side switch on resistance
for peak 5A switcher
RDSON1_H
RDSON1_L
RDSON2_H
RDSON2_L
mΩ
mΩ
mΩ
mΩ
Low-side switch on resistance
for peak 5A switcher
High-side switch on resistance
for peak 4A switcher
Low-side switch on resistance
for peak 4A switcher
VEN1/2 = 0V, VIN1/2 = 6V,
VSW1/2 = 0V and 6V,
TJ = 25°C
Switch leakage current
ILK_SW1/2
0
1
μA
High-side current limit for peak
5A switcher
ILIM1_H
ILIM2_H
6.2
5
8.5
7
A
A
High-side current limit for peak
4A switcher
Low-side zero crossing current
Oscillator frequency
Phase shift
Minimum on time (6)
Minimum off time (6)
Maximum duty cycle (6)
IZCD1/2
FSW1/2
PhS
For both channels
CCM
0.1
1.5
A
MHz
degree
ns
1.2
1.8
CCM
180
70
TMIN_ON
TMIN_OFF
DMAX
100
100
600
600
10
ns
%
TJ = 25°C
TJ = -40°C to 125°C (7)
594
591
606
609
50
mV
mV
nA
Feedback voltage
VFB1/2
Feedback currents
IFB1/2
FB1/2 = 0.65V
Internal soft-start time
TSS1/2
For both channels
0.35
ms
MP5403B Rev. 1.0
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12/5/2017
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MP5403B – DUAL BUCK AND ONE LOAD SWITCH PMIC
ELECTRICAL CHARACTERISTICS (continued)
VIN1/2 = 3.6V, VIN3 = 3.6V, TJ = -40°C to 125°C(7), typical value tested at TJ = 25°C unless otherwise
noted.
Parameters
Symbol
Issres1/2
Condition
Min
Typ
13
Max Units
Output discharge resistor
EN high logic
For both channels
Ω
EN1/2_H
1.05
1.3
150
1
1.5
V
EN low hysteresis
EN1/2_L_HYS
mV
VEN = 2V
EN1/2 input current
IEN1/2
μA
VEN = 0V
0
EN1 turn-on delay
EN2 turn-on delay
ENTD_1
ENTD_2
For channel 1
100
μs
μs
For channel 2, VIN1
VIN1_UVLO_R
>
100
+30
-10
FB with respect to the
regulation
Power good upper trip threshold
Power good lower trip threshold
PG1/2_H
PG1/2_L
%
%
FB with respect to the
regulation
Power good hysteresis
PGHY
5
%
μs
μs
Power good delay for rising
Power good delay for falling
PDTD_1/2 H
PDTD_1/2 L
20
60
Power good sink current
capability
VPG_LO_1/2
PGLK_1/2
Sink 1mA
0.4
V
Power good leakage current
VPGBUS = 1.8V
1
μA
Load Switch
VIN1 > VIN1_UVLO_R
VIN1 < VIN1_UVLO_R
0.6
2.7
6
6
V
V
Input voltage range
VIN3
Under voltage lockout threshold
rising
VIN3_UVLO_R For VIN3
VIN3_UVLO_H For VIN3
2.3
2.5
200
160
2.65
V
Under voltage lockout threshold
hysteresis
mV
μA
From VIN3, VEN1/2 = 0V,
VEN3 = 3.6V
Supply current (quiescent)
IQ3
250
1.5
On resistor
RDSON
EN3_H
20
1.3
150
70
70
1
mΩ
V
EN3 high logic threshold
EN3 low hysteresis
1.05
EN3_ L_HYS
mV
VIN1 > VIN1_UVLO_R
VIN1 < VIN1_UVLO_R
VEN3 = 2V
EN3 turn on delay
ENTD_3
µs
EN3 input current
IEN3
μA
VEN3 = 0V
0
VIN3 - VOUT3 is smaller
than the range
PG3 high logic threshold
PG3_H
150
200
mV
VIN3 - VOUT3 is larger than
the range
PG3 low logic threshold
PG3_L
PDTD_3
VPG_LO_3
PGLK_3
250
40
mV
μs
V
Power good delay for rising
Power good sink current
capability
Sink 1mA
0.4
Power good leakage current
VPGBUS = 1.8V
1
μA
MP5403B Rev. 1.0
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12/5/2017
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MP5403B – DUAL BUCK AND ONE LOAD SWITCH PMIC
ELECTRICAL CHARACTERISTICS (continued)
VIN1/2 = 3.6V, VIN3 = 3.6V, TJ = -40°C to 125°C(7), typical value tested at TJ = 25°C unless otherwise
noted.
Parameters
Symbol
ILIM3
Condition
Min
Typ
6.2
Max
Units
A
Current limit
Internal soft-start time
Output resistor
Tss3
0.35
13
ms
Ω
Issres
Power Failure Circuitry
VSUS voltage
VSUS
3.6
0
V
VSUS = 3.6V, VIN1 = VIN3
0V, TJ = 25°C
=
VSUS leakage current
PFL_ADJ reference
ISUS_LK
1
μA
TA = 25°C
TJ = -40°C to 125°C (7)
0.594
0.591
0.6
0.6
3
0.606
0.609
V
V
PFL_ADJ
PFL hysteresis
%
μs
μA
PFL high-to-low delay
CDELAY internal current source
TPFL_HL
IDELAY
1
3.1
Power good sink current
capability
VPFL_LO
Sink 1mA
0.4
V
Power good leakage current
Thermal shutdown (6)
Thermal hysteresis (6)
NOTES:
PFLLK
TSD
VPGBUS = 1.8V
1
μA
°C
°C
160
30
THYS
6) Guaranteed by engineering sample characterization, not tested in production.
7) Guaranteed by characterization test, not tested in production.
MP5403B Rev. 1.0
12/5/2017
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7
MP5403B – DUAL BUCK AND ONE LOAD SWITCH PMIC
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 5V, VOUT1 = 1.8V, VOUT2 = 1.2V, L1 = 0.47µH, L2 = 0.47µH, TA = +25°C, unless otherwise noted.
MP5403B Rev. 1.0
12/5/2017
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MP5403B – DUAL BUCK AND ONE LOAD SWITCH PMIC
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 5V, VOUT1 = 1.8V, VOUT2 = 1.2V, L1 = 0.47µH, L2 = 0.47µH, TA = +25°C, unless otherwise noted.
MP5403B Rev. 1.0
12/5/2017
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MP5403B – DUAL BUCK AND ONE LOAD SWITCH PMIC
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 5V, VOUT1 = 1.8V, VOUT2 = 1.2V, L1 = 0.47µH, L2 = 0.47µH, TA = +25°C, unless otherwise noted.
MP5403B Rev. 1.0
12/5/2017
www.MonolithicPower.com
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MP5403B – DUAL BUCK AND ONE LOAD SWITCH PMIC
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 5V, VOUT1 = 1.2V, VOUT2 = 1.2V, L1 = 0.47µH, L2 = 0.47µH, TA = +25°C, unless otherwise noted.
MP5403B Rev. 1.0
12/5/2017
www.MonolithicPower.com
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MP5403B – DUAL BUCK AND ONE LOAD SWITCH PMIC
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 5V, VOUT1 = 1.2V, VOUT2 = 1.2V, L1 = 0.47µH, L2 = 0.47µH, TA = +25°C, unless otherwise noted.
MP5403B Rev. 1.0
12/5/2017
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MP5403B – DUAL BUCK AND ONE LOAD SWITCH PMIC
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 5V, VOUT1 = 1.2V, VOUT2 = 1.2V, L1 = 0.47µH, L2 = 0.47µH, TA = +25°C, unless otherwise noted.
MP5403B Rev. 1.0
12/5/2017
www.MonolithicPower.com
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MP5403B – DUAL BUCK AND ONE LOAD SWITCH PMIC
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 5V, VOUT1 = 1.2V, VOUT2 = 1.2V, L1 = 0.47µH, L2 = 0.47µH, TA = +25°C, unless otherwise noted.
MP5403B Rev. 1.0
12/5/2017
www.MonolithicPower.com
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MP5403B – DUAL BUCK AND ONE LOAD SWITCH PMIC
PIN FUNCTIONS
Pin #
Name
Description
Programmable PFL low-to-high delay time. When CDELAY is floated, the delay time is
minimized.
1
CDELAY
Power failure threshold adjust. A resistor divider connected to the voltage rails is
used to program the power failure threshold. The resistor divider must be monitored.
2
3
PFL_ADJ
VIN1
Input supply voltage to the peak 5A switching regulators. Place a small decoupling
capacitor as close as possible to VIN1 and GND as possible.
4
5
AGND
GND
Analog ground.
Ground.
Input supply voltage to the peak 4A switching regulators. Place a small decoupling
capacitor as close to VIN2 and GND as possible.
6
VIN2
Feedback voltage sense for the peak 5A regulator. Connect the output voltage of
the peak 5A regulator through a resistor divider to FB1 to achieve voltage regulation.
Pull FB1 to ground to operate the peak 5A regulator in 100% duty cycle on mode.
7
FB1
Feedback voltage sense for the peak 4A regulator. Connect the output voltage of
the peak 4A regulator through a resistor divider to FB2 to achieve output voltage
regulation. Pull FB2 to ground to operate the peak 4A regulator in 100% duty cycle on
mode.
8
FB2
Enable on/off control for the peak 5A regulator. There is a 2MΩ resistor from EN1
to GND internally. Float or ground EN1 to turn off the peak 5A regulator.
9
EN1
EN2
EN3
SW2
VSUS
SW1
Enable on/off control for the peak 4A regulator. There is a 2MΩ resistor from EN2
to GND internally. Float or ground EN2 to turn off the peak 4A regulator.
10
11
12
13
14
Enable on/off control for the load switch. There is a 2MΩ resistor from EN3 to GND
internally. Float or ground EN3 to turn off the load switch.
Switch output for the peak 4A regulator. A thick, wide power routing trace is
recommended for SW2 to conduct current.
Sustain voltage. Place a small decoupling capacitor as close to VSUS and GND as
possible.
Switch output for the peak 5A regulator. A thick and wide power routing trace is
recommended for SW1 to conduct current.
Power good for the peak 5A regulator. PG1 is an open-drain output. When the output
voltage is between -10% to +30% of the regulation windows, PG1 is pulled high
externally. When there is no supply, PG1 is pulled low internally.
15
PG1
Power good for peak 4A regulator. PG2 is an open-drain output. When the output
voltage is between -10% to +30% of the regulation windows, PG2 is pulled high
externally. When there is no supply, PG2 is pulled low internally.
16
17
PG2
PG3
Power good for the load switch. PG3 is an open-drain output. When the output
voltage is below 200mV compared with the input voltage, PG3 is pulled high externally.
18
19
VIN3
Input supply voltage for the load switch.
Output voltage for the load switch.
OUT3
Power failure indicator. PFL is an open-drain output. When the PFL_ADJ voltage is
less than 0.6V, PFL is pulled low immediately.
20
PFL
MP5403B Rev. 1.0
12/5/2017
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MP5403B – DUAL BUCK AND ONE LOAD SWITCH PMIC
BLOCK DIAGRAM
Vsus
PFL
CDELAY
PFL_ADJ
Delay
Control
Vsus
Ctrl
+
_
0.6V
PG1
Ref1
FB1
+
_
ULVO
VIN1
SW1
Internal
Soft Start
HS
Ref1
+
PWM
+
_
Driver
FB1
EN1
LS
Output
Discharge
Mode Ctrl
Slope
Comp
+
_
1.5MHz
Osc
VIN2
SW2
Slope
Comp
EN2
Internal
Soft Start
HS
+
Ref2
PWM
+
_
Driver
FB2
PG2
LS
Output
Discharge
Mode Ctrl
+
_
Ref2
FB2
+
_
Output
Clamping
VIN3
EN3
OUT3
PG3
Charge
Pump
Output
Discharge
VIN1
+
_
Soft Start
Ctrl
GND,AGND
Figure 1: Functional Block Diagram
MP5403B Rev. 1.0
12/5/2017
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MP5403B – DUAL BUCK AND ONE LOAD SWITCH PMIC
Light-Load Operation
OPERATION
In light-load mode, the MP5403B uses a
The MP5403B has two step-down regulators and
one load switch integrated into an ultra-small
UTQFN-20 package. The two buck regulators
are able to run up to a peak 5A and peak 4A load
current, respectively. With a peak-current-mode
control scheme and an interleaving PWM clock,
the MP5403B minimizes the input voltage ripple
and achieves a fast dynamic load response. A
3A load switch with only 20mΩ of RDS(ON) can
achieve extremely small conduction loss and
provide tight regulation with a high load current.
The load switch can also clamp VOUT to 5.5V.
The MP5403B can be used in compact solid-
state drives (SSD), portable instruments, and
battery-powered devices.
proprietary control scheme to save power and
improve efficiency. The MP5403B turns off the
low-side switch when the inductor current begins
reversing.
Then
MP5403B
works
in
discontinuous
conduction
mode
(DCM)
operation. With light-load mode control, the
switching loss can be reduced greatly due to the
lower switching frequency.
A zero-current cross detection (ZCD) circuit is
used to detect if the inductor current begins
reversing. Considering the internal circuit
propagation time, the typical delay is 50ns. This
means that the inductor current continues falling
after ZCD is triggered in this delay. If the inductor
current falling slew rate is fast (VOUT is high or
close to VIN), the low-side MOSFET (LS-FET) is
turned off, and the inductor current may be
negative. This prevents the MP5403B from
entering DCM operation. If DCM operation is
required, the off time of the LS-FET in CCM
should be longer than 100ns. For example, if VIN
is 3.6V and VOUT is 3.4V, then the off time in CCM
is 37ns. It is difficult to enter DCM at light load.
Using a smaller inductor can improve this and
make it easier to enter DCM.
Peak-Current-Mode Control
The two buck regulators of the MP5403B
operate at an 180° phase shift to reduce the
input current ripple and the required input
capacitor. In continuous conduction mode
(CCM), two internal clocks control the switching
behavior. The high-side MOSFET (HS-FET)
turns on at the corresponding clock’s rising edge.
Two clocks are at an 180° phase shift. With the
high-side switch current increases and reaches
the internal compensation voltage, the high-side
switch is turned off, and the low-side switch is
turned on to conduct current.
Enable (EN)
When VIN1 is greater than the under-voltage
lockout (UVLO) threshold (typically 2.7V), the
regulators or the load switch can be enabled by
pulling its EN pins above the EN UVLO
threshold. Leave the EN pins floating or pull the
EN pins down to ground to disable the
corresponding channel. There is an internal 2MΩ
resistor from the EN pins to ground. There is a
delay of about 100µs for VIN1 and VIN2 enable
start-up. The VIN3 enable start-up delay is
shorter (around 70µs).
Soft Start (SS) and Output Discharge
Figure 2: Phase Shift
The MP5403B has a built-in soft start (SS) that
ramps up the output voltage at a controlled slew
rate to prevent overshooting at start-up for both
step-down regulators and the load switch. The
soft-start time is set to around 0.35ms. When the
regulators are disabled, the internal discharge
resistor discharges VOUT. The discharge resistor
is biased by VSUS (see Table 1).
The switching frequency is 1.5MHz, typically,
running in CCM. With a lower input voltage, the
switching frequency falls and works with a large
duty cycle and a fixed off-time mode.
MP5403B Rev. 1.0
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MP5403B – DUAL BUCK AND ONE LOAD SWITCH PMIC
Table 1: Output Discharge Conditions
than the 0.6V reference voltage, PFL is pulled
high with the delay, which is set by CDELAY
Choose CDELAY using Equation (1):
CDELAY(pF)×0.62
.
Output Discharge
VIN
EN
No
>UVLO
>UVLO
<UVLO
<UVLO
High
Low
High
Low
Yes
Yes
Yes
(1)
+3.5μs
TDELAY(μs) =
IDELAY(μA)
Power Good (PG) Indicators
Where TDELAY is the PFL delay time, and IDELAY is
the CDELAY internal current source (typically
3.1µA).
The MP5403B has three separate power good
(PG), open-drain, output indicators for the
regulators and load switch. For the two step-
down regulators, when FB is in the regulation
window (between 90% to 130% of the reference
voltage, 0.6V), PG1 and PG2 pins are pulled up
to the external bus voltage through certain
external resistors. The pull-up resistors are
recommend not to be too low to ensure that the
leakage current is small when the PG pins are
low and not too high if they are used to drive
downstream signals. Normally, pull-up resistors
between 10kΩ to 400kΩ are sufficient. The PG
rising delay is around 20µs. If the FB voltage
drops below 90% or rises above 130% of the
reference voltage, the PG pins are pulled down
to ground by an internal MOSFET. The MOSFET
has a maximum RDS(ON) of less than 400Ω. There
is also a 60µs delay for the PG falling threshold
trigger.
Current Limit
The MP5403B has a high-side 6.2A current limit
for the first regulator and a 5A current limit for the
second regulator. When the high-side switch
reaches the current-limit threshold, the
regulators shut down the high-side switch and
force the low-side switch on until the low-side
current drops to the low-side valley current
threshold (peak 5A and peak 4A for the two
regulators). After the low-side current reaches
the valley current threshold, the high-side switch
can turn on again. If the high load current
persists, the high-side turns on again, and the
current-limit mechanism repeats until the output
voltage drops to the short-circuit threshold. If the
high-load current does not persist, then the
regulator resumes normal conditions.
The power good pin for the load switch (PG3) is
pulled high when the input voltage of the load
switch (VIN3) is higher than its UVLO threshold,
the output voltage (VOUT3) is less than 200mV
compared with the input voltage of the load
switch, and there is around 40µs of rising delay
for the PG3 indicator. If any of these three
conditions are not met, PG3 is pulled low.
For the load switch, the current limit begins
working when the load switch current reaches
the current-limit threshold. The gate is pulled low
to regulate the load switch current to the current
limit. The output voltage drops until thermal
shutdown occurs.
Short Circuit and Recovery
When CH1 or CH2 is in buck mode, the
MP5403B enters short-circuit protection (SCP)
mode when the inductor current reaches the
current limit for 300µs continuously or the output
voltage drops below 50% of the regulation
voltage. In SCP mode, the MP5403B disables
the output power stage, discharges the soft-start
capacitor, and enters latch-off protection mode.
The MP5403B restarts by recycling the power.
The PG indicators are pulled low when VIN1 is
below UVLO. In this condition, the PG pins are
self-driven low (around 0.6V).
Power Failure Indicator (PFL)
The power failure indicator (PFL) senses the
external voltage rails. When the input voltage is
below the programmed threshold, the PFL open-
drain output is pulled low immediately to indicate
the monitored power failure. PFL_ADJ is used to
adjust the power failure threshold voltage. A
resistor divider is used to monitor the voltage rail.
When the PFL_ADJ voltage is lower than 0.6V,
PFL is pulled down to indicate the sense power
failure. When the PFL_ADJ voltage is higher
MP5403B Rev. 1.0
12/5/2017
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MP5403B – DUAL BUCK AND ONE LOAD SWITCH PMIC
Load Switch Mode of Buck 1/2
By pulling FB1 or FB2 to ground, the step-down
regulator 1 or 2 can enter load-switch mode
without having to install an inductor. The
MP5403B pulses a smaller current to the FB pins
before the system starts up. If a low impedance
is connected to the FB pins, the MP5403B enters
load-switch mode, where the high-side switch is
turned on gradually to achieve a soft start, and
SCP is equipped.
MP5403B Rev. 1.0
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MP5403B – DUAL BUCK AND ONE LOAD SWITCH PMIC
Selecting the Inductor
The inductor has a great impact on several key
performances for the step-down switcher, such as
APPLICATION INFORMATION
Output Voltage Setting
The output voltage of the two switchers can be
adjusted with the external resistor dividers (see
Figure 3). The typical reference voltage of both
FB1 and FB2 is 600mV. The maximum allowed
voltage for the outputs is close to the input
voltage minus the voltage drop when the high-
side switch is 100% turned on.
inductor current ripple, output voltage ripple,
efficiency, and load transient response.
Calculate the inductor current ripple with Equation (3):
VOUT(V VOUT
)
IN
IL
(3)
V LfSW
IN
Calculate the inductor peak current with Equation (4):
SW1
IL
2
(4)
ILpk ILoad
R1
FB1
R2
Choosing the inductance is a trade-off between the
output ripple, efficiency, and transient response. The
larger the inductance is, the smaller the output ripple,
but the slower the response. Choose an inductance
that makes the ripple current 30 - 40% of the max load
current.
SW2
R3
FB2
The inductor saturation current must be higher than
the inductor peak current.
R4
The inductor also impacts the solution efficiency in
terms of conduction loss and frequency- and coil-
related loss. Generally, the DC resistance provides
DC conduction loss information. For AC conduction
loss and coil-related loss, refer to the vendor’s
datasheet for more detailed information.
Figure 3: Feedback Resistor Dividers to Set the
Output Voltages
The divider current is recommended to be higher
than 500nA to avoid influence from the feedback
node leakage current (which is in the 10nA
level). Considering control loop optimization, the
pull-high resistor is recommended to be between
100 - 500kΩ. Then, the pull-down resistor can be
calculated with Equation (2):
Input Capacitor Selection
The input capacitor reduces the surge current
drawn from the input and the switching noise
from the device. Select an input capacitor with
switching frequency impedance that is less than
the input source impedance to prevent high-
frequency switching current from passing to the
input source. Use low ESR ceramic capacitors
with X5R or X7R dielectrics with small
temperature coefficients. For most applications,
a 22μF capacitor is sufficient.
R1(orR3)
R2(orR4)
(2)
VOUT
0.6V
1
Table 2 shows some typical output voltages and
their corresponding recommended resistor
divider values.
Table 2: Output Voltage vs. Resistor Values
VOUT
1.2V
1.5V
1.8V
2.5V
3.3V
R1
R2
300kΩ
300kΩ
300kΩ
300kΩ
300kΩ
300kΩ
200kΩ
150kΩ
95.3kΩ
66.5kΩ
NOTE: COUT is 22µF for each channel.
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12/5/2017
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MP5403B – DUAL BUCK AND ONE LOAD SWITCH PMIC
Output Capacitor Selection
The output capacitor limits the output voltage
ripple and ensures a stable regulation loop.
Select an output capacitor with low impedance at
the switching frequency. Use ceramic capacitors
with X5R or X7R dielectrics. Using an electrolytic
capacitor may result in additional output voltage
ripple, thermal issues, and require additional
care in selecting the feedback resistor (R1) due
to the large ESR. For most applications, a 22µF
capacitor is sufficient.
GND
VIN1
GND
C2
VIN2
C1A
C1B
R1
R3
R2
C4
C3
VIN3
PG3
PG2
PG1
EN1
EN2
EN3
R4
GND
VOUT3
PCB Layout Guidelines
C7
Efficient PCB layout of the switching power
supplies is critical for stable operation. If the
layout is not done carefully, for the high switching
frequency converter especially, the regulator
could show poor line or load regulation and
stability issues. For best results, refer to Figure 4
and follow the guideline below.
L2
L1
C6
GND
C5
VOUT1
VOUT2
Top Layer
1. Place the input capacitor as close to the IC
pins as possible for the high-speed step-
down regulator to provide clean control
voltage.
GND
VIN3
Vout2 Sense
Vout1 Sense
Bottom Layer
Figure 4: Recommended Layout
MP5403B Rev. 1.0
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MP5403B – DUAL BUCK AND ONE LOAD SWITCH PMIC
TYPICAL APPLICATION CIRCUIT
U1
VSUS
PFL
PFL
C6
0.1µF
CDELAY
C7
10nF
1.8V
L1
SW1
FB1
VOUT1
VOUT2
100kΩ
100kΩ
R6
R5
300kΩ R1
PFL_ADJ
C2
R2
150kΩ
22µF
2.7V-6V
C1A
VIN1 MP5403B
VIN
1.2V
L2
SW2
FB2
C1B
22µF
22µF
300kΩ R3
300kΩ R4
R10R11
R7 R8 R9
C3
22µF
VIN2
R12
100kΩ
VIN3
EN1
EN2
VIN3
C4
10µF
EN3
VOUT3
VOUT3
PG1
PG2
PG3
PG1
PG2
PG3
C5
10µF
GND, AGND
Figure 6: Typical System Architecture by Using Two Units
MP5403B Rev. 1.0
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MP5403B – DUAL BUCK AND ONE LOAD SWITCH PMIC
PACKAGE INFORMATION
UTQFN-20 (2.5mmX3mm)
PIN 1 ID
MARKING
PIN 1 ID
INDEX AREA
TOP VIEW
BOTTOM VIEW
SIDE VIEW
NOTE:
1) LAND PATTERN OF PIN3,5,12 AND 14 HAVE THE SAME
LENGTH AND WIDTH.
2) LAND PATTERN OF PIN4,6,13 AND 15 HAVE THE SAME
LENGTH AND WIDTH.
3)ALL DIMENSIONS ARE IN MILLIMETERS.
4) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD
FLASH.
5) LEAD COPLANARITY SHALL BE 0.10 MILLIMETERS MAX.
6) DRAWING CONFIRMS TO JEDEC MO-220.
7) DRAWING IS NOT TO SCALE.
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
MP5403B Rev. 1.0
12/5/2017
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