MP8758HGL [MPS]
High-Current, 10A, 22V, Synchronous Step-Down Converter with Hiccup OCP, PFM/PWM Mode Selection, and Auto-Retry Thermal Shutdown;
| 型号： | MP8758HGL |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | High-Current, 10A, 22V, Synchronous Step-Down Converter with Hiccup OCP, PFM/PWM Mode Selection, and Auto-Retry Thermal Shutdown |
| 文件： | 总23页 (文件大小：834K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MP8758H
High-Current, 10A, 22V, Synchronous
Step-Down Converter with Hiccup OCP, PFM/PWM
Mode Selection, and Auto-Retry Thermal Shutdown
The Future of Analog IC Technology
DESCRIPTION
FEATURES
•
•
•
•
•
•
•
•
•
•
•
Wide 4.5V to 22V Operating Input Range
10A Continuous Output Current
Low RDS(ON) Internal Power MOSFETs
Proprietary Switching Loss Reduction
Internal Soft Start
Output Discharge
500kHz Switching Frequency
PFM/PWM Mode Selection
The MP8758H is a fully integrated, high-
frequency, synchronous, rectified, step-down
converter. It offers a very compact solution to
achieve a 10A output current with excellent load
and line regulation over a wide input supply
range.
The MP8758H employs a constant-on-time
(COT) control scheme, which provides fast
transient response and eases loop stabilization.
The COT control scheme provides a seamless
transition into PFM mode at light-load operation,
which boosts light-load efficiency.
Hiccup Mode, OCP, OVP, and UVP
Auto-Retry Thermal Shutdown
Output Adjustable from 0.604V
APPLICATIONS
An open-drain power good signal indicates that
the output voltage is within its nominal voltage
range.
•
•
•
Set-Top Boxes and Multi-Function Printers
Flat-Panel Televisions and Monitors
Distributed Power Systems
Full protection features include over-current
protection (OCP), over-voltage and under-voltage
protection (OVP, UVP), and thermal shutdown.
All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For
MPS green status, please visit the MPS website under Quality
Assurance. “MPS” and “The Future of Analog IC Technology” are registered
trademarks of Monolithic Power Systems, Inc.
The MP8758H requires a minimal number of
readily available, external components and is
available in a QFN-21 (3mmx4mm) package.
TYPICAL APPLICATION
Efficiency vs.
Output Current
100
90
80
70
60
50
40
30
20
10
V
=4.5V
IN
V
=12V
IN
V
=22V
IN
0.01
0.1
1
10
LOAD CURRENT(A)
MP8758H Rev.1.0
10/13/2015
www.MonolithicPower.com
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© 2015 MPS. All Rights Reserved.
1
MP8758H–22V, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER
ORDERING INFORMATION
Part Number*
Package
Top Marking
MP8758HGL
QFN-21 (3mmx4mm)
See Below
* For Tape & Reel, add suffix –Z (e.g. MP8758HGL–Z)
TOP MARKING
MP: MPS prefix
Y: Year code
W: Week code
8758H: First five digits of the part number
LLL: Lot number
PACKAGE REFERENCE
TOP VIEW
QFN-21 (3mmx4mm)
MP8758H Rev.1.0
10/13/2015
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2
MP8758H–22V, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER
Thermal Resistance (5)
QFN-21 (3mmx4mm)..............50 ...... 12...°C/W
θJA
θJC
ABSOLUTE MAXIMUM RATINGS (1)
Supply voltage (VIN) ..................................... 24V
V
V
V
V
V
SW...............................................-0.3V to 24.3V
SW (30ns)..........................................-3V to 28V
SW (5ns)............................................-6V to 28V
BST ................................................... VSW + 5.5V
EN ............................................................... 12V
NOTES:
1) Exceeding these ratings may damage the device.
2) For details on EN’s ABS MAX rating, please refer to the “EN
Control section on page 14.
3) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-to-
ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
Enable current (IEN) (2)............................... 2.5mA
All other pins................................-0.3V to +5.5V
any ambient temperature is calculated by PD (MAX)
=
(3)
(TJ(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation produces an excessive die temperature, causing
the regulator to go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
Continuous power dissipation (TA=+25°C)
QFN-21 (3mmx4mm)................................. 2.5W
Junction temperature................................150°C
Lead temperature .....................................260°C
Storage temperature................ -65°C to +150°C
4) The device is not guaranteed to function outside of its
operating conditions.
5) Measured on JESD51-7, 4-layer PCB.
Recommended Operating Conditions (4)
Supply voltage (VIN) .........................4.5V to 22V
Output voltage (VOUT)..........................................
0.604V to VINxDMAX or 5.5V
Enable current (IEN)..................................... 1mA
Operating junction temp. (TJ)... -40°C to +125°C
MP8758H Rev.1.0
10/13/2015
www.MonolithicPower.com
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© 2015 MPS. All Rights Reserved.
3
MP8758H–22V, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER
ELECTRICAL CHARACTERISTICS
VIN = 12V, TJ = 25°C, unless otherwise noted.
Parameters
Symbol Condition
Min
Typ
Max
Units
Supply Current
Supply current (shutdown)
Supply current (quiescent)
MOSFET
ISD
IQ
VEN = 0V
0
1
μA
μA
VEN = 2V, VFB = 0.65V
160
190
220
High-side switch-on resistance
HSRDS-ON
25
mΩ
TJ = 25°C
Low-side switch-on resistance
Switch leakage
LSRDS-ON
SWLKG
9
0
mΩ
μA
TJ = 25°C
VEN = 0V, VSW = 0V
1
Current Limit
Low-side valley current limit
ILIMIT
10
11
12
A
Switching Frequency and Minimum Off Time
Switching frequency
Minimum off time(6)
FSW
400
250
500
300
600
350
kHz
ns
TOFF
Output Over-Voltage and Under-Voltage Protection
OVP threshold
OVP hysteresis
OVP delay
VOVP_OUT
110
55
115
10
120
65
%VREF
%VREF
μs
TOVPDEL
VUVP
2.5
60
UVP threshold
UVP delay
%VREF
μs
TUVPDEL
12
Reference and Soft Start
Reference voltage
Feedback current
Soft-start time
VREF
IFB
595
604
10
613
50
mV
nA
VFB = 0.604V
TSS
VOUT from 10% to 90%
2.9
ms
Enable and UVLO
Enable input low voltage
Enable hysteresis
VILEN
1.15
1.25
100
3
1.35
4.35
V
VEN-HYS
mV
VEN = 2V
Enable input current
IEN
μA
VEN = 0V
0
VCC under-voltage lockout
threshold rising
VCCVth
4.2
V
VCC under-voltage lockout
threshold hysteresis
VCCHYS
400
mV
MP8758H Rev.1.0
10/13/2015
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4
MP8758H–22V, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER
ELECTRICAL CHARACTERISTICS (continued)
VIN = 12V, TJ = 25°C, unless otherwise noted.
Parameters
Symbol
Condition
Min
Typ
Max
Units
VCC Regulator
VCC regulator
VCC
4.8
5.1
2
5.3
V
VCC load regulation
Icc = 8mA
%
Mode Selection
VCC-
0.4V
Mode high level
V
Mode low level
0.4V
V
Mode internal pull-up resistor
1
MΩ
Power Good
FB rising (good)
PGVth-Hi
PGVth-Lo
PGVth-Hi
PGVth-Lo
PGTd
95
85
FB falling (fault)
%VREF
FB rising (fault)
115
105
800
FB falling (good)
Power-good low to high delay
μs
V
Power-good sink-current
capability
VPG
Sink 4mA
0.4
1
Power good leakage current
IPG_LEAK
VPG = 3.3V
μA
Thermal Protection
Thermal shutdown(6)
Thermal shutdown hysteresis(6)
TSD
150
25
°C
°C
NOTE:
6) Guaranteed by design and engineering sample characterization.
MP8758H Rev.1.0
10/13/2015
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© 2015 MPS. All Rights Reserved.
5
MP8758H–22V, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 12V, VOUT = 1.2V, L = 1.2µH, TA = +25°C, unless otherwise noted.
Efficiency vs. Output
Current
Load Regulation
Line Regulation
100
90
80
70
60
50
40
30
20
10
2.5
2
2
1.5
1
I
=0A
OUT
1.5
1
V
=22V
IN
V
=4.5V
IN
0.5
0
0.5
0
I
=5A
OUT
V
=12V
IN
V
=12V
IN
-0.5
-1
-0.5
-1
V
=22V
IN
-1.5
-2
-1.5
-2
I
=10A
OUT
V
=4.5V
IN
-2.5
0.01
0.1
1
10
0
1
2
3
4
5
6
7
8
9 10
4
6
8
10 12 14 16 18 20 22
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
INPUT VOLTAGE (V)
Enabled Supply Current
vs. Input Voltage
Valley Current Limit
vs. Temperature
14
13
12
11
10
9
400
350
300
250
200
150
100
50
8
7
6
5
4
0
0
5
10
15
20
25
-40 -20
0
20 40 60 80 100
INPUT VOLTAGE (V)
MP8758H Rev.1.0
10/13/2015
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MP8758H–22V, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 1.2V, L = 1.2µH, TA = +25°C, unless otherwise noted.
Start-Up through V
Start-Up through V
Start-Up through V
IN
IOUT=10A
IN
IN
IOUT=0A, PFM
IOUT=0A, PWM
V
V
V
OUT
OUT
OUT
500mV/div.
500mV/div.
500mV/div.
V
V
PG
PG
5V/div.
5V/div.
V
IN
V
V
IN
IN
5V/div.
10V/div.
10V/div.
V
SW
V
V
SW
SW
5V/div.
10V/div.
10V/div.
I
INDUCTOR
2A/div.
I
I
INDUCTOR
INDUCTOR
10A/div.
2A/div.
Shutdown through V
Shutdown through V
Shutdown through V
IN
IOUT=10A
IN
IN
IOUT=0A, PFM
IOUT=0A, PWM
V
V
V
OUT
OUT
OUT
500mV/div.
500mV/div.
500mV/div.
V
V
PG
PG
5V/div.
5V/div.
V
IN
V
IN
V
IN
5V/div.
5V/div.
5V/div.
V
V
V
SW
SW
SW
5V/div.
10V/div.
10V/div.
I
INDUCTOR
I
2A/div.
I
INDUCTOR
INDUCTOR
10A/div.
2A/div.
Start-Up through EN
IOUT=0A, PFM
Start-Up through EN
IOUT=0A, PWM
Start-Up through EN
IOUT=10A
V
V
V
OUT
OUT
OUT
500mV/div.
500mV/div.
500mV/div.
V
V
PG
PG
5V/div.
5V/div.
V
EN
V
EN
V
EN
5V/div.
5V/div.
5V/div.
V
V
V
SW
SW
SW
5V/div.
10V/div.
10V/div.
I
INDUCTOR
I
2A/div.
I
INDUCTOR
INDUCTOR
10A/div.
2A/div.
MP8758H Rev.1.0
10/13/2015
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© 2015 MPS. All Rights Reserved.
7
MP8758H–22V, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 1.2V, L = 1.2µH, TA = +25°C, unless otherwise noted.
Shutdown through EN
IOUT=0A, PFM
Shutdown through EN
IOUT=0A, PWM
Shutdown through EN
IOUT=10A
V
V
OUT
OUT
V
OUT
500mV/div.
500mV/div.
500mV/div.
V
V
PG
EN
V
PG
5V/div.
5V/div.
5V/div.
V
5V/div.
V
V
EN
EN
5V/div.
V
SW
V
SW
SW
5V/div.
10V/div.
10V/div.
I
INDUCTOR
2A/div.
I
I
INDUCTOR
10A/div.
INDUCTOR
10A/div.
Output Voltage Ripple
IOUT=0A, PFM
Output Voltage Ripple
IOUT=0A, PWM
Output Voltage Ripple
IOUT=10A
V
/AC
V
/AC
V
/AC
OUT
OUT
OUT
50mV/div.
20mV/div.
20mV/div.
V
V
V
IN
IN
IN
5V/div.
5V/div.
5V/div.
V
V
V
SW
SW
SW
5V/div.
5V/div.
5V/div.
I
I
INDUCTOR
2A/div.
INDUCTOR
2A/div.
I
INDUCTOR
10A/div.
Load Transient Response
IOUT=5A to 10A
Short-Circuit Entry
IOUT=10A
Short-Circuit Recovery
IOUT=10A
V
OUT
50mV/div.
V
V
OUT
OUT
500mV/div.
500mV/div.
V
V
IN
IN
10V/div.
10V/div.
V
V
SW
SW
5V/div.
5V/div.
I
OUT
5A/div.
I
I
INDUCTOR
10A/div.
INDUCTOR
10A/div.
MP8758H Rev.1.0
10/13/2015
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© 2015 MPS. All Rights Reserved.
8
MP8758H–22V, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 1.2V, L = 1.2µH, TA = +25°C, unless otherwise noted.
Output OVP Entry
IOUT=0A, PFM
Output OVP Recovery
IOUT=0A, PFM
V
V
OUT
OUT
1V/div.
1V/div.
V
V
PG
PG
5V/div.
5V/div.
V
V
SW
SW
5V/div.
5V/div.
I
I
INDUCTOR
5A/div.
INDUCTOR
5A/div.
MP8758H Rev.1.0
10/13/2015
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9
MP8758H–22V, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER
PIN FUNCTIONS
Pin #
Name
Description
Bootstrap. A capacitor connected between SW and BST is required to form a floating
supply across the high-side switch driver.
1
BST
Switch output. Connect SW to the inductor and bootstrap capacitor. SW is driven up
to the VIN voltage by the high-side switch during the on-time of the PWM duty cycle.
The inductor current drives SW negative during the off-time. The on resistance of the
low-side switch and the internal diode fix the negative voltage. Use wide and short PCB
traces to make the connection and try to minimize the area of the SW pattern.
2, 3
SW
4, 7, 18
5, 6
NC
Not connected. Leave NC floating.
Buck regulator output voltage sense. Connect VOUT directly to the output capacitor
of the regulator.
VOUT
Analog ground. The internal reference is referred to AGND. Connect GND of the FB
resistor divider to AGND for better load regulation.
8
9
AGND
MODE
Mode selection. Pull MODE high to set PFM mode. Pull MODE low to set forced PWM
mode. MODE is pulled up internally. Floating MODE sets PFM mode.
10,11,
Exposed
Pad 20, 21
PGND
Power ground. Connect using wide PCB traces and multiple vias.
12,
Exposed
Pad 19
Supply voltage. VIN supplies power for the internal MOSFET and regulator. The
MP8758H operates on a +4.5V to +22V input rail. An input capacitor is needed to
decouple the input rail. Connect using wide PCB traces and multiple vias.
VIN
PG
Power good output. The output of PG is an open-drain signal and is low if the output
voltage is out of the regulation window.
13
Feedback. An external resistor divider from the output to GND (tapped to FB) sets the
output voltage. Place the resistor divider as close to FB as possible. Avoid vias on the
FB traces.
14
15
FB
GND
Ground. GND must be connected to either PGND or AGND for normal operation.
Internal 5V LDO output. The driver and control circuits are powered from VCC.
Decouple with a minimum 1µF ceramic capacitor as close to VCC as possible. X7R or
X5R grade dielectric ceramic capacitors are recommended because of their stable
temperature characteristics.
16
17
VCC
EN
Enable. EN is a digital input, which is used to enable or disable the regulators. When
EN=1, the regulator output turns on; when EN=0, the regulator turns off.
MP8758H Rev.1.0
10/13/2015
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10
MP8758H–22V, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER
FUNCTIONAL BLOCK DIAGRAM
VCC
VOUT
MODE
VIN
BSTREG
BST
VIN
Soft
POR&
Start
Reference
0.6V VREF
On Time
One Shot
FB
EN
Gate
SW
Min off time
Control
Logic
VOUT
PGND
PG
SW
OCP
POK
OVP
%Vref
115% Vref
Fault
Logic
95
AGND
GND
UVP
60%Vref
Figure 1: Functional Block Diagram
MP8758H Rev.1.0
10/13/2015
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MP8758H–22V, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER
OPERATION
that the switching frequency can be fairly fixed at
500kHz for different input and output conditions.
When the HS-FET is turned off, the LS-FET turns
on until the next period.
PWM Operation
The MP8758H is a fully integrated, synchronous,
rectified, step-down, switch-mode converter that
employs
a
constant-on-time (COT) control
scheme to provide fast transient response and
ease loop stabilization. At the beginning of each
cycle, the high-side MOSFET (HS-FET) is turned
on when the feedback voltage (VFB) falls below
the reference voltage (VREF), which indicates
insufficient output voltage. The on period is
determined by both the output and input voltages
to make the switching frequency constant over
the input voltage range.
After the on period elapses, the HS-FET turns off
off or enters an off state. It is turned on again
when VFB drops below VREF. By repeating this
operation, the converter regulates the output
voltage. The integrated low-side MOSFET (LS-
FET) is turned on when the HS-FET is in its off
state to minimize the conduction loss. There will
be a dead short between the input and GND if
both the HS-FET and the LS-FET are turned on
at the same time. This is called a shoot-through.
In order to avoid a shoot-through, a dead time
(DT) is generated internally between the HS-FET
off and the LS-FET on time period or the LS-FET
off and the HS-FET on time period.
Figure 2: Heavy-Load Operation
PWM mode occurs in CCM operation, where the
switching frequency is fairly constant.
Light-Load Operation
Forced PWM Mode Operation
The MP8758H enters continuous conduction
mode (CCM) when working in forced PWM mode.
In this mode, the HS-FET and the LS-FET repeat
the on/off operation, even if the inductor current
drops to zero or a negative value. The switching
frequency (FSW) is fairly constant.
PFM Mode Operation
The inductor current decreases as the load
decreases. Once the inductor current reaches
zero, the operation transitions from continuous
conduction mode (CCM) to discontinuous
conduction mode (DCM).
Internal compensation is applied for COT control
to ensure more stable operation, even when
ceramic capacitors are used as output capacitors.
This internal compensation improves the jitter
performance without affecting the line or load
regulation.
When the MP8758H works in PFM mode during
light-load operation, the switching frequency is
reduced automatically to maintain high efficiency
(see Figure 3). When VFB is below VREF, the HS-
FET is turned on for a fixed interval. When the
HS-FET is turned off, the LS-FET is turned on
until the inductor current reaches zero.
MODE Selection
The MP8758H has MODE selection. When
MODE is pulled high, the part works in PFM
mode. When MODE is pulled low, the part works
in forced PWM mode. MODE is pulled up
internally. Floating MODE sets PFM mode.
In PFM operation, VFB does not reach VREF when
the inductor current approaches zero. The LS-
FET driver turns into tri-state (high Z) whenever
the inductor current reaches zero. As a result, the
efficiency at a light-load condition is improved
greatly. At a light-load condition, the HS-FET is
not turned on as often as it is at a heavy load
condition. This is called skip mode.
Heavy-Load Operation
Continuous conduction mode (CCM) occurs
when the output current is high and the inductor
current is always above zero amps. CCM (see
Figure 2). When VFB is below VREF, the HS-FET is
turned on for a fixed interval, which is determined
by a one-shot on-timer. The one-shot timer is
controlled by the input and output voltages, so
MP8758H Rev.1.0
10/13/2015
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12
MP8758H–22V, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER
VS L OP E 2
VNOISE
At a light-load or no-load condition, the output
VFB
drops very slowly until the MP8758H reduces the
switching frequency, achieving high efficiency at
light load.
VREF
HS Driver
Jitter
Figure 5: Jitter in Skip Mode
without External
Operating
Ramp
Compensation
The traditional constant-on-time control scheme
is intrinsically unstable if the output capacitor’s
ESR is not large enough to act as an effective
current sense resistor. Usually, ceramic
capacitors cannot be used as output capacitors.
Figure 3: Light-Load Operation
As the output current increases from the light-
load condition, the time period within the current
modulator becomes shorter. The HS-FET turns
on more frequently and the switching frequency
increases. The output current reaches critical
levels when the current modulator time is zero.
The critical level of the output current is
determined by Equation (1):
To determine the stability, calculate the ESR
value with Equation (2):
TSW
TON
2
+
0.7× π
(2)
RESR
≥
COUT
(V − VOUT )× VOUT
IN
(1)
IOUT
=
Where TSW is the switching period.
2×L×F × V
S
IN
The MP8758H has a built-in internal ramp
compensator to ensure that the system is stable,
even without the help of the output capacitor’s
ESR. Use a ceramic capacitor to significantly
reduce the output ripple, total BOM cost, and
board area.
PWM mode begins once the output current
exceeds the critical level. The switching
frequency then stays fairly constant over the
output current range.
Jitter and FB Ramp Slope
Jitter occurs in both PWM and skip mode when
noise on the VFB ripple propagates a delay to the
HS-FET driver (see Figure 4 and Figure 5). Jitter
can affect system stability, with noise immunity
proportional to the steepness of VFB’s downward
slope. However, the VFB ripple does not directly
affect noise immunity.
Figure 6 shows a typical output circuit in PWM
mode without an external ramp circuit. Please
refer to the Application Information section on
page 17 for design steps without external
compensation.
SW
L
Vo
VS L OPE1
VNOISE
C4
R1
R2
VF B
FB
VR E F
CAP
HS Driver
J itter
Figure 6: Simplified Circuit in PWM Mode without
External Ramp Compensation
Figure 4: Jitter in PWM Mode
When using a large ESR capacitor on the output,
add a ceramic capacitor with a value of 10µF or
less in parallel to minimize the effect of the ESL.
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MP8758H–22V, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER
Operating with External Ramp Compensation
In skip mode, the downward slope of the VFB
ripple is the same whether the external ramp is
used or not. Figure 8 shows the simplified circuit
in skip mode when both the HS-FET and the LS-
FET are off.
Usually, the MP8758H is able to support ceramic
output capacitors without an external ramp. In
some cases, the internal ramp may not be
enough to stabilize the system, and external
ramp compensation is needed. Please refer to
the Application Information section on page 17
Vo
for
design
steps
with
external
ramp
ESR
R1
FB
compensation.
Ro
L
Vo
SW
Cout
R2
C4
R4
R8
R1
IR 4
IC 4
IFB
Figure 8: Simplified Circuit in Skip Mode
Ceramic
FB
The downward slope of the VFB ripple in skip
mode can be determined with Equation (8):
R 2
−VREF
(8)
VSLOPE2
=
Figure 7: Simplified Circuit in PWM Mode with
External Ramp Compensation
( R +R //Ro)×C
(
)
1
2
OUT
Where Ro is the equivalent load resistor.
Figure 7 shows a simplified external ramp
compensation (R4 and C4) for PWM mode.
Chose R1, R2, R8, and C4 of the external ramp
to meet the condition shown in Equation (3) and
Equation (4):
As described in Figure 5, VSLOPE2 in skip mode is
lower than it is in PWM mode, and the jitter is
larger as well. For a system with less jitter during
a light-load condition, the values of the VFB
resistors should not be too large. However, this
will decrease the light-load efficiency.
⎛
⎜
⎝
⎞
⎟
⎠
R1 ×R2
R1 + R2
1
1
5
<
×
+ R8
(3)
(4)
2π×FSW × C4
EN Control
IR4 = IC4 +IFB ≈ IC4
The regulator turns on when EN is high and turns
off when EN is low.
VRAMP on VFB can then be estimated with
Equation (5):
For automatic start-up, pull EN up to the input
voltage through a resistive voltage divider.
Choose the values of the pull-up resistor (RUP
from VIN to EN) and the pull-down resistor
(RDOWN from EN to GND) to determine the
automatic start-up voltage using Equation (9):
V − VOUT
R4 ×C4
R1 //R2
IN
(5)
VRAMP
=
×TON ×
R1 //R2 +R8
The downward slope of the VFB ripple can be
estimated with Equation (6):
−VRAMP
−VOUT
R4 ×C4
(6)
VSLOPE1
=
=
RUP + R
DOWN (V)
(9)
T
V
= 1.25×
off
IN−START
RDOWN
If there is instability in PWM mode, either R4 or
C4 can be reduced. If C4 cannot be reduced
further due to limitation from Equation (3), then
only R4 can be reduced. For stable PWM
operation, estimate Vslope1 with Equation (7):
For example, if RUP = 150kΩ and RDOWN = 51kΩ,
then V is 4.93V.
IN−START
A 10nF ceramic capacitor from EN to GND is
recommended to avoid noise.
TSW
T
ON -RESRCOUT
There is an internal Zener diode on EN, which
clamps the EN voltage to prevent runaway. EN is
clamped internally using a 12V Zener diode,
which limits the pull-up current to a maximum of
1mA.
+
Io×10-3
0.7×π
2
(7)
-Vslope1
≥
VOUT +
2×L×COUT
TSW -T
on
Where Io is the load current.
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MP8758H–22V, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER
When EN is driven by an external logic signal,
Over-Current Protection and Hiccup Mode
the EN voltage should be lower than 12V. When
EN is connected to VIN through a pull-up resistor
or a resistive voltage divider, the resistance
selection should ensure that the maximum pull-
up current less than 1mA.
The MP8758H has a cycle-by-cycle, over-current
limit. The current limit circuit employs a "valley"
current-sensing algorithm. The RDS(ON) of the LS-
FET is used as a current-sensing element. If the
magnitude of the current-sense signal is above
the current-limit threshold, the control logic is not
allowed to initiate a new cycle.
If a resistive voltage divider is being used and
VIN is higher than 12V, calculate the allowed
minimum pull-up resistor (RUP) with Equation (10):
The trip level is fixed internally. The inductor
current is monitored by the voltage between GND
and SW. Since GND is used as the positive
current sensing node, GND should be connected
to the source terminal of the bottom MOSFET.
V (V)−12
RUP(kΩ)
12
IN
(10)
−
< 1(m A )
RDOWN(kΩ)
If only the pull-up resistor (RUP) is being used and
Since the comparison is done during the HS-FET
off and the LS-FET on state, the OC trip level
sets the valley level of the inductor current.
Calculate the load current at the over-current
threshold (IOC) with Equation (12):
the pull-down resistor is not connected, V
IN-START
is determined by the UVLO input. Calculate the
minimum resistor value with Equation (11):
V (V) −12
IN
(11)
RUP(kΩ) >
1(m A )
ΔI
inductor
IOC = I_limit +
(12)
A typical pull-up resistor is 499kꢀ.
2
In an over-current condition, the current to the
load exceeds the current to the output capacitor,
and the output voltage falls off. The output
voltage drops until VFB is below the under-voltage
(UV) threshold, typically 60% below the reference.
Once UV is triggered, the MP8758H enters
hiccup mode to restart the part periodically. The
chip disables the output power stage, discharges
the soft-start capacitor, and tries to soft start
again automatically. This protection mode is
especially useful when the output is dead-shorted
to ground. The average short-circuit current is
greatly reduced to alleviate thermal issues and
protect the regulator. If the over-current condition
still holds after the soft start ends, the device
repeats this operation cycle until the over-current
condition is removed. The MP8758H then exits
hiccup mode and the output rises back to
regulation level.
Soft Start (SS)
The MP8758H employs
a
soft-start (SS)
mechanism to ensure smooth output during
power-up. When EN pulls high, both the internal
reference voltage and the output voltage ramp up
gradually. Once the reference voltage reaches its
target value, the soft start finishes and the
MP8758H enters steady-state operation.
If the output is pre-biased to a certain voltage
during start-up, the IC disables the switching of
both the high- and low-side switches until the
voltage on the internal reference exceeds the
sensed output voltage at the FB node.
Power Good (PG)
The MP8758H uses a power good (PG) output to
indicate whether the output voltage of the
regulator is ready. PG is the open drain of the
MOSFET. Connect PG to VCC or another voltage
source through a resistor (e.g. 100k). After the
input voltage is applied, the MOSFET is turned
on, and PG is pulled to GND before SS is ready.
When the soft start finishes and the FB voltage is
higher than 95% and lower than 105% of the
internal reference voltage, PG is pulled high after
a short delay of 0.8ms.
Over- and Under-Voltage Protection (OVP/UVP)
The MP8758H monitors a resistor divided
feedback voltage to detect over- and under-
voltage. When the feedback voltage rises higher
than 115% of the target voltage, the controller
enters OVP. During this period, the LS-FET is
forced on with a negative current limit of -1A,
When the FB voltage is lower than 85% and
higher than 115% of the internal reference
voltage, PG is pulled low.
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MP8758H–22V, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER
Thermal Shutdown
discharges the output, and tries to keep it within
the normal range. The part exits OVP when FB
falls below 105% of the target voltage.
The MP8758H has thermal shutdown protection.
The junction temperature of the IC is monitored
internally. The converter shuts off if the junction
temperature exceeds the threshold value,
typically 150ºC. This is called non-latch
protection. Hysteresis is about 25ºC. Once the
junction temperature drops to about 125ºC, a soft
start is initiated.
If OTP occurs during OVP, the LS-FET turns off
and stops discharging the output until the silicon
temperature falls below 125°C.
When the feedback voltage falls below 60% of
the target voltage, the UVP comparator output
goes high. If the UV still occurs after a 12µs
delay, then hiccup mode is triggered.
Output Discharge
The MP8758H discharges the output when EN is
low, or when the controller is turned off by the
protection functions (UVLO and thermal
shutdown). The part uses an internal 6ꢀ
MOSFET to discharge the output.
Under-Voltage Lockout (UVLO)
The MP8758H has under-voltage lockout
protection (UVLO). When VCC is higher than
UVLO’s rising threshold voltage, the part powers
up, and shuts off when VCC falls below the
UVLO falling threshold voltage. This is called
non-latch protection. If an application requires a
higher UVLO, use two external resistors on EN to
adjust the input voltage UVLO (see Figure 9). It is
recommended to use the EN resistors to set the
UVLO falling threshold (VSTOP) above 4.2V. The
rising threshold (VSTART) should be set to provide
enough hysteresis to allow for any input supply
variations.
8758H
MP
IN
RUP
EN Comparator
EN
RDOWN
Figure 9: Adjustable UVLO
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MP8758H–22V, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER
APPLICATION INFORMATION
Setting the Output Voltage without External
Compensation
Setting the Output Voltage with External
Compensation
If the system is not stable enough when the low
ESR ceramic capacitor is used on the output,
add an external voltage ramp to FB through
resistor R4 and capacitor C4.
The MP8758H can support different types of
output capacitors, including POSCAP, electrolytic
capacitors, and ceramic capacitors without
external ramp compensation. The output voltage
is then set by feedback resistors R1 and R2 (see
Figure 10).
SW
L
Vo
SW
R4
R1
R2
FB
C4
R8
L
Vo
Ceramic
C4
R1
R2
FB
CAP
Figure 11: Simplified Circuit of Ceramic Capacitor
The output voltage is influenced by VRAMP beside
the R divider (see Figure 11). VRAMP can be
calculated with Equation (5) on page 14. R2
should be chosen carefully, as a small value for
R2 will lead to considerable quiescent current
loss while too large a value for R2 will make the
FB noise sensitive. Use a comparatively larger
R2 when Vo is low (e.g. 1.05V), and a smaller R2
when Vo is high. The value of R1 can then be
calculated with Equation (14):
Figure 10: Simplified Circuit of POS Capacitor
First, carefully choose a value for R2, as a small
value for R2 will lead to considerable quiescent
current loss, while too large a value for R2 will
make the FB noise sensitive. Set the current
through R2 around 5-10µA for good balance,
system stability, and no load loss. Considering
the output ripple, calculate R1 with Equation (13):
R2
(14)
1
R1=
VOUT
−
ΔVOUT − VREF
V
R2
FB(AVG)
2
-
(13)
R1 =
⋅R2
(VOUT -VFB(AVG) ) R4 +R8
VREF
VFB(AVG) is the average value on FB. VFB(AVG)
varies with VIN, VOUT, and load condition. Since
the value in skip mode is lower than in PWM
mode, the load and line regulations are strictly
related to VFB(AVG). If a better load or line
regulation is needed, use a lower VRAMP, as long
as the criterion shown in Equation (7) are met.
Where ΔVOUT is the output ripple.
In addition to feedback resistors, a feed-forward
capacitor (C4) is usually applied for better
transient performance. When using ceramic
capacitors, a capacitor value around 100pF-1nF
is suggested for better transient response while
also keeping the system stable with noise
immunity. If the system is noise sensitive
because of the zero induced by this capacitor,
add a resistor (R8) between the capacitor and FB
to form a pole. This resistor can be set according
to Equation (16) on page 18.
For PWM operation, VFB(AVG) can be determined
with Equation (15):
1
R1 //R2
V
= VREF + VRAMP
×
(15)
FB(AVG)
2
R1 //R2 +R8
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MP8758H–22V, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER
R8 is set to 0ꢀ and can be set using Equation
Ceramic capacitors with X5R and X7R
dielectrics are recommended because of their
low ESR and small temperature coefficients.
(16) for better noise immunity. Also, it should be
five times smaller than R1//R2 to minimize its
influence on VRAMP. R8 can be calculated with
Equation (16):
The capacitors must also have a ripple current
rating greater than the maximum input ripple
current of the converter. The input ripple current
can be estimated with Equation (18):
1
R8 =
(16)
2π×C4 ×2F
SW
VOUT
VOUT
(18)
ICIN = IOUT
×
×(1−
)
Using Equation (14) on page 17 to calculate R1
can be complicated. To simplify the calculation,
a DC-blocking capacitor (CDC) can be added to
filter the DC influence from R4 and R8. Figure
12 shows a simplified circuit with external ramp
compensation and a DC-blocking capacitor.
With this capacitor, R1 can easily be obtained
by using the simplified equation for PWM mode
shown in Equation (17):
V
V
IN
IN
The worst-case condition occurs at VIN = 2VOUT
,
shown in Equation (19):
IOUT
ICIN
=
(19)
2
For simplification, choose an input capacitor
with an RMS current rating greater than half of
the maximum load current. The input
capacitance value determines the input voltage
ripple of the converter. If there is an input
voltage ripple requirement in the system,
choose the input capacitor that meets the
specification.
1
(VOUT − VREF − VRAMP
)
2
R1 =
R2
(17)
1
VREF + VRAMP
2
SW
FB
L
Vo
The input voltage ripple can be estimated with
Equation (20):
R4
R1
R2
C4
Cdc
IOUT
SW ×CIN
VOUT
VOUT
Ceramic
ΔV =
×
×(1−
)
(20)
IN
F
V
V
IN
IN
The worst-case condition occurs at VIN = 2VOUT
,
shown in Equation (21):
Figure 12: Simplified Circuit of Ceramic
Capacitor with DC Blocking Capacitor
IOUT
4 FSW ×CIN
1
ΔV =
×
(21)
IN
CDC is suggested to be at least 10 times larger
than C4 for better DC-blocking performance,
and should not be larger than 0.47µF,
considering start-up performance. If a larger
CDC is needed for better FB noise immunity,
combine it with reduced R1 and R2 to limit
CDC reasonably without affecting the system
start-up. Note that even when the CDC is
applied, the load and line regulations are still
Selecting the Output Capacitor
The output capacitor maintains the DC output
voltage. Ceramic or POSCAP capacitors are
recommended. The output voltage ripple can be
estimated with Equation (22):
VOUT
V
1
×(1− OUT )×(RESR
+
(22)
)
ΔVOUT
=
FSW ×L
V
8×FSW ×COUT
IN
V
RAMP-related.
For ceramic capacitors, the capacitance
dominates the impedance at the switching
frequency, and the capacitance causes the
majority of the output voltage ripple. For
simplification, the output voltage ripple can be
estimated with Equation (23):
Selecting the Input Capacitor
The input current to the step-down converter is
discontinuous, and therefore requires
capacitor to supply the AC current to the step-
down converter while maintaining the DC input
voltage. For best performance, use a ceramic
capacitor placed as close to VIN as possible.
a
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MP8758H–22V, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER
switch current limit. The inductance value can
VOUT
VOUT
(23)
ΔVOUT
=
×(1−
)
be calculated with Equation (26):
8×F 2 ×L×COUT
V
IN
SW
VOUT
SW × ΔIL
VOUT
(26)
L =
×(1−
)
Since the output voltage ripple caused by the
ESR is very small, an external ramp is needed
to stabilize the system. The external ramp can
be generated through resistor R4 and capacitor
C4.
F
V
IN
Where ΔIL is the peak-to-peak inductor ripple
current.
The inductor should not saturate under the
maximum inductor peak current. The peak
inductor current can be estimated with Equation
(27):
When using POSCAP capacitors, the ESR
dominates the impedance at the switching
frequency. Since the ramp voltage generated
from the ESR is high enough to stabilize the
system, an external ramp is not needed. A
minimum ESR value of around 12mꢀ is
required to ensure stable operation of the
converter. For simplification, the output ripple
can be approximated with Equation (24):
VOUT
VOUT
(27)
ILP = IOUT
+
×(1−
)
2FSW ×L
V
IN
PCB Layout Guidelines
Efficient PCB layout is critical for stable
operation. For best results, refer to Figure 13
and follow the guidelines below.
VOUT
V
ΔVOUT
=
×(1− OUT )×RESR
(24)
F
SW ×L
V
IN
1. Place the high-current paths (PGND, VIN,
and SW) as close to the device as possible
with short, direct, and wide traces.
2. Place the input capacitors as close to VIN
and PGND as possible.
3. Place the decoupling capacitor as close to
VCC and AGND as possible. If the distance
is long, place the capacitor close to VCC. If
a via is required to reduce the leakage
inductance, use >3 vias.
The maximum output capacitor limitation should
be considered during design application. The
MP8758H has a soft-start time period of around
2.9ms. If the output capacitor value is too large,
the output voltage cannot reach the design
value during the soft-start time and cannot
regulate. The maximum output capacitor value
limitation (Co_max) can be estimated using
Equation (25):
4. Keep the switching node (SW) short and
away from the feedback network.
CO _MAX = (ILIM_ AVG −IOUT )× Tss / VOUT
(25)
5. Place the external feedback resistors next
to FB, ensuring that there is no via on the
FB trace.
Where ILIM_AVG is the average start-up current
during a soft-start period, and Tss is the soft-
start time.
6. Keep the BST voltage path as short as
possible.
Selecting the Inductor
The inductor is necessary to supply a constant
current to the output load while being driven by
the switched input voltage. An inductor with a
larger value results in less ripple current and a
lower output ripple voltage, but also has a
larger physical footprint, a higher series
resistance, and a lower saturation current.
When determining the inductance value, select
the peak-to-peak ripple current in the inductor
to be in the range of 30% to 40% of the
maximum output current, and ensure that the
peak inductor current is below the maximum
7. Keep the VIN and PGND pads connected
with large copper traces, using at least two
layers for the IN and PGND traces to
achieve better thermal performance. To
help with thermal dissipation, add several
vias with 10mil_drill/18mil_copper_width
close to the VIN and PGND pads. A four-
layer layout is recommended strongly to
achieve better thermal performance.
NOTE:
Please refer to the PCB Layout Application Note for more details.
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MP8758H–22V, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER
Figure 13: Recommended Layout
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MP8758H–22V, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER
Design Example
Table 2 is a design example following the
application guidelines for the specifications
below:
Table 2 : Design Example
VOUT
(V)
Cout
(F)
L
(μH)
R4
(Ω)
C4
(F)
R1
(kΩ)
R2
(kΩ)
1.05
1.2
1.35
3.3
5
22μx3
22μx3
22μx3
22µx4
22µx4
1.2
1.2
1.2
2
NS
NS
NS
1M
1M
220p
220p
220p
220p
220p
59
82
100
82
100
100
88.7
150
18
2
18
The detailed application schematics for 1.2V
and 5V application (when low ESR capacitors
are applied) are shown in Figure 14 and Figure
15. The typical performance and circuit
waveforms are shown in the Typical
Performance Characteristics section. For more
device applications, please refer to the related
evaluation board datasheets.
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MP8758H–22V, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER
TYPICAL APPLICATION CIRCUITS
1
12,19
2,3
VIN
BST
SW
17
9
EN
MODE
PG
14
FB
13
4,7,18
NC
16
15
VCC
GND
5,6
VOUT
PGND
10,11,20,21
AGND
8
Figure 14: Typical Application Circuit with Low ESR Ceramic Output Capacitor
VIN=4.5-22V, VOUT=1.2V
4.7ꢀ
R3
C3
220nF
VIN
7-22V
VOUT
5V
1
L1 2μH
12,19
2,3
VIN
BST
SW
C4
220pF
R4
1Mꢀ
C1A
C1B
C1C
C2C
C2D
R5
499kꢀ
C2A
C2B
C2E
22μF
22μF
22μF
22μF
0.1μF
22μF
22μF 0.1μF
R1
D1
NS
150kꢀ
R8
499ꢀ
R6
NS
17
9
EN
14
MODE
PG
FB
J1
13
MP8758H
R7
100kꢀ
4,7,18
R2
18kꢀ
NC
16
15
VCC
GND
C5
1μF
5,6
VOUT
PGND
10,11,20,21
AGND
8
Figure 15: Typical Application Circuit with Low ESR Ceramic Output Capacitor
VIN=7-22V, VOUT=5V
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MP8758H–22V, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER
PACKAGE INFORMATION
QFN-21 (3mmx4mm)
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
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