MPQ2918GLE-AEC1 [MPS]
4V - 40V Input, Current Mode, Synchronous, Step-Down Controller AEC-Q100 Qualified;
| 型号： | MPQ2918GLE-AEC1 |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | 4V - 40V Input, Current Mode, Synchronous, Step-Down Controller AEC-Q100 Qualified |
| 文件： | 总32页 (文件大小：1353K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MPQ2918
4V - 40V Input, Current Mode,
Synchronous, Step-Down Controller
AEC-Q100 Qualified
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MPQ2918 is a high-voltage, synchronous,
step-down controller that steps down voltages
directly from up to 40V. The MPQ2918 uses
pulse-width modulation (PWM) current control
architecture with accurate cycle-by-cycle
current limiting and is capable of driving dual N-
channel MOSFETs.
Wide 4V to 40V Operating Input Range
Dual N-Channel MOSFET Driver
0.8V Voltage Reference with ±1.5%
Accuracy Over Temperature
Low Dropout Operation: Maximum Duty
Cycle at 99.5%
Programmable Frequency Range: 100kHz -
1000kHz
External Sync Clock Range: 100kHz -
1000kHz
Advanced asynchronous mode (AAM) enables
non-synchronous operation to optimize light-
load efficiency.
180° Out-of-Phase SYNCO Pin
Programmable Soft Start (SS)
Power Good (PG) Output Voltage Monitor
Selectable Cycle-by-Cycle Current Limit
Output Over-Voltage Protection (OVP)
Over-Current Protection (OCP)
Internal LDO with External Power Supply
Option
The operating frequency of the MPQ2918 can
be programmed by an external resistor or
synchronized to an external clock for noise-
sensitive applications. Full protection features
include precision output over-voltage protection
(OVP), output over-current protection (OCP),
and thermal shutdown.
The MPQ2918 is available in TSSOP20-EP and
QFN-20 (3mmx4mm) packages.
Programmable Forced CCM and AAM
Available in TSSOP20-EP and QFN-20
(3mmx4mm) Packages
AEC-Q100 Grade-1
APPLICATIONS
Automotive
Industrial Control Systems
All MPS parts are lead-free, halogen-free, and adhere to the RoHS
directive. For MPS green status, please visit the MPS website under quality
assurance. “MPS” and “The Future of Analog IC Technology” are
registered trademarks of Monolithic Power Systems, Inc.
TYPICAL APPLICATION
MPQ2918 Rev. 1.01
8/17/2017
www.MonolithicPower.com
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1
MPQ2918 – 4V - 40V, CURRENT MODE, SYNC, STEP-DOWN CONTROLLER
ORDERING INFORMATION
Part Number
Package
Top Marking
MPQ2918GF*
MPQ2918GL
MPQ2918GF-AEC1
MPQ2918GL-AEC1
MPQ2918GLE-AEC1
TSSOP-20 EP
QFN-20 (3mmx4mm)
TSSOP-20 EP
QFN-20 (3mmx4mm)
QFN-20 (3mmx4mm)
See Below
See Below
See Below
See Below
See Below
*For Tape & Reel, add suffix –Z (e.g. MPQ2918GF–Z)
TOP MARKING (MPQ2918GF & MPQ2918GF-AEC1)
MPS: MPS prefix
YY: Year code
WW: Week code
MP2918: Product code of MPQ2918GF & MPQ2918GF-AEC1
LLLLLLLLL: Lot number
TOP MARKING (MPQ2918GL & MPQ2918GL-AEC1)
MP: MPS prefix
Y: Year code
W: Week code
2918: Product code of MPQ2918GL & MPQ2918GL-AEC1
LLL: Lot number
MPQ2918 Rev. 1.01
8/17/2017
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© 2017 MPS. All Rights Reserved.
2
MPQ2918 – 4V - 40V, CURRENT MODE, SYNC, STEP-DOWN CONTROLLER
TOP MARKING (MPQ2918GLE-AEC1)
MP: MPS prefix
Y: Year code
W: Week code
2918: Product code of MPQ2918GLE-AEC1
LLL: Lot number
E: Wettable lead flank
PACKAGE REFERENCE
TOP VIEW
TOP VIEW
VCC2
VCC1
SGND
16
15
1
2
SW
BG
3
4
14
13
MPQ2918
PGND
SS
COMP
FB
SENSE+
SENSE-
12
11
5
6
SYNCO
TSSOP-20 EP
QFN-20 (3mmx4mm)
MPQ2918 Rev. 1.01
8/17/2017
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MPQ2918 – 4V - 40V, CURRENT MODE, SYNC, STEP-DOWN CONTROLLER
ABSOLUTE MAXIMUM RATINGS (1)
Input supply voltage (VIN)............................. 65V
BST supply voltage (VBST).................. VIN + 6.5V
SW..................................................-0.3V to 65V
EN/SYNC..................................................... 55V
BST - SW.................................................... 6.5V
Supply voltage (VCC1) ............................... 6.5V
External supply voltage (VCC2)................... 15V
SENSE + / - ................................................. 28V
Differential sense (SENSE+ to SENSE-)............
.....................................................-0.7V to +0.7V
TG...............................VSW - 0.3V to VBST + 0.3V
BG ...................................-0.3V to VCC1 + 0.3V
All other pins................................-0.3V to +6.5V
Thermal Resistance (3)
TSSOP-20 EP ........................40....... 8.... °C/W
QFN-20 (3mmx4mm)..............48...... 10... °C/W
θJA
θJC
NOTES:
1) Absolute maximum are rated under room temperature unless
otherwise noted. Exceeding these ratings may damage the
device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-to-
ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation produces an excessive die temperature, causing
the regulator to go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
3) Measured on JESD51-7, 4-layer PCB.
(2)
Continuous power dissipation (TA = +25°C)
TSSOP-20 EP............................................ 3.1W
QFN-20 (3mmx4mm)................................. 2.6W
Junction temperature................................150°C
Lead temperature .....................................260°C
Storage temperature................ -65°C to +175°C
Recommended Operating Conditions
Supply voltage (VIN) ............................4V to 40V
Output voltage (VOUT)................................. ≤25V
Supply voltage for (VCC2)...............4.7V to 12V
Operating junction temp. (TJ)... -40°C to +125°C
MPQ2918 Rev. 1.01
8/17/2017
www.MonolithicPower.com
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MPQ2918 – 4V - 40V, CURRENT MODE, SYNC, STEP-DOWN CONTROLLER
ELECTRICAL CHARACTERISTICS
VIN = 24V, TJ = -40°C to +125°C, EN/SYNC = 2V, VILIMIT = 75mV, unless otherwise noted.
Parameters
Symbol
Condition
Min
Typ
Max Units
Input Supply
VIN UVLO threshold (rising)
VIN UVLO threshold (falling)
VIN UVLO hysteresis
INUV RISING
INUV FALLING
INUV HYS
4
3.2
4.5
3.7
800
5
3.95
V
V
mV
VCC2 = 12V, external bias,
VIN supply current with VCC2
bias
VAAM = 5V, VFB = 0.84V,
SENSE+ = SENSE- = 0V,
no switching
VCC2 = 0V, VFB = 0.84V,
VAAM = 5V, SENSE+ = SENSE-
= 0V, no switching
IQ_VCC2
25
40
μA
μA
VIN supply current without
VCC2 bias
IQ
750
1000
VCC2 = 0V, VAAM = 0.6V,
VIN AAM current
IQ_AAM
ISHDN
V
FB = 0.84V, SENSE+ =
250
0.5
350
5
μA
μA
SENSE- = 12V, no switching
VEN = 0V
VIN shutdown current
VCC Regulator
VCC1 regulator output voltage
from VIN
VCC1 regulator load
regulation from VIN
VCC1_VIN
VIN > 6V, load = 0 to 50mA
4.5
5
1
5.5
3
V
Load = 0 to 50mA, VCC2
floating or connected to SGND
%
VCC1 regulator output voltage
from VCC2
VCC1_VCC2 VCC2 > 6V
5
V
VCC1 regulator load
regulation from VCC2
Load = 0 to 50mA, VCC2 = 12V
1
3
%
VCC2 UVLO threshold (rising) VCC2
VCC2 UVLO threshold (falling) VCC2
4.3
4.05
4.7
4.45
250
4.92
4.75
V
V
mV
RISING
FALLING
VCC2 threshold hysteresis
VCC2
HYS
VAAM = 5V, VFB = 0.84V,
SENSE+ = SENSE- = 12V,
VCC2 = 12V, no switching
VAAM = 0.6V, VFB = 0.84V,
SENSE+ = SENSE- =12V,
VCC2 = 12V, no switching
800
200
1100
300
μA
μA
VCC2 supply current
IVCC2
Feedback (FB)
Feedback voltage
Feedback current
VFB
IFB
0.788 0.800 0.812
10
V
nA
4V VIN 40V
VFB = 0.8V
Enable (EN/SYNC)
Enable threshold (rising)
Enable threshold (falling)
Enable threshold hysteresis
Enable input current
Enable turn-off delay
VEN RISING
VEN FALLING
VEN TH
IEN
1.16
1.03
1.22
1.09
130
2
1.28
1.15
V
V
mV
μA
μs
VEN/SYNC = 2V
5
tOFF
10
20
40
MPQ2918 Rev. 1.01
8/17/2017
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MPQ2918 – 4V - 40V, CURRENT MODE, SYNC, STEP-DOWN CONTROLLER
ELECTRICAL CHARACTERISTICS (continued)
VIN = 24V, TJ = -40°C to +125°C, EN/SYNC = 2V, VILIMIT = 75mV, unless otherwise noted.
Parameters
Symbol
Condition
Min
Typ
Max
Units
Oscillator and Sync
Operating frequency
Foldback operating frequency
FSW
RFREQ = 45.3kΩ
340
430
520
kHz
FSW
FSW_FOLDBACK VFB = 0.1V
FSWH
50%
Maximum programmable
frequency
1000
kHz
Minimum programmable
frequency
FSWL
FSYNC
100
kHz
kHz
V
EN/SYNC frequency range
100
2
1000
EN/SYNC voltage rising
threshold
VSYNC_RISING
EN/SYNC voltage falling
threshold
Current Sense
Current sense common mode
voltage range
VSYNC_FALLING
0.35
25
V
VSENSE+/-
0
V
ILIM = SGND, VSENSE+ = 3.3V
15
40
65
25
50
75
8
17
35
60
85
mV
mV
mV
Current limit sense voltage
VILIMIT
VREV_ILIMIT
VVAL_ILIMIT
ISENSE
ILIM = VCC1, VSENSE+ = 3.3V
ILIM = float, VSENSE+ = 3.3V
ILIM = SGND, VSENSE+ = 3.3V
ILIM = VCC1, VSENSE+ = 3.3V
ILIM = float, VSENSE+ = 3.3V
ILIM = SGND, VSENSE+ = 3.3V
ILIM = VCC1, VSENSE+ = 3.3V
ILIM = float, VSENSE+ = 3.3V
VSENSE+/-(CM) = 0V
Reverse current limit sense
voltage
mV
mV
24
22.5
47.5
72.5
-45
115
150
Valley current limit
-70
80
105
-20
160
205
μA
μA
μA
Input current of sensor
VSENSE+/-(CM) = 3.3V
VSENSE+/-(CM) > 5V
Soft Start (SS)
Soft-start source current
ISS
SS = 0.5V
2
4
6
μA
Error Amplifier (EA)
Error amp transconductance (4)
Error amp open loop DC gain (4)
Error amp sink/source current
Protection
Gm
AO
IEA
∆V = 5mV
500
70
±30
μS
dB
μA
FB = 0.7/0.9V
Over-voltage threshold
Over-voltage hysteresis
Thermal shutdown (5)
VOV
VOV HYS
110% 115% 120%
VFB
VFB
°C
10%
170
20
Thermal shutdown hysteresis (5)
°C
MPQ2918 Rev. 1.01
8/17/2017
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MPQ2918 – 4V - 40V, CURRENT MODE, SYNC, STEP-DOWN CONTROLLER
ELECTRICAL CHARACTERISTICS (continued)
VIN = 24V, TJ = -40°C to +125°C, EN/SYNC = 2V, VILIMIT = 75mV, unless otherwise noted.
Parameters
Symbol
Condition
Min
Typ
Max Units
Gate Driver
TG pull-up resistor
TG pull-down resistor
BG pull-up resistor
BG pull-down resistor
Dead time
TG maximum duty cycle
TG minimum on time (5)
BG minimum on time
Power Good (PG)
Power good low
RTG_PULLUP
RTG_PULLDN
RBG_PULLUP
RBG_PULLDN
tdead
Dmax
tON MIN TG
tON MIN BG
2
1
3
Ω
Ω
Ω
1
Ω
CLoad = 3.3nF
VFB = 0.7V
60
99.5
92
175
ns
%
ns
98
250
0.3
ns
VPG Low
Iload = 4mA
VOUT rising
VOUT falling
VOUT falling
VOUT rising
0.1
V
85%
90% 96.5%
101% 107% 112.5%
81% 87% 92.5%
PG rising threshold
PG falling threshold
PGVth_RSING
VFB
PGVth_FALLING
VFB
105% 110% 116.5%
PG threshold hysteresis
Power good leakage
PGVth HYS
IPG_LK
3%
VFB
μA
PG = 5V
Rising
Falling
2
28
28
Power good delay
tPG_delay
μs
AAM/CCM
AAM output current
IAAM
RFREQ = 45.3kΩ
13.2
2.3
μA
CCM required AAM threshold
voltage
VCCM_TH
V
NOTES:
4) Not tested in production, guaranteed by design.
5) Not tested in production, derived from bench characterization.
MPQ2918 Rev. 1.01
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MPQ2918 – 4V - 40V, CURRENT MODE, SYNC, STEP-DOWN CONTROLLER
TYPICAL CHARACTERISTICS
VIN = 24V, TJ = -40°C to +125°C, unless otherwise noted.
MPQ2918 Rev. 1.01
8/17/2017
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MPQ2918 – 4V - 40V, CURRENT MODE, SYNC, STEP-DOWN CONTROLLER
TYPICAL CHARACTERISTICS (continued)
VIN = 24V, TJ = -40°C to +125°C, unless otherwise noted.
MPQ2918 Rev. 1.01
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MPQ2918 – 4V - 40V, CURRENT MODE, SYNC, STEP-DOWN CONTROLLER
TYPICAL CHARACTERISTICS (continued)
VIN = 24V, TJ = -40°C to +125°C, unless otherwise noted.
30
ILIMIT=FLOAT
25
20
ILIMIT=VCC1
15
ILIMIT=GND
10
5
0
-40 -25 -10
5 20 35 50 65 80 95 110125
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MPQ2918 – 4V - 40V, CURRENT MODE, SYNC, STEP-DOWN CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 24V, VOUT = 5V, L = 4.7µH, AAM, FSW = 500kHz, TA = +25°C, unless otherwise noted.
Case Temperature Rise
vs. Load Current
100
90
80
70
60
50
40
30
20
10
0
40
100
95
90
85
80
75
70
65
60
V
=12V
IN
V
=12V
IN
35
30
25
20
15
10
5
V
=24V
IN
V
=24V
IN
V
=36V
V
=36V
IN
IN
V
=40V
V
=40V
IN
IN
0
10
100
1000
10000
10
100
I
1000
(mA)
10000
0
1
2
3
4
5
6
7
8
LOAD CURRENT (mA)
LOAD CURRENT (A)
OUT
0.05
0.04
0.03
0.02
0.01
0.00
-0.01
-0.02
-0.03
-0.04
-0.05
0.20
0.15
0.10
0.05
0.00
-0.05
-0.10
-0.15
-0.20
I
=8A
OUT
I
=0A
OUT
I
=4A
OUT
1
10
100
1000 10000
10
15
20
25
(V)
30
35
40
V
LOAD CURRENT (mA)
IN
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MPQ2918 – 4V - 40V, CURRENT MODE, SYNC, STEP-DOWN CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 24V, VOUT = 5V, L = 4.7µH, AAM, FSW = 500kHz, TA = +25°C, unless otherwise noted.
MPQ2918 Rev. 1.01
8/17/2017
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MPQ2918 – 4V - 40V, CURRENT MODE, SYNC, STEP-DOWN CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 24V, VOUT = 5V, L = 4.7µH, AAM, FSW = 500kHz, TA = +25°C, unless otherwise noted.
MPQ2918 Rev. 1.01
8/17/2017
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MPQ2918 – 4V - 40V, CURRENT MODE, SYNC, STEP-DOWN CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 24V, VOUT = 5V, L = 4.7µH, AAM, FSW = 500kHz, TA = +25°C, unless otherwise noted.
MPQ2918 Rev. 1.01
8/17/2017
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MPQ2918 – 4V - 40V, CURRENT MODE, SYNC, STEP-DOWN CONTROLLER
PIN FUNCTIONS
TSSOP-20 QFN-20
Name
Description
Pin #
Pin #
Input supply. The MPQ2918 operates on a 4V to 40V input range. A
ceramic capacitor is needed to prevent large voltage spikes at the input.
1
19
IN
Enable input. The EN/SYNC threshold is 1.22V with 130mV of hysteresis.
EN/SYNC is used to implement an input under-voltage lockout (UVLO)
function externally. If an external sync clock is applied to EN/SYNC, the
internal clock follows the sync frequency.
2
3
20
1
EN/SYNC
VCC2
External power supply for the internal VCC1 regulator. VCC2 disables
the power from VIN for as long as VCC2 is higher than 4.7V. Do not
connect a power supply greater than 12V to VCC2. Connect VCC2 to an
external power supply to reduce power dissipation and increase efficiency.
Internal bias supply. A ≥1µF decoupling capacitor is required between
VCC1 and PGND.
4
5
6
7
2
3
4
5
VCC1
SGND
SS
Low-noise ground reference. SGND should be connected to the VOUT
side of the output capacitors.
Soft-start control input. SS is used to program the soft-start period with
an external capacitor between SS and SGND.
Regulation control loop compensation. Connect an R-C network from
COMP to SGND to compensate for the regulation control loop.
COMP
Feedback. FB is the input of the error amplifier. An external resistive
divider connected between the output and SGND is compared to the
internal +0.8V reference to set the regulation voltage.
8
9
6
7
FB
Continuous conduction mode/advanced asynchronous mode. Floating
CCM/AAM or connecting CCM/AAM to VCC1 makes the part operate in
CCM/AAM CCM. Connecting an appropriate external resistor from CCM/AAM to
SGND (so AAM is at a low level) makes the part operate in AAM. The AAM
voltage should be no less than 480mV.
Frequency. Connect a resistor between FREQ and SGND to set the
switching frequency.
10
11
8
9
FREQ
PG
Power good output. The output of PG is an open drain.
Sense voltage limit set. The voltage at ILIM sets the nominal sense
voltage at the maximum output current. There are three fixed options: float,
VCC1, and SGND.
12
10
ILIM
Frequency synchronous out. SYNCO outputs a 180° out-of-phase clock
when the part works in CCM for dual-channel operation.
13
14
15
11
12
13
SYNCO
SENSE-
SENSE+
Negative input for the current sense. The sensed inductor current limit
threshold is determined by the status of ILIM.
Positive input for the current sense. The sensed inductor current limit
threshold is determined by the status of ILIM.
High-current ground reference for the internal low-side switch driver
and the VCC1 regulator circuit. Connect PGND to the negative terminal
of the VCC1 decoupling capacitor directly.
16
14
PGND
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MPQ2918 – 4V - 40V, CURRENT MODE, SYNC, STEP-DOWN CONTROLLER
PIN FUNCTIONS (continued)
TSSOP-20 QFN-20
Name
Description
Pin #
Pin #
Bottom gate driver output. Connect BG to the gate of the synchronous
N-channel MOSFET.
17
15
BG
Switch node. SW is the reference for the VBST supply and high-current
returns for the bootstrapped switch.
18
19
16
17
SW
Top gate drive. TG drives the gate of the top N-channel synchronous
MOSFET. The TG driver draws power from the BST capacitor and returns
to SW, providing a true floating drive to the top N-channel MOSFET.
TG
Bootstrap. BST is the positive power supply for the internal, floating, high-
side MOSFET driver. Connect a bypass capacitor between BST and SW.
A diode from VCC1 to BST charges the BST capacitor when the low-side
switch is off.
20
18
BST
Exposed pad. The exposed pad is on the bottom side of the device. It is
not connected to SGND or PGND electrically. Connect the exposed pad to
SGND and PGND during PCB layout for better thermal performance.
Exposed
pad
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MPQ2918 – 4V - 40V, CURRENT MODE, SYNC, STEP-DOWN CONTROLLER
BLOCK DIAGRAM
Figure 1: Functional Block Diagram
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MPQ2918 – 4V - 40V, CURRENT MODE, SYNC, STEP-DOWN CONTROLLER
TIMING SEQUENCE
Figure 2: Time Sequence
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MPQ2918 – 4V - 40V, CURRENT MODE, SYNC, STEP-DOWN CONTROLLER
as the benchmark for the next clock cycle.
When the load increases and the DC value of
VCOMP is higher than VAAM, the operation mode
is discontinuous conduction mode (DCM) or
continuous conduction mode (CCM), which
have a constant switching frequency.
OPERATION
The MPQ2918 is a high-performance, step-
down, synchronous, DC/DC controller IC with a
wide input voltage range. It implements current-
mode control and programmable switching
frequency control architecture to regulate the
output voltage with external N-channel
MOSFETs.
The MPQ2918 senses the voltage at FB. The
difference between the FB voltage (VFB) and an
internal 0.8V reference (VREF) is amplified to
generate an error voltage on COMP. This is
used as the threshold for the current-sense
comparator with a slope compensation ramp.
Under normal-load conditions, the controller
operates in full pulse-width modulation (PWM)
mode (see Figure 3). At the beginning of each
oscillator cycle, the top gate driver is enabled.
The top gate turns on for a period determined
by the duty cycle. When the top gate turns off,
the bottom gate turns on after a dead time and
remains on until the next clock cycle begins.
Figure 3: Forced CCM and AAM
Floating Driver and Bootstrap Charging
The floating top gate driver is powered by an
external bootstrap capacitor (CBST), which is
refreshed when the high-side MOSFET (HS-
FET) turns off, typically. This floating driver has
its own under-voltage lockout (UVLO)
protection. This UVLO’s rising threshold is
3.05V with a hysteresis of 170mV.
There is an optional power-save mode for light-
load or no-load condition.
If the BST voltage is lower than the bootstrap
UVLO, the MPQ2918 enters constant-off-time
mode to ensure that the BST capacitor is high
enough to drive the HS-FET.
Advanced Asynchronous Mode (AAM)
The
MPQ2918
employs
advanced
asynchronous mode (AAM) functionality to
optimize efficiency during light-load or no-load
condition (see Figure 3). AAM is enabled when
CCM/AAM is at a low level by connecting an
appropriate resistor to SGND to ensure that the
AAM voltage (VAAM) is no less than 480mV. See
Equation (1):
VCC1 Regulator and VCC2 Power Supply
Both the top and bottom MOSFET drivers and
most of the internal circuitries are powered by
the VCC1 regulator. An internal, low dropout,
linear regulator supplies VCC1 power from VIN.
Connect a ≥1μF ceramic capacitor from VCC1
to PGND.
VAAM (mV) = IAAM (μA) x RAAM (kΩ)
(1)
Where IAAM is the CCM/AAM output current.
If VCC2 is left open or connected to a voltage
less than 4.7V, an internal 5V regulator supplies
power to VCC1 from VIN. If VCC2 is greater
than 4.7V, the internal regulator that supplies
power to VCC1 from VCC2 is triggered. If
VCC2 is between 4.7V and 5V, the 5V regulator
is in dropout, and VCC1 approximately equals
VCC2. Using the VCC2 power supply allows the
VCC1 power to be derived from a high-
efficiency external source, such as one of the
MPQ2918’s switching regulator outputs.
AAM is disabled when CCM/AAM is floating or
connected to VCC1. Calculate the CCM/AAM
output current (IAAM) with Equation (2):
IAAM (μA) = 600 (mV) / RFREQ (kΩ)
(2)
If AAM is enabled, the MPQ2918 first enters
non-synchronous operation for as long as the
inductor current approaches zero at light load. If
the load decreases further to make the COMP
voltage (VCOMP) drop below the CCM/AAM
voltage (VAAM), the MPQ2918 enters AAM. In
AAM, the internal clock resets whenever VCOMP
crosses over VAAM. The crossover time is taken
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MPQ2918 – 4V - 40V, CURRENT MODE, SYNC, STEP-DOWN CONTROLLER
Power Good (PG) Function
Error Amplifier (EA)
The error amplifier (EA) compares VFB with the
internal 0.8V reference and outputs a current
proportional to the difference between the two
input voltages. This output current is used to
charge or discharge the external compensation
network to form VCOMP, which is used to control
the power MOSFET current. Adjusting the
compensation network from COMP to SGND
optimizes the control loop for good stability or
fast transient response.
The MPQ2918 includes an open-drain power
good (PG) output that indicates whether the
regulator’s output is within ±10% of its nominal
value. When the output voltage falls outside of
this range, the PG output is pulled low. PG
should be connected to a voltage source no
more than 5V through a resistor (e.g.: 100kΩ).
The PG delay time is 28µs.
Soft Start (SS)
Soft start (SS) is implemented to prevent the
converter output voltage from overshooting
during start-up. When the chip starts up, the
internal circuitry generates a soft-start voltage
that ramps up from 0V to 1.2V. When it is lower
than REF, SS overrides REF, so the error
amplifier uses SS as the reference. When SS is
higher than REF, REF regains control.
Current Limit Function
The MPQ2918 has three fixed current limit
options: 25mV, when ILIM is connected to
SGND; 50mV, when ILIM is connected to VCC1;
and 75mV, when ILIM is floating.
When the peak value of the inductor current
exceeds the set current-limit threshold, the
output voltage begins dropping until FB is
37.5% below the reference. The MPQ2918
enters hiccup mode to restart the part
periodically. The frequency is lowered when FB
is below 0.4V. This protection mode is
especially useful when the output is dead-
shorted to ground. The average short-circuit
current is reduced greatly to alleviate thermal
issues. The MPQ2918 exits hiccup mode once
the over-current condition is removed.
An external capacitor connected from SS to
SGND is charged from an internal 4μA current
source, producing a ramped voltage. The soft-
start time (tSS) is set by the external SS
capacitor and can be calculated by Equation (3):
CSS
nF
VREF
μA
V
(3)
tSS
ms
ISS
Where CSS is the external SS capacitor, VREF is
the internal reference voltage (0.8V), and ISS is
the 4μA SS charge current. There is no internal
SS capacitor. SS is reset when a fault
protection other than over-voltage protection
(OVP) occurs.
Low Dropout Operation
In low dropout mode, the MPQ2918 is designed
to operate in high-side fully on mode for as long
as the voltage difference across BST - SW is
greater than 3.05V, improving dropout. When
the voltage from BST to SW drops below 3.05V,
a UVLO circuit turns off the HS-FET. At the
same time, the low-side MOSFET (LS-FET)
turns on to refresh the charge on the BST
capacitor. After the BST capacitor voltage is re-
charged, the HS-FET turns on again to regulate
the output. Since the supply current sourced
from the BST capacitor is low, the HS-FET can
remain on for more switching cycles than are
required to refresh the BST capacitor,
increasing the effective duty cycle of the
switching regulator. Low dropout operation
makes the MPQ2918 suitable for automotive
cold-crank applications.
Output Over-Voltage Protection (OVP)
The output over-voltage is monitored by VFB. If
VFB is typically 15% higher than the reference,
the MPQ2918 enters discharge mode. The HS-
FET turns off, and the LS-FET turns on. The
LS-FET remains on until the reverse current
limit is triggered. The LS-FET then turns off,
and the inductor current increases to 0. The LS-
FET is turned on again after ZCD is triggered.
The MPQ2918 works in discharge mode until
the over-voltage condition is cleared.
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MPQ2918 – 4V - 40V, CURRENT MODE, SYNC, STEP-DOWN CONTROLLER
Thermal Protection
EN/SYNC Control
The MPQ2918 has
a
dedicated enable
Thermal protection prevents damage to the IC
from excessive temperatures. The die
temperature is monitored internally until the
thermal limit is reached. When the silicon die
temperature is higher than 170°C, the entire
chip shuts down. When the temperature is
lower than its lower threshold (typically 20°C),
the chip is enabled again.
(EN/SYNC) control that uses a bandgap-
generated precision threshold of 1.22V. By
pulling EN/SYNC high or low, the IC can be
enabled or disabled. To disable the part,
EN/SYNC must be pulled low for at least 40µs.
Tie EN/SYNC to VIN through a resistor divider
(R16 and R17) to program the VIN start-up
threshold (see Figure 4). The EN/SYNC
threshold is 1.09V (falling edge), so the VIN
UVLO threshold is 1.09V x (1 + R16/R17).
Start-Up and Shutdown
If both VIN and EN/SYNC are higher than their
respective thresholds, the chip starts up. The
reference block starts first, generating stable
reference voltages and currents. The internal
regulator is then enabled. The regulator
provides a stable supply for the remaining
circuitries.
Otherwise, if VIN ≤ 52V, EN/SYNC can be
connected to VIN directly. If VIN ≥ 52V, a ≥50kꢀ
pull-up resistor is needed to prevent EN/SYNC
from breaking down.
Three events can shut down the chip:
EN/SYNC low, VIN low, and thermal shutdown.
During the shutdown procedure, the signal path
is blocked first to avoid any fault triggering.
VCOMP and the internal supply rail are then
pulled down. The floating driver is not subject to
this shutdown command.
Pre-Bias Start-Up
Figure 4: EN/SYNC Resistor Divider
Synchronize
If SS is less than FB at start-up, the output has
a pre-bias voltage, and neither TG nor BG is
turned on until SS is greater than FB.
The MPQ2918 can be synchronized to an
external clock ranging from 100kHz up to
1000kHz through EN/SYNC. The internal clock
rising edge is synchronized to the external clock
rising edge. The pulse width (both on and off) of
the external clock signal should be no less than
100ns.
Under-Voltage Lockout (UVLO)
Under-voltage lockout (UVLO) is implemented
to protect the chip from operating at an
insufficient input supply voltage. The MPQ2918
UVLO rising threshold is about 4.5V, while its
falling threshold is a consistent 3.7V.
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MPQ2918 – 4V - 40V, CURRENT MODE, SYNC, STEP-DOWN CONTROLLER
Programmable Switching Frequency
APPLICATION INFORMATION
Setting the Output Voltage
Consider different variables when choosing the
switching frequency. high frequency
A
The external resistor divider is used to set the
output voltage (see Figure 5).
increases switching losses and gate charge
losses, while a low frequency requires more
inductance and capacitance, resulting in larger
real estate and higher cost. Setting the
switching frequency is a trade-off between
power loss and passive component size. In
noise-sensitive applications, the switching
frequency should be out of a sensitive
frequency band.
Figure 5: External Resistor Divider
The MPQ2918’s frequency can be programmed
from 100kHz to 1000kHz with a resistor from
FREQ to SGND (see Table 2). The value of
RFREQ for a given operating frequency can be
calculated with Equation (6):
If R8 is known, then R9 can be calculated with
Equation (4):
R8
VOUT
(4)
R9
1
20000
0.8V
(6)
RFREQ(k)
1
fs(kHz)
Table 1 lists the recommended feedback
resistor values for common output voltages.
Table 2: Frequency vs. Resistor
Table 1: Resistor Selection for Common Output
Voltages
Resistor (kΩ)
Frequency (kHz)
65
45.3
39
300
430
V
OUT (V)
3.3
5
R8 (kΩ)
37.4 (1%)
63.4 (1%)
169 (1%)
R9 (kΩ)
12 (1%)
12 (1%)
12 (1%)
500
19
1000
12
VCC Regulator Connection
Setting Current Sensing
VCC1 can be powered from both VIN and VCC2.
If connecting VCC2 to an external power supply
to improve the overall efficiency, VCC2 should
be larger than 4.7V but smaller than 12V (see
Figure 6).
The MPQ2918 has three fixed current limit
options: 25mV, when ILIM is connected to
SGND; 50mV, when ILIM is connected to VCC1;
and 75mV, when ILIM is floating. Ensure that
the application can deliver a full load of current
over the full operating temperature range when
setting ILIM.
The current sense resistor (RSENSE) monitors the
inductor current. Its value is chosen based on
the current limit threshold. The relationship
between the peak inductor current (Ipk) and
RSENSE can be calculated with Equation (5):
V
ILIMIT
Ipk
(5)
RSENSE
A higher RSENSE value increases the power loss
across it. Considering the output current,
Figure 6: Internal Circuitry of VCC2
efficiency,
and
ILIM
threshold,
the
recommended value for RSENSE is between 7mꢀ
and 50mꢀ.
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MPQ2918 – 4V - 40V, CURRENT MODE, SYNC, STEP-DOWN CONTROLLER
If VOUT is higher than 4.7V but less than 12V,
VCC2 can be connected to VOUT directly (see
Figure 7).
current capability. The RMS value of the ripple
current flowing through the input capacitor can
be calculated with Equation (9):
V
VOUT
IRMS =ILOAD OUT (1-
)
(9)
V
V
IN
IN
The worst-case condition occurs at VIN = 2VOUT
,
shown in Equation (10):
IRMS = ILOAD/2
(10)
The input capacitor must be capable of
handling this ripple current.
Output Capacitor Selection
The output capacitor impedance should be low
at the switching frequency. The output voltage
ripple can be estimated with Equation (11):
Figure 7: Configuration of VCC2 Connecting to
VOUT
VOUT
VOUT
1
(11)
ꢁVOUT
1
RESR
Selecting the Inductor
fS L
V
8 fS CO
IN
An inductor with a DC current rating at least
25% higher than the maximum load current is
recommended for most applications. A larger-
value inductor results in less ripple current and
a lower output ripple voltage. However, the
larger-value inductor also has a larger physical
size, higher series resistance, and lower
saturation current. Choose the inductor ripple
current to be approximately 30% of the
maximum load current. The inductance value
can then be calculated with Equation (7):
Where CO is the output capacitance value, and
RESR is the equivalent series resistance (ESR)
value of the output capacitor.
For
applications,
tantalum
or
the
electrolytic
ESR dominates
capacitor
the
impedance at the switching frequency. The
output voltage ripple can be approximated with
Equation (12):
VOUT
VOUT
(12)
ꢁVOUT
1
R
ESR
fS L
V
IN
VOUT (V - VOUT
)
IN
(7)
L
V ꢁIL fS
Power MOSFET Selection
IN
Two N-channel MOSFETs must be selected for
the controller: one for the high-side switch, and
one for the low-side switch.
Where VOUT is the output voltage, VIN is the
input voltage, fS is the 300kHz switching
frequency, and ∆IL is the peak-to-peak inductor
ripple current.
The driver level of the HS-FET and LS-FET is
5V, so the threshold voltage (Vth) of the
selected MOSFETs must be no higher than this
value.
The maximum inductor peak current can be
calculated with Equation (8):
ꢁIL
(8)
IL(MAX)=ILOAD
+
The input voltage (VDS), continuous drain
current (ID), on resistance (RDS(ON)), total gate
charge (Qg), and thermal-related parameters
should be considered when choosing the power
MOSFETs.
2
Where ILOAD is the load current.
Selecting the Input Capacitor
Since the input capacitor absorbs the input
switching current, it requires an adequate ripple
current rating. The selection of the input
capacitor is based mainly on its maximum ripple
V
DS of the chosen MOSFETs should exceed the
maximum applied voltage between the drain
and source in the application, which is VIN(MAX)
plus additional rings on the switch node.
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MPQ2918 – 4V - 40V, CURRENT MODE, SYNC, STEP-DOWN CONTROLLER
The MOSFET’s power dissipations can be
calculated with Equation (13) and Equation (14):
VCC1
External BST diode
IN4148
VOUT
RBST
P =IOUT2 RON-HS
+
HS
BST
V
IN
VCC1
1
CBST
L
(13)
V IOUT t +t f
f
IN
r
SW
2
VOUT
SW
+Qg-HS fSW Vdriver
COUT
VOUT
P =IOUT2 RON-LS 1
+
Figure 8: External Bootstrap Diode and Resistor
LS
V
IN
The recommended external BST diode is
IN4148, and the recommended BST capacitor
value is 0.1µF to 1μF.
Qg-LS fSW Vdriver
+
(14)
VDROP IOUT tdead1+tdead2 f
SW
A resistor in series with the BST capacitor (RBST
can reduce the SW rising rate and voltage
spikes. This helps enhance EMI performance
and reduce voltage stress at a high VIN. A
higher resistance is better for SW spike
reduction but compromises efficiency. To make
a tradeoff between EMI and efficiency, a ≤20ꢀ
)
Where RON-HS and RON-LS are the on resistance
of the HS-FET and LS-FET, tr and tf are the
rising and falling time of the switch, Qg-HS and
Qg-LS are the total gate charge of the HS-FET
and LS-FET, Vdriver is the gate driver voltage
(which is provided by VCC1), VDROP is the LS-
FET body diode forward voltage, tdead1 is the
dead time between the HS-FET turning off and
the LS-FET turning on, and tdead2 is the dead
time between the LS-FET turning off and the
HS-FET turning on.
RBST is recommended.
Compensation Components
The MPQ2918 employs current-mode control
for easy compensation and fast transient
response. COMP is the output of the internal
error amplifier and controls system stability and
transient response. A series resistor-capacitor
(R-C) combination sets a pole zero combination
to control the control system’s characteristics
(see Figure 9). The DC gain of the voltage
feedback loop can be calculated with Equation
(15):
Ensure that the thermal caused by the power
loss on the MOSFETs does not exceed the
allowed maximum thermal of the selected
MOSFETs.
Schottky Selection
The diode between SW and PGND (shown as
D2 in Figure 12) is used to absorb spikes, store
charges during dead time, and protect the body
diode of the LS-FET. Considering the size and
power loss during the dead time, a 1 - 3A
Schottky diode is recommended.
VFB
(15)
AVDC RLOAD GCS AO
VOUT
Where AO is the error amplifier voltage gain
(3000V/V), GCS is the current sense
transconductance 1/(12xRSENSE) (A/V), and
BST Charge Diode and Resistor Selection
An external BST diode can enhance the
efficiency of the regulator when the duty cycle is
high. A power supply between 2.5V and 5V can
be used to power the external bootstrap diode.
VCC1 or VOUT is recommended to be this power
supply in the circuit (see Figure 8).
R
LOAD is the load resistor value.
COMP
C6
C7
R5
Figure 9: Compensation Network
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MPQ2918 – 4V - 40V, CURRENT MODE, SYNC, STEP-DOWN CONTROLLER
The system has two important poles: one from
Follow the steps below to design the
compensation.
the compensation capacitor (C6) and the output
resistor of the error amplifier, and the other from
the output capacitor and the load resistor (see
Figure 9). These poles can be calculated with
Equation (16) and Equation (17):
1. Choose R5 to set the desired crossover
frequency with Equation (21):
2π Co fC VOUT
(21)
R5
Gm GCS
VFB
Gm
(16)
fP1
2π C6 AO
Where fC is the desired crossover frequency.
2. Choose C6 to achieve the desired phase
margin. For applications with typical
inductor values, set the compensation zero
(fZ1) <0.25 x fC to provide a sufficient phase
margin. C6 is then calculated with Equation
(22):
1
(17)
fP2
Gm
2π CoRLOAD
Where
is
the
error
amplifier
transconductance (500μA/V), and Co is the
output capacitor.
4
The system has one important zero due to the
compensation capacitor and the compensation
resistor (R5), which can be calculated with
Equation (18):
(22)
C6
2π R5 fC
3. C7 is required if the ESR zero of the output
capacitor is located at <0.5 x fSW, or
Equation (23) is valid:
1
(18)
fZ1
2πC6R5
fSW
2
1
(23)
The system may have another significant zero if
the output capacitor has a large capacitance or
high ESR value and can be calculated with
Equation (19):
2π CoRESR
If this is the case, use C7 to set the pole (fP3)
at the location of the ESR zero. Determine
C7 with Equation (24):
1
(19)
fESR
CoRESR
2π CoRESR
(24)
C7
R5
In this case, a third pole set by the
compensation capacitor (C7) and the
compensation resistor can compensate for the
effect of the ESR zero. This pole is calculated
with Equation (20):
1
(20)
fP3
2πC7R5
The goal of the compensation design is to
shape the converter transfer function for a
desired loop gain. The system crossover
frequency where the feedback loop has unity
gain is important, since lower crossover
frequencies result in slower line and load
transient responses, and higher crossover
frequencies lead to system instability. Set the
crossover frequency to ~0.1 x fSW.
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MPQ2918 – 4V - 40V, CURRENT MODE, SYNC, STEP-DOWN CONTROLLER
PCB Layout Guidelines
Efficient PCB layout is critical for stable
operation, especially for the input capacitor
placement. A four-layer layout is strongly
recommended to achieve better thermal
performance. For best results, refer to Figure
10 and Figure 11 and follow the guidelines
below.
1. Place the MOSFETs as close as possible
to the device.
Top Layer
Inner Layer 1
Inner Layer 2
2. Make the sense lines (the red lines in Inner
Layer 2 of Figure 10 and Figure 11) run
close together using a Kelvin connection to
reduce the line drop error.
3. Use a large ground plane to connect to
PGND directly.
4. Add vias near PGND if the bottom layer is a
ground plane.
5. Ensure that the high-current paths at
PGND and VIN have short, direct, and wide
traces.
6. Place the ceramic input capacitor,
especially the small package size (0603)
input bypass capacitor, as close to IN and
PGND as possible to minimize high-
frequency noise.
7. Keep the connection of the input capacitor
and IN as short and wide as possible.
8. Place the VCC1 capacitor as close to
VCC1 and SGND as possible.
9. Route SW and BST away from sensitive
analog areas such as FB.
10. Place the feedback resistors close to the
chip to ensure that the trace which
connects to FB is as short as possible.
11. Use multiple vias to connect the power
planes to the internal layers.
Bottom Layer
Figure 10: Recommended PCB Layout for
TSSOP Package (6)
NOTE:
6) The recommended PCB layout is based on Figure 12.
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MPQ2918 – 4V - 40V, CURRENT MODE, SYNC, STEP-DOWN CONTROLLER
Top Layer
Inner Layer 1
Inner Layer 2
Bottom Layer
Figure 11: Recommended PCB Layout for QFN
Package (7)
NOTE:
7) The recommended PCB layout is based on Figure 14.
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MPQ2918 – 4V - 40V, CURRENT MODE, SYNC, STEP-DOWN CONTROLLER
TYPICAL APPLICATION CIRCUITS
U1
R11
M1
VIN
6V-40V
0Ω
R13
2.2Ω
19
20
1
TG
IN
D1
1N4148WS
C1C
C1B
C1A
47µF
63V
C1
0.47µF
100V
4.7µF
4.7µF
BST
100V
100V
GND
VCC1
C8
L1
4.7µH
VOUT
R7
0.007Ω
10
0.1µF
16V
VOUT
FREQ
VCC1
5V/7A
18
17
PGND
SW
BG
4
VCC1
R1
R14
10
C11
220pF
C2
1µF
16V
PG
R18
R2
D2
R12
M2
MPQ291GF
10Ω
45.3kΩ
R19 R20
0Ω
100kΩ
DFLS
160
0Ω 0Ω
11
COUT1
68µF
COUT2
68µF
PG
COUT3
22µF
COUT4
NS
C9
NS
3
C3
4.7µF
16V
R8
63.4kΩ
VCC2
R10
16V
16V
16V
15
14
8
R3
0Ω
ENSE+
ENSE-
FB
VCC2
NS
C10
NS
SYNCO
VOUT
13
SYNCO
R15
100kΩ
2
12
6
EN/SYNC
ILIMIT
SS
VIN
R9
12kΩ
3
1
R16
100kΩ
VCC1
9
CCM/AAM
JP2
C7
10nF
EN/SYNC
R17
NS
C6
680pF
C7
NS
JP1
1
3
2
R5
51kΩ
VCC1
CCM
AAM
R4
45.3kΩ
C4
NS
Note: Thermal pad should connect to PGND and SGND
Figure 12: 5V Output Application Circuit for TSSOP Package
R11
M1
U1
IN
VIN
16V-40V
0Ω
19
20
1
TG
D1
1N4148WS
C1C
C1B
C1A
47µF
63V
C1
R13
0.47µF
100V
4.7µF
4.7µF
BST
100V
100V
GND
VCC1
C8
L1
15µH
2.2Ω
VOUT
R7
0.007Ω
10
0.1µF
16V
VOUT
FREQ
VCC1
12V/7A
18
17
PGND
R1
SW
BG
4
VCC1
R14
10Ω
C11
C2
1µF
16V
PG
R18
R2
D2
R12
M2
MPQ2918GF
10Ω
45.3kΩ
R19 R20
0Ω
100kΩ
DFLS
160
0Ω 0Ω
11
COUT1 COUT2
PG
22µF
220pF
220µF
16V
C9
NS
3
C3
4.7µF
16V
R10
0Ω
R8
VCC2
16V
15
14
8
R3
0Ω
SENSE+
SENSE-
FB
VCC2
169kΩ
C10
SYNCO
VOUT
150pF
13
SYNCO
R15
100kΩ
2
12
6
EN/SYNC
ILIMIT
SS
VIN
R9
12kΩ
3
1
R16
100kΩ
VCC1
9
CCM/AAM
JP2
C7
10nF
EN/SYNC
R17
NS
C6
220pF
C7
82pF
JP1
1
3
2
R5
10kΩ
VCC1
CCM
AAM
R4
45.3kΩ
C4
NS
Note: Thermal pad should connect to PGND and SGND
Figure 13: 12V Output Application Circuit for TSSOP Package
MPQ2918 Rev. 1.01
8/17/2017
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
28
MPQ2918 – 4V - 40V, CURRENT MODE, SYNC, STEP-DOWN CONTROLLER
TYPICAL APPLICATION CIRCUITS (continued)
PGND
AGND
R11
0Ω
M1
U1
IN
VIN
17
18
6V-40V
19
C1
TG
D1
C1C
C1B
C1A
47µF
63V
1N4148WS
4.7µF 0.47µF
4.7µF
GND
BST
VCC1
100V
100V
8
100V
R13
0Ω
C8
0.1µF
16V
VOUT
L1
R7
0.007Ω
VOUT
4.7µH
FREQ
5V/7A
16
15
13
SW
BG
R1
45.3kΩ
2
R14
10Ω
VCC1
MPQ2918GL
PG
VCC1
C2
1µF
16V
R18
R2
M2
R12
D2
10Ω
0Ω
100kΩ
R19 R20
C11
DFLS160
COUT1
68µF
COUT2
68µF
COUT3
22µF
COUT4
9
PG
0Ω
0Ω
NS
220pF
1
C3
4.7µF
16V
C9
NS
16V
16V
16V
VCC2
VCC2
R8 R10
R3
NS
NS
SENSE+
SENSE-
FB
63.4kΩ
SYNCO
12
6
C10
NS
VOUT
11
SYNCO
20
R15
EN/SYNC
VIN
10
4
3 2 1
ILIMIT
SS
100kΩ
R9
12kΩ
R16
VCC1
7
CCM/AAM
JP2
100kΩ
C5
10nF
EN/SYNC
R17
NS
C6
JP1
680pF
1
3
2
C7
NS
VCC1
R5
51kΩ
CCM
AAM
R4
45.3kΩ
Note: Thermal pad should connect to PGND and SGND
C4
NS
Figure 14: 5V Output Application Circuit for QFN Package
PGND
AGND
R11
0Ω
M1
U1
IN
VIN
17
18
16V-40V
19
C1
TG
D1
C1C
C1B
C1A
47µF
63V
1N4148WS
4.7µF 0.47µF
4.7µF
GND
BST
VCC1
100V
100V
8
100V
R13
0Ω
C8
0.1µF
16V
VOUT
L1
R7
0.007Ω
VOUT
15µH
FREQ
12V/7A
16
15
13
SW
BG
R1
45.3kΩ
2
R14
10Ω
VCC1
MPQ2918GL
PG
VCC1
C2
1µF
16V
R18
R2
M2
R12
0Ω
D2
10Ω
100kΩ
C11
R19 R20
DFLS160
COUT1
220µF
16V
COUT2
68µF
16V
9
PG
0Ω
0Ω
220pF
1
C3
4.7µF
16V
C9
NS
VCC2
VCC2
R8 R10
R3
NS
0Ω
SENSE+
SENSE-
FB
169kΩ
12
6
SYNCO
C10
VOUT
11
SYNCO
150pF
20
R15
100kΩ
EN/SYNC
VIN
10
4
3 2 1
JP2
ILIMIT
SS
R9
12kΩ
R16
VCC1
7
CCM/AAM
100kΩ
C5
10nF
EN/SYNC
R17
NS
C6
JP1
220pF
1
3
2
C7
82pF
VCC1
R5
10kΩ
CCM
AAM
R4
45.3kΩ
Note: Thermal pad should connect to PGND and SGND
C4
NS
Figure 15: 12V Output Application Circuit for QFN Package
MPQ2918 Rev. 1.01
8/17/2017
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
29
MPQ2918 – 4V - 40V, CURRENT MODE, SYNC, STEP-DOWN CONTROLLER
PACKAGE INFORMATION
TSSOP-20 EP
4.40
TYP
0.40
TYP
0.65
BSC
6.40
6.60
20
11
1.60
TYP
3.20
TYP
4.30
4.50
6.20
6.60
5.80
TYP
PIN 1 ID
1
10
TOP VIEW
RECOMMENDED LAND PATTERN
0.80
1.05
1.20 MAX
0.09
0.20
SEATING PLANE
0.00
0.15
0.19
0.30
0.65 BSC
SEE DETAIL"A"
SIDE VIEW
FRONT VIEW
GAUGE PLANE
0.25 BSC
3.80
4.30
0.45
0.75
0o-8o
DETAIL “A”
2.60
3.10
NOTE:
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
PROTRUSION OR GATE BURR.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH
OR PROTRUSION.
4) LEAD COPLANARITY(BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.10 MILLIMETERS MAX.
5) DRAWING CONFORMS TO JEDEC MO-153, VARIATION ACT.
6) DRAWING IS NOT TO SCALE.
BOTTOM VIEW
MPQ2918 Rev. 1.01
8/17/2017
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
30
MPQ2918 – 4V - 40V, CURRENT MODE, SYNC, STEP-DOWN CONTROLLER
PACKAGE INFORMATION (continued)
QFN-20 (3mmx4mm)
Non-Wettable Flank
PIN 1 ID
SEE DETAIL A
PIN 1 ID
MARKING
PIN 1 ID
INDEX AREA
TOP VIEW
BOTTOM VIEW
PIN 1 ID OPTION B
R0.20 TYP.
PIN 1 ID OPTION A
0.30x45° TYP.
DETAIL A
SIDE VIEW
NOTE:
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) EXPOSED PADDLE SIZE DOES NOT INCLUDE
MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10
MILLIMETERS MAX.
4) JEDEC REFERENCE IS MO-220.
5) DRAWING IS NOT TO SCALE.
RECOMMENDED LAND PATTERN
MPQ2918 Rev. 1.01
8/17/2017
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
31
MPQ2918 – 4V - 40V, CURRENT MODE, SYNC, STEP-DOWN CONTROLLER
PACKAGE INFORMATION (continued)
QFN-20 (3mmx4mm)
Wettable Flank
PIN 1 ID
0.30x45° TYP.
PIN 1 ID
MARKING
PIN 1 ID
INDEX AREA
TOP VIEW
BOTTOM VIEW
SIDE VIEW
SECTION A-A
NOTE:
1) THE LEAD SIDE IS WETTABLE.
2) ALL DIMENSIONS ARE IN MILLIMETERS.
3) EXPOSED PADDLE SIZE DOES NOT INCLUDE
MOLD FLASH.
4) LEAD COPLANARITY SHALL BE 0.08
MILLIMETERS MAX.
5) JEDEC REFERENCE IS MO-220.
6) DRAWING IS NOT TO SCALE.
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MPQ2918 Rev. 1.01
8/17/2017
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
32
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