MSFS6 [MSI]
Selectable Lowpass/Bandpass Filter;型号: | MSFS6 |
厂家: | Mixed Signal Integration |
描述: | Selectable Lowpass/Bandpass Filter |
文件: | 总8页 (文件大小:96K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
03/ 2001
S e l e ct a b l e Lo w p a s s / B a n d p a s s F i l t e r
D a t a S h e e t
Fe a t u r e s
D e s cr i p t i o n
Six Filter Types In One Package
No External Components
Switched-Capacitor Filters
Low Power Operation
Low Voltage Operation
Input Multiplexor
Adjustable Gain 0, 10 or 20 dB
Small Package Size
Low Cost
The selectable lowpass/ bandpass filter IC Is a
CMOS chip that can be configured for either a
lowpass or a bandpass filte r. The lowpass
response can be a 7 pole Butterworth, Elliptic
or Bessel filter. The band pass response can be
a six pole full, third or sixth octave bandpass
filter. The device uses switched-capacitor fil-
ters and no external components (except for
decoupling capacitors) are required, Only an
external CMOS level clock is needed.
On Chip Power Save Pin
ANSI Compatible Bandpass
A four input multiplexor and externally selecta-
ble gain setting pin, along with a power down
and clock to corner ratio select pin are included
in the 16 pin version. An 8 pin version is also
available for PC board area savings. Typical
current consumption is as low as 200 uA and
the minimum operating voltage is 2.7 volts,
making the device ideal for portable applica-
tions. MSFS3, MSFS4 and MSFS6 are low cur-
rent, lower frequency versions.
Ap p l i ca t i o n s
Spectrum Analyzers
General Purpose Systems
Portable Systems
Anti-Alias Filters
Reconstruction Filters
Telecommunications
Tracking Filters
Harmonic Analysis
Noise Analysis
Data Communication
Wireless Applications
Lo w p a s s R e s p o n s e s
Ba n d p a s s R e s p o n s e s
Web Site “www.mix-sig.com”
© 2001 Mixed Signal Integration 1
03/ 2001
S e l e ct a b l e Lo w p a s s / B a n d p a s s F i l t e r
D a t a S h e e t
Ele ctr ica l Ch a r a cte r istics_______
o
(VDD = +5.0V, T = 25 C)
PARAMETER
DC Specifications
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Operating Voltage
Supply Current
Supply Current
Power Down Current
AC Specifications
Gain
VDD
IDD
IDD
IPD
2.7
5
1
5.5
1.5
V
MSFS1, MSFS2, MSFS5
MSFS3, MSFS4, MSFS6
MSFS2, MSFS4, PD = 1
mA
uA
uA
200
150
300
Av
-0.5
4
0
0.5
dB
uVrms
dB
Noise
Distortion
To 1/ 2 Sample
A weighted
1 kHz
250
-72
4.5
1
THD
Signal Swing
Input Impedance
Output Drive
V p-p
Mohm
mA
ZIN
Io
1
Output Impedance
Output Capacitive Load
Clock to Corner
Clock to Corner
Clock to Corner
Clock to Corner
Center Frequency Range
Center Frequency Range
Ripple
Zo
500
25
ohm
pF
MSFS5, MSFS6
MSFS1, MSFS3
99
49.5
99
100
50
101
50.5
101
50.5
20
MSFS2, MSFS4, Fo=1
MSFS2, MSFS4, Fo=0
MSFS1, MSFS2, MSFS5 0.001
MSFS3, MSFS4, MSFS6 0.001
100
50
49.5
Fo
Fo
kHz
kHz
3
Elliptic Lowpass
Full Octave
Third Octave
0.2
0.2
0.2
0.2
dB
dB
dB
dB
Sixth Octave
Stop Band Rejection
Elliptic Lowpass
Bessel Lowpass
40 dB Bandwidth
Full Octave
80
65
dB
dB
Normalized Fo
Normalized Fo
Normalized Fo
0.3
0.6
3
1.67
1.32
Third Octave
Sixth Octave
0.76
Bandpass Q
Full Octave Q
Third Octave
Sixth Octave
Q
Q
Q
1.5
4.5
9
Web Site “www.mix-sig.com”
© 2001 Mixed Signal Integration 2
03/ 2001
S e l e ct a b l e Lo w p a s s / B a n d p a s s F i l t e r
D a t a S h e e t
Filte r Se le ctio n ________________
G a in a n d Fr e q u e n cy Se le ctio n ____
The filter type is selected using the two filter select pins,
TYPE and FSEL, FSEL is a CMOS level pin that selects
lowpass or bandpass (lowpass = 0, bandpass = 1). TYPE
Is a tertiary control pin that selects the filter response.
State 0 is VSS, state 1 is GND and state 2 is VDD.
The Gain control pin G is a tertiary control pin where
state 0 is VSS, state 1 is GND level and state 2 is VDD.
G
0
Gain
OdB
1
2
10dB
20dB
TYPE
Lowpass
Butterworth
Bessel
Bandpass
0
1
2
Full Octave
Third Octave
Sixth Octave
The frequency control pin F0 is a CMOS level pin where
high is clock to corner of 100 to 1 (200 to 1 for Bessel)
and low is clock to corner of 50 to 1 (100 to 1 for Bessel).
Elliptic
P in De scr ip tio n ________________
P i n Co n f i g u r a t i o n
1. TYPE
2. S2
3. CLK
4. G
Filter Response Select Pin.
Input Multiiplexor Select Pin
Clock Input
FSEL
OUT
TYPE
CLK
IN
Gain Select Pin
8 P in
5. VDD
Positive Power Supply, Typically 2.5
Volts for Split Supply 5.0 Volts for
Single SuppLy
Power Down Pin, CMOS level,
Hi = Power Down
GND
VSS
VDD
6. PD
5
7, VSS
Negative Power Supply, Typically -2.5
Volts for Split Supply. 0 Volts for Single
Supply
16
8. F0
9. GND
Clock to Corner Select Pin
GND Pin, OV for Split Supplies
2.5 Volts Typical for Single Supply
Input 1, Select Code 00
Input 2, Select Code 01
Input 3, Select Code 10
Input 4, Select Code 11
Selects Filter.
TYPE
S2
S1
15
14
13
OUT
FSEL
CLK
10. IN1
11. IN2
12. IN3
13. IN4
14. FSEL
G
IN4
IN3
VDD
12
11
PD
IN2
IN1
O = Low Pass, 1 = Bandpass
Filter Output
Input Multiplexor Select Pin
VSS
1 6 P in
10
9
15. Out
16. S1
F0
GND
Web Site “www.mix-sig.com”
© 2001 Mixed Signal Integration 3
03/ 2001
S e l e ct a b l e Lo w p a s s / B a n d p a s s F i l t e r
D a t a S h e e t
VCC
5V
C1
R1
R2
47kohm
47kohm
100nF
U1
100nF
C6
FSEL
OUT
TYPE
CLK
IN
LOWPASS_BANDPASS
FILTER_OUTPUT
FILTER_INPUT
GND
VSS
VDD
MSFS1_3_5_6
BU_BE_EL_FL_3_6
V1
300kHz 5V
100nF
C2
Ty p ica l Ap p lica tio n -Sin g le Su p p ly O p e r a tio n
Web Site “www.mix-sig.com”
© 2001 Mixed Signal Integration 4
03/ 2001
S e l e ct a b l e Lo w p a s s / B a n d p a s s F i l t e r
D a t a S h e e t
VCC
5V
C1
R1
R2
100nF
47kohm
47kohm
X1
TYPE
S2
S1
BU_BE_EL_FL_3_6
SELECT3_4
SELECT_1_2
OUT
FSEL
IN4
FILTER_OUTPUT
LOWPASS_BANDPASS
INPUT_4
CLK
G
100nF
C3
C4
C5
C6
0_10_20dB
POWERDOWN
50_100
VDD
PD
IN3
MSFS2_4
100nF
100nF
100nF
IN2
INPUT_3
INPUT_2
INPUT_1
VSS
FO
IN1
GND
100nF
C2
V1
1MHz 5V
Ty p ica l Ap p lica tio n -Sin g le Su p p ly O p e r a tio n
Web Site “www.mix-sig.com”
© 2001 Mixed Signal Integration 5
03/ 2001
S e l e ct a b l e Lo w p a s s / B a n d p a s s F i l t e r
D a t a S h e e t
VDD
VSS
2.5V
-2.5V
U1
FSEL
OUT
TYPE
CLK
IN
LOWPASS_BANDPASS
FILTER_OUTPUT
FILTER_INPUT
GND
VSS
VDD
MSFS1_3_5_6
BU_BE_EL_FL_3_6
100nF
100nF
C2
C1
P2V5_N2V5_300kHz
Ty p ica l Ap p lica tio n -Du a l Su p p ly O p e r a tio n
Web Site “www.mix-sig.com”
© 2001 Mixed Signal Integration 6
03/ 2001
S e l e ct a b l e Lo w p a s s / B a n d p a s s F i l t e r
D a t a S h e e t
VDD
2.5V
VSS
-2.5V
C1
100nF
X1
TYPE
S1
BU_BE_EL_FL_3_6
SELECT3_4
SELECT_1_2
S2
CLK
G
OUT
FSEL
IN4
FILTER_OUTPUT
LOWPASS_BANDPASS
INPUT_4
0_10_20dB
POWERDOWN
50_100
VDD
PD
IN3
MSFS2_4
IN2
INPUT_3
INPUT_2
INPUT_1
VSS
FO
IN1
GND
P2V5_N2V5_300kHz
C2
100nF
Ty p ica l Ap p lica tio n -Du a l Su p p ly O p e r a tio n
Web Site “www.mix-sig.com”
© 2001 Mixed Signal Integration 7
03/ 2001
S e l e ct a b l e Lo w p a s s / B a n d p a s s F i l t e r
D a t a S h e e t
Blo ck Dia g r a m ________________
G
IN1
IN2
IN3
IN4
4
SCF
Section
One
Adjustable
Gain
Input
MUX
S1
S2
Filter
and
Clock
Select
(TYPE, FSEL, Fo)
Single
Out
o
SCF
Section
Three
SCF
Section
Two
Pole
Lowpass
Buffer
Ab s o lu te M a x im u m Ra tin g s
D i g i t a l Le v e l s
Power Supply Voltage
Storage Temperature
Operating Temperature
+6V
-60 to +150 C
0 to 7 0 C
All the clock and control pins (except TYPE and
G) are referenced between GND and VDD. In
single supply applications, the digital levels
should be CMOS levels from VSS to VDD. In dual
supply systems, the digital levels should be
CMOS levels from GND to VDD.
O r d e r in g In fo r m a tio n __________
Part Number
Package
Clock to Corner Ratio
MSFS1P
MSFS2P
MSFS3P
MSFS4P
MSFS5P
MSFS6P
MSFS1S
MSFS2S
MSFS3S
MSFS4S
MSFS5S
MSFS6S
8 Pin DIP
16 Pin DIP
8 Pin DIP
16 Pin DIP
8 Pin DIP
50
50 or 100
50
50 or 100
100
100
50
50 or 100
50
50 or 100
100
I n p u t S e l e ct i o n
The input is selected using the Input Select Pins
S1 and S2.
8 Pin DIP
S2
0
S1
0
Input
8 Pin SOIC
16 Pin SOIC
8 Pin SOIC
16 Pin SOIC
8 Pin SOIC
8 Pin SOIC
1
2
3
4
0
1
1
0
1
1
100
Web Site “www.mix-sig.com”
© 2001 Mixed Signal Integration 8
Mixed Signal Integration Corporation reserves the right to change any product or specification without notice at any time. Mixed Signal Integration
products are not designed or authorized for use in life support systems. Mixed Signal Integration assumes no responsibility for errors in this docu-
ment.
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