SN8205UFL_技术文档

SN820X Wi-Fi Network Controller

Module Family

Data Sheet

Version 2.2

February 28, 2014

Note: Murata Electronics N.A, Inc (Murata) reserves the right to make changes in specifications at any time and

without notice. The information furnished in this data sheet is believed to be accurate and reliable. However, no

responsibility is assumed by Murata for its use, nor any infringements of patents or other rights of third parties

resulting from its use. No license is generated under any rights of Murata or its supporters unless specifically

agreed. Murata Electronics N.A, Inc is a wholly owned subsidiary of Murata Manufacturing Company, Ltd. of

Japan.

Revision History

Revision

0.1

Date

Author

Y. Fang

Change Description

12/09/2012

02/03/2012

02/20/2012

Initial version

0.5

Y. Fang

Preliminary version

0.6

N. Nagayama

Update performance data and adjusted table for-

mat

0.7

1.0

1.1

04/20/2012

08/27/2012

01/23/2013

J. Gregus

Y. Fang

Update CE compliance information

Formal release

Added Power Rail Current specification and

Standby Mode Current specification

1.2

1.3

05/30/2013

09/20/2013

R. Willett

R Willett

Changed specs in Table 1 for Pin 2, 3, 4, and 30

Separated Data Sheet/User Manual and created

new data sheet combining

SN8200/8200 UFL and SN8205/8205 UFL

1.4

1.5

11/07/13

11/11/13

R. Willett

R Willett

Added Acronyms list; Revised Fig. 1.1, 2.1; revised

content and renumbered tables in Chap. 3: added

Chapters 4 - 10 and reorganized information;

amended regulatory information.

Revised Operating Temperature specification on

page 6; revised Table 5.1 “Absolute Maximum Rat-

ings,” page 38.

2.0

2.1

2.2

11/25/13

12/17/13

02/28/14

R Willett

R. Willett

Removed references to SyChip; updated copyright,

deleted Chap 11, “Disclaimer;”

Added text describing module software download in

Chapter 1, page 7.

Revised text on page 42, Table 9.2.

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Page 2 of 43

SN820X - 2/28/14

Table of Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

1.1 Model SN820X Module Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.2 Model SN820X Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.4 Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.5 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

2.1 Module Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 Top and Side View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 PCB Footprint (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.1 Typical Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.2 GPIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.3 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.4 Output Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.5 I2C Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.6 I2S SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.7 12-Bit ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.8 DAC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4 RF Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

4.1 DC/RF Characteristics for IEEE 802.11b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.2 DC/RF Characteristics for IEEE 802.11g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.3 DC/RF Characteristics for IEEE 802.11n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5 Environmental Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

5.1 Absolute Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6 Regulatory Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

7 Packing and Marking Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

7.1 Carrier Tape Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.2 Module Marking Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8 RoHS Delcaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

9 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

10 Technical Support Contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

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Page 3 of 43

SN820X - 02/28/14

List of Figures

FIGURE 1.1: SN820X Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

FIGURE 2.1: SN820X and SN820XUFL Top and Side View . . . . . . . . . . . . . . . . . . . . . . . .8

FIGURE 2.2: Detailed Pad Dimensions (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

FIGURE 3.1: SN8200/8200UFL I2C bus AC Waveforms and Measurement Circuit . . . . .18

FIGURE 3.2: SN8205/8205UFL I2C bus AC Waveforms and Measurement Circuit . . . . . 19

FIGURE 3.3: SPI Timing Diagram - Slave Mode and CPHA = 0, SN8200/8200UFL and

SN8205/8205UFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

FIGURE 3.4: SPI Timing Diagram - Slave Mode and CPHA = 1(1)SPI Timing Diagram - Slave

Mode and CPHA = 0, SN8200/8200UFL and SN8205/8205UFL . . . . . . . . . 23

FIGURE 3.5: SPI Timing Diagram - Master Mode SN8200/8200UFL

and SN8205/8205UFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

FIGURE 3.6: ADC Accuracy Characteristics, SN8200/8200UFL . . . . . . . . . . . . . . . . . . . . 27

FIGURE 3.7: ADC Accuracy Characteristics, SN8205/8205UFL . . . . . . . . . . . . . . . . . . . . 30

FIGURE 3.8: Typical Connection Diagram Using the ADC, SN8205/8205UFL . . . . . . . . . 30

FIGURE 7.1 SN820X/820XUFL Carrier Tape Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 40

FIGURE 7.2 Typical SN820X/820XUFL module marking . . . . . . . . . . . . . . . . . . . . . . . . . 40

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Page 4 of 43

SN820X - 02/28/14

List of Tables

Table 1.1: SN820X WiFi Network Controller Module Family . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2.1: Module Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 2.2: Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 2.3: Signal Pinouts for SN820X/820XUFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 3.1.1: SN8200/SN8200UFL and SN8205/SN8205 UFL Typical

Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 3.2.1: Digital I/O Characteristics SN8200/SN8200UFL . . . . . . . . . . . . . . . . . . . . . . 13

Table 3.2.2: Digital I/O Characteristics, SN8205/8205UFL . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 3.3.1: Voltage Characteristics, SN820X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 3.3.2: Current Characteristics, SN8200/8200UFL . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 3.3.3: Current Characteristics, SN8205/8205UFL . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 3.4.1: Output Voltage Characteristics, SN8200/SN8200UFL . . . . . . . . . . . . . . . . . 16

Table 3.4.2: Output Voltage Characteristics, SN8205/SN8205UFL . . . . . . . . . . . . . . . . . 16

Table 3.5.1: I2C Characteristics SN8200/8200UFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 3.5.2: I2C Characteristics SN8205/8205UFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 3.5.3: SCL Frequency (fPCLK1= 36 MHz., VDD = 3.3 V)(1)(2) SN8200/8200UFL 19

Table 3.5.4: SCL Frequency (fPCLK1= 30 MHz., VDD = 3.3 V)(1)(2) SN8205/8205UFL 20

Table 3.6.1: SPI Characteristics SN8200/8200UFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 3.6.2: SPI Characteristics SN8205/8205UFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 3.7.1: ADC Characteristics, SN8200/8200UFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 3.7.2: RAIN max for fADC = 14 MHz(1), SN8200/8200UFL . . . . . . . . . . . . . . . . . . 26

Table 3.7.3: ADC accuracy, SN8200/8200UFL - limited test conditions(1)(2) . . . . . . . . . 26

Table 3.7.4: ADC Accuracy (1) (2) (3), SN8200/8200UFL . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 3.7.5: ADC Characteristics, SN8205/8205UFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 3.7.6: ADC Accuracy, SN8205/8205UFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 3.8.1: DAC Characteristics, SN8200/8200UFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 3.8.2: DAC Characteristic, SN8205/8205UFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 4.1.1: RF Characteristics for IEEE 802.11b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 4.2.1: RF Characteristics for IEEE 802.11g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 4.3.1: RF Characteristics for IEEE 802.11n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 5.1: Absolute Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 5.2: Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 9.1: SN8200/8200UFL Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 9.2: SN8205/8205UFL Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

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Page 5 of 43

SN820X - 02/28/14

SN820X Family

1 Introduction

1.1 Model SN820X Module Family

Wi-Fi Network

Controller Module

The SN820X Module Family is a portfolio of low power, self-contained,

embedded wireless module solutions that address the connectivity demands

of M2M applications. These products integrate a micro-controller, a Wi-Fi

BB/MAC/RF IC, an RF front end and two clocks into small form factor mod-

ules. The module family includes 2 different micro-controller options as

shown below. The modules can also be purchased with either a standard on-

board chip antenna or a U.FL connector where remote antenna flexibility is

required.

Table 1.1: SN820X WiFi Network Controller Module Family

Model #

SN8200

P/N

Built-in STM

ARM Cortex M3

RAM Size

Flash Size

768KB

88-00151-00

88-00151-02

88-00158-00

88-00158-02

96KB

SN8200UFL

SN8205

96KB

768KB

128KB

1024KB

SN8205UFL

1.2 Model SN820X Module Features

• 2.4 GHz IEEE 802.11 b/g/n radio technology

• Dimensions: 30.5 × 19.4 × 2.8 mm

• Antenna configurations: On-board antenna or U.FL connector

• Transmitter power: +18 dBm @80211b

• Receiver sensitivity: -96 dBm

• MCU: ARM Cortex-M3

• Serial Interface Options: UART, SPI

• Peripheral Interface Options: ADC, DAC, I2C, I2S, GPIO

• Operating temperature range: -40 ºC to +85 ºC

• RoHS2 compliant

• MSL Level 3

• FCC/IC certified and CE compliant

• Compatible with Broadcom WICED™ SDK

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Page 6 of 43

SN820X - 02/28/14

1.3 Block Diagram

for on-board

antenna version

(

)

VBAT

VDD

VDD_WIFI_IN

16 MHz

26 MHz

TCXO

ANT

UART

SPI

I2C

12S

Wi-Fi SoC

(802.11b/g/n

ARM

Cortex M3

LPF

SPDT

ADC

DAC

GPIO

for U.FL

connector version

(

)

32 KHz

(optional)

WIFI_SLEEP

_CLK_IN

(optional)

FIGURE 1.1: SN820X Block Diagram

Murata offers Serial-to-WiFi and EZ Web Wizzard software for SN820x in the SN820x EVK+. The modules are

also compatible with Broadcom WICED™ SDK. The customer can obtain the WICED™ SDK from Broadcom

directly. The modules are delivered with no application firmware pre-installed.

Finalize the firmware image, and then download the firmware to the module. For more details, please see ref-

erence [4].

1.4 Acronyms

- ADC Analog to Digital Converter

- DAC Digital to Analog Converter

- GPIO General-Purpose Input-Output

- I2C

- I2S

- ISM

Intelligent Interface Controller

Integrated Interchip Sound

Industrial, Scientific and Medical

- MAC Medium Access Control

- MSL Moisture Sensitivity Level

- PER Packet Error Rate

- ROHS Restriction of Hazardous Substances

- SPI

Serial Peripheral Interface

- UART Universal Asynchronous Receiver-Transmitter

1.5 References

[1] STM32F103RF Data Sheet, ST Microelectronics

[2] STM32F205RG, Data Sheet, ST Microelectronics

[3] SN820X Wi-Fi Network Controller Module Family User Manual, Murata

[4] AN_SN8200_002 SN820X Firmware Downloading Application Note, Murata

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Page 7 of 43

SN820X - 02/28/14

2 Mechanical Specifications

2.1 Module Dimensions

Table 2.1: Module Dimensions

Parameter

Typical

30.5 x 19.4 x 2.8

±0.2

Units

mm

Dimensions (LxWxH)

Dimension tolerances (LxWxH)

mm

2.2 Top and Side View

SN820X Top and Side View

SN820XUFL Top and Side View

FIGURE 2.1: SN820X and SN820XUFL Top and Side View

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Page 8 of 43

SN820X - 02/28/14

2.3 PCB Footprint (top view)

FIGURE 2.2: Detailed Pad Dimensions (top view)

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Page 9 of 43

SN820X - 02/28/14

2.4 Pinouts

Table 2.2: Pinouts

Pin #

Pin Name

I/O

-

Description

1

2

GND

Ground

OSC32_IN

I/O

Optional precision 32.768 KHz slow

clock input. No connect if not used

3

OSC32_OUT

WIFI_VDD_EN

ADC3

I/O

No connect

4

I/O

No connect

5

I/O

General purpose I/O or ADC3

General purpose I/O or ADC4

General purpose I/O or ADC5

DC supply for MCU and I/O

General purpose I/O or ADC6

General purpose I/O or DAC2

General purpose I/O or DAC1

General purpose I/O or ADC1

No connect

6

ADC4

I/O

7

ADC5

I/O

8

VDD

PI

9

ADC6

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

DAC2

I/O

DAC1

I/O

ADC1

I/O

-

Reserved

GND

-

No connect

-

Ground

GND

-

Ground

GND

-

Ground

GND

-

Ground

GND

-

Ground

GND

-

Ground

GND

-

Ground

GND

-

Ground

GND

-

Ground

GND

-

Ground

GND

-

Ground

VDD_WIFI_IN

Reserved

WIFI_SLEEP_CLK_IN

PI

-

Wi-Fi power supply

No connect

-

No connect

-

No connect

I

Optional precision 32.768 kHz Wi-Fi

sleep clock input. Tie to GND if not

used

31

32

33

34

35

36

37

GND

-

Ground

UART_TX

UART_RX

UART_CTS

UART_RTS

JTMS

I/O

General purpose I/O or UART_TX

General purpose I/O or UART_RX

General purpose I/O or UART_CTS

General purpose I/O or UART_RTS

General purpose I/O or JTMS

JTDI/SPI_NSS

General purpose I/O or JTDI or

SPI_NSS

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Page 10 of 43

SN820X - 02/28/14

Table 2.2: Pinouts (Continued)

Pin #

38

Pin Name

I/O

-

Description

General purpose I/O or JTCK

Ground

JTCK

39

Ground

40

JTDO/SPI_SCK

I/O

General purpose I/O or JTDO or

SPI_SCK

41

JTRST/SPI_MISO

I/O

General purpose I/O or JTRST or

SPI_MISO

42

43

44

45

SPI_MOSI

I2C_SCL

I2C_SDA

BOOT

I/O

-

General purpose I/O or SPI_MOSI

General purpose I/O or I2C_SCL

General purpose I/O or I2C_SDA

Normal operation if connected to

ground at power up.

46

47

48

ADC2

I/O

I

General purpose I/O or ADC2

Module reset

MICRO_RST_N

VBAT

PI

Power supply for backup circuitry

when VDD is not present

49

50

51

52

53

54

55

56

57

58

59

60

61

62

GND

Reserved

GND

-

Ground

No connect

Ground

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Page 11 of 43

SN820X - 02/28/14

Table 2.3: Signal Pinouts for SN820X/820XUFL

Pin Pin name STM32F103RF/STM32F205RG pin

5

6

7

9

ADC3

ADC4

ADC5

ADC6

PA0/WKUP/ADC123_0/USART2_CTS

TIM2_CH1_ETR/ TIM5_CH1 / TIM8_ETR

PA1/ADC123_1/USART2_RTS TIM2_CH2 / TIM5_CH2

PA2/ADC123_2/USART2_TX TIM2_CH3 / TIM5_CH3 /

TIM9_CH1

PA3/ADC123_3/USART2_RX TIM2_CH4 / TIM5_CH4 /

TIM9_CH2

10

11

12

32

33

34

35

36

37

38

40

41

42

43

44

46

DAC2

DAC1

ADC1

PA4/ADC12_4/DAC1/USART2_CK/SPI1_NSS

PA5/ADC12_5/DAC2/SPI1_SCK

PA7/ADC12_7/SPI1_MOSI

PA9/UART1_TX

UART_TX

UART_RX

UART_CTS

UART_RTS

JTMS

PA10/UART1_RX

PA11/UART1_CTS/USB2_DM/CAN_RX

PA12/UART1_RTS/USB2_DP/CAN_TX

PA13/JTMS/SWIO

JTDI/SPI_NSS

JTCK

PA15/JTDI/SPI3_NSS/I2S3_WS

PA14/JTCK/SWCLK

JTDO/SPI_SCK

JTRST/SPI_MISO

SPI_MOSI

I2C_SCL

PB3/JTDO/SPI3_SCK/I2S3_CK

PB4/JTRST/SPI3_MISO

PB5/I2C1_SMBA/SPI3_MOSI/ I2S3_SD

PB6/I2C1_SCL TIM4_CH1

PB7/I2C1_SDA TIM4_CH2

PA6/ADC12_6/SPI1_MISO

I2C_SDA

ADC2

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Page 12 of 43

SN820X - 02/28/14

3 DC Electrical Specifications

The I/O pins from SN820X are based on the built-in STM32 microcontroller. The information shown in sections

3.2 through 3.8 is derived from the ST Microelectronics Data Sheet for user convenience. For original informa-

tion, see reference [1] and [2] on page of References.

3.1 Typical Power Consumption

Table 3.1.1: SN8200/SN8200UFL and SN8205/SN8205 UFL Typical Power Consumption

Values

Item

Condition

Min

Typ

110

370

Max

Units

mA

11b

11g

11n

Receive mode

11 Mbps

Transmit mode

(18 dBm/

mA

100% Duty Cycle)

Receive mode

54 Mbps

MCS7

110

290

mA

Transmitmode

(14.5 dBm/100%

Duty Cycle)

Receive mode

110

280

mA

Transmit mode

(13.5 dBm/

100%DutyCycle)

Standby Mode with IEEE802.11 Power

Save

DTIM 1, Telnet session estab-

lished and idling

3.15

1.28

mA

Standby Mode with IEEE802.11 Power

Save

DTIM 3, Telnet session estab-

lished and idling

3.2 GPIO Interface

The general purpose I/O (GPIO) pins available on the SN820X will connect to various external devices. GPIOs are configured

as input floating by default. Subsequently, they can be programmed to be either input or output pins via the GPIO control reg-

ister. They can also be programmed to have internal pull-up or pull-down resistors. The MICRO_RST_N pin is connected to a

permanent pull-up resistor, R

.

PU

Table 3.2.1: Digital I/O Characteristics SN8200/SN8200UFL

SYM

min.

typ.

max.

unit

Input Low Voltage¹

Input High Voltage¹

Input Low Voltage²

VIL

-0.3

0.28 (VDD-2) +0.8

V

VIH

VIL

VIH

0.41 (VDD-2) +1.3

-0.3

VDD+0.3

0.32 (VDD2) +0.75

VDD +0.5

V

Input High Voltage²

0.42 (VDD-2) +1

Input Low Voltage (MICRO_RST_N)

Input High Voltage (MICRO_RST_N)

Output Low Voltage

VIL

VIH

-0.5

2

0.8

VDD + 0.5

0.4

V

VOL

VOH

R_PU

V

Output High Voltage

VDD - 0.4

30

V

Weak Pull-up Equivalent Resistor

40

50

kΩ

Weak Pull-down Equivalent resistor

R_PD

30

kΩ

1 - for pins 5, 6, 7, 9, 10, 11, 12, 42, 46

2 - for pins 32 - 38, 40, 41, 43, 44

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SN820X - 02/28/14

Table 3.2.2: Digital I/O Characteristics, SN8205/8205UFL

SYM

min.

typ.

max.

unit

Input Low Voltage¹

Input High Voltage¹

Input Low Voltage²

VIL

-0.3

0.3 VDD

V

VIH

VIL

VIH

0.7 VDD

-0.3

3.6

0.3 VDD

3.6

V

Input High Voltage²

0.7

Input Low Voltage (MICRO_RST_N)

Input High Voltage (MICRO_RST_N)

Output Low Voltage

VIL

VIH

-0.5

2

0.8

VDD + 0.5

0.4

V

VOL

VOH

R_PU

V

Output High Voltage

VDD - 0.4

30/8*

V

Weak Pull-up Equivalent Resistor

40/11*

50/15*

kΩ

Weak Pull-down Equivalent resistor

R_PD

30/8*

kΩ

1 - for pins 5, 6, 7, 9, 10, 11, 12, 42, 46

2 - for pins 32-38, 40, 41, 43, 44

(*) - Pin 33

3.3 Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ±20 mA

(with a relaxed VOL/VOH) except PC13, PC14 and PC15 which can sink or source up to ±3mA. When using

the PC13 to PC15 GPIOs in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF.

• In the user application, the number of I/O pins which can drive current must be limited to respect the

absolute maximum rating specified in Table 3.3.1.

• The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the

MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD.

Table 3.3.1: Voltage Characteristics, SN820X

Symbol

Ratings

Min

–0.3

Max

4.0

U

(1)

V_DD–V_SS

External main supply voltage (including V_DDA, V_DD

Input voltage on five-volt tolerant pin⁽²⁾

Input voltage on any other pin

)

V_SS–0.3

V_DD+4

4.0

V

V_IN

V_SS–0.3

|∆V_DDx

|

Variations between different VDD power pins

-

50

mV

V

|V_SSX− V_SS|

Variations between all the different ground pins

Electrostatic discharge voltage (human body model)

50

V_ESD(HBM)

2000

1. All main power (V_DD, V_DDA) and ground (V_SS, V_SSA) pins must always be connected to the external power supply, in

the permitted range.

2. V_INmaximum value must always be respected.

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SN820X - 02/28/14

Table 3.3.2: Current Characteristics, SN8200/8200UFL

Symbol

Ratings

Max.

150

Uni

Total current into V_DD/V_DDApower lines (source)⁽¹⁾

Total current out of V_SSground lines (sink)⁽¹⁾

Output current sunk by any I/O and control pin

Output current source by any I/Os and control pin

I_VDD

I_VSS

150

25

I_IO

25

mA

Injected current on five volt tolerant pins⁽³⁾

Injected current on any other pin⁽⁴⁾

(2)

-5/+0

± 5

I_INJ(PIN)

Total injected current (sum of all I/O and control pins)⁽⁵⁾

ΣI_INJ(PIN)

± 25

Table 3.3.3: Current Characteristics, SN8205/8205UFL

Symbol

Ratings

Max.

Unit

I_VDD

I_VSS

120

25

(1)

Total current into VDD power lines (source)

Total current out of VSS ground lines (sink)

Output current sunk by any I/O and control pin

Output current source by any I/Os and control pin

I_IO

25

mA

-5/+0

±5

(3)

Injected current on five-volt tolerant I/O

(2)

(4)

I_INJ(PIN)

(4)

Injected current on any other pin

ΣI_INJ(PIN)

±25

(5)

Total injected current (sum of all I/O and control pins)

1. All main power (V_DD, V_DDA)and ground (V_SS, V_SSA)pins must always be connected to the external power supply, in the

permitted range.

2. Negative injection disturbs the analog performance of the device.

3. Positive injection is not possible on these I/Os. A negative injection is induced by V_IN<V_SS. I_INJ(PIN)must never be

exceeded.

4. A positive injection is induced by V_IN>V_DDwhile a negative injection is induced by V_IN<V_{SS. INJ(PIN)}

I

must never be

exceeded.

Σ

5. When several inputs are submitted to a current injection, the maximum

and negative injected currents (instantaneous values)

I_INJ(PIN)is the absolute sum of the positive

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SN820X - 02/28/14

3.4 Output Voltage Levels

Unless otherwise specified, the parameters given in Table 3.4.1 and Table 3.4.2 are derived from tests per-

formed under ambient temperature and V supply voltage conditions. All I/Os are CMOS and TTL compliant.

DD

Table 3.4.1: Output Voltage Characteristics, SN8200/SN8200UFL

Symbol

Parameter

Conditions

Min

Max

Unit

(1)

Output low level voltage for an I/O pin

when 8 pins are sunk at same time

-

0.4

VOL

TTL port⁽³⁾

I_IO= +8 mA

2.7 V < VDD < 3.6 V

V

(2)

Output high level voltage for an I/O pin

when 8 pins are sourced at same time

V_DD—0.4

VOH

(1)

CMOS port⁽³⁾

I_IO=+ 8mA

2.7 V < V_DD< 3.6 V

Output low level voltage for an I/O pin

when 8 pins are sunk at same time

-

0.4

1.3

0.4

VOL

V

(2)

Output high level voltage for an I/O pin

when 8 pins are sourced at same time

2.4

-

VOH

(1)(4)

Output low level voltage for an I/O pin

when 8 pins are sunk at same time

V_OL

I_IO= +20 mA

2.7 V < V_DD< 3.6 V

(2)(4)

Output high level voltage for an I/O pin

when 8 pins are sourced at same time

VDD—1.3

V_OL

(1)(4)

Output low level voltage for an I/O pin

when 8 pins are sunk at same time

V_OL

I_IO= +6 mA

2 V < VDD < 2.7 V

(2)(4)

Output high level voltage for an I/O pin

when 8 pins are sourced at same time

V_DD—0.4

V_OL

1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 3.4.1 and the

sum of IIO (I/O ports and control pins) must not exceed IVSS.

2. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 3.4.1 and

the sum of IIO (I/O ports and control pins) must not exceed IVDD.

3. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

4. Based on characterization data, not tested in production.

Table 3.4.2: Output Voltage Characteristics, SN8205/SN8205UFL

Symbol

Parameter

Conditions

Min

Max

Unit

(2)

CMOS port⁽³⁾

I_IO=+ 8mA

2.7 V < VDD < 3.6 V

Output low level voltage for an I/O pin

when 8 pins are sunk at same time

-

0.4

VOL

V

(3)

Output high level voltage for an I/O pin

when 8 pins are sourced at same time

V_DD—0.4

VOH

(2)

Output low level voltage for an I/O pin

when 8 pins are sunk at same time

-

0.4

1.3

0.4

VOL

TTL port⁽³⁾

I_IO= +8 mA

2.7 V < V_DD< 3.6 V

V

(3)

Output high level voltage for an I/O pin

when 8 pins are sourced at same time

2.4

-

VOH

(2)(4)

Output low level voltage for an I/O pin

when 8 pins are sunk at same time

V_OL

I_IO= +20 mA

2.7 V < VDD < 3.6 V

(3)(4)

Output high level voltage for an I/O pin

when 8 pins are sourced at same time

VDD—1.3

V_OL

(2)(4)

Output low level voltage for an I/O pin

when 8 pins are sunk at same time

V_OL

I_IO= +6 mA

2 V < VDD < 2.7 V

(3)(4)

Output high level voltage for an I/O pin

when 8 pins are sourced at same time

V_DD—0.4

V_OL

1. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of

current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: the speed should not exceed 2

MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive an LED).

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SN820X - 02/28/14

2. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 3.4.2 and the

sum of IIO (I/O ports and control pins) must not exceed IVSS.

3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 3.4.2 and

the sum of IIO (I/O ports and control pins) must not exceed IVDD.

4. Based on characterization data, not tested in production.

2

3.5 I C Interface Characteristics

Unless otherwise specified, the parameters given below are derived from tests performed under ambient tem-

perature, fPCLK1 frequency and VDD supply voltage conditions. The SN8200/8200UFL and SN8205/

2

8205UFL performance line I C interface meets the requirements of the standard I C communication protocol

with the following restrictions: the I/O pins to which SDA and SCL are mapped are not "true" open-drain. When

configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present.

2

The I C characteristics are described in Table 3.5.1 and Table 3.5.2.

2

Table 3.5.1: I C Characteristics SN8200/8200UFL

2

(1)

Standard mode

Fast mode I C

Symbol

Parameter

Unit

M

Max

Min

Max

4.7

4.0

-

1.3

0.6

100

(4)

-

µs

t_w(SCLL)

t_w(SCLH)

t_su(SDA)

t_h(SDA)

SCL clock low time

SCL clock high time

SDA setup time

-

250

-

(3)

0

(3)

0

900

SDA data hold time

-

1000

20 + 0.1Cb

300

t_r(SDA)

t_r(SCL)

t_f(SDA)

t_f(SCL)

SDA and SCL rise time

ns

µs

300

-

300

SDA and SCL fall time

Start condition hold time

4.0

4.7

-

0.6

-

t_h(STA)

Repeated Start

t_su(STA)

condition setup time

4.0

4.7

-

0.6

1.3

-

μs

t_su(STO)

Stop condition setup time

t_w(STO:STA)

Stop to Start condition

time (bus free)

-

400

-

400

pF

Cb

Capacitive load for each

bus line

1. Guaranteed by design, not tested in production.

2. fPCLK1 must be at least 2 MHz to achieve standard mode I²C frequencies. It must be at least 4 MHz to achieve the

fast mode I²C frequencies and it must be a multiple of 10 MHz in order to reach the I²C fast mode maximum clock

speed of 400 kHz.

3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of

SCL signal.

4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined

region of the falling edge of SCL.

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SN820X - 02/28/14

2

Table 3.5.2: I C Characteristics SN8205/8205UFL

Standard mode

2

(1

Fast mode I C

Symbol

Parameter

Unit

M

Max

Min

Max

t_w(SCLL)

t_w(SCLH)

t_su(SDA)

t_h(SDA)

SCL clock low time

SCL clock high time

SDA setup time

4.7

4.0

250

0

-

1.3

0.6

100

0

-

µs

-

(3)

900

SDA data hold time

t_{r(SDA) r(SCL)}

t

-

1000

20 +

300

0.1Cb

ns

µs

SDA and SCL rise time

t_{f(SDA) f(SCL)}

t

-

300

-

300

SDA and SCL fall time

Start condition hold time

t_h(STA)

4.0

4.7

-

0.6

-

t_su(STA)

Repeated Start condition

setup time

t_su(STO)

Stop condition setup time

4.0

4.7

-

0.6

1.3

-

μs

t_w(STO:STA)

Stop to Start condition time

(bus free)

C_b

Capacitive load for each

bus line

-

400

-

400

pF

1. Guaranteed by design, not tested in production.

2

2. f^PCLK1must be at least 2 MHz to achieve standard mode I C frequencies. It must be at least 4 MHz to achieve fast

2

mode I C frequencies, and a multiple of 10 MHz to reach the 400 kHz maximum I C fast mode clock.

3. The maximum Data hold time has only to be met if the interface does not stretch the low period of the SCL signal.

2

FIGURE 3.1: SN8200/8200UFL I C bus AC Waveforms and Measurement Circuit

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2

FIGURE 3.2: SN8205/8205UFL I C bus AC Waveforms and Measurement Circuit

f

Table 3.5.3: SCL Frequency (

= 36 MHz., VDD = 3.3 V)⁽¹⁾⁽²⁾SN8200/8200UFL

I2C_CCR value

PCLK1

fSCL (kHz)

RP = 4.7 kΩ

400

300

200

100

50

0x801E

0x8028

0x803C

0x00B4

0x0168

0x0384

20

2

1. R^P= External pull-up resistance, f^SCL= I C speed.

2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the tolerance on

the achieved speed is ±2%. These variations depend on the accuracy of the external components used to design the

application.

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SN820X - 02/28/14

(1)(2)

= 30 MHz., VDD = 3.3 V)

f

Table 3.5.4: SCL Frequency (

SN8205/8205UFL

PCLK1

I2C_CCR value

fSCL (kHz)

RP = 4.7 kΩ

400

300

200

100

50

0x8019

0x8021

0x8032

0x0096

0x012C

0x02EE

20

2

1. R^P= External pull-up resistance, f^SCL= I C speed.

2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the tolerance on

the achieved speed is ±2%. These variations depend on the accuracy of the external components used to design the

application.

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2

3.6 I S SPI Characteristics

The I2S interface is multiplexed with SPI and can be operated in master or slave mode. Unless otherwise

specified, the parameters given below for I2S are derived from tests performed under ambient temperature,

f

PCLKx frequency and V supply voltage conditions.

DD

Table 3.6.1: SPI Characteristics SN8200/8200UFL

Symbol

Parameter

Conditions

Master mode

Min

Max

Uni

f_SCK

SPI clock frequency

-

18

8

MHz

1/t_c(SCK)

Slave mode

t_r(SCK)

t_f(SCK)

SPI clock rise and fall

time

Capacitive load: C = 30 pF

ns

%

DuCy(SCK)

SPI slave input clock

duty cycle

Slave mode

30

70

(1)

NSS setup time

NSS hold time

Slave mode

4t_PCLK

2t_PCLK

50

-

t_su(NSS)

(1)

t_h(NSS)

(1)

SCK high and low time

Master mode, f_PCLK=36MHz,

presc = 4

60

t_w(SCLH)

(1)

t_w(SCLL)

(1)

Master mode

5

4

0

2

-

t_su(MI)

Data input setup time

Data input hold time

(2)

Slave mode

-

t_su(SI)

(1)

Master mode

-

t_h(MI)

(1)

Slave mode

-

t_h(SI)

(1)(3)

Data output access

Data output disable

Data output valid time

Slave mode, f_PCLK= 20 MHz

Slave mode

3t_PCLK

t_a(SO)

ns

(1)(2)

10

25

5

t_dis(SO)

(1)

Slave mode (after enable edge)

Master mode (after enable edge)

Slave mode (after enable edge)

Master mode (after enable edge)

t_v(SO)

(1)

-

t_v(MO)

(1)

15

2

-

t_h(SO)

Data output hold time

(1)

-

t_h(MO)

1. Based on characterization, not tested in production.

2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in

Hi-Z.

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Table 3.6.2: SPI Characteristics SN8205/8205UFL

Symbol

f_SCK

Parameter

Conditions

Min

Max

Unit

-

30

SPI1 master/slave mode

SPI clock frequency

MHz

1/t_c(SCK)

-

15

8

SPI2/SPI3 master/slave mode

t_r(SCL)

t_f(SCL)

SPI clock rise and fall

time

Capacitive load: C = 30 pF,

f_PCLK= 30 MHz

ns

%

SPI slave input clock

duty cycle

Slave mode

DuCy(SCK)

30

70

-

(1)

t_su(NSS)

NSS setup time

NSS hold time

4t

PCLK

2tPCLK

t_PCLK-3

Slave mode

(1)

t_h(NSS)

-

Slave mode

(1)

t_w(SCLH)

t_PCLK+3

Master mode, f_{PCLK=3- MHz}

SCK high and low time

Data input setup time

presc = 2

Master mode

(1)

t_su(MI)

5

4

0

-

Slave mode

(1)

t_h(MI)

-

Master mode

Data input hold time

Slave mode

ns

(1)(2)

(1)(3)

Data output access

time

3t_PCLK

Slave mode, f_PCLK= 30 MHz

t_a(so)

Data output disable

time

2

Slave mode

t_dis(SO)

10

25

(1)

Data output valid time

-

Slave mode (after enable edge)

Master mode (after enable edge)

Slave mode (after enable edge)

Master mode (after enable edge)

t_v(SO)

5

-

t_v(MO)

(1)

15

2

t_h(SO)

Data output hold time

(1)

-

t_(MO)

1. Based on characterization, not tested in production.

2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in

Hi-Z

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FIGURE 3.3: SPI Timing Diagram - Slave Mode and CPHA = 0, SN8200/8200UFL and SN8205/8205UFL

(1)

FIGURE 3.4: SPI Timing Diagram - Slave Mode and CPHA = 1 SPI Timing Diagram - Slave Mode and

CPHA = 0, SN8200/8200UFL and SN8205/8205UFL

1. Measurement points are done at CMOS levels: 0.3V_DDand 0.7 V_DD.

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FIGURE 3.5: SPI Timing Diagram - Master Mode SN8200/8200UFL and SN8205/8205UFL

Measurement points are done at CMOS levels: 0.3V^DDand 0.7V^DD.

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3.7 12-Bit ADC Characteristics

Unless otherwise specified, the parameters given below are preliminary values derived from tests performed

under ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions.

NOTE: It is recommended to perform a calibration after each power-up.

Table 3.7.1: ADC Characteristics, SN8200/8200UFL

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_DDA

Power supply

2.4

-

3.6

V

V_REF+

I_VREF

Positive reference voltage

2.4

-

V

DDA

220⁽¹⁾

Current on the V

input pin

160

µA

REF

f_ADC

ADC clock frequency

Sampling rate

0.6

-

14

1

MHz

(2)

0.05

f_S

(2)

f_ADC= 14 MHz

-

823

17

kHz

1/f_ADC

V

f_TRIG

External trigger frequency

0 (V_SSAor V_REF

-

V_REF+

(3)

V_AIN

Conversion voltage range

tied to ground)

-

(2)

See Equation 1

for details

-

50

R_AIN

External input impedance

Sampling switch resistance

kΩ

(2)

-

1

8

R_ADC

(2)

Internal sample and hold

capacitor

pF

C_ADC

t_CAL

f

_ADC= 14 MHz

5.9

83

µs

1/f_ADC

µs

Calibration time

(2)

f_ADC= 14 MHz

-

0.214

t_lat

Injection trigger conversion

latency

(4)

3

-

1/f_ADC

µs

(2)

f

_ADC= 14 MHz

-

0.143

t_latr

Regular trigger conversion

latency

(4)

-

0.107

1.5

0

-

2

1/f_ADC

µs

(2)

f_ADC= 14 MHz

-

17.1

239.5

1

t_S

Sampling time

Power-up time

-

1/f_ADC

µs

(2)

0

t_STAB

(2)

f_ADC= 14 MHz

1

18

µs

t_CONV

Total conversion time (including

sampling time)

14 to 252 (t_Sfor sampling +12.5 for suc-

cessive approximation)

1/f_ADC

1. Based on characterization, not tested in production.

2. Guaranteed by design, not tested in production.

3. V^REF+can be internally connected to V^DDAand V^REF-can be internally connected to V^SSA, depending on the package.

4. For external triggers, a delay of 1/f^PCLK2must be added to the latency specified above.

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Page 25 of 43

SN820X - 02/28/14

Equation 1 (SN8200/8200UFL): R

max formula

AIN

The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error

below 1/4 of LSB. Here N = 12 (from 12-bit resolution).

(1)

Table 3.7.2: R

max for f

= 14 MHz , SN8200/8200UFL

AIN

ADC

Ts (cycles)

tS (µs)

RAIN max (kΩ)

1.5

0.11

0.54

0.4

7.5

5.9

13.5

28.5

41.5

55.5

71.5

239.5

0.96

2.04

2.96

3.96

5.11

17.1

11.4

25.2

37.2

50

NA

1. Guaranteed by design, not tested in production.

(1)(2)

Table 3.7.3: ADC accuracy, SN8200/8200UFL - limited test conditions

(3)

Symbol

E

Parameter

Total unadjusted error

Offset error

Test conditions

fPCLK2 = 56 MHz,

Typ

±1.

±1

Max

Unit

±2

fADC = 14 MHz, RAIN < 10

kΩ,

EO

±1.5

±1

EG

Gain error

±0.

VDDA = 3 V to

LSB

ED

Differential linearity error

Integral linearity error

3.6 V TA = 25 °C

Measurements made after

EL

±1.5

1. ADC DC accuracy values are measured after internal calibration.

2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non- robust) analog

input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another

analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may poten-

tially inject negative current.

3. Based on characterization, not tested in production.

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Page 26 of 43

SN820X - 02/28/14

(1) (2) (3)

Table 3.7.4: ADC Accuracy

, SN8200/8200UFL

(4)

Symbol

Parameter

Total unadjusted error

Offset error

Test conditions

Typ

±2

Max

Unit

E

±5

f_PCLK2= 56 MHz,

fADC = 14 MHz, RAIN < 10

kΩ,

±1.

±1

±2.5

±3

E

Gain error

LSB

ED

EL

Differential linearity error

Integral linearity error

±2

V

_DDA= 2.4 V to 3.6 V

Measurements made after

±1.

±3

1. ADC DC accuracy values are measured after internal calibration.

2. Better performance could be achieved in restricted VDD, frequency, VREF and temperature ranges.

3. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non- robust) analog

input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another

analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may poten-

tially inject negative current.

4. Preliminary values.

FIGURE 3.6: ADC Accuracy Characteristics, SN8200/8200UFL

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Page 27 of 43

SN820X - 02/28/14

Table 3.7.5: ADC Characteristics, SN8205/8205UFL

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

1.8⁽¹⁾

V_DDA

Power supply

-

3.6

V

1.8⁽¹⁾

0.6

V_REF+

f_ADC

Positive reference voltage

ADC clock frequency

-

VDDA

15

V

VDDA = 1.8⁽¹⁾to 2.4 V

VDDA = 2.4 to 3.6 V

MHz

kHz

0.6

-

30

(3)

fADC = 30 MHz with

12-bit resolution

1764

f_TRI

G

External trigger frequency

-

17

1f_ADC

V

(4)

V_AIN

Conversion voltage range

0 (V_SSAor V_REF-

tied to ground)

V

REF+

(3)

External input impedance

See Equation 1

for details

-

50

kΩ

R_AIN

(3,5)

Sampling switch resistance

1.5

-

6

-

kΩ

R_ADC

(3)

Internal sample and hold capacitor

4

pF

C_ADC

Injection trigger conversion latency

Regular trigger conversion latency

f_ADC= 30 MHz

-

0.100

µs

(3)

t_lat

3⁽⁶⁾

-

1/f

ADC

(3)

f

_ADC= 30 MHz

-

0.067

µs

1/f_ADC

µs

t_latr

(6)

2

-

0.100

3

-

(3)

-

16

480

3

t_s

Sampling time

Power-up time

-

1/f_ADC

µs

(3)

-

2

-

t_STAB

(3)

f_ADC= 30 MHz

0.5

16.40

µs

t_CONV

12-bit resolution

f

_ADC= 30 MHz

0.43

0.37

0.3

-

16.34

16.27

16.20

µs

Total conversion time (including sam-

pling time)

10-bit resolution

f_ADC= 30 MHz

8-bit resolution

f_ADC= 30 MHz

6-bit resolution

µs

9 to 492 (tS for sampling +n-bit resolution for successive approxi-

mation)

1/f_ADC

(3)

12-bit resolution

Single ADC

f_s

-

2

Msps

Sampling rate (f_ADC= 30 MHz)

12-bit resolution

Interleave Dual ADC

mode

3.75

12-bit resolution

Interleave Triple ADC

mode

-

6

Msps

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Page 28 of 43

SN820X - 02/28/14

Table 3.7.5: ADC Characteristics, SN8205/8205UFL (Continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

f_ADC= 30 MHz

-

300

500

µA

3 sampling time 12-

bit resolution

(3)

ADC VREF DC current consump-

tion in conversion mode

I_VREF+

f

_ADC= 30 MHz

-

1.6

-

16

1.8

60

µA

mA

µA

480 sampling time

12-bit resolution

(3)

f_ADC= 30 MHz

I_VDDA

3 sampling time 12-

bit resolution

ADC VDDA DC current con-

sumption in conversion mode

f

_ADC= 30 MHz

480 sampling time

12-bit resolution

1. If IRROFF is set to V^DD, this value can be lowered to 1.7 V when the device operates in the 0 to 70 °C temperature

range.

2. It is recommended to maintain the voltage difference between V^REF+and V^DDAbelow 1.8 V.

3. Based on characterization, not tested in production.

4. V^REF+is internally connected to V^DDAand V^REF-is internally connected to V^SSA.

5, R^ADCmaximum value is given for V^DD=1.8 V, and minimum value for V^DD=3.3 V.

6. For external triggers, a delay of 1/f^PCLK2must be added to the latency specified above.

Equation 1: SN8205/8205UFL R

Max Formula

AIN

The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error

below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the

ADC_SMPR1 register.

Table 3.7.6: ADC Accuracy, SN8205/8205UFL

(2)

Symbol

Parameter

Total unadjusted error

Offset error

Test conditions

Typ

±2

Max

Unit

ET

E

±5

LSB

±1.

±1

±2.5

fPCLK2 = 60 MHz,

f_ADC= 30 MHz, R_AIN< 10

E

Gain error

±3

±2

±3

(3)

kΩ, VDDA = 1.8 to 3.6 V

ED

EL

Differential linearity error

Integral linearity error

±1.

1. Better performance could be achieved in restricted VDD, frequency and temperature ranges.

2. Based on characterization, not tested in production.

3. If IRROFF is set to VDD, this value can be lowered to 1.7 V when the device operates in the 0 to 70 °C temperature

range.

NOTE: ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins

should be avoided as this significantly reduces the accuracy of the conversion being performed on another

analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially

inject negative currents.

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Page 29 of 43

SN820X - 02/28/14

FIGURE 3.7: ADC Accuracy Characteristics, SN8205/8205UFL

1. Example of an actual transfer curve.

2. Ideal transfer curve.

3. End point correlation line.

4. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.

EO = Offset Error: deviation between the first actual transition and the first ideal one.

EG = Gain Error: deviation between the last ideal transition and the last actual one.

ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.

EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.

FIGURE 3.8: Typical Connection Diagram Using the ADC, SN8205/8205UFL

Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad

capacitance (roughly 7 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this, fADC should

be reduced.

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Page 30 of 43

SN820X - 02/28/14

3.8 DAC Electrical Specifications

Table 3.8.1: DAC Characteristics, SN8200/8200UFL

Symbol

Parameter

Min

Typ

Max

Unit

Comments

V_DDA

Analog supply voltage

2.4

-

3.6

V

V_REF+

V_SSA

Reference supply voltage

Ground

2.4

0

-

3.6

0

V

V_REF+must always be below VDDA

Resistive load vs. V_SSAwith

buffer ON

5

-

kΩ

1)

R_LOAD

(

Resistive load vs. V_DDAwith

buffer ON

15

When the buffer is OFF, the Minimum

resistive load between DAC_OUT and

(1)

Impedance output with buffer

OFF

R_O

V

_SSto have a 1% accuracy is

-

15

50

kΩ

1.5 MΩ

Maximum capacitive load at DAC_OUT

pin (when the buffer is ON).

(1)

Capacitive load

pF

C_LOAD

It gives the maximum output excursion of

the DAC.

DAC_OUT

min⁽¹⁾

Lower DAC_OUT voltage with

buffer ON

It corresponds to 12-bit input code

(0x0E0) to (0xF1C) at V_REF+= 3.6 V

0.2

-

V

DAC_OUT

max⁽¹⁾

Higher DAC_OUT voltage

with buffer ON

and (0x155) and (0xEAB) at V_REF+

2.4 V

=

V_DDA– 0.2

DAC_OUT

min⁽¹⁾

Lower DAC_OUT voltage with

buffer OFF

-

0.5

mV

V

It gives the maximum output excursion of

the DAC.

DAC_OUT

max⁽¹⁾

Higher DAC_OUT voltage

with buffer OFF

V_REF+

–

10

mV

DAC DC current consump-

tion in quiescent mode

(Standby mode)

With no load, worst code (0x0E4) at

V_REF+= 3.6 V in terms of DC consump-

tion on the inputs

I_DDVREF

-

380

µA

+

With no load, middle code (0x800) on the

inputs

I_DDA

DAC DC current consump-

tion in quiescent mode

(Standby mode)

-

480

µA

With no load, worst code (0xF1C) at

V_REF+= 3.6 V in terms of DC consump-

tion on the inputs

DNL⁽²⁾

Differential non linearity

Difference between two

consecutive code-1LSB)

LSB

±0.5

±3

Given for the DAC in 10-bit configuration

Given for the DAC in 12-bit configuration

-

LSB

INL⁽²⁾

Integral non linearity (difference

between measured value at Code

i and the value at Code i on a line

drawn between Code 0 and last

Code 1023)

-

±1

±4

Given for the DAC in 10-bit configuration

Given for the DAC in 12-bit configuration

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Page 31 of 43

SN820X - 02/28/14

Table 3.8.1: DAC Characteristics, SN8200/8200UFL (Continued)

Symbol

Parameter

Min

Typ

Max

Unit

Comments

Offset ⁽²⁾

Offset error

(difference between

measured value at Code

(0x800) and the ideal value =

V_REF+/2)

-

±10

mV

Given for the DAC in 12-bit configuration

-

±3

±12

±0.5

4

LSB

%

Given for the DAC in 10-bit at V_REF+

= 3.6 V

Given for the DAC in 12-bit at V_REF+

= 3.6 V

Gain error ⁽²⁾

Gain error

-

Given for the DAC in 12bit configuration

(2)

Settling time (full scale: for a 10-

bit input code transition between

the lowest and the highest input

codes when DAC_OUT reaches

final value±1LSB

3

µs

C_LOAD≤ 50 pF, R_LOAD≥ 5 kΩ

t_SETTLING

Update

rate⁽²⁾

Max frequency for a correct

DAC_OUT change when

small variation in the input

code (from code i to i+1LSB)

-

1

MS/s

µs

C_LOAD≤ 50 pF, R_LOAD≥ 5 kΩ

(2)

Wakeup time from off state

(Setting the ENx bit in the

DAC Control register)

6.5

–67

10

C_LOAD≤ 50 pF, R_LOAD≥ 5 kΩ

t_WAKEUP

input code between lowest and highest

PSRR+⁽¹⁾

Power supply rejection ratio

(to VDDA) (static DC

measurement

–40

dB

No R_LOAD,C_LOAD= 50 pF

1. Guaranteed by design, not tested in production.

2. Preliminary values.

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Page 32 of 43

SN820X - 02/28/14

Table 3.8.2: DAC Characteristic, SN8205/8205UFL

Symbol

Parameter

Min

Ty

M

Unit

Comments

(1)

V_DDA

Analog supply voltage

1.8

-

3.6

V

(1)

V_REF+

V_SSA

Reference supply voltage

Ground

-

3.6

0

V

V_REF+≤ V_DDA

0

5

(2)

R_LO

Resistive load with buffer ON

-

kΩ

AD

(2)

When the buffer is OFF, the Minimum

resistive load between DAC_OUT

and VSS to have a 1% accuracy is

1.5 MΩ

R_O

Impedance output with buffer

OFF

-

15

50

kΩ

Maximum capacitive load at

DAC_OUT pin (when the buffer is

ON).

C_LO

AD(2)

Capacitive load

pF

It gives the maximum output excur-

sion of the DAC.

DAC_OUT

min⁽²⁾

Lower DAC_OUT voltage with

buffer ON

It corresponds to 12-bit input code

0.2

-

V

(0x0E0) to (0xF1C) at V_REF+

=

DAC_OUT

max⁽²⁾

Higher DAC_OUT voltage with

buffer ON

3.6 V and (0x1C7) to (0xE38) at

V_REF+= 1.8 V

V

– 0.2

DDA

DAC_OUT

min⁽²⁾

Lower DAC_OUT voltage with

buffer OFF

-

0.5

-

mV

V

It gives the maximum output excur-

sion of the DAC.

DAC_OUT

max⁽²⁾

Higher DAC_OUT voltage with

buffer OFF

V

– 1LSB

REF+

-

With no load, worst code (0x800) at

V_REF+= 3.6 V in terms of DC con-

sumption on the inputs

DAC DC VREF current con-

sumption in quiescent mode

(Standby mode)

170

240

75

(4)

I_VREF+

µA

With no load, worst code (0xF1C) at

V_REF+= 3.6 V in terms of DC con-

-

50

sumption on the inputs

With no load, middle code (0x800) on

the inputs

(4)

DAC DC VDDA current con-

-

280

475

380

625

µA

I_DDA

(3)

sumption in quiescent mode

With no load, worst code (0xF1C) at

V_REF+ = 3.6 V in terms of DC con-

sumption on the inputs

DNL⁽⁴⁾

Differential non linearity

Difference between two

consecutive code-1LSB)

-

±0.5

LSB

Given for the DAC in 10-bit configura-

tion.

Given for the DAC in 12-bit configura-

tion.

-

±2

±1

LSB

Given for the DAC in 10-bit configu-

ration.

Integral non linearity (difference

between measured value at

(4)

INL

Code i and the value at Code i

on a line drawn between Code 0

and last Code 1023)

Given for the DAC in 12-bit configu-

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Page 33 of 43

SN820X - 02/28/14

Table 3.8.2: DAC Characteristic, SN8205/8205UFL (Continued)

Symbol

Parameter

Min

Ty

M

Unit

Comments

Offset error

(difference between

measured value at Code

(0x800) and the ideal value =

VREF+/2)

Given for the DAC in 12-bit configu-

ration

Offset⁽⁴⁾

-

±10

±3

mV

LSB

%

Given for the DAC in 10-bit at

VREF+ = 3.6 V

Given for the DAC in 12-bit at

VREF+ = 3.6 V

±12

±0.5

Gain error

Given for the DAC in 12-bit configu-

ration

Gain error⁽⁴⁾

Settling time (full scale: for a 10-bit

input code transition between the

lowest and the highest input codes

when DAC_OUT reaches final

value ±4LSB

(4)

t_SETTLING

C

_LOAD≤ 50 pF,

_LOAD≥ 5 kΩ

-

3

6

µs

R

Total Harmonic Distortion

Buffer ON

C_LOAD≤ 50 pF,

_LOAD≥ 5 kΩ

C_LOAD≤ 50 pF,

_LOAD≥ 5 kΩ

THD⁽⁴⁾

-

dB

R

Max frequency for a correct

DAC_OUT change when

small variation in the input

code (from code i to i+1LSB)

Update rate⁽²⁾

MS/s

R

1

C

≤ 50 pF, R

≥ 5 kΩ

LOAD

Wakeup time from off state

(Setting the ENx bit in the

DAC Control register)

t

(4)

LOAD

WAKEUP

input code between lowest and highest

possible ones.

-

6.5

10

µs

Power supply rejection ratio (to

VDDA) (static DC measurement)

PSRR+

–67

–40

dB

No RLOAD, CLOAD = 50 pF

1. If IRROFF is set to VDD, this value can be lowered to 1.7 V when the device operates in the 0 to 70 °C temperature

range.

2. Guaranteed by design, not tested in production.

3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic

consumption occurs.

4. Guaranteed by characterization, not tested in production.

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Page 34 of 43

SN820X - 02/28/14

4 RF Specifications

4.1 DC/RF Characteristics for IEEE 802.11b

Conditions: 25ºC, VDD_WIFI_IN=3.6 V, VDD= 3.3 V, 11 MBps mode unless otherwise specified. Parameters

measured at RF connector.

Table 4.1.1: RF Characteristics for IEEE 802.11b

Parameters

Specification

Standards conformance

IEEE 802.11b

Modulation

DSSS/CCK

Physical layer data rate

1,2,5.5,11 Mbps

RF Characteristics

Minimum

2400

Typical

Maximum

Unit

MHz

ppm

Frequency range

--

2483.5

+20

Carrier frequency error

-20

Transmit output power ¹

Spectrum mask

16

18

20

dBm

1^stside lobes

--

-30

-50

2

dBr

µs

2^ndside lobes

Power-on and power-down ramp

--

RF carrier suppression

15

--

dBc

%

Modulation accuracy (EVM)

Out-of-band spurious emissions

30 MHz to 1 GHz, BW=100 kHz

1 GHz to 12.75 GHz, BW=1 MHz

1.8 GHz to 1.9 GHz, BW=1 MHz

5.15 GHz to5.3 GHz, BW=1 MHz

35

-96

-41

-65

-85

dBm

Receive sensitivity ¹

1 Mbps, FER≤ 8%

11 Mbps, FER≤ 8%

-94

-86

-9.5

35

-96

-88

--

dBm

dB

Maximum input level, FER≤ 8%

Adjacent channel rejection, FER≤ 8%

Notes:

1. Derate by 1.5 dB for temperatures less than -10ºC or more than +55ºC in both transmit and receive modes.

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SN820X - 02/28/14

4.2 DC/RF Characteristics for IEEE 802.11g

Conditions: 25ºC, VDD_WIFI_IN=3.6 V, VDD= 3.3 V, 54 Mbps mode unless otherwise specified. Parameters

measured at RF connector.

Table 4.2.1: RF Characteristics for IEEE 802.11g

Parameters

Specification

Standards conformance

IEEE 802.11g

Modulation

Data rate

OFDM

6, 9, 12, 18, 24, 36, 48, 54 Mbps

RF Characteristics

Minimum

Typical

Maximum

Unit

Frequency range

2400

--

2483.5

MHz

Carrier frequency error

-20

--

+20

ppm

dBm

Transmit output power¹

Spectrum mask

12.5

14.5

16.5

9 MHz to 11 MHz, 0 dB to -20 dB

11 MHz to 20 MHz, -20 dB to -28 dB

20 MHz to 30 MHz, -28 dB to -40 dB

30 MHz to 33 MHz, -40 dB

0

--

-

dB

-

Constellation Error (EVM)

--

-25

Out-of-band spurious emissions

30 MHz to 1 GHz, BW=100 kHz

1 GHz to 12.75 GHz, BW=1 MHz

1.8 GHz to 1.9 GHz, BW=1 MHz

5.15 GHz to5.3 GHz, BW=1 MHz

-96

-41

-65

-85

dBm

Received Sensitivity¹

6 Mbps, PER ≤ 10%

-87

-72

-13

-1

-89

-74

--

dBm

dB

54 Mbps, PER ≤ 10%

Maximum input level, PER ≤ 10%

Adjacent channel rejection, PER ≤ 10%

Notes:

1. Derate by 1.5 dB for temperatures less than -10ºC or more than +55ºC in both transmit and receive modes.

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Page 36 of 43

SN820X - 02/28/14

4.3 DC/RF Characteristics for IEEE 802.11n

Conditions: 25º C, VDD_WIFI_IN=3.6 V, VDD= 3.3 V, 65 Mbps mode unless otherwise specified. Parameters

measured at RF connector.

Table 4.3.1: RF Characteristics for IEEE 802.11n

Parameters

Standards conformance

Specification

IEEE 802.11n

Modulation

Data rate

OFDM

6.5, 13, 19.5, 26, 39, 52, 58.5, 65 Mbps

RF Characteristics

Minimum

Typical

Maximum

Unit

Frequency range

2400

--

2483.5

MHz

Carrier frequency error

-20

11

--

+20

15

Ppm

dBm

Transmit Output Power¹

Spectrum mask

13

9 MHz to 11 MHz, 0 dB to -20 dB

11 MHz to 20 MHz, -20 dB to -28 dB

20 MHz to 30 MHz, -28 dB to -45 dB

30 MHz to 33 MHz, -45 dB

0

--

-

dB

-

Constellation Error (EVM)

--

-28

Out-of-band spurious emissions

30 MHz to 1 GHz, BW=100 kHz

1 GHz to 12.75 GHz, BW=1 MHz

1.8 GHz to 1.9 GHz, BW=1 MHz

5.15 GHz to 5.3 GHz, BW=1 MHz

-96

-41

-65

-85

dBm

Received Minimum Sensitivity¹

65 Mbps, PER ≤ 10%

-69

-13

-2

-71

--

dBm

dB

Maximum input level, PER ≤ 10%

Adjacent channel rejection, PER ≤ 10%

dB

Notes:

1. Derate by 1.5 dB for temperatures less than -10ºC or more than +55ºC in both transmit and receive modes.

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Page 37 of 43

SN820X - 02/28/14

5 Environmental Specifications

5.1 Absolute Maximum Rating

Table 5.1: Absolute Maximum Rating

Symbol

Description

Minimum

Maximum

Unit

Specification operating temperature

-30

85

°C

T_sop

T_op*

T_st

Operating temperature

Storage temperature

-40

85

°C

VDD_IO

VDD_BAT

RFin

IO Power supply

0

3.6

5.0

0

V

Power supply

RF input power

dBm

MSL

Moisture Sensitivity Level

Restriction of Hazardous Substances

3

RoHS2

Compliant

*Note: RF performance may be degraded at exterme temperatures.

5.2 Recommended Operating Conditions

Table 5.2: Recommended Operating Conditions

SupplyCurrent

Specification

(mA)

Minimum (V)

Typical (V)

Maximum (V)

VDD

2.4

2.0

3.0

3.3

3.6

4.0

150

10

VBAT

VDD_WiFi

500

www.murata-ws.com E-mail: modules@murata.com

Page 38 of 43

SN820X - 02/28/14

6 Regulatory Information

The table below shows the regulatory compliance status of the SN820X Module family.

Regulatory Body

Standard

CFR Part 15

RSS-210

Certificate ID

QPU8200

FCC

IC

4523A-SN8200

Compliant

CE

For more information refer to the SN820X Wi-Fi Network Controller Module Family User Manual, reference [3],

on page 7.

www.murata-ws.com E-mail: modules@murata.com

Page 39 of 43

SN820X - 02/28/14

7 Packing and Marking Information

7.1 Carrier Tape Dimensions

FIGURE 7.1 SN820X/820XUFL Carrier Tape Dimensions

7.2 Module Marking Information

The following marking information may be printed on a permanent label affixed to the module shield or perma-

nently laser written into the module shield itself. The 2D barcode is used for internal purposes. A pin 1 ID is

stamped into the shield. The Model will vary according to the module used - SN8200, SN8200UFL, SN8205,

SN8205UFL, however the FCC ID and IC certification numbers apply to all modules in the SN820X Family.

FIGURE 7.2 Typical SN820X/820XUFL module marking

www.murata-ws.com E-mail: modules@murata.com

Page 40 of 43

SN820X - 02/28/14

8 RoHS Delcaration

To the best of our present knowledge, given our supplier declarations, this product does not contain sub-

stances that are banned by Directive 2002/95/EC or contain a maximum concentration of 0.1% by weight in

homogeneous materials for

• Lead and lead compounds

• Mercury and mercury compounds

• Chromium (VI)

• PBB (polybrominated biphenyl)

• PBDE (polybrominated biphenyl ether)

And a maximum concentration of 0.01% by weight in homogeneous materials for

• Cadmium and cadmium compounds

www.murata-ws.com E-mail: modules@murata.com

Page 41 of 43

SN820X - 02/28/14

9 Ordering Information

Table 9.1: SN8200/8200UFL Ordering Information

RFM Model

RFM Part

Number

Standard Order

Increment

Product

Number

SN8200 Evaluation Kit

SN8200 EVK+

SN8200

88-00151-95

88-00151-00

88-00151-97

88-00151-02

1 pc

SN8200 Module in Tape & Reel

SN8200UFL Evaluation Kit

SN8200UFL Module in Tape & Reel

400 pcs

1 pc

SN8200UFL EVK+

SN8200UFL

400 pcs

Table 9.2: SN8205/8205UFL Ordering Information

RFM Model

RFM Part

Number

Standard Order

Increment

Product

Number

SN8205 EVK+

SN8205

SN8205 Evaluation Kit

88-00158-95

1 pc

SN8205 Module in Tape & Reel

SN8205UFL Evaluation Kit

88-00158-00

88-00158-97

88-00158-02

400 pcs

1 pc

SN8205UFL EVK+

SN8205UFL

SN8205UFL Module in Tape & Reel

400 pcs

www.murata-ws.com E-mail: modules@murata.com

Page 42 of 43

SN820X - 02/28/14

10 Technical Support Contact

For technical support, please contact tech_sup@murata.com

Murata Electronics, N.A., Inc.

4441 Sigma Road

Dallas, TX 75244

USA

www.murata-ws.com E-mail: modules@murata.com

Page 43 of 43

SN820X - 02/28/14


型号：	SN8205UFL
厂家：	muRata
描述：	Telecom Circuit, 电信电信集成电路
文件：	总43页 (文件大小：1988K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SN8205UFL [MURATA]

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