MUAD8K136-66B272C [MUSIC]
Content Addressable SRAM, 4KX272, CMOS, PBGA272, BGA-272;
| 型号： | MUAD8K136-66B272C |
| 厂家： | 
MUSIC SEMICONDUCTORS |
| 描述： | Content Addressable SRAM, 4KX272, CMOS, PBGA272, BGA-272 双倍数据速率 静态存储器 内存集成电路 |
| 文件： | 总36页 (文件大小：919K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Advance Information
MUAD "Harmony" 2M and 1M Ternary CAMs
*(1(5$/ꢀ'(6&5,37,21
)($785(6
The MUAD "Harmony" Ternary CAM is a fast look-up
table device supporting ternary (0, 1, don’t care) elements
for networking and communication applications. Harmony
is a member of MUSIC Semiconductors RouteCAM
family.
•
•
•
•
16K and 8K x 136-bit full ternary CAMs
Configurable as 8K/4K x 272 or 32K/16K x 68
68-bit interface operates at 13.6Gbit/sec
Sustains 100 million searches per second on a 68-bit
or 136-bit field
The organization of the Harmony 2M part is 16K x 136
bits, and the 1M part is 8K x 136-bit wide, with
double-word and half-word options.
•
50 million searches per second in 272-bit
configuration
•
•
•
Holds multiple word widths within the same device
Synchronous pipelined operation
Harmony is ideally suited for high-speed, high-capacity
functions, including Ethernet and IP address search, data
Up to eight CAMs cascadable without performance
degradation or additional logic
compression,
pattern
recognition,
cache
tags,
high-bandwidth address filtering, and fast routing search
tables. These functions also include privileged, secured, or
encrypted packet-by-packet information utilized in
high-performance Internet equipment such as switches,
firewalls, bridges, and routers.
•
Glueless interface to industry-standard synchronous
SRAMs
•
•
•
Supports IEEE 1149.1 Test Access
1.8 and 3.3V power supply
272-pin BGA package
The flexibility of the Harmony device allows the creation
of multiple search tables within the same device. It
compares, simultaneously, the desired information (data)
against an entire, pre-stored, array of addresses, providing
a performance advantage by reducing search times an
order-of-magnitude over typical binary or tree-based
search algorithms. The Harmony device can be designed
into many applications, but it is particularly well suited to
perform highly intensive search operations.
/TRST
TCLK
TMS
TDI
TDO
CSO[1:0]
/SEN[3:0]
CAM
Cascade
CSI[6:0]
UID[4:0]
MF
/MM
MV
FF
FI[6:0]
CLK
PHASE
/RST
Controller
/ACK
EOT
FO[1:0]
OP[8:0]
OPV
SADR[21:0]
/OE
High-Speed
Interface
SRAM
Interface
/WE
/CE
DQ[67:0]
/ALE
SCLK
+DUPRQ\ꢀ%ORꢁNꢀ'LDJUDP
086,&ꢀ6HPLꢁRQGXꢁWRUVꢂꢀWKHꢀ086,&ꢀORJRꢂꢀDQGꢀWKHꢀSKUDVHꢀꢃ086,&ꢀ6HPLꢁRQGXꢁWRUVꢃꢀDUH
5HJLVWHUHGꢀWUDGHPDUNVꢀRIꢀ086,&ꢀ6HPLꢁRQGXꢁWRUVꢇꢀ086,&ꢀLVꢀDꢀWUDGHPDUNꢀRI
086,&ꢀ6HPLꢁRQGXꢁWRUVꢇ
$SULOꢀꢄꢅꢂꢀꢅꢆꢆꢄꢀ5HYꢇꢀꢆD
08$'ꢀꢁ+DUPRQ\ꢁꢀꢂ0ꢀDQGꢀꢃ0ꢀ7HUQDU\ꢀ&$0V
$SULOꢀꢄꢅꢂꢀꢅꢆꢆꢄꢀ5HYꢇꢀꢆD
&217(176ꢀ
%DOOꢀ'HVꢄULSWLRQVꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢂ
)XQꢄWLRQDOꢀ'HVꢄULSWLRQꢀꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢆ
&RQWHQWꢀ$GGUHVVDEOHꢀ0HPRU\ꢀ ꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢆ
7KHꢀ,ꢇ2ꢀ,QWHUIDꢄHꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢆ
65$0ꢀ,QWHUIDꢄHꢀ ꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢆ
65$0ꢀ$GGUHVVLQJꢀ ꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢆ
,QVWUXꢄWLRQꢀ%XVꢀDQGꢀ'4ꢀ%XVꢀ ꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢆ
'XDOꢀ'DWDꢀ5DWHꢀ&ORꢄNꢀ ꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢆ
&DVꢄDGHꢀ&RQWUROꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢆ
3RZHUꢀ0DQDJHPHQWꢀ ꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢈ
7HVWꢀ$ꢄꢄHVVꢀ3RUWꢀ ꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢈ
,QLWLDOL]DWLRQꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢈ
'HSWKꢉ&DVꢄDGLQJꢀꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢈ
$UELWUDWLRQꢀ ꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢈ
6HDUꢄKꢀ/ꢊꢋꢉELWꢀ&RQILJXUDWLRQꢀZLWKꢀꢌ&$0ꢀ ꢀꢃꢍꢀꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢊ
6HDUꢄKꢀ/ꢊꢋꢉELWꢀ&RQILJXUDWLRQꢀZLWKꢀꢌ5$0ꢀ ꢀꢃꢍꢀꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢊ
'HSWKꢉ&DVꢄDGLQJꢀWRꢀ*HQHUDWHꢀ)XOOꢀꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢊ
+DUPRQ\ꢀ7DEOHꢀ&RQILJXUDWLRQꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢊ
0XOWLSOHꢀ6HDUꢄKꢀ7DEOHꢀ&RQILJXUDWLRQꢀ ꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢊ
0XOWLSOHꢀꢌRJLꢄDOꢀ7DEOHVꢀRIꢀ'LIIHUHQWꢀ:LGWKVꢀ ꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢎ
'HSWKꢀ&DVꢄDGLQJꢀWRꢀ&UHDWHꢀꢌDUJHUꢀꢌRJLꢄDOꢀ7DEOHVꢀ ꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢎ
5HJLVWHUꢀ'HVꢄULSWLRQVꢀ ꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢋ
&RPSDUDQGꢀ5HJLVWHUVꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢏ
*OREDOꢀ0DVNꢀ5HJLVWHUVꢀ ꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢏ
5HVXOWꢀ5HJLVWHUVꢀ ꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢃꢐ
,QVWUXꢄWLRQꢀ5HJLVWHUꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢃꢐ
,QIRUPDWLRQꢀ5HJLVWHUꢀ ꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢃꢃ
%XUVWꢀ5HDGꢀ$GGUHVVꢀ5HJLVWHUꢀ ꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢃꢃ
%XUVWꢀ:ULWHꢀ$GGUHVVꢀ5HJLVWHUꢀ ꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢃꢃ
1H[Wꢀ)UHHꢀ$GGUHVVꢀ5HJLVWHUꢀ ꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢃꢂ
&RQILJXUDWLRQꢀ5HJLVWHUꢀꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢃꢂ
+DUPRQ\ꢀ,QVWUXꢄWLRQVꢀ ꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢃꢑ
,QVWUXꢄWLRQꢀ&RGHVꢀꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢃꢑ
,QVWUXꢄWLRQVꢀDQGꢀ,QVWUXꢄWLRQꢀ3DUDPHWHUVꢀ ꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢃꢑ
5($'ꢀ,QVWUXꢄWLRQꢀ ꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢃꢆ
6,1*ꢌ(ꢀ5($'ꢀ,QVWUXꢄWLRQꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢃꢆ
%8567ꢀ5($'ꢀ,QVWUXꢄWLRQꢀꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢃꢆ
:5,7(ꢀ,QVWUXꢄWLRQꢀ ꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢃꢈ
6,1*ꢌ(ꢀ:5,7(ꢀ,QVWUXꢄWLRQꢀ ꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢃꢈ
%8567ꢀ:5,7(ꢀ,QVWUXꢄWLRQꢀ ꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢃꢈ
6($5&+ꢀ,QVWUXꢄWLRQVꢀ ꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢃꢎ
)XOOꢀ:RUGꢀ6HDUꢄKHVꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢃꢎ
+DOIꢉ:RUGꢀ6HDUꢄKHVꢀ ꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢃꢎ
'RXEOHꢉ:RUGꢀ6HDUꢄKHVꢀ ꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢃꢎ
:ULWHꢀ1H[Wꢀ)UHHꢀ$GGUHVVꢀ ꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢃꢋ
65$0ꢀ$GGUHVVLQJꢀ ꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢃꢋ
65$0ꢀ5($'ꢀRUꢀ:5,7(ꢀ$ꢄꢄHVVHVꢀ ꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢃꢋ
65$0ꢀ5($'ꢀ ꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢃꢋ
65$0ꢀ:5,7(ꢀ ꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢃꢋ
$SSOLꢄDWLRQꢀ,QIRUPDWLRQꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢂꢐ
ꢑꢆꢉ%LWꢀ:RUGꢀ$SSOLꢄDWLRQVꢀ ꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢂꢐ
7LPLQJꢀ'LDJUDPVꢀ ꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢂꢃ
i
&RQWHQWV
08$'ꢀꢁ+DUPRQ\ꢁꢀꢃ0ꢀDQGꢀꢂ0ꢀ7HUQDU\ꢀ&$0V
6LQJOHꢀꢌRꢄDWLRQꢀ5HDGꢀ7LPLQJꢀ'LDJUDPꢀ ꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢂꢃ
:ULWHꢀ&\ꢄOHꢀ7LPLQJꢀ'LDJUDPꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢂꢃ
'DWDꢀDQGꢀ0DVNꢀ5($'ꢀ/%ꢌ(1ꢀ ꢀꢆꢍꢀIRUꢀDꢀ*URXSꢀRIꢀ&DVꢄDGHGꢀ'HYLꢄHVꢀ7LPLQJꢀ'LDJUDPꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢂꢂ
'DWDꢀDQGꢀ0DVNꢀ:5,7(ꢀ/%ꢌ(1ꢀ ꢀꢆꢍꢀIRUꢀDꢀ*URXSꢀRIꢀ&DVꢄDGHGꢀ'HYLꢄHVꢀ7LPLQJꢀ'LDJUDPꢀ ꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢂꢂ
ꢊꢋꢉ%LWꢀ6($5&+ꢀ2SHUDWLRQꢀ7LPLQJꢀ'LDJUDPꢀ ꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢂꢑ
ꢃꢑꢊꢉ%LWꢀ6($5&+ꢀ2SHUDWLRQꢀ7LPLQJꢀ'LDJUDPꢀ ꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢂꢆ
ꢂꢎꢂꢉ%LWꢀ6($5&+ꢀ2SHUDWLRQꢀ7LPLQJꢀ'LDJUDPꢀ ꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢂꢈ
$UELWUDWLRQꢀIRUꢀDꢀ*URXSꢀRIꢀ&DVꢄDGHGꢀ'HYLꢄHVꢀ7LPLQJꢀ'LDJUDPꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢂꢊ
:5,7(ꢀ7LPLQJꢀ'LDJUDPꢀꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢂꢊ
65$0ꢀ5($'ꢀ&\ꢄOHꢀ7LPLQJꢀ'LDJUDPꢀꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢂꢎ
65$0ꢀ:5,7(ꢀ&\ꢄOHꢀ7,PLQJꢀ'LDJUDPꢀ ꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢂꢋ
$&ꢀ7LPLQJꢀ:DYHIRUPVꢀꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢂꢏ
(OHꢄWULꢄDOꢀ6SHꢄLILꢄDWLRQVꢀꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢑꢐ
(OHꢄWULꢄDOꢀ&KDUDꢄWHULVWLꢄVꢀ ꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢑꢐ
&DSDꢄLWDQꢄHꢀꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢑꢐ
2SHUDWLQJꢀ&RQGLWLRQVꢀꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢑꢐ
3DꢄNDJHꢀ ꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢑꢃ
ꢂꢎꢂꢉ3LQꢀ%*$ꢀ'LPHQVLRQVꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅ ꢑꢃ
2UGHULQJꢀ ꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢀꢅꢑꢂ
LL
%DOOꢀ'HVꢁULSWLRQV
08$'ꢀꢂ+DUPRQ\ꢂꢀꢃ0ꢀDQGꢀꢄ0ꢀ7HUQDU\ꢀ&$0V
1&
1&
'4ꢅꢆ
'4ꢆꢈ
'4ꢆꢇ
9''
9''4
'4ꢉꢇ
'4ꢇꢈ
'4ꢇꢃ
9''
'4ꢄꢈ
'4ꢄꢃ
'4ꢃꢈ
9''
1&
9''4
'4ꢇ
1&
1&
$ꢃ
$ꢄ
$ꢇ
$ꢉ
$ꢆ
$ꢅ
$ꢈ
$ꢊ
$ꢋ
$ꢃꢌ
$ꢃꢃ
$ꢃꢄ
$ꢃꢇ
$ꢃꢉ
$ꢃꢆ
$ꢃꢅ
$ꢃꢈ
1&
$ꢃꢊ
$ꢃꢋ
1&
$ꢄꢌ
1&
9''
1&
'4ꢅꢃ
1&
'4ꢉꢋ
'4ꢆꢃ
'4ꢉꢆ
9''
'4ꢇꢇ
'4ꢄꢋ
'4ꢄꢆ
9''4
'4ꢃꢆ
'4ꢃꢇ
'4ꢈ
9''
6$'5ꢃ
%ꢃ
%ꢄ
%ꢇ
%ꢉ
%ꢆ
%ꢅ
%ꢈ
%ꢊ
%ꢋ
%ꢃꢌ
%ꢃꢃ
1&
%ꢃꢄ
%ꢃꢇ
%ꢃꢉ
1&
%ꢃꢆ
%ꢃꢅ
%ꢃꢈ
1&
%ꢃꢊ
%ꢃꢋ
%ꢄꢌ
7'2
7',
1&
'4ꢅꢇ
'4ꢆꢋ
'4ꢆꢆ
9''4
1&
'4ꢇꢋ
'4ꢇꢆ
'4ꢄꢇ
'4ꢃꢋ
'4ꢃꢃ
'4ꢆ
6$'5ꢌ
6$'5ꢇ
6$'5ꢄ
&ꢃ
&ꢄ
&ꢇ
&ꢉ
&ꢆ
&ꢅ
&ꢈ
&ꢊ
&ꢋ
&ꢃꢌ
&ꢃꢃ
&ꢃꢄ
1&
&ꢃꢇ
&ꢃꢉ
&ꢃꢆ
&ꢃꢅ
&ꢃꢈ
&ꢃꢊ
1&
&ꢃꢋ
&ꢄꢌ
8,'ꢌ
706
7&.
*1'
'4ꢅꢈ
9''4
'4ꢉꢈ
*1'
'4ꢉꢃ
9''4
9''4
*1'
9''4
'4ꢋ
'4ꢃ
*1'
6$'5ꢉ
9''4
'ꢃ
'ꢄ
'ꢇ
'ꢉ
'ꢆ
'ꢅ
'ꢈ
'ꢊ
'ꢋ
'ꢃꢌ
'ꢃꢃ
'ꢃꢄ
'ꢃꢇ
'ꢃꢉ
'ꢃꢆ
'ꢃꢅ
'ꢃꢈ
'ꢃꢊ
'ꢃꢋ
1&
'ꢄꢌ
8,'ꢄ
8,'ꢇ
8,'ꢃ
ꢍ7567
9''4
6$'5ꢅ
6$'5ꢊ
(ꢃ
(ꢄ
(ꢇ
(ꢉ
(ꢃꢈ
(ꢃꢊ
(ꢃꢋ
(ꢄꢌ
9''
&6,ꢄ
&6,ꢌ
8,'ꢉ
6$'5ꢆ
6$'5ꢈ
6$'5ꢃꢃ
9''
)ꢃ
)ꢄ
)ꢇ
)ꢉ
)ꢃꢈ
)ꢃꢊ
)ꢃꢋ
)ꢄꢌ
1&
&6,ꢇ
9''4
&6,ꢃ
9''4
6$'5ꢋ
6$'5ꢃꢌ
6$'5ꢃꢇ
*ꢃ
*ꢄ
*ꢇ
*ꢉ
*ꢃꢈ
*ꢃꢊ
*ꢃꢋ
1&
*ꢄꢌ
&6,ꢅ
&6,ꢆ
&6,ꢉ
*1'
*1'
6$'5ꢃꢄ
6$'5ꢃꢉ
+ꢃ
+ꢄ
+ꢇ
+ꢉ
+ꢃꢈ
+ꢃꢊ
+ꢃꢋ
+ꢄꢌ
%+,ꢌ
9''4
&62ꢃ
&62ꢌ
*1'
*1'
*1'
*1'
6$'5ꢃꢆ
6$'5ꢃꢅ
9''4
6$'5ꢃꢈ
-ꢃ
-ꢄ
-ꢇ
-ꢉ
-ꢋ
-ꢃꢌ
-ꢃꢃ
-ꢃꢄ
-ꢃꢈ
-ꢃꢊ
-ꢃꢋ
-ꢄꢌ
9''
%+,ꢄ
9''
%+,ꢃ
*1'
*1'
*1'
*1'
9''
6$'5ꢃꢊ
6$'5ꢃꢋ
6$'5ꢄꢌ
.ꢃ
.ꢄ
.ꢇ
.ꢉ
.ꢋ
.ꢃꢌ
.ꢃꢃ
.ꢃꢄ
.ꢃꢈ
&/.
.ꢃꢊ
.ꢃꢋ
.ꢄꢌ
%+2ꢌ
%+2ꢃ
%+2ꢄ
),ꢌ
*1'
*1'
*1'
*1'
6$'5ꢄꢃ
9''4
9''
/ꢃ
/ꢄ
/ꢇ
/ꢉ
/ꢋ
/ꢃꢌ
/ꢃꢃ
/ꢃꢄ
/ꢃꢈ
/ꢃꢊ
ꢍ2(
/ꢃꢋ
/ꢄꢌ
),ꢃ
),ꢄ
9''4
),ꢇ
*1'
*1'
*1'
*1'
ꢍ:(
3+$6(
6&/.
0ꢃ
),ꢉ
0ꢄ
),ꢅ
0ꢇ
1&
0ꢉ
0ꢋ
0ꢃꢌ
0ꢃꢃ
0ꢃꢄ
0ꢃꢈ
0ꢃꢊ
0ꢃꢋ
0ꢄꢌ
ꢍ&(
*1'
*1'
ꢍ$/(
9''4
1ꢃ
1ꢄ
1ꢇ
1ꢉ
1ꢃꢈ
23ꢄ
1ꢃꢊ
23ꢌ
1ꢃꢋ
1ꢄꢌ
1&
),ꢆ
1&
1&
)2ꢌ
239
3ꢃ
3ꢄ
3ꢇ
3ꢉ
3ꢃꢈ
3ꢃꢊ
3ꢃꢋ
3ꢄꢌ
9''
)2ꢃ
9''4
1&
23ꢉ
23ꢇ
23ꢃ
9''
5ꢃ
5ꢄ
5ꢇ
5ꢉ
5ꢃꢈ
1&
5ꢃꢊ
23ꢅ
5ꢃꢋ
23ꢆ
5ꢄꢌ
1&
1&
9''
ꢍ567
9''4
7ꢃ
7ꢄ
))
7ꢇ
7ꢉ
7ꢃꢈ
7ꢃꢊ
0)
7ꢃꢋ
09
7ꢄꢌ
1&
9''4
*1'
'4ꢅꢅ
'4ꢆꢊ
'4ꢆꢉ
*1'
'4ꢉꢉ
'4ꢇꢊ
'4ꢇꢌ
'4ꢄꢅ
*1'
9''4
'4ꢅ
'4ꢌ
*1'
23ꢈ
8ꢃ
8ꢄ
8ꢇ
8ꢉ
8ꢆ
8ꢅ
8ꢈ
8ꢊ
8ꢋ
8ꢃꢌ
8ꢃꢃ
8ꢃꢄ
8ꢃꢇ
8ꢃꢉ
8ꢃꢆ
8ꢃꢅ
8ꢃꢈ
8ꢃꢊ
8ꢃꢋ
ꢍ00
8ꢄꢌ
23ꢊ
(27
ꢍ$&.
ꢍ6(1ꢇ
9''
ꢍ6(1ꢄ
'4ꢆꢅ
'4ꢆꢄ
'4ꢉꢊ
9''4
'4ꢇꢅ
'4ꢇꢄ
9''4
'4ꢄꢌ
'4ꢃꢉ
9''4
'4ꢊ
9''4
9''
9ꢃ
9ꢄ
9ꢇ
9ꢉ
9ꢆ
9ꢅ
9ꢈ
9ꢊ
9ꢋ
9ꢃꢌ
1&
9ꢃꢃ
9ꢃꢄ
9ꢃꢇ
9ꢃꢉ
9ꢃꢆ
9ꢃꢅ
9ꢃꢈ
1&
9ꢃꢊ
9ꢃꢋ
1&
9ꢄꢌ
1&
*1'
1&
ꢍ6(1ꢃ
ꢍ6(1ꢌ
9''4
1&
9''4
'4ꢉꢅ
'4ꢉꢄ
'4ꢇꢉ
'4ꢄꢊ
9''
'4ꢃꢅ
'4ꢃꢊ
'4ꢃꢄ
'4ꢉ
:ꢃ
1&
:ꢄ
1&
:ꢇ
:ꢉ
:ꢆ
:ꢅ
:ꢈ
:ꢊ
1&
:ꢋ
:ꢃꢌ
9''
:ꢃꢃ
:ꢃꢄ
1&
:ꢃꢇ
:ꢃꢉ
:ꢃꢆ
9''
:ꢃꢅ
1&
:ꢃꢈ
:ꢃꢊ
'4ꢄ
:ꢃꢋ
1&
:ꢄꢌ
1&
'4ꢅꢉ
'4ꢅꢄ
'4ꢅꢌ
9''
'4ꢆꢌ
'4ꢉꢌ
9''4
'4ꢄꢉ
'4ꢄꢄ
'4ꢃꢌ
<ꢃ
<ꢄ
<ꢇ
<ꢉ
<ꢆ
<ꢅ
<ꢈ
<ꢊ
<ꢋ
<ꢃꢌ
<ꢃꢃ
<ꢃꢄ
<ꢃꢇ
<ꢃꢉ
<ꢃꢆ
<ꢃꢅ
<ꢃꢈ
<ꢃꢊ
<ꢃꢋ
<ꢄꢌ
Figure 1: Connection Diagram
5HYꢀꢁꢂDꢁ$SULOꢁꢃꢄꢅꢁꢄꢂꢂꢃ
ꢃ
08$'ꢀꢁ+DUPRQ\ꢁꢀꢂ0ꢀDQGꢀꢃ0ꢀ7HUQDU\ꢀ&$0V
%DOOꢀ'HVꢄULSWLRQV
%$//ꢁ'(6&5,37,216
This section lists and describes the Harmony signals.
7DEOHꢁꢂꢆꢁ08$'ꢁ+DUPRQ\ꢁ%DOOꢁ'HVꢇULSWLRQV
6\PERO
7\SH 'HVꢇULSWLRQ
3LQꢁ1XPEHUꢈV)
&ORꢇNVꢁDQGꢁ5HVHW
&/.
,
0DVWHUꢁ&ORꢇNꢅꢀ+DUPRQ\ꢀVDPSOHVꢀDOOꢀWKHꢀꢄRQWUROꢀDQGꢀGDWDꢀ
VLJQDOVꢀHLWKHUꢀRQꢀWKHꢀSRVLWLYHꢀHGJHꢀRIꢀ&/.#ꢀRUꢀRQꢀWKHꢀSRVLWLYHꢀ
RIꢀ&/.ꢀZKHQꢀ3+$6(ꢀLVꢀORZꢅ
/ꢂꢆ
3+$6(
6&/.
ꢉ567
,
2
,
3+$6(ꢅꢀ7KLVꢀVLJQDOꢀUXQVꢀDWꢀKDOIꢀWKHꢀIUHTXHQꢄ\ꢀRIꢀ&/.ꢀDQGꢀ 0ꢂꢇ
JHQHUDWHVꢀDQꢀLQWHUQDOꢀꢄORꢄNꢀIURPꢀ&/.ꢅ
65$0ꢁ&ORꢇNꢅꢀ7KLVꢀVLJQDOꢀJHQHUDWHVꢀꢄORꢄNꢀIRUꢀWKHꢀH[WHUQDOꢀ 0ꢃꢈ
65$0ꢀEXVꢅꢀ,WꢀUXQVꢀDWꢀKDOIꢀWKHꢀVSHHGꢀRIꢀWKHꢀLQSXWꢀ&/.ꢅ
5HVHWꢅꢀ'ULYLQJꢀꢉ567ꢀORZꢀLQLWLDOL]HVꢀWKHꢀGHYLꢄHꢀWRꢀDꢀNQRZQꢀ
7ꢊ
VWDWHꢅꢀ
,QVWUXꢇWLRQꢁDQGꢁ'4ꢁ%XV
23>ꢋꢌꢈ@
,
,QVWUXꢇWLRQꢁ%XVꢅꢀ23>ꢂꢌꢈ@ꢀVSHꢄLI\ꢀWKHꢀLQVWUXꢄWLRQꢅꢀ23>ꢋꢌꢃ@ꢀ
ꢄRQWDLQꢀWKHꢀLQVWUXꢄWLRQꢀSDUDPHWHUVꢅꢀ7KHꢀGHVꢄULSWLRQVꢀRIꢀ
LQGLYLGXDOꢀLQVWUXꢄWLRQVꢀH[SODLQꢀWKHꢀGHWDLOVꢀRIꢀWKHꢀSDUDPHWHUVꢅꢀ
7KHꢀHQꢄRGLQJꢀRIꢀLQVWUXꢄWLRQVꢀEDVHGꢀRQꢀWKHꢀ>ꢂꢌꢈ@ꢀILHOGVꢀDUHꢌꢀ
ꢈꢈꢌ5($'ꢀ
%ꢈꢌ3ꢂꢋ#ꢀ%ꢂꢌ5ꢂꢇ#ꢀ%ꢃꢌ3ꢂꢆ#ꢀ%ꢍꢌ5ꢂꢋ#ꢀ%ꢊꢌ5ꢂꢆ#ꢀ%ꢎꢌ7ꢂꢇ#ꢀ%ꢏꢌ7ꢂꢋ#ꢀ
%ꢆꢌ8ꢃꢈ#ꢀ%ꢋꢌ9ꢃꢈ
ꢈꢂꢌ:5,7(ꢀ
ꢂꢈꢌ6($5&+ꢀ
ꢂꢂꢌ:5,7(ꢀ1(;7ꢀ)5((ꢀ$''5(66ꢀ
2Sꢁ&RGHꢁ9DOLGꢅꢀ239ꢀTXDOLILHVꢀWKHꢀ,QVWUXꢄWLRQꢀEXVꢅꢀ
ꢈꢌ1Rꢀ,QVWUXꢄWLRQ#ꢀꢂꢌ,QVWUXꢄWLRQꢀ
239
,
3ꢂꢇ
'4>ꢏꢆꢌꢈ@
,ꢉ2 $GGUHVVꢉ'DWDꢁ%XVꢅꢀ'4>ꢏꢆꢌꢈ@ꢀꢄDUULHVꢀWKHꢀUHDGꢀDQGꢀZULWHꢀ
DGGUHVVꢀDQGꢀGDWDꢀGXULQJꢀUHJLVWHU#ꢀGDWD#ꢀDQGꢀPDVNꢀDUUD\ꢀ
RSHUDWLRQVꢅꢀ,WꢀꢄDUULHVꢀWKHꢀꢄRPSDUHꢀGDWDꢀGXULQJꢀVHDUꢄKꢀ
%ꢈꢌ8ꢂꢏ#ꢀ%ꢂꢌ'ꢂꢏ#ꢀ%ꢃꢌ<ꢂꢋ#ꢀ%ꢍꢌ$ꢂꢋ#ꢀ%ꢊꢌ:ꢂꢋ#ꢀ%ꢎꢌ&ꢂꢏ#ꢀ%ꢏꢌ8ꢂꢎ#ꢀ
%ꢆꢌ%ꢂꢏ#ꢀ%ꢋꢌ9ꢂꢏ#ꢀ%ꢇꢌ'ꢂꢎ#ꢀ%ꢂꢈꢌ<ꢂꢆ#ꢀ%ꢂꢂꢌ&ꢂꢎ#ꢀ%ꢂꢃꢌ:ꢂꢏ#ꢀ
%ꢂꢍꢌ%ꢂꢎ#ꢀ%ꢂꢊꢌ9ꢂꢊ#ꢀ%ꢂꢎꢌ%ꢂꢊ#ꢀ%ꢂꢏꢌ:ꢂꢊ#ꢀ%ꢂꢆꢌ$ꢂꢊ#ꢀ%ꢂꢋꢌ:ꢂꢎ#ꢀ
RSHUDWLRQVꢅꢀ,WꢀDOVRꢀꢄDUULHVꢀWKHꢀ65$0ꢀDGGUHVVꢀGXULQJꢀ65$0ꢀ %ꢂꢇꢌ&ꢂꢍ#ꢀ%ꢃꢈꢌ9ꢂꢍ#ꢀ%ꢃꢂꢌ$ꢂꢍ#ꢀ%ꢃꢃꢌ<ꢂꢊ#ꢀ%ꢃꢍꢌ&ꢂꢃ#ꢀ%ꢃꢊꢌ<ꢂꢍ#ꢀ
DꢄꢄHVVHVꢅꢀ
%ꢃꢎꢌ%ꢂꢃ#ꢀ%ꢃꢏꢌ8ꢂꢃ#ꢀ%ꢃꢆꢌ$ꢂꢃ#ꢀ%ꢃꢋꢌ:ꢂꢃ#ꢀ%ꢃꢇꢌ%ꢂꢂ#ꢀ%ꢍꢈꢌ8ꢂꢂ#ꢀ
%ꢍꢂꢌ$ꢂꢈ#ꢀ%ꢍꢃꢌ9ꢂꢂ#ꢀ%ꢍꢍꢌ%ꢂꢈ#ꢀ%ꢍꢊꢌ:ꢂꢂ#ꢀ%ꢍꢎꢌ&ꢂꢈ#ꢀ%ꢍꢏꢌ9ꢂꢈ#ꢀ
%ꢍꢆꢌ$ꢇ#ꢀ%ꢍꢋꢌ8ꢂꢈ#ꢀ%ꢍꢇꢌ&ꢇ#ꢀ%ꢊꢈꢌ<ꢇ#ꢀ%ꢊꢂꢌ'ꢇ#ꢀ%ꢊꢃꢌ:ꢇ#ꢀ
%ꢊꢍꢌ$ꢋ#ꢀ%ꢊꢊꢌ8ꢇ#ꢀ%ꢊꢎꢌ%ꢋ#ꢀ%ꢊꢏꢌ:ꢋ#ꢀ%ꢊꢆꢌ'ꢆ#ꢀ%ꢊꢋꢌ9ꢋ#ꢀ%ꢊꢇꢌ%ꢏ#ꢀ
%ꢎꢈꢌ<ꢆ#ꢀ%ꢎꢂꢌ%ꢆ#ꢀ%ꢎꢃꢌ9ꢆ#ꢀ%ꢎꢍꢌ$ꢎ#ꢀ%ꢎꢊꢌ8ꢆ#ꢀ%ꢎꢎꢌ&ꢏ#ꢀ%ꢎꢏꢌ9ꢏ#ꢀ
%ꢎꢆꢌ$ꢊ#ꢀ%ꢎꢋꢌ8ꢏ#ꢀ%ꢎꢇꢌ&ꢎ#ꢀ%ꢏꢈꢌ<ꢎ#ꢀ%ꢏꢂꢌ%ꢊ#ꢀ%ꢏꢃꢌ<ꢊ#ꢀ%ꢏꢍꢌ&ꢊ#ꢀ
%ꢏꢊꢌ<ꢍ#ꢀ%ꢏꢎꢌ$ꢍ#ꢀ%ꢏꢏꢌ8ꢎ#ꢀ%ꢏꢆꢌ'ꢎ
ꢉ$&.
7
5HDGꢁ$ꢇNQRZOHGJHꢅꢀꢉ$&.ꢀLQGLꢄDWHVꢀWKDWꢀYDOLGꢀGDWDꢀLVꢀ
DYDLODEOHꢀRQꢀWKHꢀ'4ꢀEXVꢀGXULQJꢀUHJLVWHU#ꢀGDWDꢀZRUG#ꢀDQGꢀZRUGꢀ
PDVNꢀDUUD\ꢀ5($'ꢀRSHUDWLRQV#ꢀRUꢀWKHꢀGDWDꢀLVꢀDYDLODEOHꢀRQꢀWKHꢀ
65$0ꢀGDWDꢀEXVꢀGXULQJꢀ65$0ꢀ5($'ꢀRSHUDWLRQVꢅ
9ꢃ
(27
0)
7
7
7
7
,
(QGꢁRIꢁ7UDQVIHUꢅꢀ(27ꢀLQGLꢄDWHVꢀWKHꢀHQGꢀRIꢀEXUVWꢀWUDQVIHUꢀ
GXULQJꢀ5($'ꢀRUꢀ:5,7(ꢀEXUVWꢀRSHUDWLRQVꢅꢀ
9ꢂ
0DWꢇKꢁꢊODJꢅꢀ:KHQꢀDVVHUWHG#ꢀ0)ꢀLQGLꢄDWHVꢀWKDWꢀWKHꢀGHYLꢄHꢀLVꢀ 8ꢂꢋ
VHOHꢄWHGꢀLQꢀDꢀ6($5&+ꢀRSHUDWLRQꢅꢀ
09
0DWꢇKꢁꢊODJꢁ9DOLGꢅꢀ:KHQꢀDVVHUWHG#ꢀ09ꢀTXDOLILHVꢀWKHꢀ0DWꢄKꢀ 8ꢂꢇ
)ODJꢀDQGꢀ0XOWLꢐ0DWꢄKꢀ)ODJꢀVLJQDOVꢅ
ꢉ00
0XOWLꢋ0DWꢇKꢁꢊODJꢅꢀ:KHQꢀDVVHUWHG#ꢀLQGLꢄDWHVꢀWKDWꢀWZRꢀRUꢀ
9ꢂꢇ
PRUHꢀPDWꢄKHVꢀZHUHꢀIRXQGꢅ
ꢉ6(1>ꢍꢌꢈ@
6HDUꢇKꢁ(QDEOHꢅꢀꢉ6(1>ꢍꢌꢈ@ꢀꢄRQWUROVꢀZKLꢄKꢀSDJHVꢀZLWKLQꢀWKHꢀ %ꢈꢌ:ꢊ#ꢀ%ꢂꢌ:ꢍ#ꢀ%ꢃꢌ9ꢎ#ꢀ%ꢍꢌ9ꢍ
&$0ꢀDUUD\ꢀSDUWLꢄLSDWHꢀLQꢀ6($5&+ꢀRSHUDWLRQVꢅꢀ7KHVHꢀSLQVꢀ
KDYHꢀSXOOꢐGRZQꢀUHVLVWRUV#ꢀVRꢀWKH\ꢀPD\ꢀEHꢀOHIWꢀXQꢄRQQHꢄWHGꢅ
65$0ꢁ,QWHUIDꢇH
6$'5>ꢃꢂꢌꢈ@
7
65$0ꢁ$GGUHVVꢅꢀ6$'5ꢀꢄRQWDLQVꢀDGGUHVVꢀOLQHVꢀWRꢀDꢄꢄHVVꢀ
%ꢈꢌ&ꢂꢋ#ꢀ%ꢂꢌ%ꢃꢈ#ꢀ%ꢃꢌ&ꢃꢈ#ꢀ%ꢍꢌ&ꢂꢇ#ꢀ%ꢊꢌ'ꢂꢇ#ꢀ%ꢎꢌ)ꢂꢆ#ꢀ%ꢏꢌ(ꢂꢋ#ꢀ
H[WHUQDOꢀ65$0VꢀWKDWꢀꢄRQWDLQVꢀDVVRꢄLDWLYHꢀGDWDꢅꢀ6HHꢀ7DEOHVꢀ %ꢆꢌ)ꢂꢋ#ꢀ%ꢋꢌ(ꢃꢈ#ꢀ%ꢇꢌ*ꢂꢋ#ꢀ%ꢂꢈꢌ*ꢂꢇ#ꢀ%ꢂꢂꢌ)ꢂꢇ#ꢀ%ꢂꢃꢌ+ꢂꢋ#ꢀ
ꢃꢃꢀDQGꢀꢃꢍꢀIRUꢀ65$0ꢀEXVꢀDGGUHVVLQJꢀGHWDLOVꢅ
%ꢂꢍꢌ*ꢃꢈ#ꢀ%ꢂꢊꢌ+ꢃꢈ#ꢀ%ꢂꢎꢌ-ꢂꢆ#ꢀ%ꢂꢏꢌ-ꢂꢋ#ꢀ%ꢂꢆꢌ-ꢃꢈ#ꢀ%ꢂꢋꢌ.ꢂꢋ#ꢀ
%ꢂꢇꢌ.ꢂꢇ#ꢀ%ꢃꢈꢌ.ꢃꢈ#ꢀ%ꢃꢂꢌ/ꢂꢋ
1ꢃꢈ
ꢉ&(
7
7
7
7
65$0ꢁ&KLSꢁ(QDEOHꢅꢀꢉ&(ꢀLVꢀWKHꢀꢄKLSꢀHQDEOHꢀꢄRQWUROꢀIRUꢀ
H[WHUQDOꢀ65$0Vꢅꢀ
ꢉ:(
ꢉ2(
ꢉ$/(
65$0ꢁ:ULWHꢁ(QDEOHꢅꢀꢉ:(ꢀLVꢀWKHꢀZULWHꢀHQDEOHꢀꢄRQWUROꢀIRUꢀ
H[WHUQDOꢀ65$0Vꢅꢀ
0ꢂꢆ
65$0ꢁ2XWSXWꢁ(QDEOHꢅꢀꢉ2(ꢀLVꢀWKHꢀRXWSXWꢀHQDEOHꢀꢄRQWUROꢀIRUꢀ 0ꢂꢋ
H[WHUQDOꢀ65$0Vꢅꢀ
$GGUHVVꢁ/DWꢇKꢁ(QDEOHꢅꢀꢉ$/(ꢀLVꢀWKHꢀODWꢄKꢀHQDEOHꢀꢄRQWUROꢀIRUꢀ 1ꢂꢋ
H[WHUQDOꢀ65$0Vꢅꢀ
ꢀ
$SULOꢁꢂꢀꢃꢁꢀꢄꢄꢂꢁ5HYꢅꢁꢄD
%DOOꢀ'HVꢄULSWLRQV
08$'ꢀꢁ+DUPRQ\ꢁꢀꢂ0ꢀDQGꢀꢃ0ꢀ7HUQDU\ꢀ&$0V
7DEOHꢁꢂꢆꢁ08$'ꢁ+DUPRQ\ꢁ%DOOꢁ'HVꢇULSWLRQV
6\PERO
7\SH 'HVꢇULSWLRQ
3LQꢁ1XPEHUꢈV)
&DVꢇDGHꢁ,QWHUIDꢇH
&6,>ꢏꢌꢈ@
,
&DVꢇDGHꢁ,Qꢅꢀ7KHVHꢀSLQVꢀGHSWKꢐꢄDVꢄDGHꢀWKHꢀGHYLꢄHꢀWRꢀIRUPꢀDꢀ %ꢈꢌ)ꢍ#ꢀ%ꢂꢌ*ꢊ#ꢀ%ꢃꢌ)ꢃ#ꢀ%ꢍꢌ*ꢃ#ꢀ%ꢊꢌ+ꢍ#ꢀ%ꢎꢌ+ꢃ#ꢀ%ꢏꢌ+ꢂ
ODUJHUꢀWDEOHꢀVL]Hꢅꢀ2QHꢀVLJQDOꢀRIꢀWKLVꢀEXVꢀLVꢀꢄRQQHꢄWHGꢀWRꢀWKHꢀ
&62>ꢂ@ꢀRUꢀ&62>ꢈ@ꢀRIꢀHDꢄKꢀRIꢀWKHꢀXSVWUHDPꢀGHYLꢄHVꢀLQꢀDꢀ
EORꢄNꢅꢀ&RQQHꢄWꢀDOOꢀXQXVHGꢀ&6,ꢀSLQVꢀWRꢀDꢀORJLꢄꢀꢈꢅꢀ)RUꢀPRUHꢀ
LQIRUPDWLRQ#ꢀVHHꢀWKHꢀ'HSWKꢐ&DVꢄDGLQJꢀVHꢄWLRQꢅ
&62>ꢂꢌꢈ@
),>ꢏꢌꢈ@ꢀ
2
,
&DVꢇDGHꢁ2XWꢅꢀ&62>ꢂ@ꢀDQGꢀ&62>ꢈ@ꢀDUHꢀWKHꢀVDPHꢀORJLꢄDOꢀ
VLJQDOꢅꢀ&62>ꢂ@ꢀRUꢀ&62>ꢈ@ꢀLVꢀꢄRQQHꢄWHGꢀWRꢀRQHꢀLQSXWꢀRIꢀWKHꢀ
&6,ꢀEXVꢀRIꢀXSꢀWRꢀIRXUꢀGRZQꢐꢀVWUHDPꢀGHYLꢄHVꢀFLQꢀDꢀEORꢄNꢀWKDWꢀ
ꢄRQWDLQVꢀXSꢀWRꢀHLJKWꢀGHYLꢄHVꢑꢅꢀ
%ꢈꢌ-ꢊ#ꢀ%ꢂꢌ-ꢍ
ꢊXOOꢁ,Qꢅꢀ(DꢄKꢀVLJQDOꢀLQꢀWKLVꢀEXVꢀLVꢀꢄRQQHꢄWHGꢀWRꢀ)2>ꢈ@ꢀRUꢀ
)2>ꢂ@ꢀRIꢀDQꢀXSVWUHDPꢀGHYLꢄHꢀWRꢀJHQHUDWHꢀWKHꢀ))ꢀVLJQDOꢀIRUꢀ
WKHꢀGHSWKꢐꢄDVꢄDGHGꢀEORꢄNꢅꢀ&RQQHꢄWꢀDOOꢀXQXVHGꢀ),ꢀVLJQDOVꢀWRꢀ
ORJLꢄꢀꢂꢅ
%ꢈꢌ5ꢃ#ꢀ%ꢂꢌ0ꢂ#ꢀ%ꢍꢌ0ꢊ#ꢀ%ꢊꢌ1ꢂ#ꢀ%ꢎꢌ3ꢂ#ꢀ%ꢏꢌ1ꢃ
)2>ꢂꢌꢈ@
2
ꢊXOOꢁ2XWꢅꢀ)2>ꢂ@ꢀDQGꢀ)2>ꢈ@ꢀDUHꢀWKHꢀVDPHꢀORJLꢄDOꢀVLJQDOꢅꢀ2QHꢀ %ꢈꢌ3ꢊ#ꢀ%ꢂꢌ5ꢃ
RIꢀWKHVHꢀWZRꢀVLJQDOVꢀPXVWꢀEHꢀꢄRQQHꢄWHGꢀWRꢀWKHꢀ),ꢀRIꢀXSꢀWRꢀ
IRXUꢀGRZQꢐVWUHDPꢀGHYLꢄHVꢀLQꢀDꢀGHSWKꢐꢄDVꢄDGHGꢀWDEOHꢅꢀ%LW>ꢈ@ꢀ
LQꢀWKHꢀ&$0ꢀDUUD\ꢀLQGLꢄDWHVꢀLIꢀWKHꢀHQWU\ꢀLVꢀIXOOꢀFꢂꢑꢀRUꢀHPSW\ꢀ
Fꢈꢑꢅ7KLVꢀVLJQDOꢀLVꢀDVVHUWHGꢀLIꢀDOOꢀELWVꢀLQꢀWKHꢀ&$0ꢀDUUD\ꢀDUHꢀꢂVꢅꢀ
%ORꢇNꢁ+LWꢁ,Qꢅꢀ7KHVHꢀSLQVꢀDUHꢀXVHGꢀIRUꢀꢄDVꢄDGLQJꢀPRUHꢀWKDQꢀ %ꢈꢌ-ꢂ#ꢀ%ꢂꢌ.ꢊ#ꢀ%ꢃꢌ.ꢃ
HLJKWꢀGHYLꢄHVꢅꢀ7KH\ꢀPXVWꢀEHꢀWLHGꢀWRꢀ*1'ꢀLIꢀꢄDVꢄDGLQJꢀHLJKWꢀ
RUꢀOHVVꢀGHYLꢄHVꢅ
%+,>ꢃꢌꢈ@
%+2>ꢃꢌꢈ@
))
,
2
2
%ORꢇNꢁ+LWꢁ2XWꢅꢀ7KHVHꢀSLQVꢀDUHꢀXVHGꢀIRUꢀꢄDVꢄDGLQJꢀPRUHꢀWKDWꢀ %ꢈꢌ/ꢂ#ꢀ%ꢂꢌ/ꢃ#ꢀ%ꢃꢌ/ꢍ
HLJKWꢀGHYLꢄHVꢅꢀ2XWSXWꢀLVꢀ1&ꢀLIꢀꢄDVꢄDGLQJꢀHLJKWꢀRUꢀOHVVꢀ
GHYLꢄHVꢅ
ꢊXOOꢁꢊODJꢅꢀ:KHQꢀDVVHUWHG#ꢀWKLVꢀVLJQDOꢀLQGLꢄDWHVꢀWKDWꢀWKHꢀWDEOHꢀ 8ꢃ
ꢄRQVLVWLQJꢀRIꢀDOOꢀGHSWKꢐꢄDVꢄDGHGꢀGHYLꢄHVꢀLVꢀIXOOꢅꢀ
'HYLꢇHꢁ,GHQWLILꢇDWLRQ
8,'>ꢍꢌꢈ@ꢀ
,
'HYLꢇHꢁ,GHQWLILꢇDWLRQꢅꢀ7KHꢀELQDU\ꢐHQꢄRGHGꢀGHYLꢄHꢀ,'ꢀIRUꢀDꢀ %ꢈꢌ'ꢂ#ꢀ%ꢂꢌ(ꢍ#ꢀ%ꢃꢌ(ꢂ#ꢀ%ꢍꢌ(ꢃ
GHSWKꢐꢄDVꢄDGHGꢀV\VWHPꢀVWDUWVꢀDWꢀꢈꢈꢈꢈꢀDQGꢀJRHVꢀXSꢀWRꢀꢈꢂꢂꢂꢅꢀ
ꢂꢂꢂꢂꢀLVꢀUHVHUYHGꢀIRUꢀDꢀVSHꢄLDOꢀEURDGꢄDVWꢀDGGUHVVꢀWKDWꢀ
VHOHꢄWVꢀDOOꢀꢄDVꢄDGHGꢀ&$0VꢀLQꢀWKHꢀV\VWHPꢅꢀ2QꢀDꢀEURDGꢄDVWꢀ
UHDGꢐRQO\#ꢀWKHꢀGHYLꢄHꢀZLWKꢀWKHꢀ/&$0ꢀELWꢀVHWꢀWRꢀꢂꢀUHVSRQGVꢅꢀ
8,'>ꢊ@
,
7KLVꢀGHYLꢄHꢀLQGHSHQGHQWꢀELWꢀVKRXOGꢀEHꢀWLHGꢀWRꢀ9''ꢅ
)ꢊ
7HVWꢁ$ꢇꢇHVVꢁ3RUWꢁ3LQV
7',
,
,
7HVWꢁ'DWDꢁ,Q
7HVWꢁ&ORꢇN
&ꢃ
'ꢍ
&ꢂ
'ꢃ
(ꢊ
7&.
7'2
706
ꢉ7567
7
,
7HVWꢁ'DWDꢁ2XW
7HVWꢁ0RGHꢁ6HOHꢇW
5HVHW
,
Note: The BHI and BHO pins would be used when a group of more than eight devices are cascaded; otherwise, these pins are not
connected or tied to ground.
5HYꢅꢁꢄDꢁ$SULOꢁꢂꢀꢃꢁꢀꢄꢄꢂ
ꢌ
08$'ꢀꢁ+DUPRQ\ꢁꢀꢂ0ꢀDQGꢀꢃ0ꢀ7HUQDU\ꢀ&$0V
)XQꢄWLRQDOꢀ'HVꢄULSWLRQ
ꢊ81&7,21$/ꢁ'(6&5,37,21
The Content Addressable Memory (CAM), High Speed
I/O Interface, Cascade Control, SRAM Interface, Test
Assess Port, and the Instruction and DQ Bus Interface
comprise the Harmony block diagram.
65$0ꢁ$GGUHVVLQJ
The SRAM address is formed by the information obtained
from the DQ bus and either the lowest match address from
a SEARCH instruction or the address supplied by
Instruction register. The interface timing and control will
select the address from the instruction register by asserting
the applicable READ or WRITE instruction. During a
READ or WRITE instruction to the SRAM, if the
identification (UID) is the global address, then the last
CAM on the SRAM bus of the depth cascaded devices
will drive the SRAM signals (LCAM = 1).
&RQWHQWꢁ$GGUHVVDEOHꢁ0HPRU\
The CAM section of the Harmony 2M consists of 16,384
136-element ternary words, and the Harmony 1M consists
of 8,192 136-element ternary words, arranged such that
each ternary element contains a data bit and a mask bit.
The combination of data and mask bits determine whether
the ternary element address is a 0, 1, or X (don’t care).
Internally, bit 0 determines if the ternary word contains
valid data; if the bit is set to 0, then the word is available as
it does not contain valid data. This bit is used to determine
the next free address in the device.
,QVWUXꢇWLRQꢁ%XVꢁDQGꢁ'4ꢁ%XV
OP[8:0] transports the instruction and its associated
parameters. DQ[67:0] is used for data transfer to, and
from, the CAM array. The DQ bus transports the search
data during the SEARCH instruction as well as the
addressing and data during the READ/WRITE operations
of the CAM array, and internal registers. The DQ bus also
carries the address information for SRAM accesses.
The priority encoder generates the address of the word
with the lowest address that satisfies the match criteria
using the searched data words, CAM array words, and the
specified global mask register.
'XDOꢁ'DWDꢁ5DWHꢁ&ORꢇN
7KHꢁ,ꢉ2ꢁ,QWHUIDꢇH
The dual data rate clock, configured as cycle A and cycle
B, allows the DQ bus interface to operate at double speed
while maintaining 100 Mhz search rates even though the
I/O width is less than the data width. Hence, only 68 pins,
instead of 136 pins, are required to support 136-bit data
words. Furthermore, Harmony can perform consecutive
searches on 136-bit data words. The phase signal ensures
that these double-speed operations are correctly aligned
with Harmony.
The high-speed input port is a double-data rate, 68-bit,
data bus incorporated with 9-bits to encode instructions,
such as READ and WRITE. The inputs are read on the
rising edge of clock, whereas the phase input is used to
distinguish between the first and second halves of the I/O
cycle. The first half of the I/O cycle transports bits 135:68
and the second half transports bits 67:0.
65$0ꢁ,QWHUIDꢇH
The SRAM interface sections drives the address and
control signals required to access the external SRAM.
Harmony can generate a synchronous output clock
(SCLK) to perform SRAM accesses. Using the SCLK
signal Harmony reduces the amount of required interface
logic by synchronously driving the SRAM address and
control signals. When cascaded, the Harmony device
which contains a match in its Results register will drive
the SRAM bus. However, in the case where a no match
exists, the last Harmony device of the cascade (LRAM =
1) will drive the SRAM bus. Also, when cascaded, this
section also inserts pipeline delays for the SRAM address
and SRAM control for Harmony. The SRAM data bus is
connected to the appropriate host ASIC, therefore SRAM
data does not pass through Harmony.
&DVꢇDGHꢁ&RQWURO
The cascade control section drives the cascade output
(CSO) signal when the Harmony devices are depth
cascaded. Up to eight Harmony devices can be
depth-cascaded. Harmony also contains the control logic
to determine if the entry in a single device is full or if the
table consisting of multiple devices is full. In addition, the
cascade control section provides support for multiple
matches. Although the cascade control section does not
drive the validity of matches, the success of matches,
multiple matches, or the required SRAM signals (these
signals are located in the controller section of the block
diagram), it does contain the control logic to enable the
output for these signals.
ꢍ
$SULOꢁꢂꢀꢃꢁꢀꢄꢄꢂꢁ5HYꢅꢁꢄD
)XQꢄWLRQDOꢀ'HVꢄULSWLRQ
08$'ꢀꢁ+DUPRQ\ꢁꢀꢂ0ꢀDQGꢀꢃ0ꢀ7HUQDU\ꢀ&$0V
Figure 2 shows how up to eight devices can cascade to
form a 128K x 68, 64K x 136, or 32K x 272 bit table and
the interconnection between the devices for
depth-cascading. Additionally, the host ASIC must
program the table size (TLSZ) field to 01. For each search,
if a device determines a local match within the device, it
asserts the CSO[1:0] signals.
3RZHUꢁ0DQDJHPHQW
The power management feature within Harmony reduces
power dissipation by limiting search operations to selected
portions with the CAM. If known beforehand, the desired
data can be isolated and only those portions will need to be
selected for the SEARCH instruction. The input pins
(/SEN[3:0]) independently control four equal sections of
the device. If fewer sections are desired then the designer
can connect multiple inputs together. To disable power
management, set bit 0 of the Configuration register or
connect /SEN[3:0] to GND.
65$0
'4>ꢆꢇꢈꢀ@
ꢆ
ꢅ
ꢅ
ꢅ
ꢅ
ꢅ
ꢄ ꢃ ꢂ ꢁ ꢀ
&6,
+DUPRQ\
&62>ꢁ@
&62>ꢀ@
ꢆ
ꢄ
ꢃ
&6,
ꢂ
ꢁ
ꢀ
ꢀ
ꢀ
7HVWꢁ$ꢇꢇHVVꢁ3RUWꢁ
+DUPRQ\
&62>ꢁ@
&62>ꢀ@
The Harmony test access port provides an interface for
manufacturing tests and consists of the boundary scan
access port used to support the standard JTAG IEEE
1149.1.
ꢆ
ꢄ ꢃ
&6,
ꢂ
ꢁ
+DUPRQ\
&62>ꢁ@
&62>ꢀ@
,QLWLDOL]DWLRQ
ꢆ
ꢄ ꢃ
&6,
ꢂ ꢁ
After a hard or soft reset the device register and internal
state machines are place in a known state. However, the
contents of the CAM must still be initialized. The
minimum required initialization will set bit 0 of each
136-bit CAM word to 0 to indicate that the word does not
contain valid data. In addition, the table configuration bits
of the Instruction register must be initialized to indicate
the width of the each of the four addressable sections.
+DUPRQ\
&62>ꢁ@
&62>ꢀ@
ꢆ
ꢄ ꢃ ꢂ ꢁ ꢀ
&6,
&62>ꢀ@
+DUPRQ\
ꢃ
ꢂ
&6,
ꢁ
ꢀ
ꢆ
ꢅ
ꢄ
&6,
+DUPRQ\
&62>ꢀ@
The last CAM in the table bit (LCAM) of the Instruction
register must be set to 1 in the last device of the cascaded
block; the LCAM bit must be set to 0 in all other devices.
In addition, the last CAM on the SRAM bus (LRAM)
must be set to 1 in the last device of the cascaded block;
the LRAM must be set to 0 in all other devices.
ꢃ
ꢂ
&6,
ꢁ
ꢀ
ꢆ
ꢅ ꢄ
&6,
+DUPRQ\
&62>ꢀ@
ꢃ
ꢂ
ꢁ
ꢀ
ꢆ ꢅ ꢄ
+DUPRQ\ &6,
&6,
For single Harmony configurations the table size bit, bits 2
and 3, of the Instruction register should be set to 00 to
reduce the latency from five or six to four clock cycles.
Finally, the Mask register must be initialized to values that
depend upon the specific application.
&62>ꢁ@&62>ꢀ@
ꢊLJXUHꢁꢀꢆꢁ'HSWKꢁ&DVꢇDGLQJꢁRIꢁ(LJKWꢁ+DUPRQ\ꢁ
'HYLꢇHV
Note: The Mask registers are initialized to all 0s, which will
guarantee a match, when compared with any word, in the device
regardless of the data values contained. Latency also needs to be
initialized.
$UELWUDWLRQ
Four cycles after the SEARCH instruction, each device
drives CSO[1:0] with the match result of the search. At the
next cycle, all downstream devices know the outcome of
the search in all the upstream devices. If any of the
upstream devices has a match, all the subsequent devices
defer driving the SRAM bus. If a search or no match
occurs, Harmony with its LRAM bit set (the last in the
chain) drives the SRAM bus signals. Also, the device with
LCAM set to 1 is the default driver of the MV, MF, and
/MM signals.
'HSWKꢋ&DVꢇDGLQJ
The Harmony search engine can depth-cascade up to eight
devices. Harmony performs all the necessary arbitration to
decide which device drives the SRAM bus, thereby
eliminating bus contention. The latency of the searches
increases as the table size increases; however, the search
rate remains constant.
5HYꢅꢁꢄDꢁ$SULOꢁꢂꢀꢃꢁꢀꢄꢄꢂ
ꢎ
08$'ꢀꢁ+DUPRQ\ꢁꢀꢂ0ꢀDQGꢀꢃ0ꢀ7HUQDU\ꢀ&$0V
)XQꢄWLRQDOꢀ'HVꢄULSWLRQ
6HDUꢇKꢁꢈꢏꢐꢋELWꢁ&RQILJXUDWLRQꢁZLWKꢁ/&$0ꢁ ꢁꢂ)ꢁ
The device is configured to be the last in the
depth-cascaded table by setting LCAM to 1 in the
Instruction register. The device with LCAM set to 1 drives
the MV, MF, and /MM signals in cycles when none of the
upstream devices drive these signals. Harmony with its
LCAM bit set drives MV, MF, and /MM during a search
with a no match or with non-search instructions.
+DUPRQ\ꢁ7DEOHꢁ&RQILJXUDWLRQ
The table configuration (CFG) field of the Instruction
register allows the designer to configure and manage the
internal tables of the Harmony device, using bits 9 through
16. The Harmony (1M) is internally divided into four
pages consisting of 2048 x 136 bits, each of which may be
configured as 4096 x 68 bits, 2048 x 136 bits, or 1024 x
272 bits by setting the following bits:
6HDUꢇKꢁꢈꢏꢐꢋELWꢁ&RQILJXUDWLRQꢁZLWKꢁ/5$0ꢁ ꢁꢂ)
The device is configured to be the last on the SRAM bus by
setting LRAM to 1 in the Instruction register. In a cycle
where the upstream Harmony does not drive the SRAM
bus, the last device of the SRAM bus (with LRAM = 1)
drives the SRAM control signals (SADR, /CE, /WE, /ALE)
when they are active. When set to 1, the LRAM bit sets the
default driver for the SRAM control signals (SADR, /CE,
/WE, and /ALE).
•
•
•
00:4096 x 68 bits
01:2048 x 136 bits
10:1024 x 272 bits
7DEOHꢁꢀꢆꢁ7DEOHꢁ&RQILJXUDWLRQꢁ%LWV
%LWV
ꢊXQꢇWLRQ
>ꢂꢈꢌꢇ@
7KHVHꢀELWVꢀꢄRQILJXUHꢀWKHꢀDGGUHVVꢀVSDꢄHꢀZLWKLQꢀWKHꢀ
ILUVWꢀTXDGUDQWꢅ
>ꢂꢃꢌꢂꢂ@
>ꢂꢊꢌꢂꢍ@
>ꢂꢏꢌꢂꢎ@
7KHVHꢀELWVꢀꢄRQILJXUHꢀWKHꢀDGGUHVVꢀVSDꢄHꢀZLWKLQꢀWKHꢀ
VHꢄRQGꢀTXDGUDQWꢅ
'HSWKꢋ&DVꢇDGLQJꢁWRꢁ*HQHUDWHꢁꢊXOO
7KHVHꢀELWVꢀꢄRQILJXUHꢀWKHꢀDGGUHVVꢀVSDꢄHꢀZLWKLQꢀWKHꢀ
WKLUGꢀTXDGUDQWꢅ
Bit 0 of each of the entries, regardless of width, is
designated as a special bit (1 = Full; 0 = Empty). For each
WRITE NEXT FREE ADDRESS or WRITE to the CAM
array, a device asserts FO[1] and FO[0] if it does not have
any empty locations.The Full Flag (FF) is asserted if the
device is full and all FI inputs are high.
7KHVHꢀELWVꢀꢄRQILJXUHꢀWKHꢀDGGUHVVꢀVSDꢄHꢀZLWKLQꢀWKHꢀ
IRXUWKꢀTXDGUDQWꢅ
For the Harmony 2M device, which has a similar
architecture, this same bit configuration will yield double
the amount of possible entries within the device. For
example, setting the bits in the CFG field to 00 would
yield a capacity of 8192 x 68 bits as opposed to 4096 x 68
bits.
Note: The BHI and BHO pins would be used when a group of
more than eight devices are cascaded; otherwise, these pins are
not connected or tied to ground.
9ꢉꢉ
'4>ꢆꢇꢈꢀ@
ꢆ
ꢅ
ꢅ
ꢅ
ꢅ
ꢅ
ꢄ
ꢄ
ꢄ
ꢄ
ꢃ
ꢂ
ꢁ
ꢀ
),
0XOWLSOHꢁ6HDUꢇKꢁ7DEOHꢁ&RQILJXUDWLRQ
+DUPRQ\
)2>ꢁ@
)2>ꢀ@
))
))
))
))
))
))
))
9ꢉꢉ
9ꢉꢉ
9ꢉꢉ
9ꢉꢉ
9ꢉꢉ
9ꢉꢉ
There are a variety of ways to internally configure and
manage multiple search tables, with variable widths,
within the Harmony device. We will show these methods,
by example, each of which may be configured by the
designer. See Figures 4, 5, and 6.
ꢆ
ꢃ
),
ꢂ
ꢁ
ꢀ
+DUPRQ\
)2>ꢁ@
)2>ꢀ@
ꢆ
ꢃ
ꢂ
ꢁ
ꢀ
),
+DUPRQ\
)2>ꢁ@
)2>ꢀ@
The Harmony device CAM is divided into four quadrants.
Each quadrant may be configured individually to a width
of 68 bits, 136 bits, or 272 bits.
ꢆ
ꢃ
),
ꢂ
ꢁ
ꢀ
+DUPRQ\
)2>ꢁ@
)2>ꢀ@
The Harmony device is fully capable of performing
one-cycle, successive search operations even when
configured for half-word widths of 68 bits or two cycle
search operations on double-word widths of 272 bits.
ꢆ
ꢄ
ꢃ
ꢂ
ꢁ ꢀ
),
)2>ꢀ@
+DUPRQ\
ꢃ
ꢂ
ꢁ
ꢀ
ꢆ
ꢅ
ꢄ
),
),
+DUPRQ\
)2>ꢀ@
ꢃ
ꢂ
ꢁ
ꢀ
ꢆ
ꢅ ꢄ
),
),
+DUPRQ\
)2>ꢀ@
ꢃ
ꢂ
ꢁ
ꢀ
ꢆ
ꢅ ꢄ
),
),
+DUPRQ\
))
)2>ꢁ@
)2>ꢀ@
ꢊLJXUHꢁꢌꢆꢁꢊXOOꢁ*HQHUDWLRQꢁLQꢁDꢁ&DVꢇDGHGꢁ7DEOH
ꢏ
$SULOꢁꢂꢀꢃꢁꢀꢄꢄꢂꢁ5HYꢅꢁꢄD
)XQꢄWLRQDOꢀ'HVꢄULSWLRQ
08$'ꢀꢁ+DUPRQ\ꢁꢀꢂ0ꢀDQGꢀꢃ0ꢀ7HUQDU\ꢀ&$0V
capacity. For example, if the CFG bits [16:9] are set to
10000101 then we will have configured the (2M) device to
support four different tables, of widths 2048 x 272 bits,
4096 x 136 bits, 8192 x 68 bits, and 4096 x 136 bits
respectively.
ꢂꢃꢄ
ꢂꢃꢄ
ꢅ
ꢆꢈꢂ
ꢅ
ꢀ
ꢂ
ꢇ
ꢆ
ꢄ
ꢃ
ꢈ
ꢀꢁ.
ꢂꢄꢃꢉꢅ
ꢂꢄꢃꢉꢂ
ꢂꢄꢃꢉꢆ
ꢂꢄꢃꢉꢃ
ꢁꢃꢆ
ꢄꢉ.
&)*ꢁ ꢁꢂꢅ
ꢊꢆꢈꢆꢋ%LWꢁ&RQILJXUDWLRQꢌ
ꢊLJXUHꢁꢍꢆꢁꢀꢑꢀꢋ%LWꢁꢈ'RXEOHꢋ:RUG)ꢁ&RQILJXUDWLRQ
ꢁꢃꢆ
ꢄꢉ.
Note: The WRITE NEXT FREE ADDRESS operation is not
supported in 272-bit mode.
ꢁꢃꢆ
ꢁꢃꢅ
ꢀ
ꢆꢈ
ꢈꢉ.
ꢀ
ꢂ
ꢄ
ꢆ
ꢁ
ꢃ
ꢅ
ꢇ
ꢂꢇꢂ
ꢈꢉ.
ꢂ.
&)*ꢉ ꢉꢁꢀꢀꢀꢀꢁꢀꢁ
ꢊLJXUHꢁꢑꢆꢁ'LIIHUHQWꢁ:LGWKꢁ([DPSOH
ꢁꢆꢃꢈꢂ
ꢁꢆꢃꢈꢃ
&)*ꢉ ꢉꢀꢁ
ꢊꢁꢃꢆꢋ%LWꢉ&RQILJXUDWLR
'HSWKꢁ&DVꢇDGLQJꢁWRꢁ&UHDWHꢁ/DUJHUꢁ/RJLꢇDOꢁ7DEOHV
Some high-performance applications require larger tables
than can be provided by one device. For these specific
applications, up to eight Harmony devices can be depth
cascaded to form larger table sizes without a loss of
throughput or any external glue logic.
ꢊLJXUHꢁꢎꢆꢁꢂꢌꢏꢋ%LWꢁꢈ6LQJOHꢋ:RUG)ꢁ&RQILJXUDWLRQ
ꢀꢃ
ꢀꢁ
ꢂ
ꢂ
ꢄ
ꢅ
ꢆ
If more than one Harmony is desired, the host ASIC must
set the TLSZ field of the Instruction register to 01 and the
LCAM (bit 7 in the Instruction register) to 1 in the last
Harmony of the depth-cascaded chain. The LCAM bit of all
previous devices of the depth-cascaded chain must then be
set to 0. Similarly, the last CAM on the SRAM bus
(LRAM) signal, bit 8 in the Configuration register, must be
set to 1 in the last Harmony of the depth-cascaded chain
connected to the SRAM bus. The LRAM bit of the other
Harmony devices must then be set to 0.
ꢄꢀꢇ.
When the TLSZ field is set to one, the MF, /MM, and MV
signals will have five clock cycles of latency. When a single
Harmony is used, the TLSZ field of the Instruction register
can be set to 0 to reduce the latency from five or six to four
clock cycles. Harmony will perform all of the necessary
arbitration to decide which device will drive the SRAM
bus. Although the latency of the searches will increase
proportionally with the table sizes, the search rate will
remain constant. For each search, if the device determines a
match within the device, then the CSO[1] and CSO[0]
signals will be asserted. See Table 24 on page 19 for TLSZ
configurations.
ꢄꢀꢆꢃꢆ
&)*ꢇ ꢇꢂꢂ
ꢈꢀꢃꢉ%LWꢇ&RQILJXUDWLRQꢊ
ꢊLJXUHꢁꢏꢆꢁꢏꢐꢋ%LWꢁꢈ+DOIꢋ:RUG)ꢁ&RQILJXUDWLRQ
0XOWLSOHꢁ/RJLꢇDOꢁ7DEOHVꢁRIꢁ'LIIHUHQWꢁ:LGWKV
The logical tables in the Harmony device are configured as
equal width tables but some applications justify different
table widths. The Harmony device may be configured, by
quadrant, to support different width logical tables within the
same search engine as long as the total number of bits in all
combined tables does not exceed the device’s maximum
5HYꢅꢁꢄDꢁ$SULOꢁꢂꢀꢃꢁꢀꢄꢄꢂ
ꢑ
08$'ꢀꢁ+DUPRQ\ꢁꢀꢂ0ꢀDQGꢀꢃ0ꢀ7HUQDU\ꢀ&$0V
5HJLVWHUꢀ'HVꢄULSWLRQV
5(*,67(5ꢁ'(6&5,37,216
Harmony contains sixteen Comparand registers, the
Global Mask register (consisting of nine registers), Result,
Instruction, Information, Burst Read, Burst Write, Next
Free Address, and Configuration registers. Table 3
provides an overview of the Harmony registers. The
registers are ordered in ascending address order. Each
register group is described in the following subsections.
7DEOHꢁꢌꢆꢁ5HJLVWHUꢁ2YHUYLHZ
$GGUHVV
ꢈ±ꢍꢂ
ꢍꢃ±ꢊꢆ
ꢊꢋ±ꢎꢎ
ꢎꢏ
$EEUHYLDWLRQ
&035>ꢈ±ꢍꢂ@
*05>ꢈꢐꢆ@
55>ꢈ±ꢆ@
,1675
7\SH 1DPHꢁ
ꢂꢏꢀꢂꢍꢏꢐELWꢀ&RPSDUDQGꢀ5HJLVWHUVꢅꢀ6WRUHVꢀꢄRPSDUDQGVꢀIURPꢀWKHꢀ'4ꢀEXVꢀIRUꢀZULWLQJꢀODWHUꢅ
5ꢉ: (LJKWꢀꢂꢍꢏꢐELWꢀ*OREDOꢀ0DVNꢀ5HJLVWHUV
(LJKWꢀ5HVXOWꢀ5HJLVWHUV
5ꢉ: ,QVWUXꢄWLRQꢀ5HJLVWHU
,QIRUPDWLRQꢀ5HJLVWHU
5
5
ꢎꢆ
,1)2
5
ꢎꢋ
5%$5
5ꢉ: %XUVWꢀ5HDGꢀ$GGUHVVꢀ5HJLVWHU
5ꢉ: %XUVWꢀ:ULWHꢀ$GGUHVVꢀ5HJLVWHU
ꢎꢇ
:%$5
ꢏꢈ
1)$
5
1H[Wꢀ)UHHꢀ$GGUHVVꢀ5HJLVWHU
5ꢉ: &RQILJXUDWLRQꢀ5HJLVWHU
1ꢉ$ 5HVHUYHG
ꢏꢂ
&21),*
1ꢉ$
ꢏꢃ±ꢏꢍ
'4>ꢃꢄꢅꢆ@
,ꢉ2
&RQILJXUDWLRQ
5HJLVWHU
%XUVWꢀ5HDG %XUVWꢀ:ULWH
%XUVWꢀ/HQJWK %XUVWꢀ/HQJWK
,QIRUPDWLRQ
5HJLVWHU
,QVWUX*WLRQ
5HJLVWHU
08;
08;
&RPSDUDQG
5HJLVWHUꢀꢁꢂ[
0DVNꢀ5HJꢀꢇꢃ[
08;
08;
:RUG
:RUG
:RUG
:RUG
0DVNꢀ,Q
'DWDꢀ,Q 0DVNꢀ,Q
'DWDꢀ2XW 0DVNꢀ2XW
%XUVWꢀ:ULWH
$GGUHVV
&$0
&RUH
%XUVWꢀ5HDG
$GGUHVV
$GGUHVV
5HJLVWHU
$GGUHVVꢀ,Q
08;
$GGUHVVꢀ2XW
08;
08;
5HVXOW
5HJLVWHUꢀꢈ[
1)$
5HJLVWHU
08;
ꢊLJXUHꢁꢐꢆꢁ,QWHUQDOꢁ'DWDSDWKꢁ'LDJUDPꢁRIꢁWKHꢁ+DUPRQ\ꢁ5HJLVWHUV
ꢐ
$SULOꢁꢂꢀꢃꢁꢀꢄꢄꢂꢁ5HYꢅꢁꢄD
5HJLVWHUꢀ'HVꢄULSWLRQV
08$'ꢀꢁ+DUPRQ\ꢁꢀꢂ0ꢀDQGꢀꢃ0ꢀ7HUQDU\ꢀ&$0V
&RPSDUDQGꢁ5HJLVWHUV
The device contains eight 136-bit Comparand registers
dynamically selected in every SEARCH operation to store
the comparand presented on the DQ bus. These registers
will later be used by the WRITE NEXT FREE
ADDRESS.
In Cycle A of the SEARCH instruction, Harmony stores
the SEARCH data bits[135:68]) in the even-number
Comparand register. In Cycle B, Harmony stores the
SEARCH data bits[67:0] in the odd-numbered Comparand
register. See Figure 9.
ꢁꢃꢆ
,QGH[
ꢁꢃꢅ
ꢆꢇ
ꢀ
ꢀ
ꢁ
ꢀ
ꢂ
ꢄ
ꢆ
ꢁ
ꢃ
ꢅ
ꢇ
ꢁꢅ
ꢃꢀ
ꢃꢁ
ꢊLJXUHꢁꢒꢆꢁ&RPSDUDQGꢁ5HJLVWHUVꢁ$GGUHVVꢁDQGꢁ8VDJH
*OREDOꢁ0DVNꢁ5HJLVWHUV
The device contains eight 136-bit Global Mask registers
dynamically selected in every SEARCH operation to
select the search subfield. Figure 10 specifies the address
of these registers. The 3-bit global search or write index
supplied on the Instruction bus applies eight global masks
during the SEARCH and WRITE operations, as shown in
Figure 10.
A mask bit in the Global Mask registers is used during
SEARCH and WRITE operations. In SEARCH
operations, setting the mask bit to 1 enables compares;
setting the mask bit to 0 disables compares (forced match)
at the current bit position. In WRITE operations to the data
or mask array, setting the mask bit to 1 enables writes;
setting the mask bit to 0 disables writes at the current bit
position.
Note: In a 68-bit configuration, the host must program the even
and odd mask register with the same value; Harmony uses
even-numbered mask registers as global masks.
During a SEARCH operation, the search data bit (S), data
bit (D), mask bit (M) and the global mask bit (G) are used
in the following manner to generate a match at that bit
position (see Table 4).
ꢁꢃꢆ
,QGH[
ꢁꢃꢅ
ꢀ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢀ
ꢂ
ꢁ
ꢃ
7DEOHꢁꢍꢆꢁ%LWꢁ3RVLWLRQꢁ0DS
ꢄ
ꢅ
*
ꢈ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
0
[
6
[
'
[
0DWꢇK
ꢆ
ꢇ
ꢂ
ꢂ
ꢂ
ꢈ
ꢈ
ꢂ
ꢈ
ꢉ
ꢁꢀ
ꢁꢂ
ꢁꢄ
ꢁꢁ
ꢁꢃ
ꢁꢅ
ꢈ
ꢂ
ꢂ
ꢂ
ꢂ
[
[
ꢈ
ꢈ
ꢂ
ꢂ
ꢈ
ꢂ
ꢈ
ꢂ
6($5&+ꢊDQGꢊ:5,7(ꢊ&RPPDQGꢊ*OREDOꢊ0DVNꢊ6H
ꢊLJXUHꢁꢂꢄꢆꢁ$GGUHVVLQJꢁWKHꢁ*OREDOꢁ0DVNꢁ5HJLVWHU
5HYꢅꢁꢄDꢁ$SULOꢁꢂꢀꢃꢁꢀꢄꢄꢂ
ꢒ
08$'ꢀꢁ+DUPRQ\ꢁꢀꢂ0ꢀDQGꢀꢃ0ꢀ7HUQDU\ꢀ&$0V
5HJLVWHUꢀ'HVꢄULSWLRQV
5HVXOWꢁ5HJLVWHUV
The device contains eight Result registers to hold the
lowest match address (LMA) found during a SEARCH
operation. The SEARCH instruction specifies which
Result register to use by parsing the Result register index
in Cycle B of the SEARCH instruction.
Subsequently, the host uses this register to access the mask
of the word at the LMA or external SRAM using the index
as part of the address (see SRAM Addressing on page 4).
The device with a valid bit set performs a READ or
WRITE operation. All other devices suppress the
operation.
7DEOHꢁꢎꢆꢁ5HVXOWꢁ5HJLVWHUꢁꢈꢂ0)
%LWꢈV) 1DPH
,QLWLDO 'HVꢇULSWLRQ
9DOXH
>ꢂꢍꢌꢈ@ ,1'(;
[
,QGH[ꢅꢀ7KLVꢀLVꢀWKHꢀDGGUHVVꢀRIꢀWKHꢀꢏꢋꢐELWꢀHQWU\ꢀZKHUHꢀDꢀVXꢄꢄHVVIXOꢀVHDUꢄKꢀRꢄꢄXUVꢅꢀ7KHꢀGHYLꢄHꢀXSGDWHVꢀWKLVꢀ
ILHOGꢀLIꢀLWꢀKDVꢀDꢀVXꢄꢄHVVIXOꢀVHDUꢄKꢅꢀ,QꢀꢂꢍꢏꢐELW#ꢀWKHꢀ/6%ꢀLVꢀꢈꢒꢀLQꢀDꢀꢃꢆꢃꢐELWꢀꢄRQILJXUDWLRQ#ꢀWKHꢀWZRꢀ/6%VꢀDUHꢀꢈꢈꢅꢀ
>ꢍꢈꢌꢂꢊ@
>ꢍꢂ@
1ꢉ$
ꢈ
ꢈ
5HVHUYHG
9$/,'
9DOLGꢅꢀ7KHꢀGHYLꢄHꢀVHWVꢀWKLVꢀELWꢀWRꢀꢂꢀLIꢀLWꢀLVꢀDꢀJOREDOꢀZLQQHUꢀFILUVWꢀ+DUPRQ\ꢀGRZQVWUHDPꢀZLWKꢀDꢀKLWꢑꢀLQꢀDꢀ6($5&+ꢀ
RSHUDWLRQꢅꢀ
>ꢏꢆꢌꢍꢃ@
1ꢉ$
ꢈ
5HVHUYHG
7DEOHꢁꢏꢆꢁ5HVXOWꢁ5HJLVWHUꢁꢈꢀ0)
%LWꢈV) 1DPH
,QLWLDO 'HVꢇULSWLRQ
9DOXH
>ꢂꢊꢌꢈ@ ,1'(;
[
,QGH[ꢅꢀ7KLVꢀLVꢀWKHꢀDGGUHVVꢀRIꢀWKHꢀꢏꢋꢐELWꢀHQWU\ꢀZKHUHꢀDꢀVXꢄꢄHVVIXOꢀVHDUꢄKꢀRꢄꢄXUVꢅꢀ7KHꢀGHYLꢄHꢀXSGDWHVꢀWKLVꢀ
ILHOGꢀLIꢀLWꢀKDVꢀDꢀVXꢄꢄHVVIXOꢀVHDUꢄKꢅꢀ,QꢀꢂꢍꢏꢐELW#ꢀWKHꢀ/6%ꢀLVꢀꢈꢒꢀLQꢀDꢀꢃꢆꢃꢐELWꢀꢄRQILJXUDWLRQ#ꢀWKHꢀWZRꢀ/6%VꢀDUHꢀꢈꢈꢅꢀ
>ꢍꢈꢌꢂꢎ@
>ꢍꢂ@
1ꢉ$
ꢈ
ꢈ
5HVHUYHG
9$/,'
9DOLGꢅꢀ7KHꢀGHYLꢄHꢀVHWVꢀWKLVꢀELWꢀWRꢀꢂꢀLIꢀLWꢀLVꢀDꢀJOREDOꢀZLQQHUꢀFILUVWꢀ+DUPRQ\ꢀGRZQVWUHDPꢀZLWKꢀDꢀKLWꢑꢀLQꢀDꢀ6($5&+ꢀ
RSHUDWLRQꢅꢀ
>ꢏꢆꢌꢍꢃ@
1ꢉ$
ꢈ
5HVHUYHG
,QVWUXꢇWLRQꢁ5HJLVWHU
7DEOHꢁꢑꢆꢁ,QVWUXꢇWLRQꢁ5HJLVWHU
%LWꢈV) 1DPH
,QLWLDO 'HVꢇULSWLRQ
9DOXH
>ꢈ@
>ꢂ@
6567
'(9(
ꢈ
6RIWZDUHꢁ5HVHWꢅꢀ,Iꢀꢂ#ꢀWKLVꢀELWꢀUHVHWVꢀWKHꢀGHYLꢄHꢀZLWKꢀWKHꢀVDPHꢀHIIHꢄWꢀDVꢀDꢀKDUGZDUHꢀUHVHWꢅꢀ,QWHUQDOO\#ꢀLWꢀ
JHQHUDWHVꢀDꢀUHVHWꢀSXOVHꢀODVWLQJꢀIRUꢀHLJKWꢀ&/.ꢀꢄ\ꢄOHVꢅꢀ7KLVꢀELWꢀDXWRPDWLꢄDOO\ꢀUHVHWVꢀWRꢀDꢀꢈꢀLIꢀZULWWHQꢀZLWKꢀDꢀꢂꢅꢀ
'HYLꢇHꢁ(QDEOHꢅꢀ,Iꢀꢈ#ꢀWKHꢀGHYLꢄHꢀGRHVꢀQRWꢀSHUIRUPꢀDQ\ꢀ6($5&+#ꢀ:5,7(#ꢀ:5,7(ꢀ1(;7ꢀ)5((ꢀ$''5(66#ꢀ
DQGꢀ5($'ꢀRSHUDWLRQV#ꢀDQGꢀLWꢀNHHSVꢀWKHꢀ65$0ꢀEXVꢀLQꢀꢍꢐVWDWHꢀꢄRQGLWLRQ#ꢀIRUꢄLQJꢀWKHꢀꢄDVꢄDGHꢀLQWHUIDꢄHꢀRXWSXWVꢀ
WRꢀꢈꢅꢀ
ꢈ
>ꢍꢌꢃ@
7/6=
ꢈꢂ
7DEOHꢁ6L]Hꢅꢀ7KHꢀKRVWꢀPXVWꢀSURJUDPꢀWKLVꢀILHOGꢀWRꢀꢄRQILJXUHꢀWKHꢀꢄKLSVꢀLQWRꢀDꢀWDEOHꢀRIꢀDꢀꢄHUWDLQꢀVL]Hꢅꢀ7KLVꢀILHOGꢀ
DIIHꢄWVꢀWKHꢀSLSHOLQHꢀODWHQꢄ\ꢀRIꢀWKHꢀ6($5&+ꢀDQGꢀ:5,7(ꢀ1(;7ꢀ)5((ꢀ$''5(66ꢀRSHUDWLRQVꢀDVꢀZHOOꢀDVꢀWKHꢀ
DꢄꢄHVVHVꢀWRꢀWKHꢀ65$0ꢀF6$'5>ꢃꢂꢌꢈ@#ꢀꢉ&(#ꢀꢉ2(#ꢀꢉ:(#ꢀꢉ$/(#ꢀ09#ꢀ0)#ꢀꢉ00#ꢀDQGꢀꢉ$&.ꢑꢅꢀ2QꢄHꢀSURJUDPPHG#ꢀ
WKHꢀVHDUꢄKꢀODWHQꢄ\ꢀVWD\VꢀꢄRQVWDQWꢅ
1XPEHUꢁRIꢁ'HYLꢇHV
ꢈꢈꢌꢂꢀGHYLꢄH
&/.
ꢊ
ꢎ
ꢏ
ꢈꢂꢌꢃꢐꢊꢀGHYLꢄHV
ꢂꢈꢌꢎꢐꢋꢀGHYLꢄHV
ꢂꢂꢌ5HVHUYHGꢀ
>ꢏꢌꢊ@
5/$7
ꢈꢈꢈ
/DWHQꢇ\ꢁRIꢁ+LWꢁ6LJQDOVꢅꢀ7KLVꢀILHOGꢀDGGVꢀODWHQꢄ\ꢀWRꢀWKHꢀ0)#ꢀ09#ꢀꢉ00#ꢀDQGꢀꢉ$&.ꢀVLJQDOVꢀE\ꢀWKHꢀIROORZLQJꢀ
QXPEHUꢀRIꢀ&/.ꢀꢄ\ꢄOHVꢀGXULQJꢀ6($5&+ꢀDQGꢀ65$0ꢀ5($'ꢀRSHUDWLRQVꢅ
ꢈꢈꢈꢌꢈꢀ
ꢈꢈꢂꢌꢂꢀ
ꢈꢂꢈꢌꢃꢀ
ꢈꢂꢂꢌꢍꢀ
ꢂꢈꢈꢌꢊ
ꢂꢈꢂꢌꢎ
ꢂꢂꢈꢌꢏ
ꢂꢂꢂꢌꢆ
>ꢆ@
/&$0
ꢈ
/DVWꢁ&$0ꢁLQꢁ7DEOHꢅꢀ7KLVꢀGHYLꢄHꢀLVꢀWKHꢀODVWꢀ&$0ꢀLQꢀWKHꢀGHSWKꢐꢄDVꢄDGHGꢀWDEOHꢅꢀ,QꢀWKHꢀHYHQWꢀRIꢀDꢀVHDUꢄKꢀIDLOXUH#ꢀ
WKHꢀGHYLꢄHꢀZLWKꢀWKLVꢀELWꢀVHWꢀGULYHVꢀWKHꢀKLWꢀVLJQDOVꢀDVꢀIROORZVꢅ
0)ꢀ ꢀꢈ#ꢀ09ꢀ ꢀꢂꢅꢀ
'XULQJꢀQRQꢐVHDUꢄKꢀꢄ\ꢄOHV#ꢀWKHꢀGHYLꢄHꢀZLWKꢀWKLVꢀELWꢀVHWꢀGULYHVꢀWKHꢀVLJQDOVꢀDVꢀIROORZVꢅ
0)ꢀ ꢀꢈ#ꢀ09ꢀ ꢀꢈꢅꢀ
ꢂꢄ
$SULOꢁꢂꢀꢃꢁꢀꢄꢄꢂꢁ5HYꢅꢁꢄD
5HJLVWHUꢀ'HVꢄULSWLRQV
08$'ꢀꢁ+DUPRQ\ꢁꢀꢂ0ꢀDQGꢀꢃ0ꢀ7HUQDU\ꢀ&$0V
7DEOHꢁꢑꢆꢁ,QVWUXꢇWLRQꢁ5HJLVWHUꢁꢈꢇRQWLQXHG)
%LWꢈV) 1DPH
,QLWLDO 'HVꢇULSWLRQ
9DOXH
>ꢋ@
/5$0
ꢈ
/DVWꢁ&$0ꢁRQꢁWKLVꢁ65$0ꢁ%XVꢅꢀ7KLVꢀGHYLꢄHꢀLVꢀWKHꢀODVWꢀ&$0ꢀRQꢀWKLVꢀ65$0ꢀEXVꢅꢀ,Qꢀꢄ\ꢄOHVꢀZKHUHꢀDꢀ&$0ꢀGRHVꢀ
QRWꢀGULYHꢀWKHꢀ65$0ꢀEXV#ꢀWKHꢀGHYLꢄHꢀZLWKꢀWKLVꢀELWꢀVHWꢀGULYHVꢀWKHꢀ65$0ꢀEXVꢀF6$'5#ꢀꢉ&(#ꢀDQGꢀꢉ:(ꢑꢀLQꢀWKHLUꢀ
LQDꢄWLYHꢀVWDWHꢅꢀ7KLVꢀELWꢀVHWVꢀDꢀGHIDXOWꢀGULYHUꢀIRUꢀWKHꢀ65$0ꢀꢄRQWUROꢀVLJQDOVꢀF6$'5#ꢀꢉ&(#ꢀꢉ:(#ꢀDQGꢀꢉ2(ꢑꢅ
Note: /OE is always asserted or deasserted.
>ꢂꢏꢌꢇ@
&)* ꢂꢈꢈꢈꢈꢂꢈꢂ 7DEOHꢁ&RQILJXUDWLRQꢅꢀ7KHꢀGHYLꢄHꢀLVꢀLQWHUQDOO\ꢀGLYLGHGꢀLQWRꢀIRXUꢀTXDGUDQWVꢀRIꢀꢋ.ꢀ[ꢀꢏꢋ#ꢀHDꢄKꢀRIꢀZKLꢄKꢀꢄDQꢀEHꢀ
ꢄRQILJXUHGꢀDVꢀꢋ.ꢀ[ꢀꢏꢋ#ꢀꢊ.ꢀ[ꢀꢂꢍꢏ#ꢀRUꢀꢃ.ꢀ[ꢀꢃꢆꢃꢀDVꢀIROORZVꢅ
ꢈꢈꢌꢋ.ꢀ[ꢀꢏꢋꢀ
ꢈꢂꢌꢊ.ꢀ[ꢀꢂꢍꢏꢀ
ꢂꢈꢌꢃ.ꢀ[ꢀꢃꢆꢃꢀ
ꢂꢂꢌ5HVHUYHG
%LWV>ꢂꢈꢌꢇ@ꢀDSSO\ꢀWRꢀꢄRQILJXULQJꢀWKHꢀꢂVWꢀTXDGUDQWꢀLQꢀWKHꢀDGGUHVVꢀVSDꢄHꢅꢀ
%LWV>ꢂꢃꢌꢂꢂ@ꢀDSSO\ꢀWRꢀꢄRQILJXULQJꢀWKHꢀꢃQGꢀTXDGUDQWꢀLQꢀWKHꢀDGGUHVVꢀVSDꢄHꢅꢀ
%LWV>ꢂꢊꢌꢂꢍ@ꢀDSSO\ꢀWRꢀꢄRQILJXULQJꢀWKHꢀꢍUGꢀTXDGUDQWꢀLQꢀWKHꢀDGGUHVVꢀVSDꢄHꢅꢀ
%LWV>ꢂꢏꢌꢂꢎ@ꢀDSSO\ꢀWRꢀꢄRQILJXULQJꢀWKHꢀꢊWKꢀTXDGUDQWꢀLQꢀWKHꢀDGGUHVVꢀVSDꢄHꢅꢀ
>ꢏꢆꢌꢂꢆ@
1ꢉ$
ꢈ
5HVHUYHG
,QIRUPDWLRQꢁ5HJLVWHU
7DEOHꢁꢐꢆꢁ,QIRUPDWLRQꢁ5HJLVWHU
%LWꢈV) 1DPH
,QLWLDO
9DOXH
'HVꢇULSWLRQꢁ
>ꢂꢂꢌꢈ@ 0)'
ꢈꢈꢈꢂꢈꢈꢂꢂꢈꢈꢂꢂ
0DQXIDꢇWXUHUꢁ,'ꢅꢀ7KHVHꢀELWVꢀLQꢄOXGHꢀWKHꢀ-7$*ꢀELWꢀ/6%ꢀ ꢀꢂꢅꢀ
>ꢃꢆꢌꢂꢃ@ '(9,' ꢂꢈꢂꢈꢂꢂꢈꢂꢈꢈꢈꢈꢈꢈꢂꢈ 'HYLꢇHꢁ,GHQWLILꢇDWLRQꢅꢀ7KHVHꢀELWVꢀLQGLꢄDWHꢀWKHꢀGHYLꢄHꢀLGHQWLILꢄDWLRQꢀQXPEHUꢅ
>ꢍꢂꢌꢃꢋ@ 5961
ꢈꢈꢈꢂ
5HYLVLRQꢁ1XPEHUꢅꢁ7KLVꢀLVꢀWKHꢀꢄXUUHQWꢀGHYLꢄHꢀUHYLVLRQꢀQXPEHUꢅꢀ7KLVꢀQXPEHUꢀLQꢄUHPHQWVꢀE\ꢀꢂꢀIRUꢀ
HDꢄKꢀUHYLVLRQꢀRIꢀWKHꢀGHYLꢄHꢅꢀ
>ꢏꢆꢌꢍꢃ@ 1ꢉ$
5HVHUYHG
%XUVWꢁ5HDGꢁ$GGUHVVꢁ5HJLVWHU
The Burst Read Address register fields must be programmed before each BURST READ operation.
7DEOHꢁꢒꢆꢁ%XUVWꢁ5HDGꢁ$GGUHVVꢁ5HJLVWHU
%LWꢈV) 1DPH
,QLWLDO 'HVꢇULSWLRQꢁ
9DOXH
>ꢂꢍꢌꢈ@ $''5
ꢈ
$GGUHVVꢅꢀ7KLVꢀLVꢀWKHꢀVWDUWLQJꢀDGGUHVVꢀRIꢀWKHꢀORꢄDWLRQꢀRIꢀWKHꢀ&$0ꢀDUUD\ꢀGXULQJꢀDꢀ%8567ꢀ5($'ꢀRSHUDWLRQꢅꢀ,Wꢀ
DXWRPDWLꢄDOO\ꢀLQꢄUHPHQWVꢀE\ꢀꢂꢀIRUꢀHDꢄKꢀVXꢄꢄHVVLYHꢀ5($'ꢀRIꢀWKHꢀ&$0ꢀDUUD\ꢅꢀ
>ꢂꢋꢌꢂꢊ@
1ꢉ$
ꢈ
ꢈ
5HVHUYHG
>ꢃꢆꢌꢂꢇ@ %/(1
/HQJWKꢁRIꢁ%XUVWꢁ$ꢇꢇHVVꢅꢀ7KHꢀGHYLꢄHꢀꢄDQꢀ5($'ꢀIURPꢀꢊꢀXSꢀWRꢀꢎꢂꢂꢀORꢄDWLRQVꢀLQꢀDꢀEXUVWꢀPRGHꢅꢀ8SꢀWRꢀWKHꢀ
PD[LPXPꢀQXPEHUꢀRIꢀGHYLꢄHV#ꢀWKLVꢀGHꢄUHPHQWVꢀWRꢀEDꢄNꢀꢈꢅ
>ꢏꢆꢌꢃꢋ@
1ꢉ$
ꢈ
5HVHUYHG
%XUVWꢁ:ULWHꢁ$GGUHVVꢁ5HJLVWHU
The Burst Write Address register fields must be programmed before BURST WRITE operations.
7DEOHꢁꢂꢄꢆꢁ%XUVWꢁ:ULWHꢁ$GGUHVVꢁ5HJLVWHU
%LWꢈV) 1DPH
,QLWLDO 'HVꢇULSWLRQꢁ
9DOXH
>ꢂꢍꢌꢈ@ $$'5
ꢈ
$GGUHVVꢅꢀ7KLVꢀLVꢀWKHꢀVWDUWLQJꢀDGGUHVVꢀRIꢀWKHꢀORꢄDWLRQꢀRIꢀWKHꢀ&$0ꢀDUUD\ꢀGXULQJꢀDꢀ%8567ꢀ:5,7(ꢀRSHUDWLRQꢅꢀ,Wꢀ
DXWRPDWLꢄDOO\ꢀLQꢄUHPHQWVꢀE\ꢀꢂꢀIRUꢀHDꢄKꢀVXꢄꢄHVVLYHꢀ:5,7(ꢀRIꢀWKHꢀ&$0ꢀDUUD\ꢅꢀ
>ꢂꢋꢌꢂꢊ@
1ꢉ$
ꢈ
ꢈ
5HVHUYHGꢅꢀ
>ꢃꢆꢌꢂꢇ@ %/(1
/HQJWKꢁRIꢁ%XUVWꢁ$ꢇꢇHVVꢅꢀ7KHꢀGHYLꢄHꢀSURYLGHVꢀWKHꢀꢄDSDELOLW\ꢀWRꢀ:5,7(ꢀIURPꢀꢊꢀXSꢀWRꢀꢎꢂꢂꢀORꢄDWLRQVꢀLQꢀDꢀEXUVWꢀ
PRGHꢅꢀ8SꢀWRꢀWKHꢀPD[LPXPꢀQXPEHUꢀRIꢀGHYLꢄHV#ꢀWKLVꢀGHꢄUHPHQWVꢀWRꢀEDꢄNꢀꢈꢅ
5HVHUYHGꢅꢀ
>ꢏꢆꢌꢃꢋ@
1ꢉ$
ꢈ
5HYꢅꢁꢄDꢁ$SULOꢁꢂꢀꢃꢁꢀꢄꢄꢂ
ꢂꢂ
08$'ꢀꢁ+DUPRQ\ꢁꢀꢂ0ꢀDQGꢀꢃ0ꢀ7HUQDU\ꢀ&$0V
5HJLVWHUꢀ'HVꢄULSWLRQV
1H[WꢁꢊUHHꢁ$GGUHVVꢁ5HJLVWHU
Bit 0 of each, regardless of width, entry is a special bit
designated for use in the operation of the WRITE NEXT
FREE ADDRESS instruction. In 68-bit configurations, bit
0 indicates whether a location is full (bit set to 1) or empty
(bit set to 0). Every WRITE and WRITE NEXT FREE
ADDRESS instruction loads the address of first 68-bit
location that contains a 0 in the entry’s bit 0. This is stored
in the Next Free Address register. If the bits of the LSB in
a device are set to 1, Harmony asserts FO[1:0] to 11. FF
should also be set to 1 in each data word.
In 136-bit configuration, the (LSB) of this register is
always set to 0. Regardless of the configured word width,
the host must set bit 0 of each word to 0 (empty) or 1 (full)
to indicate the full/empty status of each entry.
&RQILJXUDWLRQꢁ5HJLVWHU
7DEOHꢁꢂꢂꢆꢁ&RQILJXUDWLRQꢁ5HJLVWHU
%LWꢈV) 1DPH
,QLWLDO 'HVꢇULSWLRQꢁ
9DOXH
>ꢈ@
6(1(
ꢈ
(QDEOHꢁ6HDUꢇKꢁ(QDEOHꢅꢀ:KHQꢀWKLVꢀELWꢀLVꢀVHWꢀWRꢀꢂ#ꢀꢉ6(1>ꢍꢌꢈ@ꢀDUHꢀHQDEOHGꢅꢀ7KHVHꢀSLQVꢀDUHꢀLQGLYLGXDOꢀTXDGUDQWꢀ
HQDEOHVꢅꢀ:KHQꢀ6(1(ꢀLVꢀVHWꢀWRꢀꢈ#ꢀWKHꢀꢉ6(1>ꢍꢌꢈ@ꢀSLQVꢀKDYHꢀQRꢀHIIHꢄWꢅ
0XOWLꢋ0DWꢇKꢁ(QDEOHꢅꢀ:KHQꢀWKLVꢀELWꢀLVꢀVHWꢀWRꢀꢂ#ꢀWKHꢀꢉ00ꢀRXWSXWꢀLVꢀHQDEOHGꢅꢀ(OVH#ꢀWKHꢀꢉ00ꢀLVꢀGLVDEOHGꢀFꢍꢐVWDWHꢑꢅ
6&/.ꢁ(QDEOHꢅꢀ:KHQꢀWKLVꢀELWꢀLVꢀVHWꢀWRꢀꢂ#ꢀWKHꢀ6&/.ꢀRXWSXWꢀLVꢀHQDEOHGꢅꢀ(OVH#ꢀWKHꢀ6&/.ꢀRXWSXWꢀLVꢀGLVDEOHGꢀ
FꢍꢐVWDWHꢑꢅ
>ꢂ@
>ꢃ@
00(
6&(
ꢈ
>ꢏꢆꢌꢍ@
1ꢉ$
ꢈ
5HVHUYHGꢅ
ꢂꢀ
$SULOꢁꢂꢀꢃꢁꢀꢄꢄꢂꢁ5HYꢅꢁꢄD
+DUPRQ\ꢀ,QVWUXꢄWLRQV
08$'ꢀꢁ+DUPRQ\ꢁꢀꢂ0ꢀDQGꢀꢃ0ꢀ7HUQDU\ꢀ&$0V
+$5021<ꢁ,16758&7,216
A master device, such as a controller, issues instructions to
Harmony using the Op Code Valid (OPV) signal and the
Instruction bus. The following subsections describe the
functions of the instructions.
,QVWUXꢇWLRQꢁ&RGHV
Harmony implements four basic instructions (see Table 12).
OP[1:0] apply the instructions to the device while keeping
the command valid (OPV) signal high for two CLK cycles.
These two CLK cycles are designated as Cycle A and Cycle
B.
The OP[8:2] field passes the parameters of the instruction in
Cycles A and B. The controller must align the instructions
with the CLK signal.
7DEOHꢁꢂꢀꢆꢁ+DUPRQ\ꢁ,QVWUXꢇWLRQV
&RGH ,QVWUXꢇWLRQ 'HVꢇULSWLRQꢁ
ꢈꢈ
ꢈꢂ
ꢂꢈ
5($'
5HDGVꢀRQHꢀRIꢀWKHꢀIROORZLQJꢌꢀ&$0ꢀ$UUD\#ꢀ5HJLVWHUꢀORꢄDWLRQVꢀRUꢀH[WHUQDOꢀ65$0ꢅꢀ
:ULWHVꢀRQHꢀRIꢀWKHꢀIROORZLQJꢌꢀ&$0ꢀ$UUD\#ꢀ5HJLVWHUꢀORꢄDWLRQVꢀRUꢀH[WHUQDOꢀ65$0ꢅꢀ
:5,7(
6($5&+ 6HDUꢄKHVꢀWKHꢀ&$0ꢀDUUD\ꢀIRUꢀDꢀGHVLUHGꢀSDWWHUQꢀXVLQJꢀWKHꢀVSHꢄLILHGꢀUHJLVWHUꢀIURPꢀWKHꢀ*OREDOꢀ0DVNꢀUHJLVWHUꢀDUUD\ꢀDQGꢀ
ORꢄDOꢀPDVNꢀDVVRꢄLDWHGꢀZLWKꢀHDꢄKꢀGDWDꢀꢄHOOꢅꢀ
ꢂꢂ
:5,7(ꢀ 7KHꢀGHYLꢄHꢀꢄDQꢀZULWHꢀXSꢀWRꢀꢂꢏꢀꢄRPSDUDQGVꢀIRUꢀLQWHUQDOꢀVWRUDJHꢅꢀ7KHꢀGHYLꢄH¶VꢀꢄRQWUROOHUꢀLQVHUWVꢀWKHVHꢀHQWULHVꢀDWꢀWKHꢀ
1(;7ꢀ
)5((ꢀ
QH[WꢀIUHHꢀDGGUHVVꢀFDVꢀVSHꢄLILHGꢀE\ꢀWKHꢀ1)$ꢀUHJLVWHUꢑꢀXVLQJꢀWKHꢀ:5,7(ꢀ1(;7ꢀ)5((ꢀ$''5(66ꢀLQVWUXꢄWLRQꢅꢀ
$''5(66
,QVWUXꢇWLRQVꢁDQGꢁ,QVWUXꢇWLRQꢁ3DUDPHWHUV
Table 13 lists the Instruction bus fields that contain
Harmony instruction parameters and their respective
cycles. Each instruction is described separately in
subsections following this table.
7DEOHꢁꢂꢌꢆꢁ,QVWUXꢇWLRQꢁ3DUDPHWHUV
,QVWUXꢇWLRQ &\ꢇ
ꢐ
ꢑ
ꢏ
ꢎ
ꢍ
ꢌ
ꢀ
ꢂ
ꢄ
6$'5>ꢃꢂ@1 6$'5>ꢃꢈ@1 6$'5>ꢂꢇ@1
5($'
:5,7(
$
%
$
%
$
ꢈ
ꢈ
ꢀꢈ6LQJ ꢈꢀ
OH
ꢈ
ꢈ
ꢂꢀ ꢀ%XUVW
ꢈ
ꢈ
ꢈ
ꢈ
ꢈ
ꢀ6LꢈQJ
ꢈꢀ
OH
ꢈ
ꢈ
ꢈ
ꢂ
ꢈ
ꢂ
ꢂ
ꢈ
ꢂꢀ ꢀ%XUVW
6$'5>ꢃꢂ@1 6$'5>ꢃꢈ@1 6$'5>ꢂꢇ@1
*OREDOꢀ0DVNꢀ5HJLVWHUꢀ,QGH[
*OREDOꢀ0DVNꢀ5HJLVWHUꢀ,QGH[
ꢈꢀ ꢀ6LQJOH
ꢂꢀ ꢀ%XUVW
ꢈ
ꢈ
ꢈ
ꢈꢀ ꢀ6LQJOH
ꢂꢀ ꢀ%XUVW
6($5&+
6$'5>ꢃꢂ@
6$'5>ꢃꢈ@
6$'5>ꢂꢇ@ *OREDOꢀ0DVNꢀ5HJLVWHUꢀ,QGH[
ꢏꢋꢐELWꢀRUꢀꢂꢍꢏꢐELWꢌꢀꢈꢀ
ꢃꢆꢃꢐELWꢌꢀ
ꢂꢀLQꢀꢂVWꢀ&\ꢄOH
ꢈꢀLQꢀꢃQGꢀ&\ꢄOH
%
$
%
5HVXOWꢀ5HJLVWHUꢀ,QGH[>ꢃꢌꢈ@
&RPSDUDQGꢀ5HJLVWHUꢀ,QGH[
ꢂ
ꢂ
ꢂ
ꢈ
ꢂ
ꢂ
:5,7(ꢀ
1(;7ꢀ
)5((ꢀ
6$'5>ꢃꢂ@
ꢈ
6$'5>ꢃꢈ@
ꢈ
6$'5>ꢂꢇ@ &RPSDUDQGꢀ5HJLVWHUꢀ,QGH[
0RGH
ꢈꢌꢏꢋꢐELW
ꢂꢌꢂꢍꢏꢐELW
&RPSDUDQGꢀ5HJLVWHUꢀ,QGH[
$''5(662
Notes:
1.
2.
For SRAM read/write only.
The WRITE NEXT FREE ADDRESS instruction is not supported when the table width is 272 bits.
5HYꢅꢁꢄDꢁ$SULOꢁꢂꢀꢃꢁꢀꢄꢄꢂ
ꢂꢌ
08$'ꢀꢁ+DUPRQ\ꢁꢀꢂ0ꢀDQGꢀꢃ0ꢀ7HUQDU\ꢀ&$0V
+DUPRQ\ꢀ,QVWUXꢄWLRQV
%8567ꢁ5($'ꢁ,QVWUXꢇWLRQ
5($'ꢁ,QVWUXꢇWLRQ
The burst length (BLEN) field of the Burst Read Address
(RBAR) register determines the latency of the BURST
READ instruction. The BURST READ instruction
completes in four clock cycles plus twice the number of
burst accesses. Note that, before initiating the BURST
READ instruction, the host must first program the BURST
READ Address register with the start address and the
length of transfer. The following sequence delineates the
clock cycles required of the BURST READ instruction:
The READ instruction, configured as a SINGLE READ
(OP[2] = 0) or as a BURST READ (OP[2] = 1), will read
the CAM array, synchronous random access memory
(SRAM), or register location. The SINGLE READ
instruction operates in six clock cycles. However, the
BURST READ requires two additional clock cycles for
each successive READ instruction. Refer to Tables 14, 15,
16, and 17 for the READ address formats.
6,1*/(ꢁ5($'ꢁ,QVWUXꢇWLRQ
In the first cycle, the host ASIC configures the OP[1:0]
(OP[2] = 1), using OPV = 1 and applies the READ
instruction, while the DQ bus supplies the address. The
host will then select the device for which UID[4:0]
matches the DQ[25:21] lines, or the last chained device
when DQ[25:21] = 11111. The host will also supply
SADR[21:19] on OP[8:6] in first cycle of the BURST
READ instruction if the READ instruction has been
applied to an external SRAM.
During the first cycle, the host ASIC configures the
OP[1:0] (OP[2] = 0), using OPV = 1 and applies the
READ instruction, while the DQ bus supplies the address.
The host selects the device for which UID[4:0] matches
the DQ[25:21] lines, or the last chained Harmony of the
cascade when DQ[25:21] = 11111. The host ASIC also
will supply SADR[21:19] on OP[8:6] in the first cycle of
the READ instruction, if the READ has been applied to an
external SRAM.
For the next two cycles the host will 3-state (HIGHZ)
DQ[67:0]. In the fourth cycle, the device selected by the
host will drive DQ[67:0] to signal the end of transfer, and
deassert /ACK from Z to low. In the fifth cycle, the
selected device (selected by the host) will drive the data to
be read from the addressed location on DQ[67:0] and
assert /ACK signal back to high. These fourth and fifth
cycles are repeated until all of the specified accesses in the
burst length (BLEN) field of the Burst Read Address
register have been depleted.
For the next two cycles the host ASIC will hold the
DQ[67:0] bus in a 3-stated, high Z mode. Afterwards, in
the fourth cycle, the device selected by the host will drive
the DQ[67:0] bus and pull the /ACK signal from Z to low.
In the fifth cycle, the device selected by the host will drive
data to be read from the addressed location on DQ[67:0]
and assert the /ACK signal to high.
Lastly, the selected device 3-states DQ[67:0] and deasserts
/ACK to low. Upon the termination of the last cycle, the
selected device 3-states the /ACK, completes the SINGLE
READ instruction, and prepares Harmony for the next
instruction.
On the last transfer, the selected device drives DQ[67:0] to
a 3-stated position, asserts the end of transfer (EOT) signal
to high and deasserts /ACK to low. Upon the termination
of the last cycle, cycle 4 + 2n (where n is the number of
burst accesses), the selected device 3-states the /ACK
signal, completes the BURST READ instruction, and
prepares Harmony for the next instruction.
7DEOHꢁꢂꢍꢆꢁ5HDGꢁ,QVWUXꢇWLRQꢁ3DUDPHWHUV
,QVWUXꢇWLRQ
3DUDPHWHU
23>ꢀ@
5HDGꢁ,QVWUXꢇWLRQ 'HVꢇULSWLRQ
ꢈ
6,1*/(ꢀ5($'
%8567ꢀ5($'
5HDGVꢀDꢀVLQJOHꢀORꢄDWLRQꢀRIꢀWKHꢀ&$0ꢀDUUD\#ꢀH[WHUQDOꢀ65$0#ꢀRUꢀGHYLꢄHꢀUHJLVWHUVꢅꢀ$OOꢀDꢄꢄHVVꢀ
LQIRUPDWLRQꢀLVꢀDSSOLHGꢀRQꢀWKHꢀ'4ꢀEXVꢅꢀ
ꢂ
5HDGVꢀDꢀEORꢄNꢀRIꢀORꢄDWLRQVꢀIURPꢀWKHꢀ&$0ꢀDUUD\ꢀDVꢀDꢀEXUVWꢅꢀ7KHꢀLQWHUQDOꢀUHJLVWHUꢀF5%$5ꢑꢀVSHꢄLILHVꢀ
WKHꢀVWDUWLQJꢀDGGUHVVꢀDQGꢀWKHꢀOHQJWKꢀRIꢀWKHꢀGDWDꢀWUDQVIHUꢀIURPꢀWKHꢀ&$0ꢀDUUD\#ꢀDQGꢀLWꢀ
DXWRꢐLQꢄUHPHQWVꢀWKHꢀDGGUHVVꢀIRUꢀHDꢄKꢀDꢄꢄHVVꢅꢀ$OOꢀRWKHUꢀDꢄꢄHVVꢀLQIRUPDWLRQꢀLVꢀDSSOLHGꢀRQꢀWKHꢀ'4ꢀ
EXVꢅꢀ
Note: The device registers and external SRAM can only be read in single-read mode.
ꢂꢍ
$SULOꢁꢂꢀꢃꢁꢀꢄꢄꢂꢁ5HYꢅꢁꢄD
+DUPRQ\ꢀ,QVWUXꢄWLRQV
08$'ꢀꢁ+DUPRQ\ꢁꢀꢂ0ꢀDQGꢀꢃ0ꢀ7HUQDU\ꢀ&$0V
7DEOHꢁꢂꢎꢆꢁ&$0ꢁRUꢁ65$0ꢁ5HDGꢁ$GGUHVVꢁꢊRUPDW
'4
'4
'4
'4
'4
'4
'4
'4
>ꢏꢑꢆꢌꢄ@
>ꢀꢒ@
>ꢀꢐꢆꢀꢏ@
>ꢀꢎꢆꢀꢂ@ >ꢀꢄ@
>ꢂꢒ@
>ꢂꢐꢆꢂꢍ@
>ꢂꢌꢆꢄ@
5HVHUYHG ꢈꢌ'LUHꢄWꢀ 5HVXOWꢀ5HJLVWHUꢀ,QGH[
ꢂꢌ,QGLUHꢄWꢀ F$SSOLꢄDEOHꢀLIꢀ'4>ꢃꢇ@ꢀLV
LQGLUHꢄWꢑꢀ
8,'
8,'
ꢈ
ꢂ
ꢈꢌ'DWD
ꢂꢌ0DVN
5HVHUYHG ,Iꢀ'4>ꢃꢇ@ꢀLVꢀꢈ#ꢀWKLVꢀILHOGꢀꢄDUULHVꢀDGGUHVVꢀRIꢀ
GDWDꢀORꢄDWLRQꢅꢀ,Iꢀ'4>ꢃꢇ@ꢀLVꢀꢂ#ꢀWKHꢀ5HVXOWꢀ
UHJLVWHUꢀVSHꢄLILHGꢀRQꢀ'4>ꢃꢋꢌꢃꢏ@ꢀVXSSOLHVꢀ
WKHꢀDGGUHVVꢀRIꢀWKHꢀGDWDꢀORꢄDWLRQꢅꢀ
5HVHUYHG ꢈꢌ'LUHꢄWꢀ 5HVXOWꢀ5HJLVWHUꢀ,QGH[
ꢂꢌ,QGLUHꢄWꢀ F$SSOLꢄDEOHꢀLIꢀ'4>ꢃꢇ@ꢀLV
LQGLUHꢄWꢑ
ꢈ
5HVHUYHG ,Iꢀ'4>ꢃꢇ@ꢀLVꢀꢈ#ꢀWKLVꢀILHOGꢀꢄDUULHVꢀDGGUHVVꢀRIꢀ
65$0¶VꢀORꢄDWLRQꢅꢀ,Iꢀ'4>ꢃꢇ@ꢀLVꢀꢂ#ꢀWKHꢀ5HVXOWꢀ
UHJLVWHUꢀVSHꢄLILHGꢀRQꢀ'4>ꢃꢋꢌꢃꢏ@ꢀVXSSOLHVꢀ
WKHꢀDGGUHVVꢀRIꢀWKHꢀ65$0¶VꢀGDWDꢀORꢄDWLRQꢅꢀ
Note: DQ[25] should be set to 1.
7DEOHꢁꢂꢏꢆꢁ,QWHUQDOꢁ5HJLVWHUVꢁ5HDGꢁ$GGUHVVꢁꢊRUPDW
'4>ꢏꢑꢆꢀꢏ@
'4>ꢀꢎꢆꢀꢂ@
'4>ꢀꢄꢆꢂꢒ@
ꢂꢂꢌ5HJLVWHU
'4>ꢂꢐꢆꢏ@
'4>ꢎꢆꢄ@
5HVHUYHG
8,'
5HVHUYHG
5HJLVWHUꢀ$GGUHVV
7DEOHꢁꢂꢑꢆꢁ&$0ꢁ5HDGꢁ$GGUHVVꢁIRUꢁ%8567ꢁ5($'
'4>ꢏꢑꢆꢀꢏ@ '4>ꢀꢎꢆꢀꢂ@ '4>ꢀꢄ@
5HVHUYHG 8,'
'4>ꢂꢒ@
'4>ꢂꢐꢆꢂꢍ@ '4>ꢂꢌꢆꢄ@ꢁ
ꢈ
ꢈꢌ'DWD
ꢂꢌ0DVN
5HVHUYHG 'RQ¶Wꢀ&DUHꢅꢀ7KHVHꢀꢂꢊꢀELWVꢀꢄRPHꢀIURPꢀWKHꢀLQWHUQDOꢀUHJLVWHUꢀF%XUVWꢀ5HDGꢀ
$GGUHVVꢀUHJLVWHUꢑꢀZKLꢄKꢀLQꢄUHPHQWVꢀIRUꢀHDꢄKꢀDꢄꢄHVVꢅꢀ
%8567ꢁ:5,7(ꢁ,QVWUXꢇWLRQ
:5,7(ꢁ,QVWUXꢇWLRQ
The BURST WRITE instruction operates for the number of
burst accesses specified by the burst length (BLEN) field of
the Burst Write Address register plus two additional clock
cycles. Note that, before initiating the BURST WRITE
instruction, the host must program the Burst Write Address
register with the start address and the length of transfer as
indicated in the BLEN field. The following summarizes the
sequence of the BURST WRITE instruction
The WRITE instruction can be configured for SINGLE
WRITE (OP[2] = 0) or BURST WRITE (OP[2] = 1)
instruction of a CAM array, register location, or external
SRAM locations or using the internal auto-incrementing
Burst Write Address register, of the CAM array locations.
The SINGLE WRITE instruction can be completed in only
three-cycles. However, the BURST WRITE operation
requires an additional cycle for each successive WRITE.
In the first cycle, the host applies the WRITE instruction on
the OP[1:0] (OP[2] = 1), using OPV = 1 and supplied
address on the DQ bus. The host also supplies the index to
the Global Mask register to mask the WRITE to the CAM
array locations in OP[5:3]. The host will then select the
device for which UID[4:0] match the DQ[25:21], or all
devices when DQ[25:21] = 11111.
6,1*/(ꢁ:5,7(ꢁ,QVWUXꢇWLRQ
In the first cycle, the host applies the WRITE instruction on
the OP[1:0] (OP[2] = 0), using OPV=1 and the supplied
address on the DQ bus. The host will also supply the index
to the Global Mask register to mask the WRITE instruction
to the CAM array’s location in OP[5:3]. For the WRITE
instruction, the host selects the device for which UID[4:0]
match DQ[25:21] or all connected devices when DQ[25:21]
= 11111.
In the second cycle, the host drives DQ[67:0] with the data
to be written to the CAM array location of the selected
device. On DQ[67:0], the host will only write the data to the
corresponding subfield that has its mask bit set to 1 in the
Global Mask register. This is specified by the index
OP[5:3] and supplied in the first cycle.
In the second cycle, the host drives DQ[67:0] with the data
to be written to the CAM array, external SRAM, or register
location of the selected device. The third cycle is an idle
cycle, and soon after this idle period the device is ready for
the next instruction.
From the third cycle to number of burst accesses (indicated
th
by the BLEN field) plus one additional access, n cycle +1,
the host drives DQ[67:0] with the data to be written to the
CAM array’s next location (addressed by the
auto-increment address field of the Burst Write Address
register).
5HYꢅꢁꢄDꢁ$SULOꢁꢂꢀꢃꢁꢀꢄꢄꢂ
ꢂꢎ
08$'ꢀꢁ+DUPRQ\ꢁꢀꢂ0ꢀDQGꢀꢃ0ꢀ7HUQDU\ꢀ&$0V
+DUPRQ\ꢀ,QVWUXꢄWLRQV
This is specified by OP[5:3] index and supplied by the
first cycle. The host drives the end of transfer signal to low
th
Two cycles after the n cycle, the host will drive the end
of transfer signal to low. Afterward, when the cycle
terminates, the host drives the end of transfer signal to a Z
state, and prepares Harmony for the next instruction.
th
from the third to the n cycle. Afterward, the host drives
th
this same signal to high one cycle after the n cycle. This
value, n, is specified by the BLEN field of the Burst Write
Address register.
7DEOHꢁꢂꢐꢆꢁ&$0ꢁRUꢁ65$0ꢁꢈ6,1*/(ꢁ:5,7()ꢁ:ULWHꢁ$GGUHVVꢁꢊRUPDWꢁIRUꢁꢂ0ꢁ+DUPRQ\
'4
'4
'4
'4
'4
'4
'4
'4
>ꢏꢑꢆꢌꢄ@
>ꢀꢒ@
>ꢀꢐꢆꢀꢏ@
>ꢀꢎꢆꢀꢂ@ >ꢀꢄ@
>ꢂꢒ@
>ꢂꢐꢆꢂꢍ@
>ꢂꢌꢆꢄ@
5HVHUYHG ꢈꢌ'LUHꢄW 5HVXOWꢀ5HJLVWHUꢀ,QGH[
ꢂꢌ,QGLUHꢄW F$SSOLꢄDEOHꢀLIꢀ'4>ꢃꢇ@ꢀLV
LQGLUHꢄWꢑꢀ
8,'
8,'
ꢈ
ꢈꢌ'DWD
ꢂꢌ0DVN
5HVHUYHG ,Iꢀ'4>ꢃꢇ@ꢀLVꢀꢈ#ꢀWKLVꢀILHOGꢀꢄDUULHVꢀWKHꢀDGGUHVVꢀRIꢀ
WKHꢀGDWDꢀORꢄDWLRQꢅ
,Iꢀ'4>ꢃꢇ@ꢀLVꢀꢂ#ꢀWKHꢀ5HVXOWꢀUHJLVWHUꢀVSHꢄLILHGꢀE\ꢀ
'4>ꢃꢋꢌꢃꢏ@ꢀVXSSOLHVꢀWKHꢀDGGUHVVꢀRIꢀWKHꢀGDWDꢀ
ORꢄDWLRQꢅꢀ
5HVHUYHG ꢈꢌ'LUHꢄW 5HVXOWꢀ5HJLVWHUꢀ,QGH[
ꢂꢌ,QGLUHꢄW F$SSOLꢄDEOHꢀLIꢀ'4>ꢃꢇ@ꢀLV
LQGLUHꢄWꢑ
ꢂ
ꢈ
5HVHUYHG ,Iꢀ'4>ꢃꢇ@ꢀLVꢀꢈ#ꢀWKLVꢀILHOGꢀꢄDUULHVꢀDGGUHVVꢀRIꢀWKHꢀ
65$0¶VꢀORꢄDWLRQꢅ
,Iꢀ'4>ꢃꢇ@ꢀLVꢀꢂ#ꢀWKHꢀVXꢄꢄHVVIXOꢀVHDUꢄKꢀUHJLVWHUꢀ
VSHꢄLILHGꢀE\ꢀ'4>ꢃꢋꢌꢃꢏ@ꢀVXSSOLHVꢀWKHꢀDGGUHVVꢀ
RIꢀWKHꢀ65$0¶VꢀORꢄDWLRQꢅꢀ
7DEOHꢁꢂꢒꢆꢁ&$0ꢁRUꢁ65$0ꢁꢈ6,1*/(ꢁ:5,7()ꢁ:ULWHꢁ$GGUHVVꢁꢊRUPDWꢁIRUꢁꢀ0ꢁ+DUPRQ\
'4
'4
'4
'4
'4
'4
'4
'4
>ꢏꢑꢆꢌꢄ@
>ꢀꢒ@
>ꢀꢐꢆꢀꢏ@
>ꢀꢎꢆꢀꢂ@ >ꢀꢄ@
>ꢂꢒ@
>ꢂꢐꢆꢂꢎ@
>ꢂꢍꢆꢄ@
5HVHUYHG ꢈꢌ'LUHꢄW 5HVXOWꢀ5HJLVWHUꢀ,QGH[
ꢂꢌ,QGLUHꢄW F$SSOLꢄDEOHꢀLIꢀ'4>ꢃꢇ@ꢀLV
LQGLUHꢄWꢑꢀ
8,'
8,'
ꢈ
ꢈꢌ'DWD
ꢂꢌ0DVN
5HVHUYHG ,Iꢀ'4>ꢃꢇ@ꢀLVꢀꢈ#ꢀWKLVꢀILHOGꢀꢄDUULHVꢀWKHꢀDGGUHVVꢀRIꢀ
WKHꢀGDWDꢀORꢄDWLRQꢅ
,Iꢀ'4>ꢃꢇ@ꢀLVꢀꢂ#ꢀWKHꢀ5HVXOWꢀUHJLVWHUꢀVSHꢄLILHGꢀE\ꢀ
'4>ꢃꢋꢌꢃꢏ@ꢀVXSSOLHVꢀWKHꢀDGGUHVVꢀRIꢀWKHꢀGDWDꢀ
ORꢄDWLRQꢅꢀ
5HVHUYHG ꢈꢌ'LUHꢄW 5HVXOWꢀ5HJLVWHUꢀ,QGH[
ꢂꢌ,QGLUHꢄW F$SSOLꢄDEOHꢀLIꢀ'4>ꢃꢇ@ꢀLV
LQGLUHꢄWꢑ
ꢂ
ꢈ
5HVHUYHG ,Iꢀ'4>ꢃꢇ@ꢀLVꢀꢈ#ꢀWKLVꢀILHOGꢀꢄDUULHVꢀDGGUHVVꢀRIꢀWKHꢀ
65$0¶VꢀORꢄDWLRQꢅ
,Iꢀ'4>ꢃꢇ@ꢀLVꢀꢂ#ꢀWKHꢀ5HVXOWꢀUHJLVWHUꢀVSHꢄLILHGꢀE\ꢀ
'4>ꢃꢋꢌꢃꢏ@ꢀVXSSOLHVꢀWKHꢀDGGUHVVꢀRIꢀWKHꢀ65$0¶Vꢀ
ORꢄDWLRQꢅꢀ
7DEOHꢁꢀꢄꢆꢁ,QWHUQDOꢁ5HJLVWHUVꢁ:ULWHꢁ$GGUHVVꢁꢊRUPDW
'4>ꢏꢑꢆꢀꢏ@
'4>ꢀꢎꢆꢀꢂ@
'4>ꢀꢄꢆꢂꢒ@
'4>ꢂꢐꢆꢏ@
'4>ꢎꢆꢄ@
5HVHUYHG
8,'
ꢂꢂꢌ5HJLVWHU
5HVHUYHG
5HJLVWHUꢀ$GGUHVV
7DEOHꢁꢀꢂꢆꢁ&$0ꢁꢈ%8567ꢁ:5,7()ꢁ:ULWHꢁ$GGUHVVꢁꢊRUPDW
'4
'4
'4
'4
'4
'4
>ꢂꢌꢆꢄ@
>ꢏꢑꢆꢀꢏ@
>ꢀꢎꢆꢀꢂ@
>ꢀꢄ@
>ꢂꢒ@
>ꢂꢐꢆꢂꢍ@
5HVHUYHG
8,'
ꢈ
ꢈꢌ'DWD
ꢂꢌ0DVN
5HVHUYHG 'RQ¶WꢀꢄDUHꢅꢀ7KHVHꢀꢂꢊꢀELWVꢀꢄRPHꢀIURPꢀWKHꢀLQWHUQDOꢀUHJLVWHUꢀF%XUVWꢀ:ULWHꢀ
$GGUHVVꢀUHJLVWHUꢑ#ꢀZKLꢄKꢀLQꢄUHPHQWVꢀZLWKꢀHDꢄKꢀDꢄꢄHVVꢅꢀ
ꢂꢏ
$SULOꢁꢂꢀꢃꢁꢀꢄꢄꢂꢁ5HYꢅꢁꢄD
+DUPRQ\ꢀ,QVWUXꢄWLRQV
08$'ꢀꢁ+DUPRQ\ꢁꢀꢂ0ꢀDQGꢀꢃ0ꢀ7HUQDU\ꢀ&$0V
All SRAM interface signals, MV, MF, and /MM will shift
to the right for different values of TLSZ. Additionally, MV,
MF, and /MM shift to the right for different values of
RLAT. See Tables 24 and 25 for the TLSZ and RLAT
shift values.
6($5&+ꢁ,QVWUXꢇWLRQV
ꢊXOOꢁ:RUGꢁ6HDUꢇKHV
In the first cycle of full word searches, the host will drive
the OPV high and apply the instruction on OP[8:0]. For
the SEARCH operation, OP[5:3] carries the index to the
Global Mask register, whereas OP[8:6] carries the address
to be matched on SADR[21:19]. DQ[67:0] will then
transport the data to compare with the CAM array’s
[135:68] field.
Note: In the 68-bit configuration, the host must supply the same
data on DQ[67:0] during the first and second cycles.
'RXEOHꢋ:RUGꢁ6HDUꢇKHV
The double word SEARCH instruction completes in four
clock cycles after an initial latency search of four clock
cycles; however, since the instruction is pipelined, searches
In the second cycle, the host drives the OPV high and
applies the instruction to OP[8:0], whereas OP[5:2]
transports the index to the Comparand registers and then
sends the full, 136-bit, word (which was presented during
the first and second cycles) to the DQ bus. The OP[8:6]
carries the index to the Result register to store the
matching index and the match valid flag, whereas
DQ[67:0] carries the data to be compared with CAM array
bits 0 through 67. The resultant of the SEARCH
instruction will then appear as a pipelined, SRAM READ
cycle.
can be performed every two cycles
.
In the first cycle, the host drives the OPV to high and
applies the instruction on OP[8:0]. In this cycle OP[2]
must be set to 1. OP[5:3] carries the Global Mask register
index to be applied to field [271:136] of the search data
whereas DQ[67:0] carries the data to be compared with the
CAM array’s field of [271:204].
In the second cycle, the host also drives the OPV to high
and applies the instruction on OP[8:0], whereas DQ[67:0]
carries the data to be compared with the CAM array’s field
of [203:136].
The pipelined SEARCH instruction completes in two
clock cycles. All SRAM interface signals, MV, MF, and
/MM shift to the right for different values of TLSZ.
Additionally, MV, MF, and /MM shift to the right for
different values of RLAT. See Tables 24 and 25 for the
TLSZ and RLAT shift values.
In the third cycle, the host continues to drive the OPV to
high and to apply the instruction on OP[8:0]. In this cycle
OP[2] must be set to 0. OP[5:3] carries the Global Mask
register index to be applied to field [135:0] of the search
data. OP[8:6] carries the address to be supplied on
SADR[21:19] if the device has a successful match. The
DQ[67:0] carries the data to be compared with the
[135:68] field of the CAM array.
Note: The word in use must have bit 0 set to one, whereas an
empty word must have bit 0 set to 0.
+DOIꢋ:RUGꢁ6HDUꢇKHV
In the first cycle of half-word searches, the host drives the
OPV high and applies the instruction to OP[8:0]. For the
SEARCH instruction, the OP[5:3] carries the index to the
Global Mask register, whereas OP[8:6] carries the address
to be matched on SADR[21:19]. The DQ[67:0] will then
transport the data to be compared with the CAM array’s
[67:0] field.
In the fourth cycle, the host continues to drive OPV high
and apply the instruction on OP[8:0]. The DQ[67:0]
carries the data to be compared against the [67:0] field of
the CAM array.
In the 272-bit configuration, the SEARCH instruction will
be completed in four clock cycles. The SEARCH
instruction results appear as a pipelined SRAM READ
cycle with its latency measured from the second cycle of
the instruction.
In the second cycle, the host drives the OPV high and
applies the instruction to the OP[8:0] field. The OP[5:2]
transports the index to the Comparand registers to be stored,
and then sends the half, 68-bit word (which was presented
during the first and second cycles) to the DQ bus. The
OP[8:6] will transport the index to the Result register to
store the match index and the match valid flag. The full
word SEARCH instruction completes in four clock cycles
after an initial latency search of four clock cycles; however,
since the instruction is pipelined, searches can be performed
every two cycles.
For all SRAM interface signals, MV and MF will shift to
the right for different values of TLSZ. Additionally, MV,
MF, and /MM shift to the right for different values of
RLAT. See Tables 24 and 25 for the TLSZ and RLAT
shift values.
5HYꢅꢁꢄDꢁ$SULOꢁꢂꢀꢃꢁꢀꢄꢄꢂ
ꢂꢑ
08$'ꢀꢁ+DUPRQ\ꢁꢀꢂ0ꢀDQGꢀꢃ0ꢀ7HUQDU\ꢀ&$0V
+DUPRQ\ꢀ,QVWUXꢄWLRQV
:ULWHꢁ1H[WꢁꢊUHHꢁ$GGUHVV
instruction only supports 68 or 136 words and does not
support multiple search tables of different widths in depth
cascaded configurations. In others words, all tables must be
single, equal width tables.
The WRITE NEXT FREE ADDRESS instruction can be
completed in two clock cycles; the following delineates
the instruction sequence.
In the first half of the first cycle, the host applies the
WRITE NEXT FREE ADDRESS instruction on OP[1:0]
and sets the instruction data valid to one (OPV = 1).
OP[5:2] specifies the index of the even and odd comparand
registers that will be written in the 136-bit configuration. In
the 68-bit configuration, the even numbered comparands
are specified by this index. OP[8:6] transports the bits to be
driven on SADR[21:19] during the SRAM WRITE. In the
second half of the first cycle, the host continues to drive
OPV to 1, OP[1:0] to 11, and OP[5:2] with the even and
odd comparand indexes. OP[6] equals 0 for a half-word
searches of the next free address, and equals one for full
word searches of the next free address.
65$0ꢀ$GGUHVVLQJ
Index[13:0] (for 1M Harmony) and Index[14:0] (for 2M
Harmony) contains the address, of a half-word entries, that
results in a successful match; when configured, it is this
address that resides on the full and double-word page
boundaries, respectively.
SADR[13:0] (for 1M Harmony) and SADR[14:0] (for 2M
Harmony) contains the address supplied on the DQ bus
during device READ or WRITE accesses. See Tables 22
and 23 for the SRAM addressing.
65$0ꢁ5($'ꢁRUꢁ:5,7(ꢁ$ꢇꢇHVVHVꢁ
65$0ꢁ5($'
In the second cycle, the host will set the instruction data
valid signal to 0 (OPV = 0). After the completion of the
second cycle, the CAM is ready for the next instruction.
The search latency of the SRAM WRITE instruction is the
same as the search latency to the SRAM READ instruction;
it is measured from the second cycle of the WRITE NEXT
FREE ADDRESS instruction.
The SRAM READ enables and accesses associative data
contained in external SRAM. An SRAM READ instruction
completes in six cycles and the following delineates the
instruction sequence.
In the first cycle, the host applies the READ instruction on
OP[1:0], and sets the instruction data valid to one
(OPV = 1). The DQ bus then supplies the appropriate
address, sets DQ[20:19] to 10, and selects the SRAM
address. The host selects the device for which the UID[4:0]
matches DQ[25:21] and supplies SADR[21:19] to OP[8:6].
In the second and third cycles, the host 3-states DQ[67:0].
When the host applies the WRITE NEXT FREE
ADDRESS instruction specifying the appropriate
comparand register, Harmony writes the specified
comparand in the next free location in the depth-cascaded
table. The next free location is the first entry in a Harmony
with its bit [0] set to 0. If all the entries within the first
Harmony are occupied (bit[0] = 1), then the first entry with
bit[0] = 0 in a downstream Harmony in a group of cascaded
devices is the next free location. In 136-bit configuration,
bit[0] of both the even and the odd locations are both 0
when empty or both 1 when filled.
In the fourth cycle, the selected device starts to drive
DQ[67:0] and drives the acknowledge signal, /ACK, from
HIGHZ to low. In the fifth cycle, the selected device drives
the READ address on SADR[21:0]; it also drives /ACK
high, /CE low, and /ALE low. In the sixth cycle, the
selected device 3-states /CE, SADR, and the DQ bus and
continues to drive /ACK low. At the end of sixth cycle, the
selected device 3-states /ACK.
When configured for depth cascading, the FF signal
indicates to the host when no more entries can be written,
and when all entries within a group of cascaded devices are
occupied. Harmony updates the signal to the CAM array
after each WRITE or WRITE NEXT FREE ADDRESS
instruction.
SADR[13:0] contains the address supplied on the DQ bus
during access to Harmony. Furthermore, OP[8:6] transports
signals from the instruction bus to the SRAM[21:19]
address bus.
65$0ꢁ:5,7(
When configured for full words, the WRITE NEXT FREE
ADDRESS instruction writes to both the even and odd
Comparand registers in the data locations and uses the Next
Free Address register as the address. It generates a WRITE
to the external SRAM and also uses the Next Free Address
register as a portion of the SRAM address.
The SRAM WRITE instruction enables and writes
associative data contained in external SRAM. An SRAM
WRITE instruction completes in three clock cycles on the
DQ bus.
In the first cycle, the host ASIC applies the WRITE
instruction on CMD[1:0] (with CMD[2] = 0), and sets the
command valid signal to one (CMDV = 1). The DQ bus
then supplies the SRAM address, sets DQ[20:19] to 10. The
host ASIC selects the device for which the UID[4:0]
matches DQ[25:21]; it selects the device with LCAM bit set
when DQ[25:21] = 11111. In the second and third are
necessary wait cycles.
When configured for half-words, the WRITE NEXT FREE
ADDRESS instruction writes only to the even comparand
register within the data location and uses the NFA register
as the address. It generates a WRITE to the external SRAM
and also uses the Next Free Address register as a portion of
the SRAM address. The WRITE NEXT FREE ADDRESS
ꢂꢐ
$SULOꢁꢂꢀꢃꢁꢀꢄꢄꢂꢁ5HYꢅꢁꢄD
+DUPRQ\ꢀ,QVWUXꢄWLRQV
08$'ꢀꢁ+DUPRQ\ꢁꢀꢂ0ꢀDQGꢀꢃ0ꢀ7HUQDU\ꢀ&$0V
7DEOHꢁꢀꢀꢆꢁ65$0ꢁ$GGUHVVLQJꢁIRUꢁꢂ0ꢁ+DUPRQ\
,QVWUXꢇWLRQ
65$0ꢁ2SHUDWLRQ
5HDG
ꢀꢂ
&ꢋ
&ꢋ
&ꢋ
&ꢋ
&ꢋ
ꢀꢄ
&ꢆ
&ꢆ
&ꢆ
&ꢆ
&ꢆ
ꢂꢒ
&ꢏ
&ꢏ
&ꢏ
&ꢏ
&ꢏ
ꢂꢐ
ꢂ
>ꢂꢑꢆꢂꢍ@
8,'>ꢍꢌꢈ@
8,'>ꢍꢌꢈ@
8,'>ꢍꢌꢈ@
8,'>ꢍꢌꢈ@
8,'>ꢍꢌꢈ@
>ꢂꢌꢆꢄ@
6($5&+
,QGH[>ꢂꢍꢌꢈ@
1)$>ꢂꢍꢌꢈ@
6$'5>ꢂꢍꢌꢈ@
6$'5>ꢂꢍꢌꢈ@
55>ꢂꢍꢌꢈ@
:5,7(ꢀ1(;7ꢀ)5((ꢀ$''5(66
5($'
:ULWH
ꢂ
5HDG
ꢂ
:5,7(
:ULWH
ꢂ
,QGLUHꢄWꢀ$ꢄꢄHVV
:ULWHꢉ5HDG
ꢂ
7DEOHꢁꢀꢌꢆꢁ65$0ꢁ$GGUHVVLQJꢁIRUꢁꢀ0ꢁ+DUPRQ\
,QVWUXꢇWLRQ
65$0ꢁ2SHUDWLRQ
5HDG
ꢀꢂ
&ꢋ
&ꢋ
&ꢋ
&ꢋ
&ꢋ
ꢀꢄ
&ꢆ
&ꢆ
&ꢆ
&ꢆ
&ꢆ
ꢂꢒ
ꢂ
>ꢂꢐꢆꢂꢎ@
>ꢂꢍꢆꢄ@
6($5&+
8,'>ꢍꢌꢈ@
8,'>ꢍꢌꢈ@
8,'>ꢍꢌꢈ@
8,'>ꢍꢌꢈ@
8,'>ꢍꢌꢈ@
,QGH[>ꢂꢊꢌꢈ@
1)$>ꢂꢊꢌꢈ@
6$'5>ꢂꢊꢌꢈ@
6$'5>ꢂꢊꢌꢈ@
55>ꢂꢊꢌꢈ@
:5,7(ꢀ1(;7ꢀ)5((ꢀ$''5(66
5($'
:ULWH
ꢂ
5HDG
ꢂ
:5,7(
:ULWH
ꢂ
,QGLUHꢄWꢀ$ꢄꢄHVV
:ULWHꢉ5HDG
ꢂ
7DEOHꢁꢀꢍꢆꢁ5LJKWꢋ6KLIWꢁRIꢁ6LJQDOVꢁIRUꢁ7/6=ꢁ9DOXHV
7/6=
ꢈꢈ
1XPEHUꢁRIꢁ&/.ꢁ&\ꢇOHV
1XPEHUꢁRIꢁ'HYLꢇHV
ꢈ
ꢂ
ꢃ
ꢂ
ꢈꢂ
ꢃꢀꢐꢀꢋ
ꢎꢀꢐꢀꢋ
ꢂꢈ
7DEOHꢁꢀꢎꢆꢁ5LJKWꢋ6KLIWꢁRIꢁ6LJQDOVꢁIRUꢁ5/$7ꢁ9DOXHV
5/$7
ꢈꢈꢈ
ꢈꢈꢂ
ꢈꢂꢈ
ꢈꢂꢂ
ꢂꢈꢈ
ꢂꢈꢂ
ꢂꢂꢈ
ꢂꢂꢂ
1XPEHUꢁRIꢁ&/.ꢁ&\ꢇOHV
ꢈ
ꢂ
ꢃ
ꢍ
ꢊ
ꢎ
ꢏ
ꢆ
5HYꢅꢁꢄDꢁ$SULOꢁꢂꢀꢃꢁꢀꢄꢄꢂ
ꢂꢒ
08$'ꢀꢁ+DUPRQ\ꢁꢀꢂ0ꢀDQGꢀꢃ0ꢀ7HUQDU\ꢀ&$0V
$SSOLꢄDWLRQꢀ,QIRUPDWLRQ
$33/,&$7,21ꢁ,1ꢊ250$7,21
ꢌꢍꢋ%LWꢁ:RUGꢁ$SSOLꢇDWLRQV
Some applications (e.g. IPv4, IPv4 CIDR, MPLS and
ATM entries) will warrant smaller content addressable
widths, such as 34-bit one-quarter words. For IPv4
(non-CIDR), MPLS and ATM addresses, a one-cycle
technique that is not fully associative can be used. To
ensure that table look-ups are completed in one-cycle, the
designer must determine which of the entries are stored in
the high quarter-word (bits 34 through 67) or low
quarter-word (bits 0 through 33) based upon a single bit of
the value to be stored (e.g., bit 0 of the network address).
Based upon the value of the selected address bit to be
found, while performing search operations, the Global
Mask register can be used to restrict the search to the high
or low quadrant of the 68-bit half-word.
Hence, the rationale is to perform two search operations of
Harmony’s content addressable array, where the first
search will be performed on the bits 0 through 33 with the
Mask register configured as zeroes, or "don’t cares" in bits
34 through 67. The second search will be performed upon
bits 34 through 67 while bits 0 through 33 will be masked
out using the Global Mask register.
Harmony can perform both 68-bit and 136-bit fully
associative searches in a single clock cycle. However, for
34-bit searches (with two 34-bit entries per 68-bit word),
the designer must decide between one-cycle searches,
which are not fully associative, or two-cycle searches that
are fully associative. Where the above approach is
unacceptable, or when IPv4 using CIDR addresses, two
alternatives are available that provide fully associative
searches. The first alternative simply stores single 34-bit
entries into each 68-bit half-word. This ensures that
searches are completed in one-cycle at the expense of less
efficient memory utilization. The second alternative
performs two linear search operations: one on the high
order and the other on the low order 34-bits. This second
approach provides more efficient memory utilization at the
expense of reduced search speeds.
Hence, 32-bit data must be entered in two iterations,
masking out the bits of the right side then the left side of
the device. Since the search operations must be performed
twice, thus, decreasing the speed to 50 million searches
per second instead of the usual 100 million searches per
second for the 68-bit and 136-bit configurations.
Furthermore, in the case where a match may be produced
on both halves of Harmony, the desired information of the
left half has the higher priority. For example, if a
successful match is found within the left half then the right
half will not be searched. Hence, information must be
written on the left half first then the right half.
ꢀꢄ
$SULOꢁꢂꢀꢃꢁꢀꢄꢄꢂꢁ5HYꢅꢁꢄD
7LPLQJꢀ'LDJUDPV
08$'ꢀꢁ+DUPRQ\ꢁꢀꢂ0ꢀDQGꢀꢃ0ꢀ7HUQDU\ꢀ&$0V
7,0,1*ꢁ',$*5$06
6LQJOHꢁ/RꢇDWLRQꢁ5HDGꢁ7LPLQJꢁ'LDJUDP
&\ꢄOHꢀꢂ
&\ꢄOHꢀꢃ
&\ꢄOHꢀꢍ
&\ꢄOHꢀꢊ
&\ꢄOHꢀꢎ
&\ꢄOHꢀꢏ
&/.
3+$6(
239
5($'
23>ꢋꢌꢈ@
'4
$GGUHVV
;
'DWD
ꢉ$&.
ꢊLJXUHꢁꢂꢂꢆꢁ6LQJOHꢁ/RꢇDWLRQꢁ5HDGꢁ7LPLQJꢁ'LDJUDP
:ULWHꢁ&\ꢇOHꢁ7LPLQJꢁ'LDJUDP
&\ꢄOHꢀꢈ
&\ꢄOHꢀꢂ
&\ꢄOHꢀꢃ
&\ꢄOHꢀꢍ
&\ꢄOHꢀꢊ
&/.
3+$6(
239
:ULWH
23>ꢋꢌꢈ@
'4
$GGUHVV
'DWD
;
ꢊLJXUHꢁꢂꢀꢆꢁ:ULWHꢁ&\ꢇOHꢁ7LPLQJꢁ'LDJUDP
5HYꢅꢁꢄDꢁ$SULOꢁꢂꢀꢃꢁꢀꢄꢄꢂ
ꢀꢂ
08$'ꢀꢁ+DUPRQ\ꢁꢀꢂ0ꢀDQGꢀꢃ0ꢀ7HUQDU\ꢀ&$0V
7LPLQJꢀ'LDJUDPV
'DWDꢁDQGꢁ0DVNꢁ5($'ꢁꢈ%/(1ꢁ ꢁꢍ)ꢁIRUꢁDꢁ*URXSꢁRIꢁ&DVꢇDGHGꢁ'HYLꢇHVꢁ7LPLQJꢁ'LDJUDP
&\ꢄOHꢀꢂ
&\ꢄOHꢀꢃ
&\ꢄOHꢀꢍ
&\ꢄOHꢀꢊ
&\ꢄOHꢀꢎ
&\ꢄOHꢀꢏ
&\ꢄOHꢀꢆ
&\ꢄOHꢀꢋ
&\ꢄOHꢀꢇ
&\ꢄOHꢀꢂꢈ &\ꢄOHꢀꢂꢂ &\ꢄOHꢀꢂꢃ
&/.
3+$6(
239
5($'
23>ꢋꢌꢈ@
'4
$GGUHVV
))
'DWDꢈ
))
'DWDꢂ
))
'DWDꢃ
))
'DWDꢍ
ꢉ$&.
(27
ꢊLJXUHꢁꢂꢌꢆꢁ'DWDꢁDQGꢁ0DVNꢁ5($'ꢁꢈ%/(1ꢁ ꢁꢍ)ꢁIRUꢁDꢁ*URXSꢁRIꢁ&DVꢇDGHGꢁ'HYLꢇHVꢁ7LPLQJꢁ'LDJUDP
'DWDꢁDQGꢁ0DVNꢁ:5,7(ꢁꢈ%/(1ꢁ ꢁꢍ)ꢁIRUꢁDꢁ*URXSꢁRIꢁ&DVꢇDGHGꢁ'HYLꢇHVꢁ7LPLQJꢁ'LDJUDP
&\ꢄOHꢀꢂ
&\ꢄOHꢀꢃ
&\ꢄOHꢀꢍ
&\ꢄOHꢀꢊ
&\ꢄOHꢀꢎ
&\ꢄOHꢀꢏ
&/.
3+$6(
239
:ULWH
23>ꢋꢌꢈ@
'4
$GGUHVV
'DWDꢈ
'DWDꢂ
'DWDꢃ
'DWDꢍ
;
(27
ꢊLJXUHꢁꢂꢍꢆꢁ'DWDꢁDQGꢁ0DVNꢁ:5,7(ꢁꢈ%/(1ꢁ ꢁꢍ)ꢁIRUꢁDꢁ*URXSꢁRIꢁ&DVꢇDGHGꢁ'HYLꢇHVꢁ7LPLQJꢁ'LDJUDP
ꢀꢀ
$SULOꢁꢂꢀꢃꢁꢀꢄꢄꢂꢁ5HYꢅꢁꢄD
7LPLQJꢀ'LDJUDPV
08$'ꢀꢁ+DUPRQ\ꢁꢀꢂ0ꢀDQGꢀꢃ0ꢀ7HUQDU\ꢀ&$0V
ꢏꢐꢋ%LWꢁ6($5&+ꢁ2SHUDWLRQꢁ7LPLQJꢁ'LDJUDP
&\ꢀOHꢁꢂ
&\ꢀOHꢁꢃ
&\ꢀOHꢁꢄ
&\ꢀOHꢁꢅ
&\ꢀOHꢁꢆ
&\ꢀOHꢁꢇ
&\ꢀOHꢁꢈ
&\ꢀOHꢁꢉ
&\ꢀOHꢁꢊ
&\ꢀOHꢁꢂꢋ
&/.
3+$6(
6&/.
239
6HDUꢀKꢂ
6HDUꢀKꢃ
6HDUꢀKꢄ
6HDUꢀKꢅ
23>ꢀꢁꢂ@
23>ꢃꢁꢄ@
'4
$
%
'ꢂ
'ꢃ
'ꢄ
'ꢅ
ꢅ6(1>ꢆꢁꢂ@
6$'5>ꢄꢀꢁꢂ@
ꢅ&(
$ꢂ
$ꢃ
$ꢄ
$ꢅ
ꢅ:(
ꢅ2(
0)
ꢅ00
+LW
0LVV
+LW
0LVV
09
&)*ꢁ ꢁꢋꢋꢋꢋꢋꢋꢋꢋꢌꢁ5/$7ꢁ ꢁꢋꢋꢋꢌꢁ7/6=ꢁ ꢁꢋꢋꢌꢁ/5$0ꢁ ꢁꢋꢌꢁ/&$0ꢁ ꢁꢋ
ꢊLJXUHꢁꢂꢎꢆꢁꢏꢐꢋ%LWꢁ6($5&+ꢁ2SHUDWLRQꢁ7LPLQJꢁ'LDJUDP
5HYꢅꢁꢄDꢁ$SULOꢁꢂꢀꢃꢁꢀꢄꢄꢂ
ꢀꢌ
08$'ꢀꢁ+DUPRQ\ꢁꢀꢂ0ꢀDQGꢀꢃ0ꢀ7HUQDU\ꢀ&$0V
7LPLQJꢀ'LDJUDPV
ꢂꢌꢏꢋ%LWꢁ6($5&+ꢁ2SHUDWLRQꢁ7LPLQJꢁ'LDJUDP
&\ꢀOHꢁꢂ
&\ꢀOHꢁꢃ
&\ꢀOHꢁꢄ
&\ꢀOHꢁꢅ
&\ꢀOHꢁꢆ
&\ꢀOHꢁꢇ
&\ꢀOHꢁꢈ
&\ꢀOHꢁꢉ
&\ꢀOHꢁꢊ
&\ꢀOHꢁꢂꢋ
&/.
3+$6(
6&/.
239
6HDUꢀKꢂ
6HDUꢀKꢃ
6HDUꢀKꢄ
6HDUꢀKꢅ
23>ꢀꢁꢂ@
23>ꢃꢁꢄ@
'4
$
%
ꢅ6(1>ꢆꢁꢂ@
6$'5>ꢄꢀꢁꢂ@
ꢅ&(
$ꢂ
$ꢃ
$ꢄ
$ꢅ
ꢅ:(
ꢅ2(
0)
ꢅ00
+LW
0LVV
+LW
0LVV
09
&)*ꢁ ꢁꢋꢂꢋꢂꢋꢂꢋꢂꢌꢁ5/$7ꢁ ꢁꢋꢋꢋꢌꢁ7/6=ꢁ ꢁꢋꢋꢌꢁ/5$0ꢁ ꢁꢋꢌꢁ/&$0ꢁ ꢁꢋ
ꢊLJXUHꢁꢂꢏꢆꢁꢂꢌꢏꢋ%LWꢁ6($5&+ꢁ2SHUDWLRQꢁ7LPLQJꢁ'LDJUDP
ꢀꢍ
$SULOꢁꢂꢀꢃꢁꢀꢄꢄꢂꢁ5HYꢅꢁꢄD
7LPLQJꢀ'LDJUDPV
08$'ꢀꢁ+DUPRQ\ꢁꢀꢂ0ꢀDQGꢀꢃ0ꢀ7HUQDU\ꢀ&$0V
ꢀꢑꢀꢋ%LWꢁ6($5&+ꢁ2SHUDWLRQꢁ7LPLQJꢁ'LDJUDP
&\ꢀOHꢁꢂ
&\ꢀOHꢁꢃ
&\ꢀOHꢁꢄ
&\ꢀOHꢁꢅ
&\ꢀOHꢁꢆ
&\ꢀOHꢁꢇ
&\ꢀOHꢁꢈ
&\ꢀOHꢁꢉ
&\ꢀOHꢁꢊ
&\ꢀOHꢁꢂꢋ
&/.
3+$6(
6&/.
239
$
%
&
'
6HDUꢀKꢂ
%
6HDUꢀKꢃ
23>ꢀꢁꢂ@
23>ꢃꢁꢄ@
'4
$
&
'
'ꢋ
'ꢂ
'ꢃ
'ꢄ
'ꢋ
'ꢂ
'ꢃ
'ꢄ
ꢅ6(1>ꢆꢁꢂ@
6$'5>ꢄꢀꢁꢂ@
ꢅ&(
$ꢂ
$ꢃ
ꢅ:(
ꢅ2(
0)
ꢅ00
+LW
0LVV
09
&)*ꢁ ꢁꢂꢋꢂꢋꢂꢋꢂꢋꢌꢁ5/$7ꢁ ꢁꢋꢋꢋꢌꢁ7/6=ꢁ ꢁꢋꢋꢌꢁ/5$0ꢁ ꢁꢋꢌꢁ/&$0ꢁ ꢁꢋ
ꢊLJXUHꢁꢂꢑꢆꢁꢀꢑꢀꢋ%LWꢁ6($5&+ꢁ2SHUDWLRQꢁ7LPLQJꢁ'LDJUDP
5HYꢅꢁꢄDꢁ$SULOꢁꢂꢀꢃꢁꢀꢄꢄꢂ
ꢀꢎ
08$'ꢀꢁ+DUPRQ\ꢁꢀꢂ0ꢀDQGꢀꢃ0ꢀ7HUQDU\ꢀ&$0V
7LPLQJꢀ'LDJUDPV
$UELWUDWLRQꢁIRUꢁDꢁ*URXSꢁRIꢁ&DVꢇDGHGꢁ'HYLꢇHVꢁ7LPLQJꢁ'LDJUDP
&\ꢀOHꢁꢂ
&\ꢀOHꢁꢃ
&\ꢀOHꢁꢄ
&\ꢀOHꢁꢅ
&\ꢀOHꢁꢆ
&\ꢀOHꢁꢇ
&\ꢀOHꢁꢈ
&\ꢀOHꢁꢉ
&\ꢀOHꢁꢊ
&\ꢀOHꢁꢂꢋ
&/.
3+$6(
6&/.
239
6HDUꢀKꢂ
6HDUꢀKꢃ
6HDUꢀKꢄ
6HDUꢀKꢅ
23>ꢃꢁꢂ@
'4
'ꢋ
'ꢂ
'ꢋ
'ꢂ
'ꢋ 'ꢂ 'ꢋ
'ꢂ
$ꢂ
$ꢃ
$ꢄ
$ꢅ
6$'5>ꢄꢀꢁꢂ@
ꢅ&(
ꢅ:(
ꢅ2(
+LW
0LVV
+LW
+LW
&62>ꢀꢁꢂ@
0)
ꢅ00
09
5/$7ꢁ ꢁꢋꢋꢋꢌꢁ7/6=ꢁ ꢁꢋꢂꢌꢁ/5$0ꢁ ꢁꢋꢌꢁ/&$0ꢁ ꢁꢋ
ꢊLJXUHꢁꢂꢐꢆꢁ$UELWUDWLRQꢁIRUꢁDꢁ*URXSꢁRIꢁ&DVꢇDGHGꢁ'HYLꢇHVꢁ7LPLQJꢁ'LDJUDP
:5,7(ꢁ7LPLQJꢁ'LDJUDP
&\ꢀOHꢁꢂ
&\ꢀOHꢁꢃ
&\ꢀOHꢁꢄ
&\ꢀOHꢁꢅ
&\ꢀOHꢁꢆ
&\ꢀOHꢁꢇ
&\ꢀOHꢁꢈ
&\ꢀOHꢁꢉ
&\ꢀOHꢁꢊ
&\ꢀOHꢁꢂꢋ
&/.
3+$6(
6&/.
239
:ULWHꢂ
;
:ULWHꢃ
&RPSꢃ
23>ꢀꢁꢂ@
23>ꢃꢁꢄ@
'4
&RPSꢂ
;
ꢃ
;
;
ꢂ$
ꢂ%
;
;
;
$ꢂ
$ꢃ
6$'5>ꢄꢀꢁꢂ@
ꢅ&(
ꢅ:(
ꢅ2(
7/6=ꢁ ꢁꢋꢋꢌꢁ/5$0ꢁ ꢁꢋ
ꢊLJXUHꢁꢂꢒꢆꢁ:5,7(ꢁ7LPLQJꢁ'LDJUDP
ꢀꢏ
$SULOꢁꢂꢀꢃꢁꢀꢄꢄꢂꢁ5HYꢅꢁꢄD
7LPLQJꢀ'LDJUDPV
08$'ꢀꢁ+DUPRQ\ꢁꢀꢂ0ꢀDQGꢀꢃ0ꢀ7HUQDU\ꢀ&$0V
65$0ꢁ5($'ꢁ&\ꢇOHꢁ7LPLQJꢁ'LDJUDP
&\ꢄOHꢀꢂ
&\ꢄOHꢀꢃ
&\ꢄOHꢀꢍ
&\ꢄOHꢀꢊ
&\ꢄOHꢀꢎ
&\ꢄOHꢀꢏ
&/.
3+$6(
6&/.
239
5HDG
23>ꢋꢌꢈ@
'4
$GGUHVV
;
ꢉ&(
ꢉ:(
ꢉ2(
$GGUHVV
6$'5
ꢉ$&.
5/$7ꢀ ꢀꢈꢈꢈ#ꢀ7/6=ꢀ ꢀꢈꢈ#ꢀ/5$0ꢀ ꢀꢈ#ꢀ/&$0ꢀ ꢀꢈ
ꢊLJXUHꢁꢀꢄꢆꢁ65$0ꢁ5($'ꢁ&\ꢇOHꢁ7LPLQJꢁ'LDJUDP
5HYꢅꢁꢄDꢁ$SULOꢁꢂꢀꢃꢁꢀꢄꢄꢂ
ꢀꢑ
08$'ꢀꢁ+DUPRQ\ꢁꢀꢂ0ꢀDQGꢀꢃ0ꢀ7HUQDU\ꢀ&$0V
7LPLQJꢀ'LDJUDPV
65$0ꢁ:5,7(ꢁ&\ꢇOHꢁ7,PLQJꢁ'LDJUDP
&\ꢄOHꢀꢂ
&\ꢄOHꢀꢃ
&\ꢄOHꢀꢍ
&\ꢄOHꢀꢊ
&\ꢄOHꢀꢎ
&\ꢄOHꢀꢏ
&\ꢄOHꢀꢆ
&/.
3+$6(
6&/.
239
23>ꢋꢌꢈ@
'4
$GGUHVV
;
;
ꢉ&(
ꢉ:(
ꢉ2(
$ꢂ
6$'5
5/$7ꢀ ꢀꢈꢈꢈ#ꢀ7/6=ꢀ ꢀꢈꢈ#ꢀ/7$0ꢀ ꢀꢈ#ꢀ/&$0ꢀ ꢀꢈ
ꢊLJXUHꢁꢀꢂꢆꢁ65$0ꢁ:5,7(ꢁ&\ꢇOHꢁ7LPLQJꢁ'LDJUDP
ꢀꢐ
$SULOꢁꢂꢀꢃꢁꢀꢄꢄꢂꢁ5HYꢅꢁꢄD
7LPLQJꢀ'LDJUDPV
08$'ꢀꢁ+DUPRQ\ꢁꢀꢂ0ꢀDQGꢀꢃ0ꢀ7HUQDU\ꢀ&$0V
$&ꢁ7LPLQJꢁ:DYHIRUPV
&/.
3+$6(
7
,+&+
7
,6&+
6LJQDOꢀ*URXSꢀꢁ
6LJQDOꢀ*URXSꢀꢂ
7
,&+&+
7
,&6&+
7
&.+29
6LJQDOꢀ*URXSꢀꢃ
6LJQDOꢀ*URXSꢀꢄ
6LJQDOꢀ*URXSꢀꢅ
7
&.+29
7
&.+6+=
7
&.+69
7
&.+'=
7
&.+69
7
&.+'9
6LJQDOꢉ*URXSꢉꢁꢌꢉ3+$6(ꢍꢉ23>ꢈꢌꢀ@ꢍꢉ239ꢍꢉꢎ567
6,JQDOꢉ*URXSꢉꢂꢌꢉ&6,>ꢆꢌꢀ@ꢍꢉ),>ꢆꢌꢀ@
6LJQDOꢉ*URXSꢉꢃꢌꢉ&62>ꢁꢌꢀ@ꢍꢉ)2>ꢁꢌꢀ@ꢍꢉ))ꢍꢉ0)ꢍꢉꢎ00ꢍꢉ09ꢍꢉꢎ6(1>ꢃꢌꢀ@
6LJQDOꢉ*URXSꢉꢄꢌꢉꢎ&(ꢍꢉꢎ2(ꢍꢉꢎ:(ꢍꢉꢎ$/(
6LJQDOꢉ*URXSꢉꢅꢌꢉ'4ꢍꢉꢎ$&.ꢍꢉ(27
ꢊLJXUHꢁꢀꢀꢆꢁ$&ꢁ7LPLQJꢁ:DYHIRUPV
7DEOHꢁꢀꢏꢆꢁ$&ꢁ7LPLQJꢁ3DUDPHWHUV
5RZ
6\PERO
ꢋꢏꢏ
ꢋꢐꢌ
ꢋꢂꢄꢄ
8QLW 'HVꢇULSWLRQ
0LQ 0D[ 0LQ 0D[ 0LQ 0D[
ꢂ
ꢃ
7
ꢂꢍꢍ
ꢂꢏꢏ
0+] &/.ꢃ;ꢀSHULRGꢒꢀ0D[ꢀIUHTXHQꢄ\
&/.
&/.ꢃ;ꢀKLJKꢀSXOVHꢒꢀZRUVWꢐꢄDVHꢀꢊꢈMꢉꢏꢈMꢀGXW\ꢀꢄ\ꢄOH1
&/.ꢃ;ꢀORZꢀSXOVHꢒꢀZRUVWꢐꢄDVHꢀꢊꢈMꢉꢏꢈMꢀGXW\ꢀꢄ\ꢄOH1
7
ꢃꢅꢇ
ꢃꢅꢇ
ꢂꢅꢋ
ꢈꢅꢏ
ꢊꢅꢃ
ꢈꢅꢏ
ꢃꢅꢊ
ꢃꢅꢊ
ꢂꢅꢎ
ꢈꢅꢎ
ꢍꢅꢎ
ꢈꢅꢎ
QV
QV
&.+,
ꢍ
7
&./2
ꢊ
7
QV ,QSXWꢀ6HWXSꢀ7LPHꢀWRꢀ&/.ꢃ;ꢀULVLQJꢀHGJH
,6&+
ꢎ
7
QV ,QSXWꢀ+ROGꢀ7LPHꢀWRꢀ&/.ꢃ;ꢀULVLQJꢀHGJH
,+&+
ꢏ
7
QV &DVꢄDGHGꢀ,QSXWꢀ6HWXSꢀ7LPHꢀWRꢀ&/.ꢃ;ꢀULVLQJꢀHGJH
QV &DVꢄDGHGꢀ,QSXWꢀ+ROGꢀ7LPHꢀWRꢀ&/.ꢃ;ꢀULVLQJꢀHGJH
,&6&+
ꢆ
7
,&+&+
5LVLQJꢀHGJHꢀRIꢀ&/.ꢃ;ꢀWRꢀ/+2#ꢀ)8/2#ꢀ%+2#ꢀ)8//ꢀYDOLG2
5LVLQJꢀHGJHꢀRIꢀ&/.ꢃ;ꢀWRꢀ'4ꢀYDOLG3
ꢋ
7
ꢂꢈꢅꢃ
ꢂꢂꢅꢊ
ꢋꢅꢎ
ꢇꢅꢎ
QV
QV
QV
QV
QV
QV
&.+29
7
&.+'9
ꢇ
5LVLQJꢀHGJHꢀRIꢀ&/.ꢃ;ꢀWRꢀ'4ꢀꢍꢐVWDWH4, 5
ꢂꢈ
ꢂꢂ
ꢂꢃ
ꢂꢍ
7
7
ꢂꢅꢃ ꢋꢅꢊ ꢂꢅꢈ ꢆꢅꢈ
ꢍꢅꢏ ꢂꢂꢅꢊ ꢍꢅꢈ ꢇꢅꢎ
&.+'=
&.+69
5LVLQJꢀHGJHꢀRIꢀ&/.ꢃ;ꢀWRꢀ65$0ꢀEXVꢀYDOLG3
5LVLQJꢀHGJHꢀRIꢀ&/.ꢃ;ꢀWRꢀ65$0ꢀEXVꢀ+,*+=4, 5
5LVLQJꢀHGJHꢀRIꢀ&/.ꢃ;ꢀWRꢀ65$0ꢀEXVꢀ/2:=4, 5
7
ꢍꢅꢏ
ꢍꢅꢏ
ꢍꢅꢈ
ꢍꢅꢈ
&.+6+=
7
&.+6/=
Notes:
1.
2.
3.
4.
5.
TCLKHI and TCKLO duty cycle values are based on 20-80% signals levels.
Based on an AC load of 30 pF.
Except on notes cases, all values are based on AC load 50 pF measured at 1.5 V reference levels.
Based on AC load of 10 pF, 50-W DC loading and measured at 200mV from steady state.
These parameters are sampled and not 100% tested.
5HYꢅꢁꢄDꢁ$SULOꢁꢂꢀꢃꢁꢀꢄꢄꢂ
ꢀꢒ
08$'ꢀꢁ+DUPRQ\ꢁꢀꢂ0ꢀDQGꢀꢃ0ꢀ7HUQDU\ꢀ&$0V
(OHꢄWULꢄDOꢀ6SHꢄLILꢄDWLRQV
(/(&75,&$/ꢁ63(&,ꢊ,&$7,216
This section describes the electrical specifications,
capacitance, operating conditions, and DC characteristics
for the Harmony devices.
(OHꢇWULꢇDOꢁ&KDUDꢇWHULVWLꢇV
6\PERO 3DUDPHWHU
&RQGLWLRQVꢁ
0LQꢁ
0D[ꢁ 8QLWꢁ
,
,QSXWꢀ/HDNDJHꢀ&XUUHQW
ꢈꢀ≤ꢀ9 ꢀ≤ꢀ9
ꢐꢂꢈ
ꢂꢈ
ꢂꢈ
µ$
µ$
9
/,
,1 ''4
2XWSXWꢀ/HDNDJHꢀ&XUUHQW1
2XWSXWꢀ/RZꢀ9ROWDJH
,
ꢈꢀ≤ꢀ9
ꢀ≤ꢀ9
287 ''4
ꢐꢂꢈ
ꢃꢅꢊ
/2
9
ꢋP$#ꢀ9
ꢀ ꢀꢍꢅꢍ9
ꢀ ꢀꢍꢅꢍ9
ꢈꢅꢊ
2/
''4
''4
9
,
2XWSXWꢀ+LJKꢀ9ROWDJH
ꢊP$#ꢀ9
9
2+
ꢂꢅꢋꢀ9ꢀ6XSSO\ꢀ&XUUHQW2
ꢍꢅꢍꢀ9ꢀ6XSSO\ꢀ&XUUHQW2
7%'
7%'
P$
P$
''
,
''4
1.
2.
Applies only for outputs in 3-state.
Average operating current at maximum frequency. Transient peak currents may exceed these values.
&DSDꢇLWDQꢇH
6\PERO
3DUDPHWHU
0D[
8QLW
S)1
S)2
&
,1
,QSXWꢀ&DSDꢄLWDQꢄHꢀ
2XWSXWꢀ&DSDꢄLWDQꢄHꢀ
ꢏ
&
ꢏ
287
1.
2.
f = 1 MHz, V =0 V
IN
f = 1 MHz, V
OUT
=0 V
2SHUDWLQJꢁ&RQGLWLRQV
6\PEROꢁ 3DUDPHWHUꢁ
0LQꢁ
0D[ꢁ
8QLWꢁ
9
2SHUDWLQJꢀ9ROWDJHꢀIRUꢀ,2ꢀ
2SHUDWLQJꢀ6XSSO\ꢀ9ROWDJHꢀ
ꢍꢅꢈ
ꢂꢅꢏꢎ
ꢃꢅꢈ9
ꢐꢈꢅꢍ
ꢈ
ꢍꢅꢏ
9
''4
9
ꢂꢅꢇꢎ
9
9
''
,QSXWꢀ+LJKꢀ9ROWDJH1
9
9
ꢓꢈꢅꢍ
,+
''4
,QSXWꢀ/RZꢀ9ROWDJH2
9
,/
ꢈꢅꢋ
ꢆꢈ
9
7
$PELHQWꢀ2SHUDWLQJꢀ7HPSHUDWXUHꢀ
°&
$
6XSSO\ꢀ9ROWDJHꢀ7ROHUDQꢄHꢀ
ꢐꢂꢈM
ꢓꢂꢈM
Notes:
1.
2.
Maximum allowable applies to overshoot only (V
Minimum allowable applies to undershoot only.
is 3.3 V supply).
DDQ
ꢌꢄ
$SULOꢁꢂꢀꢃꢁꢀꢄꢄꢂꢁ5HYꢅꢁꢄD
3DꢄNDJH
08$'ꢀꢁ+DUPRQ\ꢁꢀꢂ0ꢀDQGꢀꢃ0ꢀ7HUQDU\ꢀ&$0V
3$&.$*(
3LQꢀꢁꢀꢂꢀ&RUQHU
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢊ
ꢉ
ꢁꢀ ꢁꢁ ꢁꢂ ꢁꢃ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢊ ꢁꢉ ꢂꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢊ
ꢉ
ꢁꢀ ꢁꢁ ꢁꢂ ꢁꢃ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢊ ꢁꢉ ꢂꢀ
$
%
&
$
%
&
'
(
)
'
(
)
*
+
-
*
+
-
.
/
.
/
)
(
0
1
3
5
7
0
1
3
5
7
8
9
8
9
:
<
:
<
'
H
$
/
/ꢀ
E
6HDWLQJ#3ODQH
ꢀꢑꢀꢋ3LQꢁ%*$ꢁ'LPHQVLRQV
'LPꢅꢁ$
'LPꢅꢁE
'LPꢅꢁ'
'LPꢅꢁ(
'LPꢅꢁH
'LPꢅꢁꢊ
'LPꢅꢁ/
ꢈꢅꢎꢈ
/ꢂ
0LQꢅ
ꢃꢏꢅꢋꢈ
ꢃꢆꢅꢈꢈ
ꢃꢆꢅꢃꢈ
1RPꢅ
0D[ꢅ
ꢂꢅꢂꢆ
ꢈꢅꢈꢊ
ꢃꢊꢅꢈꢈ
ꢂꢅꢃꢆ
ꢃꢊꢅꢂꢍ
ꢈꢅꢏꢈ
ꢍꢈ°ꢀ7<3ꢅ
ꢈꢅꢆꢈ
5HYꢅꢁꢄDꢁ$SULOꢁꢂꢀꢃꢁꢀꢄꢄꢂ
ꢌꢂ
08$'ꢀꢁ+DUPRQ\ꢁꢀꢂ0ꢀDQGꢀꢃ0ꢀ7HUQDU\ꢀ&$0V
2UGHULQJ
25'(5,1*
3DUWꢁ1XPEHU
'HQVLW\
&ORꢇNꢁ6SHHG
3DꢇNDJH
7HPSHUDWXUH
9ROWDJH
08$'ꢂꢏ.ꢂꢍꢏꢐꢏꢏ%ꢃꢆꢃ&
08$'ꢂꢏ.ꢂꢍꢏꢐꢋꢍ%ꢃꢆꢃ&
08$'ꢂꢏ.ꢂꢍꢏꢐꢂꢈ%ꢃꢆꢃ&
ꢏꢏꢀ0+]
ꢋꢍꢀ0+]
ꢂꢈꢈꢀ0+]
ꢃꢆꢃꢐ3LQꢀ%*$
ꢃꢆꢃꢐ3LQꢀ%*$
ꢃꢆꢃꢐ3LQꢀ%*$
ꢈꢀꢐꢀꢆꢈ°
ꢈꢀꢐꢀꢆꢈ°
ꢈꢀꢐꢀꢆꢈ°
ꢂꢅꢋꢉꢍꢅꢍ9
ꢂꢅꢋꢉꢍꢅꢍ9
ꢂꢅꢋꢉꢍꢅꢍ9
ꢃ0ELW
08$'ꢋ.ꢂꢍꢏꢐꢏꢏ%ꢃꢆꢃ&
08$'ꢋ.ꢂꢍꢏꢐꢋꢍ%ꢃꢆꢃ&
08$'ꢋ.ꢂꢍꢏꢐꢂꢈ%ꢃꢆꢃ&
ꢏꢏꢀ0+]
ꢋꢍꢀ0+]
ꢂꢈꢈꢀ0+]
ꢃꢆꢃꢐ3LQꢀ%*$
ꢃꢆꢃꢐ3LQꢀ%*$
ꢃꢆꢃꢐ3LQꢀ%*$
ꢈꢀꢐꢀꢆꢈ°
ꢈꢀꢐꢀꢆꢈ°
ꢈꢀꢐꢀꢆꢈ°
ꢂꢅꢋꢉꢍꢅꢍ9
ꢂꢅꢋꢉꢍꢅꢍ9
ꢂꢅꢋꢉꢍꢅꢍ9
ꢂ0ELW
086,&ꢀ 6HPLꢄRQGXꢄWRUVꢀ UHVHUYHVꢀ WKHꢀ ULJKWꢀ WRꢀ PDNHꢀ ꢄKDQJHVꢀ WRꢀ LWVꢀ SURGXꢄWVꢀ DQG
VSHꢄLILꢄDWLRQVꢀ DWꢀ DQ\ꢀ WLPHꢀ LQꢀ RUGHUꢀ WRꢀ LPSURYHꢀ RQꢀ SHUIRUPDQꢄH#ꢀ PDQXIDꢄWXUDELOLW\ꢀ RU
UHOLDELOLW\ꢅꢀ ,QIRUPDWLRQꢀ IXUQLVKHGꢀ E\ꢀ 086,&ꢀ LVꢀ EHOLHYHGꢀ WRꢀ EHꢀ DꢄꢄXUDWH#ꢀ EXWꢀ QR
UHVSRQVLELOLW\ꢀLVꢀDVVXPHGꢀE\ꢀ086,&ꢀ6HPLꢄRQGXꢄWRUVꢀIRUꢀWKHꢀXVHꢀRIꢀVDLGꢀLQIRUPDWLRQ#ꢀQRU
IRUꢀDQ\ꢀLQIULQJHPHQWVꢀRIꢀSDWHQWVꢀRUꢀRIꢀRWKHUꢀWKLUGꢐSDUW\ꢀULJKWVꢀZKLꢄKꢀPD\ꢀUHVXOWꢀIURPꢀVDLG
XVHꢅꢀ1RꢀOLꢄHQVHꢀLVꢀJUDQWHGꢀE\ꢀLPSOLꢄDWLRQꢀRUꢀRWKHUZLVHꢀXQGHUꢀDQ\ꢀSDWHQWꢀRUꢀSDWHQWꢀULJKWVꢀRI
DQ\ꢀ086,&ꢀꢄRPSDQ\ꢅ
086,&ꢀ6HPLꢄRQGXꢄWRUV¶ꢀDJHQWꢀRUꢀGLVWULEXWRUꢌ
ꢀ&RS\ULJKWꢀꢀꢃꢈꢈꢂ#ꢀ086,&ꢀ6HPLꢄRQGXꢄWRUV
:RUOGZLGHꢁ+HDGTXDUWHUV
$VLDQꢁ+HDGTXDUWHUV
(XURSHDQꢁ+HDGTXDUWHUV
086,&ꢀ6HPLꢄRQGXꢄWRUV
3ꢅ ꢀ2ꢅꢀ%R[ꢀꢂꢋꢊ
086,&ꢀ6HPLꢄRQGXꢄWRUV
ꢂꢎꢃꢂꢀ&DOLIRUQLDꢀ&LUꢄOH
0LOSLWDV#ꢀ&$ꢀꢇꢎꢈꢍꢎ
086,&ꢀ6HPLꢄRQGXꢄWRUV
6SHꢄLDOꢀ([SRUWꢀ3URꢄHVVLQJꢀ=RQH
&DUPHOUD\ꢀ,QGXVWULDOꢀ3DUN
&DQOXEDQJ#ꢀ&DODPED#ꢀ/DJXQD
3KLOLSSLQHV
ꢏꢊꢆꢈꢀ('ꢀ(\JHOVKRYHQ
7KHꢀ1HWKHUODQGV
86$
7HOꢌꢀꢊꢈꢋꢀꢋꢏꢇꢐꢊꢏꢈꢈ
7HOꢌꢀꢓꢍꢂꢀꢊꢍꢀꢊꢎꢎꢐꢃꢏꢆꢎ
)D[ꢌꢀꢓꢍꢂꢀꢊꢍꢀꢊꢎꢎꢐꢂꢎꢆꢍ
)D[ꢌꢀꢊꢈꢋꢀꢇꢊꢃꢐꢈꢋꢍꢆ
7HOꢌꢀꢓꢏꢍꢀꢊꢇꢀꢎꢊꢇꢐꢂꢊꢋꢈ
KWWSꢆꢉꢉZZZꢅPXVLꢇVHPLꢅꢇRP
HPDLOꢆꢁLQIR#PXVLꢇVHPLꢅꢇRP
86$ꢀ2QO\ꢌꢀꢋꢈꢈꢀꢇꢍꢍꢐꢂꢎꢎꢈꢀ7HꢄKꢀ6XSSRUW
ꢋꢋꢋꢀꢃꢃꢏꢐꢏꢋꢆꢊꢀ3URGXꢄWꢀ,QIR
)D[ꢌꢀꢓꢏꢍꢀꢊꢇꢀꢎꢊꢇꢐꢂꢈꢃꢊ
6DOHVꢀ7HOꢉ)D[ꢌꢀꢓꢏꢍꢃꢀꢆꢃꢍꢐꢏꢃꢂꢎ
ꢌꢀ
$SULOꢁꢂꢀꢃꢁꢀꢄꢄꢂꢁ5HYꢅꢁꢄD
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明