29F040-12_技术文档

MX29F040

4M-BIT[512KX8]CMOSEQUALSECTORFLASHMEMORY

FEATURES

program data to, another sector that is not being

erased, then resumes the erase.

• 524,288 x 8 only

• Single power supply operation

- 5.0V only operation for read, erase and program op-

eration

• Status Reply

- Data polling & Toggle bit for detection of program

and erase cycle completion.

• Fast access time: 55/70/90/120ns

• Low power consumption

• Sector protect/unprotect for 5V only system or 5V/

12V system.

- 30mA maximum active current(5MHz)

- 1uA typical standby current

• Sector protection

- Hardware method to disable any combination of

sectors from program or erase operations

• 100,000 minimum erase/program cycles

• Latch-up protected to 100mA from -1V to VCC+1V

• Low VCC write inhibit is equal to or less than 3.2V

• Package type:

• Command register architecture

- Byte Programming (7us typical)

- Sector Erase

8 equal sectors of 64K-Byte each

• Auto Erase (chip & sector) and Auto Program

- Automatically erase any combination of sectors with

Erase Suspend capability.

- 32-pin PLCC, TSOP or PDIP

• Compatibility with JEDEC standard

- Pinout and software compatible with single-power

supply Flash

- Automatically program and verify data at specified

address

• Erase suspend/Erase Resume

- Suspends an erase operation to read data from, or

• 20 years data retention

GENERAL DESCRIPTION

The MX29F040 is a 4-mega bit Flash memory organized

as 512K bytes of 8 bits. MXIC's Flash memories offer

the most cost-effective and reliable read/write non-vola-

tile random access memory. The MX29F040 is pack-

aged in 32-pin PLCC, TSOP, PDIP. It is designed to be

reprogrammed and erased in system or in standard

EPROM programmers.

during erase and programming, while maintaining maxi-

mum EPROM compatibility.

MXIC Flash technology reliably stores memory

contents even after 100,000 erase and program

cycles. The MXIC cell is designed to optimize the

erase and program mechanisms. In addition, the

combination of advanced tunnel oxide processing

and low internal electric fields for erase and

programming operations produces reliable cycling.

The MX29F040 uses a 5.0V±10% VCC supply to

perform the High Reliability Erase and auto

Program/Erase algorithms.

The standard MX29F040 offers access time as fast as

55ns, allowing operation of high-speed microprocessors

without wait states. To eliminate bus contention, the

MX29F040 has separate chip enable (CE) and output

enable (OE) controls.

MXIC's Flash memories augment EPROM functionality

with in-circuit electrical erasure and programming. The

MX29F040 uses a command register to manage this

functionality. The command register allows for 100%

TTL level control inputs and fixed power supply levels

The highest degree of latch-up protection is

achieved with MXIC's proprietary non-epi process.

Latch-up protection is proved for stresses up to 100

milliamps on address and data pin from -1V to VCC

+ 1V.

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REV. 2.3, DEC. 10, 2004

1

MX29F040

PIN CONFIGURATIONS

32 PDIP

32 PLCC

VCC

WE

A17

A14

A13

A8

A18

A16

A15

A12

A7

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

1

2

3

4

1

32

30

29

5

9

A7

A6

A5

A4

A3

A2

A1

A0

Q0

A14

A13

A8

4

5

A6

6

A9

A5

7

A9

A11

OE

A10

CE

A4

8

A3

9

MX29F040

25

A11

OE

A10

CE

Q7

A2

10

11

12

13

14

15

16

A1

Q7

A0

Q6

Q0

Q5

Q1

13

14

21

Q4

Q2

17

20

Q3

GND

32TSOP (StandardType) (8mm x 20mm)

A11

A9

1

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

OE

A10

CE

Q7

Q6

Q5

Q4

Q3

GND

Q2

Q1

Q0

A0

2

A8

3

A13

A14

A17

WE

VCC

A18

A16

A15

A12

A7

4

5

6

7

8

MX29F040

9

10

11

12

13

14

15

16

A6

A1

A5

A2

A4

A3

SECTOR STRUCTURE

MX29F040 SECTOR ADDRESS TABLE

PIN DESCRIPTION

SYMBOL

A0~A18

Q0~Q7

CE

PIN NAME

Sector

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

A18

0

A17

0

A16 Address Range

Address Input

0

1

0

1

0

1

0

1

00000h-0FFFFh

10000h-1FFFFh

20000h-2FFFFh

30000h-3FFFFh

40000h-4FFFFh

50000h-5FFFFh

60000h-6FFFFh

70000h-7FFFFh

Data Input/Output

Chip Enable Input

Write Enable Input

Output Enable Input

Ground Pin

0

1

WE

0

1

OE

1

0

GND

1

0

VCC

+5.0V single power supply

1

Note: All sectors are 64 Kbytes in size.

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REV. 2.3, DEC. 10, 2004

2

MX29F040

BLOCK DIAGRAM

WRITE

STATE

CONTROL

INPUT

PROGRAM/ERASE

HIGH VOLTAGE

CE

OE

WE

MACHINE

(WSM)

LOGIC

STATE

MX29F040

FLASH

ADDRESS

LATCH

REGISTER

ARRAY

A0-A18

AND

SOURCE

HV

BUFFER

Y-PASS GATE

COMMAND

DATA

DECODER

PGM

SENSE

DATA

HV

AMPLIFIER

COMMAND

DATA LATCH

PROGRAM

DATA LATCH

Q0-Q7

I/O BUFFER

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REV. 2.3, DEC. 10, 2004

3

MX29F040

AUTOMATIC PROGRAMMING

AUTOMATIC ERASE ALGORITHM

The MX29F040 is byte programmable using the Auto-

matic Programming algorithm. The Automatic Program-

ming algorithm makes the external system do not need

to have time out sequence nor to verify the data pro-

grammed. The typical chip programming time at room

temperature of the MX29F040 is less than 4 seconds.

MXIC's Automatic Erase algorithm requires the user to

write commands to the command register using stand-

ard microprocessor write timings. The device will auto-

matically pre-program and verify the entire array. Then

the device automatically times the erase pulse width,

provides the erase verification, and counts the number

of sequences. A status bit toggling between consecu-

tive read cycles provides feedback to the user as to the

status of the programming operation.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 10 ms erase pulses

according to MXIC's Automatic Chip Erase algorithm.

Typical erasure at room temperature is accomplished in

less than 4 second. The Automatic Erase algorithm au-

tomatically programs the entire array prior to electrical

erase. The timing and verification of electrical erase are

controlled internally within the device.

Register contents serve as inputs to an internal state-

machine which controls the erase and programming cir-

cuitry. During write cycles, the command register inter-

nally latches address and data needed for the program-

ming and erase operations. During a system write cycle,

addresses are latched on the falling edge of WE or CE,

whichever happens later, and data are latched on the

rising edge of WE or CE, whichever happens first.

MXIC's Flash technology combines years of EPROM

experience to produce the highest levels of quality, relia-

bility, and cost effectiveness.The MX29F040 electrically

erases all bits simultaneously using Fowler-Nordheim

tunneling. The bytes are programmed by using the

EPROM programming mechanism of hot electron injec-

tion.

AUTOMATIC SECTOR ERASE

The MX29F040 is sector(s) erasable using MXIC's

Auto Sector Erase algorithm. Sector erase modes

allow sectors of the array to be erased in one erase

cycle. The Automatic Sector Erase algorithm

automatically programs the specified sector(s) prior to

electrical erase. The timing and verification of

electrical erase are controlled internally within the

device.

During a program cycle, the state-machine will control

the program sequences and command register will not

respond to any command set. During a Sector Erase

cycle, the command register will only respond to Erase

Suspend command. After Erase Suspend is completed,

the device stays in read mode. After the state machine

has completed its task, it will allow the command regis-

ter to respond to its full command set.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm require the user

to only write program set-up commands (including 2 un-

lock write cycle and A0H) and a program command (pro-

gram data and address). The device automatically times

the programming pulse width, provides the program veri-

fication, and counts the number of sequences. A status

bit similar to DATA polling and a status bit toggling be-

tween consecutive read cycles, provide feedback to the

user as to the status of the programming operation.

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4

MX29F040

TABLE 1. SOFTWARE COMMAND DEFINITIONS

First Bus

Cycle

Second Bus Third Bus

Cycle Cycle

Fourth Bus

Cycle

Fifth Bus

Cycle

Sixth Bus

Cycle

Command

Bus

Cycle Addr

XXXH F0H

RA RD

555H AAH 2AAH 55H 555H 90H ADI

555H AAH 2AAH 55H 555H 90H (SA)X 00H

Data Addr Data Addr Data Addr Data Addr Data Addr Data

Reset

1

Read

1

Read Silicon ID

Sector Protect Verify

4

DDI

02

01H

PD

Program

4

6

1

6

555H AAH 2AAH 55H 555H A0H PA

Chip Erase

555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H

XXXH B0H

555H 10H

SA 30H

Sector Erase

Sector Erase Suspend

Sector Erase Resume

Unlock for sector

protect/unprotect

XXXH 30H

555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H

555H 20H

Note:

1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacture code,A1=0, A0 = 1 for device code A2-A18=Do

not care.

(Refer to table 3)

DDI = Data of Device identifier : C2H for manufacture code, A4H for device code.

X = X can be VIL or VIH

RA=Address of memory location to be read.

RD=Data to be read at location RA.

2. PA = Address of memory location to be programmed.

PD = Data to be programmed at location PA.

SA = Address to the sector to be erased.

3. The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 .

Address bit A11~A18=X=Don't care for all address commands except for Program Address (PA) and Sector

Address (SA). Write Sequence may be initiated with A11~A18 in either state.

4. For Sector Protect Verify Operation : If read out data is 01H, it means the sector has been protected. If read out

data is 00H, it means the sector is still not being protected.

COMMAND DEFINITIONS

Device operations are selected by writing specific ad-

dress and data sequences into the command register.

Writing incorrect address and data values or writing them

in the improper sequence will reset the device to the

read mode. Table 1 defines the valid register command

sequences. Note that the Erase Suspend (B0H) and

Erase Resume (30H) commands are valid only while the

Sector Erase operation is in progress. Either of the two

reset command sequences will reset the device (when

applicable).

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5

MX29F040

TABLE 2. MX29F040 BUS OPERATION

Mode

Pins

CE

L

OE

WE

A0

A1

A6

A9

Q0 ~ Q7

Read Silicon ID

Manufacturer Code(1)

Read Silicon ID

Device Code(1)

Read

L

H

L

X

V_ID(2)

C2H

L

H

L

X

V_ID(2)

A4H

L

H

L

H

X

H

L

A0

X

A1

X

A6

X

A9

X

D_OUT

Standby

X

HIGH Z

D_IN(3)

X

Output Disable

Write

H

X

H

A0

X

A1

X

A6

L

A9

V_ID(2)

Sector Protect with 12V

system(6)

V_ID(2)

L

Chip Unprotect with 12V

system(6)

L

X

V_ID(2)

L

X

H

X

H

X

H

X

L

V_ID(2)

H

X

Verify Sector Protect

with 12V system

Sector Protect without 12V

system (6)

L

H

L

Code(5)

X

H

L

Chip Unprotect without 12V

system (6)

L

H

X

H

X

Verify Sector Protect/Unprotect

without 12V system (7)

Reset

H

X

H

Code(5)

HIGH Z

X

NOTES:

1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1.

2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.

3. Refer to Table 1 for valid Data-In during a write operation.

4. X can be VIL or VIH.

5. Code=00H means unprotected.

Code=01H means protected.

A18~A16=Sector address for sector protect.

6. Refer to sector protect/unprotect algorithm and waveform.

Must issue "unlock for sector protect/unprotect" command before "sector protect/unprotect without 12V system" command.

7. The "verify sector protect/unprotect without 12V system" is only following "Sector protect/unprotect without 12V system"

command.

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6

MX29F040

READ/RESET COMMAND

SET-UP AUTOMATIC CHIP/SECTOR ERASE

The read or reset operation is initiated by writing the

read/reset command sequence into the command reg-

ister. Microprocessor read cycles retrieve array data.

The device remains enabled for reads until the command

register contents are altered.

Chip erase is a six-bus cycle operation. There are two

"unlock" write cycles. These are followed by writing the

"set-up" command 80H. Two more "unlock" write cy-

cles are then followed by the chip erase command 10H.

The Automatic Chip Erase does not require the device

to be entirely pre-programmed prior to executing the Au-

tomatic Chip Erase. Upon executing the Automatic Chip

Erase, the device will automatically program and verify

the entire memory for an all-zero data pattern. When the

device is automatically verified to contain an all-zero

pattern, a self-timed chip erase and verify begin. The

erase and verify operations are completed when the data

on Q7 is "1" at which time the device returns to the

Read mode. The system is not required to provide any

control or timing during these operations.

If program-fail or erase-fail happen, the write of F0H will

reset the device to abort the operation. A valid com-

mand must then be written to place the device in the

desired state.

SILICON-ID-READ COMMAND

Flash memories are intended for use in applications where

the local CPU alters memory contents. As such, manu-

facturer and device codes must be accessible while the

device resides in the target system. PROM program-

mers typically access signature codes by raising A9 to

a high voltage. However, multiplexing high voltage onto

address lines is not generally desired system design

practice.

When using the Automatic Chip Erase algorithm, note

that the erase automatically terminates when adequate

erase margin has been achieved for the memory array

(no erase verification command is required).

If the Erase operation was unsuccessful, the data on

Q5 is "1"(see Table 4), indicating the erase operation

exceed internal timing limit.

The MX29F040 contains a Silicon-ID-Read operation to

supplement traditional PROM programming methodol-

ogy. The operation is initiated by writing the read silicon

ID command sequence into the command register. Fol-

lowing the command write, a read cycle with

A1=VIL,A0=VIL retrieves the manufacturer code of C2H.

A read cycle with A1=VIL, A0=VIH returns the device

code of A4H for MX29F040.

The automatic erase begins on the rising edge of the

lastWE or CE, whichever happens first pulse in the com-

mand sequence and terminates when the data on Q7 is

"1" and the data on Q6 stops toggling for two consecu-

tive read cycles, at which time the device returns to the

Read mode.

TABLE 3. EXPANDED SILICON ID CODE

Pins

A0

A1

Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Code(Hex)

Manufacturecode

VIL VIL

1

0

1

0

1

0

1

0

1

0

1

0

C2H

Device code for MX29F040 VIH VIL

A4H

Sector Protection Verification X

X

VIH

01H(Protected)

00H(Unprotected)

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7

MX29F040

SECTOR ERASE COMMANDS

The Automatic Sector Erase does not require the device

to be entirely pre-programmed prior to executing the Au-

tomatic Set-up Sector Erase command and Automatic

Sector Erase command. Upon executing the Automatic

Sector Erase command, the device will automatically

program and verify the sector(s) memory for an all-zero

data pattern. The system is not required to provide any

control or timing during these operations.

(no erase verification command is required). Sector erase

is a six-bus cycle operation. There are two "unlock"

write cycles. These are followed by writing the set-up

command 80H. Two more "unlock" write cycles are then

followed by the sector erase command 30H. The sector

address is latched on the falling edge ofWE or CE, which-

ever happens later, while the command (data) is latched

on the rising edge ofWE or CE, whichever happens first.

Sector addresses selected are loaded into internal reg-

ister on the sixth falling edge of WE or CE, whichever

happens later. Each successive sector load cycle

started by the falling edge of WE or CE, whichever hap-

pens later must begin within 30us from the rising edge

of the preceding WE or CE, whichever happens first.

Otherwise, the loading period ends and internal auto

sector erase cycle starts. (Monitor Q3 to determine if

the sector erase timer window is still open, see section

Q3, Sector EraseTimer.) Any command other than Sec-

tor Erase (30H) or Erase Suspend (B0H) during the time-

out period resets the device to read mode.

When the sector(s) is automatically verified to contain

an all-zero pattern, a self-timed sector erase and verify

begin. The erase and verify operations are complete

when the data on Q7 is "1" and the data on Q6 stops

toggling for two consecutive read cycles, at which time

the device returns to the Read mode. The system is not

required to provide any control or timing during these

operations.

When using the Automatic Sector Erase algorithm, note

that the erase automatically terminates when adequate

erase margin has been achieved for the memory array

TABLE 4. Write Operation Status

Status

Q7

Q6

Q5

Q3

Q2

Note1

Note2

Byte Program in Auto Program Algorithm

Auto Erase Algorithm

Q7 Toggle

0

N/A No Toggle

0

1

Toggle

No

1

Toggle

Erase Suspend Read

N/A

In Progress

(Erase Suspended Sector)

Erase Suspend Read

Toggle

Erase Suspended Mode

Data Data Data Data

Data

N/A

(Non-Erase Suspended Sector)

Erase Suspend Program

Q7 Toggle

0

1

N/A

Byte Program in Auto Program Algorithm

N/A No Toggle

Exceeded Auto Erase Algorithm

0

Toggle

1

Toggle

N/A

Time Limits Erase Suspend Program

Q7 Toggle

N/A

Note:

1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further

details.

2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.

See "Q5:Exceeded Timing Limits " for more information.

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REV. 2.3, DEC. 10, 2004

8

MX29F040

tem is not required to provide further controls or timings.

The device will automatically provide an adequate inter-

nally generated program pulse and verify margin.

ERASE SUSPEND

This command only has meaning while the state ma-

chine is executing Automatic Sector Erase operation,

and therefore will only be responded during Automatic

Sector Erase operation. When the Erase Suspend com-

mand is written during a sector erase operation, the de-

vice requires a maximum of 100us to suspend the erase

operations.However,When the Erase Suspend command

is written during the sector erase time-out, the device

immediately terminates the time-out period and suspends

the erase operation. After this command has been ex-

ecuted, the command register will initiate erase suspend

mode. The state machine will return to read mode auto-

matically after suspend is ready. At this time, state ma-

chine only allows the command register to respond to

the Read Memory Array, Erase Resume and program

commands.

If the program operation was unsuccessful, the data on

Q5 is "1"(seeTable 4), indicating the program operation

exceed internal timing limit.The automatic programming

operation is completed when the data read on Q6 stops

toggling for two consecutive read cycles and the data

on Q7 and Q6 are equivalent to data written to these two

bits, at which time the device returns to the Read mode

(no program verify command is required).

DATA POLLING-Q7

The MX29F040 also features Data Polling as a method

to indicate to the host system that the Automatic Pro-

gram or Erase algorithms are either in progress or com-

pleted.

The system can determine the status of the program

operation using the Q7 or Q6 status bits, just as in the

standard program operation. After an erase-suspend pro-

gram operation is complete, the system can once again

read array data within non-suspended sectors.

While the Automatic Programming algorithm is in opera-

tion, an attempt to read the device will produce the

complement data of the data last written to Q7. Upon

completion of the Automatic Program Algorithm an at-

tempt to read the device will produce the true data last

written to Q7. The Data Polling feature is valid after the

rising edge of the fourth WE or CE, whichever happens

first pulse of the four write pulse sequences for auto-

matic program.

ERASE RESUME

This command will cause the command register to clear

the suspend state and return back to Sector Erase mode

but only if an Erase Suspend command was previously

issued. Erase Resume will not have any effect in all

other conditions. Another Erase Suspend command can

be written after the chip has resumed erasing.

While the Automatic Erase algorithm is in operation, Q7

will read "0" until the erase operation is competed. Upon

completion of the erase operation, the data on Q7 will

read "1". The Data Polling feature is valid after the rising

edge of the sixth WE or CE, whichever happens first

pulse of six write pulse sequences for automatic chip/

sector erase.

SET-UP AUTOMATIC PROGRAM COMMANDS

To initiate Automatic Program mode, A three-cycle com-

mand sequence is required. There are two "unlock" write

cycles. These are followed by writing the Automatic Pro-

gram command A0H.

The Data Polling feature is active during Automatic Pro-

gram/Erase algorithm or sector erase time-out. (see sec-

tion Q3 Sector Erase Timer)

Once the Automatic Program command is initiated, the

next WE or CE pulse causes a transition to an active

programming operation. Addresses are latched on the

falling edge, and data are internally latched on the

rising edge of the WE or CE, whichever happens first

pulse. The rising edge ofWE or CE, whichever happens

first also begins the programming operation. The sys-

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9

MX29F040

that sector is erase-suspended. Toggle Bit I is valid af-

ter the rising edge of the final WE or CE, whichever hap-

pens first pulse in the command sequence.

Q6:Toggle BIT I

Toggle Bit I on Q6 indicates whether an Automatic Pro-

gram or Erase algorithm is in progress or complete, or

whether the device has entered the Erase Suspend mode.

Toggle Bit I may be read at any address, and is valid

after the rising edge of the final WE or CE, whichever

happens first pulse in the command sequence (prior to

the program or erase operation), and during the sector

time-out.

Q2 toggles when the system reads at addresses within

those sectors that have been selected for erasure. (The

system may use either OE or CE to control the read

cycles.) But Q2 cannot distinguish whether the sector

is actively erasing or is erase-suspended. Q6, by com-

parison, indicates whether the device is actively eras-

ing, or is in Erase Suspend, but cannot distinguish which

sectors are selected for erasure. Thus, both status bits

are required for sectors and mode information. Refer to

Table 4 to compare outputs for Q2 and Q6.

During an Automatic Program or Erase algorithm opera-

tion, successive read cycles to any address cause Q6

to toggle. The system may use either OE or CE to con-

trol the read cycles.When the operation is complete, Q6

stops toggling.

Reading Toggle Bits Q6/ Q2

After an erase command sequence is written, if all sec-

tors selected for erasing are protected, Q6 toggles and

returns to reading array data. If not all selected sectors

are protected, the Automatic Erase algorithm erases the

unprotected sectors, and ignores the selected sectors

that are protected.

Whenever the system initially begins reading toggle bit

status, it must read Q7-Q0 at least twice in a row to

determine whether a toggle bit is toggling. Typically, the

system would note and store the value of the toggle bit

after the first read. After the second read, the system

would compare the new value of the toggle bit with the

first. If the toggle bit is not toggling, the device has

completed the program or erase operation. The system

can read array data on Q7-Q0 on the following read cycle.

The system can use Q6 and Q2 together to determine

whether a sector is actively erasing or is erase sus-

pended.When the device is actively erasing (that is, the

Automatic Erase algorithm is in progress), Q6 toggling.

When the device enters the Erase Suspend mode, Q6

stops toggling. However, the system must also use Q2

to determine which sectors are erasing or erase-sus-

pended. Alternatively, the system can use Q7.

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of Q5 is high

(see the section on Q5). If it is, the system should then

determine again whether the toggle bit is toggling, since

the toggle bit may have stopped toggling just as Q5 went

high. If the toggle bit is no longer toggling, the device

has successfully completed the program or erase op-

eration. If it is still toggling, the device did not complete

the operation successfully, and the system must write

the reset command to return to reading array data.

If a program address falls within a protected sector, Q6

toggles for approximately 2us after the program com-

mand sequence is written, then returns to reading array

data.

Q6 also toggles during the erase-suspend-program mode,

and stops toggling once the Automatic Program algo-

rithm is complete.

The remaining scenario is that system initially determines

that the toggle bit is toggling and Q5 has not gone high.

The system may continue to monitor the toggle bit and

Q5 through successive read cycles, determining the sta-

tus as described in the previous paragraph. Alterna-

tively, it may choose to perform other system tasks. In

this case, the system must start at the beginning of the

algorithm when it returns to determine the status of the

operation.

Table 4 shows the outputs for Toggle Bit I on Q6.

Q2:Toggle Bit II

The "Toggle Bit II" on Q2, when used with Q6, indicates

whether a particular sector is actively erasing (that is,

the Automatic Erase algorithm is in process), or whether

P/N:PM0538

REV. 2.3, DEC. 10, 2004

10

MX29F040

specific command sequences. The device also incor-

porates several features to prevent inadvertent write

cycles resulting fromVCC power-up and power-down tran-

sition or system noise.

Q5

Exceeded Timing Limits

Q5 will indicate if the program or erase time has ex-

ceeded the specified limits (internal pulse count). Under

these conditions Q5 will produce a "1". This time-out

condition indicates that the program or erase cycle was

not successfully completed. Data Polling andToggle Bit

are the only operating functions of the device under this

condition.

Q3

Sector Erase Timer

After the completion of the initial sector erase command

sequence, the sector erase time-out will begin. Q3 will

remain low until the time-out is complete. Data Polling

andToggle Bit are valid after the initial sector erase com-

mand sequence.

If this time-out condition occurs during sector erase op-

eration, it specifies that a particular sector is bad and it

may not be reused. However, other sectors are still func-

tional and may be used for the program or erase opera-

tion. The device must be reset to use other sectors.

Write the Reset command sequence to the device, and

then execute program or erase command sequence. This

allows the system to continue to use the other active

sectors in the device.

If Data Polling or the Toggle Bit indicates the device has

been written with a valid erase command, Q3 may be

used to determine if the sector erase timer window is

still open. If Q3 is high ("1") the internally controlled

erase cycle has begun; attempts to write subsequent

commands to the device will be ignored until the erase

operation is completed as indicated by Data Polling or

Toggle Bit. If Q3 is low ("0"), the device will accept

additional sector erase commands. To insure the com-

mand has been accepted, the system software should

check the status of Q3 prior to and following each sub-

sequent sector erase command. If Q3 were high on the

second status check, the command may not have been

accepted.

If this time-out condition occurs during the chip erase

operation, it specifies that the entire chip is bad or com-

bination of sectors are bad.

If this time-out condition occurs during the byte program-

ming operation, it specifies that the entire sector con-

taining that byte is bad and this sector may not be re-

used, (other sectors are still functional and can be re-

used).

The time-out condition may also appear if a user tries to

program a non blank location without erasing. In this

case the device locks out and never completes the Au-

tomatic Algorithm operation. Hence, the system never

reads a valid data on Q7 bit and Q6 never stops tog-

gling. Once the Device has exceeded timing limits, the

Q5 bit will indicate a "1". Please note that this is not a

device failure condition since the device was incorrectly

used.

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5ns (typical) on CE or WE will

not initiate a write cycle.

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE = VIL, CE

= VIH or WE = VIH. To initiate a write cycle CE and WE

must be a logical zero while OE is a logical one.

DATA PROTECTION

The MX29F040 is designed to offer protection against

accidental erasure or programming caused by spurious

system level signals that may exist during power transi-

tion. During power up the device automatically resets

the state machine in the Read mode. In addition, with

its control register architecture, alteration of the memory

contents only occurs after successful completion of

POWER SUPPLY DECOUPLING

In order to reduce power switching effect, each device

should have a 0.1uF ceramic capacitor connected be-

tween itsVCC and GND.

P/N:PM0538

REV. 2.3, DEC. 10, 2004

11

MX29F040

is noted that all sectors are unprotected after the chip

unprotect algorithm is completed.

SECTOR PROTECTION WITH 12V SYSTEM

The MX29F040 features sector protection. This feature

will disable both program and erase operations for these

sectors protected. To activate this mode, the program-

ming equipment must force VID on address pin A9 and

control pin OE, (suggest VID = 12V) A6 = VIL and CE =

VIL. (see Table 2) Programming of the protection cir-

cuitry begins on the falling edge of the WE or CE, which-

ever happens later pulse and is terminated on the rising

edge. Please refer to sector protect algorithm and wave-

form.

POWER-UP SEQUENCE

The MX29F040 powers up in the Read only mode. In

addition, the memory contents may only be altered after

successful completion of the predefined command se-

quences.

SECTOR PROTECTION WITHOUT 12V SYS-

TEM

To verify programming of the protection circuitry, the pro-

gramming equipment must force VID on address pin A9

( with CE and OE at VIL and WE at VIH). When A1=1, it

will produce a logical "1" code at device output Q0 for a

protected sector. Otherwise the device will produce 00H

for the unprotected sector. In this mode, the addresses,

except for A1, are don't care. Address locations with A1

=VIL are reserved to read manufacturer and device codes.

(Read Silicon ID)

The MX29F040 also feature a sector protection method

in a system without 12V power supply.The programming

equipment do not need to supply 12 volts to protect sec-

tors. The details are shown in sector protect algorithm

and waveform.

CHIP UNPROTECT WITHOUT 12V SYSTEM

It is also possible to determine if the sector is protected

in the system by writing a Read Silicon ID command.

Performing a read operation with A1=VIH, it will produce

a logical "1" at Q0 for the protected sector.

The MX29F040 also feature a chip unprotection method

in a system without 12V power supply.The programming

equipment do not need to supply 12 volts to unprotect all

sectors. The details are shown in chip unprotect algo-

rithm and waveform.

CHIP UNPROTECT WITH 12V SYSTEM

The MX29F040 also features the chip unprotect mode,

so that all sectors are unprotected after chip unprotect

is completed to incorporate any changes in the code. It

is recommended to protect all sectors before activating

chip unprotect mode.

To activate this mode, the programming equipment must

forceVID on control pin OE and address pin A9. The CE

pins must be set atVIL. Pins A6 must be set toVIH.(see

Table 2) Refer to chip unprotect algorithm and wave-

form for the chip unprotect algorithm. The unprotection

mechanism begins on the falling edge of the WE or CE,

whichever happens later, pulse and is terminated on the

rising edge.

It is also possible to determine if the chip is unprotected

in the system by writing the Read Silicon ID command.

Performing a read operation with A1=VIH, it will produce

00H at data outputs(Q0-Q7) for an unprotected sector.It

P/N:PM0538

REV. 2.3, DEC. 10, 2004

12

MX29F040

CAPACITANCE (TA = 25^oC, f = 1.0 MHz)

SYMBOL

CIN1

PARAMETER

MIN.

TYP

MAX.

8

UNIT

pF

CONDITIONS

VIN = 0V

Input Capacitance

Control Pin Capacitance

Output Capacitance

CIN2

12

pF

VIN = 0V

COUT

12

pF

VOUT = 0V

READ OPERATION

DC CHARACTERISTICS (TA = 0^°CTO 70^°C, -40^oC to 85^oC,VCC = 5V±10%)

SYMBOL PARAMETER

MIN.

TYP

MAX.

UNIT

uA

mA

uA

mA

V

CONDITIONS

ILI

Input Leakage Current

1

VIN = GND to VCC

VOUT = GND to VCC

CE = VIH

ILO

Output Leakage Current

Standby VCC current

10

ISB1

ISB2

ICC1

ICC2

VIL

1

5

CE = VCC + 0.3V

IOUT = 0mA, f=5MHz

IOUT = 0mA, f=10MHz

Operating VCC current

30

50

Input Low Voltage

-0.3(NOTE 1)

2.0

0.8

VIH

Input High Voltage

VCC + 0.3

0.45

V

VOL

VOH1

VOH2

Output Low Voltage

Output High Voltage(TTL)

V

IOL = 2.1mA

2.4

V

IOH = -2mA

Output High Voltage(CMOS) VCC-0.4

V

IOH = -100uA,VCC=VCC MIN

NOTES:

1. VIL min. = -1.0V for pulse width is equal to or less than 50 ns.

VIL min. = -2.0V for pulse width is equal to or less than 20 ns.

2. VIH max. = VCC + 1.5V for pulse width is equal to or less

than 20 ns.

IfVIHisoverthespecifiedmaximumvalue, readoperation

cannot be guaranteed.

AC CHARACTERISTICS (TA = 0^oC to 70^oC, -40^oC to 85^oC,VCC = 5V±10%)

29F040-55(note2)29F040-70 29F040-90 29F040-12

MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. Unit Conditions

55

Symbol PARAMETER

tACC Address to Output Delay

70

40

30

90

40

120

50

ns

CE=OE=VIL

OE=VIL

tCE

tOE

tDF

tOH

CE to Output Delay

55

30

OE to Output Delay

CE=VIL

OE High to Output Float (Note1)0

0

40

CE=VIL

Address to Output hold

0

CE=OE=VIL

TEST CONDITIONS:

NOTE:

•

Input pulse levels: 0.45V/2.4V

1. tDF is defined as the time at which the output achieves the

open circuit condition and data is no longer driven.

2. Under condition of VCC=5V±10%,CL=50pF,VIH/VIL=3.0/

0V,VOH/VOL=1.5/1.5V,IOL=2mA,IOH=-2mA.

Input rise and fall times is equal to or less than 0ns

Output load: 1 TTL gate + 100pF (Including scope and jig)

Reference levels for measuring timing: 0.8V, 2.0V

P/N:PM0538

REV. 2.3, DEC. 10, 2004

13

MX29F040

NOTICE:

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed under ABSOLUTE

MAXIMUM RATINGS may cause permanent damage to

the device. This is a stress rating only and functional

operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for

extended period may affect reliability.

RATING

VALUE

Ambient Operating Temperature -40^oC to 85^oC

Storage Temperature

Ambient Temperature with Power -55^oC to 125^oC

-65^oC to 125^oC

Applied

NOTICE:

Applied Input Voltage

Applied Output Voltage

VCC to Ground Potential

A9 & OE

-0.5V to 7.0V

-0.5V to 13.5V

Specifications contained within the following tables are

subject to change.

READ TIMING WAVEFORMS

VIH

ADD Valid

Addresses

VIL

tCE

VIH

CE

VIL

VIH

WE

tDF

VIL

tOE

VIH

OE

tACC

VIL

tOH

HIGH Z

VOH

VOL

Outputs

DATA Valid

COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION

DC CHARACTERISTICS (TA = 0^oC to 70^oC, -40^oC to 85^oC,VCC = 5V±10%)

SYMBOL

PARAMETER

MIN.

TYP

MAX.

30

UNIT

mA

CONDITIONS

ICC1 (Read)

ICC2

Operating VCC Current

IOUT=0mA, f=5MHz

IOUT=0mA, F=10MHz

In Programming

50

ICC3 (Program)

ICC4 (Erase)

ICCES

50

In Erase

VCC Erase Suspend Current

2

CE=VIH, Erase Suspended

NOTES:

3. ICCES is specified with the device de-selected. If the

device is read during erase suspend mode, current draw

is the sum of ICCES and ICC1 or ICC2.

1. VILmin.=-0.6Vforpulsewidthisequaltoorlessthan20ns.

2. If VIH is over the specified maximum value, programming

operation cannot be guaranteed.

4. All current are in RMS unless otherwise noted.

P/N:PM0538

REV. 2.3, DEC. 10, 2004

14

MX29F040

AC CHARACTERISTICS TA = 0^oC to 70^oC, -40^oC to 85^oC,VCC = 5V ± 10%

29F040-55(Note2) 29F040-70

29F040-90

29F040-12

SYMBOL PARAMETER

MIN.

50

70

45

20

0

MAX. MIN.

MAX. MIN. MAX. MIN.

MAX. Unit

tOES

tCWC

tCEP

tCEPH1

tCEPH2

tAS

OE setup time

50

90

45

20

0

50

120

50

20

0

ns

Command programming cycle

WE programming pulse width

WE programming pulse width High

Address setup time

70

45

20

0

tAH

Address hold time

45

30

0

45

0

50

0

tDS

Data setup time

30

tDH

Data hold time

0

tCESC

tDF

CE setup time before command write

Output disable time (Note 1)

Total erase time in auto chip erase

Total erase time in auto sector erase

Total programming time in auto verify

Sector address load time

CE Hold Time

0

30

40

ns

s

tAETC

tAETB

tAVT

4(TYP.) 32

1.3(TYP.)10.4 1.3(TYP.) 10.4

1.3(TYP.)10.4

s

7

210

7

210

7

210

7

210

us

ns

us

ms

tBAL

100

0

100

0

100

0

100

0

tCH

tCS

CE setup to WE going low

Voltage Transition Time

0

tVLHT

tOESP

tWPP1

tWPP2

4

OE Setup Time to WE Active

Write pulse width for sector protect

4

10

12

10

12

10

12

Write pulse width for sector unprotect 12

NOTES:

1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.

2. Under conditions of VCC=5V±10%,CL=50pF,VIH/VIL=3.0/0V,VOL/VOH=1.5/1.5, IOL=2mA,IOH=-2mA.

P/N:PM0538

REV. 2.3, DEC. 10, 2004

15

MX29F040

SWITCHING TEST CIRCUITS

DEVICE UNDER

TEST

1.6K ohm

+5V

CL

DIODES=IN3064

OR EQUIVALENT

1.2K ohm

CL=100pF Including jig capacitance

CL= 50pF for 29F040-55

SWITCHING TEST WAVEFORMS

2.4V

2.0V

0.8V

2.0V

TEST POINTS

0.8V

0.45V

INPUT

OUTPUT

AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0".

Input pulse rise and fall times are < 20ns.(5ns for 29F040-55)

Note:VIH/VIL=3.0/0V,VOH/VOL=1.5/1.5V for 29F040-55

COMMAND WRITE TIMING WAVEFORM

VCC

5V

VIH

VIL

Addresses

ADD Valid

tAH

tAS

VIH

VIL

WE

CE

tOES

tCEPH1

tCEP

tCWC

VIH

VIL

tCS

tCH

tDH

VIH

VIL

OE

tDS

VIH

VIL

Data

DIN

P/N:PM0538

REV. 2.3, DEC. 10, 2004

16

MX29F040

AUTOMATIC PROGRAMMING TIMING WAVEFORM

One byte data is programmed. Verify in fast algorithm

and additional programming by external control are not

required because these operations are executed auto-

matically by internal control circuit. Programming

completion can be verified by DATA polling and toggle

bit checking after automatic verification starts. Device

outputs DATA during programming and DATA after pro-

gramming on Q7.(Q6 is for toggle bit; see toggle bit,

DATA polling, timing waveform)

AUTOMATIC PROGRAMMING TIMING WAVEFORM

Vcc 5V

A11~A18

ADD Valid

2AAH

555H

ADD Valid

tAVT

A0~A10

WE

555H

tAS

tCWC

tCEPH1

tAH

tCESC

CE

OE

tCEP

tDS tDH

tDF

Q0,Q1,Q2

Q4(Note 1)

DATA

Command In

Data In

DATA polling

DATA

Command In

Q7

Command #A0H

Command #55H

Command #AAH

(Q0~Q7)

tOE

Notes:

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit

P/N:PM0538

REV. 2.3, DEC. 10, 2004

17

MX29F040

AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data A0H Address 555H

Write Program Data/Address

NO

Toggle Bit Checking

Q6 not Toggled

YES

NO

Invalid

Verify Byte Ok

Command

YES

NO

.

Q5 = 1

Reset

Auto Program Completed

YES

Auto Program Exceed

Timing Limit

P/N:PM0538

REV. 2.3, DEC. 10, 2004

18

MX29F040

AUTOMATIC CHIP ERASE TIMING WAVEFORM

All data in chip are erased. External erase verification is

not required because data is erased automatically by

internal control circuit. Erasure completion can be

verified by DATA polling and toggle bit checking after

automaticerasestarts. Deviceoutputs0duringerasure

and1aftererasureonQ7.(Q6isfortogglebit;seetoggle

bit, DATA polling, timing waveform)

AUTOMATIC CHIP ERASE TIMING WAVEFORM

Vcc 5V

A11~A18

2AAH

555H

2AAH

555H

A0~A10

WE

555H

tAS

tCWC

tAH

tCEPH1

tAETC

CE

OE

tCEP

tDS tDH

Command In

Q0,Q1,

Command In

Q4(Note 1)

DATA polling

Command In

Q7

Command #80H

Command #AAH

Command #55H

Command #10H

Command #AAH

(Q0~Q7)

Command #55H

Notes:

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

P/N:PM0538

REV. 2.3, DEC. 10, 2004

19

MX29F040

AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 80H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 10H Address 555H

NO

Toggle Bit Checking

Q6 not Toggled

YES

NO

Invalid

DATA Polling

Q7 = 1

Command

YES

.

Q5 = 1

Auto Chip Erase Completed

YES

Reset

Auto Chip Erase Exceed

Timing Limit

P/N:PM0538

REV. 2.3, DEC. 10, 2004

20

MX29F040

AUTOMATIC SECTOR ERASE TIMING WAVEFORM

Sector dataindicatedbyA16toA18areerased. External

erase verify is not required because data are erased

automaticallybyinternalcontrolcircuit. Erasurecomple-

tion can be verified by DATA polling and toggle bit

checking after automatic erase starts. Device outputs 0

duringerasureand1aftererasureonQ7.(Q6isfortoggle

bit; see toggle bit, DATA polling, timing waveform)

AUTOMATIC SECTOR ERASE TIMING WAVEFORM

Vcc 5V

Sector

Addressn

Sector

Address0

Sector

Address1

A16-A18

555H

tAS

2AAH

A0~A10

tCWC

tAH

WE

CE

tCEPH1

tBAL

tAETB

tCEP

tDS

OE

tDH

Command

In

Command

In

Q0,Q1,

Command

In

Command

In

Command

In

Command

In

Command

In

Command

In

Q4(Note 1)

DATA polling

Command

In

Command

In

Command

In

Command

In

Command

In

Command

In

Command

In

Command

In

Q7

Command #AAH Command #55H Command #80H Command #AAH Command #55H Command #30H

(Q0~Q7)

Command #30H

Notes:

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

P/N:PM0538

REV. 2.3, DEC. 10, 2004

21

MX29F040

AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 80H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 30H Sector Address

NO

Toggle Bit Checking

Invalid Command

Q6 Toggled ?

YES

Load Other Sector Addrss If Necessary

(Load Other Sector Address)

NO

Last Sector

to Erase

YES

NO

Time-out Bit

Checking Q3=1 ?

YES

Toggle Bit Checking

Q6 not Toggled

YES

.

Q5 = 1

Reset

DATA Polling

Q7 = 1

Auto Sector Erase Completed

Auto Sector Erase Exceed

Timing Limit

P/N:PM0538

REV. 2.3, DEC. 10, 2004

22

MX29F040

ERASE SUSPEND/ERASE RESUME FLOWCHART

START

Write Data B0H

NO

Toggle Bit checking Q6

not toggled

YES

Read Array or

Program

Reading or

NO

Programming End

YES

Write Data 30H

Continue Erase

Another

.

NO

Erase Suspend ?

YES

P/N:PM0538

REV. 2.3, DEC. 10, 2004

23

MX29F040

TIMING WAVEFORM FOR SECTOR PROTECTION FOR SYSTEM WITH 12V

A1

A6

12V

5V

A9

tVLHT

Verify

12V

5V

OE

tVLHT

tWPP 1

WE

CE

tOESP

Data

01H

F0H

tOE

A18-A16

Sector Address

P/N:PM0538

REV. 2.3, DEC. 10, 2004

24

MX29F040

TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITH 12V

A1

12V

5V

A9

A6

tVLHT

Verify

12V

5V

OE

tVLHT

tWPP 2

WE

CE

tOESP

Data

00H

F0H

tOE

P/N:PM0538

REV. 2.3, DEC. 10, 2004

25

MX29F040

SECTOR PROTECTION ALGORITHM FOR SYSTEM WITH 12V

START

Set Up Sector Addr

(A18, A17, A16)

PLSCNT=1

OE=VID,A9=VID,CE=VIL

A6=VIL

Activate WE Pulse

Time Out 10us

Set WE=VIH, CE=OE=VIL

A9 should remain VID

.

Read from Sector

No

Addr=SA, A1=1

No

Data=01H?

PLSCNT=32?

Yes

Device Failed

Yes

Protect Another

Sector?

Remove VID from A9

Write Reset Command

Sector Protection

Complete

P/N:PM0538

REV. 2.3, DEC. 10, 2004

26

MX29F040

CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITH 12V

START

Protect All Sectors

PLSCNT=1

Set OE=A9=VID

CE=VIL,A6=1

Activate WE Pulse

Time Out 12ms

Increment

PLSCNT

Set OE=CE=VIL

A9=VID,A1=1

Set Up First Sector Addr

Read Data from Device

No

Data=00H?

Increment

PLSCNT=1000?

Sector Addr

Yes

Device Failed

No

All sectors have

been verified?

Yes

Remove VID from A9

Write Reset Command

Chip Unprotect

Complete

* It is recommended before unprotect whole chip, all sectors should be protected in advance.

P/N:PM0538

REV. 2.3, DEC. 10, 2004

27

MX29F040

TIMING WAVEFORM FOR SECTOR PROTECTION FOR SYSTEM WITHOUT 12V

A1

A6

Toggle bit polling

Verify

5V

OE

tCEP

WE

* See the following Note!

CE

Don't care

(Note 2)

Data

01H

F0H

tOE

A18-A16

Sector Address

Note1: Must issue "unlock for sector protect/unprotect" command before sector protection

for a system without 12V provided.

Note2: Except F0H

P/N:PM0538

REV. 2.3, DEC. 10, 2004

28

MX29F040

TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITHOUT 12V

A1

A6

Toggle bit polling

Verify

5V

OE

tCEP

WE

* See the following Note!

CE

Don't care

(Note 2)

Data

F0H

00H

tOE

Note1: Must issue "unlock for sector protect/unprotect" command before sector unprotection

for a system without 12V provided.

Note2: Except F0H

P/N:PM0538

REV. 2.3, DEC. 10, 2004

29

MX29F040

SECTOR PROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V

START

PLSCNT=1

Write "unlock for sector protect/unprotect"

Command(Table1)

Set Up Sector Addr

(A18, A17, A16)

OE=VIH,A9=VIH

CE=VIL,A6=VIL

Activate WE Pulse to start

Data don't care

Toggle bit checking

Q6 not Toggled

No

.

Yes

Increment PLSCNT

Set CE=OE=VIL

A9=VIH

Read from Sector

Addr=SA, A1=1

No

Data=01H?

PLSCNT=32?

Yes

Device Failed

Yes

Protect Another

Sector?

Write Reset Command

Sector Protection

Complete

P/N:PM0538

REV. 2.3, DEC. 10, 2004

30

MX29F040

CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V

START

Protect All Sectors

PLSCNT=1

Write "unlock for sector protect/unprotect"

Command (Table 1)

Set OE=A9=VIH

CE=VIL,A6=1

Activate WE Pulse to start

Data do'nt care

No

Toggle bit checking

Q6 not Toggled

Increment

PLSCNT

Yes

Set OE=CE=VIL

A9=VIH,A1=1

Set Up First Sector Addr

Read Data from Device

No

Data=00H?

Increment

PLSCNT=1000?

Sector Addr

Yes

Device Failed

No

All sectors have

been verified?

Yes

Write Reset Command

Chip Unprotect

Complete

* It is recommended before unprotect whole chip, all sectors should be protected in advance.

P/N:PM0538

REV. 2.3, DEC. 10, 2004

31

MX29F040

ID CODE READ TIMING WAVEFORM

VCC

5V

VID

ADD

A9

VIH

VIL

VIH

VIL

ADD

A0

tACC

VIH

VIL

A1

ADD

A2-A8

VIH

A10-A18 VIL

CE

VIH

VIL

VIH

VIL

tCE

WE

OE

tOE

VIH

VIL

tDF

tOH

VIH

VIL

DATA

Q0-Q7

DATA OUT

C2H

DATA OUT

A4H

P/N:PM0538

REV. 2.3, DEC. 10, 2004

32

MX29F040

ERASE AND PROGRAMMING PERFORMANCE (1)

LIMITS

TYP.(2)

PARAMETER

MIN.

MAX.(3)

10.4

32

UNITS

sec

Sector Erase Time

Chip Erase Time

1.3

4

sec

Byte Programming Time

Chip Programming Time

Erase/Program Cycles

7

210

us

4

12

sec

100,000

Cycles

Note: 1.Not 100% Tested, Excludes external system level over head.

2.Typical values measured at 25°C,5V.

3.Maximunm values measured at 25° C,4.5V.

LATCH-UP CHARACTERISTICS

MIN.

-1.0V

MAX.

Input Voltage with respect to GND on all pins except I/O pins

Input Voltage with respect to GND on all I/O pins

Current

13.5V

Vcc + 1.0V

+100mA

-1.0V

-100mA

Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.

DATA RETENTION

PARAMETER

MIN.

UNIT

Data Retention Time

20

Years

P/N:PM0538

REV. 2.3, DEC. 10, 2004

33

MX29F040

ORDERING INFORMATION

PLASTIC PACKAGE

PART NO.

AccessTime Operating Current Standby Current Temperature PACKAGE

Remark

(ns)

MAX.(mA)

MAX.(uA)

Range

MX29F040QC-55

MX29F040QC-70

MX29F040QC-90

MX29F040QC-12

MX29F040TC-55

55

70

30

5

0^oC~70^oC

32 Pin PLCC

32 Pin TSOP

(Normal Type)

32 Pin TSOP

(Normal Type)

32 Pin TSOP

(Normal Type)

32 Pin TSOP

(Normal Type)

32 Pin PDIP

90

120

55

MX29F040TC-70

MX29F040TC-90

MX29F040TC-12

70

90

30

5

0^oC~70^oC

120

MX29F040PC-55

MX29F040PC-70

MX29F040PC-90

MX29F040PC-12

MX29F040QC-55G

MX29F040QC-70G

MX29F040QC-90G

MX29F040TC-55G

MX29F040TC-70G

MX29F040TC-90G

MX29F040TC-12G

MX29F040PC-55G

MX29F040PC-70G

MX29F040PC-90G

MX29F040QI-55

MX29F040QI-70

MX29F040QI-90

55

70

90

120

55

70

90

55

70

90

120

55

70

90

55

70

90

30

5

0^oC~70^oC

32 pin PLCC PB free

32 pin TSOP PB free

32 pin PDIP PB free

-40^oC~85^oC 32 Pin PLCC

P/N:PM0538

REV. 2.3, DEC. 10, 2004

34

MX29F040

PART NO.

AccessTime Operating Current Standby Current Temperature PACKAGE

Remark

(ns)

MAX.(mA)

MAX.(uA)

Range

MX29F040TI-55

MX29F040TI-70

MX29F040TI-90

55

30

5

-40^oC~85^oC 32 Pin TSOP

(Normal Type)

70

90

30

5

-40^oC~85^oC 32 Pin TSOP

(Normal Type)

-40^oC~85^oC 32 Pin TSOP

(Normal Type)

MX29F040PI-55

MX29F040PI-70

MX29F040PI-90

MX29F040QI-55G

MX29F040QI-70G

MX29F040QI-90G

MX29F040TI-55G

55

70

90

55

70

90

55

30

5

-40^oC~85^oC 32 Pin PDIP

-40^oC~85^oC 32 Pin PLCC PB free

-40^oC~85^oC 32 Pin TSOP PB free

(Normal Type)

MX29F040TI-70G

MX29F040TI-90G

70

90

30

5

-40^oC~85^oC 32 Pin TSOP PB free

(Normal Type)

-40^oC~85^oC 32 Pin TSOP PB free

(Normal Type)

MX29F040PI-55G

MX29F040PI-70G

MX29F040PI-90G

55

70

90

30

5

-40^oC~85^oC 32 Pin PDIP PB free

P/N:PM0538

REV. 2.3, DEC. 10, 2004

35

MX29F040

PACKAGE INFORMATION

P/N:PM0538

REV. 2.3, DEC. 10, 2004

36

MX29F040

P/N:PM0538

REV. 2.3, DEC. 10, 2004

37

MX29F040

P/N:PM0538

REV. 2.3, DEC. 10, 2004

38

MX29F040

REVISION HISTORY

Revision Description

Page

Date

1.0

To remove "Advanced Information" datasheet marking and

P1

JUL/01/1999

contain information on products in full production.

To improve ICC1:from 40mA @5MHz to 30mA @5MHz

To add the description for 100K endurance cycle

To modify timing of sector address loading period while

operating multi-sector erase from 80us to 30us

To modify tBAL from 80us to 100us

1.1

1.2

P1,13,14,33

P1,34

P8

JUL/12/1999

OCT/04/1999

P15

1.3

1.Program/erase cycle times:10K cycles-->100K cycles

2.To remove A9 from "timing waveform for sector protection for

system without 12V"

P1,34

P28

DEC/17/1999

To remove A9 from "timing waveform for chip unprotection for

system without 12V"

P29

3.To add data retention minimum 20 years

Add erase suspend ready max. 100us in ERASE SUSPEND's

section at page 9

P1,34

P9

1.4

MAY/29/2000

1.5

1.6

1.7

1.8

To modify "Package Information"

To add "Ambient temperature with power applied"

1.To corrected typing error

1. Changed flow chart of chip unprotection algorithm for system

with and without 12V

P35~37

P14

All

JUN/12/2001

AUG/08/2001

JUL/01/2002

SEP/04/2002

P27,31

1.9

2.0

To modify Package Information

1. Add 32 pin TSOP PB free package

P35~37

P34

NOV/21/2002

JAN/17/2003

2.To modify 32-PDIP & 32-PLCC package information

1. Add industrial grade option

1.Added Pb-free option

P35,36

P13~15, P34

P34

2.1

2.2

2.3

AUG/20/2004

NOV/08/2004

DEC/10/2004

1.Added industrial-grade PB free option

P35

P/N:PM0538

REV. 2.3, DEC. 10, 2004

39

MX29F040

MACRONIX INTERNATIONALCO., LTD.

Headquarters:

TEL:+886-3-578-6688

FAX:+886-3-563-2888

Europe Office :

TEL:+32-2-456-8020

FAX:+32-2-456-8021

Hong Kong Office :

TEL:+86-755-834-335-79

FAX:+86-755-834-380-78

Japan Office :

Kawasaki Office :

TEL:+81-44-246-9100

FAX:+81-44-246-9105

Osaka Office :

TEL:+81-6-4807-5460

FAX:+81-6-4807-5461

Singapore Office :

TEL:+65-6346-5505

FAX:+65-6348-8096

Taipei Office :

TEL:+886-2-2509-3300

FAX:+886-2-2509-2200

MACRONIX AMERICA, INC.

TEL:+1-408-262-8887

FAX:+1-408-262-8810

http : //www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.


型号：	29F040-12
厂家：	MACRONIX INTERNATIONAL
描述：	4M-BIT [512KX8] CMOS EQUAL SECTOR FLASH MEMORY 4M- BIT [ 512KX8 ] CMOS EQUAL部门FLASH MEMORY
文件：	总40页 (文件大小：592K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

29F040-12 [Macronix]

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