MX10EXAQI [Macronix]
Microcontroller, 16-Bit, FLASH, 8051 CPU, 30MHz, CMOS, PQCC44, PLASTIC, LCC-44;
| 型号： | MX10EXAQI |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | Microcontroller, 16-Bit, FLASH, 8051 CPU, 30MHz, CMOS, PQCC44, PLASTIC, LCC-44 时钟 微控制器 外围集成电路 |
| 文件： | 总55页 (文件大小：474K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MX10EXA
Major Difference
Feature
Product
FLASH
RAM
BIT
Package
(K BYTES)
(BYTES)
(CPU BUS)
MX10EXAQC
MX10EXAUC
MX10EXAQCG
MX10EXAUCG
44 PLCC
40 LQFP
64 K
2048
16
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REV. 1.0, JUL. 01, 2005
1
MX10EXA
XA16-bitMicrocontrollerFamily
64KFlash/2KRAM,Watchdog,2UARTs
FEATURE
•Watchdogtimer
• 4.5V to 5.5V
• Two enhanced UARTs with independent baud rates
• Seven software interrupts
• 64K bytes of on-chip Flash program memory with In-
System Programming capability
• Four 8-bit I/O ports, with 4 programmable output
configurations for each pin
• Five Flash blocks = two 8k byte blocks and three 16k
byte blocks
• 30 MHz operating frequency at 5V
• Single supply voltage In-System Programming of the
Flash memory, (VPP=VDD or VPP=12V if desired)
• Boot ROM contains low level Flash programming
routines for In-Application Programming and a default
serial loader using the UART
• 2048 bytes of on-chip data RAM
•Supportsoff-chipprogramanddataaddressingupto1
megabyte (20 address lines)
• Power saving operating modes: Idle and Power-
Down.Wake-Upfrompower-downviaanexternalinter-
rupt is supported.
•44-pinPLCC(MX10EXAQC)Commercialgrade
•44-pinLQFP(MX10EXAUC)Commercialgrade
•44-pinPLCC(MX10EXAQI)Industrialgrade
•44-pinLQFP(MX10EXAUI)Industrialgrade
•Threestandardcounter/timerswithenhancedfeatures
All timers have a toggle output capability
GENERAL DESCRIPTION
A default serial loader program in the Boot ROM allows
In-System Programming (ISP) of the Flash memory with-
out the need for a loader in the Flash code. User pro-
grams may erase and reprogram the Flash memory at
will through the use of standard routines contained in
the Boot ROM (In-Application Programming).
The MX10EXA is a member of Philips’ 80C51 XA
(eXtended Architecture) family of high performance 16-
bit single-chip microcontrollers.
The MX10EXA contains 64k bytes of Flash program
memory, and provides three general purpose timers/
counters, a watchdog timer, dual UARTs, and four gen-
eral purpose I/O ports with programmable output con-
figurations.
1
PIN CONFIGURATIONS
44 PLCC
44 LQFP
6
1
44
40
39
44
34
33
P0.4/A8D4
P0.5/A9D5
P0.6/A10D6
P0.7/A11D7
EA/VPP/WAIT
NC
P0.4/A8D4
P0.5/A9D5
P0.6/A10D6
P0.7/A11D7
EA/VPP/WAIT
NC
P1.5/TxD1
P1.6/T2
7
P1.5/TxD1
P1.6/T2
1
P1.7/T2EX
RST
P1.7/T2EX
RST
P3.0/RxD0
NC
P3.0/RxD0
NC
12
34
MX10EXAQC
MX10EXAUC
ALE
ALE
P3.1/TxD0
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.1/TxD0
P3.2/INT0
P3.3/INT1
P3.4/T0
PSEN
PSEN
P2.7/A19D15
P2.6/A18D14
P2.5/A17D13
P2.7/A19D15
P2.6/A18D14
P2.5/A17D13
P3.5/T1/BUSW
17
29
28
P3.5/T1/BUSW
11
12
23
22
18
23
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2
MX10EXA
BLOCK DIAGRAM
XA CPU Core
SFR
Bus
Program
Memory Bus
64K Bytes
FLASH
UART0
Data
Bus
2048 Bytes
Static RAM
UART1
Port 0
Timer 0,1
Port 1
Port 2
Port 3
Timer 2
Watchdog
Timer
LOGIC SYMBOL
VDD VSS
XTAL1
XTAL2
T2EX*
T2*
TxD1
RxD1
A3
A2
A1
A0/WRH
RST
EA/WAIT
PSEN
ALE
RxD0
TxD0
INT0
INT1
T0
T1/BUSW
WRL
RD
* NOT AVAILABLE ON 40-PIN DIP PACKAGE
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3
MX10EXA
PIN DESCRIPTIONS
MNEMONIC
PIN. NO.
TYPE NAMEAND FUNCTION
PLCC
1, 22
23, 44
LQFP
16,39
17,38
V SS
V DD
I
I
Ground: 0V reference.
Power Supply: This is the power supply voltage for normal, idle, and
power down operation.
P0.0-P0.7
43-36
37-30
I/O
Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type.
Port 0 latches have 1s written to them and are configured in the quasi-
bidirectional mode during reset. The operation of port 0 pins as inputs
and outputs depends upon the port configuration selected. Each port
pin is configured independently. Refer to the section on I/O port con-
figuration and the DC Electrical Characteristics for details.
When the external program/data bus is used, Port 0 becomes the mul-
tiplexed low data/instruction byte and address lines 4 through 11.
Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type.
Port 1 latches have 1s written to them and are configured in the quasi-
bidirectional mode during reset. The operation of port 1 pins as inputs
and outputs depends upon the port configuration selected. Each port
pin is configured independently. Refer to the section on I/O port con-
figuration and the DC Electrical Characteristics for details.
Port 1 also provides special functions as described below.
A0/WRH: Address bit 0 of the external address bus when the external
data bus is configured for an 8 bit width. When the external data bus is
configured for a 16 bit width, this pin becomes the high byte write
strobe.
P1.0-P1.7
2-9
40-44,
1-3
I/O
2
40
O
3
4
5
6
7
8
9
41
42
43
44
1
O
O
O
I
O
I/O
I
A1: Address bit 1 of the external address bus.
A2: Address bit 2 of the external address bus.
A3: Address bit 3 of the external address bus.
RxD1 (P1.4): Receiver input for serial port 1.
TxD1 (P1.5): Transmitter output for serial port 1.
2
3
T2 (P1.6): Timer/counter 2 external count input/clockout.
T2EX (P1.7): Timer/counter 2 reload/capture/direction control
Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type.
Port 2 latches have 1s written to them and are configured in the quasi-
bidirectional mode during reset. The operation of port 2 pins as inputs
and outputs depends upon the port configuration selected. Each port
pin is configured independently. Refer to the section on I/O port con-
figuration and the DC Electrical Characteristics for details.
When the external program/data bus is used in 16-bit mode, Port 2
becomes the multiplexed high data/instruction byte and address lines
12 through 19. When the external program/data bus is used in 8-bit
mode, the number of address lines that appear on port 2 is user pro-
grammable.
P2.0-P2.7
24-31
18-25
I/O
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4
MX10EXA
MNEMONIC
PIN. NO.
PLCC LQFP
11,13-19 5,7-13
TYPE NAMEAND FUNCTION
P3.0-P3.7
I/O
Port 3: Port 3 is an 8-bit I/O port with a user configurable output type.
Port 3 latches have 1s written to them and are configured in the quasi-
bidirectional mode during reset. the operation of port 3 pins as inputs
and outputs depends upon the port configuration selected. Each port
pin is configured independently. Refer to the section on I/O port con-
figuration and the DC Electrical Characteristics for details.
Port 3 also provides various special functions as described below.
RxD0 (P3.0): Receiver input for serial port 0.
TxD0 (P3.1): Transmitter output for serial port 0.
INT0 (P3.2): External interrupt 0 input.
INT1 (P3.3): External interrupt 1 input.
T0 (P3.4): Timer 0 external input, or timer 0 overflow output.
T1/BUSW (P3.5): Timer 1 external input, or timer 1 overflow output.
The value on this pin is latched as the external reset input is released
and defines the default external data bus width (BUSW). 0 = 8-bit bus
and 1 = 16-bit bus.
11
13
14
15
16
17
5
7
8
9
10
11
I
O
I
I
I/O
I/O
18
19
10
12
13
4
O
O
I
WRL (P3.6): External data memory low byte write strobe.
RD (P3.7): External data memory read strobe.
Reset: A low on this pin resets the microcontroller, causing I/O ports
and peripherals to take on their default states, and the processor to
begin execution at the address contained in the reset vector. Refer to
the section on Reset for details.
RST
ALE
33
32
35
27
26
29
I/O
O
I
Address Latch Enable: A high output on the ALE pin signals external
circuitry to latch the address portion of the multiplexed address/data
bus. A pulse on ALE occurs only when it is needed in order to process
a bus cycle.
Program Store Enable: The read strobe for external program memory.
When the microcontroller accesses external program memory, PSEN
is driven low in order to enable memory devices. PSEN is only active
when external code accesses are performed.
External Access/Wait/Programming Supply Voltage: The EAinput
determines whether the internal program memory of the microcontroller
is used for code execution. The value on the EA pin is latched as the
external reset input is released and applies during later execution. When
latched as a 0, external program memory is used exclusively, when
latched as a 1, internal program memory will be used up to its limit, and
external program memory used above that point. After reset is released,
this pin takes on the function of bus Wait input. If Wait is asserted high
during any external bus access, that cycle will be extended until Wait
is released. During EPROM programming, this pin is also the program-
ming supply voltage input.
PSEN
EA/WAIT
/VPP
XTAL1
XTAL2
21
20
15
14
I
Crystal 1: Input to the inverting amplifier used in the oscillator circuit
and input to the internal clock generator circuits.
Crystal 2: Output from the oscillator amplifier.
O
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5
MX10EXA
SPECIAL FUNCTION REGISTERS
NAME
DESCRIPTION
SFR
BIT FUNCTIONS AND ADDRESSES
Reset
ADDRESS MSB
LSB VALUE
AUXR
BCR
BTRH
BTRL
CS
Auxiliary function register
Bus configuration register
44C
46A
ENBOOT FMIDLE PWR_VLD ---
---
---
---
---
---
---
---
WAITD BUSD BC2 BC1 BC0 Note 1
Bus timing register high byte 469
Bus timing register low byte 468
DW1
DW0 DWA1 DWA0 DR1 DR0 DRA1 DRA0 FF
WM1 WM0 ALEW — ---
CR1 CR0 CRA1 CRA0 EF
Code segment
Data segment
Extra segment
443
441
442
00
00
00
DS
ES
33F
---
33E
---
33D
---
33C
---
33B
33A
339
338
IEH*
Interrupt enable high byte
427
ETI1 ERI1 ETI0 ERI0 00
337
EA
---
336
---
335
---
334
ET2
333
ET1
---
332
EX1
331
330
EX0
IEL*
IPA0
IPA1
IPA2
IPA4
IPA5
Interrupt enable low byte
Interrupt priority 0
Interrupt priority 1
Interrupt priority 2
Interrupt priority 4
Interrupt priority 5
426
4A0
4A1
4A2
4A4
4A5
ET0
PX0
PX1
PT2
PRI0
PRI1
381
00
00
00
00
00
00
PT0
PT1
---
---
---
---
---
---
PTI0
PTI1
385
---
---
---
387
AD7
38F
386
384
AD4
38C
383
382
380
P0*
P1*
P2*
P3*
Port 0
Port 1
Port 2
Port 3
430
431
432
433
AD6 AD5
38E 38D
AD3 AD2 AD1 AD0 FF
38B
38A
A2
389
A1
388
T2EX T2
TxD1 RxD1 A3
WRH FF
390
397
P2.7
39F
RD
396
395
394
P2.4
39C
T0
393
392
391
P2.6 P2.5
P2.3 P2.2 P2.1 P2.0 FF
39B 39A 399 398
INT1 INT0 TxD0 RxD0 FF
39E
WR
39D
T1
P0CFGA Port 0 configuration A
P1CFGA Port 1 configuration A
P2CFGA Port 2 configuration A
P3CFGA Port 3 configuration A
P0CFGB Port 0 configuration B
P1CFGB Port 1 configuration B
P2CFGB Port 2 configuration B
P3CFGB Port 3 configuration B
470
471
472
473
4F0
4F1
4F2
4F3
Note 5
Note 5
Note 5
Note 5
Note 5
Note 5
Note 5
Note 5
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6
MX10EXA
NAME
DESCRIPTION
SFR
BIT FUNCTIONS AND ADDRESSES
Reset
address MSB
LSB VALUE
227
226
---
225
---
224
---
223
---
222
---
221
PD
220
IDL
208
PCON* Power control register
404
401
---
00
20F
SM
20E
TM
20D
RS1
20C
RS0
20B
IM3
20A
IM2
209
PSWH* Program status word
(high byte)
IM1 I M0
Note 2
207
C
206
AC
205
---
204
---
203
---
202
V
201
N
200
Z
PSWL* Program status word
(low byte)
400
Note 2
217
C
216
AC
215
F0
214
213
212
V
211
F1
210
P
PSW51* 80C51 compatible PSW
402
455
RS1
RS0
Note 3
00
RTH0
RTH1
RTL0
RTL1
Timer 0 extended reload,
high byte
Timer 1 extended reload,
high byte
457
454
456
00
00
00
Timer 0 extended reload,
low byte
Timer 1 extended reload,
low byte
307
306
305
304
303
302
301
300
S0CON* Serial port 0 control register 420
S0STAT* Serial port 0 extended status 421
SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 00
30F
---
30E
---
30D
---
30C
---
30B
FE0
30A
309
308
BR0 OE0
STINT0 00
x
S0BUF Serial port 0 buffer register
460
S0ADDR Serial port 0 address register 461
S0ADEN Serial port 0 address enable 462
register
0
00
327
326
325
324
323
322
321
320
S1CON* Serial port 1 control register 424
S1STAT* Serial port 1 extended status 425
SM0_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1
RI_1 00
328
32F
---
32E
---
32D
---
32C
---
32B
FE1
32A
329
BR1 OE1
STINT1 00
x
S1BUF Serial port 1 buffer register
464
S1ADDR Serial port 1 address register 465
S1ADEN Serial port 1 address enabler 466
register
00
00
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MX10EXA
NAME
DESCRIPTION
SFR
BIT FUNCTIONS AND ADDRESSES
Reset
address MSB
LSB VALUE
SCR
System configuration register 440
---
---
---
---
PT1
21B
PT0
21A
CM
PZ
00
21F
21E
21D
21C
219
218
SSEL*
SWE
Segment selection register 403
ESWEN R6SEG R5SEG R4SEG R3SEG R2SEG R1SEG R0SEG 00
Software Interrupt Enable
47A
---
SWE7 SWE6 SWE5 SWE4 SWE3 SWE2 SWE1 00
356 355 354 353 352 351 350
SWR7 SWR6 SWR5 SWR4 SWR3 SWR2 SWR1 00
2C6 2C5 2C4 2C3 2C2 2C1 2C0
EXF2 RCLK0 TCLK0 EXEN2 TR2 C/T2 CP/RL2 00
2CE 2CD 2CC 2CB 2CA 2C9
RCLK1 TCLK1 ---
357
---
SWR*
Software Interrupt Request 42A
2C7
TF2
2CF
---
T2CON* Timer 2 control register
418
2C8
T2MOD* Timer 2 mode control
419
459
458
45B
---
---
T2OE DCEN 00
TH2
TL2
Timer 2 high byte
Timer 2 low byte
00
00
00
T2CAPH Timer 2 capture register,
high byte
T2CAPL Timer 2 capture register,
low byte
45A
00
287
TF1
286
TR1
285
TF0
284
TR0
283
IE1
282
IT1
281
IE0
280
IT0
TCON*
TH0
Timer 0 and 1 control register410
00
00
00
00
00
00
Timer 0 high byte
Timer 1 high byte
Timer 0 low byte
Timer 1 low byte
451
453
450
452
TH1
TL0
TL1
TMOD
Timer 0 and 1 mode control 45C
GATE C/T
M1
M0
GATE C/T
M1
M0
28F
---
28E
---
28D
---
28C
---
28B
---
28A
289
288
TSTAT* Timer 0 and 1 extended status 411
T1OE ---
T0OE 00
2F8
2FF
2FE
2FD
2FC
2FB
---
2FA
2F9
WDCON* Watchdog control register
WDL Watchdog timer reload
41F
45F
45D
45E
PRE2 PRE1 PRE0 ---
WDRUN WDTOF
---
Note 6
00
x
WFEED1 Watchdog feed 1
WFEED2 Watchdog feed 2
x
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MX10EXA
NOTES:
* SFRs are bit addressable.
1.At reset, the BCR register is loaded with the binary value 0000 0a11, where "a" is the value on the BUSW pin. This
defaults the address bus size to 20 bits, Since the MX10EXA has only 20 address lines.
2. SFR is loaded from the reset vector.
3. All bits except F1, F0, and P are loaded from the reset vector. Those bits are all 0.
4. Unimplemented bits in SFRs are X (unknown) at all times. Ones should not be written to these bits since they may
be used for other purposes in future XA derivatives. The reset value shown for these bits is 0.
5. Port configurations default to quasi-bidirectional when the XA begins execution from internal code memory after
reset, based on the condition found on the EA pin. Thus all PnCFGA registers will contain FF and PnCFGB
registers will contain 00. When the XAbegins execution using external code memory, the default configuration for
pins that are associated with the external bus will be push-pull. The PnCFGA and PnCFGB register contents will
reflect this difference.
6. The WDCON reset value is E6 for a Watchdog reset, E4 for all other reset causes.
7. The MX10EXA implements an 8-bit SFR bus. All SFR accesses must be 8-bit operations.
Attempts to write 16 bits to an SFR will actually write only the lower 8 bits. Sixteen bit SFR reads will return
undefined data in the upper byte.
8. TheAUXR reset value is typically 00h. If the Boot Loader is activated at reset because the Flash status byte is non-
zero or because the Boot Vector has been forced (by PSEN = 0, ALE = 1, EA = 1 at reset), the AUXR reset value
will be 1x00 0000b. Bit 6 will be a 1 if the on-chip VPP generator is running and ready, otherwise it will be a 0.
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MX10EXA
FFFFFh
UP TO 1M BYTES
TOTAL CODE
MEMORY
10000h
FFFFh
FFFFh
2K BYTE BOOT ROM
F800h
64K BYTEs
ON-CHIP
CODE MEMORY
0000h
Note:The Boot ROM replaces the top 2K bytes of Flash memory
when it is enable via the xxx bit in xxx.
Figure 1. XA Program Memory Map
Data Segment 0
Other Data Segments
FFFFFh
FFFFFh
DATA MEMORY
(INDIRECTLY ADDRESSED,
OFF-CHIP)
DATA MEMORY
(INDIRECTLY ADDRESSED,
OFF-CHIP)
0800h
07FFh
DATA MEMORY
(INDIRECTLY ADDRESSED,
ON CHIP)
0400H
03FFh
0400H
03FFh
2K BYTES
DATA MEMORY
DATA MEMORY
ON-CHIP DATA
MEMORY (RAM)
(DIRECTLY AND INDIRECTLY
ADDRESSABLE, ON CHIP)
(DIRECTLY AND INDIRECTLY
ADDRESSABLE, OFF-CHIP)
0040h
003Fh
0040h
003Fh
DIRECTLY
ADDRESSED DATA
BIT-ADDRESSABLE
BIT-ADDRESSABLE
DATA AREA
(1K PER SEGMENT)
DATA AREA
0020h
001Fh
0020h
001Fh
DATA MEMORY
DATA MEMORY
(DIRECTLY AND INDIRECTLY
ADDRESSABLE, ON CHIP)
0000h
(DIRECTLY AND INDIRECTLY
ADDRESSABLE, OFF-CHIP)
0000h
Figure 1. XA Data Memory Map
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MX10EXA
FLASH EPROM MEMORY
GENERAL DESCRIPTION
FEATURES
• Flash EPROM internal program memory with Block
Erase.
The XA Flash memory augments EPROM functionality
with in-circuit electrical erasure and programming. The
Flash can be read and written as bytes. The Chip Erase
operation will erase the entire program memory. The Block
Erase function can erase any single Flash block. In-cir-
cuit programming and standard parallel programming are
both available. On-chip erase and write timing genera-
tion contribute to a user friendly programming interface.
• Internal 2k byte fixed boot ROM, containing low-level
programming routines and a default loader. The Boot
ROMcanbeturnedofftoprovideaccesstothefull64k
byte Flash memory.
• Boot vector allows user provided Flash loader code to
reside anywhere in the Flash memory space. This
configuration provides flexibility to the user.
• DefaultloaderinBootROMallowsprogrammingviathe
serial port without the need for a user provided loader.
• Up to 1Mbyte external program memory if the internal
programmemoryisdisabled(EA=0).
The XA Flash reliably stores memory contents even af-
ter 10,000 erase and program cycles. The cell is designed
to optimize the erase and programming mechanisms. In
addition, the combination of advanced tunnel oxide pro-
cessing and low internal electric fields for erase and pro-
gramming operations produces reliable cycling. For In-
System Programming, the XA can use a single +5 V
power supply. Faster In-system Programming may be
obtained, if required, through the use of a+12V VPP sup-
ply. Parallel programming (using separate programming
hardware) uses a+12V VPP supply.
• Programming and erase voltage VPP = VDD or 12V
±5% for ISP, 12V 5% for parallel programming.Using
12VVPPforISPmayimproveprogramminganderase
time.
• Read/Programming/Erase:
- Byte-wise read (60 ns access time at 4.5 V).
- Byte Programming (1-2 minutes for 64 K flash,
depending on clock frequency).
• In-circuit programming via user selected method, typi-
cally RS232 or parallel I/O port interface.
• Programmable security for the code in the Flash
• 10,000 minimum erase/program cycles
• 10 year minimum data retention.
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11
MX10EXA
Flash organization
ENBOOT and PWR_VLD
The XA contains 64k bytes of Flash program memory.
This memory is organized as 5 separate blocks. The
first two blocks are 8k bytes in size, filling the program
memory space from address 0 through 3FFF hex. The
final three blocks are 16k bytes in size and occupy ad-
dresses from 4000 through FFFF hex.
Setting the ENBOOT bit in the AUXR register enables
the Boot ROM and activates the on-chip VPP generator if
VPP is connected to rather than 12V externally. The
PWR_VLD flag indicates that VPP is available for
programming and erase operations. This flag should be
checked prior to calling the Boot ROM for programming
and erase services. When ENBOOT is set, it typically
takes 5 microseconds for the internal programming
voltage to be ready.
Figure 3 depicts the Flash memory configuration.
Flash Programming and Erasure
The ENBOOT bit will automatically be set if the status
byte is non-zero during reset, or when PSENis low, ALE
is high, and EA is high at the falling edge of reset. Other-
wise, ENBOOT will be cleared during reset.
The XAFlash microcontroller supports a number of pro-
gramming possibilities for the on-chip Flash memory. The
Flash memory may be programmed in a parallel fashion
on standard programming equipment in a manner similar
to an EPROM microcontroller. The XAmicrocontroller is
able to program its own Flash memory while the applica-
tion code is running. Also, a default loader built into a
Boot ROM allows programming blank devices serially
through the UART.
When programming functions are not needed, ENBOOT
may be cleared. This enables access to the 2k bytes of
Flash code memory that is overlaid by the Boot ROM,
allowing a full 64k bytes of Flash cede memory.
FFFF
F800
FFFF
BOOT ROM
Using any of these types of programming, any of the
individual blocks may be erased separately, or the entire
chip may be erased. Programming of the Flash memory
is accomplished one byte at a time.
BLOCK 4
16K BYTES
C000
Boot ROM
BLOCK 3
16K BYTES
When the microcontroller programs its own Flash
memory, all of the low level details are handled by code
that is permanently contained in a 2k byte “Boot ROM”
that is separate from the Flash memory. Auser program
simply calls the entry point with the appropriate
parameters to accomplish the desired operation. Boot
ROM operations include things like: erase block, program
byte, verity byte, program security lock bit, etc. The Boot
ROM overlays the program memory space at the top of
the address space from F800 to FFFF hex, when it is
enabled by setting the ENBOOT bit at AUXR1.7.. The
Boot ROM may be turned off so that the upper 2k bytes
of Flash program memory are accessible for execution.
8000
4000
PROGRAM
ADDRESS
BLOCK 2
16K BYTES
BLOCK 1
8K BYTES
2000
0000
BLOCK 0
8K BYTES
Figure 3. Flash Memory Configuration
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MX10EXA
NOTE: When erasing the Status Byte or Boot Vector,
these bytes are erased at the same time. It is necessary
to reprogram the Boot Vector after erasing and updating
the Status Byte.
FMIDLE
The FMIDLE bit in theAUXR register allows saving addi-
tional power by turning off the Flash memory when the
CPU is in the Idle mode. This must be done just prior to
initiating the Idle mode, as shown below.
HardwareActivation of the Boot Vector
OR
AUXR, #$40
;Set Flash memory to idle
mode.
Program execution at the Boot Vector may also be forced
from outside of the microcontroller by setting the correct
state on a few pins. While Reset is asserted, the PSEN
pin must be pulled low, the ALE pin allowed to float high
(need not be pulled up externally), and the EA pin driven
to a logic high (or up to VPP). Then reset may be released.
This is the same effect as having a non-zero status byte.
This allows building an application that will normally ex-
ecute the end user’s code but can be manually forced
into ISP operation. The Boot ROM is enabled when use
of the Boot Vector is forced as described above, so the
branch may go to the default loader. Conversely, user
code in the top 2k bytes of the Flash memory may not
be executed when the Boot Vector is used.
OR
PCON, #$0l
;Turn on Idle mode.
;Execution resumes here when
Idle mode terminates.
.
.
When the Flash memory is put into the Idle mode by
setting FMIDLE, restarting the CPU upon exiting Idle
mode takes slightly longer, about 3 microseconds. How-
ever, the standby current consumed by the Flash memory
is reduced from about 8mA to about 1mA.
Default Loader
A default loader that accepts programming commands
in a predetermined format is contained permanently in
the Boot ROM. A factory fresh device will enter this loader
automatically if it is powered up without first being pro-
grammed by the user. Loader commands include func-
tions such as erase block; program Flash memory; read
Flash memory; and blank check.
If the factory defauolt setting for the BPC (F800h) is
changed, it will no longer point to the ISP masked-ROM
boot loader code. If this happens, the only possible way
to change the contents of the Boot Vector is through the
parallel programming method, provided that the end user
application does not contain a customized loader that
provides for erasing and reprogramming of the Boot Vec-
tor and Status Byte.
Boot Vector
The XAcontains two special FLASH registers: the BOOT
VECTOR and the STATUS BYTE.
After programming the FLASH, the status byte should
be erased to zero in order to allow execution of theuser’s
application code beginning at address 0000H.
The "Boot Vector" allows forcing the execution of a user
supplied Flash loader upon reset, under two specific sets
of conditions. At the falling edge of reset, the XA exam-
ines the contents of the Status Byte. If the Status Byte
is set to zero, power-up execution starts at location
0000H, which is the normal start address of the user’s
application code.
When the Status Byte is set to a value other than zero,
the Boot Vector is used as the reset vector (4 bytes),
including the Boot Program Counter (BPC) and the Boot
PSW (BPSW). The factory default settings are 8000h for
the BPSW and F800h for the BPC, which corresponds
to the address F900h for the factory masked-ROM ISP
boot loader. The Status Byte is automatically set to a
non-zero value when a programming error occurs. A cus-
tom boot loader can be written with the Boot Vector set
to the custom boot loader.
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MX10EXA
VCC
FOR USE WITH WINISP
+12V±5% or VDD SUPPLY
5V ±5%
VPP
RST
VDD
VxD
RxD
2
3
TxD
RxD
VSS
XTAL2
RS - 232
TRANSCEIVER
MC145406, MAX232,
OR EQUIVALENT
5
XTAL1
VSS
FEMALE
DB - 9
Figure 4. In-System Programming with a Minimum of Pins
In-System Programming (ISP)
In-System Programming (ISP) is performed without re-
moving the microcontroller from the system. The In-Sys-
tem Programming (ISP) facility consists of a series of
internal hardware resources coupled with internal firm-
ware to facilitate remote programming of the XA through
the serial port.
The ISP feature allows for a wide range of baud rates to
be used in the application, independent of the oscillator
frequency. It is also adaptable to a wide range of oscilla-
tor frequencies. This is accomplished by measuring the
bit-time of a single bit in a received character. This infor-
mation is then used to program the baud rate in terms of
timer counts based on the oscillator frequency. The ISP
feature requires that an initial character (a lowercase f)
be sent to the XA to establish the baud rate. The ISP
firmware provides auto-echo of received characters.
The In-System Programming (ISP) facility has made in-
circuit programming in an embedded application possible
with a minimum of additional expense in components
and circuit board area.
Once baud rate initialization has been performed, the
ISP firmware will only accept specific Intel Hex-type
records. Intel Hex records consist of ASCII characters
used to represent hexadecimal values and are summa-
rized below:
The ISP function uses five pins: TxD, RxD, VSS, and VPP
(see Figure 4). Only a small connector needs to be avail-
able to interface your application to an external circuit in
order to use this feature. The VPP supply should be ad-
equately decoupled and VPP not allowed to exceed data
sheet limits.
:NNAAAARRDD..DDCC<crlf>
In the Intel Hex record, the “NN” represents the number
of data bytes in the record. The XA will accept up to 16
(10H) data bytes. The "AAAA"” string represents the ad-
dress of the first byte in the record. If there are zero
bytes in the record, this field is often set to 0000. The
"RR" string indicates the record type. A record type of
"00" is a data record. A record type of "01" indicates the
Using In-System Programming (ISP)
ISP mode is entered by holding PSEN low, asserting,
un-asserting RESET, then releasing PSEN. When ISP
mode is entered, the default loader first disables the
watchdog timer to prevent a watchdog reset from occur-
ring during programming.
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MX10EXA
end-of-file mark. In this application, additional record types
will be added to indicate either commands or data for the
ISP facility. The maximum number of data bytes in a
record is limited to 16 (decimal). ISP commands are sum-
marized in Table 1.
The actual loader code would typically be programmed
by the user into the microcontroller in a parallel fashion
or via the default loader during their manufacturing pro-
cess. The entire initial Flash contents may be programmed
at that time, or the rest of the application may be pro-
grammed into the Flash memory at a later time, possibly
using the loader code to do the programming.
As a record is received by the XA, the information in the
record is stored internally and a checksum calculation is
performed. The operation indicated by the record type is
not performed until the entire record has been received.
Should an error occur in the checksum, the XA will send
an "X" out the serial port indicating a checksum error. If
the checksum calculation is found to match the
checksum in the record, then the command will be ex-
ecuted. In most cases, successful reception of the record
will be indicated by transmitting a "." character out the
serial port (displaying the contents of the internal pro-
gram memory is an exception).
This application controlled programming capability allows
for the possibility of changing the application code in the
field. If the application circuit is embedded in a PC, or
has a way to establish a telephone data link to a user’s
or manufacturer’s computer, new code could be down-
loaded from diskette or a manufacturer’s support sys-
tem. There is even the possibility of conducting very
specialized remote testing of a failing circuit board by
the manufacturer by remotely programming a series of
detailed test programs into the application board and
checking the results.
In the case of a Data Record (record type 00), an addi-
tional check is made. A "." character will NOT be sent
unless the record checksum matched the calculated
checksum and all of the bytes in the record were suc-
cessfully programmed. For a data record, an "X" indi-
cates that the checksum failed to match, and an "R"
character indicates that one of the bytes did not prop-
erty program.
Any user supplied loader should take the watchdog timer
into account. Typically, the watchdog timer would be dis-
abled upon entry to the loader if it might be running, in
order to prevent a watchdog reset from occurring during
programming.
The ISP facility was designed so that specific crystal
frequencies were not required in order to generate baud
rates or time the programming pulses.
User Supplied Loader
A user program can simply decide at any time, for any
reason, to begin Flash programming operations. All it has
to do in advance is to instruct external circuitry to apply
+5V or +12V to the VPP pin, and make certain that the
Boot ROM is enabled. User code may contain a loader
designed to replace the application code contained in
the Flash memory by loading new code through any com-
munication medium available in the application. This is
completely flexible and defined by the designer of the
system. It could be done serially using RS-232, serially
using some other method, or even parallel over a user
defined I/O port. The user has the freedom to choose a
method that does not interfere with the application cir-
cuit. As an added feature, the application program may
also use the Flash memory as a long term data storage,
saving configuration information, sensor readings, or any
other desired data.
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MX10EXA
Table 1. Intel-Hex Records Used by In-System Programming
RECORDTYPE
00 or 80
COMMANDIDATAFUNCTION
Data Record
:nnaaaa00dd....ddcc
Where:
Nn
= number of bytes (hex) in record
Aaaa = memory address of first byte in record
dd....dd= data bytes
cc
= checksum
Example:10008000AF5F67F0602703E0322CFA92007780C3FD
0l or 81
End of File (EOF), no operation
:xxxxxx0lcc
Where:
xxxxxx = required field, but value is a "don't care”
cc
= checksum
Example:00000001FF
Miscellaneous Write Functions
:nnxxxx83 ffssddcc
Where:
83
nn
= number of bytes (hex) in record
xxxx = required field, but value is a "don't care”
83
ff
ss
dd
cc
= Write Function
= subfunction code
= selection code
= data input (as needed)
= checksum
Subfunction Code = 0l (Erase Blocks)
ff
= 0l
ss
= block number in bits 7:5, Bits 4:0 = zeros
block 0 : = 00h
block 1 : ss = 20h
block 2 : ss = 40h
block 3 : ss = 80h
block 4 : ss = C0h
Example:0200008301203C erase block 1
Subfunction Code =04 (Erase Boot Vector and Status Byte)
ff = 04
as = don't care
dd = don't care
Example:010000830478 erase boot vector and status byte
Subtunction Code = 05 (Program Security Bits)
ff = 05
ss = 00 program security bit 1 (inhibit writing to FLASH)
01 program security bit 2 (inhibit FLASH verify)
02 program security bit 3 (disable external memory)
Example:02000083050175 program security bit 2
Subtunction Code = 06 (Program Status Byte or Boot Vector)
ff = 06
ss = 00 program status byte
01 program boot vector
Note : only two bits of these special cells may be programmed at one time.
Example:020000830601FC78 program boot vector to FC00h
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MX10EXA
RECORDTYPE
84
COMMANDIDATAFUNCTION
Display Device Data or Blank Check - Record type 84 causes the contents of the entire
FLASH array to be sent out the serial port in a formatted display. This display consists of an
address and the contents of 16 bytes starting with that address. No display of the device
contents will occur it security bit 2 has been programmed. The dumping of the device data to
the serial port is terminated by the reception of any character.
General Format of Function 84 :05xxxx84sssseeeeffcc
Where:
05
xxxx = required field, but value is a "don't care”
84 = "Display Device Data or blank Check" function code
= number of bytes (hex) in record
ssss = starting address
eeee = ending address
ff
= subfunction
00 = display data
01 = blank check
= checksum
cc
Example:0500008440004FFF00E9 display 4000-4FFF
Miscellaneous Read Functions
85
General Format of Function 85 :02xxxx85ffsscc
Where:
02
= number of bytes (hex) in record
xxxx = required field, but value is a "don't care”
85
= "Miscellaneous Read" function code
ffss
= subfunction and selection code
0000 = read signature byte - manufacturer id(15H)
0001 = read signature byte - device id # 1(EAH)
0002 = read signature byte - device id # 2(XA= 54H))
0700 = read security bits (returned value bits 3:1 = sb3,sb2,sbl)
0701 = read status byte
0702 = read boot vector
cc
= checksum
Example:02000085000178 read signature byte - device id # 1
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MX10EXA
In-Application Programming Method
Several Application Program Interface (API) calls are available for use by an application program to permit selective
erasing and programming of FLASH sectors. All calls are made through a common interface, PGM_MTP. The pro-
gramming functions are selected by setting up the microcontroller's registers before making a call to PGM_MTP at
FFFOH. Results are returned in the registers. TheAPI calls are shown in Table 2.
Table 2. API calls
API CALL
PROGRAMDATABYTE Input Parameters:
R0H = 02h or 92h
R6 = address of byte to program
R4L = byte to program
Return Parameter
R4L = 00 if pass, non-zero if fail
Input Parameters:
PARAMETER
ERASE BLOCK
R0H = 01h or 93h
R6H = block number in bits 7:5, bits 4:0 = "0"
block 0 : R6H = 00h
block 1 : R6H = 20h
block 2 : R6H = 40h
block 3 : R6H = 80h
block 4 : R6H = C0h
REL = 00h
Return Parameter
R4L = 00 if pass, non-zero if fail
Input Parameters:
ERASE BPC and
STATUS BYTE
ROH =04h
Return Parameter
R4L =00 if pass, non-zero if fail
PROGRAM SECURITY
BIT
Input Parameters:
R0H = 05h
R6H = 00h
R6L = 00h - security bit # 1 (inhibit writing to FLASH)
0lh - security bit # 2 (inhibit FLASH verify)
02h - security bit # 3 (disable external memory)
Return Parameter:none
PROGRAM STATUS
BYTE
Input Parameters:
R0H = 60h
R6H = 00h
R6L = 00H- program status byte
R4L = status byte
Return Parameter
R4L = 00 if pass, non-zero if fail
Note : only two bits of status byte may be programmed at one time
PROGRAM BPC HIGH
BYTE
Input Parameters:
R0H = 06h
R6H = 00h
R6L = 0lh - program BPC
R4L = BPC[15:8] (BPC[7:0] unchanged)
Return Parameter
R4L = 00 if pass, non-zero if fail
Note : only two bits of BPC [15:8] may be programmed at one time
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MX10EXA
API CALL
READDEVICEDATA
PARAMETER
Input Parameters:
R0H = 03h
R6
= address of byte to read
Return Parameter
R4L = value of byte read
READMANUFACTURER Input Parameters:
ID
R0H = 00h
R6H = 00h
R6L = 00h (manufacturer ID)
Return Parameter
R4L = value of byte read
Input Parameters:
READ DEVICE ID # 1
R0H = 00h
R6H = 00h
R6L = 0lh (device ID # 1)
Return Parameter
R4L =value of byte read
Input Parameters:
READ DEVICE ID # 2
READ SECURITY BITS
READSTATUS BYTE
READ BPC
R0H = 00h
R6H =00h
R6L = 02h (device ID # 2)
Return Parameter
R4L = value of byte read
Input Parameters:
R0H = 07h
R6H = 00h
R6L = 00h (security bits)
Return Parameter
R4L = value of byte read R4L[3:l] = sb3, sb2, sb1
Input Parameters:
R0H = 07h
R6H = 00h
R6L = 01h (status byte)
Return Parameter
R4L = value of BPC[l5:8]
Input Parameters:
R0H = 07h
R6H = 00h
R6L = 02h (boot vector)
Return Parameter
R4L = value of byte read
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MX10EXA
API CALL
PROGRAM ALL ZERO
PARAMETER
Input Parameters:
R0H = 90h
R6H = block number in bits 7:5, bits 4:0 = '0'
block 0 : r6h = 00h
block 1 : r6h = 20h
block 2 : r6h = 40h
block 3 : r6h = 80h
block 4 : r6h = c0h
R6L = 00h
Return Parameters:
R4L = 00 if pass, non-zero if fail
ERASE CHIP
Input Parameters:
R0H = 91h
R4L = 55H (after chip erase, return to caller)
= AAh (after chip erase, reset chip)
= others: error
Return Parameters:
R4L = 00 if pass, non-zero if fail
PROGRAM SPECIAL
CELL
Input Parameters:
R0H = 94h
R6 = special cell address
0000h:program BPSW[7:0]
0001h:program BPSW[15:8]
0002h:program BPC[7:0]
0003h:program BPC[15:8]
0004b:program status byte
000Ah:program security bit #1
000Ch:program security bit #2
000Eh:program security bit #3
R4L =byte value to program
Return Parameters:
R4L =00 if pass, non-zero if fail
Note : only two bits of these special cells may be programmed at one time
ERASE SPECIAL CELL Input Parameters:
R0H = 95h
R6
= special cell address
0000h: erase DPSW[7:0]
000lh: erase DPSW[15:8]
0002h: erase BPC(7:0)
0003h: erase BPC[15:8]
0004h: erase status byte
Return Parameters:
R4L = 00 if pass, non-zero if fail
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MX10EXA
API CALL
READ SPECIAL CELL
PARAMETER
Input Parameters:
R0H = 96h
R6
= special cell address
0000h: read BPSW[7:0]
000lh: read BPSW[15:8]
0002h: read BPC[7:0]
0003h: read BPC[15:8]
0004h: read status byte
0006h: read manufacturer ID
0007h: read device ID #1
0008h: read device ID #2
000Ah: read security bit #1
000Ch: read security bit #2
000Eh: read security bit #3
Return Parameters:
R4L
= value of byte read
Security
The security feature protects against software piracy and prevents the contents of the Flash from being read. The
Security Lock bits are located in Flash. The XAhas 3 programmable security lock bits that will provide different levels
of protection for the on-chip code and data
(see Table 3).
Table 3.
SECURITY LOCK BITS1
PROTECTIONDESCRIPTION
Level
SB1
0
SB2
0
SB3
0
1
2
No program security features enabled
1
0
0
Same as level 1, plus block erase is disabled. Erase or
programming of the status byte or boot vector is disabled.
Same as level 2, plus program verification is disabled
Same as level 3, plus external execution is disabled.
3
4
1
1
1
1
0
1
NOTE:
1. Any other combination of the Lock bits is not defined.
2. Security bits are independent of each other. Full-chip erase may be performed regardless of the states of the
security bits.
3. Setting LB doesn't prevent programming of unprogrammed bits.
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MX10EXA
XATIMER/COUNTERS
Timer modes 1, 2, and 3 in XA are kept identical to the
80C51 timer modes for code compatibility. Only the mode
0 is replaced in the XA by a more powerful 16-bit auto-
reload mode. This will give the XA timers a much larger
range when used as time bases.
The XAhas two standard 16-bit enhancedTimer/Counters:
Timer 0 and Timer 1.Additionally, it has a third 16-bit Up/
Down timer/counter, T2.Acentral timing generator in the
XA core provides the time-base for all XA Timers and
Counters. The timer/event counters can perform the fol-
lowing functions:
The recommended Ml, M0 settings for the different modes
are shown in Figure 6.
- Measure time intervals and pulse duration
- Count external events
- Generate interrupt requests
- Generate PWM or timed output waveforms
All of the timer/counters (Timer 0, Timer 1 and Timer 2)
can be independently programmed to operate either as
timers or event counters via the C/T bit in the TnCON
register. All timers count up unless otherwise stated.
These timers may be dynamically read during program
execution.
The base clock rate of all of the timers is user program-
mable. This applies to timers T0, T1, and T2 when run-
ning in timer mode (as opposed to counter mode), and
the watchdog timer. The clock driving the timers is called
TCLK and is determined by the setting of two bits (PT1,
PT0) in the System Configuration Register (SCR). The
frequency of TCLK may be selected to be the oscillator
input divided by 4 (Osc/4), the oscillator input divided by
16 (Osc/16), or the oscillator input divided by 64 (Osc/
64). This gives a range of possibilities for the XA timer
functions, including baud rate generation, Timer 2 cap-
ture. Note that this single rate setting applies to all of the
timers.
When timers T0, T1, or T2 are used in the counter mode,
the register will increment whenever a falling edge (high
to low transition) is detected on the external input pin
corresponding to the timer clock. These inputs are
sampled once every 2 oscillator cycles, so it can take
as many as 4 oscillator cycles to detect a transition.
Thus the maximum count rate that can be supported is
Osc/4. The duty cycle of the timer clock inputs is not
important, but any high or low state on the timer clock
input pins must be present for 2 oscillator cycles before
it is guaranteed to be “seen” by the timer logic.
Timer 0 and Timer 1
The “Timer” or “Counter” function is selected by control
bits C/T in the special function register TMOD. These
two Timer/Counters have four operating modes, which
are selected by bit-pairs (Ml, M0) in the TMOD register.
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MX10EXA
MSB
-
SCR
Address:440
LSB
Not Bit Addressable
Reset Value:00H
-
-
-
PT1
CM
PT0
PZ
PT1
PT0
OPERATING
Prescaler selection.
Osc/4
0
0
1
0
1
0
Osc/16
1
Osc/64
1
Reserved
CM
Compatibility Mode allows the XAto execute most translated 80C51 code on the XA. The
XA register file must copy the 80C51 mapping to data memory and mimic the 80C51
indirect addressing scheme.
PZ
Page Zero mode forces all program and data addresses to 16-bits only. This saves stack
space and speeds up execution but limits memory access to 64k.
Figure 5. System Configuration Register (SCR)
LSB
M0
MSB
Address:45C
Not Bit Addressable
Reset Value:00H
TMOD
GATE C/T
GATE
M1
TIMER 1
M0
M1
C/T
TIMER 0
GATE
C/T
Gating control when set. Timer/Counter "n" is enabled only while "INTn" pin is high and "TRn"
control bit is set. When cleared Timer "n" is enabled whenever "TRn" control bit is set.
Timer or Counter Selector cleared for Timer operation (input from internal system clock.) Set for
Counter operation (input from "Tn" input pin).
M1
0
0
1
1
M0
0
1
0
1
OPERATING
16-bit auto-reload timer/counter
16-bit non-auto-reload timer/counter
8-bit auto-reload timer/counter
Dual 8-bit timer mode (timer 0 only)
Figure 6. Timer/Counter Mode Control (TMOD) Register
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MX10EXA
New Enhanced Mode 0
sets TFn, but also reloads TLn with the contents of RTLn,
which is preset by software. The reload leaves THn un-
changed.
For timers T0 or T1 the 13-bit count mode on the 80C51
(current Mode 0) has been replaced in the XA with a 16-
bit auto-reload mode. Four additional 8-bit data registers
(two per timer: RTHn and RTLn) are created to hold the
auto-reload values. In this mode, the TH overflow will set
the TF flag in the TCON register and cause both the TL
and TH counters to be loaded from the RTL and RTH
registers respectively.
Mode 2 operation is the same for Timer/Counter 0.
The overflow rate for Timer 0 or Timer 1 in Mode 2 may
be calculated as follows:
Timer_Rate = Osc/(N* (256 - Timer_Reload_Value))
where N = the TCLK prescaler value: 4, 16, or 64.
These new SFRs will also be used to hold the TL reload
data in the 8-bit auto-reload mode (Mode 2) instead of
TH.
Mode 3
Timer 1 in Mode 3 simply holds its count. The effect is
The overflow rate for Timer 0 or Timer 1 in Mode 0 may
be calculated as follows:
the same as setting TR1 =0.
Timer 0 in Mode 3 establishes TL0 and TH0 as two sepa-
rate counters. TL0 uses the Timer 0 control bits: CIT;
GATE, TR0, INT0, and TF0. TH0 is locked into a timer
function and takes over the use of TR1 and TF1 from
Timer 1. Thus, TH0 now controls the "Timer 1" interrupt.
Timer_Rate = Osc/(N*(65536 - Timer_Reload_Value))
where N = the TCLK prescaler value: 4 (default), 16, or
64.
Mode 1
Mode 3 is provided for applications requiring an extra 8-
bit timer. When Timer 0 is in Mode 3, Timer 1 can be
turned on and off by switching it out of and into its own
Mode 3, or can still be used by the serial port as a baud
rate generator, or in fact, in any application not requiring
an interrupt.
Mode 1 is the 16-bit non-auto reload mode.
Mode 2
Mode 2 configures the Timer register as an 8-bit Counter
(TLn) with automatic reload. Overflow from TLn not only
LSB
IT0
MSB
TCON Address:410
Bit Addressable
Reset Value:00H
IT1
TR1
TF1
TF0
TR0
IE0
IE1
BIT
TCON.7
SYMBOL FUNCTION
TF1
Timer 1 overflow flag. Set by hardware on Timer/Counter overflow.
This flag will not be set if T1OE(TSTAT.2) is set.
Cleared by hardware when processor vectors to interrupt routine, or by clearing the bit
in software.
Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter 1 on/off.
Timer 0 overflow flag. Set by hardware on Timer/Counter overflow.
This flag will not be set if T0OE (TSTAT.0) is set.
TCON.6
TCON.5
TR1
TF0
Cleared by hardware when processor vectors to interrupt routine, or by clearing the bit
in software.
Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter 0 on/off.
Interrupt 1 Edge flag. Set by hardware when external interrupt edge detected.
Cleared when interrupt processed.
TCON.4
TCON.3
TR0
IE1
TCON.2
TCON.2
TCON.0
IT1
IE0
IT0
Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level
triggered external interrupts.
Interrupt 0 Edge flag. Set by hardware when external interrupt edge detected.
Cleared when interrupt processed.
Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/tow level
triggered external interrupts.
Figure 7. Timer/Counter(TCON) Register
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LSB
T2CON
Bit Addressable
Reset Value:00H
MSB
TF2
Address:418
TR2
EXEN2
C/T2
CP/RL2
EXF2 RCLK0 TCLK0
BIT
SYMBOL FUNCTION
T2CON.7
TF2
Timer 2 overflow flag. Set by hardware on Timer/Counter overflow. Must be cleared
by software. TF2 will not be set when RCLK0, RCLK1, TCLK0, TCLK1 or T2OE=1.
Timer 2 external flag is set when a capture or reload occurs due to a negative
transition on T2EX (and EXEN2 is set). This flag will cause a Timer 2 interrupt when
this interrupt is enabled. EXF2 is cleared by software.
Receive Clock Flag.
T2CON.6
EXF2
T2CON.5
T2CON.4
RCLK0
TCLK0
Transmit Clock Flag. RCLK0 and TCLK0 are used to select Timer 2 overflow rate as
a clock source for UART0 instead of Timer T1.
T2CON.3
EXEN2
Timer 2 external enable bit allows a capture or reload to occur due to a negative
transition on T2EX.
T2CON.2
T2CON.1
TR2
C/T2
Start = 1/Stop=0 control for Timer 2.
Timer or counter select.
0 = Internal timer
1 = External event counter (falling edge triggered)
Capture/Reload flag.
T2CON.0
CP/RL2
If CP/RL2 & EXEN2 = 1 captures will occur on negative transitions of T2EX.
If CP/RL2 = 0, EXEN2 = 1 auto reloads occur with either Timer 2 overflows or
negative transitions at T2EX.
If RCLK or TCLK = 1 the timer is set to auto reload on Timer 2 overflow, this bit has
no effect.
Figure 8. Timer/Counter 2 Control (T2CON) Register
which may be used to generate an interrupt. It can be
operated in one of three operating modes: auto-reload
(up or down counting), capture, or as the baud rate gen-
erator (for either or both UARTs via SFRs T2MOD and
T2CON). These modes are shown in Table 4.
New Timer-Overflow Toggle Output
In the XA, the timer module now has two outputs, which
toggle on overflow from the individual timers. The same
device pins that are used for the T0 and T1 count inputs
are also used for the new overflow outputs. An SFR bit
(TnOE in the TSTAT register) is associated with each
counter and indicates whether Port-SFR data or the over-
flow signal is output to the pin. These outputs could be
used in applications for generating variable duty cycle
PWM outputs (changing the auto-reload register values).
Also variable frequency (Osc/8 to Osc/8,388,608) out-
puts could be achieved by adjusting the prescaler along
with the auto-reload register values. With a 30.0MHz os-
cillator, this range would be 3.58Hz to 3.75MHz.
Capture Mode
In the capture mode there are two options which are se-
lected by bit EXEN2 in T2CON. If EXEN2 = 0, then timer
2 is a 16-bit timer or counter, which upon overflowing
sets bit TF2, the timer 2 overflow bit. This will cause an
interrupt when the timer 2 interrupt is enabled.
If EXEN2 = 1, then Timer 2 still does the above, but with
the added feature that a 1-to-0 transition at external in-
put T2EX causes the current value in the Timer 2 regis-
ters, TL2 and TH2, to be captured into registers RCAP2L
and RCAP2H, respectively. In addition, the transition at
T2EX causes bit EXF2 in T2CON to be set. This will
cause an interrupt in the same fashion as TF2 when the
Timer 2 interrupt is enabled. The capture mode is illus-
trated in Figure 11.
Timer T2
Timer 2 in the XA is a 16-bit Timer/Counter which can
operate as either a timer or as an event counter. This is
selected by C/T2 in the special function register T2CON.
Upon timer T2 overflow/underflow, the TF2 flag is set,
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timer T2 is incremented by TCLK.
Auto-Reload Mode (Up or Down Counter)
Baud Rate Generator Mode
In the auto-reload mode, the timer registers are loaded
with the 16-bit value in T2CAPH and T2CAPL when the
count overflows. T2CAPH and T2CAPLare initialized by
software. If the EXEN2 bit in T2CON is set, the timer
registers will also be reloaded and the EXF2 flag set
when a 1-to-0 transition occurs at input T2EX. The auto-
reload mode is shown in Figure 12.
By setting theTCLKn and/or RCLKn in T2CONorT2MOD,
the Timer 2 can be chosen as the baud rate generator for
either or both UARTs. The baud rates for transmit and
receive can be
simultaneously different.
Programmable Clock-Out
In this mode, Timer 2 can be configured to count up or
down. This is done by setting or clearing the bit DCEN
(Down Counter Enable) in the T2MOD special function
register (see Table 4). The T2EX pin then controls the
count direction. When T2EX is high, the count is in the
up direction, when T2EX is low, the count is in the down
direction.
A 50% duty cycle clock can be programmed to come
out on P1 .6. This pin, besides being a regular I/O pin,
has two alternate functions. It can be programmed (1) to
input the external clock for Timer/Counter 2 or (2) to out-
put a 50% duty cycle clock ranging from 3.58Hz to
3.75MHz at a 30MHz operating frequency.
Figure 12 shows Timer 2, which will count up automati-
cally, since DCEN = 0. In this mode there are two op-
tions selected by bit EXEN2 in the T2CON register. If
EXEN2 =0, then Timer 2 counts up to FFFFH and sets
the TF2 (Overflow Flag) bit upon overflow. This causes
the Timer 2 registers to be reloaded with the 16-bit value
in T2CAPL and T2CAPH, whose values are preset by
software. If EXEN2 = 1, a 16-bit reload can be triggered
either by an overflow or by a 1 -to-0 transition at input
T2EX. This transition also sets the EXF2 bit. If enabled,
either TF2 or EXF2 bit can generate the Timer 2 inter-
rupt.
To configure the Timer/Counter 2 as a clock generator,
bit C/T2 (in T2CON) must be cleared and bit T2OE in
T2MOD must be set. Bit TR2 (T2CON.2) also must be
set to start the timer.
The Clock-Out frequency depends on the oscillator fre-
quency and the reload value of Timer 2 capture registers
(TCAP2H, TCAP2L) as shown in this equation:
TCLK
2 x (65536 - TCAP2H, TCAP2L)
In the Clock-Out mode Timer 2 roll-overs will net gener-
ate an interrupt. This is similar to when it is used as a
baud-rate generator. It is possible to use Timer 2 as a
baud-rate generator and a clock generator simultaneously.
Note, however, that the baud-rate will be 1/8 of the Clock-
Out frequency.
In Figure 13, the DCEN = 1; this enables the Timer 2 to
count up or down. In this mode, the logic level of T2EX
pin controls the direction of count. When a logic "1" is
applied at pin T2EX, the Timer 2 will count up. The Timer
2 will overflow at FFFFH and set the TF2 flag, which can
then generate an interrupt if enabled. This timer overflow,
also causes the 16-bit value in T2CAPL and T2CAPH to
be reloaded into the timer registers TL2 and TH2, respec-
tively.
A logic "0" at pin T2EX causes Timer 2 to count down.
When counting down, the timer value is compared to the
16-bit value contained in T2CAPH and T2CAPL. When
the value is equal, the timer register is loaded with FFFF
hex. The underflow also sets the TF2 flag, which can
generate an interrupt if enabled.
The external Flag EXF2 toggles when Timer 2 underflows
or overflows. This EXF2 bit can be used as a 17th bit of
resolution, if needed. the EXF2 flag does not generate
an interrupt in this mode. As the baud rate generator,
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MX10EXA
Table 4. Timer 2 Operating Modes
TR2 CP/RL2 RCLK+TCLK
OCEN
MODE
0
1
1
1
1
X
0
0
1
X
X
0
0
0
1
X
0
Timer oft (stopped)
16-bit auto-reload, counting up
1
16-bit auto-reload, counting up or down depending on T2EX pin
X
X
16-bitcapture
Baud rate generator
MSB
-
LSB
Address:411
Bit Addressable
Reset Value:00H
TSTAT
-
-
-
-
-
T1OE
T0OE
BIT
SYMBOL FUNCTION
TSTAT.2
T1OE
When 0, this bit allows the T1 pin to clock Timer 1 when in the counter mode.
When 1, T1 acts as an output and toggles at every Timer 1 overflow.
When 0, this bit allows the To pin to clock Timer 0 when in the counter mode.
When 1, T0 acts as an output and toggles at every Timer 0 overflow.
TSTAT.0
T0OE
Figure 9. Timer 0 and 1 Extended Status (TSTAT)
MSB
-
LSB
T2MOD
Address:419
Bit Addressable
Reset Value:00H
-
RCLK1
-
-
T2OE DCEN
TCLK1
BIT
SYMBOL FUNCTION
T2MOD.5
T2MOD.4
RCLK1
TCLK1
Receive Clock Flag.
Transmit Clock Flag. RCLK1 and TCLK1 are used to select Timer 2 overflow rate as
a clock source for UART1 instead of Timer T1.
T2MOD.1
T2MOD.5
T2OE
DCEN
When 0, this bit allows the T2 pin to clock Timer 2 when in the counter mode.
When 1, T2 acts as an output and toggles at every Timer 2 overflow.
Controls count direction for Timer 2 in autoreload mode.
DCEN=0 counter set to count up only
DCEN=1 counter set to count up or down, depending on T2EX (see text).
Figure 10. Timer 2 Mode Control (T2MOD)
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MX10EXA
TCLK
C/T2=0
C/T2=1
TL2
(8-bits)
TH2
(8-bits)
TF2
T2 Pin
Control
TR2
Capture
Timer 2
Interrupt
T2CAPL
T2CAPH
Transition
Detector
EXF2
T2EX Pin
Control
EXEN2
Figure 11.Timer 2 in Capture Mode
TCLK
C/T2=0
C/T2=1
TH2
(8-bits)
TL2
(8-bits)
T2 Pin
Control
TR2
Reload
T2CAPL
T2CAPH
Transition
Detector
TF2
Timer 2
Interrupt
T2EX Pin
EXF2
Control
EXEN2
Figure 12.Timer2 in Auto-Reload Mode(DECN=0)
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MX10EXA
(DOWN COUNTING RELOAD VALUE)
TOGGLE
FFH
FFH
EXF2
TCLK
OVERFLOW
C/T2=0
C/T2=1
TH2
TL2
INTERUPT
TF2
T2 PIN
CONTROL
TR2
COUNT
DIRECTION
1=UP
0=DOWN
T2CAPL
T2CAPH
T2EX PIN
(UP COUNTING RELOAD VALUE)
Figure 13.Timer 2 Auto Reload Mode (DCEN=1)
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WATCHDOGTIMER
before feeding the watchdog. The instructions should
moveA5H to the WFEED1 register and then 5AH to the
WFEED2 register. If WFEED1 is correctly loaded and
WFEED2 is not correctly loaded, then an immediate
watchdog reset will occur. The program sequence to feed
the watchdog timer or cause new WDCON settings to
take effect is as follows:
The watchdog timer subsystem protects the system from
incorrect code execution by causing a system reset when
the watchdog timer underflows as a result of a failure of
software to feed the timer prior to the timer reaching its
terminal count. It is important to note that the watchdog
timer is running after any type of reset and must be turned
off by user software if the application does not use the
watchdog function.
clr
ea
; disable global interrupts.
Mov.b wfeed1, #A5h ; do watchdog feed part 1
mov.b wfeed2, #5Ah ; do watchdog feed part 2
setb
ea
; re-enable global interrupts.
Watchdog Function
This sequence assumes that the XA interrupt system is
enabled and there is a possibility of an interrupt request
occurring during the feed sequence. If an interrupt was
allowed to be serviced and the service routine contained
any SFR access, it would trigger a watchdog reset. If it
is known that no interrupt could occur during the feed
sequence, the instructions to disable and re-enable in-
terrupts may be removed.
The watchdog consists of a programmable prescaler and
the main timer. The prescaler derives its clock from the
TCLK source that also drives timers 0, 1, and 2. The
watchdog timer subsystem consists of a programmable
13-bit prescaler, and an 8-bit main timer. The main timer
is clocked (decremented) by a tap taken from one of the
top 8-bits of the prescaler as shown in Figure 14. The
clock source for the prescaler is the same as TCLK (same
as the clock source for the timers). Thus the main counter
can be docked as often as once every 32 TCLKs (see
Table 5). The watchdog generates an underflow signal
(and is autoloaded from WDL) when the watchdog is at
count 0 and the clock to decrement the watchdog oc-
curs. The watchdog is 8 bits wide and the autoload value
can range from 0 to FFH. (The autoload value of 0 is
permissible since the prescaler is cleared upon autoload).
The software must be written so that a feed operation
takes place every tD seconds from the last feed opera-
tion. Some tradeoffs may need to be made. It is not ad-
visable to include feed operations in minor loops or in
subroutines unless the feed operation is a specific sub-
routine.
To turn the watchdog timer completely off, the following
code sequence should be used:
mov.b wdcon, #0
; setWDcontrol register to clear
WDRUN.
This leads to the following user design equations. Defini-
tions: tOSC is the oscillator period, N is the selected
prescaler tap value, Wis the main counter autoload value,
P is the prescaler value from Table 5, tMIN is the mini-
mum watchdog time-out value (when the autoload value
is 0), tMAX is the maximum time-out value (when the
autoload value is FFH), tD is the design time-out value.
mov.b wfeed1 , #A5h ; do watchdog feed part 1
mov.b wfeed2, #5Ah ; do watchdog feed part 2
This sequence assumes that the watchdog timer is be-
ing turned off at the beginning of initialization code and
that the XA interrupt system has not yet been enabled. If
the watchdog timer is to be turned off at a point when
interrupts may be enabled, instructions to disable and
re-enable interrupts should be added to this sequence.
tMIN = tOSC x 4 x 32 (W = 0, N = 4)
tMAX = tOSC x 64 x 4096 x 256 (W =255, N =64)
tD = tOSC x N x P x (W + 1)
The watchdog timer is not directly loadable by the user.
Instead, the value to be loaded into the main timer is
held in an autoload register. In order to cause the main
timer to be loaded with the appropriate value, a special
sequence of software action must take place. This op-
eration is referred to as feeding the watchdog timer.
Watchdog Control Register (WDCON)
The reset values of the WDGON and WDL registers will
be such that the watchdog timer has a timeout period of
4 x 4096 x tOSC and the watchdog is running. WDCON
can be written by software but the changes only take
effect after executing a valid watchdog feed sequence.
To feed the watchdog, two instructions must be sequen-
tially executed successfully. No intervening SFR ac-
cesses are allowed, so interrupts should be disabled
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Table 5. Prescaler Select Values in WDCON
WatchdogDetailed Operation
When external RESET is applied, the following takes
place:
• Watchdog run control bit set to ON (1).
• Autoload register WDL set to 00 (mm. count).
• Watchdog time-out flag cleared.
• Prescaler is cleared.
• Prescaler tap set to the highest divide.
• Autoload takes place.
When coming out of a hardware reset, the software should
load the autoload register and then feed the watchdog
(cause an autoload).
If the watchdog is running and happens to underflow at
the time the external RESET is applied, the watchdog
time-out flag will be cleared.
PRE2
PRE1
PRED
DIVISOR
32
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
64
128
256
512
1024
2048
4096
WDL
WATCHDOG FEED SEQUENCE
MOV WFEED1,#A5H
MOV WFEED2,#5AH
8-BIT DOWN
COUNTER
INTERNAL RESET
TCLK
PRESCALER
WDTOF
WDRUN
PRE2 PRE1
PRE0
-
-
-
WDCON
Figure 14. Watchdog Timer in XA
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MX10EXA
When the watchdog underflows, the following action takes
place (see Figure 14):
• Autoload takes place.
• Watchdog time-out flag is set
• Watchdog run bit unchanged.
Timer 1 defaults to clock both UART0 and UART1. Timer
2 can be programmed to clock either UART0 through
T2CON(via bits R0CLK and T0CLK) or UART1 through
T2MOD (via bits R1CLK and T1 CLK). In this case, the
UARTnot clocked byT2 could use T1 as the clock source.
• Autoload (WDL) register unchanged.
• Prescaler tap unchanged.
The serial port receive and transmit registers are both
accessed at Special Function Register SnBUF Writing
to SnBUF loads the transmit register, and reading SnBUF
accesses a physically separate receive register.
• All other device action same as external reset.
Note that if the watchdog underflows, the program counter
will be loaded from the reset vector as in the case of an
internal reset. The watchdog time-out flag can be exam-
ined to determine if the watchdog has caused the reset
condition. The watchdog time-out flag bit can be cleared
by software.
The serial port can operate in 4 modes:
Mode 0: Serial I/O expansion mode. Serial data enters
and exits through RxDn. TxDn outputs the shift clock. 8
bits are transmitted/received (LSB first). (The baud rate
is fixed at 1/16 the oscillator frequency.)
WDCON Register Bit Definitions
WDCON.7 PRE2
WDCON.6 PREl
WDCON.5 PRE0
Prescaler Select 2, reset to 1
Prescaler Select 1, reset to 1
Prescaler Select 0, reset to 1
Mode 1: Standard 8-bit UART mode. 10 bits are
transmitted(through TxDn) or received (through RxDn): a
start bit (0), 8 data bits (LSB first), and a stop bit (1). On
receive, the stop bit goes intoRB8 in Special Function
Register SnCON. The baud rate is variable.
WDCON.4
WDCON.3
-
-
WDCON.2 WDRUN Watchdog Run Control bit, re
set to 1
WDCON.1 WDTOF Time out flag
Mode 2: Fixed rate 9-bit UART mode. 11 bits are trans-
mitted (through TxD) or received (through RxD): start bit
(0), 8 data bits (LSB first), a programmable 9th data bit,
and a stop bit (1). On Transmit, the 9th data bit TB8_n in
SnCON) can be assigned the value of 0 or 1. Or, for
example, the parity bit (P, in the PSW) could be moved
intoTB8_n. On receive, the 9th data bit goes into RB8_n
in Special Function Register SnCON, while the stop bit
is ignored. The baud rate is programmable to 1/32 of the
oscillator frequency.
WDCON.0
-
UARTs
Baud rate selection is somewhat different due to the
clocking scheme used for the XA timers.
Some other enhancements have been made to UART
operation. The first is that there are separate interrupt
vectors for each UART’s transmit and receive functions.
The UART transmitter has been double buffered, allow-
ing packed transmission of data with no gaps between
bytes and less critical interrupt service routine timing. A
break detect function has been added to the UART. This
operates independently of the UART itself and provides
a start-of-break status bit that the program may test.
Finally, an Overrun Error flag has been added to detect
missed characters in the received data stream. The
double buffered UART transmitter may require some
software changes in code written for the original XA single
buffered UART.
Mode 3: Standard 9-bit UART mode. 11 bits are trans-
mitted (through TxDn) or received (through RxDn): a start
bit (0), 8 data bits (LSB first), a programmable 9th data
bit, and a stop bit (1). In fact, Mode 3 is the same as
Mode 2 in all respects except baud rate. The baud rate in
Mode 3 is variable.
In all four modes, transmission is initiated by any in-
struction that uses SnBUF as a destination register. Re-
ception is initiated in Mode 0 by the condition RI_n = 0
and REN_n = 1. Reception is initiated in the other modes
by the incoming start bit if REN_n = 1.
Each UART baud rate is determined by either a fixed
division of the oscillator (in UART modes 0 and 2) or by
the timer 1 or timer 2 overflow rate (in UART modes 1
and 3).
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MX10EXA
Serial Port Control Register
9-bIt Mode
The serial port control and status register is the Special
Function Register SnCON, shown in Figure 16. This reg-
ister contains not only the mode selection bits, but also
the 9th data bit for transmit and receive (TB8_n and
RB8_n), and the serial port interrupt bits TI_n and RI_n).
Please note that the ninth data bit (TB8) is not double
buffered. Care must be taken to insure that the TB8 bit
contains the intended data at the point where it is trans-
mitted.Double buffering of the UART transmitter may be
bypassed as a simple means of synchronizing TB8 to
the rest of the data stream.
TI Flag
Bypassing Double Buffering
In order to allow easy use of the double buffered UART
transmitter feature, the TI_n flag is set by the UART hard-
ware under two conditions. The first condition is the
completion of any byte transmission. This occurs at the
end of the stop bit in modes 1, 2, or 3, or at the end of
the eighth data bit in mode 0. The second condition is
when SnBUF is written while the UART transmitter is
idle. In this case, the TI_n flag is set in order to indicate
that the second UART transmitter buffer is still avail-
able.
The UART transmitter may be used as if it is single buff-
ered. The recommended UART transmitter interrupt ser-
vice routine (ISR) technique to bypass double buffering
first clears the TI_n flag upon entry into the ISR, as in
standard practice. This clears the interrupt that activated
the ISR. Secondly, the TI_n flag is cleared immediately
following each write to SnBUF. This clears the interrupt
flag that would otherwise direct the program to write to
the second transmitter buffer. If there is any possibility
that a higher priority interrupt might become active be-
tween the write to SnBUF and the clearing of the TI_n
flag, the interrupt system may have to be temporarily
disabled during that sequence by clearing, then setting
the EA bit in the IEL register.
Typically, UART transmitters generate one interrupt per
byte transmitted. In the case of the XA UART, one addi-
tional interrupt is generated as defined by the stated con-
ditions for setting the TI_n flag. This additional interrupt
does not occur if double buffering is bypassed as ex-
plained below.Note that if a character oriented approach
is used to transmit data through the UART; there could
be a second interrupt for each character transmitted,
depending on the timing of the writes to SBUF. For this
reason, it is generally better to bypass double buffering
when the UART transmitter is used in character oriented
mode. This is also true if the UART is polled rather than
interrupt driven, and when transmission is character ori-
ented rather than message or string oriented. The inter-
rupt occurs at the end of the last byte transmitted when
the UART becomes idle.Among other things, this allows
a program to determine when a message has been trans-
mitted completely. The interrupt service routine should
handle this additional interrupt.
The recommended method of using the double buffering
in the application program is to have the interrupt ser-
vice routine handle a single byte for each interrupt oc-
currence. In this manner the program essentially does
not require any special considerations for double buffer-
ing. Unless higher priority interrupts cause delays in the
servicing of the UART transmitter interrupt, the double
buffering will result in transmitted bytes being tightly
packed with no intervening gaps.
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MX10EXA
CLOCKING SCHEME/BAUD RATEGENERATION
Baud Rate for UART Mode 2:
Baud_Rate = Osc/32
The XA UARTS clock rates are determined by either a
fixed division (modes 0 and 2) of the oscillator clock or
by the Timer 1 or Timer 2 overflow rate (modes 1 and 3).
Using Timer 2 toGenerate Baud Rates
The clock for the UARTs in XA runs at 1 6x the Baud
rate. If the timers are used as the source for Baud Clock,
since maximum speed of timers/Baud Clock is Osc/4,
the maximum baud rate is timer overflow divided by 16
i.e. Osc/64.
Timer T2 is a 16-bit up/down counter in XA. As a baud
rate generator, timer 2 is selected as a clock source for
either/both UART0 and UART1 transmitters and/or re-
ceivers by setting TCLKn and/or RCLKn in T2CON and
T2MOD. As the baud rate generator, T2 is incremented
as Osc/N where N = 4, 16 or 64 depending on TCLK as
programmed in the SCR bits PT1, and PTO. So, if T2 is
the source of one UART, the other UART could be clocked
by either T1 overflow or fixed clock, and the UARTs could
run independently with different baud rates.
In Mode 0, it is fixed at Osc/1 6. In Mode 2, however, the
fixed rate is Osc/32.
Pre-scaler
00
01
10
11
Osc/4
for all Timers T0, 1, 2,
controlled by PT1, PT0
bits in SCR
Osc/16
Osc/64
reserved
T2CON
0x418
bit5
bit4
RCLK0
TCLK0
T2MOD
0x419
bit5
bit4
Baud Rate for UART Mode 0:
Baud_Rate = Osc/16
RCLK1
TCLK1
Baud Rate calculation for UART Mode 1 and 3:
Baud_Rate
= Timer_Rate/16
Timer_Rate
=Osc/(N*(Timer_Range-
Timer_Reload_Value))
Prescaler Select for Timer Clock (TCLK)
whereN = the TCLK prescaler value: 4,16, or 64.
and Timer_Range = 256 for timer 1 in mode 2.
65536 for timer 1 in mode 0 and timer 2 in count up
mode.
SCR
bit3
bit2
0x440
PT1
PT0
The timer reload value may be calculated as follows:
Timer_Reload_Value
(Baud_Rate*N*1 6))
=
Timer_Range(Osc/
NOTES:
1.The maximum baud rate for a UART in mode 1 or 3 is
Osc/64.
2.The lowest possible baud rate (for a given oscillator
frequency and N value) may be found by using a timer
reload value of 0.
3.The timer reload value may never be larger than the
timer range.
4.If a timer reload value calculation gives a negative or
fractional result, the baud rate requested is not pos-
sible at the given oscillator frequency and N value.
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MX10EXA
SnSTATAddress:
S0STAT 421
S1STAT 425
LSB
MSB
-
-
-
-
BRn
FEn
OEn STINTn
Bit Addressable
Reset Value:00H
BIT
SYMBOL FUNCTION
SnSTAT.3
FEn
Framing Error flag is set when the receiver fails to see a valid STOP bit at the end
of the frame. Cleared by software.
SnSTAT.2
BRn
Break Detect flag is set if a character is received with all bits (including STOP bit)
being logic ‘0’. Thus it gives a “Start of Break Detect” on bit 8 for Mode 1 and bit
9 for Modes 2 and 3. The break detect feature operates independently of the UARTs
and provides the START of Break Detect status bit that a user program may poll.
Cleared by software.
SnSTAT.1
SnSTAT.0
OEn
Overrun Error flag is set if a new character is received in the receiver buffer while it
is still full (before the software has read the previous character from the buffer), i.e.,
when bit 8 of a new byte is received while RI in SnCON is still set. Cleared by
software.
This flag must be set to enable any of the above status flags to generate a receive
interrupt (Rln). The only way it can be cleared is by a software write to this register.
STINTn
Figure 15. Serial Port Extended Status (SnSTAT) Register
(See also Figure 17 regarding Framing Error flag)
INTERRUPT SCHEME
received. The 9th one goes into RB8. Then comes a stop
bit. The port can be programmed such that when the
There are separate interrupt vectors for each UART’s
transmit and receive functions.
stop bit is received, the serial port interrupt will be acti-
vated only if RB8 = 1. This feature is enabled by setting
bit SM2 in SCON. A way to use this feature in multipro-
cessor systems is as follows:
Table 6. Vector Locations for UARTS in XA
Vector Address Interrupt Source Arbitration
When the master processor wants to transmit a block of
data to one of several slaves, it first sends out an ad-
dress byte which identifies the target slave. An address
byte differs from a data byte in that the 9th bit is 1 in an
address byte and 0 in a data byte. With SM2 = 1, no
slave will be interrupted by a data byte. An address byte,
however, will interrupt all slaves, so that each slave can
examine the received byte and see if it is being addressed.
The addressed slave will clear its SM2 bit and prepare to
receive the data bytes that will be coming. The slaves
that weren’t being addressed leave their SM2s set and
go on about their business, ignoring the coming data
bytes.
A0H - A3H
A4H - A7H
A8H - ABH
ACH-AFH
UART 0 Receiver
UART 0 Transmitter 8
UART I Receiver
UARTI Transmitter 10
7
9
NOTE:
The transmit and receive vectors could contain the same
ISR address to work like a 8051 interrupt scheme
Error Handling, Status Rags and Break Detect
The UARTs in XA has the following error flags; see Fig-
ure 15.
SM2 has no effect in Mode 0, and in Mode 1 can be
used to check the validity of the stop bit although this is
better done with the Framing Error (FE) flag. In a Mode 1
reception, if SM2 = 1, the receive interrupt will not be
activated unless a valid stop bit is received.
Multiprocessor Communications
Modes 2 and 3 have a special provision for multiproces-
sor communications. in these modes, 9 data bits are
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MX10EXA
Automatic Address Recognition
Slave0
SADDR
SADEN
Given
=1100 0000
=1111 1001
=1100 0XX0
=1110 0000
=1111 1010
=1110 0X0X
=1110 0000
=1111 1100
=1110 00XX
Automatic Address Recognition is a feature which al-
lows the UART to recognize certain addresses in the
serial bit stream by using hardware to make the com-
parisons. This feature saves a great deal of software
overhead by eliminating the need for the software to ex-
amine every serial address which passes by the serial
port. This feature is enabled by setting the SM2 bit in
SCON. In the 9 bit UART modes, mode 2 and mode 3,
the Receive Interrupt flag (RI) will be automatically set
when the received byte contains either the "Given"” ad-
dress or the “Broadcast” address. The 9 bit mode re-
quires that the 9th information bit is a 1 to indicate that
the received information is an address and not data.
Automatic address recognition is shown in Figure 18.
Slave 1 SADDR
SADEN
Given
SIave2 SADDR
SADEN
Given
In the above example the differentiation among the 3
slaves is in the lower 3 address bits. Slave 0 requires
that bit 0 = 0 and it can be uniquely addressed by 1110
0110. Slave 1 requires that bit 1 = 0 and it can be uniquely
addressed by 1110 and 0101. Slave 2 requires that bit 2
= 0 and its unique address is 1110 0011. To select Slaves
0 and 1 and exclude Slave 2 use address 1110 0100,
since it is necessary to make bit 2 = 1 to exclude slave
2.
Using the Automatic Address Recognition feature allows
a master to selectively communicate with one or more
slaves by invoking the Given slave address or addresses.
All of the slaves may be contacted by using the Broad-
cast address. Two special Function Registers are used
to define the slave’s address, SADDR, and the address
mask, SADEN. SADEN is used to define which bits in
the SAD DR are to be used and which bits are “don’t
care”. The SADEN mask can be logically ANDed with
the SAD DR to create the “Given” address which the
master will use for addressing each of the slaves. Use
of the Given address allows multiple slaves to be recog-
nized while excluding others. The following examples will
help to show the versatility of this scheme:
The Broadcast Address for each slave is created by tak-
ing the logical OR of SADDR and SADEN. Zeros in this
result are tested as don’t-cares. In most cases, inter-
preting the don’t-cares as ones, the broadcast address
will be FF hexadecimal.
Upon reset SADDR and SADENare loaded with Os. This
produces a given address of all “don’t cares” as well as
a Broadcast address of all “don’t cares”. This effec-
tively disables the Automatic Addressing mode and al-
lows the microcontroller to use standard UART drivers
which do not make use of this feature.
Siave0 SADDR
SADEN
Given
Slavel SADDR
SADEN
=1100 0000
=1111 1101
=1100 00X0
=1100 0000
=1111 1110
=1100 000X
Given
In the above example SADDR is the same and the SAD
EN data is used to differentiate between the two slaves.
Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1
requires a 0 in bit 1 and bit 0 is ignored. A unique ad-
dress for Slave 0 would be 1100 0010 since slave 1
requires a 0 in bit 1. A unique address for slave 1 would
be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both
slaves can be selected at the same time by an address
which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave
1). Thus, both could be addressed with 1100 0000.
In a more complex system the following could be used
to select slaves 1 and 2 while excluding slave 0:
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MX10EXA
LSB
SnCON
MSB
SM0
Address:S0CON 420
S1CON 424
RB8
TB8
TI
RI
SM1
SM2 REN
Bit Addressable
Reset Value:00H
Where SM0, SM1, specify the serial port mode, as bollows:
SM0
SM1
Mode
Description
shift register
8-bit UART
9-bit UART
9-bit UART
Baud Rate
fOSC/16
variable
fOSC/32
variable
0
0
1
1
0
1
0
1
0
1
2
3
BIT
SnCON.5
SYMBOL
SM2
FUNCTION
Enables the multiprocessor communication feature in Modes 2 and 3. In Mode 2 or
3, if SM2 is set to 1, then RI will not be activated it the received 9th data bit (RB8)
is 0. In Mode 1, it SM2=1 then RI will not be activated if a valid stop bit was not
received. In Mode 0, SM2 should be 0.
SnCON.4
SnCON.3
SnCON.2
SnCON.1
SnCON.0
REN
TB8
RB8
TI
Enables serial reception. Set by software to enable reception. Clear by software to
disable reception.
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software
as desired. The TB8 bit is not double buffered. See text for details.
In Modes 2 and 3, is the 9th data bit that was received. In Mode 1, it SM2=0, RB8
is the stop bit that was received. In Mode 0, RB8 is not used.
Transmit interrupt flag. Set when another byte may be written to the UART transmit-
ter. See text for details. Must be cleared by software.
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or
at the end of the stop bit time in the other modes (except see SM2). Must be
cleared by software.
RI
Figure 16. Serial Port Control (SnCON) Register
D0
D1
D2
D3
D4
D5
D6
D7
D8
ONLY IN
STOP
BIT
START
BIT
MODE 2,3
DATA BYTE
If 0, sets FE
-
-
-
-
FEn
BRn
OEn STINTn
SnSTAT
Figure 17. UART Framing Error Detection
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MX10EXA
D0
D1
D2
D3
D4
D5
D6
D7
D8
SM1_n SM2_n REN_n
SM0_n
TB8_n RB8_n TI_n
X
RI_n
SnCON
1
1
1
0
1
1
RECEIVED ADDRESS D0 TO D7
PROGRAMMED ADDRESS
COMPARATOR
IN UART MODE 2 OR MODE 3 AND SM2=1:
INTERRUPT IF REN=1, RB8=1 AND "RECEIVED ADDRESS" = "PROGRAMMED ADDRESS"
-WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVED DATA BYTES
-WHEN ALL DATA BYTES HAVE BEEN RECEIVED:SET SM2 TO WAIT FOR NEXT ADDRESS
Figure 18. UART Multiprocessor Communication, Automatic Address Recognition
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MX10EXA
I/OPORTOUTPUTCONFIGURATION
RESET
Each I/O port pin can be user configured to one of 4
output types. The types are Quasi-bidirectional (essen-
tially the same as standard 80C51 family I/O ports),
Open-Drain, Push-Pull, and Off (high impedance). The
default configuration after reset is Quasi-bidirectional.
However, in the ROM less mode (the EA pin is low at
reset), the port pins that comprise the external data bus
will default to push-pull outputs.
The device is reset whenever a logic "0" is applied to
RST for at least 10 microseconds, placing a low level
on the pin re-initializes the on-chip logic. Reset must be
asserted when power is initially applied to the XA and
held until the oscillator is running.
The duration of reset must be extended when power is
initially applied or when using reset to exit power down
mode. This is due to the need to allow the oscillator time
to start up and stabilize. For most power supply ramp up
conditions, this time is 10 milliseconds.
I/O port output configurations are determined by the set-
tings in port configuration SFRs. There are 2 SFRs for
each port, called PnCFGA and PnCFGB, where “n” is
the port number. One bit in each of the 2 SFRs relates to
the output setting for the corresponding port pin, allow-
ing any combination of the 2 output types to be mixed
on those port pins. For instance, the output type of port
1 pin 3 is controlled by the setting of bit 3 in the SFRs
P1CFGA and P1CFGB.
As RST is brought high again, an exception is generated
which causes the processor to jump to the reset address.
Typically, this is the address contained in the memory
location 0000. The destination of the reset jump must be
located in the first 64k of code address on power-up, all
vectors are 16-bit values and so point to page zero ad-
dresses only. After a reset the RAM contents are inde-
terminate.
Table 7 shows the configuration register settings for the
4 port output types. The electrical characteristics of each
output type may be found in the DC Characteristic table.
Alternatively, the Boot Vector may supply the reset ad-
dress. This happens when use of the Boot Vector is forced
or when the Flash status byte is non-zero. These cases
are described in the section “Hardware Activation of the
Boot Vector” on page 10.
Table 7. Port Configuration Register Settings
PnCFGB
PnCFGA
Port Output Mode
0
0
1
1
0
1
0
1
Open Drain
Quasi-bidirectional
Off (high impedance)
Push-Pull
VDD
NOTE:
XA
Mode changes may cause glitches to occur during tran-
sitions. When modifying both registers, WRITE instruc-
tions should be carried out consecutively.
R
RESET
C
EXTERNAL BUS
The external program/data bus allows for 8-bit or 16-bit
bus width, and address sizes from 12 to 20 bits. The bus
width is selected by an input at reset (see Reset Op-
tions below), while the address size is set by the pro-
gram in a configuration register. If all off-chip code is
selected (through the use of the EA pin), the initial code
fetches will be done with the maximum address size (20
bits).
SOME TYPICAL VALUES FOR A AND C:
R=100K, C=1.0uF
R=1.0M, C=0.1uF
(ASSUMING THAT THE VDD RISE TIME IS 1ms OR LESS)
Figure 19. Recommended Reset Circuit
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MX10EXA
RESET OPTIONS
The XA defines tour types of interrupts:
The EA pin is sampled on the rising edge of the RST
pulse, and determines whether the device is to begin
execution from internal or external code memory. EA
pulled high configures the XA in single-chip mode. If EA
is driven low, the device enters ROMless mode. After
Reset is released, the EA/WAIT pin becomes a bus wait
signal for external bus transactions.
• Exception Interrupts - These are system level errors
and other very important occurrences which include stack
overflow, divid-by-0, and reset.
• Event Interrupts - These are peripheral interrupts from
devices such as UARTs, timers, and external interrupt
inputs.
• Software Interrupts - These are equivalent of hard-
ware interrupt, but are requested only under software
control.
• Trap Interrupts - These are TRAP instructions, gener-
ally used to call system services in a multi-tasking sys-
tem.
The BUSW/P3.5 pin is weakly pulled high while reset is
asserted, allowing simple biasing of the pin with a resis-
tor to ground to select the altermate bus width. If the
BUSW pin is not driven at reset, the weak pullup will
causes 1 to be loaded for the bus width, giving a 16-bit
external bus. BUSW may be pulled low with a 2.7K or
smaller value resistor, giving an 8-bit external bus. The
bus width setting from the BUSW pin may be overridden
by software once the user program is running.
Exception interrupts, software interrupts, and trap inter-
rupts are generally standard for XA derivatives and are
detailed in the XA User Guide. Event interrupts tend to
be different on different XA derivatives.
Both EA and BUSW must be held for three oscillator
clock times after reset is deasserted to guarantee that
their values are latched correctly.
The XA supports a total of 9 maskable event interrupt
sources (for the various XA peripherals), seven software
interrupts, 5 exception interrupts (plus reset), and 16 traps.
The maskable event interrupts share a global interrupt
disable bit (the EA bit in the IEL register) and each also
has a separate individual interrupt enable bit (in the IEL
or IEH registers). Only three bits of the IPA register val-
ues are used on the XA. Each event interrupt can be set
to occur at one of 8 priority levels via bits in the Interrupt
Priority (IP) registers, IPA0 through IPA5. The value 0 in
the IPA field gives the interrupt priority 0, in effect dis-
abling the interrupt. A value of 1 gives the interrupt a
priority of 9, the value 2 gives priority 10, etc. The result
is the same as if all four bits were used and the top bit
set for all values except 0.
POWER REDUCTION MODES
The XAsupports Idle and Power Down modes of power
reduction. The idle mode leaves some peripherals run-
ning to allow them to wake up the processor when an
interrupt is generated. The power down mode stops the
oscillator in order to minimize power. The processor can
be made to exit power down mode via reset or one of the
external interrupt inputs. In order to use an external inter-
rupt to re-activate the XA while in power down mode, the
external interrupt must be enabled and be configured to
level sensitive mode. In power down mode, the power
supply voltage may be reduced to the RAM keep-alive
voltage (2V), retaining the RAM, register, and SFR val-
ues at the point where the power down mode was en-
tered.
The complete interrupt vector list for the XA, including
all 4 interrupt types, is shown in the following tables. The
tables include the address of the vector for each inter-
rupt, the related priority register bits (if any), and the ar-
bitration ranking for that interrupt source. The arbitration
ranking determines the order in which interrupts are pro-
cessed if more than one interrupt of the same priority
occurs simultaneously.
INTERRUPTS
The XA supports 38 vectored interrupt sources. These
include 9 maskable event interrupts, 7 exception inter-
rupts, 16 trap interrupts, and 7 software interrupts. The
maskable interrupts each have 8 priority levels and may
be globally and/or individually enabled or disabled.
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MX10EXA
Table 8. Interrupt Vectors
EXCEPTION/TRAPS PRECEDENCE
DESCRIPTION
VECTORADDRESS
0000-0003
ARBITRATIONRANKING
Reset (h/w, watchdog, s/w)
Breakpoint (h/w trap 1)
Trace (h/w trap 2)
0 (High)
0004-0007
1
1
1
1
1
1
0008-000B
Stack Overflow (h/w trap 3)
Divide by 0 (h/w trap 4)
User RETI (h/w trap 5)
TRAP 0-15 (software)
000C-000F
0010-0013
0014-0017
0040-007F
EVENT INTERRUPTS
DESCRIPTION
FLAG BIT
VECTOR
ARBITRATION
ADDRESS
0080-0083
0084-0087
0088-008B
008C-008F
ENABLE BIT INTERRUPT PRIORITY
RANKING
External interrupt 0 lE0
Timer 0 interrupt TF0
External interrupt 1 IE1
EX0
ET0
EX1
ET1
ET2
ERI0
ETI0
ERI1
ETI1
lPA0.2-0 (PX0)
IPA0.6-4 (PT0)
IPA1.2-0 (PX1)
lPA1.6-4 (PT1)
lPA2.2-0(PT2)
lPA4.2-0(PRIO)
lPA4.6-4 (PTIO)
lPA5.2-0(PRT1)
lPA5.6-4(PTI1)
2
3
4
5
6
7
8
9
10
Timer 1 interrupt
Timer 2 interrupt
Serial port 0 Rx
Serial port 0 Tx
Serial port 1 Rx
Serial port 1 Tx
TF1
TF2(EXF2) 0090-0093
RI.0
TI.0
RI.1
TI.1
00A0-00A3
00A4-00A7
00A8-00AB
OOAC-00AF
SOFTWARE INTERRUPTS
DESCRIPTION
FLAG BIT
VECTOR
ADDRESS
0100-0103
0104-0107
0108-010B
010C-010F
0110-0113
0114-0117
0118-011B
ENABLE BIT
SWE1
INTERRUPT PRIORITY
(fixed at 1)
Software interrupt 1
Software interrupt 2
Software interrupt 3
Software interrupt 4
Software interrupt 5
Software interrupt 6
Software interrupt 7
SWR1
SWR2
SWR3
SWR4
SWR5
SWR6
SWR7
SWE2
(fixed at 2)
SWE3
(fixed at 3)
SWE4
(fixed at 4)
SWES
SWE6
(fixed at 5)
(fixed at 6)
SWE7
(fixed at 7)
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MX10EXA
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
UNIT
°C
°C
V
Operating temperature under bias
Storage temperature range
-55 to + 125
-65 to + 150
0 to + 13.0
0.5 to VDD + 0.5V
15
Voltage on EA/VPP pin to VSS
Voltage on any other pin to VSS
Maximum IOL per I/O pin
V
mA
w
Power dissipation (based on package heat transfer limitations, not device
power consumption)
1.5
DC ELECTRICAL CHARACTERISTICS
VDD = 4.5V to 5.5V unless otherwise specified;
Tamb = 0 to + 70°C for commercial
= - 40OC to +85OC for industrial, unless otherwise specified.
Symbol PARAMETER
Supplies
TEST CONDITIONS
LIMITS
UNIT
MIN
TYP
MAX
IDD
Supply current operating
5.5V, 30 MHz
5.5V, 30 MHz
110
32
mA
mA
uA
uA
V
IID
Idle mode supply current
IPD
Power-down current
30
IPDI
VRAM
VIL
Power-down current
150
RAM-keep-alive voltage
RAM-keep-alive voltage
1.5
Input low voltage
-0.5
2.2
0.22VDD
V
VIH
VIH1
VIL1
VOL
VOH1
VOH2
CIO
IIL
Input high voltage, except XTAL1, RST
Input high voltage to XTAL1, RST
Input low voltage to XATL1, RST
Output low voltage all ports, ALE, PS EN3
Output high voltage all ports, ALE, PSEN1
At 5.0V
V
At 5.0V
0.8VDD
V
At 5.0V
0.12VDD
0.5
IOL=3.2mA, VDD=5.0V
V
IOH=-100uA, VDD=4.5V
2.4
2.4
V
Output high voltage, ports P0-3, ALE, PSEN2 IOH=3.2mA, VDD=4.5V
V
Input/Output pin capacitance
15
pF
uA
uA
uA
Logical 0 input current, P0-36
VIN = 0.45V
VIN = VIL OR VIH
At 5.5V
-25
-75
+10
-650
ILI
Input leakage current, P0-35
ITL
Logical 1 to 0 transition current all ports4
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MX10EXA
NOTES:
1.Ports in Quasi bi-directional mode with weak pull-up (applies to ALE, PSEN only during RESET).
2.Ports in Push-Pull mode, both pull-up and pull-down assumed to be same strength.
3.In all output modes.
4.Port pins source a transition current when used in quasi-bidirectional mode and externally driven from 1 to 0. This
current is highest when VIN is approximately 2V.
5.Measured with port in high impedance output mode.
6.Measured with port in quasi-bidirectional output mode.
7.Load capacitance for all outputs=80pF
8.Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin:
Maximum IOL per 8-bit port:
1 5mA (*NOTE: This is 85°C specification for VDD= 5V.)
26mA
Maximum total IOL for all output: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current
greater than the listed test conditions.
Specifications subject to change without notice, contact your sales representatives for the most update information.
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MX10EXA
AC ELECTRICAL CHARACERISTICS (5V)
VDD = 4.5V to 5.5V; Tamb = 0 to +70°C for commercial - 40OC to +85OC for Industrial
SYMBOL FIGURE
External Clock
PARAMETER
VARIABLE CLOCK
UNIT
MIN
MAX
fC
26
26
26
26
26
26
Oscillator frequency
Clock period and CPU timing cycle
Clock high time
0
30
MHz
ns
tC
1/ fC
tCHCX
tCLCX
tCLCH
tCHCL
tC * 0.57
tC * 0.47
ns
Clock low time
ns
Clock rise time
5
5
ns
Clock fall time
ns
Address Cycle
tCRAR
tLHLL
tAVLL
tLLAX
25
20
20
20
Delay from clock rising edge to ALE rising edge
ALE pulse width (programmable)
5
46
ns
ns
ns
ns
(V1 * tC)-6
(V1 * tC)-12
(tC/2)-10
Address valid to ALE de-asserted (set-up)
Address hold after ALE de-asserted
Code Read Cycle
tPLPH
tLLPL
tAVIVA
20
20
20
PSEN pulse width
(V2 * tC )-10
(tC/2)-7
ns
ns
ALE de-asserted to PSEN asserted
Address valid to instruction valid, ALE cycle
(access time)
(V3 * tC)-36 ns
(V4 * tC)-29 ns
(V2 * tC)-29 ns
ns
tAVIVB
tCPLIV
tPXIX
tPXIZ
tIXUA
21
20
20
20
20
Address valid to instruction valid, non-ALE cycle
(access time)
PSEN asserted to instruction valid
(enable time)
Instruction hold after PSEN de-asserted
0
0
Bus 3-State after PSEN de-asserted
(disable time)
tC - 8
ns
ns
Hold time of unlatched part of address after
instruction latched
Data Read Cycle
tRLRH
tLLRL
22
22
22
RD pulse width
(V7 * tC )-10
(tC/2)-7
ns
ns
ALE de-asserted to RD asserted
Address valid to data input valid, ALE cycle
(access time)
tAVDVA
(V6 * tC)-36 ns
tAVDVB
23
Address valid to data input valid, non-ALE cycle
(access time)
(V5 * tC)-29 ns
tRLDV
tRHDX
tRHDZ
tDXUA
22
22
22
22
RD low to valid data in, enable time
Data hold time after RD de-asserted
Bus 3-State after RD de-asserted (disable time)
Hold time of unlatched part of address after
data latched
(V7 * tC)-29 ns
ns
0
0
tC-8
ns
ns
Specifications subject to change without notice, contact your sales representatives for the most update information.
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MX10EXA
SYMBOL FIGURE
Data Write Cycle
PARAMETER
VARIABLE CLOCK
UNIT
MIN
MAX
tWLWH
tLLWL
24
24
24
24
24
WR pulse width
(V8 * tC)-10
ns
ALE falling edge to WR asserted
(V12 * tC)-10
ns
ns
ns
ns
tQVWX
tWHQX
tAVWL
Data valid before WR asserted (data setup time) (V13 * tC)-22
Data hold time after WR de-asserted (Note 6) (V11 * tC)-5
Address valid to WR asserted (address setup time) (V9 * tC)-22
(Note 5)
tUAWH
24
Hold time of unlatched part of address after WR
is de-asserted
(V11 * tC)-7
(V10 * tC)-5
ns
Wait Input
tWTH
25
25
WAIT stable after bus strobe
(RD,WR,or PSEN) asserted
WAIT hold after bus strobe
(RD,WR,or PSEN) asserted
(V10*tC)-30
ns
ns
tWTL
NOTES:
1.Load capacitance for all outputs = 80p F.
2.Variables V1 through V13 reflect programmable bus timing, which is programmed via the Bus Timing registers
(BTRH and BTRL). Refer to the XA User Guide for details of the bus timing settings.
V1) This variable represents the programmed width of the ALE pulse as determined by the ALEW bit in the BTRL
register. V1 = 0.5 if the ALEW bit = 0, and 1.5 if the ALEW bit = 1.
V2) This variable represents the programmed width of the PSEN pulse as determined by the CR1 and CR0 bits
or the CRAl, CRA0, and ALEW bits in the BTRL register.
- For a bus cycle with no ALE, V2 = l if CR1/0 = 00, 2 if CR1/0 = 01, 3 if CR1/0 = 10, and 4 if CR1/0 = 11. Note that
during burst mode code fetches, PSENdoes not exhibit transitions at the boundaries of bus cycles. V2 still applies
for the purpose of determining peripheral timing requirements.
- For a bus cycle with an ALE, V2 = the total bus cycle duration (2 if CRA1/0 = 00, 3 if CRA1/0 = 01, 4 if CRA1/0 =
10, and 5 if CRA1/0 = 11) minus the number of clocks used by ALE (V1 + 0.5).
Example: If CRA1/0 = 10 and ALEW = 1, the V2 = 4 - (1.5 + 0.5) = 2.
V3) This variable represents the programmed length of an entire code read cycle with ALE. This time is deter
mined by the CRA1 and CRA0 bits in the BTRL register. V3 = the total bus cycle duration (2 if CRA1/0 =00,
3 if CRA1/0 =01, 4 if CRA1/0 = 10, and 5 it CRA1/0 = 11).
V4) This variable represents the programmed length of an entire code read cycle with no ALE. This time is
determined by the CR1 and CR0 bits in the BTRL register. V4 = 1 if CR1/0 = 00,2 if CR1/0= 01,3 if CR1/0= 10,
and 4 if CR1/0 = 11.
V5) This variable represents the programmed length of an entire data read cycle with no ALE. this time is
determined by the DR1 and DR0 bits in the BTRH register. V5 = l if DR1/0 = 00,2 if DR1/0 = 01,3 if DR1/0 =
10, and 4 it DR1/0 = 11.
V6) This variable represents the programmed length of an entire data read cycle withALE. The time is determined
by the DRA1 and DRA0 bits in the BTRH register. V6 = the total bus cycle duration (2 if DRA1/0 = 00, 3 if
DRA1/0 = 01, 4 if DRA1/0 = 10, and 5 if DRA1/0 = 11).
V7) This variable represents the programmed width of the RD pulse as determined by the DR1 and DR0 bits or
the DRA1, DRA0 in the BTRH register, and the ALEW bit in the BTRL register. Note that during a 16-bit
operation on an 8-bit external bus, RD remains low and does not exhibit a transition between the first and
second byte bus cycles. V7still applies for the purpose of determining peripheral timing requirements. The
timing for the first byte is for a bus cycle with ALE, the timing for the second byte is for a bus cycle with no
ALE.
Specifications subject to change without notice, contact your sales representatives for the most update information.
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MX10EXA
- For a bus cycle with no ALE, V7 = l if DR1/0 = 00, 2 if DR1/0 = 01,3 if DR1/0 = 10, and 4 if DR1/0 = 11.
- For a bus cycle with an ALE, V7 = the total bus cycle duration (2 it DR1/0 = 00, 3 if DRA1/0 = 01, 4 if DRA1/0 =
10, and S if DRA1/0 = 11) minus the number of clocks used by ALE (V1 + 0.5).
Example: If DRA1/0 = 00 and ALEW = 0, then V7=2 - (0.5 + 0.5) = 1.
V8) This variable represents the programmed width of the WRL and/or WRH pulse as determined by the WM1 bit
in the BTRL register. V8 1 if WM1 =0,and2 if WM1 =1.
V9) This variable represents the programmed address setup time for a write as determined by the data write
cycle duration (defined by DW1 and DW0 or the DWA1 and DWA0 bits in the BTRH register), the WM0 bit in
the BTRL register, and the value of V8.
- For a bus cycle with anALE, V9 = the total bus write cycle duration (2 ifDWA1/0 = 00, 3 ifDWA1/0 = 01, 4 ifDWA1/
0 = 10, and 5 if DWA1/0= 11) minus the number of clocks used by the WRL and/or WRH pulse (V8), minus the
number of clocks used by data hold time (0 if WM0= 0 and l iF WM0 = 1).
Example: If DWA1/0=10,WM0= 1, and WM1 =1, then V9=4-1 -2=1.
- For a bus cycle with no ALE, V9 = the total bus cycle duration (2 if DW1/0 = 00, 3 if OW1/0 = 01, 4 if DW1/0 = 10,
and 5 if DW1/0 = 11) minus the number of clocks used by the WRL and/or WRH pulse (V8), minus the number of
clocks used by data hold time (0 if WM0 = 0 and l if WM0 = 1).
Example: If DW1/0=11, WM0=1, and WM1 =0, then V9=5-1 -1=3.
V10) This variable represents the length of a bus strobe for calculation of WAIT setup and hold times. The strobe
may be RD (for data read cycles), WRL and/or WRH (for data write cycles), or PSEN (for code read cycles),
depending on the type of bus cycle being widened by WAIT. V10 = V2 for WAIT associated with a code read
cycle using PSENV10 = V8 for a data write cycle using WRL and/or WRH. V10 = V7-1 for a data read cycle
using RD. This means that a single clock data read cycle cannot be stretched using WAIT. If WAIT is used
to vary the duration of data read cycles, the RD strobe width must be set to be at least twoclocks in dura-
tion. Also see Note 4.
V11) This variable represents the programmed write hold time as determined by the WM0 bit in the BTRLregister.
V11=0 if the WM0 bit=0, and 1 if the WM0 bit=1.
V12) This variable represents the programmed period between the end of the ALE pulse and the beginning of the
WRL and/or WRH pulse as determined by the data write cycle duration (defined by theDWA1 andDWA0 bits
in the BTRH register), the WM0 bit in the BTRL register, and the values of V1 and V8. V12= the total bus cycle
duration (2 if DWA1/0 =00, 3 if DWA1/0 = 01, 4 it DWA1/0 = 10, and 5 it DWA1/0 = 11) minus the number of
clocks used by the WRL and/or WRH pulse (V8), minus the number of clocks used by data hold time (0 if
WM0 = 0 and lit WM0 = 1), minus the width of the ALE pulse (V1).
Example:If DWA1/0= 11,WM0=1,WM1 =0, and ALEW =1, then V12=5-1 -1-1.5=1.5.
V13) This variable represents the programmed data setup time for a write as determined by the data write cycle
duration (defined by DW1 and DW0 or the DWA1 and DWA0 bits in the BTRH register), the WM0 bit in the
BTRL register, and the values of V1 and V8.
- For a bus cycle with an ALE, V13 = the total bus cycle duration (2 if DWA1/0 = 00, 3 it DWA1/0 = 01, 4 if
DWA1/0 = 10, and 5 if DWA1/0 = 11) minus the number of clocks used by the WRL and/or WRH pulse (V8),
minus the number of clocks used by data hold time (0 if WM0 = 0 and 1 if WM0 = 1), minus the number of
clocks used by ALE (V1 + 0.5).
Example:IfDWA1/0= 11, WM0=1, WM1 =1, and ALEW=0,then V13=5-1-2-1= 1.
-For a bus cycle with no ALE, V13 = the total bus cycle duration (2 if DW1/0 = 00, 3 if DW1/0 = 01, 4 it DW1/
0 = 10, and 5 ifDW1/0= 11) minus the number of clocks used by the WRL and/or WRH pulse (V8), minus the
number of clocks used by data hold time (0 if WM0 = 0 and 1 if WM0 = 1).
Example:IfDW1/0=01, WM0=1, and WM1 =0, then V13=3 -1 -1=1.
3. Not all combinations of bus timing configuration values result in valid bus cycles. Please refer to the XA User Guide
section on the External Bus for details.
4.When code is being fetched for execution on the external bus, a burst mode fetch is used that does not have PSEN
edges in every fetch cycle. Thus, it WAIT is used to delay code fetch cycles, a change in the low order address lines
must be detected to locate the beginning of a cycle. This would be A3-A0 for an 8-bit bus, and A3-A1 for a 16-bit
bus. Also, a 16-bit data read operation conducted on a 8-bit wide bus similarly does not include two separate RD
strobes. So, a rising edge on the low order address line (A0) must be used to trigger a WAIT in the second halt of
such a cycle.
Specifications subject to change without notice, contact your sales representatives for the most update information.
P/N:PM0625
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MX10EXA
5.This parameter is provided for peripherals that have the data clocked in on the tailing edge of the WR strobe. This
is not usually the case, and in most applications this parameter is not used.
6.Please note that the XA requires that extended data bus hold time (WM0 = 1) to be used with external bus write
cycles.
7.Applies only to an external clock source, not when a crystal or ceramic resonator is connected to the XTAL1 and
XTA12 pins.
t
LHLL
ALE
t
AVLL
t
LLPL
t
PLPH
t
PLIV
PSEN
t
PXIZ
t
LLAX
t
PXIX
MULTIPLEXED
ADDRESS AND DATA
A4-A11 or A4-A19
INSTR IN*
t
AVIVA
t
IXUA
UNMULTIPLEXED
ADDRESS
A0 or A1-3, A12-19
* INSTR IN is either D0-D7 or D0-D15, depending on the bus width (8 or 16 bits).
Figure 20. External Program Memory Read Cycle (ALE Cycle)
ALE
PSEN
MULTIPLEXED
ADDRESS AND DATA
A4-A11 or A4-A19
INSTR IN*
t
AVIVB
UNMULTIPLEXED
ADDRESS
A0 or A1-3, A12-19
A0 or A1-A3, A12-19
* INSTR IN is either D0-D7 or D0-D15, depending on the bus width (8 or 16 bits).
Figure 21. External Program Memory Read Cycle (Non-ALE Cycle)
Specifications subject to change without notice, contact your sales representatives for the most update information.
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MX10EXA
ALE
RD
t
LLRL
t
RLRH
t
RHDZ
t
AVLL
t
LLAX
t
RLDV
t
RHDX
MULTIPLEXED
ADDRESS AND DATA
A4-A11 or A4-A19
INSTR IN*
t
AVDVA
t
DXUA
UNMULTIPLEXED
ADDRESS
A0 or A1-A3, A12-19
* INSTR IN is either D0-D7 or D0-D15, depending on the bus width (8 or 16 bits).
Figure 22. External Data Memory Read Cycle (ALE Cycle)
ALE
RD
MULTIPLEXED
ADDRESS AND DATA
A4-A11
D0-D7
DATA IN*
t
AVDVB
UNMULTIPLEXED
ADDRESS
A0-A3,A12-A19
A0-A3, A12-A19
Figure 23. External Data Memory Read Cycle (Non-ALE Cycle)
Specifications subject to change without notice, contact your sales representatives for the most update information.
P/N:PM0625
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MX10EXA
ALE
t
LLWL
t
WLWH
WRL or WRH
t
WHQX
t
AVLL
t
QVWX
t
LLAX
MULTIPLEXED
ADDRESS AND DATA
A4-A11 or A4-A15
DATA OUT*
t
UAWH
t
AVWL
UNMULTIPLEXED
ADDRESS
A0 or A1-A3, A12-19
* INSTR IN is either D0-D7 or D0-D15, depending on the bus width (8 or 16 bits).
Figure 24. External Data Memory Write Cycle
XTAL1
ALE
t
CRAR
ADDRESS BUS
WAIT
t
WTH
BUS STROBE
(WRL,WRH,
RD,OR PSEN)
t
WTL
(The dashed line shows the strobe without WAIT.)
Figure 25. WAIT Signal Timing
Specifications subject to change without notice, contact your sales representatives for the most update information.
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MX10EXA
VDD-0.5
0.45V
0.7VDD
0.2VDD-0.1
tCHCX
tCHCH
tCLCX
tCHCL
tC
Figure 26. External Clock Drive
VDD-0.5
0.45V
0.2VDD+0.9
0.2VDD-0.1
NOTE:
AC inputs during testing are driven at VDD-0.5 for a logic "1" and 0.45V for logic "0".
Timing measurements are made at the 50% point of transitions.
VOH-0.1V
VLOAD+0.1V
TIMING REFERENCE
POINTS
VLOAD
NOTE:
VLOAD-0.1V
VOL+0.1V
For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs,
and begins to float when a 100mV change from the loaded VOH/VOL level occurs.
IOH/IOL > ±20mA
Specifications subject to change without notice, contact your sales representatives for the most update information.
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MX10EXA
VDD
VDD
VDD
VDD
EA
VDD
RST
EA
RST
XTAL2
XTAL1
VSS
(NC)
CLOCK
SIGNAL
XTAL2
XTAL1
VSS
(NC)
CLOCK
SIGNAL
Figure 29. IDD Test Condition, Active Mode
All other pins are disconnected
Figure 30. IDD Test Condition, Idle Mode
All other pins are disconnected
120
100
80
MAX.IDD (ACTIVE)
CURRENT(mA)
60
40
20
MAX.IDD (IDLE)
0
5
10
15
20
25
30
FREQUENCY (MHz)
Figure 31. IDD VS. Frequency
Valid only within frequency specification of the device under test.
Specifications subject to change without notice, contact your sales representatives for the most update information.
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MX10EXA
VDD-0.5
0.45V
0.7VDD
0.2VDD-0.1
t
CHCX
t
CLCX
t
CLCH
t
CHCL
t
CL
Figure 32. Clock Signal Waveform for IDD Tests in Active and Idle Modes
tCLCH=
t
CHCL=5ns
VDD
VDD
EA
VDD
RST
XTAL2
XTAL1
VSS
(NC)
Figure 33. IDD Test Condition, Power Down Mode
All other pins are disconnected. VDD=2V to 5.5V
Specifications subject to change without notice, contact your sales representatives for the most update information.
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MX10EXA
PACKAGE INFORMATION
44-PIN PLASTIC LEADED CHIP CARRIER(PLCC)
A
B
1
6
44
40
ITEM
A
MILLIMETERS
17.53 ± .12
16.59 ± .12
16.59 ± .12
17.53 ± .12
1.95
INCHES
.690 ± .005
.653 ± .005
.653 ± .005
.690 ± .005
.077
7
39
B
C
D
E
13
C
D
33
29
F
4.70 max.
2.55 ± .25
.51 min.
.185 max
.100 ± .010
.020 min.
G
H
I
17
1.27 [Typ.]
.71 ± .10
.46 ± .10
15.50 ± .51
.63 R
.050 [Typ.]
.028 ± .004
.018 ± .004
.610 ± .020
.025 R
J
18
28
23
K
E
L
N
F
G
H
M
N
M
I
.25 [Typ.]
.010 [Typ.]
J
K
L
Specifications subject to change without notice, contact your sales representatives for the most update information.
P/N:PM0625
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53
MX10EXA
LQFP44 : plastic low profile quad flat package ; 44 leads ; body 10 x 10 x 1.4mm
Specifications subject to change without notice, contact your sales representatives for the most update information.
P/N:PM0625
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54
MX10EXA
MACRONIX INTERNATIONALCO., LTD .
Headquarters:
TEL:+886-3-578-6688
FAX:+886-3-563-2888
Europe Office :
TEL:+32-2-456-8020
FAX:+32-2-456-8021
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Kawasaki Office :
TEL:+81-44-246-9100
FAX:+81-44-246-9105
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TEL:+81-6-4807-5460
FAX:+81-6-4807-5461
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TEL:+886-2-2509-3300
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MACRONIX AMERICA, INC.
TEL:+1-408-262-8887
FAX:+1-408-262-8810
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
54
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