MX25L1605AMC-12_技术文档

MX25L1605A

DATASHEET

The MX25L1605A product will be phase-out, and is not recommended for new

design. The MX25L1605A will be migrated to MX25L1605D, which is a functional

compatible product. Please refer to MX25L1605D datasheet for new design.

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MX25L1605A

16M-BIT [x 1] CMOS SERIAL FLASH

The MX25L1605A product will be phase-out, and is not recommended for new

design. The MX25L1605A will be migrated to MX25L1605D, which is a functional

compatible product. Please refer to MX25L1605D datasheet for new design.

FEATURES

GENERAL

• Serial Peripheral Interface (SPI) compatible -- Mode 0 and Mode 3

• 16,777,216 x 1 bit structure

• 512 Equal Sectors with 4K byte each

- Any Sector can be erased individually

• 32 Equal Blocks with 64K byte each

- Any Block can be erased individually

• Single Power Supply Operation

- 2.7 to 3.6 volt for read, erase, and program operations

• Latch-up protected to 100mA from -1V to Vcc +1V

• Low Vcc write inhibit is from 1.5V to 2.5V

PERFORMANCE

• High Performance

- Fast access time: 85MHz serial clock (15pF + 1TTL Load) and 66MHz serial clock (30pF + 1TTL Load)

- Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)

-Fasterasetime:60ms(typ.)and120ms(max.)/sector(4K-bytepersector);1s(typ.)and2s(max.)/block(64K-byteper

block);14s(typ.)and30s(max.)/chip(16Mb)

• Low Power Consumption

- Low active read current: 12mA(max.) at 85MHz, 8mA(max.) at 66MHz and 4mA(max.) at 33MHz

- Low active programming current: 15mA (max.)

- Low active erase current: 15mA (max.)

- Low standby current: 20uA (max.)

-Deeppower-downmode1uA(typical)

• Minimum 100,000 erase/program cycles

SOFTWAREFEATURES

• Input Data Format

- 1-byte Command code

• Block Lock protection

-TheBP0~BP2statusbitdefinesthesizeoftheareatobesoftwareprotectedagainstProgramandEraseinstructions.

• Auto Erase and Auto Program Algorithm

- Automatically erases and verifies data at selected sector

- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the

program pulse widths (Any page to be programed should have page in the erased state first)

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MX25L1605A

• Status Register Feature

• Electronic Identification

- JEDEC 2-byte Device ID

- RES command, 1-byte Device ID

HARDWAREFEATURES

• SCLK Input

- Serial clock input

• SI Input

- Serial Data Input

• SO Output

- Serial Data Output

• WP# pin

- Hardware write protection

• HOLD# pin

- pause the chip without diselecting the chip

• PACKAGE

- 16-pin SOP (300mil)

- 8-land SON (8x6mm)

- 8-pin SOP (200mil)

- All Pb-free devices are RoHS Compliant

GENERAL DESCRIPTION

The MX25L1605A is a CMOS 16,777,216 bit serial Flash memory, which is configured as 2,097,152 x 8 internally. The

MX25L1605Afeaturesaserialperipheralinterfaceandsoftwareprotocolallowingoperationonasimple3-wirebus. The

threebussignalsareaclockinput(SCLK), aserialdatainput(SI), andaserialdataoutput(SO). SPIaccesstothedevice

is enabled by CS# input.

The MX25L1605A provides sequential read operation on whole chip.

After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified

page or sector/block locations will be executed. Program command is executed on page (256 bytes) basis, and erase

command is executes on chip or sector(4K-bytes) or block(64K-bytes).

To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read

command can be issued to detect completion status of a program or erase operation via WIP bit.

When the device is not in operation and CS# is high, it is put in standby mode and draws less than 20uA DC current.

The MX25L1605A utilizes MXIC's proprietary memory cell, which reliably stores memory contents even after 100,000

program and erase cycles.

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MX25L1605A

PIN CONFIGURATIONS

16-PIN SOP (300mil)

PIN DESCRIPTION

SYMBOL DESCRIPTION

CS#

SI

Chip Select

1

2

3

4

5

6

7

8

SCLK

SI

HOLD#

VCC

NC

16

15

14

13

12

11

10

9

Serial Data Input

Serial Data Output

Clock Input

NC

SO

NC

SCLK

HOLD#

GND

WP#

CS#

SO

Hold, to pause the device without

deselecting the device

+ 3.3V Power Supply

Ground

8-LANDSON(8x6mm)

VCC

GND

1

2

3

4

VCC

HOLD#

SCLK

SI

CS#

SO

8

7

6

5

WP#

GND

8-PIN SOP (200mil)

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MX25L1605A

BLOCK DIAGRAM

Address

Generator

Memory Array

Page Buffer

Data

Register

SI

Y-Decoder

SRAM

Buffer

Output

Buffer

Sense

Amplifier

Mode

Logic

State

Machine

CS#

HV

Generator

SO

SCLK

Clock Generator

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MX25L1605A

DATA PROTECTION

TheMX25L1605Aisdesignedtoofferprotectionagainstaccidentalerasureorprogrammingcausedbyspurioussystem

levelsignalsthatmayexistduringpowertransition. Duringpowerupthedeviceautomaticallyresetsthestatemachinein

the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after

successfulcompletionofspecificcommandsequences.Thedevicealsoincorporatesseveralfeaturestopreventinadvertent

write cycles resulting from VCC power-up and power-down transition or system noise.

•

Power-on reset and tPUW: to avoid sudden power switch by system power supply transition, the power-on reset and

tPUW (internal timer) may protect the Flash.

• Validcommandlengthchecking:Thecommandlengthwillbecheckedwhetheritisatbytebaseandcompletedonbyte

boundary.

• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other

command to change data. The WEL bit will return to reset stage under following situation:

-Power-up

- Write Disable (WRDI) command completion

- Write Status Register (WRSR) command completion

- Page Program (PP) command completion

- Sector Erase (SE) command completion

- Block Erase (BE) command completion

- Chip Erase (CE) command completion

•

Software Protection Mode (SPM): by using BP0-BP2 bits to set the part of Flash protected from data change.

HardwareProtectionMode(HPM):byusingWP#goinglowtoprotecttheBP0-BP2bitsandSRWDbitfromdatachange.

DeepPowerDownMode:Byenteringdeeppowerdownmode,theflashdevicealsoisunderprotectedfromwritingall

commandsexceptReleasefromdeeppowerdownmodecommand(RDP)andReadElectronicSignaturecommand

(RES).

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MX25L1605A

Table 1. Protected Area Sizes

Statusbit

ProtectionArea

MX25L1605A

BP2

0

BP1

0

BP0

0

0(none)

None

0

1

1 (1 block)

2 (2 blocks)

3 (4 blocks)

4 (8 blocks)

5 (16 blocks)

6 (All)

Upper 32nd (Block 31)

Upper sixteenth (two blocks: 30 and 31)

Upper eighth (four blocks: 28 to 31)

Upper quarter (eight blocks: 24 to 31)

Upper half (sixteen blocks: 16 to 31)

All

0

1

0

1

0

1

0

1

0

1

7 (All)

All

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MX25L1605A

HOLD FEATURE

HOLD#pinsignalgoeslowtoholdanyserialcommunicationswiththedevice.TheHOLDfeaturewillnotstoptheoperation

of write status register, programming, or erasing in progress.

TheoperationofHOLDrequiresChipSelect(CS#)keepinglowandstartsonfallingedgeofHOLD#pinsignalwhileSerial

Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start until Serial Clock

signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Serial Clock(SCLK) signal is

being low( if Serial Clock signal is not being low, HOLD operation will not end until Serial Clock being low), see Figure 1.

Figure 1. Hold Condition Operation

CS#

SCLK

HOLD#

Hold

Condition

(standard)

Condition

(non-standard)

TheSerialDataOutput(SO)ishighimpedance, bothSerialDataInput(SI)andSerialClock(SCLK)aredon'tcareduring

the HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of the device.

To re-start communication with chip, the HOLD# must be at high and CS# must be at low.

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MX25L1605A

Table 2. COMMAND DEFINITION

COMMAND WREN

WRDI

(write

RDID

RDSR

WRSR

READ

FastRead

(fastread

data)

(byte)

(write

(readident- (readstatus

(writestatus (readdata)

register)

Enable)

06 Hex

disable) ification)

04 Hex 9F Hex

register)

1st

05 Hex

01 Hex

03 Hex

AD1

0B Hex

AD1

2nd

3rd

AD2

4th

AD3

5th

x

Action

sets the

(WEL)

write

reset the output the

to read out

to write new

n bytes

(WEL)

write

manufacturer the status

ID and 2-byte register

device ID

values to the readout

status register until

CS# goes

enable

latch bit

enable

latch bit

high

COMMAND SE

BE

CE

PP

DP

RDP

RES

REMS (Read

Electronic

Manufacturer

& Device ID)

90 Hex

(byte)

(Sector

(Block

Erase)

(Chip

Erase)

(Page

(Deep

(Release

(Read

Electronic

ID)

Erase)

Program) Power

Down)

fromDeep

Power-down)

1st

20 Hex

52 or

60 or

02 Hex

B9 Hex AB Hex

AB Hex

D8 Hex C7 Hex

2nd

3rd

AD1

AD2

AD3

AD1

AD2

AD3

AD1

AD2

AD3

x

4th

ADD(1)

5th

Action

Output the

manufacturer

ID and device

ID

(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first.

(2) It is not recommended to adopt any other code which is not in the above command definition table.

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MX25L1605A

Table 3. Memory Organization

Bolck

31

Sector

511

Address Range

1FF000h 1FFFFFh

Bolck

14

Sector

239

Address Range

0EF000h 0EFFFFh

496

495

1F0000h 1F0FFFh

1EF000h 1EFFFFh

224

223

0E0000h 0E0FFFh

0DF000h 0DFFFFh

30

29

28

27

26

25

24

23

22

13

12

11

10

9

480

479

1E0000h 1E0FFFh

1DF000h 1DFFFFh

208

207

0D0000h 0D0FFFh

0CF000h 0CFFFFh

464

463

1D0000h 1D0FFFh

1CF000h 1CFFFFh

192

191

0C0000h 0C0FFFh

0BF000h 0BFFFFh

448

447

1C0000h 1C0FFFh

1BF000h 1BFFFFh

176

175

0B0000h 0B0FFFh

0AF000h 0AFFFFh

432

431

1B0000h 1B0FFFh

1AF000h 1AFFFFh

160

159

0A0000h 0A0FFFh

09F000h 09FFFFh

416

415

1A0000h 1A0FFFh

19F000h 19FFFFh

144

143

090000h 090FFFh

08F000h 08FFFFh

8

400

399

190000h 190FFFh

18F000h 18FFFFh

128

127

080000h 080FFFh

07F000h 07FFFFh

7

384

383

180000h 180FFFh

17F000h 17FFFFh

112

111

070000h 070FFFh

06F000h 06FFFFh

368

367

170000h 170FFFh

16F000h 16FFFFh

6

5

96

95

060000h 060FFFh

05F000h 05FFFFh

352

351

160000h 160FFFh

15F000h 15FFFFh

80

79

050000h 050FFFh

04F000h 04FFFFh

21

20

336

335

150000h 150FFFh

14F000h 14FFFFh

4

3

2

1

64

63

040000h 040FFFh

03F000h 03FFFFh

320

319

140000h 140FFFh

13F000h 13FFFFh

19

48

47

030000h 030FFFh

02F000h 02FFFFh

304

303

130000h 130FFFh

12F000h 12FFFFh

18

32

31

020000h 020FFFh

01F000h 01FFFFh

288

287

120000h 120FFFh

11F000h 11FFFFh

17

16

15

010000h 010FFFh

00F000h 00FFFFh

272

271

110000h 110FFFh

10F000h 10FFFFh

16

4

3

2

1

0

004000h 004FFFh

003000h 003FFFh

002000h 002FFFh

001000h 001FFFh

000000h 000FFFh

256

255

100000h 100FFFh

0FF000h 0FFFFFh

0

15

240

0F0000h 0F0FFFh

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MX25L1605A

DEVICE OPERATION

1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation.

2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode until

next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z.

3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next

CS# rising edge.

4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK. The

difference of SPI mode 0 and mode 3 is shown as Figure 2.

5. Forthefollowinginstructions:RDID,RDSR,READ,FAST_READ,RESandREMStheshifted-ininstructionsequence

is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following

instructions:WREN, WRDI, WRSR, SE, BE, CE, PP, RDPandDPtheCS#mustgohighexactlyatthebyteboundary;

otherwise, the instruction will be rejected and not executed.

6. DuringtheprogressofWriteStatusRegister,Program,Eraseoperation,toaccessthememoryarrayisneglectedand

not affect the current operation of Write Status Register, Program, Erase.

Figure 2. SPI Modes Supported

CPOL CPHA

shift in

shift out

SCLK

(SPI mode 0)

(SPI mode 3)

0

1

0

1

SI

MSB

SO

MSB

Note:

CPOL indicates clock polarity of SPI master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not

transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which SPI mode is

supported.

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MX25L1605A

COMMAND DESCRIPTION

(1) Write Enable (WREN)

The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, SE, BE,

CE, and WRSR, which are intended to change the device content, should be set every time after the WREN instruction

setting the WEL bit.

The sequence of issuing WREN instruction is: CS# goes low-> sending WREN instruction code-> CS# goes high. (see

Figure11)

(2) Write Disable (WRDI)

The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.

ThesequenceofissuingWRDIinstructionis:CS#goeslow->sendingWRDIinstructioncode->CS#goeshigh.(seeFigure

12)

The WEL bit is reset by following situations:

-Power-up

- Write Disable (WRDI) instruction completion

- Write Status Register (WRSR) instruction completion

- Page Program (PP) instruction completion

- Sector Erase (SE) instruction completion

- Block Erase (BE) instruction completion

- Chip Erase (CE) instruction completion

(3) Read Identification (RDID)

The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC

Manufacturer ID is C2(hex), the memory type ID is 20(hex) as the first-byte device ID, and the individual device ID of

second-byte ID is: 15(hex).

ThesequenceofissuingRDIDinstructionis:CS#goeslow->sendingRDIDinstructioncode->24-bitsIDdataoutonSO

-> to end RDID operation can use CS# to high at any time during data out. (see Figure. 13)

While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of

program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.

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MX25L1605A

(4) Read Status Register (RDSR)

The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in

program/erase/writestatusregistercondition)andcontinuously. ItisrecommendedtochecktheWriteinProgress(WIP)

bit before sending a new instruction when a program, erase, or write status register operation is in progress.

ThesequenceofissuingRDSRinstructionis:CS#goeslow->sendingRDSRinstructioncode->StatusRegisterdataout

on SO (see Figure. 14)

The definition of the status register bits is as below:

WIP bit. TheWriteinProgress(WIP)bit, avolatilebit, indicateswhetherthedeviceisbusyinprogram/erase/writestatus

registerprogress.WhenWIPbitsetsto1,whichmeansthedeviceisbusyinprogram/erase/writestatusregisterprogress.

When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle.

WELbit.TheWriteEnableLatch(WEL)bit, avolatilebit, indicateswhetherthedeviceissettointernalwriteenablelatch.

When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/erase/write

status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept

program/erase/writestatusregisterinstruction.

BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area(as defined

intable1)ofthedevicetoagainsttheprogram/eraseinstructionwithouthardwareprotectionmodebeingset.Towritethe

Block Protect (BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits

define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip

Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed)

SRWDbit.TheStatusRegisterWriteDisable(SRWD)bit,non-volatilebit,isoperatedtogetherwithWriteProtection(WP#)

pinforprovidinghardwareprotectionmode. ThehardwareprotectionmoderequiresSRWDsetsto1andWP#pinsignal

is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for

execution and the SRWD bit and Block Protect bits (BP2, BP1, BP0) are read only.

bit 7

SRWD

bit 6

0

bit 5

0

bit 4

BP2

bit 3

BP1

bit 2

BP0

bit 1

bit 0

WIP

WEL

Status

the level of the level of the level of

(writeenable (writeinprogress

latch) bit)

RegisterWrite

Protect

protected

block

protected

block

protected

block

1= status

registerwrite

disable

(note1)

1=writeenable 1=writeoperation

0=notwrite

enable

0=not in write

operation

Note: 1. See the table "Protected Area Sizes".

2. Theendurancecyclesofprotectbitsare100,000cycles;however, thetWtimeoutspecofprotectbitsisrelaxed

as tW = N x 15ms (N is a multiple of 10,000 cycles, ex. N = 2 for 20,000 cycles) after 10,000 cycles on those bits.

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MX25L1605A

(5) Write Status Register (WRSR)

The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write

Enable(WREN)instructionmustbedecodedandexecutedtosettheWriteEnableLatch(WEL)bitinadvance.TheWRSR

instructioncanchangethevalueofBlockProtect(BP2, BP1, BP0)bitstodefinetheprotectedareaofmemory(asshown

in table 1). The WRSR also can set or reset the Status Register Write Disable (SRWD) bit in accordance with Write

Protection (WP#) pin signal. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is

entered.

The sequence of issuing WRSR instruction is: CS# goes low-> sending WRSR instruction code-> Status Register data

on SI-> CS# goes high. (see Figure 15)

The WRSR instruction has no effect on b6, b5, b1, b0 of the status register.

TheCS#mustgohighexactlyatthebyteboundary;otherwise, theinstructionwillberejectedandnotexecuted. Theself-

timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress

(WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing,

and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset.

Table 4. Protection Modes

Mode

Status register condition

WP# and SRWD bit status

Memory

Status register can be written

in (WEL bit is set to "1") and

the SRWD, BP0-BP2

WP#=1 and SRWD bit=0, or

WP#=0 and SRWD bit=0, or

WP#=1 and SRWD=1

Software protection

mode(SPM)

The protected area cannot

be program or erase.

bits can be changed

The SRWD, BP0-BP2 of

status register bits cannot be

changed

Hardware protection

mode (HPM)

The protected area cannot

be program or erase.

WP#=0, SRWD bit=1

Note:

1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 1.

Astheabovetableshowing, thesummaryoftheSoftwareProtectedMode(SPM)andHardwareProtectedMode(HPM).

Software Protected Mode (SPM):

-

WhenSRWDbit=0,nomatterWP#isloworhigh,theWRENinstructionmaysettheWELbitandcanchangethevalues

of SRWD, BP2, BP1, BP0. The protected area, which is defined by BP2, BP1, BP0, is at software protected mode

(SPM).

-

WhenSRWDbit=1andWP#ishigh,theWRENinstructionmaysettheWELbitcanchangethevaluesofSRWD,BP2,

BP1, BP0. The protected area, which is defined by BP2, BP1, BP0, is at software protected mode (SPM)

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MX25L1605A

Note: If SRWD bit=1 but WP# is low, it is impossible to write the Status Register even if the WEL bit has previously been

set. It is rejected to write the Status Register and not be executed.

HardwareProtectedMode(HPM):

-

When SRWD bit=1, and then WP# is low (or WP# is low before SRWD bit=1), it enters the hardware protected mode

(HPM). The data of the protected area is protected by software protected mode by BP2, BP1, BP0 and hardware

protected mode by the WP# to against data modification.

Note:toexitthehardwareprotectedmoderequiresWP#drivinghighoncethehardwareprotectedmodeisentered.Ifthe

WP# pin is permanently connected to high, the hardware protected mode can never be entered; only can use software

protected mode via BP2, BP1, BP0.

(6) Read Data Bytes (READ)

Thereadinstructionisforreadingdataout.TheaddressislatchedonrisingedgeofSCLK,anddatashiftsoutonthefalling

edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically

increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single

READ instruction. The address counter rolls over to 0 when the highest address has been reached.

The sequence of issuing READ instruction is: CS# goes low-> sending READ instruction code-> 3-byte address on SI

-> data out on SO-> to end READ operation can use CS# to high at any time during data out. (see Figure. 16)

(7) Read Data Bytes at Higher Speed (FAST_READ)

The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of

each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location.

Theaddressisautomaticallyincreasedtothenexthigheraddressaftereachbytedataisshiftedout,sothewholememory

can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has

beenreached.

The sequence of issuing FAST_READ instruction is: CS# goes low-> sending FAST_READ instruction code-> 3-byte

address on SI-> 1-dummy byte address on SI->data out on SO-> to end FAST_READ operation can use CS# to high at

any time during data out. (see Figure. 17)

While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact

on the Program/Erase/Write Status Register current cycle.

(8) Sector Erase (SE)

TheSectorErase(SE)instructionisforerasingthedataofthechosensectortobe "1".AWriteEnable(WREN)instruction

must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector

(see table 3) is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the

latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed.

Address bits [Am-A12] (Am is the most significant address) select the sector address.

The sequence of issuing SE instruction is: CS# goes low -> sending SE instruction code-> 3-byte address on SI -> CS#

goes high. (see Figure 19)

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MX25L1605A

The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress

(WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE timing, and

sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by

BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the page.

(9) Block Erase (BE)

TheBlockErase(BE)instructionisforerasingthedataofthechosenblocktobe "1". AWriteEnable(WREN)instruction

must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block

(see table 3) is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the

latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed.

The sequence of issuing BE instruction is: CS# goes low -> sending BE instruction code-> 3-byte address on SI -> CS#

goes high. (see Figure 20)

The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress

(WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tBE timing, and

sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by

BP2, BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the page.

(10) Chip Erase (CE)

TheChipErase(CE)instructionisforerasingthedataofthewholechiptobe"1".AWriteEnable(WREN)instructionmust

executetosettheWriteEnableLatch(WEL)bitbeforesendingtheChipErase(CE). Anyaddressofthesector(seetable

3)isavalidaddressforChipErase(CE)instruction. TheCS#mustgohighexactlyatthebyteboundary(thelatesteighth

of address byte been latched-in); otherwise, the instruction will be rejected and not executed.

The sequence of issuing CE instruction is: CS# goes low-> sending CE instruction code-> CS# goes high. (see Figure

20)

The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress

(WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE timing, and

sets0whenChipEraseCycleiscompleted,andtheWriteEnableLatch(WEL)bitisreset.Ifthechipisprotectedby BP2,

BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when BP2, BP1, BP0 all set

to "0".

(11) Page Program (PP)

The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must

execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). If the eight least significant

address bits (A7-A0) are not all 0, all transmitted data which goes beyond the end of the current page are programmed

from the start address if the same page (from the address whose 8 least significant address bits (A7-A0) are all 0). The

CS# must keep during the whole Page Program cycle. The CS# must go high exactly at the byte boundary( the latest

eighthofaddressbytebeenlatched-in);otherwise,theinstructionwillberejectedandnotexecuted. Ifmorethan256bytes

are sent to the device, the data of the last 256-byte is programmed at the request page and previous data will be

disregarded. If less than 256 bytes are sent to the device, the data is programmed at the request address of the page

without effect on other address of the same page.

ThesequenceofissuingPPinstructionis:CS#goeslow->sendingPPinstructioncode->3-byteaddressonSI->atleast

1-byte on data on SI-> CS# goes high. (see Figure 18)

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MX25L1605A

Theself-timedPageProgramCycletime(tPP)isinitiatedassoonasChipSelect(CS#)goeshigh. TheWriteinProgress

(WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and

sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by

BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed.

(12) Deep Power-down (DP)

TheDeepPower-down(DP)instructionisforsettingthedeviceontheminimizingthepowerconsumption(toenteringthe

Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the

Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/

Program/Eraseinstructionareignored. WhenCS#goeshigh, it'sonlyinstandbymodenotdeeppower-downmode. It's

different from Standby mode.

ThesequenceofissuingDPinstructionis:CS#goeslow->sendingDPinstructioncode->CS#goeshigh.(seeFigure22)

OncetheDPinstructionisset,allinstructionwillbeignoredexcepttheReleasefromDeepPower-downmode(RDP)and

ReadElectronicSignature(RES)instruction.(RESinstructiontoallowtheIDbeenreadout).WhenPower-down,thedeep

power-down mode automatically stops, and when power-up, the device automatically is in standby mode. For RDP

instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in);

otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before

entering the Deep Power-down mode and reducing the current to ISB2.

(13) Release from Deep Power-down (RDP), Read Electronic Signature (RES)

TheReleasefromDeepPower-down(RDP)instructionisterminatedbydrivingChipSelect(CS#)High.WhenChipSelect

(CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Power-

downmode,thetransitiontotheStand-byPowermodeisimmediate.IfthedevicewaspreviouslyintheDeepPower-down

mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip Select (CS#) must remain High

for at least tRES2(max), as specified in Table 6. Once in the Stand-by Power mode, the device waits to be selected, so

that it can receive, decode and execute instructions.

RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID

Definitions. ThisisnotthesameasRDIDinstruction.Itisnotrecommendedtousefornewdesign.Fornewdeisng,please

use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except

the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in

progress.

The sequence is shown as Figure 23,24.

The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if

continuouslysendtheadditionalclockcyclesonSCLKwhileCS#isatlow. IfthedevicewasnotpreviouslyinDeepPower-

downmode,thedevicetransitiontostandbymodeisimmediate. IfthedevicewaspreviouslyinDeepPower-downmode,

there'sadelayoftRES2totransittostandbymode,andCS#mustremaintohighatleasttRES2(max). Onceinthestandby

mode, the device waits to be selected, so it can be receive, decode, and execute instruction.

The RDP instruction is for releasing from Deep Power Down Mode.

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MX25L1605A

(14) Read Electronic Manufacturer ID & Device ID (REMS)

TheREMSinstructionisanalternativetotheReleasefromPower-down/DeviceIDinstructionthatprovidesboththeJEDEC

assigned manufacturer ID and the specific device ID.

The REMS instruction is very similar to the Release from Power-down/Device ID instruction. The instruction is initiated

bydrivingtheCS#pinlowandshifttheinstructioncode"90h"followedbytwodummybytesandonebytesaddress(A7~A0).

After which, the Manufacturer ID for MXIC (C2h) and the Device ID are shifted out on the falling edge of SCLK with most

significant bit (MSB) first as shown in figure 25. The Device ID values are listed in Table of ID Definitions on page 16. If

the one-byte address is initially set to 01h, then the device ID will be read first and then followed by the Manufacturer ID.

TheManufacturerandDeviceIDscanbereadcontinuously,alternatingfromonetotheother.Theinstructioniscompleted

by driving CS# high.

Table of ID Definitions:

RDID

RES

manufacturer ID

C2

memory type

20

memory density

15

electronic ID

14

REMS

manufacturer ID

C2

device ID

14

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MX25L1605A

POWER-ON STATE

The device is at below states when power-up:

- Standby mode ( please note it is not deep power-down mode)

- Write Enable Latch (WEL) bit is reset

The device must not be selected during power-up and power-down stage unless the VCC achieves below correct level:

- VCC minimum at power-up stage and then after a delay of tVSL

-GNDatpower-down

Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.

Aninternalpower-onreset(POR)circuitmayprotectthedevicefromdatacorruptionandinadvertentdatachangeduring

powerupstate.WhenVCCislowerthanVWI(PORthresholdvoltagevalue),theinternallogicisresetandtheflashdevice

has no response to any command.

For further protection on the device, after VCC reaching the VWI level, a tPUW time delay is required before the device

isfullyaccessibleforcommandslikewriteenable(WREN),pageprogram(PP),sectorerase(SE),chiperase(CE)andwrite

status register(WRSR). If the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The

write, erase, and program command should be sent after the below time delay:

- tPUW after VCC reached VWI level

- tVSL after VCC reached VCC minimum level

The device can accept read command after VCC reached VCC minimum and a time delay of tVSL, even time of tPUW

has not passed.

Please refer to the figure of "power-up timing".

Note:

- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is

recommended.(generallyaround0.1uF)

- At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response to any

command. The data corruption might occur during the stage while a write, program, erase cycle is in progress.

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MX25L1605A

ELECTRICAL SPECIFICATIONS

ABSOLUTEMAXIMUMRATINGS

RATING

NOTICE:

VALUE

1. Stresses greater than those listed under ABSOLUTE

MAXIMUM RATINGS may cause permanent damage

to the device. This is stress rating only and functional

operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for

extended period may affect reliability.

AmbientOperatingTemperature -40°C to 85°C for

Industrial grade

0°C to 70°C for

Commercialgrade

2. Specificationscontainedwithinthefollowingtablesare

subject to change.

3. During voltage transitions, all pins may overshoot Vss

to -2.0V and Vcc to +2.0V for periods up to 20ns, see

Figure3,4.

StorageTemperature

Applied Input Voltage

AppliedOutputVoltage

VCC to Ground Potential

-55°Cto125°C

-0.5V to 4.6V

Figure 3.Maximum Negative Overshoot Waveform

Figure4.MaximumPositiveOvershootWaveform

20ns

Vss

Vcc + 2.0V

Vss - 2.0V

Vcc

20ns

CAPACITANCE TA = 25°C, f = 1.0 MHz

SYMBOL

CIN

PARAMETER

MIN.

TYP

MAX.

UNIT

pF

CONDITIONS

VIN = 0V

InputCapacitance

OutputCapacitance

6

8

COUT

pF

VOUT = 0V

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MX25L1605A

Figure 5. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL

Input timing referance level

Output timing referance level

0.8VCC

0.2VCC

0.7VCC

0.3VCC

AC

Measurement

Level

0.5VCC

Note: Input pulse rise and fall time are <5ns

Figure 6. OUTPUT LOADING

DEVICE UNDER

TEST

2.7K ohm

+3.3V

CL

6.2K ohm

DIODES=IN3064

OR EQUIVALENT

CL=30pF Including jig capacitance

(CL=15pF Including jig capacitance for 85MHz and 70MHz)

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MX25L1605A

Table 5. DC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, Temperature =

0°C to 70°C for Commercial grade, VCC = 2.7V ~ 3.6V)

SYMBOL PARAMETER

NOTES

MIN.

TYP MAX. UNITS

TESTCONDITIONS

VCC = VCC Max

ILI

InputLoad

Current

1

± 2

20

10

12

8

uA

VIN = VCC or GND

VCC = VCC Max

ILO

OutputLeakage

Current

1

VIN = VCC or GND

CS# = VCC

ISB1

ISB2

ICC1

VCCStandby

Current

uA

DeepPower-down

Current

1

uA

VIN = VCC or GND

CS# = VCC

VCCRead

1

mA

f=85MHz and 70MHz

SCLK=0.1VCC/0.9VCC,SO=Open

f=66MHz

SCLK=0.1VCC/0.9VCC,SO=Open

f=33MHz

4

SCLK=0.1VCC/0.9VCC,SO=Open

PrograminProgress

CS# = VCC

ICC2

ICC3

VCCProgram

1

15

Current(PP)

VCC Write Status

Register(WRSR)

Current

Programstatusregisterinprogress

CS#=VCC

ICC4

ICC5

VCC Sector Erase

Current(SE)

1

15

mA

Erase in Progress

CS#=VCC

VCC Chip Erase

Current(CE)

Erase in Progress

CS#=VCC

VIL

Input Low Voltage

Input High Voltage

OutputLowVoltage

OutputHighVoltage

-0.5

0.3VCC

VCC+0.4

0.4

V

VIH

VOL

VOH

0.7VCC

IOL = 1.6mA

IOH = -100uA

VCC-0.2

Notes :

1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds).

2. Typical value is calculated by simulation.

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MX25L1605A

Table 6. AC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, Temperature =

0°C to 70°C for Commercial grade, VCC = 2.7V ~ 3.6V)

Symbol

Alt.

Parameter

Min.

Typ. Max.

Unit

fSCLK

fC

Clock Frequency for the following instructions:

FAST_READ, PP, SE, BE, CE, DP, RES,RDP

WREN, WRDI, RDID, RDSR, WRSR

1KHz

70 & 85 MHz

(Condition:15pF)

66

MHz

(Condition:30pF)

fRSCLK

tCH(1)

fR

Clock Frequency for READ instructions

1KHz

7

33

MHz

tCLH Clock High Time

tCLL Clock Low Time

ns

V/ns

ns

us

ms

s

tCL(1)

7

tCLCH(2)

tCHCL(2)

tSLCH

tCHSL

tDVCH

tCHDX

tCHSH

tSHCH

tSHSL

Clock Rise Time (3) (peak to peak)

0.1

5

Clock Fall Time (3) (peak to peak)

tCSS CS# Active Setup Time (relative to SCLK)

CS# Not Active Hold Time (relative to SCLK)

tDSU Data In Setup Time

5

2

tDH

Data In Hold Time

5

CS# Active Hold Time (relative to SCLK)

CS# Not Active Setup Time (relative to SCLK)

5

tCSH CS# Deselect Time

100

tSHQZ(2) tDIS Output Disable Time

6

8

6

tCLQV

tV

Clock Low to Output Valid @33MHz 30pF

@85MHz/70MHz 15pF or @66MHz 30pF

0

tCLQX

tHLCH

tCHHH

tHHCH

tCHHL

tHO

Output Hold Time

HOLD# Setup Time (relative to SCLK)

HOLD# Hold Time (relative to SCLK)

HOLD Setup Time (relative to SCLK)

HOLD Hold Time (relative to SCLK)

HOLD to Output Low-Z

5

tHHQX(2) tLZ

tHLQZ(2) tHZ

tWHSL(4)

tSHWL(4)

tDP(2)

6

HOLD#toOutputHigh-Z

Write Protect Setup Time

20

Write Protect Hold Time

100

CS#HightoDeepPower-downMode

CS# High to Standby Mode without Electronic Signature Read

CS# High to Standby Mode with Electronic Signature Read

Write Status Register Cycle Time

Page Program Cycle Time

3

tRES1(2)

tRES2(2)

tW

1.8

15

5

1.4

60

1

tPP

tSE

Sector Erase Cycle Time

120

2

tBE

Block Erase Cycle Time

tCE

Chip Erase Cycle Time

14

30

s

Notes:

1. tCH + tCL must be greater than or equal to 1/ fC

2. Value guaranteed by characterization, not 100% tested in production.

3. Expressed as a slew-rate.

4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.

5. Test condition is shown as Figure 3.

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MX25L1605A

Table 7. Power-Up Timing and VWI Threshold

Symbol

tVSL(1)

tPUW(1)

VWI(1)

Parameter

Min.

30

Max.

Unit

us

VCC(min) to CS# low

Time delay to Write instruction

Write Inhibit Voltage

1

10

ms

V

1.5

2.5

Note: 1. These parameters are characterized only.

INITIAL DELIVERY STATE

The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register

contains 00h (all Status Register bits are 0).

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MX25L1605A

Figure 7. Serial Input Timing

tSHSL

tSHCH

tCHCL

CS#

tCHSL

tSLCH

tCHSH

SCLK

tDVCH

tCHDX

tCLCH

MSB

LSB

SI

High-Z

SO

Figure 8. Output Timing

CS#

tCH

SCLK

tCLQV

tCL

tSHQZ

tCLQX

LSB

SO

SI

tQLQH

tQHQL

ADDR.LSB IN

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25

MX25L1605A

Figure 9. Hold Timing

CS#

tHLCH

tCHHH

tCHHL

tHLQZ

tHHCH

tHHQX

SCLK

SO

HOLD#

* SI is "don't care" during HOLD operation.

Figure 10. WP# Disable Setup and Hold Timing during WRSR when SRWD=1

WP#

tSHWL

tWHSL

CS#

0

1

2

3

4

5

6

7

8

9

10 11 12

13 14

15

SCLK

01

SI

High-Z

SO

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MX25L1605A

Figure 11. Write Enable (WREN) Sequence (Command 06)

CS#

0

1

2

3

4

5

6

7

SCLK

Command

06

SI

High-Z

SO

Figure 12. Write Disable (WRDI) Sequence (Command 04)

CS#

0

1

2

3

4

5

6

7

SCLK

Command

04

SI

High-Z

SO

Figure 13. Read Identification (RDID) Sequence (Command 9F)

CS#

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18

28 29 30 31

SCLK

SI

Command

9F

Manufacturer Identification

Device Identification

High-Z

SO

7

6

5

3

2

1

0

15 14 13

MSB

3

2

1

0

MSB

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MX25L1605A

Figure 14. Read Status Register (RDSR) Sequence (Command 05)

CS#

SCLK

SI

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

command

05

Status Register Out

High-Z

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

MSB

Figure 15. Write Status Register (WRSR) Sequence (Command 01)

CS#

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

SCLK

command

01

Status

Register In

SI

7

6

5

4

3

2

0

1

MSB

High-Z

SO

Figure 16. Read Data Bytes (READ) Sequence (Command 03)

CS#

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38 39

SCLK

command

03

24-Bit Address

23 22 21

MSB

3

2

1

0

SI

Data Out 1

Data Out 2

High-Z

2

7

6

5

4

3

1

7

0

SO

MSB

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MX25L1605A

Figure 17. Read at Higher Speed (FAST_READ) Sequence (Command 0B)

CS#

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31

SCLK

Command

0B

24 BIT ADDRESS

SI

23 22 21

3

2

1

0

High-Z

SO

CS#

47

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

SCLK

Dummy Byte

7

6

5

4

3

2

0

1

SI

DATA OUT 2

DATA OUT 1

7

6

5

4

3

2

1

0

7

6

5

4

3

2

0

1

SO

MSB

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MX25L1605A

Figure 18. Page Program (PP) Sequence (Command 02)

CS#

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38 39

SCLK

Command

02

24-Bit Address

Data Byte 1

23 22 21

MSB

3

2

1

0

7

6

5

4

3

2

0

1

SI

MSB

CS#

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

SCLK

Data Byte 2

Data Byte 3

Data Byte 256

7

6

5

4

3

2

0

7

6

5

4

3

2

0

7

6

5

4

3

2

0

1

SI

MSB

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MX25L1605A

Figure 19. Sector Erase (SE) Sequence (Command 20)

CS#

0

1

2

3

4

5

6

7

8

9

29 30 31

SCLK

Command

20

24 Bit Address

SI

7

6

2

1

0

MSB

Note: SE command is 20(hex).

Figure 20. Block Erase (BE) Sequence (Command 52 or D8)

CS#

0

1

2

3

4

5

6

7

8

9

29 30 31

SCLK

Command

52 or D8

24 Bit Address

SI

23 22

MSB

2

0

1

Note: BE command is 52 or D8(hex).

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MX25L1605A

Figure 21. Chip Erase (CE) Sequence (Command 60 or C7)

CS#

0

1

2

3

4

5

6

7

SCLK

SI

Command

60 or C7

Note: CE command is 60(hex) or C7(hex).

Figure 22. Deep Power-down (DP) Sequence (Command B9)

CS#

t_DP

0

1

2

3

4

5

6

7

SCLK

SI

Command

B9

Stand-by Mode

Deep Power-down Mode

Figure 23. Release from Deep Power-down and Read Electronic Signature (RES) Sequence

(Command AB)

CS#

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38

SCLK

Command

AB

t

3 Dummy Bytes

RES2

SI

23 22 21

MSB

3

2

1

0

Electronic Signature Out

High-Z

7

6

5

4

3

2

0

1

SO

MSB

Deep Power-down Mode

Stand-by Mode

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MX25L1605A

Figure 24. Release from Deep Power-down (RDP) Sequence (Command AB)

CS#

t

RES1

0

1

2

3

4

5

6

7

SCLK

Command

AB

SI

High-Z

SO

Deep Power-down Mode

Stand-by Mode

Figure 25. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90)

CS#

0

1

2

3

4

5

6

7

8

9 10

SCLK

Command

90

2 Dummy Bytes

SI

15 14 13

3

2

1

0

High-Z

SO

CS#

47

28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

SCLK

ADD (1)

7

6

5

4

3

2

0

1

SI

Manufacturer ID

Device ID

7

6

5

4

3

2

1

0

7

6

5

4

3

2

0

1

X

SO

MSB

Notes:

(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first

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33

MX25L1605A

Figure 26. Power-up Timing

V

CC

V

(max)

CC

Program, Erase and Write Commands are Ignored

Chip Selection is Not Allowed

V

(min)

CC

tVSL

Read Command is

allowed

Device is fully

accessible

Reset State

of the

Flash

V

WI

tPUW

time

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MX25L1605A

RECOMMENDED OPERATING CONDITIONS

AtDevicePower-Up

AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up. If

the timing in the figure is ignored, the device may not operate correctly.

VCC(min)

VCC

GND

tSHSL

tVR

CS#

tCHSL

tSLCH

tCHSH

tSHCH

SCLK

tDVCH

tCHCL

tCHDX

tCLCH

MSB IN

LSB IN

SI

High Impedance

SO

Figure A. AC Timing at Device Power-Up

Symbol

Parameter

VCC Rise Time

Notes

Min.

Max.

500000

Unit

tVR

1

0.5

us/V

Notes :

1. Sampled, not 100% tested.

2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "AC

CHARACTERISTICS"table.

P/N:PM1211

REV. 1.6, APR. 18, 2008

35

MX25L1605A

ERASE AND PROGRAMMING PERFORMANCE

PARAMETER

Min.

TYP. (1)

Max.(2)

UNIT

ms

Write Status Register Cycle Time

Sector erase Time

Block erase Time

5

60

1

15

120

2

ms

s

Chip Erase Time

14

1.4

30

5

s

PageProgramTime

Erase/ProgramCycle

ms

100,000

cycles

Note:

1. Typical program and erase time assumes the following conditions: 25°C, 3.3V, and checker board pattern.

2. Under worst conditions of 70°C and 3.0V.

3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming command.

4. Themaximumchipprogrammingtimeisevaluatedundertheworstconditionsof0C, VCC=3.0V, and100Kcyclewith

90% confidence level.

LATCH-UP CHARACTERISTICS

MIN.

-1.0V

MAX.

12.5V

Input Voltage with respect to GND on ACC

Input Voltage with respect to GND on all power pins, SI, CS#

Input Voltage with respect to GND on SO

-1.0V

2 VCCmax

VCC + 1.0V

+100mA

-1.0V

Current

-100mA

Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.

P/N:PM1211

REV. 1.6, APR. 18, 2008

36

MX25L1605A

ORDERING INFORMATION

PARTNO.

CLOCK

OPERATING

STANDBY

Temperature PACKAGE Remark

(MHz)

CURRENTMAX. CURRENTMAX.

(mA)

12

(uA)

20

MX25L1605AMC-12

MX25L1605AMC-12G

MX25L1605AMI-12

MX25L1605AMI-12G

MX25L1605AZMC-12G

85

0~70°C

16-SOP

8-landSON

(8x6 mm)

8-landSON

(8x6 mm)

8-SOP

12

20

Pb-free

12

20

-40~85°C

0~70°C

12

20

Pb-free

12

20

MX25L1605AZMI-12G

MX25L1605AM2C-12

MX25L1605AM2C-12G

MX25L1605AM2I-12

MX25L1605AM2I-12G

85

12

20

-40~85°C

0~70°C

Pb-free

(200mil)

8-SOP

0~70°C

Pb-free

(200mil)

8-SOP

-40~85°C

(200mil)

8-SOP

Pb-free

(200mil)

16-SOP

8-landSON

(8x6 mm)

8-landSON

(8x6 mm)

8-SOP

MX25L1605AMC-15

MX25L1605AMC-15G

MX25L1605AMI-15

MX25L1605AMI-15G

MX25L1605AZMC-15G

70

12

20

0~70°C

-40~85°C

0~70°C

Pb-free

MX25L1605AZMI-15G

MX25L1605AM2C-15

MX25L1605AM2C-15G

MX25L1605AM2I-15

MX25L1605AM2I-15G

70

12

20

-40~85°C

0~70°C

Pb-free

(200mil)

8-SOP

0~70°C

(200mil)

8-SOP

-40~85°C

(200mil)

8-SOP

(200mil)

P/N:PM1211

REV. 1.6, APR. 18, 2008

37

MX25L1605A

PART NAME DESCRIPTION

MX 25 L 1605A ZM

C

12 G

OPTION:

G: Pb-free

blank: normal

SPEED:

12: 85MHz

15: 70MHz

TEMPERATURE RANGE:

C: Commercial (0˚C to 70˚C)

I: Industrial (-40˚C to 85˚C)

PACKAGE:

ZM: SON

M: 300mil 16-SOP

M2: 200mil 8-SOP

DENSITY & MODE:

1605A: 16Mb

TYPE:

L: 3V

DEVICE:

25: Serial Flash

P/N:PM1211

REV. 1.6, APR. 18, 2008

38

MX25L1605A

PACKAGE INFORMATION

P/N:PM1211

REV. 1.6, APR. 18, 2008

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MX25L1605A

P/N:PM1211

REV. 1.6, APR. 18, 2008

40

MX25L1605A

P/N:PM1211

REV. 1.6, APR. 18, 2008

41

MX25L1605A

REVISION HISTORY

RevisionNo. Description

Page

P1

Date

SEP/09/2005

1.0

1. Removed "Advanced Information" title

2. Added description about Pb-free device is RoHS compliant

1. Added 85MHz spec

P1

1.1

P1,19-21,35 SEP/29/2005

P36

2. Standby current is reduced from 50uA(max) to 20uA(max)

3.ModifiedtSE:90ms(typ)/270ms(max)-->60ms(typ)/120ms(max);

tBE:3s(max)-->2s(max); tCE:32s(typ)/64s(max)-->14s(typ)/30s(max)

4. Supplemented 52(hex) code for 64KB erase

1. Format change

P1,2,20,35

P1,21,34

P7,29

All

1.2

JUN/08/2006

2. Supplemented the footnote for tW of protect/unprotect bits

1. Added statement

1. Defined min. clock frequency of fSCLK & fRSCLK as 1KHz

1. Modified figure 3 & figure 4 waveforms

P11

P41

P22

P19

P1,2

1.3

1.4

1.5

1.6

NOV/06/2006

NOV/29/2006

MAR/09/2007

APR/18/2008

1.Announced"phase-out"wording

P/N:PM1211

REV. 1.6, APR. 18, 2008

42

MX25L1605A

Macronix's products are not designed, manufactured, or intended for use for any high risk applications in which the failure

of a single component could cause death, personal injury, severe physical damage, or other substantial harm to persons

or property, such as life-support systems, high temperature automotive, medical, aircraft and military application. Macronix

and its suppliers will not be liable to you and/or any third party for any claims, injuries or damages that may be incurred due

to use of Macronix's products in the prohibited applications.

MACRONIX INTERNATIONALCO., LTD.

Taipei Office

Headquarters

Macronix, Int'l Co., Ltd.

16, Li-Hsin Road, Science Park,

Hsinchu, Taiwan, R.O.C.

Tel: +886-3-5786688

19F, 4, Min-Chuan E. Road, Sec. 3,

Taipei, Taiwan, R.O.C.

Tel: +886-2-2509-3300

Fax: +886-2-2509-2200

Fax: +886-3-5632888

Macronix EuropeN.V.

MacronixAmerica, Inc.

680 North McCarthy Blvd.

Milpitas, CA 95035, U.S.A.

Tel: +1-408-262-8887

Koningin Astridlaan 59, Bus 1

1780 Wemmel Belgium

Tel: +32-2-456-8020

Fax: +32-2-456-8021

Fax: +1-408-262-8810

Email: sales.northamerica@macronix.com

Macronix Japan Cayman Islands Ltd.

NKF Bldg. 5F, 1-2 Higashida-cho,

Kawasaki-ku Kawasaki-shi,

Kanagawa Pref. 210-0005, Japan

Tel: +81-44-246-9100

SingaporeOffice

Macronix Pte. Ltd.

1 Marine Parade Central

#11-03 Parkway Centre

Singapore 449408

Tel: +65-6346-5505

Fax: +65-6348-8096

Fax: +81-44-246-9105

Macronix (Hong Kong) Co., Limited.

702-703, 7/F, Building 9,

Hong Kong Science Park,

5 Science Park West Avenue, Sha Tin, N.T.

Tel: +86-852-2607-4289

Fax: +86-852-2607-4229

http : //www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.

43


型号：	MX25L1605AMC-12
厂家：	MACRONIX INTERNATIONAL
描述：	Flash, 16MX1, PDSO16, 0.300 INCH, MS-013, SOP-16 光电二极管
文件：	总43页 (文件大小：966K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MX25L1605AMC-12 [Macronix]

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