MX25L1605DMI-12G_技术文档

MX25L1605D

MX25L3205D

MX25L6405D

16M-BIT [x 1 / x 2] CMOS SERIAL FLASH

32M-BIT [x 1 / x 2] CMOS SERIAL FLASH

64M-BIT [x 1 / x 2] CMOS SERIAL FLASH

FEATURES

GENERAL

• Serial Peripheral Interface compatible -- Mode 0 and Mode 3

• 16M:16,777,216 x 1 bit structure or 8,388,608 x 2 bits (two I/O read mode) structure

32M:33,554,432 x 1 bit structure or 16,772,216 x 2 bits (two I/O read mode) structure

64M:67,108,864 x 1 bit structure or 33,554,432 x 2 bits (two I/O read mode) structure

• 512 Equal Sectors with 4K byte each (16Mb)

1024 Equal Sectors with 4K byte each (32Mb)

2048 Equal Sectors with 4K byte each (64Mb)

- Any Sector can be erased individually

• 32 Equal Blocks with 64K byte each (16Mb)

64 Equal Blocks with 64K byte each (32Mb)

128 Equal Blocks with 64K byte each (64Mb)

- Any Block can be erased individually

• Single Power Supply Operation

- 2.7 to 3.6 volt for read, erase, and program operations

• Latch-up protected to 100mA from -1V to Vcc +1V

• Low Vcc write inhibit is from 1.5V to 2.5V

PERFORMANCE

• High Performance

- Fast access time: 86MHz serial clock (15pF + 1TTL Load) and 66MHz serial clock (30pF + 1TTL Load)

- Serial clock of two I/O read mode : 50MHz (15pF + TTL Load), which is equivalent to 100MHz

- Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)

- Byte program time: 9us (typical)

-Continuouslyprogrammode(automaticallyincreaseaddressunderwordprogrammode)

- Fast erase time: 60ms(typ.) /sector (4K-byte per sector) ; 0.7s(typ.) /block (64K-byte per block); 14s(typ.) /chip for

16Mb, 25s(typ.) for 32Mb, and 50s(typ.) for 64Mb

• Low Power Consumption

- Low active read current: 25mA(max.) at 86MHz, 20mA(max.) at 66MHz and 10mA(max.) at 33MHz

- Low active programming current: 20mA (max.)

- Low active erase current: 20mA (max.)

- Low standby current: 20uA (max.)

-Deeppower-downmode1uA(typical)

• Typical 100,000 erase/program cycles

SOFTWAREFEATURES

• Input Data Format

- 1-byte Command code

• Advanced Security Features

- Block lock protection

The BP0-BP3 status bit defines the size of the area to be software protection against program and erase instructions

- Additional 512-bit secured OTP for unique identifier

• Auto Erase and Auto Program Algorithm

- Automatically erases and verifies data at selected sector

- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the

program pulse widths (Any page to be programed should have page in the erased state first)

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• Status Register Feature

• Electronic Identification

- JEDEC 1-byte manufacturer ID and 2-byte device ID

- RES command for 1-byte Device ID

- Both REMS and REMS2 commands for 1-byte manufacturer ID and 1-byte device ID

HARDWAREFEATURES

• SCLK Input

- Serial clock input

• SI Input

- Serial Data Input

• SO Output

- Serial Data Output

• WP#/ACC pin

- Hardware write protection and program/erase acceleration

• HOLD# pin

- pause the chip without diselecting the chip

• PACKAGE

- 16-pin SOP (300mil)

- 8-landWSON (8x6mm or 6x5mm)

- 8-pin SOP (200mil, 150mil)

- 8-pin PDIP (300mil)

- 8-land USON (4x4mm)

- All Pb-free devices are RoHS Compliant

ALTERNATIVE

• Security Serial Flash (MX25L1615D/MX25L3215D/MX25L6415D) may provides additional protection features for op-

tion.The datasheet is provided under NDA.

GENERAL DESCRIPTION

The MX25L1605D are 16,777,216 bit serial Flash memory, which is configured as 2,097,152 x 8 internally. When it is in

twoI/Oreadmode,thestructurebecomes8,388,608bitsx2.TheMX25L3205Dare33,554,432bitserialFlashmemory,

which is configured as 4,194,304 x 8 internally. When it is in two I/O read mode, the structure becomes 16,772,216 bits

x 2. The MX25L6405D are 67,108,864 bit serial Flash memory, which is configured as 8,388,608 x 8 internally. When it

is in two I/O read mode, the structure becomes 33,554,432 bits x 2. (please refer to the "Two I/O Read mode" section).

TheMX25L1605D/3205D/6405Dfeatureaserialperipheralinterfaceandsoftwareprotocolallowingoperationonasimple

3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial

access to the device is enabled by CS# input.

When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and

data output.

TheMX25L1605D/3205D/6405Dprovidessequentialreadoperationonwholechip.

After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified

pageorsector/blocklocationswillbeexecuted. Programcommandisexecutedonbytebasis, orpage(256bytes)basis,

orwordbasisforContinuouslyprogrammode,anderasecommandisexecutesonsector(4K-byte),orblock(64K-byte),

or whole chip basis.

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To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read

command can be issued to detect completion status of a program or erase operation via WIP bit.

Advancedsecurityfeaturesenhancetheprotectionandsecurityfunctions, pleaseseesecurityfeaturessectionformore

details.

When the device is not in operation and CS# is high, it is put in standby mode and draws less than 20uA DC current.

The MX25L1605D/3205D/6405D utilizes MXIC's proprietary memory cell, which reliably stores memory contents even

after typical 100,000 program and erase cycles.

Table 1. Additional Feature Comparison

Read

Performance

Additional

Protection and Security

Flexible

Identifier

Featu-

res

Device ID

(command :

AB hex)

Device ID

(command :

EF hex)

RDID

(command:

9F hex)

Block

512-bit

2 I/O Read

(50MHz)

(command :

90 hex)

protection

(BP0-BP3)

secured OTP

Part Name

C2 14 (hex)

(if ADD=0)

C2 14 (hex)

(if ADD=0)

MX25L1605D

V

14 (hex)

15 (hex)

C2 20 15 (hex)

C2 20 16 (hex)

C2 15 (hex)

(if ADD=0)

C2 15 (hex)

(if ADD=0)

MX25L3205D

MX25L6405D

C2 16 (hex)

(if ADD=0)

C2 16 (hex)

(if ADD=0)

V

16 (hex)

C2 20 17 (hex)

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PIN CONFIGURATIONS

16-PIN SOP (300mil)

8-PIN SOP (200mil, 150mil)

1

2

3

4

5

6

7

8

SCLK

SI/SIO0

NC

HOLD#

VCC

NC

16

15

14

13

12

11

10

9

1

2

3

4

CS#

SO/SIO1

WP#/ACC

GND

VCC

8

7

6

5

HOLD#

SCLK

NC

SI/SIO0

GND

WP#/ACC

CS#

SO/SIO1

8-PIN PDIP (300mil)

8-LANDWSON(8x6mm,6x5mm),USON(4x4mm)

1

2

3

4

VCC

CS#

SO/SIO1

WP#/ACC

GND

1

VCC

CS#

SO/SIO1

WP#/ACC

GND

8

7

6

5

8

7

6

5

HOLD#

SCLK

2

3

4

HOLD#

SCLK

SI/SIO0

PIN DESCRIPTION

PACKAGE OPTIONS

SYMBOL DESCRIPTION

16M

32M

64M

V

CS#

Chip Select

150mil8-SOP

200mil8-SOP

300mil16-SOP

300mil8-PDIP

6x5mmWSON

8x6mmWSON

4x4mmUSON

V

SI/SIO0

Serial Data Input (for 1 x I/O)/ Serial Data

Input & Output (for 2xI/O read mode)

Serial Data Output (for 1 x I/O)/ Serial

DataInput&Output(for2xI/Oreadmode)

Clock Input

V

SO/SIO1

SCLK

V

WP#/ACC Write protection: connect to GND ;

9.5~10.5Vforprogram/erase

V

acceleration: connect to 9.5~10.5V

HOLD#

Hold, to pause the device without

deselecting the device

+ 3.3V Power Supply

Ground

VCC

GND

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BLOCK DIAGRAM

Address

Generator

Memory Array

Page Buffer

Data

Register

SI/SIO0

Y-Decoder

SO/SIO1

SRAM

Buffer

Sense

Amplifier

CS#,

WP#/ACC,

HOLD#

Mode

Logic

State

Machine

HV

Generator

SCLK

Clock Generator

Output

Buffer

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DATA PROTECTION

The MX25L1605D/3205D/6405D is designed to offer protection against accidental erasure or programming caused by

spurioussystemlevelsignalsthatmayexistduringpowertransition.Duringpowerupthedeviceautomaticallyresetsthe

statemachineintheReadmode. Inaddition, withitscontrolregisterarchitecture, alterationofthememorycontentsonly

occurs after successful completion of specific command sequences. The device also incorporates several features to

prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise.

•

Power-on reset and tPUW: to avoid sudden power switch by system power supply transition, the power-on reset and

tPUW (internal timer) may protect the Flash.

• Validcommandlengthchecking:Thecommandlengthwillbecheckedwhetheritisatbytebaseandcompletedonbyte

boundary.

• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other

command to change data. The WEL bit will return to reset stage under following situation:

-Power-up

- Write Disable (WRDI) command completion

- Write Status Register (WRSR) command completion

- Page Program (PP) command completion

- Continuously Program mode (CP) instruction completion

- Sector Erase (SE) command completion

- Block Erase (BE) command completion

- Chip Erase (CE) command completion

- Write Read-lock Bit (WRLB) instruction completion

•

Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing

allcommandsexceptReleasefromdeeppowerdownmodecommand(RDP)andReadElectronicSignaturecommand

(RES).

AdvancedSecurityFeatures:therearesomeprotectionandsecuruityfeatureswhichprotectcontentfrominadvertent

write and hostile access.

I. Block lock protection

- TheSoftwareProtectedMode(SPM)use(BP3,BP2,BP1,BP0)bitstoallowpartofmemorytobeprotectedasread

only. The proected area definition is shown as table of "Protected Area Sizes", the protected areas are more flexible

which may protect various area by setting value of BP0-BP3 bits.

Please refer to table of "protected area sizes".

- The Hardware Proteced Mode (HPM) use WP#/ACC to protect the (BP3, BP2, BP1, BP0) bits and SRWD bit.

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Table 2. Protected Area Sizes

Status bit

Protect Level

64Mb

32Mb

BP3 BP2 BP1 BP0 16Mb

0(none)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0(none)

1(2blocks, block 126th-127th)

1(1block, block 63th)

1(1block, block 31th)

2(2blocks, block 30th-31th)

3(4blocks, block 28th-31th)

4(8blocks, block 24th-31th)

5(16blocks, block 16th-31th)

6(32blocks, all)

2(4blocks, block 124th-127th)

3(8blocks, block 120th-127th)

4(16blocks, block 112th-127th)

5(32blocks, block 96th-127th)

6(64blocks,block 64th-127th)

7(128blocks, all)

2(2blocks, block 62th-63th)

3(4blocks, block 60th-63th)

4(8blocks, block 56th-63th)

5(16blocks, block 48th-63th)

6(32blocks, block 32th-63th)

7(64blocks, all)

7(32blocks, all)

8(128blocks, all)

8(64blocks, all)

8(32blocks, all)

9(64blocks, block 0th-63th)

10(96blocks, block 0th-95th)

11(112blocks, block 0th-111th)

12(120blocks, block 0th-119th)

13(124blocks, block 0th-123th)

14(126blocks, block 0th-125th)

15(128blocks, all)

9(32blocks, block 0th-31th)

10(48blocks, block 0th-47th)

11(56blocks, block 0th-55th)

12(60blocks, block 0th-59th)

13(62blocks, block 0th-61th)

14(63blocks, block 0th-62th)

15(64blocks, all)

9(32blocks, all)

10(16blocks, block 0th-15th)

11(24blocks, block 0th-23th)

12(28blocks, block 0th-27th)

13(30blocks, block 0th-29th)

14(31blocks, block 0th-30th)

15(32blocks, all)

II. Additional 512-bit secured OTP for unique identifier: to provide 512-bit one-time program area for setting device

uniqueserialnumber-Whichmaybesetbyfactoryorsystemcustomer. Pleaserefertotable3. 512-bitsecuredOTP

definition.

- Security register bit 0 indicates whether the chip is locked by factory or not.

-Toprogramthe512-bitsecuredOTPbyentering512-bitsecuredOTPmode(withENSOcommand),andgoingthrough

normal program procedure, and then exiting 512-bit secured OTP mode by writing EXSO command.

-Customermaylock-downthecustomerlockablesecuredOTPbywritingWRSCUR(writesecurityregister)command

to set customer lock-down bit1 as "1". Please refer to table of "security register definition" for security register bit

definition and table of "512-bit secured OTP definition" for address range definition.

-Note:Oncelock-downwhateverbyfactoryorcustomer,itcannotbechangedanymore.Whilein512-bitsecuredOTP

mode, array access is not allowed.

Table 3. 512-bit Secured OTP Definition

Addressrange

xxxx00~xxxx0F

xxxx10~xxxx3F

Size

Standard

Factory Lock

CustomerLock

128-bit

384-bit

ESN (electrical serial number)

Determinedbycustomer

N/A

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HOLD FEATURES

HOLD#pinsignalgoeslowtoholdanyserialcommunicationswiththedevice.TheHOLDfeaturewillnotstoptheoperation

of write status register, programming, or erasing in progress.

TheoperationofHOLDrequiresChipSelect(CS#)keepinglowandstartsonfallingedgeofHOLD#pinsignalwhileSerial

Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start until Serial Clock

signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Serial Clock(SCLK) signal is

being low( if Serial Clock signal is not being low, HOLD operation will not end until Serial Clock being low), see Figure 1.

Figure 1. Hold Condition Operation

CS#

SCLK

HOLD#

Hold

Condition

(standard)

Condition

(non-standard)

TheSerialDataOutput(SO)ishighimpedance, bothSerialDataInput(SI)andSerialClock(SCLK)aredon'tcareduring

the HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of the device.

To re-start communication with chip, the HOLD# must be at high and CS# must be at low.

PROGRAM/ERASE ACCELERATION

Toactivatetheprogram/eraseaccelerationfunctionrequiresACCpinconnectingto9.5~10.5Vvoltage(seeFigure2),and

then to be followed by the normal program/erase process. By utilizing the program/erase acceleration operation, the

performances are improved as shown on table of "ERASE AND PROGRAM PERFORMACE".

After power-up ready, it should wait 10ms at least to apply VHH(9.5~10.5V) on the WP#/ACC pin.

Figure 2. ACCELERATED PROGRAM TIMING DIAGRAM

V_HH

9.5~10.5V

V_ILor V_IH

ACC

t_VHH

Note: tVHH (VHH Rise and Fall Time) min. 250ns

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Table 4. COMMAND DEFINITION

COMMAND WREN

(byte)

WRDI

(write

disable)

RDID (read RDSR

identification (read

WRSR

(write

status

READ FAST

(read data) READ

2READ (2 SE (sector

x I/O read erase)

(write

enable)

)

status

register)

(fast read command)

register)

data)

05 (hex) 01 (hex) 03 (hex) 0B (hex) BB (hex) 20 (hex)

note1

1st byte

2nd byte

3rd byte

06 (hex)

04 (hex) 9F (hex)

AD1

AD2

AD1

AD2

ADD(2)

AD1

ADD(2) & AD2

Dummy(2)

AD3

4th byte

5th byte

Action

AD3

Dummy

sets the

(WEL)

write

resets the outputs

(WEL)

write

enable

latch bit

to read out to write n bytes

JEDEC ID: the values new valuesread out read out read out the

n bytes

to erase

1-byte

of the

to the

status

register

until CS# until CS# by 2 x I/O selected

goes high goes high until CS# sector

goes high

enable

latch bit

manufactur status

er ID & 2- register

byte device

ID

Note 1: The count base is 4-bit for ADD(2) and Dummy(2) because of 2 x I/O. And the MSB is on SI/SIO0 which is

different from 1 x I/O condition

COMMAND BE (block CE (chip PP (Page CP

DP (Deep RDP RES (read REMS

(Continuo- power (Release electronic (read

REMS2

(read ID

(byte)

erase)

program)

usly

program

mode)

down)

from deep ID)

power

down)

electronic for 2x I/O

manufactu- mode)

rer &

device ID)

AD (hex) B9 (hex) AB (hex) AB (hex) 90 (hex) EF (hex)

1st byte

D8 (hex) 60 or C7 02 (hex)

(hex)

2nd byte

3rd byte

4th byte

AD1

AD2

AD3

AD1

AD2

AD3

AD1

AD2

AD3

x

ADD(note ADD(note

2) 2)

5th byte

Action

to erase

the

selected

block

to erase

whole chip the selected program deep

page whole power

to program continously enters

release

from deep 1-byte

power

down

mode

to read out outout the output the

manufactu- manufactu-

device ID rer ID & rer ID &

device ID device ID

chip, the down

address is mode

automatica

lly increase

Note 2: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first

COMMAND ENSO

EXSO

(exit

secured

OTP)

RDSCUR

(read

security

register)

WRSCUR

(write

security

register)

ESRY

DSRY

(byte)

(enter

secured

OTP)

(enable

SO to

output

(disable

SO to

output

RY/BY#)

70 (hex)

RY/BY#)

80 (hex)

1st byte

2nd byte

3rd byte

4th byte

5th byte

Action

B1 (hex)

C1 (hex)

2B (hex)

2F (hex)

to enter the

512-bit

secured

to exit the

512-bit

secured

to read

value of

security

register

to set the

lock-down

bit as "1"

(once lock-

down,

to enable

SO to

output

RY/BY#

during CP

mode

to disable

SO to

output

RY/BY#

during CP

mode

OTP mode

cannot be

updated)

Note 3: It is not recommoded to adopt any other code not in the command definition table, which will potentially enter

the hidden mode.

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Table 5-1. Memory Organization (16Mb)

Address Range

0FF000h 0FFFFFh

Block

15

Sector

255

.

Address Range

1FF000h 1FFFFFh

Block

31

Sector

511

.

240

0F0000h

0EF000h

0F0FFFh

0EFFFFh

.

239

.

496

1F0000h

1EF000h

1F0FFFh

1EFFFFh

14

13

12

11

495

224

0E0000h

0E0FFFh

.

30

29

28

27

223

0DF000h

0DFFFFh

.

480

1E0000h

1E0FFFh

479

1DF000h

1DFFFFh

208

0D0000h

0D0FFFh

.

207

0CF000h

0CFFFFh

.

464

1D0000h

1D0FFFh

192

0C0000h

0C0FFFh

463

1CF000h

1CFFFFh

.

191

0BF000h

0BFFFFh

.

448

1C0000h

1C0FFFh

176

0B0000h

0B0FFFh

447

1BF000h

1BFFFFh

.

175

0AF000h

0AFFFFh

.

10

9

432

1B0000h

1B0FFFh

160

0A0000h

0A0FFFh

431

1AF000h

1AFFFFh

.

159

09F000h

09FFFFh

26

25

24

23

.

416

1A0000h

1A0FFFh

144

090000h

090FFFh

415

19F000h

19FFFFh

143

08F000h

08FFFFh

.

8

400

190000h

190FFFh

128

080000h

080FFFh

399

18F000h

18FFFFh

127

07F000h

07FFFFh

.

7

384

180000h

180FFFh

112

070000h

070FFFh

383

17F000h

17FFFFh

111

06F000h

06FFFFh

.

6

5

4

3

368

170000h

170FFFh

96

060000h

060FFFh

367

16F000h

16FFFFh

95

05F000h

05FFFFh

.

22

21

20

19

352

160000h

160FFFh

80

050000h

050FFFh

351

15F000h

15FFFFh

79

04F000h

04FFFFh

.

64

040000h

040FFFh

336

150000h

150FFFh

63

03F000h

03FFFFh

335

14F000h

14FFFFh

.

48

030000h

030FFFh

320

140000h

140FFFh

47

02F000h

02FFFFh

319

13F000h

13FFFFh

.

2

1

32

020000h

020FFFh

304

130000h

130FFFh

31

01F000h

01FFFFh

303

12F000h

12FFFFh

.

18

17

16

010000h

010FFFh

288

120000h

120FFFh

15

00F000h

00FFFFh

287

11F000h

11FFFFh

.

4

3

2

1

0

004000h

003000h

002000h

001000h

000000h

004FFFh

003FFFh

002FFFh

001FFFh

000FFFh

272

110000h

110FFFh

0

271

10F000h

10FFFFh

.

256

100000h

100FFFh

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Table 5-2. Memory Organization (32Mb)

Address Range

2FF000h 2FFFFFh

Block

47

Sector

767

Address Range

3FF000h 3FFFFFh

Block

63

Sector

1023

.

752

2F0000h

2EF000h

2F0FFFh

2EFFFFh

.

751

1008

3F0000h

3EF000h

3F0FFFh

3EFFFFh

.

46

45

44

43

1007

.

736

2E0000h

2E0FFFh

62

61

60

59

735

2DF000h

2DFFFFh

992

3E0000h

3E0FFFh

.

991

3DF000h

3DFFFFh

.

720

2D0000h

2D0FFFh

719

2CF000h

2CFFFFh

976

3D0000h

3D0FFFh

.

975

3CF000h

3CFFFFh

.

704

2C0000h

2C0FFFh

703

2BF000h

2BFFFFh

960

3C0000h

3C0FFFh

.

959

3BF000h

3BFFFFh

.

688

2B0000h

2B0FFFh

944

3B0000h

3B0FFFh

687

2AF000h

2AFFFFh

.

42

41

40

39

943

3AF000h

3AFFFFh

.

58

57

56

55

672

2A0000h

2A0FFFh

928

3A0000h

3A0FFFh

671

29F000h

29FFFFh

.

927

39F000h

39FFFFh

.

656

290000h

290FFFh

912

390000h

390FFFh

655

28F000h

28FFFFh

.

911

38F000h

38FFFFh

.

640

280000h

280FFFh

896

380000h

380FFFh

639

27F000h

27FFFFh

.

895

37F000h

37FFFFh

.

624

270000h

270FFFh

880

370000h

370FFFh

623

26F000h

26FFFFh

.

879

36F000h

36FFFFh

38

37

36

35

.

54

53

52

51

608

260000h

260FFFh

864

360000h

360FFFh

607

25F000h

25FFFFh

.

863

35F000h

35FFFFh

.

592

250000h

250FFFh

848

350000h

350FFFh

591

24F000h

24FFFFh

847

34F000h

34FFFFh

.

576

240000h

240FFFh

832

340000h

340FFFh

575

23F000h

23FFFFh

831

33F000h

33FFFFh

.

560

230000h

230FFFh

816

330000h

330FFFh

559

22F000h

22FFFFh

815

32F000h

32FFFFh

.

34

33

32

.

50

49

48

544

220000h

220FFFh

800

320000h

320FFFh

543

21F000h

21FFFFh

799

31F000h

31FFFFh

.

528

210000h

210FFFh

784

310000h

310FFFh

527

20F000h

20FFFFh

783

30F000h

30FFFFh

.

512

200000h

200FFFh

768

300000h

300FFFh

P/N:PM1290

REV. 1.4, OCT. 01, 2008

11

MX25L1605D

MX25L3205D

MX25L6405D

Address Range

1FF000h 1FFFFFh

Address Range

Block

31

Sector

511

Block

15

Sector

255

.

0FF000h

0FFFFFh

.

240

0F0000h

0F0FFFh

496

1F0000h

1EF000h

1F0FFFh

1EFFFFh

239

.

0EF000h

0EFFFFh

495

.

14

13

12

11

30

29

28

27

224

0E0000h

0E0FFFh

480

1E0000h

1E0FFFh

223

.

0DF000h

0DFFFFh

479

1DF000h

1DFFFFh

.

208

0D0000h

0D0FFFh

464

1D0000h

1D0FFFh

207

.

0CF000h

0CFFFFh

.

463

1CF000h

1CFFFFh

.

192

0C0000h

0C0FFFh

448

1C0000h

1C0FFFh

191

.

0BF000h

0BFFFFh

.

447

1BF000h

1BFFFFh

.

176

0B0000h

0B0FFFh

432

1B0000h

1B0FFFh

175

0AF000h

0AFFFFh

.

10

9

431

1AF000h

1AFFFFh

.

26

25

24

23

160

0A0000h

0A0FFFh

159

.

09F000h

09FFFFh

416

1A0000h

1A0FFFh

.

415

19F000h

19FFFFh

.

144

090000h

090FFFh

143

.

08F000h

08FFFFh

400

190000h

190FFFh

.

8

399

18F000h

18FFFFh

128

080000h

080FFFh

.

127

.

07F000h

07FFFFh

.

384

180000h

180FFFh

7

383

17F000h

17FFFFh

112

070000h

070FFFh

.

111

.

06F000h

06FFFFh

.

368

170000h

170FFFh

6

5

4

3

367

16F000h

16FFFFh

96

060000h

060FFFh

.

22

21

20

19

95

.

05F000h

05FFFFh

.

352

160000h

160FFFh

80

050000h

050FFFh

351

15F000h

15FFFFh

.

79

.

04F000h

04FFFFh

.

336

150000h

150FFFh

64

040000h

040FFFh

335

14F000h

14FFFFh

.

63

.

03F000h

03FFFFh

.

320

140000h

140FFFh

48

030000h

030FFFh

319

13F000h

13FFFFh

.

47

.

02F000h

02FFFFh

.

2

1

304

130000h

130FFFh

32

020000h

020FFFh

303

12F000h

12FFFFh

31

.

01F000h

01FFFFh

.

18

17

16

288

120000h

120FFFh

16

010000h

010FFFh

287

11F000h

11FFFFh

15

00F000h

00FFFFh

.

4

3

2

1

0

004000h

003000h

002000h

001000h

000000h

004FFFh

003FFFh

002FFFh

001FFFh

000FFFh

272

110000h

110FFFh

0

271

10F000h

10FFFFh

.

256

100000h

100FFFh

P/N:PM1290

REV. 1.4, OCT. 01, 2008

12

MX25L1605D

MX25L3205D

MX25L6405D

Table 5-3. Memory Organization (64Mb)

Address Range

6FF000h 6FFFFFh

Block

111

Sector

1791

Address Range

7FF000h 7FFFFFh

Block

Sector

2047

.

1776

6F0000h

6EF000h

6F0FFFh

6EFFFFh

.

127

.

1775

2032

7F0000h

7EF000h

7F0FFFh

7EFFFFh

.

110

109

108

107

2031

.

126

125

124

123

1760

6E0000h

6E0FFFh

1759

6DF000h

6DFFFFh

2016

7E0000h

7E0FFFh

.

2015

7DF000h

7DFFFFh

.

1744

6D0000h

6D0FFFh

1743

6CF000h

6CFFFFh

2000

7D0000h

7D0FFFh

.

1999

7CF000h

7CFFFFh

.

1728

6C0000h

6C0FFFh

1984

7C0000h

7C0FFFh

1727

6BF000h

6BFFFFh

.

1983

7BF000h

7BFFFFh

.

1712

6B0000h

6B0FFFh

1968

7B0000h

7B0FFFh

1711

6AF000h

6AFFFFh

.

1967

7AF000h

7AFFFFh

106

105

104

103

.

122

121

120

119

1696

6A0000h

6A0FFFh

1952

7A0000h

7A0FFFh

1695

69F000h

69FFFFh

.

1951

79F000h

79FFFFh

.

1680

690000h

690FFFh

1936

790000h

790FFFh

1679

68F000h

68FFFFh

.

1935

78F000h

78FFFFh

.

1664

680000h

680FFFh

1920

780000h

780FFFh

1663

67F000h

67FFFFh

.

1919

77F000h

77FFFFh

.

1648

670000h

670FFFh

1904

770000h

770FFFh

1647

66F000h

66FFFFh

1903

76F000h

76FFFFh

.

102

101

100

99

.

118

117

116

115

1632

660000h

660FFFh

1888

760000h

760FFFh

1631

65F000h

65FFFFh

1887

75F000h

75FFFFh

.

1616

650000h

650FFFh

1872

750000h

750FFFh

1615

64F000h

64FFFFh

1871

74F000h

74FFFFh

.

1600

640000h

640FFFh

1856

740000h

740FFFh

1599

63F000h

63FFFFh

1855

73F000h

73FFFFh

.

1584

630000h

630FFFh

1840

730000h

730FFFh

1583

62F000h

62FFFFh

1839

72F000h

72FFFFh

.

98

97

96

114

113

112

1568

620000h

620FFFh

1824

720000h

720FFFh

1567

61F000h

61FFFFh

1823

71F000h

71FFFFh

.

1552

610000h

610FFFh

1808

710000h

710FFFh

1551

60F000h

60FFFFh

1807

70F000h

70FFFFh

.

1536

600000h

600FFFh

1792

700000h

700FFFh

P/N:PM1290

REV. 1.4, OCT. 01, 2008

13

MX25L1605D

MX25L3205D

MX25L6405D

Address Range

4FF000h 4FFFFFh

Block

79

Sector

1279

Address Range

5FF000h 5FFFFFh

Block

95

Sector

1535

.

1264

4F0000h

4EF000h

4F0FFFh

4EFFFFh

1520

5F0000h

5EF000h

5F0FFFh

5EFFFFh

1263

1519

.

78

77

76

75

94

93

92

91

1248

4E0000h

4E0FFFh

1504

5E0000h

5E0FFFh

1247

4DF000h

4DFFFFh

1503

5DF000h

5DFFFFh

.

1232

4D0000h

4D0FFFh

1488

5D0000h

5D0FFFh

1231

4CF000h

4CFFFFh

1487

5CF000h

5CFFFFh

.

1216

4C0000h

4C0FFFh

1472

5C0000h

5C0FFFh

1215

4BF000h

4BFFFFh

1471

5BF000h

5BFFFFh

.

1200

4B0000h

4B0FFFh

1456

5B0000h

5B0FFFh

1119

4AF000h

4AFFFFh

1455

5AF000h

5AFFFFh

.

74

73

72

71

90

1184

4A0000h

4A0FFFh

1440

5A0000h

5A0FFFh

1183

49F000h

49FFFFh

1439

59F000h

59FFFFh

.

89

88

87

1168

490000h

490FFFh

1424

590000h

590FFFh

1167

48F000h

48FFFFh

1423

58F000h

58FFFFh

.

1152

480000h

480FFFh

1408

580000h

580FFFh

1151

47F000h

47FFFFh

1407

57F000h

57FFFFh

.

1136

470000h

470FFFh

1392

570000h

570FFFh

1135

46F000h

46FFFFh

1391

56F000h

56FFFFh

.

70

69

68

67

86

1120

460000h

460FFFh

1376

560000h

560FFFh

1119

45F000h

45FFFFh

1375

55F000h

55FFFFh

.

85

84

83

1104

450000h

450FFFh

1360

550000h

550FFFh

1103

44F000h

44FFFFh

1359

54F000h

54FFFFh

.

1088

440000h

440FFFh

1344

540000h

540FFFh

1087

43F000h

43FFFFh

1343

53F000h

53FFFFh

.

1072

430000h

430FFFh

1328

530000h

530FFFh

1071

42F000h

42FFFFh

1327

52F000h

52FFFFh

.

66

65

64

82

81

80

1056

420000h

420FFFh

1312

520000h

520FFFh

1311

51F000h

51FFFFh

1055

41F000h

41FFFFh

.

1296

510000h

510FFFh

1040

410000h

410FFFh

1295

50F000h

50FFFFh

1039

40F000h

40FFFFh

.

1280

500000h

500FFFh

1024

400000h

400FFFh

P/N:PM1290

REV. 1.4, OCT. 01, 2008

14

MX25L1605D

MX25L3205D

MX25L6405D

Address Range

3FF000h 3FFFFFh

Block

63

Sector

1023

Address Range

2FF000h 2FFFFFh

Block

47

Sector

767

.

1008

3F0000h

3EF000h

3F0FFFh

3EFFFFh

752

2F0000h

2EF000h

2F0FFFh

2EFFFFh

1007

751

.

62

61

60

59

46

45

44

43

992

3E0000h

3E0FFFh

736

2E0000h

2E0FFFh

991

3DF000h

3DFFFFh

735

2DF000h

2DFFFFh

.

976

3D0000h

3D0FFFh

720

2D0000h

2D0FFFh

975

3CF000h

3CFFFFh

719

2CF000h

2CFFFFh

.

960

3C0000h

3C0FFFh

704

2C0000h

2C0FFFh

959

3BF000h

3BFFFFh

703

2BF000h

2BFFFFh

.

944

3B0000h

3B0FFFh

688

2B0000h

2B0FFFh

943

3AF000h

3AFFFFh

687

2AF000h

2AFFFFh

.

58

42

41

40

39

928

3A0000h

3A0FFFh

672

2A0000h

2A0FFFh

927

39F000h

39FFFFh

671

29F000h

29FFFFh

.

57

56

55

912

390000h

390FFFh

656

290000h

290FFFh

911

38F000h

38FFFFh

655

28F000h

28FFFFh

.

896

380000h

380FFFh

640

280000h

280FFFh

895

37F000h

37FFFFh

639

27F000h

27FFFFh

.

880

370000h

370FFFh

624

270000h

270FFFh

879

36F000h

36FFFFh

623

26F000h

26FFFFh

.

54

38

37

36

35

864

360000h

360FFFh

608

260000h

260FFFh

863

35F000h

35FFFFh

607

25F000h

25FFFFh

.

53

52

51

848

350000h

350FFFh

592

250000h

250FFFh

847

34F000h

34FFFFh

591

24F000h

24FFFFh

.

832

340000h

340FFFh

576

240000h

240FFFh

831

33F000h

33FFFFh

575

23F000h

23FFFFh

.

816

330000h

330FFFh

560

230000h

230FFFh

815

32F000h

32FFFFh

559

22F000h

22FFFFh

.

50

49

48

34

33

32

800

320000h

320FFFh

544

220000h

220FFFh

799

31F000h

31FFFFh

543

21F000h

21FFFFh

.

784

310000h

310FFFh

528

210000h

210FFFh

783

30F000h

30FFFFh

527

20F000h

20FFFFh

.

768

300000h

300FFFh

512

200000h

200FFFh

P/N:PM1290

REV. 1.4, OCT. 01, 2008

15

MX25L1605D

MX25L3205D

MX25L6405D

Address Range

1FF000h 1FFFFFh

Address Range

Block

31

Sector

511

Block

15

Sector

255

.

0FF000h

0FFFFFh

.

240

0F0000h

0F0FFFh

496

1F0000h

1EF000h

1F0FFFh

1EFFFFh

239

.

0EF000h

0EFFFFh

495

.

14

13

12

11

30

29

28

27

224

0E0000h

0E0FFFh

480

1E0000h

1E0FFFh

223

.

0DF000h

0DFFFFh

479

1DF000h

1DFFFFh

.

208

0D0000h

0D0FFFh

464

1D0000h

1D0FFFh

207

.

0CF000h

0CFFFFh

.

463

1CF000h

1CFFFFh

.

192

0C0000h

0C0FFFh

448

1C0000h

1C0FFFh

191

.

0BF000h

0BFFFFh

.

447

1BF000h

1BFFFFh

.

176

0B0000h

0B0FFFh

175

0AF000h

0AFFFFh

432

1B0000h

1B0FFFh

.

10

9

431

1AF000h

1AFFFFh

.

160

0A0000h

0A0FFFh

26

159

.

09F000h

09FFFFh

416

1A0000h

1A0FFFh

.

415

19F000h

19FFFFh

144

090000h

090FFFh

.

25

24

23

143

.

08F000h

08FFFFh

.

400

190000h

190FFFh

8

399

18F000h

18FFFFh

128

080000h

080FFFh

.

127

.

07F000h

07FFFFh

.

384

180000h

180FFFh

7

383

17F000h

17FFFFh

112

070000h

070FFFh

.

111

.

06F000h

06FFFFh

.

368

170000h

170FFFh

6

5

4

3

96

060000h

060FFFh

367

16F000h

16FFFFh

.

95

.

05F000h

05FFFFh

22

.

352

160000h

160FFFh

80

050000h

050FFFh

351

15F000h

15FFFFh

.

79

.

04F000h

04FFFFh

21

20

19

.

336

150000h

150FFFh

64

040000h

040FFFh

335

14F000h

14FFFFh

63

.

03F000h

03FFFFh

.

320

140000h

140FFFh

48

030000h

030FFFh

319

13F000h

13FFFFh

47

.

02F000h

02FFFFh

.

2

1

304

130000h

130FFFh

32

020000h

020FFFh

31

.

01F000h

01FFFFh

303

12F000h

12FFFFh

.

18

17

16

010000h

010FFFh

288

120000h

120FFFh

15

.

4

3

2

1

0

00F000h

00FFFFh

287

11F000h

11FFFFh

.

004000h

003000h

002000h

001000h

000000h

004FFFh

003FFFh

002FFFh

001FFFh

000FFFh

272

110000h

110FFFh

0

271

10F000h

10FFFFh

.

256

100000h

100FFFh

P/N:PM1290

REV. 1.4, OCT. 01, 2008

16

MX25L1605D

MX25L3205D

MX25L6405D

DEVICE OPERATION

1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation.

2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode until

next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z.

3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next

CS# rising edge.

4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK. The

difference of Serial mode 0 and mode 3 is shown as Figure 3.

5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, 2READ, RES, REMS and REMS2 the

shifted-ininstructionsequenceisfollowedbyadata-outsequence. Afteranybitofdatabeingshiftedout, theCS#can

be high. For the following instructions: WREN, WRDI, WRSR, SE, BE, CE, PP, CP, RDP, DP, ENSO, EXSO,and

WRSCUR, the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not

executed.

6. DuringtheprogressofWriteStatusRegister,Program,Eraseoperation,toaccessthememoryarrayisneglectedand

not affect the current operation of Write Status Register, Program, Erase.

Figure 3. Serial Modes Supported

CPOL CPHA

SCLK

(Serial mode 0)

(Serial mode 3)

0

1

0

1

SI

MSB

SO

MSB

Note:

CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not

transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is

supported.

P/N:PM1290

REV. 1.4, OCT. 01, 2008

17

MX25L1605D

MX25L3205D

MX25L6405D

COMMAND DESCRIPTION

(1) Write Enable (WREN)

The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, CP, SE,

BE,CE,andWRSR,whichareintendedtochangethedevicecontent,shouldbeseteverytimeaftertheWRENinstruction

setting the WEL bit.

The sequence of issuing WREN instruction is: CS# goes low-> sending WREN instruction code-> CS# goes high. (see

Figure12)

(2) Write Disable (WRDI)

The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.

ThesequenceofissuingWRDIinstructionis:CS#goeslow->sendingWRDIinstructioncode->CS#goeshigh.(seeFigure

13)

The WEL bit is reset by following situations:

-Power-up

- Write Disable (WRDI) instruction completion

- Write Status Register (WRSR) instruction completion

- Page Program (PP) instruction completion

- Sector Erase (SE) instruction completion

- Block Erase (BE) instruction completion

- Chip Erase (CE) instruction completion

- Continuously program mode (CP) instruction completion

(3) Read Identification (RDID)

The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC

Manufacturer ID is C2(hex), the memory type ID is 20(hex) as the first-byte device ID, and the individual device ID of

second-byte ID are listed as table of "ID Definitions".

ThesequenceofissuingRDIDinstructionis:CS#goeslow->sendingRDIDinstructioncode->24-bitsIDdataoutonSO

-> to end RDID operation can use CS# to high at any time during data out. (see Figure. 14)

While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of

program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.

P/N:PM1290

REV. 1.4, OCT. 01, 2008

18

MX25L1605D

MX25L3205D

MX25L6405D

(4) Read Status Register (RDSR)

The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in

program/erase/writestatusregistercondition)andcontinuously. ItisrecommendedtochecktheWriteinProgress(WIP)

bit before sending a new instruction when a program, erase, or write status register operation is in progress.

ThesequenceofissuingRDSRinstructionis:CS#goeslow->sendingRDSRinstructioncode->StatusRegisterdataout

on SO (see Figure. 15)

The definition of the status register bits is as below:

WIP bit. TheWriteinProgress(WIP)bit, avolatilebit, indicateswhetherthedeviceisbusyinprogram/erase/writestatus

registerprogress.WhenWIPbitsetsto1,whichmeansthedeviceisbusyinprogram/erase/writestatusregisterprogress.

When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle.

WELbit.TheWriteEnableLatch(WEL)bit, avolatilebit, indicateswhetherthedeviceissettointernalwriteenablelatch.

When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/erase/write

status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept

program/erase/writestatusregisterinstruction.Theprogram/erasecommandwillbeignoredandnotaffectvalueofWEL

bit if it is applied to a protected memory area.

BP3, BP2, BP1, BP0bits. TheBlockProtect(BP3, BP2, BP1, BP0)bits, non-volatilebits, indicatetheprotectedarea(as

defined in table 1) of the device to against the program/erase instruction without hardware protection mode being set. To

write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed.

Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE)

and Chip Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed).

ContinuouslyProgramMode(CPmode)bit.TheContinuouslyProgramModebitindicatesthestatusofCPmode, "0"

indicates not in CP mode; "1" indicates in CP mode.

SRWDbit.TheStatusRegisterWriteDisable(SRWD)bit,non-volatilebit,isoperatedtogetherwithWriteProtection(WP#/

ACC)pinforprovidinghardwareprotectionmode.ThehardwareprotectionmoderequiresSRWDsetsto1andWP#/ACC

pinsignalislowstage.Inthehardwareprotectionmode,theWriteStatusRegister(WRSR)instructionisnolongeraccepted

for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only.

StatusRegister

bit7

SRWD

bit6

Continuously

bit5

BP3

bit4

BP2

bit3

BP1

bit2

BP0

bit1

WEL

bit0

WIP

(status register program mode

(level of

(write enable

(write in

write protect)

(CP mode) protected block) protected block) protected block) protected block)

0 = normal

latch)

progress bit)

1= write

1= status

register write

disable

program mode

1= write enable

0= not write

enable

operation

0= not in write

operation

(note1)

1 = CP

mode(default 0)

volatile bit

Non- volatile bit

Non- volatile bit Non- volatile bit Non- volatile bit Non- volatile bit

volatile bit

note1: see the table "Protected Area Sizes"

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(5) Write Status Register (WRSR)

The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write

Enable(WREN)instructionmustbedecodedandexecutedtosettheWriteEnableLatch(WEL)bitinadvance.TheWRSR

instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to define the protected area of memory (as

shownintable1).TheWRSRalsocansetorresettheStatusRegisterWriteDisable(SRWD)bitinaccordancewithWrite

Protection(WP#/ACC)pinsignal.TheWRSRinstructioncannotbeexecutedoncetheHardwareProtectedMode(HPM)

is entered.

The sequence of issuing WRSR instruction is: CS# goes low-> sending WRSR instruction code-> Status Register data

on SI-> CS# goes high. (see Figure 16)

The WRSR instruction has no effect on b6, b1, b0 of the status register.

TheCS#mustgohighexactlyatthebyteboundary;otherwise, theinstructionwillberejectedandnotexecuted. Theself-

timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress

(WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing,

and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset.

Table 6. Protection Modes

Mode

Status register condition

WP# and SRWD bit status

Memory

Status register can be written

in (WEL bit is set to "1") and

the SRWD, BP0-BP3

WP#=1 and SRWD bit=0, or

WP#=0 and SRWD bit=0, or

WP#=1 and SRWD=1

Software protection

mode(SPM)

The protected area cannot

be program or erase.

bits can be changed

The SRWD, BP0-BP3 of

status register bits cannot be

changed

Hardware protection

mode (HPM)

The protected area cannot

be program or erase.

WP#=0, SRWD bit=1

Note:

1. As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in Table 1.

Astheabovetableshowing, thesummaryoftheSoftwareProtectedMode(SPM)andHardwareProtectedMode(HPM).

Software Protected Mode (SPM):

-

When SRWD bit=0, no matter WP#/ACC is low or high, the WREN instruction may set the WEL bit and can change

thevaluesofSRWD,BP3,BP2,BP1,BP0. Theprotectedarea,whichisdefinedbyBP3,BP2,BP1,BP0,isatsoftware

protected mode (SPM).

-

WhenSRWDbit=1andWP#/ACCishigh,theWRENinstructionmaysettheWELbitcanchangethevaluesofSRWD,

BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode

(SPM)

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Note: If SRWD bit=1 but WP#/ACC is low, it is impossible to write the Status Register even if the WEL bit has previously

been set. It is rejected to write the Status Register and not be executed.

HardwareProtectedMode(HPM):

-

WhenSRWDbit=1,andthenWP#/ACCislow(orWP#/ACCislowbeforeSRWDbit=1),itentersthehardwareprotected

mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2, BP1, BP0 and

hardware protected mode by the WP#/ACC to against data modification.

Note:toexitthehardwareprotectedmoderequiresWP#/ACCdrivinghighoncethehardwareprotectedmodeisentered.

If the WP#/ACC pin is permanently connected to high, the hardware protected mode can never be entered; only can use

software protected mode via BP3, BP2, BP1, BP0.

(6) Read Data Bytes (READ)

Thereadinstructionisforreadingdataout.TheaddressislatchedonrisingedgeofSCLK,anddatashiftsoutonthefalling

edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically

increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single

READ instruction. The address counter rolls over to 0 when the highest address has been reached.

The sequence of issuing READ instruction is: CS# goes low-> sending READ instruction code-> 3-byte address on SI

-> data out on SO-> to end READ operation can use CS# to high at any time during data out. (see Figure. 17)

(7) Read Data Bytes at Higher Speed (FAST_READ)

The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of

each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location.

Theaddressisautomaticallyincreasedtothenexthigheraddressaftereachbytedataisshiftedout,sothewholememory

can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has

beenreached.

The sequence of issuing FAST_READ instruction is: CS# goes low-> sending FAST_READ instruction code-> 3-byte

address on SI-> 1-dummy byte address on SI->data out on SO-> to end FAST_READ operation can use CS# to high at

any time during data out. (see Figure. 18)

While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact

on the Program/Erase/Write Status Register current cycle.

(8) 2 x I/O Read Mode (2READ)

The 2READ instruction enable double throughput of Serial Flash in read mode. The address is latched on rising edge of

SCLK, and data of every two bits(interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency

fT. The first address byte can be at any location. The address is automatically increased to the next higher address after

each byte data is shifted out, so the whole memory can be read out at a single 2READ instruction. The address counter

rollsoverto0whenthehighestaddresshasbeenreached.Oncewriting2READinstruction,thefollowingaddress/dummy/

data out will perform as 2-bit instead of previous 1-bit.

The sequence of issuing 2READ instruction is: CS# goes low→sending 2READ instruction→24-bit address interleave

on SIO1 & SIO0→ 8-bit dummy interleave on SIO1 & SIO0→ data out interleave on SIO1 & SIO0→ to end 2READ

operation can use CS# to high at any time during data out (see Figure of 2 x I/O Read Mode Timing Waveform)

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WhileProgram/Erase/WriteStatusRegistercycleisinprogress,2READinstructionisrejectedwithoutanyimpactonthe

Program/Erase/Write Status Register current cycle.

The 2 I/O only perform read operation. Program/Erase /Read ID/Read status/Read ID....operation do not support 2 I/O

throughputs.

(9) Sector Erase (SE)

The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for any

4K-bytesector. AWriteEnable(WREN)instructionmustexecutetosettheWriteEnableLatch(WEL)bitbeforesending

the Sector Erase (SE). Any address of the sector (see table 3) is a valid address for Sector Erase (SE) instruction. The

CS#mustgohighexactlyatthebyteboundary(thelatesteighthofaddressbytebeenlatched-in);otherwise,theinstruction

will be rejected and not executed.

Address bits [Am-A12] (Am is the most significant address) select the sector address.

The sequence of issuing SE instruction is: CS# goes low -> sending SE instruction code-> 3-byte address on SI -> CS#

goes high. (see Figure 22)

The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress

(WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE timing, and

sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by

BP3, BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the page.

(10) Block Erase (BE)

The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 64K-

byte sector erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit

before sending the Block Erase (BE). Any address of the block (see table 3) is a valid address for Block Erase (BE)

instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in);

otherwise, the instruction will be rejected and not executed.

The sequence of issuing BE instruction is: CS# goes low -> sending BE instruction code-> 3-byte address on SI -> CS#

goes high. (see Figure 23)

The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress

(WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tBE timing, and

sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by

BP3, BP2, BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the page.

(11) Chip Erase (CE)

TheChipErase(CE)instructionisforerasingthedataofthewholechiptobe"1".AWriteEnable(WREN)instructionmust

executetosettheWriteEnableLatch(WEL)bitbeforesendingtheChipErase(CE). Anyaddressofthesector(seetable

3)isavalidaddressforChipErase(CE)instruction. TheCS#mustgohighexactlyatthebyteboundary(thelatesteighth

of address byte been latched-in); otherwise, the instruction will be rejected and not executed.

The sequence of issuing CE instruction is: CS# goes low-> sending CE instruction code-> CS# goes high. (see Figure

24)

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The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress

(WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE timing, and sets

0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is protected by BP3,

BP2, BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when BP3, BP2, BP1,

BP0 all set to "0".

(12) Page Program (PP)

The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must

executetosettheWriteEnableLatch(WEL)bitbeforesendingthePageProgram(PP). Iftheeightleastsignificantaddress

bits(A7-A0)arenotall0,alltransmitteddatawhichgoesbeyondtheendofthecurrentpageareprogrammedfromthestart

address if the same page (from the address whose 8 least significant address bits (A7-A0) are all 0). The CS# must keep

during the whole Page Program cycle. The CS# must go high exactly at the byte boundary( the latest eighth of address

byte been latched-in); otherwise, the instruction will be rejected and not executed. If more than 256 bytes are sent to the

device, thedataofthelast256-byteisprogrammedattherequestpageandpreviousdatawillbedisregarded. Iflessthan

256bytesaresenttothedevice,thedataisprogrammedattherequestaddressofthepagewithouteffectonotheraddress

of the same page.

The sequence of issuing PP instruction is: CS# goes low-> sending PP instruction code-> 3-byte address on SI-> at least

1-byte on data on SI-> CS# goes high. (see Figure 20)

Theself-timedPageProgramCycletime(tPP)isinitiatedassoonasChipSelect(CS#)goeshigh. TheWriteinProgress

(WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and

sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by

BP3, BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed.

(13) Continuously program mode (CP mode)

TheCPmodemayenhanceprogramperformancebyautomaticallyincreasingaddresstothenexthigheraddressaftereach

byte data has been programmed.

TheContinuouslyprogram(CP)instructionisformultiplebyteprogramtoFlash. AwriteEnable(WREN)instructionmust

execute to set the Write Enable Latch(WEL) bit before sending the Continuously program (CP) instruction. CS# requires

togohighbeforeCPinstructionisexecuting. AfterCPinstructionandaddressinput,twobytesofdataisinputsequentially

fromMSB(bit7)toLSB(bit0).ThefirstbytedatawillbeprogrammedtotheinitialaddressrangewithA0=0andsecondbyte

data with A0=1. If only one byte data is input, the CP mode will not process. If more than two bytes data are input, the

additional data will be ignored and only two byte data are valid. The CP program instruction will be ignored and not affect

the WEL bit if it is applied to a protected memory area. Any byte to be programmed should be in the erase state (FF) first.

It will not roll over during the CP mode, once the last unprotected address has been reached, the chip will exit CP mode

and reset write Enable Latch bit (WEL) as "0" and CP mode bit as "0". Please check the WIP bit status if it is not in write

progress before entering next valid instruction. During CP mode, the valid commands are CP command (AD hex), WRDI

command(04hex),RDSRcommand(05hex),RDPRcommand(A1hex),andRDSCURcommand(2Bhex).AndtheWRDI

command is valid after completion of a CP programming cycle, which means the WIP bit=0.

The sequence of issuing CP instruction is : CS# high to low-> sending CP instruction code-> 3-byte address on SI-> Data

ByteonSI->CS#goeshightolow->sendingCPinstruction......->lastdesiredbyteprogrammedorsendingWriteDisable

(WRDI) instruction to end CP mode-> sending RDSR instruction to verify if CP mode is ended. (see Figure of CP mode

timingwaveform)

Three methods to detect the completion of a program cycle during CP mode:

1) Software method-I: by checking WIP bit of Status Register to detect the completion of CP mode.

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2) Software method-II: by waiting for a tBP time out to determine if it may load next valid command or not.

3) Hardware method: by writing ESRY (enable SO to output RY/BY#) instruction to detect the completion of a program

cycle during CP mode. The ESRY instruction must be executed before CP mode execution. Once it is enable in CP

mode, the CS# goes low will drive out the RY/BY# status on SO, "0" indicates busy stage, "1" indicates ready stage,

SO pin outputs tri-state if CS# goes high. DSRY (disable SO to output RY/BY#) instruction to disable the SO to output

RY/BY#andreturntostatusregisterdataoutputduringCPmode.PleasenotethattheESRY/DSRYcommandarenot

accepted unless the completion of CP mode.

(14) Deep Power-down (DP)

TheDeepPower-down(DP)instructionisforsettingthedeviceontheminimizingthepowerconsumption(toenteringthe

DeepPower-downmode), thestandbycurrentisreducedfromISB1toISB2). TheDeepPower-downmoderequiresthe

Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/

Program/Eraseinstructionareignored. WhenCS#goeshigh, it'sonlyinstandbymodenotdeeppower-downmode. It's

different from Standby mode.

The sequence of issuing DP instruction is: CS# goes low-> sending DP instruction code-> CS# goes high. (see Figure

25)

OncetheDPinstructionisset,allinstructionwillbeignoredexcepttheReleasefromDeepPower-downmode(RDP)and

ReadElectronicSignature(RES)instruction. (thoseinstructionsallowtheIDbeingreadingout). WhenPower-down, the

deeppower-downmodeautomaticallystops, andwhenpower-up, thedeviceautomaticallyisinstandbymode. ForRDP

instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in);

otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before

entering the Deep Power-down mode and reducing the current to ISB2.

(15) Release from Deep Power-down (RDP), Read Electronic Signature (RES)

TheReleasefromDeepPower-down(RDP)instructionisterminatedbydrivingChipSelect(CS#)High.WhenChipSelect

(CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Power-

downmode,thetransitiontotheStand-byPowermodeisimmediate.IfthedevicewaspreviouslyintheDeepPower-down

mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip Select (CS#) must remain High

for at least tRES2(max), as specified in Table 6. Once in the Stand-by Power mode, the device waits to be selected, so

that it can receive, decode and execute instructions.

RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID

Definitions. ThisisnotthesameasRDIDinstruction.Itisnotrecommendedtousefornewdesign.Fornewdesign,please

use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except

the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in

progress.

The sequence is shown as Figure 26,27.

The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if

continuouslysendtheadditionalclockcyclesonSCLKwhileCS#isatlow. IfthedevicewasnotpreviouslyinDeepPower-

downmode,thedevicetransitiontostandbymodeisimmediate. IfthedevicewaspreviouslyinDeepPower-downmode,

there'sadelayoftRES2totransittostandbymode,andCS#mustremaintohighatleasttRES2(max). Onceinthestandby

mode, the device waits to be selected, so it can be receive, decode, and execute instruction.

The RDP instruction is for releasing from Deep Power Down Mode.

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(16) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2)

The REMS & REMS2 instruction is an alternative to the Release from Power-down/Device ID instruction that provides

both the JEDEC assigned manufacturer ID and the specific device ID.

The REMS & REMS2 instruction is very similar to the Release from Power-down/Device ID instruction. The instruction

is initiated by driving the CS# pin low and shift the instruction code "90h" or "EFh" followed by two dummy bytes and one

bytes address (A7~A0). After which, the Manufacturer ID for MXIC (C2h) and the Device ID are shifted out on the falling

edge of SCLK with most significant bit (MSB) first as shown in figure 25. The Device ID values are listed in Table of ID

Definitions. If the one-byte address is initially set to 01h, then the device ID will be read first and then followed by the

Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The

instruction is completed by driving CS# high.

Table 7. ID Definitions

Command Type

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Manufacturer ID Memory type

Memory Density Manufacturer ID Memory type

Memory Density

16

Manufacturer ID Memory type

Memory Density

17

RDID (JEDEC ID)

C2

20

Electronic ID

14

15

C2

20

Electronic ID

15

C2

20

Electronic ID

16

RES

Manufacturer ID

C2

Device ID

14

Manufacturer ID

C2

Device ID

15

Manufacturer ID

C2

Device ID

16

REMS/REMS2

(17) Enter Secured OTP (ENSO)

The ENSO instruction is for entering the additional 512-bit secured OTP mode. The additional 512-bit secured OTP is

independentfrommainarray,whichmayusetostoreuniqueserialnumberforsystemidentifier.AfterenteringtheSecured

OTP mode, and then follow standard read or program, procedure to read out the data or update data. The Secured OTP

data cannot be updated again once it is lock-down.

The sequence of issuing ENSO instruction is: CS# goes low-> sending ENSO instruction to enter Secured OTP mode

-> CS# goes high.

PleasenotethatWRSR/WRSCURcommandsarenotacceptableduringtheaccessofsecureOTPregion,oncesecurity

OTP is lock down, only read related commands are valid.

(18) Exit Secured OTP (EXSO)

The EXSO instruction is for exiting the additional 512-bit secured OTP mode.

The sequence of issuing EXSO instruction is: CS# goes low-> sending EXSO instruction to exit Secured OTP mode->

CS# goes high.

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(19) Read Security Register (RDSCUR)

TheRDSCURinstructionisforreadingthevalueofSecurityRegisterbits. TheReadSecurityRegistercanbereadatany

time (even in program/erase/write status register/write security register condition) and continuously.

ThesequenceofissuingRDSCURinstructionis:CS#goeslow->sendingRDSCURinstruction->SecurityRegisterdata

out on SO-> CS# goes high.

The definition of the Security Register bits is as below:

Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory before ex- factory or not.

When it is "0", it indicates non- factory lock; "1" indicates factory- lock.

Lock-downSecuredOTP(LDSO)bit.BywritingWRSCURinstruction,theLDSObitmaybesetto"1" forcustomerlock-

down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 512-bit Secured OTP area cannot

be update any more. While it is in 512-bit secured OTP mode, array access is not allowed.

Table 8. Security Register Definition

bit7

bit6

bit5

bit4

x

bit3

x

bit2

x

bit1

LDSO

(indicate if Secrured OTP

bit0

x

lock-down

0 = not lock-

down

indicator bit

1 = lock-down

(cannot

0 = non-

factory lock

reserved

program/erase 1 = factory

OTP) lock

volatile bit

volatile bit non-volatile bit non-volatile bit

(20) Write Security Register (WRSCUR)

The WRSCUR instruction is for changing the values of Security Register Bits. Unlike write status register, the WREN

instructionisnotrequiredbeforesendingWRSCURinstruction. TheWRSCURinstructionmaychangethevaluesofbit1

(LDSO bit) for customer to lock-down the 512-bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP

area cannot be updated any more.

The sequence of issuing WRSCUR instruction is :CS# goes low-> sending WRSCUR instruction -> CS# goes high.

The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.

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POWER-ON STATE

The device is at below states when power-up:

- Standby mode ( please note it is not deep power-down mode)

- Write Enable Latch (WEL) bit is reset

The device must not be selected during power-up and power-down stage unless the VCC achieves below correct level:

- VCC minimum at power-up stage and then after a delay of tVSL

-GNDatpower-down

Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.

Aninternalpower-onreset(POR)circuitmayprotectthedevicefromdatacorruptionandinadvertentdatachangeduring

powerupstate.WhenVCCislowerthanVWI(PORthresholdvoltagevalue),theinternallogicisresetandtheflashdevice

has no response to any command.

For further protection on the device, after VCC reaching the VWI level, a tPUW time delay is required before the device

is fully accessible for commands like write enable(WREN), page program (PP), Continuously Program (CP), sector

erase(SE),chiperase(CE),WRSCURandwritestatusregister(WRSR).IftheVCCdoesnotreachtheVCCminimumlevel,

thecorrectoperationisnotguaranteed.Thewrite,erase,andprogramcommandshouldbesentafterthebelowtimedelay:

- tPUW after VCC reached VWI level

- tVSL after VCC reached VCC minimum level

The device can accept read command after VCC reached VCC minimum and a time delay of tVSL, even time of tPUW

has not passed.

Please refer to the figure of "power-up timing".

Note:

- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is

recommended.(generallyaround0.1uF)

- At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response to any

command. The data corruption might occur during the stage while a write, program, erase cycle is in progress.

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ELECTRICAL SPECIFICATIONS

ABSOLUTEMAXIMUMRATINGS

RATING

VALUE

AmbientOperatingTemperature

StorageTemperature

Applied Input Voltage

AppliedOutputVoltage

VCC to Ground Potential

-40°Cto85°CforIndustrialgrade

-55°Cto125°C

-0.5V to 4.6V

NOTICE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the

device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to

absolute maximum rating conditions for extended period may affect reliability.

2. Specifications contained within the following tables are subject to change.

3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see Figure

4, 5.

Figure 4.Maximum Negative Overshoot Waveform

Figure5.MaximumPositiveOvershootWaveform

20ns

Vss

Vcc + 2.0V

Vss - 2.0V

Vcc

20ns

CAPACITANCE TA = 25°C, f = 1.0 MHz

SYMBOL

PARAMETER

MIN.

TYP

MAX.

UNIT

pF

CONDITIONS

VIN = 0V

CIN

InputCapacitance

OutputCapacitance

6

8

COUT

pF

VOUT = 0V

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MX25L3205D

MX25L6405D

Figure 6. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL

Input timing referance level

Output timing referance level

0.8VCC

0.2VCC

0.7VCC

0.3VCC

AC

Measurement

Level

0.5VCC

Note: Input pulse rise and fall time are <5ns

Figure 7. OUTPUT LOADING

DEVICE UNDER

TEST

2.7K ohm

+3.3V

CL

6.2K ohm

DIODES=IN3064

OR EQUIVALENT

CL=30pF Including jig capacitance

(CL=15pF Including jig capacitance for 86MHz and 50MHz@2x I/O)

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MX25L6405D

Table 9. DC CHARACTERISTICS

(Temperature = -40°C to 85° C for Industrial grade, VCC = 2.7V ~ 3.6V)

SYMBOL PARAMETER

NOTES

MIN.

TYP MAX. UNITS

TESTCONDITIONS

VCC = VCC Max

VIN = VCC or GND

VCC = VCC Max

VIN = VCC or GND

WP#/ACC=10.5V

ILI

InputLoad

Current

1

2

uA

mA

ILO

OutputLeakage

Current

1

ILIHV

ISB1

ISB2

ICC1

HV pin input Leakage

Current

35

VCCStandby

Current

20

25

VIN = VCC or GND

CS# = VCC

DeepPower-down

Current

VIN = VCC or GND

CS# = VCC

VCCRead

f=86MHz

fT=50MHz (2 x I/O read)

SCLK=0.1VCC/0.9VCC,SO=Open

f=66MHz

20

10

20

mA

SCLK=0.1VCC/0.9VCC,SO=Open

f=33MHz

SCLK=0.1VCC/0.9VCC,SO=Open

PrograminProgress

CS# = VCC

ICC2

ICC3

VCCProgram

Current(PP)

1

VCC Write Status

Register(WRSR)

Current

Programstatusregisterinprogress

CS#=VCC

ICC4

ICC5

VHH

VCC Sector Erase

Current(SE)

1

20

mA

V

Erase in Progress

CS#=VCC

VCC Chip Erase

Current(CE)

Erase in Progress

CS#=VCC

Voltage for ACC Program/

EraseAcceleration

Input Low Voltage

9.5

10.5

VCC=2.7V~3.6V

VIL

-0.5

0.3VCC

VCC+0.4

0.4

V

VIH

VOL

VOH

Input High Voltage

OutputLowVoltage

OutputHighVoltage

0.7VCC

IOL = 1.6mA

IOH = -100uA

VCC-0.2

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MX25L1605D

MX25L3205D

MX25L6405D

Table 10. AC CHARACTERISTICS

(Temperature = -40°C to 85° C for Industrial grade, VCC = 2.7V ~ 3.6V)

Symbol

Alt.

fC

Parameter

Clock Frequency for the following instructions:

Min.

10KHz

Typ. Max.

86

Unit

fSCLK

MHz

FAST_READ, PP, SE, BE, CE, DP, RES,RDP

WREN, WRDI, RDID, RDSR, WRSR

(Condition:15pF)

66

MHz

(Condition:30pF)

fRSCLK

fTSCLK

fR

fT

Clock Frequency for READ instructions

Clock Frequency for 2READ instructions

10KHz

33

50

MHz

(Condition:15pF)

ns

tCH(1)

tCLH Clock High Time

tCLL Clock Low Time

7

tCL(1)

ns

V/ns

ns

tCLCH(2)

tCHCL(2)

tSLCH

tCHSL

tDVCH

tCHDX

tCHSH

tSHCH

tSHSL

Clock Rise Time (3) (peak to peak)

0.1

5

Clock Fall Time (3) (peak to peak)

tCSS CS# Active Setup Time (relative to SCLK)

CS# Not Active Hold Time (relative to SCLK)

tDSU Data In Setup Time

5

ns

2

ns

tDH

Data In Hold Time

5

ns

CS# Active Hold Time (relative to SCLK)

CS# Not Active Setup Time (relative to SCLK)

5

ns

5

ns

tCSH CS# Deselect Time

100

ns

tSHQZ(2) tDIS Output Disable Time

64Mb/

32Mb/

16Mb

64Mb/

32Mb/

16Mb

2.7V-3.6V

3.0V-3.6V

10

8

ns

tCLQV

tV

Clock Low to Output Valid

Output Hold Time

2.7V-3.6V

3.0V-3.6V

10

8

ns

tCLQX

tHLCH

tCHHH

tHHCH

tCHHL

tHO

0

5

ns

HOLD# Setup Time (relative to SCLK)

HOLD# Hold Time (relative to SCLK)

HOLD Setup Time (relative to SCLK)

HOLD Hold Time (relative to SCLK)

tHHQX(2) tLZ

HOLD to Output Low-Z

64Mb/

2.7V-3.6V

3.0V-3.6V

10

8

32Mb/

16Mb

64Mb/

32Mb/

16Mb

tHLQZ(2) tHZ

HOLD#toOutputHigh-Z

2.7V-3.6V

3.0V-3.6V

10

8

ns

tWHSL(4)

tSHWL(4)

tDP(2)

Write Protect Setup Time

Write Protect Hold Time

20

ns

us

100

CS#HightoDeepPower-downMode

10

8.8

tRES1(2)

tRES2(2)

CS# High to Standby Mode without Electronic Signature Read

CS# High to Standby Mode with Electronic Signature Read

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MX25L1605D

MX25L3205D

MX25L6405D

Symbol

tW

Alt.

Parameter

Min.

Typ. Max.

Unit

ms

us

ms

s

Write Status Register Cycle Time

Byte-Program

40

9

100

300

5

tBP

tPP

Page Program Cycle Time

Sector Erase Cycle Time

Block Erase Cycle Time

Chip Erase Cycle Time

1.4

60

0.7

50

25

14

tSE

300

2

tBE

tCE

64Mb

32Mb

16Mb

80

50

30

s

Notes:

1. tCH + tCL must be greater than or equal to 1/ fC. For Fast Read, tCL/tCH=5.5/5.5.

2. Value guaranteed by characterization, not 100% tested in production.

3. Expressed as a slew-rate.

4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.

5. Test condition is shown as Figure 6.

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MX25L6405D

Table 11. Power-Up Timing and VWI Threshold

Symbol

tVSL(1)

tPUW(1)

VWI(1)

Parameter

Min.

200

1

Max.

Unit

us

VCC(min) to CS# low

Time delay to Write instruction

Write Inhibit Voltage

10

ms

V

1.5

2.5

Note: 1. These parameters are characterized only.

INITIAL DELIVERY STATE

The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register

contains 00h (all Status Register bits are 0).

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MX25L1605D

MX25L3205D

MX25L6405D

Figure 8. Serial Input Timing

tSHSL

tSHCH

tCHCL

CS#

tCHSL

tSLCH

tCHSH

SCLK

tDVCH

tCHDX

tCLCH

MSB

LSB

SI

High-Z

SO

Figure 9. Output Timing

CS#

tCH

SCLK

tCLQV

tCL

tSHQZ

tCLQX

LSB

SO

SI

tQLQH

tQHQL

ADDR.LSB IN

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MX25L1605D

MX25L3205D

MX25L6405D

Figure 10. Hold Timing

CS#

tHLCH

tCHHH

tCHHL

tHLQZ

tHHCH

SCLK

tHHQX

SO

HOLD#

* SI is "don't care" during HOLD operation.

Figure 11. WP# Disable Setup and Hold Timing during WRSR when SRWD=1

WP#

tSHWL

tWHSL

CS#

0

1

2

3

4

5

6

7

8

9

10 11 12

13 14

15

SCLK

01

SI

High-Z

SO

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MX25L1605D

MX25L3205D

MX25L6405D

Figure 12. Write Enable (WREN) Sequence (Command 06)

CS#

0

1

2

3

4

5

6

7

SCLK

Command

06

SI

High-Z

SO

Figure 13. Write Disable (WRDI) Sequence (Command 04)

CS#

0

1

2

3

4

5

6

7

SCLK

Command

04

SI

High-Z

SO

Figure 14. Read Identification (RDID) Sequence (Command 9F)

CS#

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18

28 29 30 31

SCLK

SI

Command

9F

Manufacturer Identification

Device Identification

High-Z

SO

7

6

5

3

2

1

0

15 14 13

MSB

3

2

1

0

MSB

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MX25L6405D

Figure 15. Read Status Register (RDSR) Sequence (Command 05)

CS#

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

SCLK

SI

command

05

Status Register Out

High-Z

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

MSB

Figure 16. Write Status Register (WRSR) Sequence (Command 01)

CS#

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

SCLK

command

01

Status

Register In

SI

7

6

5

4

3

2

0

1

MSB

High-Z

SO

Figure 17. Read Data Bytes (READ) Sequence (Command 03)

CS#

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38 39

SCLK

command

03

24-Bit Address

23 22 21

MSB

3

2

1

0

SI

Data Out 1

Data Out 2

High-Z

2

7

6

5

4

3

1

7

0

SO

MSB

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MX25L3205D

MX25L6405D

Figure 18. Read at Higher Speed (FAST_READ) Sequence (Command 0B)

CS#

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31

SCLK

Command

0B

24 BIT ADDRESS

SI

23 22 21

3

2

1

0

High-Z

SO

CS#

47

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

SCLK

Dummy Byte

7

6

5

4

3

2

0

1

SI

DATA OUT 2

DATA OUT 1

7

6

5

4

3

2

1

0

7

6

5

4

3

2

0

1

SO

MSB

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MX25L3205D

MX25L6405D

Figure 19. 2 x I/O Read Mode Sequence (Command BB)

CS#

0

1

2

3

4

5

6

7

8

9

10 11

18 19 20 21 22 23 24 25 26 27

SCLK

data

address

BB(hex)

dummy

SI/SIO0

SO/SIO1

bit6, bit4, bit2...bit0, bit6, bit4....

bit22, bit20, bit18...bit0

High Impedance

address

bit23, bit21, bit19...bit1

data

bit7, bit5, bit3...bit1, bit7, bit5....

Figure 20. Page Program (PP) Sequence (Command 02)

CS#

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38 39

SCLK

Command

02

24-Bit Address

Data Byte 1

23 22 21

MSB

3

2

1

0

7

6

5

4

3

2

0

1

SI

MSB

CS#

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

SCLK

Data Byte 2

Data Byte 3

Data Byte 256

7

6

5

4

3

2

0

7

6

5

4

3

2

0

7

6

5

4

3

2

0

1

SI

MSB

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MX25L1605D

MX25L3205D

MX25L6405D

Figure 21. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD)

CS#

20 2122 23 24

0

1

30 31 31 32

47 48

0

7

8

0

6

7 8

0

1

6 7 8 9

SCLK

SI

Command

AD (hex)

data in

Byte n-1, Byte n

Valid

Command (1)

data in

Byte 0, Byte1

04 (hex)

05 (hex)

24-bit address

high impedance

status (2)

S0

Note: (1)DuringCPmode,thevalidcommandsareCPcommand(ADhex),WRDIcommand(04hex),RDSRcommand

(05 hex), RDPR command (A1 hex), and RDSCUR command (2B hex).

(2)Onceaninternalprogrammingoperationbegins,CS#goeslowwilldrivethestatusontheSOpinandCS#goes

high will return the SO pin to tri-state.

(3)ToendtheCPmode,eitherreachingthehighestunprotectedaddressorsendingWriteDisable(WRDI)command

(04hex)mayachieveitandthenitisrecommendedtosendRDSRcommand(05hex)toverifyifCPmodeisended

Figure 22. Sector Erase (SE) Sequence (Command 20)

CS#

0

1

2

3

4

5

6

7

8

9

29 30 31

SCLK

Command

20

24 Bit Address

SI

23 22

MSB

2

1

0

Note: SE command is 20(hex).

Figure 23. Block Erase (BE) Sequence (Command D8)

CS#

0

1

2

3

4

5

6

7

8

9

29 30 31

SCLK

Command

D8

24 Bit Address

2

SI

23 22

0

1

MSB

Note: BE command is D8(hex).

P/N:PM1290

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MX25L3205D

MX25L6405D

Figure 24. Chip Erase (CE) Sequence (Command 60 or C7)

CS#

0

1

2

3

4

5

6

7

SCLK

SI

Command

60 or C7

Note: CE command is 60(hex) or C7(hex).

Figure 25. Deep Power-down (DP) Sequence (Command B9)

CS#

t_DP

0

1

2

3

4

5

6

7

SCLK

SI

Command

B9

Stand-by Mode

Deep Power-down Mode

Figure 26. Release from Deep Power-down and Read Electronic Signature (RES) Sequence

(Command AB)

CS#

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38

SCLK

Command

AB

t

3 Dummy Bytes

RES2

SI

23 22 21

MSB

3

2

1

0

Electronic Signature Out

High-Z

7

6

5

4

3

2

0

1

SO

MSB

Deep Power-down Mode

Stand-by Mode

P/N:PM1290

REV. 1.4, OCT. 01, 2008

41

MX25L1605D

MX25L3205D

MX25L6405D

Figure 27. Release from Deep Power-down (RDP) Sequence (Command AB)

CS#

t

RES1

0

1

2

3

4

5

6

7

SCLK

Command

AB

SI

High-Z

SO

Deep Power-down Mode

Stand-by Mode

Figure 28. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF)

CS#

0

1

2

3

4

5

6

7

8

9 10

SCLK

Command

90

2 Dummy Bytes

SI

15 14 13

3

2

1

0

High-Z

SO

CS#

47

28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

SCLK

ADD (1)

7

6

5

4

3

2

0

1

SI

Manufacturer ID

Device ID

7

6

5

4

3

2

1

0

7

6

5

4

3

2

0

1

X

SO

MSB

Notes:

(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first

(2) Instruction is either 90(hex) or EF(hex).

P/N:PM1290

REV. 1.4, OCT. 01, 2008

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MX25L3205D

MX25L6405D

Figure 29. Power-up Timing

V

CC

V

(max)

CC

Program, Erase and Write Commands are Ignored

Chip Selection is Not Allowed

V

(min)

CC

tVSL

Read Command is

allowed

Device is fully

accessible

Reset State

of the

Flash

V

WI

tPUW

time

Note: VCC (max.) is 3.6V and VCC (min.) is 2.7V.

P/N:PM1290

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MX25L1605D

MX25L3205D

MX25L6405D

RECOMMENDED OPERATING CONDITIONS

AtDevicePower-Up

AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up. If

the timing in the figure is ignored, the device may not operate correctly.

VCC(min)

VCC

GND

tSHSL

tVR

CS#

tCHSL

tSLCH

tCHSH

tSHCH

SCLK

tDVCH

tCHCL

tCHDX

tCLCH

MSB IN

LSB IN

SI

High Impedance

SO

Figure A. AC Timing at Device Power-Up

Symbol

Parameter

VCC Rise Time

Notes

Min.

Max.

500000

Unit

tVR

1

20

us/V

Notes :

1. Sampled, not 100% tested.

2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "AC

CHARACTERISTICS"table.

P/N:PM1290

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MX25L1605D

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MX25L6405D

ERASE AND PROGRAMMING PERFORMANCE

PARAMETER

Min.

TYP. (1)

Max.(2)

100

300

2

UNIT

Write Status Register Cycle Time

Sector Erase Time

Block Erase Time

64Mb

40

60

ms

0.7

50

s

80

s

Chip Erase Time

32Mb

16Mb

64Mb

32Mb

16Mb

25

50

s

14

30

48

s

Chip Erase Time (at ACC mode)

15

30

s

8

18

s

Byte Program Time (via page program command)

PageProgramTime

9

300

5

us

ms

cycles

1.4

100,000

Page Program Time (at ACC mode)

Erase/ProgramCycle

5

Note:

1. Typical program and erase time assumes the following conditions: 25° C, 3.3V, and checker board pattern.

2. Under worst conditions of 85° C and 2.7V.

3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming command.

4. Erase/Program cycles comply with JEDEC JESD-47E & A117A standard.

LATCH-UP CHARACTERISTICS

MIN.

-1.0V

MAX.

10.5V

Input Voltage with respect to GND on ACC

Input Voltage with respect to GND on all power pins, SI, CS#

Input Voltage with respect to GND on SO

-1.0V

2 VCCmax

VCC + 1.0V

+100mA

-1.0V

Current

-100mA

Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.

P/N:PM1290

REV. 1.4, OCT. 01, 2008

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MX25L1605D

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MX25L6405D

ORDERING INFORMATION

PARTNO.

CLOCK

OPERATING

STANDBY Temperature PACKAGE Remark

(MHz) CURRENTMAX. CURRENTMAX.

(mA)

(uA)

MX25L1605DM2I-12G

86

25

20

-40°C~85°C 8-SOP

Pb-free

(200mil)

-40°C~85°C 16-SOP

-40°C~85°C 8-SOP

(150mil)

MX25L1605DMI-12G

MX25L1605DM1I-12G

86

25

20

Pb-free

MX25L1605DPI-12G

MX25L1605DZNI-12G

MX25L1605DZUI-12G

MX25L3205DZNI-12G

MX25L3205DM2I-12G

86

25

20

-40°C~85°C 8-PDIP

(300mil)

Pb-free

-40°C~85°C 8-WSON

(6x5mm)

-40°C~85°C 8-USON

(4x4mm)

-40°C~85°C 8-WSON

(6x5mm)

-40°C~85°C 8-SOP

(200mil)

MX25L3205DMI-12G

MX25L3205DPI-12G

86

25

20

-40°C~85°C 16-SOP

-40°C~85°C 8-PDIP

(300mil)

Pb-free

MX25L3205DZUI-12G

MX25L6405DZNI-12G

MX25L6405DMI-12G

86

25

20

-40°C~85°C 8-USON

(4x4mm)

Pb-free

-40°C~85°C 8-WSON

(8x6mm)

-40°C~85°C 16-SOP

P/N:PM1290

REV. 1.4, OCT. 01, 2008

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MX25L1605D

MX25L3205D

MX25L6405D

PART NAME DESCRIPTION

MX 25 L 1605D ZN

I

12 G

OPTION:

G: Pb-free

SPEED:

12: 86MHz

TEMPERATURE RANGE:

I: Industrial (-40˚C to 85˚C)

PACKAGE:

ZN: WSON (0.8mm package height)

ZU: USON (0.6mm package height)

M: 300mil 16-SOP

M1: 150mil 8-SOP

M2: 200mil 8-SOP

P: 300mil 8-PDIP

DENSITY & MODE:

1605D: 16Mb

3205D: 32Mb

6405D: 64Mb

TYPE:

L: 3V

DEVICE:

25: Serial Flash

P/N:PM1290

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MX25L6405D

PACKAGE INFORMATION

P/N:PM1290

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P/N:PM1290

REV. 1.4, OCT. 01, 2008

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MX25L6405D

P/N:PM1290

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P/N:PM1290

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REVISION HISTORY

RevisionNo. Description

Page

Date

1.0

1.1

1.2

1.3

1. Removed "Preliminary"

1. Dual I/O Pre-released

1. Added 8-land USON package information

1. Modified figure 4 & 5 waveform

P1

P1,3,21,31

P2,4,46,47,50 JUL/08/2008

P28

MAR/07/2008

MAY/12/2008

AUG/15/2008

2. Revised VHH spec from 11.0V(typ.)~11.5V(max.) to

9.5V(min.)~10.5V(max.)

P4,8,30,45

1.4

1. Revised sector erase time spec from 90ms(typ.) to 60ms(typ.)

2.Removed"AdvancedInformation"forMX25L3205DZUI-12G

P32,45

P46

OCT/01/2008

P/N:PM1290

REV. 1.4, OCT. 01, 2008

55

MX25L1605D

MX25L3205D

MX25L6405D

Macronix's products are not designed, manufactured, or intended for use for any high risk applications in which the failure

of a single component could cause death, personal injury, severe physical damage, or other substantial harm to persons

or property, such as life-support systems, high temperature automotive, medical, aircraft and military application. Macronix

and its suppliers will not be liable to you and/or any third party for any claims, injuries or damages that may be incurred due

to use of Macronix's products in the prohibited applications.

MACRONIX INTERNATIONALCO., LTD.

Taipei Office

Headquarters

Macronix, Int'l Co., Ltd.

16, Li-Hsin Road, Science Park,

Hsinchu, Taiwan, R.O.C.

Tel: +886-3-5786688

19F, 4, Min-Chuan E. Road, Sec. 3,

Taipei, Taiwan, R.O.C.

Tel: +886-2-2509-3300

Fax: +886-2-2509-2200

Fax: +886-3-5632888

Macronix EuropeN.V.

MacronixAmerica, Inc.

680 North McCarthy Blvd.

Milpitas, CA 95035, U.S.A.

Tel: +1-408-262-8887

Koningin Astridlaan 59, Bus 1

1780 Wemmel Belgium

Tel: +32-2-456-8020

Fax: +32-2-456-8021

Fax: +1-408-262-8810

Email: sales.northamerica@macronix.com

MacronixAsia Limited.

NKF Bldg. 5F, 1-2 Higashida-cho,

Kawasaki-ku Kawasaki-shi,

Kanagawa Pref. 210-0005, Japan

Tel: +81-44-246-9100

SingaporeOffice

Macronix Pte. Ltd.

1 Marine Parade Central

#11-03 Parkway Centre

Singapore 449408

Tel: +65-6346-5505

Fax: +65-6348-8096

Fax: +81-44-246-9105

Macronix (Hong Kong) Co., Limited.

702-703, 7/F, Building 9,

Hong Kong Science Park,

5 Science Park West Avenue, Sha Tin, N.T.

Tel: +86-852-2607-4289

Fax: +86-852-2607-4229

http : //www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.

56


型号：	MX25L1605DMI-12G
厂家：	MACRONIX INTERNATIONAL
描述：	16M-BIT [x 1 / x 2] CMOS SERIAL FLASH 16M - BIT [X 1 / X 2 ] CMOS串行闪存闪存存储内存集成电路光电二极管时钟
文件：	总56页 (文件大小：994K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MX25L1605DMI-12G [Macronix]

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