MX25L1635DMI-12G_技术文档

MX25L1635D

DATASHEET

P/N:PM1374

REV. 1.5, OCT. 01, 2008

1

MX25L1635D

Contents

FEATURES ................................................................................................................................................................. 5

GENERAL DESCRIPTION ........................................................................................................................................ 7

Table 1.Additional Feature Comparison ............................................................................................................. 7

PIN CONFIGURATIONS ............................................................................................................................................. 8

PIN DESCRIPTION .................................................................................................................................................... 8

BLOCK DIAGRAM ...................................................................................................................................................... 9

DATA PROTECTION ..................................................................................................................................................10

Table 2. Protected Area Sizes ..........................................................................................................................11

Table 3. 512-bit Secured OTP Definition ...........................................................................................................11

Memory Organization ..............................................................................................................................................12

Table 4. Memory Organization (16Mb)..............................................................................................................12

DEVICE OPERATION................................................................................................................................................13

Figure 1.Serial Modes Supported.....................................................................................................................13

COMMAND DESCRIPTION .......................................................................................................................................14

Table 5. Command Set .....................................................................................................................................14

(1)Write Enable (WREN) ..................................................................................................................................15

(2)Write Disable (WRDI) ..................................................................................................................................15

(3) Read Identification (RDID) ...........................................................................................................................15

(4) Read Status Register (RDSR) .....................................................................................................................16

(5) Write Status Register (WRSR) ....................................................................................................................17

Table 6.Protection Modes.................................................................................................................................17

(6) Read Data Bytes (READ)............................................................................................................................18

(7) Read Data Bytes at Higher Speed (FAST_READ) .......................................................................................18

(8) 2 x I/O Read Mode (2READ) .......................................................................................................................18

(9) 4 x I/O Read Mode (4READ) .......................................................................................................................19

(10) Sector Erase (SE) .....................................................................................................................................19

(11) Block Erase (BE) ......................................................................................................................................19

(12) Chip Erase (CE) ........................................................................................................................................20

(13) Page Program (PP) ...................................................................................................................................20

(14) 4 x I/O Page Program (4PP)......................................................................................................................21

(15) Continuously program mode (CP mode) .....................................................................................................21

(16) Deep Power-down (DP) .............................................................................................................................21

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MX25L1635D

(17) Release from Deep Power-down (RDP), Read Electronic Signature (RES) .................................................22

(18) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4) .............................................22

Table 7.ID Definitions.......................................................................................................................................23

(19) Enter Secured OTP (ENSO)......................................................................................................................23

(20) Exit Secured OTP (EXSO) ........................................................................................................................23

(21) Read Security Register (RDSCUR) ...........................................................................................................23

(22) Write Security Register (WRSCUR) ...........................................................................................................24

Table 8.Security Register Definition .................................................................................................................24

POWER-ON STATE ...................................................................................................................................................25

ELECTRICAL SPECIFICATIONS ..............................................................................................................................26

Figure 2.Maximum Negative Overshoot Waveform............................................................................................26

ABSOLUTE MAXIMUM RATINGS ...................................................................................................................26

CAPACITANCE TA = 25° C, f = 1.0 MHz ...........................................................................................................26

Figure 3. Maximum Positive Overshoot Waveform ............................................................................................26

Figure 5. OUTPUT LOADING..........................................................................................................................27

Figure 4.INPUTTEST WAVEFORMS AND MEASUREMENT LEVEL .............................................................27

Table 9.DC CHARACTERISTICS (Temperature = -40° C to 85°C for Industrial grade,VCC = 2.7V ~ 3.6V)........28

Table 10.AC CHARACTERISTICS (Temperature = -40° C to 85° C for Industrial grade, VCC = 2.7V ~ 3.6V) ....29

Figure 6. Serial Input Timing.............................................................................................................................30

Figure 7.OutputTiming ....................................................................................................................................30

Timing Analysis .......................................................................................................................................................30

Figure 8.WP# SetupTiming and HoldTiming during WRSR when SRWD=1 .....................................................31

Figure 9.Write Enable (WREN) Sequence (Command 06) ................................................................................31

Figure 10.Write Disable (WRDI) Sequence (Command 04) ...............................................................................31

Figure 11.Read Identification (RDID) Sequence (Command 9F) .......................................................................32

Figure 12.Read Status Register (RDSR) Sequence (Command 05) .................................................................32

Figure 13.Write Status Register (WRSR) Sequence (Command 01) ................................................................32

Figure 14.Read Data Bytes (READ) Sequence (Command 03) .......................................................................33

Figure 15.Read at Higher Speed (FAST_READ) Sequence (Command 0B) ....................................................33

Figure 16.2 x I/O Read Mode Sequence (Command BB) .................................................................................34

Figure 17.4 x I/O Read Mode Sequence (Command EB) .................................................................................34

Figure 18.4 x I/O Read enhance performance Mode Sequence (Command EB) ...............................................35

Figure 19.Page Program (PP) Sequence (Command 02).................................................................................36

Figure 20.4 x I/O Page Program (4PP) Sequence (Command 38) ...................................................................36

Figure 21.Continously Program (CP) Mode Sequence with Hardware Detection (Command AD) .......................37

Figure 22. Sector Erase (SE) Sequence (Command 20) ..................................................................................37

Figure 23.Block Erase (BE) Sequence (Command D8) ...................................................................................37

Figure 24.Chip Erase (CE) Sequence (Command 60 or C7) ............................................................................38

Figure 25.Deep Power-down (DP) Sequence (Command B9) ..........................................................................38

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MX25L1635D

Figure 26.Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB) ..38

Figure 27.Release from Deep Power-down (RDP) Sequence (Command AB) ..................................................39

Figure 28. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF).............39

Figure 29.Power-upTiming ..............................................................................................................................40

Table 11.Power-UpTiming andVWIThreshold .................................................................................................40

INITIAL DELIVERY STATE .......................................................................................................................................40

RECOMMENDED OPERATING CONDITIONS ..........................................................................................................41

ERASE AND PROGRAMMING PERFORMANCE......................................................................................................42

LATCH-UP CHARACTERISTICS ...............................................................................................................................42

ORDERING INFORMATION ......................................................................................................................................43

PART NAME DESCRIPTION .....................................................................................................................................44

PACKAGE INFORMATION.........................................................................................................................................45

REVISION HISTORY .................................................................................................................................................49

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MX25L1635D

16M-BIT [x 1/x 2/x 4] CMOS SERIAL FLASH

FEATURES

GENERAL

• Serial Peripheral Interface compatible -- Mode 0 and Mode 3

• 16M:16,777,216x1bitstructureor8,388,608x2bits(two I/Oreadmode)structureor4,194,304x4bits(four I/Oread

mode)structure

• 512 Equal Sectors with 4K byte each

- Any Sector can be erased individually

• 32 Equal Blocks with 64K byte each

- Any Block can be erased individually

• Single Power Supply Operation

- 2.7 to 3.6 volt for read, erase, and program operations

• Latch-up protected to 100mA from -1V to Vcc +1V

• Low Vcc write inhibit is from 1.5V to 2.5V

PERFORMANCE

• High Performance

- Fast read

- 1 I/O: 104MHz & 86MHz with 8 dummy cycles

- 4 I/O: 75MHz with 6 dummy cycles

- 2 I/O: 75MHz with 4 dummy cycles

- Fast access time: 104MHz & 86MHz serial clock (15pF + 1TTL Load) and 66MHz serial clock (30pF + 1TTL Load)

- Serial clock of four I/O read mode : 75MHz (15pF + TTL Load), which is equivalent to 300MHz

- Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)

- Byte program time: 9us (typical)

-Continuouslyprogrammode(automaticallyincreaseaddressunderwordprogrammode)

- Fast erase time: 60ms (typ.)/sector (4K-byte per sector) ; 0.7s(typ.) /block (64K-byte per block); 14s(typ.) /chip

• Low Power Consumption

- Low active read current: 25mA(max.) at 104MHz & 86MHz, 20mA(max.) at 66MHz and 10mA(max.) at 33MHz

- Low active programming current: 20mA (max.)

- Low active erase current: 20mA (max.)

- Low standby current: 20uA (max.)

• Typical 100,000 erase/program cycles

• 10 years data retention

SOFTWAREFEATURES

• Input Data Format

- 1-byte Command code

• Advanced Security Features

- Block lock protection

The BP0-BP3 status bit defines the size of the area to be software protection against program and erase instructions

- Additional 512-bit secured OTP for unique identifier

• Auto Erase and Auto Program Algorithm

- Automatically erases and verifies data at selected sector

- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the

program pulse widths (Any page to be programed should have page in the erased state first)

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MX25L1635D

• Status Register Feature

• Electronic Identification

- JEDEC 1-byte manufacturer ID and 2-byte device ID

- RES command for 1-byte Device ID

- Both REMS,REMS2 and REMS4 commands for 1-byte manufacturer ID and 1-byte device ID

HARDWAREFEATURES

• SCLK Input

- Serial clock input

• SI/SIO0

- Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode

• SO/SIO1

- Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode

• WP#/SIO2

- Hardware write protection or serial data Input/Output for 4 x I/O read mode

• NC/SIO3

- NC pin or serial data Input/Output for 4 x I/O read mode

• PACKAGE

- 16-pin SOP (300mil)

- 8-landWSON (6x5mm)

- 8-pin SOP (200mil, 150mil)

- All Pb-free devices are RoHS Compliant

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REV. 1.5, OCT. 01, 2008

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MX25L1635D

GENERAL DESCRIPTION

The MX25L1635D are 16,777,216 bit serial Flash memory, which is configured as 2,097,152 x 8 internally. When it is in

two or four I/O read mode, the structure becomes 8,388,608 bits x 2 or 4,194,304 bits x 4. The MX25L1635D feature a

serialperipheralinterfaceandsoftwareprotocolallowingoperationonasimple3-wirebus.Thethreebussignalsareaclock

input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input.

When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and

data output. When it is in four I/O read mode, the SI pin, SO pin, WP# pin and NC pin become SIO0 pin, SIO1 pin, SIO2

pin and SIO3 pin for address/dummy bits input and data output.

TheMX25L1635Dprovidessequentialreadoperationonwholechip.

After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified

pageorsector/blocklocationswillbeexecuted. Programcommandisexecutedonbytebasis, orpage(256bytes)basis,

orwordbasisforContinuouslyprogrammode,anderasecommandisexecutesonsector(4K-byte),orblock(64K-byte),

or whole chip basis.

To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read

command can be issued to detect completion status of a program or erase operation via WIP bit.

Advancedsecurityfeaturesenhancetheprotectionandsecurityfunctions, pleaseseesecurityfeaturessectionformore

details.

When the device is not in operation and CS# is high, it is put in standby mode and draws less than 20uA(typical:1uA) DC

current.

The MX25L1635D utilizes MXIC's proprietary memory cell, which reliably stores memory contents even after 100,000

program and erase cycles.

Table 1. Additional Feature Comparison

Read

Performance

Additional

Protection and Security

Flexible

Identifier

REMS2

Featu-

res

4 I/O

Read

RES

REMS

REMS4

RDID

2 I/O

Read

Block

512-bit

(command : (command : (command : (command : (command:

protection

(BP0-BP3)

secured OTP

(75MHz)

AB hex)

90 hex)

EF hex)

DF hex)

9F hex)

Part Name

(75MHz)

C2 24 (hex) C2 24 (hex) C2 24 (hex)

MX25L1635D

V

24 (hex)

C2 24 15 (hex)

(if ADD=0) (if ADD=0)

(if ADD=0)

X

C2 14 (hex) C2 14 (hex)

(if ADD=0) (if ADD=0)

MX25L1605D

14 (hex)

C2 20 15 (hex)

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MX25L1635D

PIN CONFIGURATIONS

16-PIN SOP (300mil)

8-PIN SOP (200mil, 150mil)

1

2

3

4

5

6

7

8

SCLK

SI/SIO0

NC

NC/SIO3

VCC

NC

16

15

14

13

12

11

10

9

1

2

3

4

CS#

SO/SIO1

WP#/SIO2

GND

VCC

8

7

6

5

NC/SIO3

SCLK

NC

SI/SIO0

NC

GND

WP#/SIO2

CS#

SO/SIO1

8-LANDWSON(6x5mm)

PIN DESCRIPTION

SYMBOL DESCRIPTION

1

2

3

4

VCC

CS#

SO/SIO1

WP#/SIO2

GND

8

7

6

5

CS#

Chip Select

NC/SIO3

SCLK

SI/SIO0

Serial Data Input (for 1 x I/O)/ Serial Data

Input & Output (for 2xI/O or 4xI/O read

mode)

SI/SIO0

SO/SIO1

SCLK

Serial Data Output (for 1 x I/O)/ Serial

Data Input & Output (for 2xI/O or 4xI/O

readmode)

Clock Input

PACKAGEOPTIONS

WP#/SIO2 Writeprotection:connecttoGNDorSerial

DataInput&Output(for4xI/Oreadmode)

16M

V

150mil8-SOP

209mil8-SOP

300mil16-SOP

6x5mmWSON

NC/SIO3

NC pin (Not connect) or Serial Data

Input & Output (for 4xI/O read mode)

+ 3.3V Power Supply

V

VCC

GND

V

Ground

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MX25L1635D

BLOCK DIAGRAM

Address

Generator

Memory Array

Page Buffer

Data

Register

SI/SIO0

Y-Decoder

SRAM

Buffer

Sense

Amplifier

CS#

WP#/SIO2

NC/SIO3

Mode

Logic

State

Machine

HV

Generator

SCLK

Clock Generator

Output

Buffer

SO/SIO1

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MX25L1635D

DATA PROTECTION

TheMX25L1635Disdesignedtoofferprotectionagainstaccidentalerasureorprogrammingcausedbyspurioussystem

level signals that may exist during power transition. During power up the device automatically resets the state machine

in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after

successful completion of specific command sequences. The device also incorporates several features to prevent

inadvertent write cycles resulting from VCC power-up and power-down transition or system noise.

•

Power-on reset and tPUW: to avoid sudden power switch by system power supply transition, the power-on reset and

tPUW (internal timer) may protect the Flash.

• Validcommandlengthchecking:Thecommandlengthwillbecheckedwhetheritisatbytebaseandcompletedonbyte

boundary.

• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other

command to change data. The WEL bit will return to reset stage under following situation:

-Power-up

- Write Disable (WRDI) command completion

- Write Status Register (WRSR) command completion

- Page Program (PP) command completion

- Sector Erase (SE) command completion

- Block Erase (BE) command completion

- Chip Erase (CE) command completion

•

Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing

allcommandsexceptReleasefromdeeppowerdownmodecommand(RDP)andReadElectronicSignaturecommand

(RES).

AdvancedSecurityFeatures:therearesomeprotectionandsecuruityfeatureswhichprotectcontentfrominadvertent

write and hostile access.

I. Block lock protection

- TheSoftwareProtectedMode(SPM)use(BP3,BP2,BP1,BP0)bitstoallowpartofmemorytobeprotectedasread

only. The proected area definition is shown as table of "Protected Area Sizes", the protected areas are more flexible

which may protect various area by setting value of BP0-BP3 bits.

Please refer to table of "protected area sizes".

- The Hardware Proteced Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and SRWD bit. If the

system goes into four I/O read mode, the feature of HPM will be disabled.

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MX25L1635D

Table 2. Protected Area Sizes

Status bit

Protect Level

16Mbit block grouping

(none)

BP3 BP2 BP1 BP0 NO.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

(1block, protected block 31th)

(2blocks, protected block 30th-31th)

(4blocks, protected block 28th-31th)

(8blocks, protected block 24th-31th)

(16blocks, protected block 16th-31th)

(32blocks, protected all)

2

3

4

5

6

(32blocks, protected all)

7

(32blocks, protected all)

8

(32blocks, protected all)

9

(16blocks, protected block 0th-15th)

(24blocks, protected block 0th-23th)

(28blocks, protected block 0th-27th)

(30blocks, protected block 0th-29th)

10

11

12

13

14

15

(31blocks, protected block 0th-30th)

(32blocks, protected all)

II. Additional 512-bit secured OTP for unique identifier: to provide 512-bit one-time program area for setting device

uniqueserialnumber-Whichmaybesetbyfactoryorsystemcustomer. Pleaserefertotable3. 512-bitsecuredOTP

definition.

- Security register bit 0 indicates whether the chip is locked by factory or not.

-Toprogramthe512-bitsecuredOTPbyentering512-bitsecuredOTPmode(withENSOcommand),andgoingthrough

normal program procedure, and then exiting 512-bit secured OTP mode by writing EXSO command.

-Customermaylock-downthecustomerlockablesecuredOTPbywritingWRSCUR(writesecurityregister)command

to set customer lock-down bit1 as "1". Please refer to table of "security register definition" for security register bit

definition and table of "512-bit secured OTP definition" for address range definition.

-Note:Oncelock-downwhateverbyfactoryorcustomer,itcannotbechangedanymore.Whilein512-bitsecuredOTP

mode, array access is not allowed.

Table 3. 512-bit Secured OTP Definition

Addressrange

xxxx00~xxxx0F

xxxx10~xxxx3F

Size

Standard

FactoryLock

CustomerLock

128-bit

384-bit

ESN (electrical serial number)

Determinedbycustomer

N/A

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MX25L1635D

Memory Organization

Table 4. Memory Organization (16Mb)

Address Range

0FF000h 0FFFFFh

Block

15

Sector

255

Address Range

1FF000h 1FFFFFh

Block

31

Sector

511

.

240

0F0000h

0EF000h

0F0FFFh

0EFFFFh

496

1F0000h

1EF000h

1F0FFFh

1EFFFFh

239

.

495

.

14

13

12

11

.

30

29

28

27

224

0E0000h

0E0FFFh

480

1E0000h

1E0FFFh

223

.

0DF000h

0DFFFFh

.

479

1DF000h

1DFFFFh

.

208

0D0000h

0D0FFFh

464

1D0000h

1D0FFFh

207

.

0CF000h

0CFFFFh

.

463

1CF000h

1CFFFFh

.

192

0C0000h

0C0FFFh

191

.

0BF000h

0BFFFFh

448

1C0000h

1C0FFFh

.

447

1BF000h

1BFFFFh

.

176

0B0000h

0B0FFFh

175

.

0AF000h

0AFFFFh

432

1B0000h

1B0FFFh

.

10

9

431

1AF000h

1AFFFFh

.

160

0A0000h

0A0FFFh

26

25

24

23

159

.

09F000h

09FFFFh

416

1A0000h

1A0FFFh

.

415

19F000h

19FFFFh

144

090000h

090FFFh

.

143

.

08F000h

08FFFFh

.

400

190000h

190FFFh

8

399

18F000h

18FFFFh

128

080000h

080FFFh

.

127

.

07F000h

07FFFFh

.

384

180000h

180FFFh

7

383

17F000h

17FFFFh

112

070000h

070FFFh

.

111

.

06F000h

06FFFFh

.

6

5

4

3

368

170000h

170FFFh

96

060000h

060FFFh

367

16F000h

16FFFFh

.

95

.

05F000h

05FFFFh

22

21

20

19

.

352

160000h

160FFFh

80

050000h

050FFFh

351

15F000h

15FFFFh

.

79

.

04F000h

04FFFFh

.

336

150000h

150FFFh

64

040000h

040FFFh

335

14F000h

14FFFFh

63

.

03F000h

03FFFFh

.

320

140000h

140FFFh

48

030000h

030FFFh

319

13F000h

13FFFFh

47

.

02F000h

02FFFFh

.

2

1

304

130000h

130FFFh

32

020000h

020FFFh

303

12F000h

12FFFFh

31

.

01F000h

01FFFFh

.

18

17

16

010000h

010FFFh

288

120000h

120FFFh

15

.

4

3

2

1

0

00F000h

00FFFFh

287

11F000h

11FFFFh

.

004000h

003000h

002000h

001000h

000000h

004FFFh

003FFFh

002FFFh

001FFFh

000FFFh

272

110000h

110FFFh

0

271

10F000h

10FFFFh

.

256

100000h

100FFFh

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MX25L1635D

DEVICE OPERATION

1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation.

2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode until

next CS# falling edge. In standby mode, all SO pins of this LSI should be High-Z.

3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next

CS# rising edge.

4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK. The

difference of Serial mode 0 and mode 3 is shown as Figure 2.

5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, 2READ, 4READ,RES, REMS, REMS2

and REMS4 the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted

out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE, CE, PP, 4PP, CP, RDP, DP,

ENSO, EXSO,and WRSCUR, the CS# must go high exactly at the byte boundary; otherwise, the instruction will be

rejected and not executed.

6. DuringtheprogressofWriteStatusRegister,Program,Eraseoperation,toaccessthememoryarrayisneglectedand

not affect the current operation of Write Status Register, Program, Erase.

Figure 1. Serial Modes Supported

CPOL CPHA

shift in

shift out

SCLK

(Serial mode 0)

(Serial mode 3)

0

1

0

1

SI

MSB

SO

MSB

Note:

CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not

transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is

supported.

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MX25L1635D

COMMAND DESCRIPTION

Table 5. Command Set

COMMAND W REN

W RDI

(write

disable)

RDID (read

identification) status

register)

RDSR (read W RSR

READ (read FAST

2READ (2 4READ (4

(byte)

(write

(write status data)

register)

READ (fast x I/O read x I/O read

read data)

enable)

command) command)

Note1

1st byte

2nd byte

06 (hex) 04 (hex)

9F (hex)

05 (hex)

01 (hex)

Values

03 (hex)

0B (hex)

AD1

BB (hex)

ADD(2)

EB (hex)

AD1(A23-

A16)

AD2 (A15- AD2

A8)

AD3 (A7-

A0)

ADD(4) &

Dummy(4)

3rd byte

4th byte

ADD(2) &

Dummy(2)

AD3

5th byte

Action

Dummy

sets the resets the outputs

to read out to write new n bytes

JEDEC ID: 1- the values values to the read out

byte of the

manufacturer status

n bytes

(W EL)

write

(W EL)

write

read out

until CS#

goes high

read out by read out by

2 x I/O until 4 x I/O until

CS# goes CS# goes

status

register

until CS#

goes high

enable

latch bit

enable

latch bit

ID & 2-byte

device ID

register

high

COMMAND 4PP (quad SE (sector BE (block CE (chip PP (Page CP

DP (Deep RDP

program) (Continuou power (Release

from deep ID)

RES (read Release

(byte)

page

erase)

electronic

Read

program)

sly

down)

Enhanced

program

mode)

power

down)

1st byte

38 (hex)

AD1

20 (hex)

D8 (hex) 60 or C7 02 (hex)

(hex)

AD (hex)

B9 (hex)

AB (hex)

FFh (hex)

2nd byte

3rd byte

4th byte

Action

AD1

AD2

AD3

AD1

AD2

AD3

AD1

AD2

AD3

AD1

AD2

AD3

x

quad input to erase

to program the

the selected selected

to erase to erase to

continously enters

program

whole chip, down mode power

release

to read out All these

the

whole

program

the

selected

page

deep power from deep 1-byte

device ID

commands

FFh,00h,AA

h or 55h will

escape the

performance

enhance

selected chip

block

page

sector

the

down mode

address is

automatical

ly increase

mode.

COMMAND REMS (read REMS2

REMS4

(read ID for

ENSO

(enter

EXSO (exit RDSCUR WRSCUR ESRY

DSRY

(disable

SO to

(byte)

electronic

(read ID for

secured

OTP)

(read

security

(write

security

(enable

SO to

manufacturer 2x I/O mode) 4x I/O mode) secured

& device ID)

OTP)

register) register)

2B (hex) 2F (hex)

output

RY/BY#)

output

RY/BY#)

1st byte

2nd byte

3rd byte

4th byte

Action

90 (hex)

EF (hex)

DF (hex)

B1 (hex) C1 (hex)

70 (hex)

80 (hex)

x

ADD (Note 2) ADD (Note 2) ADD (Note 2)

output the output the output the

manufacturer manufacturer manufacturer the 512-bit 512-bit

ID & device

ID

to enter

to exit the to read

to set the to enable to disable

value of

security

lock-down SO to

bit as "1" output

SO to

output

RY/BY#

ID & device ID & device secured

ID

secured

ID

OTP

OTP mode register

(once

RY/BY#

mode

lock-down, during CP during CP

cannot be mode

updated)

mode

Note 1: The count base is 4-bit for ADD(2) and Dummy(2) because of 2 x I/O. And the MSB is on SI/SIO1 which is different from

1 x I/O condition.

Note 2: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first.

Note 3: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden

mode.

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(1)WriteEnable(WREN)

TheWriteEnable(WREN)instructionisforsettingWriteEnableLatch(WEL)bit. ForthoseinstructionslikePP, 4PP, CP,

SE, BE, CE, and WRSR, which are intended to change the device content, should be set every time after the WREN

instruction setting the WEL bit.

The sequence of issuing WREN instruction is: CS# goes low-> sending WREN instruction code-> CS# goes high. (see

Figure9)

(2)WriteDisable(WRDI)

The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.

ThesequenceofissuingWRDIinstructionis:CS#goeslow->sendingWRDIinstructioncode->CS#goeshigh.(seeFigure

10)

The WEL bit is reset by following situations:

-Power-up

- Write Disable (WRDI) instruction completion

- Write Status Register (WRSR) instruction completion

- Page Program (PP) instruction completion

- Quad Page Program (4PP) instruction completion

- Sector Erase (SE) instruction completion

- Block Erase (BE) instruction completion

- Chip Erase (CE) instruction completion

- Continuously program mode (CP) instruction completion

(3)ReadIdentification(RDID)

The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC

Manufacturer ID is C2(hex), the memory type ID is 24(hex) as the first-byte device ID, and the individual device ID of

second-byte ID are listed as table of "ID Definitions". (see table 7 in page 26)

ThesequenceofissuingRDIDinstructionis:CS#goeslow->sendingRDIDinstructioncode->24-bitsIDdataoutonSO

-> to end RDID operation can use CS# to high at any time during data out. (see Figure 11.)

While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of

program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.

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(4)ReadStatusRegister(RDSR)

The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in

program/erase/writestatusregistercondition)andcontinuously. ItisrecommendedtochecktheWriteinProgress(WIP)

bit before sending a new instruction when a program, erase, or write status register operation is in progress.

ThesequenceofissuingRDSRinstructionis:CS#goeslow->sendingRDSRinstructioncode->StatusRegisterdataout

on SO (see Figure 12)

The definition of the status register bits is as below:

WIP bit. TheWriteinProgress(WIP)bit, avolatilebit, indicateswhetherthedeviceisbusyinprogram/erase/writestatus

registerprogress.WhenWIPbitsetsto1,whichmeansthedeviceisbusyinprogram/erase/writestatusregisterprogress.

When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle.

WELbit.TheWriteEnableLatch(WEL)bit, avolatilebit, indicateswhetherthedeviceissettointernalwriteenablelatch.

When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/erase/write

status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept

program/erase/writestatusregisterinstruction.Theprogram/erasecommandwillbeignoredandnotaffectvalueofWEL

bit if it is applied to a protected memory area.

BP3, BP2, BP1, BP0bits. TheBlockProtect(BP3, BP2, BP1, BP0)bits, non-volatilebits, indicatetheprotectedarea(as

defined in table 1) of the device to against the program/erase instruction without hardware protection mode being set. To

write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed.

Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE)

and Chip Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed).

QE bit. The Quad Enable (QE) bit, non-volatile bit, performs Quad when it is reset to "0" (factory default) to enable WP#

or is set to "1" to enable Quad SIO2 and SIO3.

SRWDbit.TheStatusRegisterWriteDisable(SRWD)bit,non-volatilebit,whichissetto"0"(factorydefault).TheSRWD

bit is operated together with Write Protection (WP#/SIO2) pin for providing hardware protection mode. The hardware

protection mode requires SRWD sets to 1 and WP#/SIO2 pin signal is low stage. In the hardware protection mode, the

Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits

(BP3, BP2, BP1, BP0) are read only.

StatusRegister

bit7

SRWD

(status register

write protect)

bit6

bit5

BP3

(level of

bit4

BP2

(level of

bit3

BP1

(level of

bit2

BP0

(level of

bit1

WEL

(write enable

bit0

WIP

(write in

progress bit)

1= write

operation

QE

(Quad Enable)

protected block) protected block) protected block) protected block)

latch)

1= Quad

Enable

1= status

register write

disable

1= write enable

0= not write

enable

(note1)

0=not Quad

Enable

0= not in write

operation

Non- volatile bit Non- volatile bit Non- volatile bit Non- volatile bit Non- volatile bit Non- volatile bit

volatile bit

Note 1: see the table 2 "Protected Area Size" in page 11.

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(5)WriteStatusRegister(WRSR)

The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write

Enable(WREN)instructionmustbedecodedandexecutedtosettheWriteEnableLatch(WEL)bitinadvance.TheWRSR

instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to define the protected area of memory (as

shown in table 1). The WRSR also can set or reset the Quad enable (QE) bit and set or reset the Status Register Write

Disable (SRWD) bit in accordance with Write Protection (WP#/SIO2) pin signal, but has no effect on bit1(WEL) and bit0

(WIP) of the statur register. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is

entered.

The sequence of issuing WRSR instruction is: CS# goes low-> sending WRSR instruction code-> Status Register data

on SI-> CS# goes high. (see Figure 13)

TheCS#mustgohighexactlyatthebyteboundary;otherwise, theinstructionwillberejectedandnotexecuted. Theself-

timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress

(WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing,

and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset.

Table 6. Protection Modes

Mode

Status register condition

WP# and SRWD bit status

Memory

Status register can be written

in (WEL bit is set to "1") and

the SRWD, BP0-BP3

WP#=1 and SRWD bit=0, or

WP#=0 and SRWD bit=0, or

WP#=1 and SRWD=1

Software protection

mode(SPM)

The protected area cannot

be program or erase.

bits can be changed

The SRWD, BP0-BP3 of

status register bits cannot be

changed

Hardware protection

mode (HPM)

The protected area cannot

be program or erase.

WP#=0, SRWD bit=1

Note:

1. As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in Table 1.

Astheabovetableshowing, thesummaryoftheSoftwareProtectedMode(SPM)andHardwareProtectedMode(HPM).

Software Protected Mode (SPM):

-

When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can change

thevaluesofSRWD,BP3,BP2,BP1,BP0. Theprotectedarea,whichisdefinedbyBP3,BP2,BP1,BP0,isatsoftware

protected mode (SPM).

-

WhenSRWDbit=1andWP#/SIO2ishigh,theWRENinstructionmaysettheWELbitcanchangethevaluesofSRWD,

BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode

(SPM)

Note:

If SRWD bit=1 but WP#/SIO2 is low, it is impossible to write the Status Register even if the WEL bit has previously been

set. It is rejected to write the Status Register and not be executed.

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HardwareProtectedMode(HPM):

-

When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware

protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2, BP1,

BP0 and hardware protected mode by the WP#/SIO2 to against data modification.

Note:

ToexitthehardwareprotectedmoderequiresWP#/SIO2drivinghighoncethehardwareprotectedmodeisentered.Ifthe

WP#/SIO2pinispermanentlyconnectedtohigh,thehardwareprotectedmodecanneverbeentered;onlycanusesoftware

protected mode via BP3, BP2, BP1, BP0.

If the system goes into four I/O read mode, the feature of HPM will be disabled.

(6)ReadDataBytes(READ)

Thereadinstructionisforreadingdataout.TheaddressislatchedonrisingedgeofSCLK,anddatashiftsoutonthefalling

edgeofSCLKatamaximumfrequencyfR.Thefirstaddresscanbeatanylocation.Theaddressisautomaticallyincreased

to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ

instruction. The address counter rolls over to 0 when the highest address has been reached.

The sequence of issuing READ instruction is: CS# goes low-> sending READ instruction code-> 3-byte address on SI

-> data out on SO-> to end READ operation can use CS# to high at any time during data out. (see Figure 14)

(7)ReadDataBytesatHigherSpeed(FAST_READ)

The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of

each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address can be at any location. The

address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory

can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has

beenreached.

The sequence of issuing FAST_READ instruction is: CS# goes low-> sending FAST_READ instruction code-> 3-byte

address on SI-> 1-dummy byte address on SI->data out on SO-> to end FAST_READ operation can use CS# to high at

any time during data out. (see Figure 15)

While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact

on the Program/Erase/Write Status Register current cycle.

(8) 2 x I/O Read Mode (2READ)

The 2READ instruction enable double throughput of Serial Flash in read mode. The address is latched on rising edge of

SCLK, and data of every two bits(interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency

fT. The first address can be at any location. The address is automatically increased to the next higher address after each

byte data is shifted out, so the whole memory can be read out at a single 2READ instruction. The address counter rolls

overto0whenthehighestaddresshasbeenreached.Oncewriting2READinstruction,thefollowingaddress/dummy/data

out will perform as 2-bit instead of previous 1-bit.

The sequence of issuing 2READ instruction is: CS# goes low→sending 2READ instruction→24-bit address interleave

on SIO1 & SIO0→4 dummy cycles on SIO1 & SIO0→data out interleave on SIO1 & SIO0→to end 2READ operation

can use CS# to high at any time during data out (see Figure 16 for 2 x I/O Read Mode Timing Waveform).

WhileProgram/Erase/WriteStatusRegistercycleisinprogress, 2READinstructionisrejectedwithoutanyimpactonthe

Program/Erase/Write Status Register current cycle.

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(9) 4 x I/O Read Mode (4READ)

The 4READ instruction enable quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status Register

mustbesetto"1"beforesedingthe4READinstruction.TheaddressislatchedonrisingedgeofSCLK, anddataofevery

four bits(interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ. The first address can

be at any location. The address is automatically increased to the next higher address after each byte data is shifted out,

sothewholememorycanbereadoutatasingle4READinstruction.Theaddresscounterrollsoverto0whenthehighest

addresshasbeenreached. Oncewriting4READinstruction, thefollowingaddress/dummy/dataoutwillperformas4-bit

instead of previous 1-bit.

The sequence of issuing 4READ instruction is: CS# goes low→sending 4READ instruction→24-bit address interleave

on SIO3, SIO2, SIO1 & SIO0→6 dummy cycles →data out interleave on SIO3, SIO2, SIO1 & SIO0→to end 4READ

operation can use CS# to high at any time during data out (see Figure 17 for 4 x I/O Read Mode Timing Waveform).

Anothersequenceofissuing4READinstructionespeciallyusefulinrandomaccessis:CS#goeslow→sending4READ

instruction→24-bitaddressinterleaveonSIO3, SIO2, SIO1&SIO0→performanceenhancetogglingbitP[7:0]→4dummy

cycles→dataoutinterleaveonSIO3,SIO2,SIO1andSIO0tillCS#goeshigh→CS#goeslow(reduce4Readinstruction)

→24-bit random access address (see figure 18 for 4x I/O read enhance performance mode timing waveform).

Intheperformance-enhancingmode(NoteofFigure.18),P[7:4]mustbetogglingwithP[3:0];likewiseP[7:0]=A5h,5Ah,F0h

or0Fhcanmakethismodecontinueandreducethenext4READinstruction.OnceP[7:4]isnolongertogglingwithP[3:0];

likewiseP[7:0]=FFh,00h,AAhor55h. AndafterwardsCS#israisedorissuingFFcommand(CS#goeshigh->CS#goes

low->sending0xFF->CS#goeshigh)insteadofnotoggling,thesystemthenwillescapefromperformanceenhancemode

and return to normal opertaion.In these cases,tSHSL=15ns(min) will be specified.

WhileProgram/Erase/WriteStatusRegistercycleisinprogress,4READinstructionisrejectedwithoutanyimpactonthe

Program/Erase/Write Status Register current cycle.

(10) Sector Erase (SE)

The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for any

4K-bytesector. AWriteEnable(WREN)instructionmustexecutetosettheWriteEnableLatch(WEL)bitbeforesending

the Sector Erase (SE). Any address of the sector (see table 3) is a valid address for Sector Erase (SE) instruction. The

CS# must go high exactly at the byte boundary (the eighth bit of last address byte been latched-in); otherwise, the

instruction will be rejected and not executed.

Address bits [Am-A12] (Am is the most significant address) select the sector address.

The sequence of issuing SE instruction is: CS# goes low -> sending SE instruction code-> 3-byte address on SI -> CS#

goes high. (see Figure 22)

The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress

(WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE timing, and

sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by

BP3, BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the page.

(11)BlockErase(BE)

The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 64K-

byteblockeraseoperation.AWriteEnable(WREN)instructionmustexecutetosettheWriteEnableLatch(WEL)bitbefore

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MX25L1635D

sending the Block Erase (BE). Any address of the block (see table 3) is a valid address for Block Erase (BE) instruction.

The CS# must go high exactly at the byte boundary (the eighth bit of address byte been latched-in); otherwise, the

instruction will be rejected and not executed.

The sequence of issuing BE instruction is: CS# goes low -> sending BE instruction code-> 3-byte address on SI -> CS#

goes high. (see Figure 23)

The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress

(WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tBE timing, and

sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by

BP3, BP2, BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the page.

(12) Chip Erase (CE)

TheChipErase(CE)instructionisforerasingthedataofthewholechiptobe"1".AWriteEnable(WREN)instructionmust

execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must go high exactly at

the byte boundary (the eighth bit of address byte been latched-in), otherwise the instruction will be rejected and not

executed.

The sequence of issuing CE instruction is: CS# goes low-> sending CE instruction code-> CS# goes high. (see Figure

24)

The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress

(WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE timing, and

sets0whenChipEraseCycleiscompleted, andtheWriteEnableLatch(WEL)bitisreset. Ifthechipisprotectedby BP3,

BP2, BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when BP3, BP2, BP1,

BP0 all set to "0".

(13) Page Program (PP)

The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must

execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device programs only the

last 256 data bytes sent to the device. If the entire 256 data bytes are going to be programmed, A7-A0 (The eight least

significant address bits) should be set to 0. If the eight least significant address bits (A7-A0) are not all 0, all transmitted

datagoingbeyondtheendofthecurrentpageareprogrammedfromthestartaddressofthesamepage(fromtheaddress

A7-A0areall0). Ifmorethan256bytesaresenttothedevice, thedataofthelast256-byteisprogrammedattherequest

page and previous data will be disregarded. If less than 256 bytes are sent to the device, the data is programmed at the

requested address of the page without effect on other address of the same page.

ThesequenceofissuingPPinstructionis:CS#goeslow->sendingPPinstructioncode->3-byteaddressonSI->atleast

1-byte on data on SI-> CS# goes high. (see Figure 19)

The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte boundary(

the eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed.

Theself-timedPageProgramCycletime(tPP)isinitiatedassoonasChipSelect(CS#)goeshigh. TheWriteinProgress

(WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and

sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected

by BP3, BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed.

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(14) 4 x I/O Page Program (4PP)

TheQuadPageProgram(4PP)instructionisforprogrammingthememorytobe"0". AWriteEnable(WREN)instruction

must execute to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1" before sending the

QuadPageProgram(4PP). TheQuadPageProgrammingtakesfourpins:SIO0, SIO1, SIO2, andSIO3asaddressand

datainput,whichcanimproveprogramerperformanceandtheeffectivenessofapplicationoflowerclocklessthan20MHz.

For system with faster clock, the Quad page program cannot provide more actual favors, because the required internal

page program time is far more than the time data flows in. Therefore, we suggest that while executing this command

(especially during sending data), user can slow the clock speed down to 20MHz below. The other function descriptions

are as same as standard page program.

Thesequenceofissuing4PPinstructionis:CS#goeslow->sending4PPinstructioncode->3-byteaddressonSIO[3:0]-

> at least 1-byte on data on SIO[3:0]-> CS# goes high. (see Figure 20)

(15) Continuously program mode (CP mode)

The CP mode may enhance program performance by automatically increasing address to the next higher address after

each byte data has been programmed.

TheContinuouslyprogram(CP)instructionisformultiplebyteprogramtoFlash.AwriteEnable(WREN)instructionmust

executetosettheWriteEnableLatch(WEL)bitbeforesendingtheContinuouslyprogram(CP)instruction. CS#requires

togohighbeforeCPinstructionisexecuting. AfterCPinstructionandaddressinput,twobytesofdataisinputsequentially

from MSB(bit7) to LSB(bit0). The first byte data will be programmed to the initial address range with A0=0 (or A0=1) and

secondbytedatawithA0=1(orA0=0). Ifonlyonebytedataisinput, theCPmodewillnotprocess. Ifmorethantwobytes

dataareinput,theadditionaldatawillbeignoredandonlytwobytedataarevalid.TheCPprograminstructionwillbeignored

and not affect the WEL bit if it is applied to a protected memory area. Any byte to be programmed should be in the erase

state (FF) first. It will not roll over during the CP mode, once the last unprotected address has been reached, the chip will

exit CP mode and reset write Enable Latch bit (WEL) as "0" and CP mode bit as "0". Please check the WIP bit status

ifitisnotinwriteprogressbeforeenteringnextvalidinstruction. DuringCPmode, thevalidcommandsareCPcommand

(ADhex),WRDIcommand(04hex),RDSRcommand(05hex),andRDSCURcommand(2Bhex).AndtheWRDIcommand

is valid after completion of a CP programming cycle, which means the WIP bit=0.

The sequence of issuing CP instruction is : CS# high to low -> sending CP instruction code -> 3-byte address on SI pin

->twodatabytesonSI->CS#goeshightolow->sendingCPinstructionandthencontinue twodatabytesareprogrammed

->CS#goeshightolow->tilllastdesiredtwodatabytesareprogrammed->CS#goeshightolow->sendingWRDI(Write

Disable)instruction toendCPmode->sendRDSRinstructiontoverifyifCPmodewordprogramends,orsendRDSCUR

to check bit4 to verify if CP mode ends. (see Figure21 of CP mode timing waveform)

Three methods to detect the completion of a program cycle during CP mode:

1) Software method-I: by checking WIP bit of Status Register to detect the completion of CP mode.

2) Software method-II: by waiting for a tBP time out to determine if it may load next valid command or not.

3) Hardware method: by writing ESRY (enable SO to output RY/BY#) instruction to detect the completion of a program

cycle during CP mode. The ESRY instruction must be executed before CP mode execution. Once it is enable in CP

mode, the CS# goes low will drive out the RY/BY# status on SO, "0" indicates busy stage, "1" indicates ready stage,

SOpinoutputstri-stateifCS#goeshigh. DSRY(disableSOtooutputRY/BY#)instructiontodisabletheSOtooutput

RY/BY#andreturntostatusregisterdataoutputduringCPmode.PleasenotethattheESRY/DSRYcommandarenot

accepted unless the completion of CP mode.

(16)DeepPower-down(DP)

TheDeepPower-down(DP)instructionisforsettingthedeviceontheminimizingthepowerconsumption(toenteringthe

DeepPower-downmode), thestandbycurrentisreducedfromISB1toISB2). TheDeepPower-downmoderequiresthe

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Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/

Program/Eraseinstructionareignored. WhenCS#goeshigh, it'sonlyinstandbymodenotdeeppower-downmode. It's

different from Standby mode.

The sequence of issuing DP instruction is: CS# goes low-> sending DP instruction code-> CS# goes high. (see Figure

25)

OncetheDPinstructionisset,allinstructionwillbeignoredexcepttheReleasefromDeepPower-downmode(RDP)and

ReadElectronicSignature(RES)instruction. (thoseinstructionsallowtheIDbeingreadingout). WhenPower-down, the

deeppower-downmodeautomaticallystops, andwhenpower-up, thedeviceautomaticallyisinstandbymode. ForRDP

instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in);

otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before

enteringtheDeepPower-downmode.

(17)ReleasefromDeepPower-down(RDP), ReadElectronicSignature(RES)

TheReleasefromDeepPower-down(RDP)instructionisterminatedbydrivingChipSelect(CS#)High.WhenChipSelect

(CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Power-

downmode,thetransitiontotheStand-byPowermodeisimmediate.IfthedevicewaspreviouslyintheDeepPower-down

mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip Select (CS#) must remain High

foratleasttRES2(max),asspecifiedinTable10.ACCharacteristics.OnceintheStand-byPowermode,thedevicewaits

tobeselected,sothatitcanreceive,decodeandexecuteinstructions.TheRDPinstructionisonlyforreleasingfromDeep

PowerDownMode.

RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID

Definitions in next page. This is not the same as RDID instruction. It is not recommended to use for new design. For new

design, please use RDID instruction.

The sequence is shown as Figure 26,27. Even in Deep power-down mode, the RDP and RES are also allowed to be

executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/

erase/write cycle in progress.

The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if

continuouslysendtheadditionalclockcyclesonSCLKwhileCS#isatlow. IfthedevicewasnotpreviouslyinDeepPower-

downmode,thedevicetransitiontostandbymodeisimmediate. IfthedevicewaspreviouslyinDeepPower-downmode,

there'sadelayoftRES2totransittostandbymode,andCS#mustremaintohighatleasttRES2(max). Onceinthestandby

mode, the device waits to be selected, so it can be receive, decode, and execute instruction.

(18) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4)

The REMS, REMS2 & REMS4 instruction is an alternative to the Release from Power-down/Device ID instruction that

providesboththeJEDECassignedmanufacturerIDandthespecificdeviceID. TheREMS4instructionisrecommended

to use for 4 I/O identification and REMS2 instruction is recommended to use for 2 I/O identification.

The REMS, REMS2 & REMS4 instruction is very similar to the Release from Power-down/Device ID instruction. The

instruction is initiated by driving the CS# pin low and shift the instruction code "90h" or "EFh" or "DFh"followed by two

dummy bytes and one bytes address (A7~A0). After which, the Manufacturer ID for MXIC (C2h) and the Device ID are

shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in figure 31. The Device ID values

are listed in Table 7 of ID Definitions in next page. If the one-byte address is initially set to 01h, then the device ID will

be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously,

alternating from one to the other. The instruction is completed by driving CS# high.

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MX25L1635D

Table 7. ID Definitions

Command Type

MX25L1635D

Manufacturer ID Memory type

Memory Density

15

RDID (JEDEC ID)

RES

C2

24

Electronic ID

24

REMS/REMS2/

REMS4

Manufacturer ID

C2

Device ID

24

(19) Enter Secured OTP (ENSO)

The ENSO instruction is for entering the additional 512-bit secured OTP mode. The additional 512-bit secured OTP is

independentfrommainarray,whichmayusetostoreuniqueserialnumberforsystemidentifier.AfterenteringtheSecured

OTP mode, and then follow standard read or program, procedure to read out the data or update data. The Secured OTP

data cannot be updated again once it is lock-down.

The sequence of issuing ENSO instruction is: CS# goes low-> sending ENSO instruction to enter Secured OTP mode

-> CS# goes high.

PleasenotethatWRSR/WRSCURcommandsarenotacceptableduringtheaccessofsecureOTPregion,oncesecurity

OTP is lock down, only read related commands are valid.

(20) Exit Secured OTP (EXSO)

The EXSO instruction is for exiting the additional 512-bit secured OTP mode.

The sequence of issuing EXSO instruction is: CS# goes low-> sending EXSO instruction to exit Secured OTP mode->

CS# goes high.

(21)ReadSecurityRegister(RDSCUR)

TheRDSCURinstructionisforreadingthevalueofSecurityRegisterbits. TheReadSecurityRegistercanbereadatany

time (even in program/erase/write status register/write security register condition) and continuously.

ThesequenceofissuingRDSCURinstructionis:CS#goeslow->sendingRDSCURinstruction->SecurityRegisterdata

out on SO-> CS# goes high.

The definition of the Security Register bits is as below:

Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory before ex- factory or not.

When it is "0", it indicates non- factory lock; "1" indicates factory- lock.

Lock-downSecuredOTP(LDSO)bit.BywritingWRSCURinstruction,theLDSObitmaybesetto"1" forcustomerlock-

down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 512-bit Secured OTP area cannot

be update any more. While it is in 512-bit secured OTP mode, main array access is not allowed.

ContinuouslyProgramMode(CPmode)bit. TheContinuouslyProgramModebitindicatesthestatusofCPmode, "0"

indicates not in CP mode; "1" indicates in CP mode.

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MX25L1635D

Table 8. Security Register Definition

bit7

x

bit6

x

bit5

x

bit4

bit3

x

bit2

x

bit1

LDSO

bit0

Continuously

Program mode

(CP mode)

(indicate if Secrured OTP

lock-down

0 = not lock-

down

1 = lock-down

(cannot

indicator bit

0=normal

Program mode

1=CP mode

(default=0)

0 = non-

factory lock

reserved

program/erase 1 = factory

OTP) lock

volatile bit

volatile bit non-volatile bit non-volatile bit

(22)WriteSecurityRegister(WRSCUR)

The WRSCUR instruction is for changing the values of Security Register Bits. Unlike write status register, the WREN

instructionisnotrequiredbeforesendingWRSCURinstruction. TheWRSCURinstructionmaychangethevaluesofbit1

(LDSO bit) for customer to lock-down the 512-bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP

area cannot be updated any more.

The sequence of issuing WRSCUR instruction is :CS# goes low-> sending WRSCUR instruction -> CS# goes high.

The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.

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MX25L1635D

POWER-ON STATE

The device is at below states when power-up:

- Standby mode ( please note it is not deep power-down mode)

- Write Enable Latch (WEL) bit is reset

The device must not be selected during power-up and power-down stage unless the VCC achieves below correct level:

- VCC minimum at power-up stage and then after a delay of tVSL

-GNDatpower-down

Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.

Aninternalpower-onreset(POR)circuitmayprotectthedevicefromdatacorruptionandinadvertentdatachangeduring

powerupstate.WhenVCCislowerthanVWI(PORthresholdvoltagevalue),theinternallogicisresetandtheflashdevice

has no response to any command.

For further protection on the device, after VCC reaching the VWI level, a tPUW time delay is required before the device

is fully accessible for commands like write enable(WREN), page program (PP), quad page program (4PP), continuously

program(CP),sectorerase(SE),blockerase(BE),chiperase(CE),WRSCURandwritestatusregister(WRSR).IftheVCC

doesnotreachtheVCCminimumlevel,thecorrectoperationisnotguaranteed.Thewrite,erase,andprogramcommand

should be sent after the below time delay:

- tPUW after VCC reached VWI level

- tVSL after VCC reached VCC minimum level

The device can accept read command after VCC reached VCC minimum and a time delay of tVSL, even time of tPUW

has not passed.

Please refer to the figure of "power-up timing".

Note:

- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended.

(generallyaround0.1uF)

- At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response to any

command. The data corruption might occur during the stage while a write, program, erase cycle is in progress.

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25

MX25L1635D

ELECTRICAL SPECIFICATIONS

ABSOLUTEMAXIMUMRATINGS

RATING

VALUE

AmbientOperatingTemperature

StorageTemperature

Applied Input Voltage

AppliedOutputVoltage

VCC to Ground Potential

-40°Cto85°CforIndustrialgrade

-55°Cto125°C

-0.5V to 4.6V

NOTICE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the

device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to

absolute maximum rating conditions for extended period may affect reliability.

2. Specifications contained within the following tables are subject to change.

3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see Figure

2, 3.

Figure 3. Maximum Positive Overshoot Waveform

Figure2.MaximumNegativeOvershootWaveform

20ns

Vss

Vcc + 2.0V

Vss - 2.0V

Vcc

20ns

CAPACITANCE TA = 25° C, f = 1.0 MHz

SYMBOL

CIN

PARAMETER

MIN.

TYP

MAX.

UNIT

pF

CONDITIONS

VIN = 0V

InputCapacitance

OutputCapacitance

6

8

COUT

pF

VOUT = 0V

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MX25L1635D

Figure 4. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL

Input timing referance level

0.8VCC

Output timing referance level

0.7VCC

AC

Measurement

Level

0.5VCC

0.3VCC

0.2VCC

Note: Input pulse rise and fall time are <5ns

Figure 5. OUTPUT LOADING

DEVICE UNDER

TEST

2.7K ohm

+3.3V

CL

6.2K ohm

DIODES=IN3064

OR EQUIVALENT

CL=30pF Including jig capacitance

(CL=15pF Including jig capacitance for 86MHz & 104MHz, 75MHz@2xI/O and 75MHz@4xI/O)

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MX25L1635D

Table 9. DC CHARACTERISTICS (Temperature = -40° C to 85° C for Industrial grade, VCC = 2.7V ~ 3.6V)

SYMBOL PARAMETER

NOTES

MIN.

TYP MAX. UNITS

TESTCONDITIONS

VCC = VCC Max

ILI

InputLoad

Current

1

2

uA

mA

VIN = VCC or GND

VCC = VCC Max

ILO

OutputLeakage

Current

1

2

VIN = VCC or GND

CS# = VCC

ISB1

ISB2

ICC1

VCCStandby

Current

1

20

DeepPower-down

Current

20

25

VIN = VCC or GND

CS# = VCC

VCCRead

1

f=86MHzand104MHz

fQ=75MHz (4 x I/O read)

SCLK=0.1VCC/0.9VCC,SO=Open

f=66MHz

20

mA

fT=75MHz (2 x I/O read)

SCLK=0.1VCC/0.9VCC,SO=Open

f=33MHz

10

20

mA

SCLK=0.1VCC/0.9VCC,SO=Open

PrograminProgress

CS# = VCC

ICC2

ICC3

VCCProgram

1

Current(PP)

VCC Write Status

Register(WRSR)

Current

Programstatusregisterinprogress

CS#=VCC

ICC4

ICC5

VCC Sector Erase

Current(SE)

1

20

mA

Erase in Progress

CS#=VCC

VCC Chip Erase

Current(CE)

Erase in Progress

CS#=VCC

VIL

Input Low Voltage

Input High Voltage

OutputLowVoltage

OutputHighVoltage

-0.5

0.3VCC

VCC+0.4

0.4

V

VIH

VOL

VOH

0.7VCC

IOL = 1.6mA

IOH = -100uA

VCC-0.2

Notes :

1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds).

2. Typical value is calculated by simulation.

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MX25L1635D

Table 10. AC CHARACTERISTICS (Temperature = -40° C to 85° C for Industrial grade, VCC = 2.7V ~ 3.6V)

Symbol

Alt.

Parameter

Min.

Typ. Max.

Unit

fSCLK

fC

Clock Frequency for the following instructions:

FAST_READ, PP, SE, BE, CE, DP, RES,RDP

WREN, WRDI, RDID, RDSR, WRSR

D.C.

86 & 104 MHz

(Condition:15pF)

D.C.

66

MHz

(Condition:30pF)

fRSCLK

fTSCLK

fR

fT

Clock Frequency for READ instructions

Clock Frequency for 2READ instructions

Clock Frequency for 4READ instructions

33

75

MHz

fQ

(Condition:15pF)

ns

tCH(1)

tCLH Clock High Time

tCLL Clock Low Time

4.8

0.1

5

tCL(1)

ns

V/ns

ns

us

ms

us

ms

s

tCLCH(2)

tCHCL(2)

tSLCH

tCHSL

tDVCH

tCHDX

tCHSH

tSHCH

Clock Rise Time (3) (peak to peak)

Clock Fall Time (3) (peak to peak)

tCSS CS# Active Setup Time (relative to SCLK)

CS# Not Active Hold Time (relative to SCLK)

tDSU Data In Setup Time

5

2

tDH

Data In Hold Time

5

CS# Active Hold Time (relative to SCLK)

CS# Not Active Setup Time (relative to SCLK)

5

tSHSL(3) tCSH CS# Deselect Time

Read

15

50

Write/Erase/Program

2.7V-3.6V

tSHQZ(2) tDIS Output Disable Time

10

8

3.0V-3.6V

tCLQV

tV

Clock Low to Output Valid

Loading:30pF/15pF

2.7V-3.6V

10/8

8/6

3.0V-3.6V

tCLQX

tWHSL(4)

tSHWL(4)

tDP(2)

tRES1(2)

tRES2(2)

tW

tHO

Output Hold Time

0

Write Protect Setup Time

Write Protect Hold Time

CS#HightoDeepPower-downMode

20

100

10

8.8

100

300

5

CS# High to Standby Mode without Electronic Signature Read

CS# High to Standby Mode with Electronic Signature Read

Write Status Register Cycle Time

Byte-Program

40

9

tBP

tPP

Page Program Cycle Time

1.4

60

0.7

14

tSE

Sector Erase Cycle Time

300

2

tBE

Block Erase Cycle Time

tCE

Chip Erase Cycle Time

30

s

Notes:

1. tCH + tCL must be greater than or equal to 1/ fC

2. Value guaranteed by characterization, not 100% tested in production.

3. tSHSL=15ns from read instruction, tSHSL=50ns from Write/Erase/Program instruction.

4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.

5. Test condition is shown as Figure 4, 5.

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MX25L1635D

Timing Analysis

Figure 6. Serial Input Timing

tSHSL

tSHCH

tCHCL

CS#

tCHSL

tSLCH

tCHSH

SCLK

tDVCH

tCHDX

tCLCH

MSB

LSB

SI

High-Z

SO

Figure 7. Output Timing

CS#

tCH

SCLK

tCLQV

tCL

tSHQZ

tCLQX

SO

tCLQX

LSB

tQLQH

tQHQL

ADDR.LSB IN

SI

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MX25L1635D

Figure 8. WP# Setup Timing and Hold Timing during WRSR when SRWD=1

WP#

tSHWL

tWHSL

CS#

0

1

2

3

4

5

6

7

8

9

10 11 12

13 14

15

SCLK

01

SI

High-Z

SO

Figure 9. Write Enable (WREN) Sequence (Command 06)

CS#

0

1

2

3

4

5

6

7

SCLK

Command

06

SI

High-Z

SO

Figure 10. Write Disable (WRDI) Sequence (Command 04)

CS#

0

1

2

3

4

5

6

7

SCLK

Command

04

SI

High-Z

SO

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MX25L1635D

Figure 11. Read Identification (RDID) Sequence (Command 9F)

CS#

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18

28 29 30 31

SCLK

SI

Command

9F

Manufacturer Identification

Device Identification

High-Z

SO

7

6

5

3

2

1

0

15 14 13

MSB

3

2

1

0

MSB

Figure12. ReadStatusRegister(RDSR)Sequence(Command05)

CS#

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

SCLK

SI

command

05

Status Register Out

High-Z

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

MSB

Figure 13. Write Status Register (WRSR) Sequence (Command 01)

CS#

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

SCLK

command

01

Status

Register In

SI

7

6

5

4

3

2

0

1

MSB

High-Z

SO

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MX25L1635D

Figure 14. Read Data Bytes (READ) Sequence (Command 03)

CS#

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38 39

SCLK

command

03

24-Bit Address

23 22 21

MSB

3

2

1

0

SI

Data Out 1

Data Out 2

High-Z

2

7

6

5

4

3

1

7

0

SO

MSB

Figure 15. Read at Higher Speed (FAST_READ) Sequence (Command 0B)

CS#

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31

SCLK

Command

0B

24 BIT ADDRESS

SI

23 22 21

3

2

1

0

High-Z

SO

CS#

47

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

SCLK

Configurable

Dummy Cycle

7

6

5

4

3

2

0

1

SI

DATA OUT 2

DATA OUT 1

7

6

5

4

3

2

1

0

7

6

5

4

3

2

0

1

SO

MSB

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MX25L1635D

Figure 16. 2 x I/O Read Mode Sequence (Command BB)

CS#

0

1

2

3

4

5

6

7

8

9

10 11

18 19 20 21 22 23 24 25 26 27

SCLK

4 dummy

cycle

8 Bit Instruction

12 BIT Address

Data Output

data

address

BB(hex)

dummy

SI/SIO0

bit6, bit4, bit2...bit0, bit6, bit4....

bit22, bit20, bit18...bit0

High Impedance

address

bit23, bit21, bit19...bit1

data

SO/SIO1

bit7, bit5, bit3...bit1, bit7, bit5....

Figure 17. 4 x I/O Read Mode Sequence (Command EB)

CS#

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23

SCLK

6 dummy

cycle

8 Bit Instruction

EB(hex)

6 Address cycles

Data Output

data

bit4, bit0, bit4....

address

bit20, bit16..bit0

dummy

SI/SIO0

High Impedance

address

data

dummy

SO/SIO1

WP#/SIO2

NC/SIO3

bit21, bit17..bit1

bit5 bit1, bit5....

address

bit22, bit18..bit2

data

bit6 bit2, bit6....

address

bit23, bit19..bit3

data

bit7 bit3, bit7....

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MX25L1635D

Figure 18. 4 x I/O Read enhance performance Mode Sequence (Command EB)

CS#

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23

n

SCLK

4 dummy

cycles

8 Bit Instruction

EB(hex)

6 Address cycles

Data Output

Performance

enhance

indicator (Note)

data

bit4, bit0, bit4....

address

bit20, bit16..bit0

P4 P0

P5 P1

P6 P2

P7 P3

SI/SIO0

High Impedance

address

bit21, bit17..bit1

data

bit5 bit1, bit5....

SO/SIO1

WP#/SIO2

NC/SIO3

address

bit22, bit18..bit2

data

bit6 bit2, bit6....

address

bit23, bit19..bit3

data

bit7 bit3, bit7....

CS#

n+1

...........

n+7......n+9 ........... n+13

...........

SCLK

4 dummy

cycles

6 Address cycles

address

Data Output

Performance

enhance

indicator (Note)

data

bit4, bit0, bit4....

P4 P0

P5 P1

P6 P2

P7 P3

SI/SIO0

bit20, bit16..bit0

address

bit21, bit17..bit1

data

bit5 bit1, bit5....

SO/SIO1

WP#/SIO2

NC/SIO3

address

bit22, bit18..bit2

data

bit6 bit2, bit6....

address

bit23, bit19..bit3

data

bit7 bit3, bit7....

Note: Performance enhance mode, if P7=P3 & P6=P2 & P5=P1 & P4=P0 (Toggling), ex: A5, 5A, 0F

Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF

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MX25L1635D

Figure 19. Page Program (PP) Sequence (Command 02)

CS#

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38 39

SCLK

Command

02

24-Bit Address

Data Byte 1

23 22 21

MSB

3

2

1

0

7

6

5

4

3

2

0

1

SI

MSB

CS#

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

SCLK

Data Byte 2

Data Byte 3

Data Byte 256

7

6

5

4

3

2

0

7

6

5

4

3

2

0

7

6

5

4

3

2

0

1

SI

MSB

Figure 20. 4 x I/O Page Program (4PP) Sequence (Command 38)

CS#

10 11 12 13 14 15 16 17 18 19 20 21

Data Data Data Data

0

1

2

3

4

5

6

7

8

9

SCLK

Command

38

6 Address cycle

Byte 1 Byte 2 Byte 3 Byte 4

16 12

8

9

4

0

20

4

0

4

0

4

0

4

0

SI/SIO0

21 17 13

5

6

7

1

2

3

SO/SIO1

WP#/SIO2

NC/SIO3

5

6

7

1

2

3

5

6

7

1

2

3

5

6

7

1

2

3

5

6

7

1

2

3

22 18 14 10

23 19 15 11

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Figure 21. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD)

CS#

SCLK

SI

20 2122 23 24

0

1

30 31 31 32

47 48

0

7

8

0

6

7 8

0

1

6 7 8 9

Command

AD (hex)

data in

Byte n-1, Byte n

Valid

Command (1)

data in

04 (hex)

05 (hex)

24-bit address

Byte 0, Byte1

high impedance

status (2)

S0

Note: (1)DuringCPmode,thevalidcommandsareCPcommand(ADhex),WRDIcommand(04hex),RDSRcommand

(05 hex), and RDSCUR command (2B hex).

(2)Onceaninternalprogrammingoperationbegins,CS#goeslowwilldrivethestatusontheSOpinandCS#goes

high will return the SO pin to tri-state.

(3)ToendtheCPmode,eitherreachingthehighestunprotectedaddressorsendingWriteDisable(WRDI)command

(04 hex) may achieve it and then it is recommended to send RDSCUR command (2B hex) to verify if CP mode is

ended

Figure 22. Sector Erase (SE) Sequence (Command 20)

CS#

0

1

2

3

4

5

6

7

8

9

29 30 31

SCLK

Command

20

24 Bit Address

SI

23 22

MSB

2

1

0

Note: SE command is 20(hex).

Figure 23. Block Erase (BE) Sequence (Command D8)

CS#

0

1

2

3

4

5

6

7

8

9

29 30 31

SCLK

Command

D8

24 Bit Address

SI

23 22

MSB

2

0

1

Note: BE command is D8(hex).

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MX25L1635D

Figure 24. Chip Erase (CE) Sequence (Command 60 or C7)

CS#

0

1

2

3

4

5

6

7

SCLK

SI

Command

60 or C7

Note: CE command is 60(hex) or C7(hex).

Figure 25. Deep Power-down (DP) Sequence (Command B9)

CS#

t_DP

0

1

2

3

4

5

6

7

SCLK

SI

Command

B9

Stand-by Mode

Deep Power-down Mode

Figure 26. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB)

CS#

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38

SCLK

Command

AB

t

3 Dummy Bytes

RES2

SI

23 22 21

MSB

3

2

1

0

Electronic Signature Out

High-Z

7

6

5

4

3

2

0

1

SO

MSB

Deep Power-down Mode

Stand-by Mode

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REV. 1.5, OCT. 01, 2008

38

MX25L1635D

Figure 27. Release from Deep Power-down (RDP) Sequence (Command AB)

CS#

t

RES1

0

1

2

3

4

5

6

7

SCLK

SI

Command

AB

High-Z

SO

Deep Power-down Mode

Stand-by Mode

Figure 28. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF)

CS#

0

1

2

3

4

5

6

7

8

9 10

SCLK

Command

90

2 Dummy Bytes

SI

15 14 13

3

2

1

0

High-Z

SO

CS#

47

28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

SCLK

ADD (1)

7

6

5

4

3

2

0

1

SI

Manufacturer ID

Device ID

7

6

5

4

3

2

1

0

7

6

5

4

3

2

0

1

X

SO

MSB

Notes:

(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first

(2) Instruction is either 90(hex) or EF(hex) or DF(hex).

P/N:PM1374

REV. 1.5, OCT. 01, 2008

39

MX25L1635D

Figure 29. Power-up Timing

V

CC

V

(max)

CC

Program, Erase and Write Commands are Ignored

Chip Selection is Not Allowed

V

(min)

CC

tVSL

Read Command is

allowed

Device is fully

accessible

Reset State

of the

Flash

V

WI

tPUW

time

Note: VCC (max.) is 3.6V and VCC (min.) is 2.7V.

Table 11. Power-Up Timing and VWI Threshold

Symbol

tVSL(1)

tPUW(1)

VWI(1)

Parameter

Min.

200

1

Max.

Unit

us

VCC(min) to CS# low

Time delay to Write instruction

Write Inhibit Voltage

10

ms

V

1.5

2.5

Note: 1. These parameters are characterized only.

INITIAL DELIVERY STATE

The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register

contains 00h (all Status Register bits are 0).

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REV. 1.5, OCT. 01, 2008

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MX25L1635D

RECOMMENDED OPERATING CONDITIONS

AtDevicePower-Up

AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up. If

the timing in the figure is ignored, the device may not operate correctly.

VCC(min)

VCC

GND

tSHSL

tVR

CS#

tCHSL

tSLCH

tCHSH

tSHCH

SCLK

tDVCH

tCHCL

tCHDX

tCLCH

MSB IN

LSB IN

SI

High Impedance

SO

Figure A. AC Timing at Device Power-Up

Symbol

Parameter

VCC Rise Time

Notes

Min.

Max.

500000

Unit

tVR

1

20

us/V

Notes :

1. Sampled, not 100% tested.

2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "AC

CHARACTERISTICS"table.

P/N:PM1374

REV. 1.5, OCT. 01, 2008

41

MX25L1635D

ERASE AND PROGRAMMING PERFORMANCE

PARAMETER

Min.

TYP. (1)

Max.(2)

100

300

2

UNIT

ms

s

Write Status Register Cycle Time

Sector Erase Time

40

60

Block Erase Time

0.7

Chip Erase Time

14

30

s

Byte Program Time (via page program command)

PageProgramTime

9

300

5

us

1.4

ms

cycles

Erase/ProgramCycle

100,000

Note:

1. Typical program and erase time assumes the following conditions: 25° C, 3.3V, and checker board pattern.

2. Under worst conditions of 85° C and 2.7V.

3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming command.

4. Themaximumchipprogrammingtimeisevaluatedundertheworstconditionsof0C, VCC=3.0V, and100Kcyclewith

90% confidence level.

LATCH-UP CHARACTERISTICS

MIN.

-1.0V

MAX.

Input Voltage with respect to GND on all power pins, SI, CS#

Input Voltage with respect to GND on SO

2 VCCmax

VCC + 1.0V

+100mA

-1.0V

Current

-100mA

Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.

P/N:PM1374

REV. 1.5, OCT. 01, 2008

42

MX25L1635D

ORDERING INFORMATION

PARTNO.

CLOCK

OPERATING

STANDBY Temperature PACKAGE Remark

(MHz) CURRENTMAX. CURRENTMAX.

(mA)

25

(uA)

20

MX25L1635DMI-12G

MX25L1635DM1I-12G

86

-40°C~85°C 16-SOP

-40°C~85°C 8-SOP

(150mil)

Pb-free

25

20

MX25L1635DM2I-12G

MX25L1635DZNI-12G

MX25L1635DM2I-10G

86

25

20

-40°C~85°C 8-SOP

(200mil)

Pb-free

-40°C~85°C 8-WSON

(6x5mm)

104

-40°C~85°C 8-SOP

(200mil)

P/N:PM1374

REV. 1.5, OCT. 01, 2008

43

MX25L1635D

PART NAME DESCRIPTION

MX 25 L 1635D ZN

I

12 G

OPTION:

G: Pb-free

SPEED:

12: 86MHz

10: 104MHz

TEMPERATURE RANGE:

I: Industrial (-40˚ C to 85˚ C)

PACKAGE:

ZN: WSON

M: 300mil 16-SOP

M1: 150mil 8-SOP

M2: 200mil 8-SOP

DENSITY & MODE:

1635D: 16Mb standard type

TYPE:

L: 3V

DEVICE:

25: Serial Flash

P/N:PM1374

REV. 1.5, OCT. 01, 2008

44

MX25L1635D

PACKAGE INFORMATION

P/N:PM1374

REV. 1.5, OCT. 01, 2008

45

MX25L1635D

P/N:PM1374

REV. 1.5, OCT. 01, 2008

46

MX25L1635D

P/N:PM1374

REV. 1.5, OCT. 01, 2008

47

MX25L1635D

P/N:PM1374

REV. 1.5, OCT. 01, 2008

48

MX25L1635D

REVISION HISTORY

RevisionNo. Description

Page

Date

1.0

1.1

1. Removed "Advanced Information" on page 1

1.Correctedwording

2. Added the description of SRWD bit for factory default

1. Correct typo

1. Changed tSHSL spec from 30/50ns to 15/50ns

P1

P10,18,19

P16

P13,19,20

P29

FEB/27/2008

APR/18/2008

1.2

1.3

APR/24/2008

JUL/08/2008

2. Modified the performance enhance mode reset function description P19,35

3. Added 8-SOP 104MHz solution

P5,27,28,29,

P43,44

P29

P14

P19

4. Changed tCH/tCL spec from 5.5/5.5 (ns) to 5/5 (ns)

1. tCH(1), tCL(1) change from 5ns to 4.8ns

2. Added "Release Read Enhance mode" in cmd set table

3. Rewrite 4xI/O Read performance enhance mode process flow

description

1.4

1.5

AUG/06/2008

OCT/01/2008

4. Modified figure 2 & 3 waveform

1. Revised sector erase time spec from 90ms(typ.) to 60ms(typ.)

P26

P5,42

2. Revised sector erase time spec from 120ms(max.) to 300ms(max.) P29

3. Revised block erase time spec from 1s(typ.) to 0.7s(typ.)

P29

P/N:PM1374

REV. 1.5, OCT. 01, 2008

49

MX25L1635D

Macronix's products are not designed, manufactured, or intended for use for any high risk applications in which the failure

of a single component could cause death, personal injury, severe physical damage, or other substantial harm to persons

or property, such as life-support systems, high temperature automotive, medical, aircraft and military application. Macronix

and its suppliers will not be liable to you and/or any third party for any claims, injuries or damages that may be incurred due

to use of Macronix's products in the prohibited applications.

MACRONIX INTERNATIONALCO., LTD.

Taipei Office

Headquarters

Macronix, Int'l Co., Ltd.

16, Li-Hsin Road, Science Park,

Hsinchu, Taiwan, R.O.C.

Tel: +886-3-5786688

19F, 4, Min-Chuan E. Road, Sec. 3,

Taipei, Taiwan, R.O.C.

Tel: +886-2-2509-3300

Fax: +886-2-2509-2200

Fax: +886-3-5632888

Macronix EuropeN.V.

MacronixAmerica, Inc.

680 North McCarthy Blvd.

Milpitas, CA 95035, U.S.A.

Tel: +1-408-262-8887

Koningin Astridlaan 59, Bus 1

1780 Wemmel Belgium

Tel: +32-2-456-8020

Fax: +32-2-456-8021

Fax: +1-408-262-8810

Email: sales.northamerica@macronix.com

MacronixAsia Limited.

NKF Bldg. 5F, 1-2 Higashida-cho,

Kawasaki-ku Kawasaki-shi,

Kanagawa Pref. 210-0005, Japan

Tel: +81-44-246-9100

SingaporeOffice

Macronix Pte. Ltd.

1 Marine Parade Central

#11-03 Parkway Centre

Singapore 449408

Tel: +65-6346-5505

Fax: +65-6348-8096

Fax: +81-44-246-9105

Macronix (Hong Kong) Co., Limited.

702-703, 7/F, Building 9,

Hong Kong Science Park,

5 Science Park West Avenue, Sha Tin, N.T.

Tel: +86-852-2607-4289

Fax: +86-852-2607-4229

http : //www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.

50


型号：	MX25L1635DMI-12G
厂家：	MACRONIX INTERNATIONAL
描述：	16M-BIT [x 1/x 2/x 4] CMOS SERIAL FLASH 16M - BIT [ ×1 / ×2 / ×4 ] CMOS串行闪存闪存存储内存集成电路光电二极管时钟
文件：	总50页 (文件大小：728K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MX25L1635DMI-12G [Macronix]

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