MX25L1675EZNI-10G_技术文档

MX25L1675E

HIGH PERFORMANCE

SERIAL FLASH SPECIFICATION

P/N: PM1850

REV. 1.2, NOV. 11, 2013

1

MX25L1675E

Contents

1. FEATURES ........................................................................................................................................................ 4

2. GENERAL DESCRIPTION ............................................................................................................................... 6

Table 1. Additional Feature.....................................................................................................................6

3. PIN CONFIGURATION ...................................................................................................................................... 7

4. PIN DESCRIPTION............................................................................................................................................ 7

5. BLOCK DIAGRAM............................................................................................................................................. 8

6. DATA PROTECTION.......................................................................................................................................... 9

Table 2. Protected Area Sizes..............................................................................................................10

Table 3. 512-bit Secured OTP Deﬁnition..............................................................................................10

7. MEMORY ORGANIZATION..............................................................................................................................11

Table 4. Memory Organization .............................................................................................................11

8. DEVICE OPERATION...................................................................................................................................... 12

9. COMMAND DESCRIPTION............................................................................................................................. 13

Table 5. Command Sets.......................................................................................................................13

9-1. Write Enable (WREN)..........................................................................................................................15

9-2. Write Disable (WRDI)...........................................................................................................................16

9-3. Read Identiﬁcation (RDID)...................................................................................................................17

9-4. Read Status Register (RDSR).............................................................................................................18

9-5. Write Status Register (WRSR).............................................................................................................20

Table 6. Protection Modes....................................................................................................................21

9-6. Read Data Bytes (READ) ....................................................................................................................23

9-7. Read Data Bytes at Higher Speed (FAST_READ) ..............................................................................24

9-8. Dual Read Mode (DREAD)..................................................................................................................25

9-9. 2 x I/O Read Mode (2READ) ...............................................................................................................26

9-10. Quad Read Mode (QREAD) ................................................................................................................27

9-11. 4 x I/O Read Mode (4READ) ...............................................................................................................28

9-12. Performance Enhance Mode...............................................................................................................29

9-13. Performance Enhance Mode Reset (FFh)...........................................................................................29

9-14. Sector Erase (SE)................................................................................................................................32

9-15. Block Erase (BE) .................................................................................................................................33

9-16. Chip Erase (CE)...................................................................................................................................34

9-17. Page Program (PP) .............................................................................................................................35

9-18. 4 x I/O Page Program (4PP)................................................................................................................36

9-19. Deep Power-down (DP).......................................................................................................................37

9-20. Release from Deep Power-down (RDP), Read Electronic Signature (RES) .......................................38

9-21. Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4) .....................................40

9-22. ID Read................................................................................................................................................41

Table 7. ID Deﬁnitions .........................................................................................................................41

9-23. Enter Secured OTP (ENSO)................................................................................................................41

9-24. Exit Secured OTP (EXSO)...................................................................................................................41

9-25. Read Security Register (RDSCUR).....................................................................................................42

Table 8. Security Register Deﬁnition ....................................................................................................42

9-26. Write Security Register (WRSCUR).....................................................................................................43

9-27. Read SFDP Mode (RDSFDP)..............................................................................................................44

Table 9. Signature and Parameter Identiﬁcation Data Values .............................................................45

P/N: PM1850

REV. 1.2, NOV. 11, 2013

2

MX25L1675E

Table 10. Parameter Table (0): JEDEC Flash Parameter Tables.........................................................46

Table 11. Parameter Table (1): Macronix Flash Parameter Tables.......................................................48

10. POWER-ON STATE....................................................................................................................................... 50

11. ELECTRICAL SPECIFICATIONS.................................................................................................................. 51

11-1. Absolute Maximum Ratings.................................................................................................................51

11-2. Capacitance.........................................................................................................................................51

Table 12. DC Characteristics................................................................................................................53

Table 13. AC Characteristics................................................................................................................54

12. TIMING ANALYSIS ........................................................................................................................................ 55

Table 14. Power-Up Timing .................................................................................................................56

12-1. Initial Delivery State.............................................................................................................................56

13. OPERATING CONDITIONS........................................................................................................................... 57

14. ERASE AND PROGRAMMING PERFORMANCE........................................................................................ 59

15. DATA RETENTION ........................................................................................................................................ 59

16. LATCH-UP CHARACTERISTICS.................................................................................................................. 59

17. ORDERING INFORMATION.......................................................................................................................... 60

18. PART NAME DESCRIPTION......................................................................................................................... 61

19. REVISION HISTORY ..................................................................................................................................... 64

P/N: PM1850

REV. 1.2, NOV. 11, 2013

3

MX25L1675E

16M-BIT [x 1/x 2/x 4] CMOS MXSMIO^®(SERIAL MULTI I/O) FLASH MEMORY

1. FEATURES

GENERAL

• Serial Peripheral Interface compatible -- Mode 0 and Mode 3

• 16,777,216 x 1 bit structure or 8,388,608 x 2 bits (two I/O read mode) structure or 4,194,304 x 4 bits (four I/O

read mode) structure

• 512 Equal Sectors with 4K byte each

- Any Sector can be erased individually

• 32 Equal Blocks with 64K byte each

- Any Block can be erased individually

• Single Power Supply Operation

- 2.7 to 3.6 volt for read, erase, and program operations

• Latch-up protected to 100mA from -1V to Vcc +1V

• Default QE=1 (4 I/O) before factory shipping

PERFORMANCE

• High Performance

- Fast read

- 1 I/O: 104MHz with 8 dummy cycles

- 2 I/O: 85MHz with 4 dummy cycles

- 4 I/O: 85MHz with 6 dummy cycles

- Fast access time: 104MHz serial clock

- Serial clock of four I/O read mode : 85MHz, which is equivalent to 340MHz

- Fast program time: 0.6ms(typ.) and 3ms(max.)/page (256-byte per page)

- Byte program time: 9us (typical)

- Fast erase time: 40ms (typ.)/sector (4K-byte per sector) ; 0.4s(typ.) /block (64K-byte per block); 5s(typ.) /chip

• Low Power Consumption

- Low active read current: 25mA(max.) at 104MHz and 10mA(max.) at 33MHz

- Low active programming current: 15mA (typ.)

- Low active sector erase current: 9mA (typ.)

- Low standby current: 15uA (typ.)

• Typical 100,000 erase/program cycles

• 20 years data retention

P/N: PM1850

REV. 1.2, NOV. 11, 2013

4

MX25L1675E

SOFTWARE FEATURES

• Input Data Format

- 1-byte Command code

• Advanced Security Features

- Block lock protection

The BP0-BP3 status bit deﬁnes the size of the area to be software protection against program and erase

instructions

- Additional 512-bit secured OTP for unique identiﬁer

• Auto Erase and Auto Program Algorithm

- Automatically erases and veriﬁes data at selected sector

- Automatically programs and veriﬁes data at selected page by an internal algorithm that automatically times the

program pulse widths (Any page to be programed should have page in the erased state ﬁrst)

• Status Register Feature

• Electronic Identiﬁcation

- JEDEC 1-byte manufacturer ID and 2-byte device ID

- RES command for 1-byte Device ID

- Both REMS,REMS2 and REMS4 commands for 1-byte manufacturer ID and 1-byte device ID

• Support Serial Flash Discoverable Parameters (SFDP) mode

HARDWARE FEATURES

• SCLK Input

- Serial clock input

• SI/SIO0

- Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode

• SO/SIO1

- Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode

• WP#/SIO2

- Hardware write protection or serial data Input/Output for 4 x I/O read mode

• NC/SIO3

- NC pin or serial data Input/Output for 4 x I/O read mode

• PACKAGE

8-pin SOP (200mil)

8-WSON (6x5mm)

-

- All devices are RoHS Compliant & Halogen-free.

P/N: PM1850

REV. 1.2, NOV. 11, 2013

5

MX25L1675E

2. GENERAL DESCRIPTION

The MX25L1675E are 16,777,216 bit serial Flash memory, which is conﬁgured as 2,097,152 x 8 internally. When it

is in two or four I/O read mode, the structure becomes 8,388,608 bits x 2 or 4,194,304 bits x 4. The MX25L1675E

feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus

signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device

is enabled by CS# input.

When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input

and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# pin and NC pin become SIO0 pin, SIO1

pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output.

The MX25L1675E provides sequential read operation on whole chip.

After program/erase command is issued, auto program/erase algorithms which program/erase and verify the speci-

ﬁed page or sector/block locations will be executed. Program command is executed on byte basis, or page (256

bytes) basis, and erase command is executes on sector (4K-byte), or block (64K-byte), or whole chip basis.

To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read

command can be issued to detect completion status of a program or erase operation via WIP bit.

Advanced security features enhance the protection and security functions, please see security features section for

more details.

When the device is not in operation and CS# is high, it is put in standby mode.

The MX25L1675E utilizes Macronix proprietary memory cell, which reliably stores memory contents even after

100,000 program and erase cycles.

Table 1. Additional Feature

Protection and

Security

Read

Performance

Identiﬁer

Additional

Features

Flexible

Block

Protection secured

512-bit

RES

REMS

REMS2

REMS4

RDID

2 I/O

4 I/O

Part

Name

(command: (command: (command: (command: (command:

Read

(BP0-

BP3)

OTP

AB hex)

90 hex)

EF hex)

DF hex)

9F hex)

C2 24 (hex) C2 24 (hex) C2 24 (hex) C2 24 15

(if ADD=0) (if ADD=0) (if ADD=0) (hex)

MX25L1675E

V

24 (hex)

P/N: PM1850

REV. 1.2, NOV. 11, 2013

6

MX25L1675E

3. PIN CONFIGURATION

8-PIN SOP (200mil)

4. PIN DESCRIPTION

SYMBOL DESCRIPTION

CS#

Chip Select

Serial Data Input (for 1 x I/O)/ Serial

Data Input & Output (for 2xI/O or 4xI/

O read mode)

1

2

3

4

CS#

SO/SIO1

WP#/SIO2

GND

VCC

8

7

6

5

NC/SIO3

SCLK

SI/SIO0

Serial Data Output (for 1 x I/O)/

Serial Data Input & Output (for 2xI/O

or 4xI/O read mode)

SO/SIO1

SCLK

Clock Input

8-WSON (6x5mm)

Write protection: connect to GND or

1

2

3

4

VCC

CS#

SO/SIO1

WP#/SIO2

GND

WP#/SIO2 Serial Data Input & Output (for 4xI/O

8

7

6

5

NC/SIO3

SCLK

read mode)

NC pin (Not connect) or Serial Data

Input & Output (for 4xI/O read mode)

NC/SIO3

SI/SIO0

VCC

GND

+ 3.3V Power Supply

Ground

P/N: PM1850

REV. 1.2, NOV. 11, 2013

7

MX25L1675E

5. BLOCK DIAGRAM

Address

Generator

Memory Array

Page Buffer

Y-Decoder

Data

Register

SI/SIO0

SRAM

Buffer

Sense

Amplifier

CS#

WP#/SIO2

NC#/SIO3

Mode

Logic

State

Machine

HV

Generator

SCLK

Clock Generator

Output

Buffer

SO/SIO1

P/N: PM1850

REV. 1.2, NOV. 11, 2013

8

MX25L1675E

6. DATA PROTECTION

During power transition, there may be some false system level signals which result in inadvertent erasure or pro-

gramming. The device is designed to protect itself from these accidental write cycles.

The state machine will be reset as standby mode automatically during power up. In addition, the control register ar-

chitecture of the device constrains that the memory contents can only be changed after speciﬁc command sequenc-

es have completed successfully.

In the following, there are several features to protect the system from the accidental write cycles during VCC power-

up and power-down or from system noise.

•

Valid command length checking: The command length will be checked whether it is at byte base and completed

on byte boundary.

Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before

other command to change data. The WEL bit will return to reset stage under following situation:

- Power-up

- Write Disable (WRDI) command completion

- Write Status Register (WRSR) command completion

- Page Program (PP, 4PP) command completion

- Sector Erase (SE) command completion

- Block Erase (BE) command completion

- Chip Erase (CE) command completion

•

Deep Power Down Mode: By entering deep power down mode, the ﬂash device also is under protected from

writing all commands except Release from deep power down mode command (RDP) and Read Electronic Sig-

nature command (RES).

Advanced Security Features: there are some protection and securuity features which protect content from inad-

vertent write and hostile access.

I. Block lock protection

- The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected

as read only. The proected area deﬁnition is shown as table of "Protected Area Sizes", the protected areas are

more ﬂexible which may protect various area by setting value of BP0-BP3 bits.

Please refer to table of "protected area sizes".

- The Hardware Proteced Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and SRWD bit.

If the system goes into four I/O read mode, the feature of HPM will be disabled.

P/N: PM1850

REV. 1.2, NOV. 11, 2013

9

MX25L1675E

Table 2. Protected Area Sizes

Status bit

Protect Level

BP0 16Mb

BP3

0

BP2

0

BP1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0 (none)

0

1 (1block, protected block 31th)

2 (2blocks, protected block 30th-31th)

3 (4blocks, protected block 28th-31th)

4 (8blocks, protected block 24th-31th)

0

1

0

1

0

1

0

1

0

5 (16blocks, protected block 16th-31th)

6 (32blocks, protected all)

0

1

0

1

7 (32blocks, protected all)

1

0

8 (32blocks, protected all)

1

0

9 (32blocks, protected all)

1

0

1

10 (16blocks, protected block 0th-15th)

11 (24blocks, protected block 0th-23th)

12 (28blocks, protected block 0th-27th)

13 (30blocks, protected block 0th-29th)

14 (31blocks, protected block 0th-30th)

15 (32blocks, protected all)

1

0

1

0

1

0

1

II. Additional 512-bit secured OTP for unique identiﬁer: to provide 512-bit one-time program area for setting de-

vice unique serial number - Which may be set by factory or system customer. Please refer to "Table 3. 512-bit

Secured OTP Deﬁnition"

- Security register bit 0 indicates whether the chip is locked by factory or not.

- To program the 512-bit secured OTP by entering 512-bit secured OTP mode (with ENSO command), and going

through normal program procedure, and then exiting 512-bit secured OTP mode by writing EXSO command.

- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register) com-

mand to set customer lock-down bit1 as "1". Please refer to table of "security register deﬁnition" for security reg-

ister bit deﬁnition and table of "512-bit secured OTP deﬁnition" for address range deﬁnition.

- Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 512-bit secured

OTP mode, array access is not allowed.

Table 3. 512-bit Secured OTP Deﬁnition

Address range

xxxx00~xxxx0F

xxxx10~xxxx3F

Size

Standard Factory Lock

ESN (electrical serial number)

N/A

Customer Lock

128-bit

384-bit

Determined by customer

P/N: PM1850

REV. 1.2, NOV. 11, 2013

10

MX25L1675E

7. MEMORY ORGANIZATION

Table 4. Memory Organization

Block

Sector

255

:

Address Range

0FF000h 0FFFFFh

Block

Sector

511

:

Address Range

1FF000h 1FFFFFh

15

:

31

:

240

239

:

224

223

:

208

207

:

192

191

:

176

175

:

160

159

:

144

143

:

128

127

:

112

111

:

96

95

:

80

79

:

64

63

:

48

47

:

32

31

:

16

15

:

0F0000h

0EF000h

:

0E0000h

0DF000h

:

0D0000h

0CF000h

:

0C0000h

0BF000h

:

0B0000h

0AF000h

:

0A0000h

09F000h

:

090000h

08F000h

:

080000h

07F000h

:

070000h

06F000h

:

060000h

05F000h

:

050000h

04F000h

:

040000h

03F000h

:

030000h

02F000h

:

020000h

01F000h

:

010000h

00F000h

:

0F0FFFh

0EFFFFh

:

0E0FFFh

0DFFFFh

:

0D0FFFh

0CFFFFh

:

0C0FFFh

0BFFFFh

:

0B0FFFh

0AFFFFh

:

0A0FFFh

09FFFFh

:

090FFFh

08FFFFh

:

080FFFh

07FFFFh

:

070FFFh

06FFFFh

:

060FFFh

05FFFFh

:

050FFFh

04FFFFh

:

040FFFh

03FFFFh

:

030FFFh

02FFFFh

:

020FFFh

01FFFFh

:

010FFFh

00FFFFh

:

496

495

:

480

479

:

464

463

:

448

447

:

432

431

:

416

415

:

400

399

:

384

383

:

368

367

:

352

351

:

336

335

:

320

319

:

304

303

:

288

287

:

272

271

:

1F0000h

1EF000h

:

1E0000h

1DF000h

:

1D0000h

1CF000h

:

1C0000h

1BF000h

:

1B0000h

1AF000h

:

1A0000h

19F000h

:

190000h

18F000h

:

180000h

17F000h

:

170000h

16F000h

:

160000h

15F000h

:

150000h

14F000h

:

140000h

13F000h

:

130000h

12F000h

:

120000h

11F000h

:

110000h

10F000h

:

1F0FFFh

1EFFFFh

:

1E0FFFh

1DFFFFh

:

1D0FFFh

1CFFFFh

:

1C0FFFh

1BFFFFh

:

1B0FFFh

1AFFFFh

:

1A0FFFh

19FFFFh

:

190FFFh

18FFFFh

:

180FFFh

17FFFFh

:

170FFFh

16FFFFh

:

160FFFh

15FFFFh

:

150FFFh

14FFFFh

:

140FFFh

13FFFFh

:

130FFFh

12FFFFh

:

120FFFh

11FFFFh

:

110FFFh

10FFFFh

:

14

13

12

11

10

9

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

8

7

6

5

4

3

2

1

0

2

1

0

002000h

001000h

000000h

002FFFh

001FFFh

000FFFh

256

100000h

100FFFh

P/N: PM1850

REV. 1.2, NOV. 11, 2013

11

MX25L1675E

8. DEVICE OPERATION

1. Before a command is issued, status register should be checked to ensure device is ready for the intended opera-

tion.

2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode

until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z.

3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until

next CS# rising edge.

4. For standard single data rate serial mode, input data is latched on the rising edge of Serial Clock(SCLK) and

data shifts out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as "Figure 1.

Serial Modes Supported (for Normal Serial mode)" .

5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, RDSFDP, 2READ, DREAD,

4READ, QREAD, RES, REMS, REMS2, and REMS4 the shifted-in instruction sequence is followed by a data-

out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN,

WRDI, WRSR, SE, BE, CE, PP, 4PP, RDP, DP, ENSO, EXSO,and WRSCUR, the CS# must go high exactly at

the byte boundary; otherwise, the instruction will be rejected and not executed.

6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglect-

ed and not affect the current operation of Write Status Register, Program, Erase.

Figure 1. Serial Modes Supported (for Normal Serial mode)

CPOL CPHA

shift in

shift out

SCLK

(Serial mode 0)

(Serial mode 3)

0

1

0

1

SI

MSB

SO

MSB

Note:

CPOL indicates clock polarity of Serial master,

-CPOL=1 for SCLK high while idle,

-CPOL=0 for SCLK low while not transmitting.

CPHA indicates clock phase.

The combination of CPOL bit and CPHA bit decides which Serial mode is supported.

P/N: PM1850

REV. 1.2, NOV. 11, 2013

12

MX25L1675E

9. COMMAND DESCRIPTION

Table 5. Command Sets

Read Commands

2READ (2 x I/O

DREAD

4READ (4 x I/O

QREAD

Command

(byte)

READ (read

data)

FAST READ

(fast read data) (Read SFDP)

RDSFDP

read command) (1I / 2O read read command) (1I / 4O read

(Note1)

BB (hex)

ADD(2)

command)

3B (hex)

AD1(8)

(Note2)

command)

6B (hex)

AD1(8)

1st byte

2nd byte

03 (hex)

AD1

(A23-A16)

0B (hex)

AD1

5A (hex)

AD1

EB (hex)

ADD(4) &

Dummy(4)

AD2

(A15-A8)

AD3

ADD(2) &

Dummy(2)

3rd byte

AD2

AD3

AD2

AD3

AD2(8)

Dummy(4)

AD2(8)

4th byte

5th byte

AD3(8)

(A7-A0)

Dummy(8)

n bytes read

Dummy(8)

Read SFDP

mode

Dummy(8)

n bytes read

out until CS# out until CS#

goes high goes high

n bytes

read out

by 2 x I/O until

CS# goes high

n bytes read

out by 4 x I/O

until CS# goes

high

Action

Note 1: The count base is 4-bit for ADD(2) and Dummy(2) because of 2 x I/O.

Note 2: The count base is 4-bit for ADD(4) and Dummy(4) because of 4 x I/O.

P/N: PM1850

REV. 1.2, NOV. 11, 2013

13

MX25L1675E

Other Commands

RDID

(read identiﬁc-

ation)

Command WREN (write

WRDI

(write disable)

RDSR (read

status register) status register) page program)

WRSR (write

4PP (quad

SE (sector

erase)

(byte)

enable)

1st byte

2nd byte

3rd byte

4th byte

06 (hex)

04 (hex)

9F (hex)

05 (hex)

01 (hex)

38 (hex)

AD1

20 (hex)

AD1

Values

AD2

AD3

sets the (WEL)

write enable

latch bit

resets the

(WEL) write

outputs JEDEC to read out the to write new

ID: 1-byte values of the values of the

quad input to

program the selected sector

to erase the

Action

enable latch bit Manufact-urer status register status register selected page

ID & 2-byte

Device ID

RDP (Release

from deep

power down)

Release Read

Enhanced

Command

(byte)

BE (block

erase)

PP (page

program)

DP (Deep

power down)

RES (read

electronic ID)

CE (chip erase)

60 or C7 (hex)

1st byte

2nd byte

3rd byte

4th byte

D8 (hex)

AD1

02 (hex)

AD1

B9 (hex)

AB (hex)

FFh (hex)

x

AD2

AD3

to erase the to erase whole to program the enters deep

release from

deep power

down mode

to read out

1-byte Device

ID

All these

commands

FFh, 00h, AAh

or 55h will

selected block

chip

selected page power down

mode

Action

escape the

performance

enhance mode

REMS (read

electronic

manufacturer &

device ID)

REMS2 (read REMS4 (read

RDSCUR

(read security (write security

WRSCUR

Command

(byte)

ENSO (enter

secured OTP) secured OTP)

EXSO (exit

ID for 2x I/O

mode)

ID for 4x I/O

mode)

register)

2F (hex)

1st byte

2nd byte

3rd byte

4th byte

90 (hex)

EF (hex)

DF (hex)

B1 (hex) C1 (hex)

2B (hex)

x

X

x

ADD (Note3)

output the

ADD (Note3)

output the

ADD (Note3)

output the

to enter the to exit the 512- to read value of to set the lock-

Manufacturer Manufacturer Manufacturer 512-bit secured bit secured security register down bit as

ID & Device ID ID & Device ID ID & Device ID

OTP mode

"1" (once lock-

down, cannot

be update)

Action

Note 3: ADD=00H will output the manufacturer ID ﬁrst and ADD=01H will output device ID ﬁrst.

Note 4: It is not recommended to adopt any other code not in the command deﬁnition table, which will potentially enter the hid-

den mode.

P/N: PM1850

REV. 1.2, NOV. 11, 2013

14

MX25L1675E

9-1.

Write Enable (WREN)

The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP,

4PP, SE, BE, CE, and WRSR, which are intended to change the device content, should be set every time after the

WREN instruction setting the WEL bit.

The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→ CS# goes high.

The SIO[3:1] are don't care in this mode.

Figure 2. Write Enable (WREN) Sequence (Command 06)

CS#

0

1

2

3

4

5

6

7

SCLK

Command

06h

SI

High-Z

SO

P/N: PM1850

REV. 1.2, NOV. 11, 2013

15

MX25L1675E

9-2.

Write Disable (WRDI)

The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.

The sequence of issuing WRDI instruction is: CS# goes low→ sending WRDI instruction code→ CS# goes high.

The WEL bit is reset by following situations:

- Power-up

- Write Disable (WRDI) instruction completion

- Write Status Register (WRSR) instruction completion

- Page Program (PP, 4PP) instruction completion

- Sector Erase (SE) instruction completion

- Block Erase (BE) instruction completion

- Chip Erase (CE) instruction completion

Figure 3. Write Disable (WRDI) Sequence (Command 04)

CS#

0

1

2

3

4

5

6

7

SCLK

Command

04h

SI

High-Z

SO

P/N: PM1850

REV. 1.2, NOV. 11, 2013

16

MX25L1675E

9-3.

Read Identiﬁcation (RDID)

The RDID instruction is for reading the Manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC

Manufacturer ID is C2(hex), the memory type ID is as the ﬁrst-byte Device ID, and the individual Device ID of sec-

ond-byte ID are listed as table of "Table 7. ID Deﬁnitions".

The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code → 24-bits ID data out

on SO→ to end RDID operation can use CS# to high at any time during data out.

While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cy-

cle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.

Figure 4. Read Identiﬁcation (RDID) Sequence (Command 9F)

CS#

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18

28 29 30 31

SCLK

SI

Command

9Fh

Manufacturer Identification

Device Identification

High-Z

SO

7

6

5

3

2

1

0

15 14 13

MSB

3

2

1

0

MSB

P/N: PM1850

REV. 1.2, NOV. 11, 2013

17

MX25L1675E

9-4.

Read Status Register (RDSR)

The RDSR instruction is for reading Status Register. The Read Status Register can be read at any time (even in

program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP)

bit before sending a new instruction when a program, erase, or write status register operation is in progress.

The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register

data out on SO.

The SIO[3:1] are don't care when during this mode.

Figure 5. Read Status Register (RDSR) Sequence (Command 05)

CS#

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

SCLK

SI

command

05h

Status Register Out

High-Z

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

MSB

P/N: PM1850

REV. 1.2, NOV. 11, 2013

18

MX25L1675E

The deﬁnition of the status register bits is as below:

WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write

status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status

register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status

register cycle.

WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable

latch. When WEL bit sets to "1", which means the internal write enable latch is set, the device can accept program/

erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the de-

vice will not accept program/erase/write status register instruction. The program/erase command will be ignored and

will reset WEL bit if it is applied to a protected memory area. To ensure both WIP bit & WEL bit are both set to 0 and

available for next program/erase/operations, WIP bit needs to be conﬁrm to be 0 before polling WEL bit. After WIP bit

conﬁrmed, WEL bit needs to be conﬁrm to be 0.

BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area (as

deﬁned in "Table 2. Protected Area Sizes") of the device to against the program/erase instruction without hardware

protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register

(WRSR) instruction to be executed. Those bits deﬁne the protected area of the memory to against Page Program (PP),

Sector Erase (SE), Block Erase (BE) and Chip Erase (CE) instructions (only if all Block Protect bits set to 0, the CE

instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default. Which is un-protected.

QE bit. The Quad Enable (QE) bit, non-volatile bit, while it is "0", it performs non-Quad and WP# is enable. While

QE is "1", it performs Quad I/O mode and WP# is disabled. QE bit is set to "1" before factory shipping, in the other

word, the system goes into four I/O mode (QE=1) before factory shipping, and the feature of HPM is disabled.

SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, default value is "0". SRWD bit is operat-

ed together with Write Protection (WP#/SIO2) pin for providing hardware protection mode. The hardware protection

mode requires SRWD sets to 1 and WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write

Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP3,

BP2, BP1, BP0) are read only. The SRWD bit defaults to be "0".

Status Register

bit7

bit6

bit5

BP3

(level of

protected

block)

bit4

BP2

(level of

protected

block)

bit3

BP1

(level of

protected

block)

bit2

BP0

(level of

protected

block)

bit1

bit0

SRWD (status

register write

protect)

QE

(Quad

Enable)

WEL

(write enable

latch)

WIP

(write in

progress bit)

1=Quad

Enable

0=not Quad

Enable

1=write

enable

0=not write 0=not in write

enable

1=write

operation

1=status

register write

disable

(Note)

operation

Non-volatile Non-volatile Non-volatile Non-volatile Non-volatile Non-volatile

bit bit bit bit bit bit

volatile bit

Note: See the "Table 2. Protected Area Sizes".

P/N: PM1850

REV. 1.2, NOV. 11, 2013

19

MX25L1675E

9-5.

Write Status Register (WRSR)

The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the

Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in ad-

vance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to deﬁne the pro-

tected area of memory (as shown in "Table 2. Protected Area Sizes"). The WRSR also can set or reset the Quad

enable (QE) bit and set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#/

SIO2) pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of the status register. The WRSR instruction cannot

be executed once the Hardware Protected Mode (HPM) is entered.

The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register

data on SI→ CS# goes high.

Figure 6. Write Status Register (WRSR) Sequence (Command 01)

CS#

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Mode 3

Mode 0

SCLK

command

01h

Status

Register In

Configuration

Register In

SI

4

15 14

13

12 11

10 9

8

2

1

0

7

6

5

3

MSB

High-Z

SO

P/N: PM1850

REV. 1.2, NOV. 11, 2013

20

MX25L1675E

The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.

The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write

in Progress (WIP) bit still can be checked out during the Write Status Register cycle is in progress. The WIP sets 1

during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL)

bit is reset.

Table 6. Protection Modes

Mode

Status register condition

WP# and SRWD bit status

Memory

Status register can be written

in (WEL bit is set to "1") and

the SRWD, BP0-BP3

Software protection

mode (SPM)

WP#=1 and SRWD bit=0, or

WP#=0 and SRWD bit=0, or

WP#=1 and SRWD=1

The protected area cannot

be programmed or erased.

bits can be changed

The SRWD, BP0-BP3 of

status register bits cannot be

changed

Hardware protection

mode (HPM)

The protected area cannot

be programmed or erased.

WP#=0, SRWD bit=1

Note: As deﬁned by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in

"Table 2. Protected Area Sizes".

As the table above showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM):

Software Protected Mode (SPM):

-

When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can

change the values of SRWD, BP3, BP2, BP1, BP0 and QE. The protected area, which is deﬁned by BP3, BP2,

BP1, BP0, is at software protected mode (SPM).

-

When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values of

SRWD, BP3, BP2, BP1, BP0 and QE. The protected area, which is deﬁned by BP3, BP2, BP1, BP0, is at soft-

ware protected mode (SPM)

Hardware Protected Mode (HPM):

-

When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware

protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2,

BP1, BP0 and hardware protected mode by the WP#/SIO2 to against data modiﬁcation.

Note:

To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is en-

tered. If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be entered;

only can use software protected mode via BP3, BP2, BP1, BP0.

If the system goes into four I/O mode, the feature of HPM will be disabled.

P/N: PM1850

REV. 1.2, NOV. 11, 2013

21

MX25L1675E

Figure 7. WRSR ﬂow

start

WREN command

RDSR command

No

WREN=1?

Yes

WRSR command

Write status register data

RDSR command

No

WIP=0?

Yes

RDSR command

Read WEL=0, BP[3:0], QE,

and SRWD data

No

Verify OK?

Yes

WRSR successfully

WRSR fail

P/N: PM1850

REV. 1.2, NOV. 11, 2013

22

MX25L1675E

9-6.

Read Data Bytes (READ)

The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on

the falling edge of SCLK at a maximum frequency fR. The ﬁrst address byte can be at any location. The address

is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can

be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been

reached.

The sequence of issuing READ instruction is: CS# goes low→ sending READ instruction code→3-byte address on

SI →data out on SO→ to end READ operation can use CS# to high at any time during data out.

Figure 8. Read Data Bytes (READ) Sequence (Command 03)

CS#

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38 39

SCLK

Command

03

24 ADD Cycles

A23 A22 A21

MSB

A3 A2 A1 A0

SI

Data Out 2

Data Out 1

High-Z

D7 D6 D5 D4 D3 D2 D1 D0 D7

MSB MSB

SO

P/N: PM1850

REV. 1.2, NOV. 11, 2013

23

MX25L1675E

9-7.

Read Data Bytes at Higher Speed (FAST_READ)

The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and

data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The ﬁrst address byte can be at

any location. The address is automatically increased to the next higher address after each byte data is shifted out,

so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when

the highest address has been reached.

The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code→

3-byte address on SI→1-dummy byte (default) address on SI→ data out on SO→ to end FAST_READ operation

can use CS# to high at any time during data out.

In the performance-enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0]=A5h,5Ah,F0h or 0Fh can

make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0]; like-

wise P[7:0]=FFh,00h,AAh or 55h and afterwards CS# is raised and then lowered, the system then will escape from

performance enhance mode and return to normal operation.

While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any im-

pact on the Program/Erase/Write Status Register current cycle.

Figure 9. Read at Higher Speed (FAST_READ) Sequence (Command 0B) (104MHz)

CS#

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31

SCLK

Command

0Bh

24 BIT ADDRESS

SI

23 22 21

3

2

1

0

High-Z

SO

CS#

47

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

SCLK

Dummy Cycle

7

6

5

4

3

2

0

1

SI

DATA OUT 2

DATA OUT 1

7

6

5

4

3

2

1

0

7

6

5

4

3

2

0

1

SO

MSB

P/N: PM1850

REV. 1.2, NOV. 11, 2013

24

MX25L1675E

9-8.

Dual Read Mode (DREAD)

The DREAD instruction enable double throughput of Serial Flash in read mode. The address is latched on rising

edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maxi-

mum frequency fT. The ﬁrst address byte can be at any location. The address is automatically increased to the next

higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD instruc-

tion. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruc-

tion, the following data out will perform as 2-bit instead of previous 1-bit.

The sequence of issuing DREAD instruction is: CS# goes low

sending DREAD instruction

3-byte address on

→

SI

8-bit dummy cycle

data out interleave on SO1 & SO0

to end DREAD operation can use CS# to high at

→

any time during data out.

While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact

on the Program/Erase/Write Status Register current cycle.

Figure 10. Dual Read Mode Sequence (Command 3B)

CS#

30 31 32

39 40 41 42 43 44 45

0

1

2

3

4

5

6

7

8

9

SCLK

…

Data Out

1

8 dummy

cycle

Command

24 ADD Cycle

2

…

A23 A22

A1 A0

D4 D2

D6 D4

D7 D5

3B

D6

D7

D0

SI/SIO0

High Impedance

D1

D5 D3

SO/SIO1

P/N: PM1850

REV. 1.2, NOV. 11, 2013

25

MX25L1675E

9-9.

2 x I/O Read Mode (2READ)

The 2READ instruction enables Double Transfer Rate of Serial Flash in read mode. The address is latched on rising

edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maxi-

mum frequency fT. The ﬁrst address byte can be at any location. The address is automatically increased to the next

higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ instruc-

tion. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ instruc-

tion, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit.

The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 24-bit address in-

terleave on SIO1 & SIO0→ 4-bit dummy cycles on SIO1 & SIO0→ data out interleave on SIO1 & SIO0→ to end

2READ operation can use CS# to high at any time during data out.

While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact

on the Program/Erase/Write Status Register current cycle.

Figure 11. 2 x I/O Read Mode Sequence (Command BB)

CS#

28 29

18 19 20 21 22 23 24 25 26 27

0

1

2

3

4

5

6

7

8

9

SCLK

…

Data Out

4 dummy

cycle

Command

12 ADD Cycle

2

1

…

A22 A20

A23 A21

A2 A0

P0

D4 D2

D6 D4

D7 D5

P2

BB(hex)

D6

D7

D0

D1

SI/SIO0

High Impedance

…

A3 A1 P3

P1

D5 D3

SO/SIO1

Note: SI/SIO0 or SO/SIO1 should be kept "0h" or "Fh" in the ﬁrst two dummy cycles. In other words, P2=P0 or

P3=P1 is necessary.

P/N: PM1850

REV. 1.2, NOV. 11, 2013

26

MX25L1675E

9-10. Quad Read Mode (QREAD)

The QREAD instruction enable quad throughput of Serial Flash in read mode. The address is latched on rising edge

of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum

frequency fQ. The ﬁrst address byte can be at any location. The address is automatically increased to the next high-

er address after each byte data is shifted out, so the whole memory can be read out at a single QREAD instruction.

The address counter rolls over to 0 when the highest address has been reached. Once writing QREAD instruction,

the following data out will perform as 4-bit instead of previous 1-bit.

The sequence of issuing QREAD instruction is: CS# goes low

sending QREAD instruction → 3-byte address on

→

SI

8-bit dummy cycle

data out interleave on SO3, SO2, SO1 & SO0

to end QREAD operation can use

→

CS# to high at any time during data out.

While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any impact

on the Program/Erase/Write Status Register current cycle.

Figure 12. Quad Read Mode Sequence (Command 6B)

CS#

29 30 31 32 33

38 39 40 41 42

0

1

2

3

4

5

6

7

8

9

SCLK

…

Data

Out 2

Data

Out 3

Command

6B

8 dummy cycles

24 ADD Cycles

Data

Out 1

…

A23A22

A2 A1 A0

D4 D0 D4 D0 D4

SI/SO0

High Impedance

SO/SO1

D5 D1 D5 D1 D5

D6 D2 D6 D2 D6

WP#/SO2

HOLD#/SO3

D7 D3 D7 D3 D7

P/N: PM1850

REV. 1.2, NOV. 11, 2013

27

MX25L1675E

9-11. 4 x I/O Read Mode (4READ)

The 4READ instruction enables quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status

Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCLK,

and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency

fQ. The ﬁrst address byte can be at any location. The address is automatically increased to the next higher address

after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address

counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following

address/dummy/data out will perform as 4-bit instead of previous 1-bit.

The sequence of issuing 4READ instruction is: CS# goes low sending 4READ instruction 24-bit address inter-

→

leave on SIO3, SIO2, SIO1 & SIO0 2+4 dummy cycles data out interleave on SIO3, SIO2, SIO1 & SIO0 to

→

end 4READ operation can use CS# to high at any time during data out.

Figure 13. 4 x I/O Read Mode Sequence (Command EB)

CS#

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23

n

SCLK

4 dummy

cycles

8 Bit Instruction

EB(hex)

6 Address cycles

Data Output

Performance

enhance

indicator (Note)

data

bit4, bit0, bit4....

address

bit20, bit16..bit0

P4 P0

P5 P1

P6 P2

P7 P3

SI/SIO0

High Impedance

address

bit21, bit17..bit1

data

bit5 bit1, bit5....

SO/SIO1

WP#/SIO2

NC/SIO3

address

bit22, bit18..bit2

data

bit6 bit2, bit6....

address

bit23, bit19..bit3

data

bit7 bit3, bit7....

Note:

1. Hi-impedance is inhibited for the two clock cycles.

2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited.

P/N: PM1850

REV. 1.2, NOV. 11, 2013

28

MX25L1675E

Another sequence of issuing 4READ instruction especially useful in random access is : CS# goes low→ sending

4READ instruction→ 3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 →performance enhance toggling bit

P[7:0]→ 4 dummy cycles→ data out until CS# goes high → CS# goes low (reduce 4 Read instruction) → 24-bit ran-

dom access address (Please refer to "Figure 14. 4 x I/O Read enhance performance Mode Sequence (Command

EB)" ).

In the performance-enhancing mode (Notes of "Figure 14. 4 x I/O Read enhance performance Mode Sequence

(Command EB)"), P[7:4] must be toggling with P[3:0]; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh can make this mode

continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0]; likewise P[7:0]=FFh,

00h, AAh or 55h. These commands will reset the performance enhance mode. And afterwards CS# is raised and

then lowered, the system then will return to normal operation.

While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact

on the Program/Erase/Write Status Register current cycle.

9-12. Performance Enhance Mode

The device could waive the command cycle bits if the two cycle bits after address cycle toggles. (Please note "Fig-

ure 14. 4 x I/O Read enhance performance Mode Sequence (Command EB)")

Please be noticed that “EBh” and “E7h” commands support enhance mode. The performance enhance mode is not

supported in dual I/O mode.

After entering enhance mode, following CSB go high, the device will stay in the read mode and treat CSB go low of

the ﬁrst clock as address instead of command cycle.

To exit enhance mode, a new fast read command whose ﬁrst two dummy cycles is not toggle then exit. Or issue

”FFh” command to exit enhance mode.

9-13. Performance Enhance Mode Reset (FFh)

To conduct the Performance Enhance Mode Reset operation, FFh command code, 8 clocks, should be issued in 1I/

O sequence.

If the system controller is being Reset during operation, the ﬂash device will return to the standard operation.

Upon Reset of main chip, Instruction would be issued from the system. Instructions like Read ID (9Fh) or Fast Read

(0Bh) would be issued.

The SIO[3:1] are don't care when during this mode.

P/N: PM1850

REV. 1.2, NOV. 11, 2013

29

MX25L1675E

Figure 14. 4 x I/O Read enhance performance Mode Sequence (Command EB)

CS#

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23

n

SCLK

4 dummy

cycles

8 Bit Instruction

EB(hex)

6 Address cycles

Data Output

Performance

enhance

indicator (Note)

data

bit4, bit0, bit4....

address

bit20, bit16..bit0

P4 P0

P5 P1

P6 P2

P7 P3

SI/SIO0

High Impedance

address

bit21, bit17..bit1

data

bit5 bit1, bit5....

SO/SIO1

WP#/SIO2

NC/SIO3

address

bit22, bit18..bit2

data

bit6 bit2, bit6....

address

bit23, bit19..bit3

data

bit7 bit3, bit7....

CS#

n+1

...........

n+7......n+9 ........... n+13

...........

SCLK

4 dummy

cycles

6 Address cycles

address

Data Output

Performance

enhance

indicator (Note)

data

bit4, bit0, bit4....

P4 P0

P5 P1

P6 P2

P7 P3

SI/SIO0

bit20, bit16..bit0

address

bit21, bit17..bit1

data

bit5 bit1, bit5....

SO/SIO1

WP#/SIO2

NC/SIO3

address

bit22, bit18..bit2

data

bit6 bit2, bit6....

address

bit23, bit19..bit3

data

bit7 bit3, bit7....

Note:

1. Performance enhance mode, if P7≠P3 & P6≠P2 & P5≠P1 & P4≠P0 (Toggling), ex: A5, 5A, 0F, if not using

performance enhance recommend to keep 1 or 0 in performance enhance indicator.

Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF

P/N: PM1850

REV. 1.2, NOV. 11, 2013

30

MX25L1675E

Figure 15. Performance Enhance Mode Reset for Fast Read Quad I/O

Mode Bit Reset

for Quad I/O

CS#

Mode 3

０

1

2

3

4

5

6

7

SCLK

Mode ０

IO0

IO1

IO2

FFh

Don’t Care

IO3

P/N: PM1850

REV. 1.2, NOV. 11, 2013

31

MX25L1675E

9-14. Sector Erase (SE)

The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for

any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before

sending the Sector Erase (SE). Any address of the sector (see "Table 4. Memory Organization" ) is a valid address

for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address

byte has been latched-in); otherwise, the instruction will be rejected and not executed.

The sequence of issuing SE instruction is: CS# goes low → sending SE instruction code→ 3-byte address on SI

→CS# goes high.

The SIO[3:1] are don't care when during this mode.

The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Pro-

gress (WIP) bit still can be checked out during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE

timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page

is protected by BP3, BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the page.

Figure 16. Sector Erase (SE) Sequence (Command 20)

CS#

0

1

2

3

4

5

6

7

8

9

29 30 31

SCLK

Command

20h

24 Bit Address

SI

23 22

MSB

2

1

0

P/N: PM1850

REV. 1.2, NOV. 11, 2013

32

MX25L1675E

9-15. Block Erase (BE)

The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for

64K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL)

bit before sending the Block Erase (BE). Any address of the block (see "Table 4. Memory Organization" ) is a valid

address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of

address byte has been latched-in); otherwise, the instruction will be rejected and not executed.

The sequence of issuing BE instruction is: CS# goes low → sending BE instruction code → 3-byte address on SI →

CS# goes high.

The SIO[3:1] are don't care when during this mode.

The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Pro-

gress (WIP) bit still can be checked out during the Sector Erase cycle is in progress. The WIP sets 1 during the tBE

timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page

is protected by BP3, BP2, BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the page.

Figure 17. Block Erase (BE) Sequence (Command D8)

CS#

0

1

2

3

4

5

6

7

8

9

29 30 31

SCLK

Command

D8h

24 Bit Address

SI

23 22

MSB

2

0

1

P/N: PM1850

REV. 1.2, NOV. 11, 2013

33

MX25L1675E

9-16. Chip Erase (CE)

The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruc-

tion must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must go

high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.

The sequence of issuing CE instruction is: CS# goes low → sending CE instruction code → CS# goes high.

The SIO[3:1] are don't care when during this mode.

The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Pro-

gress (WIP) bit still can be checked out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE

timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is

protected, the Chip Erase (CE) instruction will not be executed, but WEL will be reset.

Figure 18. Chip Erase (CE) Sequence (Command 60 or C7)

CS#

0

1

2

3

4

5

6

7

SCLK

SI

Command

60h or C7h

P/N: PM1850

REV. 1.2, NOV. 11, 2013

34

MX25L1675E

9-17. Page Program (PP)

The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction

must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device programs

only the last 256 data bytes sent to the device. If the entire 256 data bytes are going to be programmed, A7-A0

(The eight least signiﬁcant address bits) should be set to 0. If A7-A0 are not all zero, transmitted data that exceed

page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently selected

page. If the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the request page

and previous data will be disregarded. If the data bytes sent to the device has not exceeded 256, the data will be

programmed at the request address of the page. There will be no effort on the other data bytes of the same page.

The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→ at

least 1-byte on data on SI→ CS# goes high.

The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte

boundary (the latest eighth bit of data being latched in), otherwise, the instruction will be rejected and will not be

executed.

The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in

Progress (WIP) bit still can be checked out during the Page Program cycle is in progress. The WIP sets 1 during

the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If

the page is protected by BP3~0, the array data will be protected (no change) and the WEL bit will still be reset.

The SIO[3:1] are don't care when during this mode.

Figure 19. Page Program (PP) Sequence (Command 02)

CS#

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38 39

SCLK

Command

02h

24-Bit Address

Data Byte 1

23 22 21

MSB

3

2

1

0

7

6

5

4

3

2

0

1

SI

MSB

CS#

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

SCLK

Data Byte 2

Data Byte 3

Data Byte 256

7

6

5

4

3

2

0

7

6

5

4

3

2

0

7

6

5

4

3

2

0

1

SI

MSB

P/N: PM1850

REV. 1.2, NOV. 11, 2013

35

MX25L1675E

9-18. 4 x I/O Page Program (4PP)

The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN)

instruction must execute to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1"

before sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1, SIO2,

and SIO3, which can raise programmer performance and the effectiveness of application of lower clock less than

85MHz. For system with faster clock, the Quad page program cannot provide more actual favors, because the

required internal page program time is far more than the time data ﬂows in. Therefore, we suggest that while

executing this command (especially during sending data), user can slow the clock speed down to 85MHz below.

The other function descriptions are as same as standard page program.

The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on

SIO[3:0]→ at least 1-byte on data on SIO[3:0]→ CS# goes high.

If the page is protected by BP3~0, the array data will be protected (no change) and the WEL bit will still be reset.

Figure 20. 4 x I/O Page Program (4PP) Sequence (Command 38)

CS#

524 525

10 11 12 13 14 15 16 17

0

1

2

3

4

5

6

7

8

9

SCLK

…

Data

Byte 256

Data Data

Byte 1 Byte 2

Command

38

6 ADD cycles

D4 D0 D4 D0

D4 D0

A20 A16 A12 A8 A4 A0

SI/SIO0

…

D5 D1 D5 D1

D6 D2 D6 D2

D7 D3 D7 D3

D5 D1

D6 D2

D7 D3

SO/SIO1

A21 A17 A13 A9 A5 A1

A22 A18 A14 A10 A6 A2

WP#/SIO2

HOLD#/SIO3

A23 A19 A15 A11 A7 A3

P/N: PM1850

REV. 1.2, NOV. 11, 2013

36

MX25L1675E

9-19. Deep Power-down (DP)

The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to enter-

ing the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode

requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not ac-

tive and all Write/Program/Erase instructions are ignored. When CS# goes high, it's only in standby mode not deep

power-down mode. It's different from Standby mode.

The sequence of issuing DP instruction is: CS# goes low→ sending DP instruction code→ CS# goes high.

The SIO[3:1] are don't care when during this mode.

Once the DP instruction is set, all instructions will be ignored except the Release from Deep Power-down mode (RDP)

and Read Electronic Signature (RES) instruction. (those instructions allow the ID being reading out). When Power-

down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby

mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction

code has been latched-in); otherwise, the instruction will not be executed. As soon as Chip Select (CS#) goes high,

a delay of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2.

Figure 21. Deep Power-down (DP) Sequence (Command B9)

CS#

t_DP

0

1

2

3

4

5

6

7

SCLK

SI

Command

B9h

Stand-by Mode

Deep Power-down Mode

P/N: PM1850

REV. 1.2, NOV. 11, 2013

37

MX25L1675E

9-20. Release from Deep Power-down (RDP), Read Electronic Signature (RES)

The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip

Select (CS#) is driven High, the device is put in the standby Power mode. If the device was not previously in the

Deep Power-down mode, the transition to the standby Power mode is immediate. If the device was previously in the

Deep Power-down mode, though, the transition to the standby Power mode is delayed by tRES2, and Chip Select

(CS#) must remain High for at least tRES2(max), as speciﬁed in "Table 13. AC Characteristics". Once in the stand-

by mode, the device waits to be selected, so that it can receive, decode and execute instructions.

RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as "Table 7.

ID Deﬁnitions". This is not the same as RDID instruction. It is not recommended to use for new design. For new

design, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be

executed, only except the device is in progress of program/erase/write cycles; there's no effect on the current pro-

gram/erase/write cycles in progress.

The SIO[3:1] are don't care when during this mode.

The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeat-

edly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously

in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in

Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least

tRES2(max). Once in the standby mode, the device waits to be selected, so it can receive, decode, and execute

instruction.

The RDP instruction is for releasing from Deep Power-down Mode.

Figure 22. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB)

CS#

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38

SCLK

Command

ABh

t

3 Dummy Bytes

RES2

SI

23 22 21

MSB

3

2

1

0

Electronic Signature Out

High-Z

7

6

5

4

3

2

0

1

SO

MSB

Deep Power-down Mode

Stand-by Mode

P/N: PM1850

REV. 1.2, NOV. 11, 2013

38

MX25L1675E

Figure 23. Release from Deep Power-down (RDP) Sequence (Command AB)

CS#

t_RES1

0

1

2

3

4

5

6

7

SCLK

Command

ABh

SI

High-Z

SO

Deep Power-down Mode

Stand-by Mode

P/N: PM1850

REV. 1.2, NOV. 11, 2013

39

MX25L1675E

9-21. Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4)

The REMS, REMS2, and REMS4 instruction provides both the JEDEC assigned Manufacturer ID and the speciﬁc

Device ID.

The instruction is initiated by driving the CS# pin low and shift the instruction code "90h", "DFh" or "EFh" followed

by two dummy bytes and one byte address (A7~A0). After which, the Manufacturer ID for MXIC (C2h) and the De-

vice ID are shifted out on the falling edge of SCLK with most signiﬁcant bit (MSB) ﬁrst as shown in the ﬁgure below.

The Device ID values are listed in "Table 7. ID Deﬁnitions". If the one-byte address is initially set to 01h, then the

Device ID will be read ﬁrst and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be

read continuously, alternating from one to the other. The instruction is completed by driving CS# high.

Figure 24. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF)

CS#

0

1

2

3

4

5

6

7

8

9

10

47

30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

28

29

SCLK

Command

90

24 ADD Cycles

SI

A0

A1

A3 A2

A23 A22 A21

Manufacturer ID

Device ID

High-Z

SO

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

MSB

Notes:

1. A0=0 will output the Manufacturer ID ﬁrst and A0=1 will output Device ID ﬁrst. A1~A23 are don't care.

2. Instruction is either 90(hex) or EF(hex) or DF(hex).

P/N: PM1850

REV. 1.2, NOV. 11, 2013

40

MX25L1675E

9-22. ID Read

User can execute this ID Read instruction to identify the Device ID and Manufacturer ID. The sequence of issue ID

instruction is CS# goes low→sending ID instruction→→Data out on SO→CS# goes high. Most signiﬁcant bit (MSB)

ﬁrst.

After the command cycle, the device will immediately output data on the falling edge of SCLK. The manufacturer ID,

memory type, and device ID data byte will be output continuously, until the CS# goes high.

Table 7. ID Deﬁnitions

manufacturer ID

C2

memory type

memory density

15

RDID Command

RES Command

24

electronic ID

24

manufacturer ID

C2

device ID

24

REMS/REMS2/REMS4/

Command

9-23. Enter Secured OTP (ENSO)

The ENSO instruction is for entering the additional 512-bit secured OTP mode. The additional 512-bit secured OTP

is independent from main array, which may use to store unique serial number for system identiﬁer. After entering

the Secured OTP mode, and then follow standard read or program, procedure to read out the data or update data.

The Secured OTP data cannot be updated again once it is lock-down.

The sequence of issuing ENSO instruction is: CS# goes low→sending ENSO instruction to enter Secured OTP

mode→ CS# goes high.

Please note that WRSR/WRSCUR commands are not acceptable during the access of secure OTP region, once

se- curity OTP is lock down, only read related commands are valid.

9-24. Exit Secured OTP (EXSO)

The EXSO instruction is for exiting the additional 512-bit secured OTP mode.

The sequence of issuing EXSO instruction is: CS# goes low→sending EXSO instruction to exit Secured OTP

mode→CS# goes high.

P/N: PM1850

REV. 1.2, NOV. 11, 2013

41

MX25L1675E

9-25. Read Security Register (RDSCUR)

The RDSCUR instruction is for reading the value of Security Register. The Read Security Register can be read at

any time (even in program/erase/write status register/write security register condition) and continuously.

The sequence of issuing RDSCUR instruction is : CS# goes low→ sending RDSCUR instruction → Security Regis-

ter data out on SO→ CS# goes high.

The SIO[3:1] are don't care when during this mode.

Figure 25. Read Security Register (RDSCUR) Sequence (Command 2B)

CS#

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

SCLK

SI

command

2B

Security Register Out

High-Z

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

MSB

The deﬁnition of the Security Register is as below:

Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory before ex- factory or

not. When it is "0", it indicates non- factory lock; "1" indicates factory- lock.

Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for custom-

er lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 512-bit Secured OTP

area cannot be update any more. While it is in 512-bit secured OTP mode, main array access is not allowed.

Table 8. Security Register Deﬁnition

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

LDSO

(indicate if

lock-down

Secured OTP

indicator bit

x

0 = not lock-down

1 = lock-down

(cannot

program/erase

OTP)

0 = non-factory

lock

reserved

1 = factory

lock

volatile bit volatile bit volatile bit volatile bit volatile bit volatile bit

non-volatile bit

P/N: PM1850

REV. 1.2, NOV. 11, 2013

42

MX25L1675E

9-26. Write Security Register (WRSCUR)

The WRSCUR instruction is for changing the values of Security Register Bits. The WREN instruction is required be-

fore sending WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO bit) for customer

to lock-down the Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area cannot be updated any

more.

The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high.

The SIO[3:1] are don't care when during this mode.

The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.

Figure 26. Write Security Register (WRSCUR) Sequence (Command 2F)

CS#

0

1

2

3

4

5

6

7

SCLK

Command

2F

SI

High-Z

SO

P/N: PM1850

REV. 1.2, NOV. 11, 2013

43

MX25L1675E

9-27. Read SFDP Mode (RDSFDP)

The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional

and feature capabilities of serial ﬂash devices in a standard set of internal parameter tables. These parameter tables

can be interrogated by host system software to enable adjustments needed to accommodate divergent features

from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on

CFI.

The sequence of issuing RDSFDP instruction is same as CS# goes low→send RDSFDP instruction (5Ah)→send 3

address bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP operation can

use CS# to high at any time during data out.

SFDP is a JEDEC Standard. JESD216.

Figure 27. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence

CS#

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31

SCLK

Command

5Ah

24 BIT ADDRESS

SI

23 22 21

3

2

1

0

High-Z

SO

CS#

47

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

SCLK

Dummy Cycle

7

6

5

4

3

2

0

1

SI

DATA OUT 2

DATA OUT 1

7

6

5

4

3

2

1

0

7

6

5

4

3

2

0

1

SO

MSB

P/N: PM1850

REV. 1.2, NOV. 11, 2013

44

MX25L1675E

Table 9. Signature and Parameter Identiﬁcation Data Values

Add (h) DW Add Data (h/b)

Data

(h)

Description

Comment

(Byte)

(Bit)

(Note1)

00h

07:00

53h

46h

44h

50h

00h

01h

02h

03h

04h

05h

06h

15:08

23:16

31:24

07:00

15:08

23:16

46h

44h

50h

00h

01h

SFDP Signature

Fixed: 50444653h

SFDP Minor Revision Number

SFDP Major Revision Number

Number of Parameter Headers

Start from 00h

Start from 01h

Unused

07h

08h

09h

0Ah

0Bh

31:24

07:00

15:08

23:16

31:24

FFh

00h

01h

09h

FFh

00h

01h

09h

00h: it indicates a JEDEC speciﬁed

header.

ID number (JEDEC)

Parameter Table Minor Revision

Number

Parameter Table Major Revision

Number

Parameter Table Length

(in double word)

Start from 00h

Start from 01h

How many DWORDs in the

Parameter table

0Ch

0Dh

0Eh

07:00

15:08

23:16

30h

00h

30h

00h

First address of JEDEC Flash

Parameter table

Parameter Table Pointer (PTP)

Unused

0Fh

10h

11h

12h

13h

31:24

07:00

15:08

23:16

31:24

FFh

C2h

00h

01h

04h

FFh

C2h

00h

01h

04h

ID number

(Macronix manufacturer ID)

Parameter Table Minor Revision

Number

Parameter Table Major Revision

Number

Parameter Table Length

(in double word)

it indicates Macronix manufacturer

ID

Start from 00h

Start from 01h

How many DWORDs in the

Parameter table

14h

15h

16h

07:00

15:08

23:16

60h

00h

60h

00h

First address of Macronix Flash

Parameter table

Parameter Table Pointer (PTP)

Unused

17h

31:24

FFh

P/N: PM1850

REV. 1.2, NOV. 11, 2013

45

MX25L1675E

Table 10. Parameter Table (0): JEDEC Flash Parameter Tables

Add (h) DW Add Data (h/b)

Data

(h)

Description

Comment

(Byte)

(Bit)

(Note1)

00: Reserved, 01: 4KB erase,

10: Reserved,

Block/Sector Erase sizes

01:00

01b

11: not support 4KB erase

Write Granularity

0: 1Byte, 1: 64Byte or larger

02

03

1b

0b

Write Enable Instruction Required 0: not required

for Writing to Volatile Status

1: required 00h to be written to the

Registers

status register bit

30h

E5h

0: use 50h opcode,

1: use 06h opcode

Write Enable Opcode Select for

Writing to Volatile Status Registers

Note: If target ﬂash status register

is nonvolatile, then bits 3 and 4

must be set to 00b.

04

0b

Contains 111b and can never be

changed

Unused

07:05

111b

4KB Erase Opcode

31h

32h

15:08

16

20h

1b

20h

F1h

FFh

(1-1-2) Fast Read (Note2)

0=not support 1=support

Address Bytes Number used in

addressing ﬂash array

00: 3Byte only, 01: 3 or 4Byte,

10: 4Byte only, 11: Reserved

18:17

19

00b

0b

Double Transfer Rate (DTR)

Clocking

0=not support 1=support

(1-2-2) Fast Read

(1-4-4) Fast Read

(1-1-4) Fast Read

Unused

0=not support 1=support

20

21

1b

22

1b

23

1b

Unused

33h

31:24

31:00

FFh

Flash Memory Density

37h:34h

00FFFFFFh

(1-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy

04:00

0 0100b

states (Note3)

Clocks) not support

38h

39h

3Ah

3Bh

44h

EBh

08h

6Bh

(1-4-4) Fast Read Number of

Mode Bits (Note4)

000b: Mode Bits not support

07:05

15:08

20:16

010b

EBh

(1-4-4) Fast Read Opcode

(1-1-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy

states

(1-1-4) Fast Read Number of

Mode Bits

0 1000b

Clocks) not support

000b: Mode Bits not support

23:21

31:24

000b

6Bh

(1-1-4) Fast Read Opcode

P/N: PM1850

REV. 1.2, NOV. 11, 2013

46

MX25L1675E

Add (h) DW Add Data (h/b) Data

Description

Comment

(Byte)

(Bit)

(Note1)

(h)

(1-1-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy

04:00

0 1000b

states

Clocks) not support

3Ch

08h

(1-1-2) Fast Read Number of

Mode Bits

000b: Mode Bits not support

07:05

15:08

20:16

000b

3Bh

(1-1-2) Fast Read Opcode

3Dh

3Eh

3Fh

3Bh

04h

BBh

(1-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy

0 0100b

states

Clocks) not support

(1-2-2) Fast Read Number of

Mode Bits

000b: Mode Bits not support

23:21

000b

(1-2-2) Fast Read Opcode

(2-2-2) Fast Read

Unused

31:24

00

BBh

0b

0=not support 1=support

03:01

04

111b

0b

40h

EEh

(4-4-4) Fast Read

Unused

07:05

31:08

15:00

111b

FFh

Unused

43h:41h

45h:44h

FFh

Unused

(2-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy

20:16

23:21

0 0000b

000b

states

Clocks) not support

46h

00h

(2-2-2) Fast Read Number of

Mode Bits

000b: Mode Bits not support

(2-2-2) Fast Read Opcode

Unused

47h

31:24

15:00

FFh

49h:48h

(4-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy

20:16

0 0000b

states

Clocks) not support

4Ah

00h

(4-4-4) Fast Read Number of

Mode Bits

000b: Mode Bits not support

23:21

31:24

07:00

15:08

23:16

31:24

07:00

15:08

23:16

31:24

000b

FFh

0Ch

20h

10h

D8h

00h

FFh

00h

FFh

(4-4-4) Fast Read Opcode

4Bh

4Ch

4Dh

4Eh

4Fh

50h

51h

52h

53h

FFh

0Ch

20h

10h

D8h

00h

FFh

00h

FFh

Sector/block size = 2^N bytes (Note5)

0x00b: this sector type doesn't exist

Sector Type 1 Size

Sector Type 1 erase Opcode

Sector Type 2 Size

Sector/block size = 2^N bytes

0x00b: this sector type doesn't exist

Sector Type 2 erase Opcode

Sector Type 3 Size

Sector/block size = 2^N bytes

0x00b: this sector type doesn't exist

Sector Type 3 erase Opcode

Sector Type 4 Size

Sector/block size = 2^N bytes

0x00b: this sector type doesn't exist

Sector Type 4 erase Opcode

P/N: PM1850

REV. 1.2, NOV. 11, 2013

47

MX25L1675E

Table 11. Parameter Table (1): Macronix Flash Parameter Tables

Add (h) DW Add Data (h/b)

Data

(h)

Description

Comment

2000h=2.000V

2700h=2.700V

3600h=3.600V

(Byte)

(Bit)

(Note1)

07:00

15:08

00h

36h

00h

36h

Vcc Supply Maximum Voltage

61h:60h

1650h=1.650V

2250h=2.250V

2350h=2.350V

2700h=2.700V

23:16

31:24

00h

27h

00h

27h

Vcc Supply Minimum Voltage

H/W Reset# pin

63h:62h

0=not support 1=support

00

0b

H/W Hold# pin

0=not support 1=support

01

02

03

0b

1b

0b

Deep Power Down Mode

S/W Reset

Reset Enable (66h) should be

issued before Reset Opcode

1111 1111b

(FFh)

65h:64h

4FF4h

S/W Reset Opcode

11:04

Program Suspend/Resume

Erase Suspend/Resume

Unused

0=not support 1=support

12

13

0b

14

1b

Wrap-Around Read mode

Wrap-Around Read mode Opcode

0=not support 1=support

15

0b

66h

67h

23:16

FFh

08h:support 8B wrap-around read

16h:8B&16B

32h:8B&16B&32B

Wrap-Around Read data length

31:24

FFh

64h:8B&16B&32B&64B

Individual block lock

0=not support 1=support

0=Volatile 1=Nonvolatile

00

01

0b

1b

Individual block lock bit

(Volatile/Nonvolatile)

1111 1111b

(FFh)

Individual block lock Opcode

09:02

10

Individual block lock Volatile

protect bit default protect status

0=protect 1=unprotect

1b

CFFEh

6Bh:68h

Secured OTP

Read Lock

Permanent Lock

Unused

0=not support 1=support

11

12

1b

0b

13

0b

15:14

31:16

31:00

11b

FFh

Unused

FFh

Unused

6Fh:6Ch

P/N: PM1850

REV. 1.2, NOV. 11, 2013

48

MX25L1675E

Note 1: h/b is hexadecimal or binary.

Note 2: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x),

address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1), (2-2-2),

and (4-4-4)

Note 3: Wait States is required dummy clock cycles after the address bits or optional mode bits.

Note 4: Mode Bits is optional control bits that follow the address bits. These bits are driven by the system controller

if they are speciﬁed. (eg,read performance enhance toggling bits)

Note 5: 4KB=2^0Ch, 32KB=2^0Fh, 64KB=2^10h

Note 6: All unused and undeﬁned area data is blank FFh.

P/N: PM1850

REV. 1.2, NOV. 11, 2013

49

MX25L1675E

10. POWER-ON STATE

The device is at below states when power-up:

- Standby mode (please note it is not Deep Power-down mode)

- Write Enable Latch (WEL) bit is reset

The device must not be selected during power-up and power-down stage unless the VCC achieves below correct

level:

- VCC minimum at power-up stage and then after a delay of tVSL

- GND at power-down

Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.

An internal Power-on Reset (POR) circuit may protect the device from data corruption and inadvertent data change

during power up state.

For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not

guaranteed. The read, write, erase, and program command should be sent after the time delay:

- tVSL after VCC reached VCC minimum level

The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.

Note:

- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended.

(generally around 0.1uF)

P/N: PM1850

REV. 1.2, NOV. 11, 2013

50

MX25L1675E

11. ELECTRICAL SPECIFICATIONS

11-1. Absolute Maximum Ratings

RATING

VALUE

Ambient Operating Temperature

Storage Temperature

Applied Input Voltage

Applied Output Voltage

VCC to Ground Potential

Industrial grade

-40°C to 85°C

-65°C to 150°C

-0.5V to 4.6V

NOTICE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the

device. This is stress rating only and functional operational sections of this speciﬁcation is not implied. Exposure

to absolute maximum rating conditions for extended period may affect reliability.

2. Speciﬁcations contained within the following tables are subject to change.

3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see the

ﬁgures below.

Figure 29. Maximum Positive Overshoot Waveform

Figure 28. Maximum Negative Overshoot Waveform

20ns

Vcc + 2.0V

Vcc

Vss

Vss-2.0V

20ns

11-2. Capacitance

TA = 25°C, f = 1.0 MHz

SYMBOL PARAMETER

MIN.

TYP.

MAX.

UNIT

pF

CONDITIONS

VIN = 0V

CIN

Input Capacitance

6

8

COUT Output Capacitance

pF

VOUT = 0V

P/N: PM1850

REV. 1.2, NOV. 11, 2013

51

MX25L1675E

Figure 30. Input Test Waveforms and Measurement Level

Input timing reference level

Output timing reference level

0.8VCC

0.7VCC

AC

Measurement

Level

0.5VCC

0.3VCC

0.2VCC

Note: Input pulse rise and fall time are <5ns

Figure 31. Output Loading

DEVICE UNDER

TEST

2.7K ohm

+3.3V

CL

6.2K ohm

DIODES=IN3064

OR EQUIVALENT

CL=30/15pF Including jig capacitance

P/N: PM1850

REV. 1.2, NOV. 11, 2013

52

MX25L1675E

Table 12. DC Characteristics

Temperature = -40°C to 85°C for Industrial grade

SYMBOL PARAMETER

NOTES

MIN.

TYP.

MAX. UNITS TEST CONDITIONS

VCC = VCC Max,

VIN = VCC or GND

ILI

Input Load Current

1

± 2

25

uA

VCC = VCC Max,

VIN = VCC or GND

ILO

Output Leakage Current

1

VIN = VCC or GND,

CS# = VCC

ISB1 VCC Standby Current

15

2

Deep Power-down

Current

VIN = VCC or GND,

CS# = VCC

ISB2

20

f=104MHz,

fQ=85MHz (4 x I/O read)

SCLK=0.1VCC/0.9VCC,

SO=Open

25

mA

fT=85MHz (2 x I/O read)

mA SCLK=0.1VCC/0.9VCC,

ICC1 VCC Read

1

20

10

SO=Open

f=33MHz,

mA SCLK=0.1VCC/0.9VCC,

SO=Open

VCC Program Current

Program in Progress,

CS# = VCC

ICC2

(PP)

15

3

20

mA

VCC Write Status

ICC3

Program status register in

mA

Register (WRSR) Current

progress, CS#=VCC

VCC Sector Erase

Current (SE)

ICC4

1

9

mA Erase in Progress, CS#=VCC

VCC Chip Erase Current

ICC5

(CE)

15

VIL

VIH

VOL

Input Low Voltage

Input High Voltage

Output Low Voltage

-0.5

0.3VCC

VCC+0.4

0.4

V

0.7VCC

V

IOL = 1.6mA

IOH = -100uA

VOH Output High Voltage

VCC-0.2

Notes :

1. Typical values at VCC = 3.3V, T = 25 C. These currents are valid for all product versions (package and speeds).

°

2. Typical value is calculated by simulation.

P/N: PM1850

REV. 1.2, NOV. 11, 2013

53

MX25L1675E

Table 13. AC Characteristics

Temperature = -40°C to 85°C for Industrial grade

Symbol Alt. Parameter

Min.

Typ.

Max.

Unit

Clock Frequency for the following instructions:

fSCLK

fC FAST_READ, RDSFDP, SE, BE, CE, DP, RES, RDP,

WREN, WRDI, RDID, RDSR, WRSR

D.C.

104

MHz

fP Clock Frequency for PP instructions

f4P Clock Frequency for 4PP instructions

fR Clock Frequency for READ instructions

fT Clock Frequency for 2READ/DREAD instructions

fQ Clock Frequency for 4READ/QREAD instructions

fC=104MHz

D.C.

86

85

33

85

MHz

ns

V/ns

ns

fPSCLK

fRSCLK

fTSCLK

4.7

13

4.7

13

0.1

5

tCH(1) tCLH Clock High Time

fR=33MHz

fC=104MHz

fR=33MHz

tCL(1)

tCLL Clock Low Time

Clock Rise Time (3) (peak to peak)

Clock Fall Time (3) (peak to peak)

tCLCH(2)

tCHCL(2)

tSLCH tCSS CS# Active Setup Time (relative to SCLK)

tCHSL CS# Not Active Hold Time (relative to SCLK)

tDVCH tDSU Data In Setup Time

5

2

tCHDX

tCHSH

tSHCH

tDH Data In Hold Time

5

15

50

ns

CS# Active Hold Time (relative to SCLK)

CS# Not Active Setup Time (relative to SCLK)

Read

tSHSL(3) tCSH CS# Deselect Time

Write/Erase/Program

2.7V-3.6V

3.0V-3.6V

10

8

tSHQZ(2) tDIS Output Disable Time

2.7V-3.6V

9/8

8/6

ns

Clock Low to Output Valid

tCLQV

tV

Loading: 30pF/15pF

tHO Output Hold Time

Write Protect Setup Time

3.0V-3.6V

ns

tCLQX

tWHSL

tSHWL

tDP(2)

0

20

100

Write Protect Hold Time

CS# High to Deep Power-down Mode

10

us

CS# High to Standby Mode without Electronic Signature

Read

tRES1(2)

8.8

us

tRES2(2)

tW

CS# High to Standby Mode with Electronic Signature Read

Write Status Register Cycle Time

Byte-Program

Page Program Cycle Time

Sector Erase Cycle Time

8.8

100

50

3

200

2

us

ms

us

ms

s

40

9

0.6

40

0.4

5

tBP

tPP

tSE

tBE

Block Erase Cycle Time

Chip Erase Cycle Time

tCE

20

s

Notes:

1. tCH + tCL must be greater than or equal to 1/ f (fC or fR).

2. Value guaranteed by characterization, not 100% tested in production.

3. tSHSL=15ns from read instruction, tSHSL=50ns from Write/Erase/Program instruction.

4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.

5. Test condition is shown as "Figure 30. Input Test Waveforms and Measurement Level" and "Figure 31. Output

Loading".

P/N: PM1850

REV. 1.2, NOV. 11, 2013

54

MX25L1675E

12. TIMING ANALYSIS

Figure 32. Serial Input Timing

tSHSL

tSHCH

tCHCL

CS#

tCHSL

tSLCH

tCHSH

SCLK

tDVCH

tCHDX

tCLCH

MSB

LSB

SI

High-Z

SO

Figure 33. Output Timing

CS#

tCH

SCLK

tCLQV

tCL

tSHQZ

tCLQX

SO

tCLQX

LSB

ADDR.LSB IN

SI

P/N: PM1850

REV. 1.2, NOV. 11, 2013

55

MX25L1675E

Figure 34. Power-Up Timing

V

CC

V

(max)

CC

Chip Selection is Not Allowed

V

(min)

CC

Device is fully accessible

tVSL

time

Note: VCC (max.) is 3.6V and VCC (min.) is 2.7V.

Table 14. Power-Up Timing

Symbol Parameter

Min.

Max.

Unit

tVSL(1)

VCC(min) to CS# low

200

us

Note: The parameter is characterized only.

12-1. Initial Delivery State

The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status

Register contains 00h (all Status Register bits are 0).

P/N: PM1850

REV. 1.2, NOV. 11, 2013

56

MX25L1675E

13. OPERATING CONDITIONS

At Device Power-Up and Power-Down

AC timing illustrated in "Figure 35. AC Timing at Device Power-Up" and "Figure 36. Power-Down Sequence" are

for the supply voltages and the control signals at device power-up and power-down. If the timing in the ﬁgures is

ignored, the device will not operate correctly.

During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be

selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.

Figure 35. AC Timing at Device Power-Up

VCC(min)

VCC

GND

tVR

tSHSL

CS#

tSHCH

tSLCH

tCHSL

tCHSH

SCLK

tDVCH

tCHCL

tCHDX

tCLCH

MSB IN

LSB IN

SI

High Impedance

SO

Symbol

tVR

Parameter

VCC Rise Time

Notes

Min.

5

Max.

500000

Unit

us/V

1

Notes :

1. Sampled, not 100% tested.

2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the ﬁgure, please refer

to "Table 13. AC Characteristics".

P/N: PM1850

REV. 1.2, NOV. 11, 2013

57

MX25L1675E

Figure 36. Power-Down Sequence

During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.

VCC

CS#

SCLK

P/N: PM1850

REV. 1.2, NOV. 11, 2013

58

MX25L1675E

14. ERASE AND PROGRAMMING PERFORMANCE

PARAMETER

Min.

TYP. (1)

Max. (2)

UNIT

ms

s

Write Status Register Cycle Time

Sector Erase Cycle Time

Block Erase Cycle Time

40

100

200

2

0.4

Chip Erase Cycle Time

5

20

50

3

s

Byte Program Time (via page program command)

Page Program Cycle Time

Erase/Program Cycle

9

us

0.6

ms

cycles

100,000

Notes:

1. Typical program and erase time assumes the following conditions: 25 C, 3.3V, and checker board pattern.

°

2. Under worst conditions of 85 C and 2.7V.

°

3. System-level overhead is the time required to execute the ﬁrst-bus-cycle sequence for the programming com-

mand.

15. DATA RETENTION

PARAMETER

Condition

Min.

Max.

UNIT

Data retention

55˚C

20

years

16. LATCH-UP CHARACTERISTICS

MIN.

MAX.

Input Voltage with respect to GND on all power pins, SI, CS#

Input Voltage with respect to GND on SO

Current

-1.0V

-100mA

2 VCCmax

VCC + 1.0V

+100mA

Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.

P/N: PM1850

REV. 1.2, NOV. 11, 2013

59

MX25L1675E

17. ORDERING INFORMATION

PART NO.

CLOCK (MHz)

TEMPERATURE

PACKAGE

Remark

8-SOP

(200mil)

8-WSON

(6x5mm)

MX25L1675EM2I-10G

104

-40°C~85°C

MX25L1675EZNI-10G

104

-40°C~85°C

*

* Advanced Information.

P/N: PM1850

REV. 1.2, NOV. 11, 2013

60

MX25L1675E

18. PART NAME DESCRIPTION

M2

MX 25 L 1675E

I

10 G

OPTION:

G: RoHS Compliant & Halogen-free

SPEED:

10: 104MHz

TEMPERATURE RANGE:

I: Industrial (-40° C to 85° C)

PACKAGE:

M2: 200mil 8-SOP

ZN: 6x5mm 8-WSON

DENSITY & MODE:

1675E: 16Mb standard type

TYPE:

L: 3V

DEVICE:

25: Serial Flash

P/N: PM1850

REV. 1.2, NOV. 11, 2013

61

MX25L1675E

P/N: PM1850

REV. 1.2, NOV. 11, 2013

62

MX25L1675E

P/N: PM1850

REV. 1.2, NOV. 11, 2013

63

MX25L1675E

19. REVISION HISTORY

Revision No. Description

Page

Date

0.00

1.0

1.1

1. Initial released

1. Added 8-WSON packages as Advanced Information

1. Added QREAD/DREAD function

All

JUN/06/2012

JUL/05/2012

P5,7,57~58,60

P12,13,25,27,54 OCT/18/2012

2. Updated 1-1-2, 1-1-4 parameter values in SFDP Table

1. Updated parameters for DC Characteristics.

2. Updated Erase and Programming Performance.

P46,47

P4,53

P4,54,59

1.2

NOV/11/2013

P/N: PM1850

REV. 1.2, NOV. 11, 2013

64

MX25L1675E

Except for customized products which have been expressly identiﬁed in the applicable agreement, Macronix's products are

designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and

not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. In

the event Macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to

ensure said Macronix's product qualiﬁed for its actual use in accordance with the applicable laws and regulations; and Macro-

nix as well as it’s suppliers and/or distributors shall be released from any and all liability arisen therefrom.

such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit, NBiit, Macronix NBit, eLiteFlash, Hy-

bridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC, Kingtech, MXSMIO, Macronix vEE, Macronix MAP,

Rich Audio, Rich Book, Rich TV, and FitCAM. The names and brands of third party referred thereto (if any) are for identiﬁcation

purposes only.

For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and speciﬁcations without notice.

65


型号：	MX25L1675EZNI-10G
厂家：	MACRONIX INTERNATIONAL
描述：	Flash, 4MX4, PDSO8, 6 X 5 MM, 0.80 MM HEIGHT, 1.27 MM PITCH, HALOGEN FREE AND ROHS COMPLIANT, MO-220, WSON-8 时钟光电二极管内存集成电路
文件：	总65页 (文件大小：761K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MX25L1675EZNI-10G [Macronix]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E