MX25L2006EM1I-12G [Macronix]
Flash, 1MX2, PDSO8, 0.150 INCH, HALOGEN FREE AND ROHS COMPLIANT, MS-012, SOP-8;
| 型号： | MX25L2006EM1I-12G |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | Flash, 1MX2, PDSO8, 0.150 INCH, HALOGEN FREE AND ROHS COMPLIANT, MS-012, SOP-8 时钟 光电二极管 内存集成电路 |
| 文件： | 总50页 (文件大小：1023K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MX25L2006E
MX25L2006E
DATASHEET
P/N: PM1578
REV.1.5, NOV. 14, 2013
1
MX25L2006E
Contents
FEATURES ................................................................................................................................................. 4
GENERAL DESCRIPTION ........................................................................................................................ 5
PIN CONFIGURATIONS............................................................................................................................. 5
PIN DESCRIPTION..................................................................................................................................... 5
BLOCK DIAGRAM...................................................................................................................................... 6
MEMORY ORGANIZATION........................................................................................................................ 7
Table 1. Memory Organization ............................................................................................................................. 7
DEVICE OPERATION................................................................................................................................. 8
Figure 1. Serial Peripheral Interface Modes Supported .......................................................................................8
DATA PROTECTION................................................................................................................................... 9
Table 2. Protected Area Sizes .............................................................................................................................. 9
HOLD FEATURE....................................................................................................................................... 10
Figure 2. Hold Condition Operation ................................................................................................................... 10
Table 3. COMMAND DEFINITION ..................................................................................................................... 11
COMMAND DESCRIPTION...................................................................................................................... 12
(1) Write Enable (WREN)...................................................................................................................................12
(2) Write Disable (WRDI)....................................................................................................................................12
(3) Read Status Register (RDSR) ...................................................................................................................... 13
(4) Write Status Register (WRSR)...................................................................................................................... 14
Table 4. Protection Modes..................................................................................................................................14
(5) Read Data Bytes (READ) ............................................................................................................................. 15
(6) Read Data Bytes at Higher Speed (FAST_READ) .......................................................................................15
(7) Dual Output Mode (DREAD)......................................................................................................................... 15
(8) Sector Erase (SE).........................................................................................................................................15
(9) Block Erase (BE)...........................................................................................................................................16
(10) Chip Erase (CE)..........................................................................................................................................16
(11) Page Program (PP).....................................................................................................................................16
(12) Deep Power-down (DP).............................................................................................................................. 17
(13) Release from Deep Power-down (RDP), Read Electronic Signature (RES) ............................................. 17
(14) Read Identification (RDID).......................................................................................................................... 18
(15) Read Electronic Manufacturer ID & Device ID (REMS)..............................................................................18
Table 5. ID Definitions ........................................................................................................................................18
(16) Read SFDP Mode (RDSFDP)..................................................................................................................... 19
Read Serial Flash Discoverable Parameter (RDSFDP) Sequence....................................................................19
Table a. Signature and Parameter Identification Data Values ...........................................................................20
Table b. Parameter Table (0): JEDEC Flash Parameter Tables .........................................................................21
Table c. Parameter Table (1): Macronix Flash Parameter Tables.......................................................................23
POWER-ON STATE.................................................................................................................................. 25
ELECTRICAL SPECIFICATIONS............................................................................................................. 26
ABSOLUTE MAXIMUM RATINGS..................................................................................................................... 26
P/N: PM1578
REV.1.5, NOV. 14, 2013
2
MX25L2006E
Figure 3.Maximum Negative Overshoot Waveform ...........................................................................................26
CAPACITANCE TA = 25°C, f = 1.0 MHz............................................................................................................. 26
Figure 4. Maximum Positive Overshoot Waveform............................................................................................26
Figure 5. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL..............................................................27
Figure 6. OUTPUT LOADING ........................................................................................................................... 27
Table 6. DC CHARACTERISTICS (Temperature = -40°C to 85°C, VCC = 2.7V ~ 3.6V) ................................. 28
Table 7. AC CHARACTERISTICS (Temperature = -40°C to 85°C, VCC = 2.7V ~ 3.6V) ................................. 29
Table 8. Power-Up Timing ..................................................................................................................................30
Timing Analysis....................................................................................................................................... 31
Figure 7. Serial Input Timing .............................................................................................................................. 31
Figure 8. Output Timing......................................................................................................................................31
Figure 9. Hold Timing .........................................................................................................................................32
Figure 10. WP# Disable Setup and Hold Timing during WRSR when SRWD=1 ............................................... 32
Figure 11. Write Enable (WREN) Sequence (Command 06) .............................................................................33
Figure 12. Write Disable (WRDI) Sequence (Command 04)..............................................................................33
Figure 13. Read Status Register (RDSR) Sequence (Command 05) ................................................................33
Figure 14. Write Status Register (WRSR) Sequence (Command 01)...............................................................34
Figure 15. Read Data Bytes (READ) Sequence (Command 03) ......................................................................34
Figure 16. Read at Higher Speed (FAST_READ) Sequence (Command 0B)................................................... 35
Figure 17. Dual Output Read Mode Sequence (Command 3B).........................................................................35
Figure 18. Sector Erase (SE) Sequence (Command 20)..................................................................................36
Figure 19. Block Erase (BE) Sequence (Command 52 or D8)..........................................................................36
Figure 20. Chip Erase (CE) Sequence (Command 60 or C7)...........................................................................36
Figure 21. Page Program (PP) Sequence (Command 02)................................................................................37
Figure 22. Deep Power-down (DP) Sequence (Command B9).........................................................................37
Figure 23. Read Electronic Signature (RES) Sequence (Command AB)..........................................................38
Figure 24. Release from Deep Power-down (RDP) Sequence (Command AB) ............................................... 38
Figure 25. Read Identification (RDID) Sequence (Command 9F)......................................................................39
Figure 26. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90).............................. 39
Figure 27. Power-up Timing ............................................................................................................................... 40
OPERATING CONDITIONS...................................................................................................................... 41
Figure 28. AC Timing at Device Power-Up......................................................................................................... 41
Figure 29. Power-Down Sequence .................................................................................................................... 42
ERASE AND PROGRAMMING PERFORMANCE................................................................................... 43
DATA RETENTION .................................................................................................................................. 43
LATCH-UP CHARACTERISTICS............................................................................................................. 43
ORDERING INFORMATION..................................................................................................................... 44
PART NAME DESCRIPTION.................................................................................................................... 45
PACKAGE INFORMATION....................................................................................................................... 46
REVISION HISTORY ................................................................................................................................ 49
P/N: PM1578
REV.1.5, NOV. 14, 2013
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MX25L2006E
2M-BIT [x 1/x 2] CMOS SERIAL FLASH
FEATURES
GENERAL
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• 2,097,152 x 1 bit structure or 1,048,576 x 2 bits (Dual Output mode) structure
• 64 Equal Sectors with 4K byte each
- Any Sector can be erased individually
• 4 Equal Blocks with 64K byte each
- Any Block can be erased individually
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
- Fast access time: 86MHz serial clock
- Serial clock of Dual Output mode: 80MHz
- Fast program time: 0.6ms(typ.) and 3ms(max.)/page
- Byte program time: 9us (typ.)
- Fast erase time: 40ms(typ.)/sector (4K-byte per sector) ; 0.4s(typ.)/block (64K-byte per block)
• Low Power Consumption
- Low active read current: 12mA(max.) at 86MHz and 4mA(max.) at 33MHz
- Low active programming current: 15mA (typ.)
- Low active sector erase current: 9mA (typ.)
- Low standby current: 15uA (typ.)
- Deep power-down mode 2uA (typ.)
• Minimum 100,000 erase/program cycles
• 20 years data retention
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Block Lock protection
- The BP0~BP1 status bit defines the size of the area to be software protected against Program and Erase in-
structions
• Auto Erase and Auto Program Algorithm
Automatically erases and verifies data at selected sector
Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse widths (Any page to be programed should have page in the erased state first)
-
-
• Status Register Feature
• Electronic Identification
JEDEC 2-byte Device ID
- RES command, 1-byte Device ID
-
• Support Serial Flash Discoverable Parameters (SFDP) mode
HARDWARE FEATURES
• PACKAGE
8-pin SOP (150mil)
- 8-land WSON (6x5mm, 0.8mm package height)
-
- 8-land USON (2x3x0.6mm)
- All devices are RoHS Compliant and Halogen-free
P/N: PM1578
REV.1.5, NOV. 14, 2013
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MX25L2006E
GENERAL DESCRIPTION
The device features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus.
The four bus signals are a clock input (SCLK), a serial data input (SI), a serial data output (SO), and a chip select (CS#).
Serial access to the device is enabled by CS# input.
When it is in Dual Output read mode, the SI and SO pins become SIO0 and SIO1 pins for data output.
The device provides sequential read operation on whole chip.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the speci-
fied page or sector/block locations will be executed. Program command is executed on byte basis, or page basis, or
word basis for erase command is executes on sector, or block, or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
When the device is not in operation and CS# is high, it is put in standby mode.
The device utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000
program and erase cycles.
PIN CONFIGURATIONS
8-PIN SOP (150mil)
PIN DESCRIPTION
SYMBOL DESCRIPTION
CS#
Chip Select
1
Serial Data Input (for 1 x I/O) / Serial Data
Input & Output (for Dual Output mode)
Serial Data Output (for 1 x I/O) / Serial
Data Output (for Dual Output mode)
CS#
VCC
8
7
6
5
SI/SIO0
2
3
4
SO/SIO1
WP#
HOLD#
SCLK
SO/SIO1
GND
SI/SIO0
SCLK Clock Input
WP# Write Protection
8-LAND, WSON (6x5mm)
Hold, to pause the device without
deselecting the device
HOLD#
VCC
GND Ground
+ 3.3V Power Supply
1
2
3
4
VCC
CS#
SO/SIO1
WP#
8
7
6
5
HOLD#
SCLK
SI/SIO0
GND
8-LAND USON (2x3mm)
1
2
3
4
VCC
CS#
SO/SIO1
WP#
8
7
6
5
HOLD#
SCLK
SI/SIO0
GND
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REV.1.5, NOV. 14, 2013
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MX25L2006E
BLOCK DIAGRAM
Address
Generator
Memory Array
Page Buffer
Data
Register
SI
Y-Decoder
SRAM
Buffer
Output
Buffer
Sense
Amplifier
Mode
Logic
State
Machine
CS#
HV
Generator
SO
SCLK
Clock Generator
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REV.1.5, NOV. 14, 2013
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MX25L2006E
MEMORY ORGANIZATION
Table 1. Memory Organization
Block
Sector
63
:
Address Range
03F000h 03FFFFh
3
:
:
48
47
:
32
31
:
030000h
02F000h
:
020000h
01F000h
:
030FFFh
02FFFFh
:
020FFFh
01FFFFh
:
2
1
16
15
:
010000h
00F000h
:
010FFFh
00FFFFh
:
3
2
1
0
003000h
002000h
001000h
000000h
003FFFh
002FFFh
001FFFh
000FFFh
0
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MX25L2006E
DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended opera-
tion.
2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode
until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z. The CS# falling time needs to
follow tCHCL spec.
3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until
next CS# rising edge. The CS# rising time needs to follow tCLCH spec.
4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK.
The difference of serial peripheral interface mode 0 and mode 3 is shown as Figure 1.
5. For the following instructions: RDID, RDSR, READ, FAST_READ, RDSFDP, DREAD, RES and REMS the shift-
ed-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS#
can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE, CE, PP, RDP and DP the CS# must
go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglected
and not affect the current operation of Write Status Register, Program, Erase.
Figure 1. Serial Peripheral Interface Modes Supported
CPOL CPHA
shift out
shift in
SCLK
SCLK
(Serial mode 0)
(Serial mode 3)
0
1
0
1
SI
MSB
SO
MSB
Note:
CPOL indicates clock polarity of serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which serial mode is
supported.
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REV.1.5, NOV. 14, 2013
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MX25L2006E
DATA PROTECTION
During power transition, there may be some false system level signals which result in inadvertent erasure or
programming. The device is designed to protect itself from these accidental write cycles.
The state machine will be reset as standby mode automatically during power up. In addition, the control register
architecture of the device constrains that the memory contents can only be changed after specific command
sequences have completed successfully.
In the following, there are several features to protect the system from the accidental write cycles during VCC power-
up and power-down or from system noise.
• Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other command to change data. The WEL bit will return to reset stage under following situation:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP) command completion
- Sector Erase (SE) command completion
- Block Erase (BE) command completion
- Chip Erase (CE) command completion
•
Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from
writing all commands except Release from deep power down mode command (RDP) and Read Electronic Sig-
nature command (RES).
I. Block lock protection
- Software Protection Mode (SPM): by using BP0-BP1 bits to set the part of Flash protected from data change.
- Hardware Protection Mode (HPM): by using WP# going low to protect the BP0-BP1 bits and SRWD bit from
data change.
Table 2. Protected Area Sizes
Status bit
Protect level
2Mb
BP1
BP0
0
0
1
1
0
1
0
1
0 (none)
1 (1 block)
2 (2 blocks)
3 (All)
None
Block 3
Block 2-3
All
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REV.1.5, NOV. 14, 2013
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MX25L2006E
HOLD FEATURE
HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the
operation of write status register, programming, or erasing in progress.
The operation of HOLD requires Chip Select(CS#) keeping low and starts on falling edge of HOLD# pin signal
while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start
until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Se-
rial Clock(SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not end until Serial
Clock being low), see Figure 2.
Figure 2. Hold Condition Operation
SCLK
HOLD#
Hold
Hold
Condition
Condition
(standard use)
(non-standard use)
The Serial Data Output (SO) is high impedance, both Serial Data Input (SI) and Serial Clock (SCLK) are don't care
during the HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of
the device. To re-start communication with chip, the HOLD# must be at high and CS# must be at low.
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REV.1.5, NOV. 14, 2013
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MX25L2006E
Table 3. COMMAND DEFINITION
RDID
(read
identi-
fication)
WREN
(write
Enable)
WRSR
(write status
register)
RDSR
(read status
register)
Fast Read
(fast read
data)
COMMAND
(byte)
WRDI
(write disable)
READ
(read data)
1st
2nd
3rd
4th
5th
06 Hex
04 Hex
01 Hex
9F Hex
05 Hex
03 Hex
AD1
AD2
0B Hex
AD1
AD2
AD3
Dummy
AD3
sets the
reset the
to write new
output the
to read out n bytes read n bytes read
(WEL) write (WEL) write status register manufacturer the status out until CS# out until CS#
Action
enable latch enable latch
ID and 2-byte
device ID
register
goes high
goes high
bit
bit
REMS (Read
Electronic
DREAD
(Double
SE
(Sector
Erase)
COMMAND
(byte)
RDSFDP
RES (Read
BE
CE
(Read SFDP) Electronic ID) Manufacturer Output Mode
& Device ID) command)
(Block Erase) (Chip Erase)
1st
2nd
3rd
4th
5th
5A Hex
AD1
AD2
AD3
Dummy
AB Hex
90 Hex
3B Hex
AD1
AD2
AD3
Dummy
20 Hex
AD1
AD2
52 or D8 Hex 60 or C7 Hex
x
x
x
x
x
AD1
AD2
AD3
ADD(1)
AD3
Read SFDP to read out
Output the n bytes read to erase the to erase the
to erase
mode 1-byte Device manufacturer out by Dual
selected
sector
selected
block
whole chip
Action
ID
ID and device Output until
ID
CS# goes
high
RDP (Release
from Deep
Power-down)
AB Hex
COMMAND PP (Page
DP (Deep
(byte)
Program) Power Down)
1st
2nd
3rd
4th
5th
02 Hex
AD1
AD2
B9 Hex
AD3
to program enters deep release from
the selected power down deep power
Action
page
mode
down mode
(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first.
(2) It is not recommended to adopt any other code which is not in the above command definition table.
P/N: PM1578
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MX25L2006E
COMMAND DESCRIPTION
(1) Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, SE,
BE, CE, and WRSR, which are intended to change the device content, should be set every time after the WREN in-
struction setting the WEL bit.
The sequence is shown as Figure 11.
(2) Write Disable (WRDI)
The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.
The sequence is shown as Figure 12.
The WEL bit is reset by following situations:
- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase (BE) instruction completion
- Chip Erase (CE) instruction completion
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MX25L2006E
(3) Read Status Register (RDSR)
The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in
program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP)
bit before sending a new instruction when a program, erase, or write status register operation is in progress.
The sequence is shown as Figure 13.
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write
status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status
register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status
register cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable
latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/
erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the de-
vice will not accept program/erase/write status register instruction.
BP1, BP0 bits. The Block Protect (BP1, BP0) bits, non-volatile bits, indicate the protected area(as defined in table-
2) of the device to against the program/erase instruction without hardware protection mode being set. To write the
Block Protect (BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits
define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE) and
Chip Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed)
SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protec-
tion (WP#) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1
and WP# pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is
no longer accepted for execution and the SRWD bit and Block Protect bits (BP1, BP0) are read only.
bit 7
bit 6
0
bit 5
0
bit 4
0
bit 3
BP1
bit 2
BP0
bit 1
bit 0
SRWD Status
Register
(the level
(the level
WEL (write WIP (write in
of protected of protected enable latch) progress bit)
Write Protect
block)
block)
1=write
enable
1=write
1= status
register write
disable
operation
0
0
0
(note 1)
(note 1)
0=not write 0=not in write
enable
operation
Note:
1. See the table "Protected Area Sizes".
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MX25L2006E
(4) Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the
Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in ad-
vance. The WRSR instruction can change the value of Block Protect (BP1, BP0) bits to define the protected area
of memory (as shown in table 2). The WRSR also can set or reset the Status Register Write Disable (SRWD) bit in
accordance with Write Protection (WP#) pin signal. The WRSR instruction cannot be executed once the Hardware
Protected Mode (HPM) is entered.
The sequence is shown as Figure 14.
The WRSR instruction has no effect on b6, b5, b1, b0 of the status register.
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1
during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL)
bit is reset.
Table 4. Protection Modes
Mode
Status register condition
WP# and SRWD bit status
Memory
Status register can be written
in (WEL bit is set to "1") and
the SRWD, BP1-BP0
Software protection
mode (SPM)
WP#=1 and SRWD bit=0, or
WP#=0 and SRWD bit=0, or
WP#=1 and SRWD=1
The protected area
cannot
be program or erase.
bits can be changed
The SRWD, BP1-BP0 of
status register bits cannot be
changed
The protected area
cannot
be program or erase.
Hardware protection
mode (HPM)
WP#=0, SRWD bit=1
Note:
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 2.
As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM).
Software Protected Mode (SPM):
-
When SRWD bit=0, no matter WP# is low or high, the WREN instruction may set the WEL bit and can change
the values of SRWD, BP1, BP0. The protected area, which is defined by BP1, BP0, is at software protected
mode (SPM).
-
When SRWD bit=1 and WP# is high, the WREN instruction may set the WEL bit can change the values of
SRWD, BP1, BP0. The protected area, which is defined by BP1, BP0, is at software protected mode (SPM).
Note: If SRWD bit=1 but WP# is low, it is impossible to write the Status Register even if the WEL bit has previously
been set. It is rejected to write the Status Register and not be executed.
Hardware Protected Mode (HPM):
-
When SRWD bit=1, and then WP# is low (or WP# is low before SRWD bit=1), it enters the hardware protected
mode (HPM). The data of the protected area is protected by software protected mode by BP1, BP0 and hard-
ware protected mode by the WP# to against data modification.
Note: to exit the hardware protected mode requires WP# driving high once the hardware protected mode is entered.
If the WP# pin is permanently connected to high, the hardware protected mode can never be entered; only
can use software protected mode via BP1, BP0.
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MX25L2006E
(5) Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on
the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address
is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can
be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been
reached.
The sequence is shown as Figure 15.
(6) Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at
any location. The address is automatically increased to the next higher address after each byte data is shifted out,
so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when
the highest address has been reached.
The sequence is shown as Figure 16.
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any im-
pact on the Program/Erase/Write Status Register current cycle.
(7) Dual Output Mode (DREAD)
The DREAD instruction enable double throughput of Serial Flash in read mode. The address is latched on rising
edge of SCLK, and data of every two bits(interleave on 1I/2O pins) shift out on the falling edge of SCLK at a maxi-
mum frequency fT. The first address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD instruc-
tion. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruc-
tion, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit.
The sequence is shown as Figure 17.
While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
The DREAD only perform read operation. Program/Erase /Read ID/Read status....operation do not support DREAD
throughputs.
(8) Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". A Write Enable (WREN) in-
struction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address
of the sector (see table 1) is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the
byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not
executed.
Address bits [Am-A12] (Am is the most significant address) select the sector address.
P/N: PM1578
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MX25L2006E
The sequence is shown as Figure 18.
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the
tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
page is protected by BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the page.
(9) Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". A Write Enable (WREN) in-
struction must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address
of the block (see table 1) is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the
byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not
executed.
The sequence is shown as Figure 19.
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the
tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
page is protected by BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the page.
(10) Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruc-
tion must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). Any address of the
sector (see table 1) is a valid address for Chip Erase (CE) instruction. The CS# must go high exactly at the byte
boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not ex-
ecuted.
The sequence is shown as Figure 20.
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE
timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is
protected by BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when BP1,
BP0 all set to "0".
(11) Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruc-
tion must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device
programs only the last 256 data bytes sent to the device. The last address byte (the 8 least significant address
bits, A7-A0) should be set to 0 for 256 bytes page program. If A7-A0 are not all zero, transmitted data that exceed
page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently selected
page. If the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the request page
and previous data will be disregarded. If the data bytes sent to the device has not exceeded 256, the data will be
programmed at the request address of the page. There will be no effort on the other data bytes of the same page.
P/N: PM1578
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MX25L2006E
The sequence is shown as Figure 21.
The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte
boundary( the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be ex-
ecuted.
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the
tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
page is protected by BP1, BP0 bits, the Page Program (PP) instruction will not be executed.
(12) Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to enter-
ing the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode
requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not ac-
tive and all Write/Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep
power-down mode. It's different from Standby mode.
The sequence is shown as Figure 22.
Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP)
and Read Electronic Signature (RES) instruction. (RES instruction to allow the ID been read out). When Power-
down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby
mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction
code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay
of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2.
(13) Release from Deep Power-down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip
Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the
Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in
the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip
Select (CS#) must remain High for at least tRES2(max), as specified in Table 7. Once in the Stand-by Power mode,
the device waits to be selected, so that it can receive, decode and execute instructions.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID
Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new deisng,
please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed,
only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/
write cycle in progress.
The sequence is shown as Figure 23 and Figure 24.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeat-
edly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously
in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in
Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least
tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute
instruction.
P/N: PM1578
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MX25L2006E
The RDP instruction is for releasing from Deep Power Down Mode.
(14) Read Identification (RDID)
The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Macronix
Manufacturer ID and Device ID are listed as table of "ID Definitions".
The sequence is shown as Figure 25.
While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cy-
cle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.
(15) Read Electronic Manufacturer ID & Device ID (REMS)
The REMS instruction is an alternative to the Release from Power-down/Device ID instruction that provides both the
JEDEC assigned manufacturer ID and the specific device ID.
The REMS instruction is very similar to the Release from Power-down/Device ID instruction. The instruction is initi-
ated by driving the CS# pin low and shift the instruction code "90h" followed by two dummy bytes and one bytes ad-
dress (A7~A0). After which, the Manufacturer ID for Macronix (C2h) and the Device ID are shifted out on the falling
edge of SCLK with most significant bit (MSB) first as shown in Figure 26. The Device ID values are listed in Table 5.
ID Definitions. If the one-byte address is initially set to 01h, then the device ID will be read first and then followed by
the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other.
The instruction is completed by driving CS# high.
Table 5. ID Definitions
Command Type
MX25L2006E
memory type
20
manufacturer ID
C2
memory density
12
RDID Command
electronic ID
11
RES Command
manufacturer ID
C2
device ID
11
REMS Command
P/N: PM1578
REV.1.5, NOV. 14, 2013
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MX25L2006E
(16) Read SFDP Mode (RDSFDP)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional
and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables
can be interrogated by host system software to enable adjustments needed to accommodate divergent features
from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on
CFI.
The sequence of issuing RDSFDP instruction is CS# goes low→send RDSFDP instruction (5Ah)→send 3 address
bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP operation can use CS#
to high at any time during data out.
SFDP is a JEDEC Standard, JESD216.
Read Serial Flash Discoverable Parameter (RDSFDP) Sequence
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
SCLK
Command
5Ah
24 BIT ADDRESS
SI
23 22 21
3
2
1
0
High-Z
SO
CS#
47
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
SCLK
Dummy Cycle
7
6
5
4
3
2
0
1
SI
DATA OUT 2
DATA OUT 1
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
SO
MSB
MSB
MSB
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MX25L2006E
Table a. Signature and Parameter Identification Data Values
Description Comment
Add (h) DW Add Data (h/b)
Data
(h)
(Byte)
(Bit)
(Note1)
00h
07:00
53h
53h
46h
44h
50h
00h
01h
01h
02h
03h
04h
05h
15:08
23:16
31:24
07:00
15:08
46h
44h
50h
00h
01h
SFDP Signature
Fixed: 50444653h
SFDP Minor Revision Number
Start from 00h
Start from 01h
SFDP Major Revision Number
This number is 0-based. Therefore,
0 indicates 1 parameter header.
Number of Parameter Headers
Unused
06h
07h
08h
09h
0Ah
0Bh
23:16
31:24
07:00
15:08
23:16
31:24
01h
FFh
00h
00h
01h
09h
01h
FFh
00h
00h
01h
09h
00h: it indicates a JEDEC specified
header.
ID number (JEDEC)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length
(in double word)
Start from 00h
Start from 01h
How many DWORDs in the
Parameter table
0Ch
0Dh
0Eh
07:00
15:08
23:16
30h
00h
00h
30h
00h
00h
First address of JEDEC Flash
Parameter table
Parameter Table Pointer (PTP)
Unused
0Fh
10h
11h
12h
13h
31:24
07:00
15:08
23:16
31:24
FFh
C2h
00h
01h
04h
FFh
C2h
00h
01h
04h
ID number
(Macronix manufacturer ID)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length
(in double word)
it indicates Macronix manufacturer
ID
Start from 00h
Start from 01h
How many DWORDs in the
Parameter table
14h
15h
16h
07:00
15:08
23:16
60h
00h
00h
60h
00h
00h
First address of Macronix Flash
Parameter table
Parameter Table Pointer (PTP)
Unused
17h
31:24
FFh
FFh
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MX25L2006E
Table b. Parameter Table (0): JEDEC Flash Parameter Tables
Add (h) DW Add Data (h/b)
Data
(h)
Description
Comment
(Byte)
(Bit)
(Note1)
00: Reserved, 01: 4KB erase,
10: Reserved,
11: not support 4KB erase
Block/Sector Erase sizes
Write Granularity
01:00
01b
0: 1Byte, 1: 64Byte or larger
02
03
1b
0b
Write Enable Instruction Required 0: not required
for Writing to Volatile Status
1: required 00h to be written to the
Registers
status register
30h
E5h
0: use 50h opcode,
1: use 06h opcode
Write Enable Opcode Select for
Writing to Volatile Status Registers
Note: If target flash status register is
nonvolatile, then bits 3 and 4 must
be set to 00b.
04
0b
Contains 111b and can never be
changed
Unused
07:05
111b
4KB Erase Opcode
31h
32h
33h
15:08
16
20h
1b
20h
81h
FFh
(1-1-2) Fast Read (Note2)
0=not support 1=support
Address Bytes Number used in
addressing flash array
00: 3Byte only, 01: 3 or 4Byte,
10: 4Byte only, 11: Reserved
18:17
19
00b
0b
Double Transfer Rate (DTR)
Clocking
0=not support 1=support
(1-2-2) Fast Read
(1-4-4) Fast Read
(1-1-4) Fast Read
Unused
0=not support 1=support
0=not support 1=support
0=not support 1=support
20
21
0b
0b
22
0b
23
1b
Unused
31:24
FFh
Flash Memory Density
37h:34h 31:00
001F FFFFh
(1-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
04:00
38h
0 0000b
states (Note3)
Clocks) not support
00h
FFh
00h
FFh
(1-4-4) Fast Read Number of
Mode Bits (Note4)
000b: Mode Bits not support
07:05
000b
FFh
(1-4-4) Fast Read Opcode
39h
3Ah
3Bh
15:08
20:16
(1-1-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
0 0000b
states
Clocks) not support
(1-1-4) Fast Read Number of
Mode Bits
000b: Mode Bits not support
23:21
31:24
000b
FFh
(1-1-4) Fast Read Opcode
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MX25L2006E
Add (h) DW Add Data (h/b)
Data
(h)
Description
Comment
(Byte)
(Bit)
(Note1)
(1-1-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy
04:00
0 1000b
states
Clocks) not support
3Ch
08h
3Bh
00h
FFh
(1-1-2) Fast Read Number of
Mode Bits
000b: Mode Bits not support
07:05
15:08
20:16
000b
3Bh
(1-1-2) Fast Read Opcode
3Dh
3Eh
3Fh
(1-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy
0 0000b
states
Clocks) not support
(1-2-2) Fast Read Number of
Mode Bits
000b: Mode Bits not support
23:21
000b
(1-2-2) Fast Read Opcode
(2-2-2) Fast Read
Unused
31:24
00
FFh
0b
0=not support 1=support
0=not support 1=support
03:01
04
111b
0b
40h
EEh
(4-4-4) Fast Read
Unused
07:05
111b
FFh
FFh
Unused
43h:41h 31:08
45h:44h 15:00
FFh
FFh
Unused
(2-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy
20:16
46h
0 000b
000b
states
Clocks) not support
00h
(2-2-2) Fast Read Number of
Mode Bits
000b: Mode Bits not support
23:21
(2-2-2) Fast Read Opcode
Unused
47h
31:24
FFh
FFh
FFh
FFh
49h:48h 15:00
(4-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
20:16
4Ah
0 0000b
states
Clocks) not support
00h
(4-4-4) Fast Read Number of
Mode Bits
000b: Mode Bits not support
23:21
000b
FFh
0Ch
20h
10h
D8h
00h
FFh
00h
FFh
(4-4-4) Fast Read Opcode
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
53h
31:24
07:00
15:08
23:16
31:24
07:00
15:08
23:16
31:24
FFh
0Ch
20h
10h
D8h
00h
FFh
00h
FFh
Sector/block size = 2^N bytes (Note5)
0x00b: this sector type doesn't exist
Sector Type 1 Size
Sector Type 1 erase Opcode
Sector Type 2 Size
Sector/block size = 2^N bytes
0x00b: this sector type doesn't exist
Sector Type 2 erase Opcode
Sector Type 3 Size
Sector/block size = 2^N bytes
0x00b: this sector type doesn't exist
Sector Type 3 erase Opcode
Sector Type 4 Size
Sector/block size = 2^N bytes
0x00b: this sector type doesn't exist
Sector Type 4 erase Opcode
P/N: PM1578
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MX25L2006E
Table c. Parameter Table (1): Macronix Flash Parameter Tables
Add (h) DW Add Data (h/b)
Data
(h)
Description
Comment
2000h=2.000V
2700h=2.700V
3600h=3.600V
(Byte)
(Bit)
(Note1)
07:00
15:08
00h
36h
00h
36h
Vcc Supply Maximum Voltage
61h:60h
1650h=1.650V
2250h=2.250V
2350h=2.350V
2700h=2.700V
23:16
31:24
00h
27h
00h
27h
Vcc Supply Minimum Voltage
63h:62h
H/W Reset# pin
0=not support 1=support
00
0b
H/W Hold# pin
0=not support 1=support
0=not support 1=support
0=not support 1=support
01
02
03
1b
1b
0b
Deep Power Down Mode
S/W Reset
Reset Enable (66h) should be issued
before Reset Opcode
1111 1111b
(FFh)
65h:64h
4FF6h
S/W Reset Opcode
11:04
Program Suspend/Resume
Erase Suspend/Resume
Unused
0=not support 1=support
0=not support 1=support
12
13
0b
0b
14
1b
Wrap-Around Read mode
Wrap-Around Read mode Opcode
0=not support 1=support
15
0b
66h
67h
23:16
FFh
FFh
FFh
08h:support 8B wrap-around read
16h:8B&16B
32h:8B&16B&32B
Wrap-Around Read data length
31:24
FFh
64h:8B&16B&32B&64B
Individual block lock
0=not support 1=support
00
01
0b
1b
Individual block lock bit
(Volatile/Nonvolatile)
0=Volatile 1=Nonvolatile
Individual block lock Opcode
09:02 1111 1111b
Individual block lock Volatile
protect bit default protect status
0=protect 1=unprotect
10
1b
C7FEh
6Bh:68h
Secured OTP
Read Lock
Permanent Lock
Unused
0=not support 1=support
0=not support 1=support
0=not support 1=support
11
12
0b
0b
13
0b
15:14
31:16
11b
Unused
0xFFh
0xFFh
0xFFh
0xFFh
Unused
6Fh:6Ch 31:00
P/N: PM1578
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MX25L2006E
Note 1: h/b is hexadecimal or binary.
Note 2: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x),
address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1), (2-2-2),
and (4-4-4)
Note 3: Wait States is required dummy clock cycles after the address bits or optional mode bits.
Note 4: Mode Bits is optional control bits that follow the address bits. These bits are driven by the system controller
if they are specified. (eg,read performance enhance toggling bits)
Note 5: 4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h
Note 6: All unused and undefined area data is blank FFh.
P/N: PM1578
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MX25L2006E
POWER-ON STATE
The device is at below states when power-up:
- Standby mode ( please note it is not deep power-down mode)
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage unless the VCC achieves below correct
level:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change
during power up state.
For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not
guaranteed. The write, read, erase, and program command should be sent after the below time delay:
- tVSL after VCC reached VCC minimum level
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.
Please refer to the figure of "power-up timing".
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended.
(generally around 0.1uF)
P/N: PM1578
REV.1.5, NOV. 14, 2013
25
MX25L2006E
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
RATING
VALUE
Industrial (I) grade
-40°C to 85°C
-55°C to 125°C
-0.5V to 4.6V
-0.5V to 4.6V
-0.5V to 4.6V
Ambient Operating Temperature
Storage Temperature
Applied Input Voltage
Applied Output Voltage
VCC to Ground Potential
Notes:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is stress rating only and functional operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended period may affect reliability.
2. Specifications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot to 4.6V or -0.5V for period up to 20ns.
4. All input and output pins may overshoot to VCC+0.5V while VCC+0.5V is smaller than or equal to 4.6V.
Figure 4. Maximum Positive Overshoot Waveform
Figure 3.Maximum Negative Overshoot Waveform
20ns
4.6V
0V
3.6V
-0.5V
20ns
CAPACITANCE TA = 25°C, f = 1.0 MHz
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Min.
Typ.
Max.
6
8
Unit
pF
pF
Conditions
VIN = 0V
VOUT = 0V
P/N: PM1578
REV.1.5, NOV. 14, 2013
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MX25L2006E
Figure 5. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL
Input timing reference level
0.8VCC
Output timing reference level
0.7VCC
AC
Measurement
Level
0.5VCC
0.3VCC
0.2VCC
Note: Input pulse rise and fall time are <5ns
Figure 6. OUTPUT LOADING
DEVICE UNDER
TEST
2.7K ohm
+3.3V
CL
6.2K ohm
DIODES=IN3064
OR EQUIVALENT
CL=30pF Including jig capacitance
P/N: PM1578
REV.1.5, NOV. 14, 2013
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MX25L2006E
Table 6. DC CHARACTERISTICS (Temperature = -40°C to 85°C, VCC = 2.7V ~ 3.6V)
Symbol
ILI
Parameter
Input Load Current
Notes
Min.
Typ.
Max.
± 2
± 2
25
Units
uA
Test Conditions
VCC = VCC Max
VIN = VCC or GND
VCC = VCC Max
VOUT = VCC or GND
VIN = VCC or GND
CS# = VCC
1
1
1
ILO
Output Leakage Current
uA
ISB1 VCC Standby Current
15
2
uA
VIN = VCC or GND
CS# = VCC
ISB2 Deep Power-down Current
10
uA
f=86MHz
12
12
4
mA SCLK=0.1VCC/0.9VCC,
SO=Open
f=66MHz
mA SCLK=0.1VCC/0.9VCC,
SO=Open
f=33MHz
mA SCLK=0.1VCC/0.9VCC,
SO=Open
ICC1 VCC Read
1
1
Program in Progress
CS# = VCC
ICC2 VCC Program Current (PP)
15
3
20
15
15
20
mA
VCC Write Status Register
ICC3
Program status register in
progress, CS#=VCC
mA
(WRSR) Current
VCC Sector Erase Current
Erase in Progress,
CS#=VCC
ICC4
(SE)
1
1
9
mA
VCC Chip Erase Current
Erase in Progress,
CS#=VCC
ICC5
(CE)
15
mA
VIL
VIH
Input Low Voltage
Input High Voltage
-0.5
0.7VCC
0.3VCC
VCC+0.4
0.4
V
V
V
V
VOL Output Low Voltage
VOH Output High Voltage
IOL = 1.6mA
IOH = -100uA
VCC-0.2
Low VCC Write Inhibit
Voltage
VWI
3
2.1
2.3
2.5
V
Notes:
1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds).
2. Typical value is calculated by simulation.
3. Not 100% tested.
P/N: PM1578
REV.1.5, NOV. 14, 2013
28
MX25L2006E
Table 7. AC CHARACTERISTICS (Temperature = -40°C to 85°C, VCC = 2.7V ~ 3.6V)
Symbol
Alt.
Parameter
Min.
Typ.
Max.
Unit
Clock Frequency for the following instructions:
fSCLK
fC FAST_READ, RDSFDP, PP, SE, BE, CE, DP, RES,
RDP, WREN, WRDI, RDID, RDSR, WRSR
DC
86
MHz
fRSCLK
fTSCLK
fR Clock Frequency for READ instructions
fT Clock Frequency for DREAD instructions
DC
DC
13
5.5
13
5.5
0.1
0.1
7
33
80
MHz
MHz
ns
ns
ns
@33MHz
@86MHz
tCH(1)
tCL(1)
tCLH Clock High Time
@33MHz
@86MHz
tCLL Clock Low Time
ns
tCLCH(2)
tCHCL(2)
tSLCH
Clock Rise Time (3) (peak to peak)
Clock Fall Time (3) (peak to peak)
tCSS CS# Active Setup Time (relative to SCLK)
CS# Not Active Hold Time (relative to SCLK)
V/ns
V/ns
ns
tCHSL
7
ns
tDVCH tDSU Data In Setup Time
2
ns
tCHDX
tCHSH
tSHCH
tDH Data In Hold Time
CS# Active Hold Time (relative to SCLK)
5
7
7
ns
ns
ns
CS# Not Active Setup Time (relative to SCLK)
Read
Write
15
40
ns
ns
tSHSL
tCSH CS# Deselect Time
tSHQZ(2) tDIS Output Disable Time
6
8
6
ns
ns
ns
30pF
15pF
tCLQV
tV Clock Low to Output Valid
tCLQX
tHLCH
tCHHH
tHHCH
tCHHL
tHO Output Hold Time
0
5
5
5
5
ns
ns
ns
ns
HOLD# Setup Time (relative to SCLK)
HOLD# Hold Time (relative to SCLK)
HOLD Setup Time (relative to SCLK)
HOLD Hold Time (relative to SCLK)
ns
tHHQX(2) tLZ HOLD to Output Low-Z
tHLQZ(2) tHZ HOLD# to Output High-Z
6
6
ns
ns
tWHSL(4)
tSHWL(4)
tDP(2)
Write Protect Setup Time
Write Protect Hold Time
CS# High to Deep Power-down Mode
20
100
ns
ns
us
10
CS# High to Standby Mode without Electronic
Signature Read
CS# High to Standby Mode with Electronic Signature
Read
tRES1(2)
tRES2(2)
8.8
us
us
8.8
tW
Write Status Register Cycle Time
Byte-Program
Page Program Cycle Time
Sector Erase Cycle Time
Block Erase Cycle Time
5
9
0.6
40
0.4
1.7
40
50
3
200
2
ms
us
ms
ms
s
tBP
tPP
tSE
tBE
tCE
Chip Erase Cycle Time
3.8
s
Note:
1. tCH + tCL must be greater than or equal to 1/f (fC or fR).
2. Value guaranteed by characterization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
5. Test condition is shown as Figure 5 & 6.
6. The CS# rising time needs to follow tCLCH spec and CS# falling time needs to follow tCHCL spec.
P/N: PM1578
REV.1.5, NOV. 14, 2013
29
MX25L2006E
Table 8. Power-Up Timing
Symbol
Parameter
VCC(min) to CS# low
Min.
200
Max.
Unit
us
tVSL(1)
Note: 1. The parameter is characterized only.
INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh).
P/N: PM1578
REV.1.5, NOV. 14, 2013
30
MX25L2006E
Timing Analysis
Figure 7. Serial Input Timing
tSHSL
tSHCH
tCHCL
CS#
tCHSL
tSLCH
tCHSH
SCLK
tDVCH
tCHDX
tCLCH
MSB
LSB
SI
High-Z
SO
Figure 8. Output Timing
CS#
tCH
SCLK
tCLQV
tCLQV
tCL
tSHQZ
tCLQX
LSB
SO
ADDR.LSB IN
SI
P/N: PM1578
REV.1.5, NOV. 14, 2013
31
MX25L2006E
Figure 9. Hold Timing
CS#
tHLCH
tHHCH
tCHHL
SCLK
tCHHH
tHLQZ
tHHQX
SO
tCLHS
tCLHH
HOLD#
* SI is "don't care" during HOLD operation.
Figure 10. WP# Disable Setup and Hold Timing during WRSR when SRWD=1
WP#
tSHWL
tWHSL
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12
13 14
15
SCLK
01
SI
High-Z
SO
P/N: PM1578
REV.1.5, NOV. 14, 2013
32
MX25L2006E
Figure 11. Write Enable (WREN) Sequence (Command 06)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
06
SI
High-Z
SO
Figure 12. Write Disable (WRDI) Sequence (Command 04)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
04
SI
High-Z
SO
Figure 13. Read Status Register (RDSR) Sequence (Command 05)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI
command
05
Status Register Out
Status Register Out
High-Z
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
P/N: PM1578
REV.1.5, NOV. 14, 2013
33
MX25L2006E
Figure 14. Write Status Register (WRSR) Sequence (Command 01)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
command
01
Status
Register In
SI
7
6
5
4
3
2
0
1
MSB
High-Z
SO
Figure 15. Read Data Bytes (READ) Sequence (Command 03)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
command
03
24-Bit Address
23 22 21
MSB
3
2
1
0
SI
Data Out 1
Data Out 2
High-Z
2
7
6
5
4
3
1
7
0
SO
MSB
P/N: PM1578
REV.1.5, NOV. 14, 2013
34
MX25L2006E
Figure 16. Read at Higher Speed (FAST_READ) Sequence (Command 0B)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
SCLK
Command
0B
24 BIT ADDRESS
SI
23 22 21
3
2
1
0
High-Z
SO
CS#
47
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
SCLK
Dummy Byte
7
6
5
4
3
2
0
1
SI
DATA OUT 2
DATA OUT 1
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
SO
MSB
MSB
MSB
Figure 17. Dual Output Read Mode Sequence (Command 3B)
CS#
0
1
2
3
4
5
6
7
8
9
10 11
30 31 32
39 40 41 42 43
SCLK
8 dummy
cycle
8 Bit Instruction
24 BIT Address
Data Output
data
address
bit23, bit22, bit21...bit0
3B(hex)
dummy
SI/SO0
bit6, bit4, bit2...bit0, bit6, bit4....
High Impedance
data
SO/SO1
bit7, bit5, bit3...bit1, bit7, bit5....
P/N: PM1578
REV.1.5, NOV. 14, 2013
35
MX25L2006E
Figure 18. Sector Erase (SE) Sequence (Command 20)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
20
24 Bit Address
SI
23 22
MSB
2
1
0
Note: SE command is 20(hex).
Figure 19. Block Erase (BE) Sequence (Command 52 or D8)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
52 or D8
24 Bit Address
SI
23 22
MSB
2
0
1
Note: BE command is 52 or D8(hex).
Figure 20. Chip Erase (CE) Sequence (Command 60 or C7)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
60 or C7
SI
Note: CE command is 60(hex) or C7(hex).
P/N: PM1578
REV.1.5, NOV. 14, 2013
36
MX25L2006E
Figure 21. Page Program (PP) Sequence (Command 02)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
02
24-Bit Address
Data Byte 1
23 22 21
MSB
3
2
1
0
7
6
5
4
3
2
0
1
SI
MSB
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
Data Byte 2
Data Byte 3
Data Byte 256
7
6
5
4
3
2
0
7
6
5
4
3
2
0
7
6
5
4
3
2
0
1
1
1
SI
MSB
MSB
MSB
Figure 22. Deep Power-down (DP) Sequence (Command B9)
CS#
t
DP
0
1
2
3
4
5
6
7
SCLK
SI
Command
B9
Stand-by Mode
Deep Power-down Mode
P/N: PM1578
REV.1.5, NOV. 14, 2013
37
MX25L2006E
Figure 23. Read Electronic Signature (RES) Sequence (Command AB)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38
SCLK
Command
AB
t
3 Dummy Bytes
RES2
SI
23 22 21
MSB
3
2
1
0
Electronic Signature Out
High-Z
7
6
5
4
3
2
0
1
SO
MSB
Deep Power-down Mode
Stand-by Mode
Figure 24. Release from Deep Power-down (RDP) Sequence (Command AB)
CS#
t
RES1
0
1
2
3
4
5
6
7
SCLK
SI
Command
AB
High-Z
SO
Deep Power-down Mode
Stand-by Mode
P/N: PM1578
REV.1.5, NOV. 14, 2013
38
MX25L2006E
Figure 25. Read Identification (RDID) Sequence (Command 9F)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
28 29 30 31
SCLK
SI
Command
9F
Manufacturer Identification
Device Identification
High-Z
SO
7
6
5
3
2
1
0
15 14 13
MSB
3
2
1
0
MSB
Figure 26. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90)
CS#
0
1
2
3
4
5
6
7
8
9 10
SCLK
Command
90
2 Dummy Bytes
SI
15 14 13
3
2
1
0
High-Z
SO
CS#
47
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
SCLK
ADD (1)
7
6
5
4
3
2
0
1
SI
Manufacturer ID
Device ID
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
X
SO
MSB
MSB
MSB
Notes:
(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first.
P/N: PM1578
REV.1.5, NOV. 14, 2013
39
MX25L2006E
Figure 27. Power-up Timing
V
CC
V
(max)
CC
Chip Selection is Not Allowed
V
(min)
CC
Device is fully accessible
tVSL
time
P/N: PM1578
REV.1.5, NOV. 14, 2013
40
MX25L2006E
OPERATING CONDITIONS
At Device Power-Up and Power-Down
AC timing illustrated in Figure 28 and Figure 29 are the supply voltages and the control signals at device power-up
and power-down. If the timing in the figures is ignored, the device will not operate correctly.
During power-up and power down, CS# need to follow the voltage applied on VCC to keep the device not be se-
lected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.
Figure 28. AC Timing at Device Power-Up
VCC(min)
VCC
GND
tVR
tSHSL
CS#
tSHCH
tSLCH
tCHSL
tCHSH
SCLK
tDVCH
tCHCL
tCHDX
tCLCH
MSB IN
LSB IN
SI
High Impedance
SO
Symbol
tVR
Parameter
VCC Rise Time
Notes
Min.
0.5
Max.
500000
Unit
us/V
1
Notes :
1. Sampled, not 100% tested.
2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to
"AC CHARACTERISTICS" table.
P/N: PM1578
REV.1.5, NOV. 14, 2013
41
MX25L2006E
Figure 29. Power-Down Sequence
During power down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.
VCC
CS#
SCLK
P/N: PM1578
REV.1.5, NOV. 14, 2013
42
MX25L2006E
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Min.
Typ. (1)
Max. (2)
Unit
ms
ms
s
Write Status Register Cycle Time
Sector erase Time
5
40
200
2
40
0.4
1.7
Block erase Time
Chip Erase Time
3.8
50
3
s
Byte Program Time (via page program command)
Page Program Time
9
us
0.6
ms
cycles
Erase/Program Cycle
100,000
Note:
1. Typical program and erase time assumes the following conditions: 25°C, 3.3V, and checker board pattern.
2. Under worst conditions of 85°C and 2.7V.
3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming com-
mand.
DATA RETENTION
Parameter
Condition
Min.
Max.
Unit
Data retention
55˚C
20
years
LATCH-UP CHARACTERISTICS
Min.
-1.0V
Max.
Input Voltage with respect to GND on all power pins, SI, CS#
Input Voltage with respect to GND on SO
Current
2 VCCmax
VCC + 1.0V
+100mA
-1.0V
-100mA
Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.
P/N: PM1578
REV.1.5, NOV. 14, 2013
43
MX25L2006E
ORDERING INFORMATION
PART NO.
CLOCK (MHz)
Temperature
-40~85°C
PACKAGE
Remark
MX25L2006EM1I-12G
MX25L2006EZNI-12G
MX25L2006EZUI-12G
86
86
86
8-SOP (150mil)
8-land WSON
(6x5mm)
-40~85°C
8-USON
(2x3x0.6mm)
-40~85°C
P/N: PM1578
REV.1.5, NOV. 14, 2013
44
MX25L2006E
PART NAME DESCRIPTION
MX 25 L 2006E M1
I
12 G
OPTION:
G: RoHS Compliant and Halogen-free
SPEED:
12: 86MHz
TEMPERATURE RANGE:
I: Industrial (-40°C to 85°C)
PACKAGE:
ZN: WSON (0.8mm package height)
M1: 150mil 8-SOP
ZU: 8-USON (2x3x0.6mm)
DENSITY & MODE:
2006E: 2Mb
TYPE:
L: 3V
DEVICE:
25: Serial Flash
P/N: PM1578
REV.1.5, NOV. 14, 2013
45
MX25L2006E
PACKAGE INFORMATION
P/N: PM1578
REV.1.5, NOV. 14, 2013
46
MX25L2006E
P/N: PM1578
REV.1.5, NOV. 14, 2013
47
MX25L2006E
P/N: PM1578
REV.1.5, NOV. 14, 2013
48
MX25L2006E
REVISION HISTORY
Revision No. Description
Page
Date
0.01
1. Modified "Initial Delivery State" description
P27
MAY/19/2010
2. Modified OTP Capable data from 1 to 0
3. Revised Vcc Supply Minimum Voltage Address Bits
4. Changed wording from DMC to SFDP
5. Changed title from "Advanced Information" to "Preliminary"
6. Revised SFDP sequence description
1. Removed Preliminary
2. Removed SFDP sequence description & content table
3. Removed Write Status Register Cycle Time in notes
1. Added CS# rising and falling time description
2. Modified tW from 10(typ.)/100(max.) to 5(typ.)/40(max.)
3. Added tSE(max.): 300ms
P21
P21
P4,8,11,19
P4
P19
P4 JUL/02/2010
P4,8,11,19
P23,37
P8,23
P23,37
P23,37
P18
1.0
1.1
OCT/20/2010
4. Corrected RDID description
5. Removed note 2
P13
1.2
1. Modified tVSL from 10us(min.) to 200us(min.)
2. Modified description for RoHS compliance
3. Added 8-USON package
P24
MAR/21/2011
P4,38,39
P4,5,38,39,42
P4,8,11,
P19~24,29
P23
1.3
1. Added Read SFDP (RDSFDP) Mode
FEB/10/2012
1.4
1.5
1. Modified Secured OTP data from 1 to 0
1. Updated parameters for DC/AC Characteristics
2. Updated Erase and Programming Performance
AUG/13/2013
NOV/14/2013
P4,28,29
P4,43
P/N: PM1578
REV.1.5, NOV. 14, 2013
49
MX25L2006E
Except for customized products which has been expressly identified in the applicable agreement, Macronix's
products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or
household applications only, and not for use in any applications which may, directly or indirectly, cause death,
personal injury, or severe property damages. In the event Macronix products are used in contradicted to their
target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its
actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or
distributors shall be released from any and all liability arisen therefrom.
Copyright© Macronix International Co., Ltd. 2011~2013. All rights reserved, including the trademarks and
tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit,
NBiit, Macronix NBit, eLiteFlash, HybridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC,
Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich Audio, Rich Book, Rich TV, and FitCAM. The names
and brands of third party referred thereto (if any) are for identification purposes only.
For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
50
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