MX25L6433FMI-08Q [Macronix]
Flash,;
| 型号： | MX25L6433FMI-08Q |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | Flash, 时钟 光电二极管 内存集成电路 |
| 文件： | 总83页 (文件大小：1646K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MX25L6433F
MX25L6433F
3V, 64M-BIT [x 1/x 2/x 4]
CMOS MXSMIO® (SERIAL MULTI I/O)
FLASH MEMORY
Key Features
• Hold Feature
• Multi I/O Support - Single I/O, Dual I/O and Quad I/O
• Auto Erase and Auto Program Algorithms
• Program Suspend/Resume & Erase Suspend/Resume
P/N: PM2130
Rev. 1.6, October 21, 2016
1
MX25L6433F
Contents
1. FEATURES ........................................................................................................................................................ 5
2. GENERAL DESCRIPTION ............................................................................................................................... 6
3. PIN CONFIGURATION ...................................................................................................................................... 7
4. PIN DESCRIPTION............................................................................................................................................ 7
5. BLOCK DIAGRAM............................................................................................................................................. 8
6. DATA PROTECTION.......................................................................................................................................... 9
Table 1. Protected Area Sizes..............................................................................................................10
Table 2. 8K-bit Secured OTP Definition ...............................................................................................11
7. MEMORY ORGANIZATION............................................................................................................................. 12
Table 3. Memory Organization .............................................................................................................12
8. DEVICE OPERATION...................................................................................................................................... 13
9. HOLD FEATURE.............................................................................................................................................. 14
10. COMMAND DESCRIPTION........................................................................................................................... 15
Table 4. Command Sets.......................................................................................................................15
10-1. Write Enable (WREN)..........................................................................................................................18
10-2. Write Disable (WRDI)...........................................................................................................................19
10-3. Read Identification (RDID)...................................................................................................................20
10-4. Read Status Register (RDSR).............................................................................................................21
10-5. Read Configuration Register (RDCR)..................................................................................................22
Table 5. Status Register.......................................................................................................................23
Table 6. Configuration Register............................................................................................................24
Table 7. Dummy Cycle and Frequency Table.......................................................................................24
10-6. Write Status Register (WRSR).............................................................................................................25
Table 8. Protection Modes....................................................................................................................26
10-7. Read Data Bytes (READ) ....................................................................................................................28
10-8. Read Data Bytes at Higher Speed (FAST_READ) ..............................................................................29
10-9. Dual Read Mode (DREAD)..................................................................................................................30
10-10. 2 x I/O Read Mode (2READ) ...............................................................................................................31
10-11. Quad Read Mode (QREAD) ................................................................................................................32
10-12. 4 x I/O Read Mode (4READ) ...............................................................................................................33
10-13. Performance Enhance Mode...............................................................................................................35
10-14. Burst Read...........................................................................................................................................36
10-15. Sector Erase (SE)................................................................................................................................37
10-16. Block Erase (BE) .................................................................................................................................38
10-17. Block Erase (BE32K)...........................................................................................................................39
10-18. Chip Erase (CE)...................................................................................................................................40
10-19. Page Program (PP) .............................................................................................................................41
10-20. 4 x I/O Page Program (4PP)................................................................................................................42
10-21. Deep Power-down (DP).......................................................................................................................45
10-22. Release from Deep Power-down (RDP), Read Electronic Signature (RES) .......................................46
10-23. Read Electronic Manufacturer ID & Device ID (REMS).......................................................................48
Table 9. ID Definitions .........................................................................................................................49
10-24. Enter Secured OTP (ENSO)................................................................................................................49
P/N: PM2130
Rev. 1.6, October 21, 2016
2
MX25L6433F
10-25. Exit Secured OTP (EXSO)...................................................................................................................49
10-26. Read Security Register (RDSCUR).....................................................................................................50
Table 10. Security Register Definition ..................................................................................................51
10-27. Write Security Register (WRSCUR).....................................................................................................52
10-28. Program Suspend and Erase Suspend ...............................................................................................53
Table 11. Readable Area of Memory While a Program or Erase Operation is Suspended..................53
Table 12. Acceptable Commands During Program/Erase Suspend after tPSL/tESL...........................53
Table 13. Acceptable Commands During Suspend (tPSL/tESL not required)......................................54
10-29. Program Resume and Erase Resume.................................................................................................55
10-30. No Operation (NOP) ............................................................................................................................56
10-31. Software Reset (Reset-Enable (RSTEN) and Reset (RST)) ...............................................................56
10-32. Read SFDP Mode (RDSFDP)..............................................................................................................57
Table 14. Signature and Parameter Identification Data Values ...........................................................58
Table 15. Parameter Table (0): JEDEC Flash Parameter Tables.........................................................59
Table 16. Parameter Table (1): Macronix Flash Parameter Tables ......................................................61
11. POWER-ON STATE ....................................................................................................................................... 63
12. Electrical Specifications.............................................................................................................................. 64
12-1. Absolute Maximum Ratings.................................................................................................................64
12-2. Capacitance TA = 25°C, f = 1.0 MHz ...................................................................................................64
Table 17. DC Characteristics................................................................................................................66
Table 18. AC Characteristics................................................................................................................67
13. TIMING ANALYSIS ........................................................................................................................................ 69
14. OPERATING CONDITIONS........................................................................................................................... 71
Table 19. Power-Up/Down Voltage and Timing....................................................................................73
14-1. Initial Delivery State.............................................................................................................................73
15. ERASE AND PROGRAMMING PERFORMANCE........................................................................................ 74
16. DATA RETENTION ........................................................................................................................................ 74
17. LATCH-UP CHARACTERISTICS.................................................................................................................. 74
18. ORDERING INFORMATION.......................................................................................................................... 75
19. PART NAME DESCRIPTION......................................................................................................................... 76
20. PACKAGE INFORMATION............................................................................................................................ 77
20-1. 8-pin SOP (200mil) ..............................................................................................................................77
20-2. 16-pin SOP (300mil) ............................................................................................................................78
20-3. 8-WSON (8x6mm) ...............................................................................................................................79
20-4. 8-WSON (6x5mm) ...............................................................................................................................80
20-5. 24 ball TFBGA (6x8mm) ......................................................................................................................81
21. REVISION HISTORY ..................................................................................................................................... 82
P/N: PM2130
Rev. 1.6, October 21, 2016
3
MX25L6433F
Figures
Figure 1. Serial Modes Supported (for Normal Serial mode)..............................................................13
Figure 2. Hold Condition Operation ....................................................................................................14
Figure 3. Write Enable (WREN) Sequence (Command 06)................................................................18
Figure 4. Write Disable (WRDI) Sequence (Command 04) ...............................................................19
Figure 5. Read Identification (RDID) Sequence (Command 9F)........................................................20
Figure 6. Read Status Register (RDSR) Sequence (Command 05)..................................................21
Figure 7. Read Configuration Register (RDCR) Sequence.................................................................22
Figure 8. Write Status Register (WRSR) Sequence (Command 01) .................................................25
Figure 9. WRSR flow...........................................................................................................................27
Figure 10. Read Data Bytes (READ) Sequence (Command 03) .......................................................28
Figure 11. Read at Higher Speed (FAST_READ) Sequence (Command 0B)....................................29
Figure 12. Dual Read Mode Sequence (Command 3B) .....................................................................30
Figure 13. 2 x I/O Read Mode Sequence (Command BB)..................................................................31
Figure 14. Quad Read Mode Sequence (Command 6B)....................................................................32
Figure 15. 4 x I/O Read Mode Sequence (Command EB)..................................................................33
Figure 16. 4 x I/O Read enhance performance Mode Sequence (Command EB) (SPI Mode)...........35
Figure 17. Burst Read.........................................................................................................................36
Figure 18. Sector Erase (SE) Sequence (Command 20)...................................................................37
Figure 19. Block Erase (BE) Sequence (Command D8)....................................................................38
Figure 20. Block Erase 32KB (BE32K) Sequence (Command 52) ...................................................39
Figure 21. Chip Erase (CE) Sequence (Command 60 or C7)............................................................40
Figure 22. Page Program (PP) Sequence (Command 02) ................................................................41
Figure 23. 4 x I/O Page Program (4PP) Sequence (Command 38)...................................................42
Figure 24. Program/Erase Flow(1) with read array data.....................................................................43
Figure 25. Program/Erase Flow(2) without read array data................................................................44
Figure 26. Deep Power-down (DP) Sequence (Command B9) .........................................................45
Figure 27. Read Electronic Signature (RES) Sequence (Command AB)...........................................46
Figure 28. Release from Deep Power-down (RDP) Sequence...........................................................47
Figure 29. Read Electronic Manufacturer & Device ID (REMS) Sequence ........................................48
Figure 30. Read Security Register (RDSCUR) Sequence (Command 2B).........................................50
Figure 31. Write Security Register (WRSCUR) Sequence (Command 2F) (SPI mode).....................52
Figure 32. Suspend to Read Latency..................................................................................................54
Figure 33. Resume to Suspend Latency.............................................................................................54
Figure 34. Suspend to Program Latency ............................................................................................55
Figure 35. Resume to Read Latency ..................................................................................................55
Figure 36. Software Reset Recovery ..................................................................................................56
Figure 37. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence ...................................57
Figure 38. Maximum Negative Overshoot Waveform .........................................................................64
Figure 39. Maximum Positive Overshoot Waveform...........................................................................64
Figure 40. Input Test Waveforms and Measurement Level.................................................................65
Figure 41. Output Loading ..................................................................................................................65
Figure 42. Serial Input Timing .............................................................................................................69
Figure 43. Output Timing.....................................................................................................................69
Figure 44. Hold Timing........................................................................................................................70
Figure 45. WP# Setup Timing and Hold Timing during WRSR when SRWD=1..................................70
Figure 46. AC Timing at Device Power-Up..........................................................................................71
Figure 47. Power-Down Sequence .....................................................................................................72
Figure 48. Power-up Timing................................................................................................................72
Figure 49. Power Up/Down and Voltage Drop ....................................................................................73
P/N: PM2130
Rev. 1.6, October 21, 2016
4
MX25L6433F
64M-BIT [x 1 / x 2 / x 4] CMOS MXSMIO® (SERIAL MULTI I/O)
FLASH MEMORY
1. FEATURES
• Additional 8K-bit bit security OTP
GENERAL
- Features unique identifier
• Supports Serial Peripheral Interface -- Mode 0 and
Mode 3
• 67,108,864 x 1 bit structure
- Factory locked identifiable, and customer lockable
• Auto Erase and Auto Program Algorithms
- Automatically erases and verifies data at selected
sector
or 33,554,432 x 2 bits (two I/O read mode) structure
or 16,777,216 x 4 bits (four I/O mode) structure
• 2048 Equal Sectors with 4K bytes each
- Any Sector can be erased individually
• 256 Equal Blocks with 32K bytes each
- Any Block can be erased individually
• 128 Equal Blocks with 64K bytes each
- Any Block can be erased individually
• Power Supply Operation
- Automatically programs and verifies data at select-
ed page by an internal algorithm that automatically
times the program pulse width (Any page to be
programmed should have page in the erased state
first.)
• Status Register Feature
• Command Reset
• Program/Erase Suspend
- 2.65~3.6 volt for read, erase, and program opera-
tions
• Latch-up protected to 100mA from -1V to Vcc +1V
• Program/Erase Resume
• Electronic Identification
JEDEC 1-byte Manufacturer ID and 2-byte Device
ID
-
PERFORMANCE
• High Performance
- RES command for 1-byte Device ID
• Support Serial Flash Discoverable Parameters (SFDP)
mode
VCC = 2.65~3.6V
- Normal read
- 50MHz
- Fast read
HARDWARE FEATURES
• SCLK Input
- FAST_READ, DREAD, QREAD:
133MHz with 8 dummy cycles
- 2READ: 80MHz with 4 dummy cycles,
133MHz with 8 dummy cycles
- 4READ: 80MHz with 6 dummy cycles,
133MHz with 10 dummy cycles
- Configurable dummy cycle number for 2READ
and 4READ operation
Serial clock input
• SI/SIO0
-
Serial Data Input or Serial Data Input/Output for 2 x
I/O mode or Serial Data Input/Output for 4 x I/O mode
-
• SO/SIO1
Serial Data Output or Serial Data Input/Output for
2 x I/O mode or Serial Data Input/Output for 4 x I/O
-
- 8/16/32/64 byte Wrap-Around Burst Read Mode
• Low Power Consumption
• Typical 100,000 erase/program cycles
• 20 years data retention
mode
• WP#/SIO2
Hardware write protection or Serial Data Input/Out-
put for 4 x I/O mode
-
• HOLD#/SIO3
To pause the device without deselecting the device
or serial data Input/Output for 4 x I/O mode
• PACKAGE
-
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
- 8-pin SOP (200mil)
- 16-pin SOP (300mil)
- 8-WSON (6x5mm)
- 8-WSON (8x6mm)
- 24 ball TFBGA (6x8mm)
- WLCSP
• Advanced Security Features
- Block lock protection
The BP0-BP3 and T/B status bits define the size
of the area to be protected against program and
erase instructions
All devices are RoHS Compliant and Halogen-
free
-
P/N: PM2130
Rev. 1.6, October 21, 2016
5
MX25L6433F
2. GENERAL DESCRIPTION
MX25L6433F is 64Mb bits Serial NOR Flash memory, which is configured as 8,388,608 x 8 internally. When it is
in four I/O mode, the structure becomes 16,777,216 bits x 4. When it is in two I/O mode, the structure becomes
33,554,432 bits x 2. MX25L6433F feature a serial peripheral interface and software protocol allowing operation
on a simple 3-wire bus while it is in single I/O mode. The three bus signals are a clock input (SCLK), a serial data
input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input.
MX25L6433F, MXSMIO® (Serial Multi I/O) flash memory, provides sequential read operation on the whole chip
and multi-I/O features.
When it is in quad I/O mode, the SI pin, SO pin, WP# pin and HOLD# pin become SIO0 pin, SIO1 pin, SIO2 pin
and SIO3 pin for address/dummy bits input and data Input/Output.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the
specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis. Erase command is executed on 4K-byte sector, 32K-byte/64K-byte block, or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status
read command can be issued to detect completion status of a program or erase operation via WIP bit.
When the device is not in operation and CS# is high, it is put in standby mode.
The MX25L6433F utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after
100,000 program and erase cycles.
P/N: PM2130
Rev. 1.6, October 21, 2016
6
MX25L6433F
3. PIN CONFIGURATION
8-PIN SOP (200mil)
16-PIN SOP (300mil)
1
SCLK
SI/SIO0
NC
HOLD#/SIO3
VCC
16
15
14
13
12
11
10
9
1
2
3
4
CS#
SO/SIO1
WP#/SIO2
GND
VCC
8
7
6
5
2
3
4
5
6
7
8
HOLD#/SIO3
SCLK
NC
NC
NC
SI/SIO0
NC
NC
NC
NC
GND
WP#/SIO2
CS#
SO/SIO1
8-WSON (6x5mm, 8x6mm)
1
2
3
4
VCC
CS#
SO/SIO1
WP#/SIO2
GND
8
7
6
5
HOLD#/SIO3
SCLK
4. PIN DESCRIPTION
SYMBOL
SI/SIO0
DESCRIPTION
CS#
Chip Select
Serial Data Input (for 1xI/O)/ Serial Data
SI/SIO0 Input & Output (for 2xI/O mode and 4xI/
O mode)
24-Ball TFBGA (6x8 mm)
Serial Data Output (for 1xI/O)/Serial
SO/SIO1 Data Input & Output (for 2xI/O mode
and 4xI/O mode)
4
NC
NC
VCC
GND
WP#/SIO2 HOLD#/SIO3 NC
NC
NC
SCLK
Clock Input
Write protection Active Low or Serial
Data Input & Output (for 4xI/O mode)
3
2
1
WP#/SIO2
SI/SIO0
NC
NC
NC
To pause the device without deselecting
the device or Serial data Input/Output
for 4 x I/O mode
HOLD#/
SIO3
NC
SCLK
CS#
SO/SIO1
NC
VCC
GND
NC
+ 3.0V Power Supply
Ground
No Connection
NC
A
NC
B
NC
C
NC
D
NC
E
NC
F
Note:
1. The HOLD# pin has internal pull up.
P/N: PM2130
Rev. 1.6, October 21, 2016
7
MX25L6433F
5. BLOCK DIAGRAM
Address
Generator
Memory Array
Y-Decoder
SI/SIO0
SO/SIO1
SIO2 *
Data
Register
SIO3 *
WP# *
SRAM
Buffer
Sense
Amplifier
HOLD# *
RESET# *
CS#
Mode
Logic
State
Machine
HV
Generator
SCLK
Clock Generator
Output
Buffer
* Depends on part number options.
P/N: PM2130
Rev. 1.6, October 21, 2016
8
MX25L6433F
6. DATA PROTECTION
During power transition, there may be some false system level signals which result in inadvertent erasure or
programming. The device is designed to protect itself from these accidental write cycles.
The state machine will be reset as standby mode automatically during power up. In addition, the control register
architecture of the device constrains that the memory contents can only be changed after specific command
sequences have completed successfully.
In the following, there are several features to protect the system from the accidental write cycles during VCC
power-up and power-down or from system noise.
•
Valid command length checking: The command length will be checked whether it is at byte base and
completed on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other command to change data.
• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from
writing all commands except Release from Deep Power Down mode command (RDP) and Read Electronic
Signature command (RES).
I. Block lock protection
- The Software Protected Mode (SPM) uses (TB, BP3, BP2, BP1, BP0) bits to allow part of memory to be
protected as read only. The protected area definition is shown as table of "Table 1. Protected Area Sizes", the
protected areas are more flexible which may protect various areas by setting value of TB, BP0-BP3 bits.
- The Hardware Protected Mode (HPM) uses WP#/SIO2 to protect the (BP3, BP2, BP1, BP0, TB) bits and
SRWD bit.
P/N: PM2130
Rev. 1.6, October 21, 2016
9
MX25L6433F
Table 1. Protected Area Sizes
Protected Area Sizes (T/B bit = 0)
Status bit
Protect Level
64Mb
BP3
0
BP2
0
BP1
0
BP0
0
0 (none)
0
0
0
1
1 (1block, block 127th)
0
0
1
0
2 (2blocks, block 126th-127th)
3 (4blocks, block 124th-127th)
4 (8blocks, block 120th-127th)
5 (16blocks, block 112th-127th)
6 (32blocks, block 96th-127th)
7 (64blocks, block 64th-127th)
8 (128blocks, protect all)
9 (128blocks, protect all)
10 (128blocks, protect all)
11 (128blocks, protect all)
12 (128blocks, protect all)
13 (128blocks, protect all)
14 (128blocks, protect all)
15 (128blocks, protect all)
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Protected Area Sizes (T/B bit = 1)
Status bit
Protect Level
64Mb
BP3
0
BP2
0
BP1
0
BP0
0
0 (none)
0
0
0
1
1 (1block, block 0th)
0
0
1
0
2 (2blocks, block 0th-1st)
3 (4blocks, block 0th-3rd)
4 (8blocks, block 0th-7th)
5 (16blocks, block 0th-15th)
6 (32blocks, block 0th-31st)
7 (64blocks, block 0th-63rd)
8 (128blocks, protect all)
9 (128blocks, protect all)
10 (128blocks, protect all)
11 (128blocks, protect all)
12 (128blocks, protect all)
13 (128blocks, protect all)
14 (128blocks, protect all)
15 (128blocks, protect all)
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Note: The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP3, BP2, BP1,
BP0) are 0.
P/N: PM2130
Rev. 1.6, October 21, 2016
10
MX25L6433F
II. Additional 8K-bit secured OTP for unique identifier: to provide 8K-bit One-Time Program area for setting
device unique serial number - Which may be set by factory or system maker.
The 8K-bit secured OTP area is composed of two rows of 4K-bit. Customer could lock the first 4K-bit OTP
area and factory could lock the other.
- Security register bit 0 indicates whether the 2nd 4K-bit is locked by factory or not.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register)
command to set customer lock-down bit1 as "1". Please refer to table of "Table 10. Security Register
Definition" for security register bit definition and table of "Table 2. 8K-bit Secured OTP Definition" for
address range definition.
- To program 8K-bit secured OTP by entering secured OTP mode (with ENSO command), and going through
normal program procedure, and then exiting secured OTP mode by writing EXSO command.
Note: Once lock-down whatever by factory or customer, the corresponding secured area cannot be changed
any more. While in 8K-bit Secured OTP mode, array access is not allowed.
Table 2. 8K-bit Secured OTP Definition
Address range
xxx000~xxx1FF
xxx200~xxx3FF
Size
Lock-down
4096-bit
4096-bit
Determined by Customer
Determined by Factory
P/N: PM2130
Rev. 1.6, October 21, 2016
11
MX25L6433F
7. MEMORY ORGANIZATION
Table 3. Memory Organization
Block(64K-byte) Block(32K-byte) Sector (4K-byte)
Address Range
2047
7FF000h
7FFFFFh
255
2040
2039
7F8000h
7F7000h
7F8FFFh
7F7FFFh
127
254
253
252
251
250
2032
2031
7F0000h
7EF000h
7F0FFFh
7EFFFFh
2024
2023
7E8000h
7E7000h
7E8FFFh
7E7FFFh
126
2016
2015
7E0000h
7DF000h
7E0FFFh
7DFFFFh
2008
2007
7D8000h
7D7000h
7D8FFFh
7D7FFFh
125
2000
7D0000h
7D0FFFh
47
02F000h
02FFFFh
5
4
3
2
1
0
40
39
028000h
027000h
028FFFh
027FFFh
2
1
32
31
020000h
01F000h
020FFFh
01FFFFh
24
23
018000h
017000h
018FFFh
017FFFh
16
15
010000h
00F000h
010FFFh
00FFFFh
8
7
008000h
007000h
008FFFh
007FFFh
0
0
000000h
000FFFh
P/N: PM2130
Rev. 1.6, October 21, 2016
12
MX25L6433F
8. DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended
operation.
2. When incorrect command is inputted to this device, it enters standby mode and remains in standby mode
until next CS# falling edge. In standby mode, SO pin of the device is High-Z.
3. When correct command is inputted to this device, it enters active mode and remains in active mode until next
CS# rising edge.
4. For standard single data rate serial mode, input data is latched on the rising edge of Serial Clock(SCLK) and
data is shifted out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as "Figure 1.
Serial Modes Supported (for Normal Serial mode)".
5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, RDSFDP, 4READ, QREAD,
2READ, DREAD, RDCR, RES, and REMS the shifted-in instruction sequence is followed by a data-out
sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN,
WRDI, WRSR, SE, BE, BE32K, CE, PP, 4PP, Suspend, Resume, NOP, RSTEN, RST, ENSO, EXSO, and
WRSCUR, the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and
not executed.
6. While a Write Status Register, Program, or Erase operation is in progress, access to the memory array is
neglected and will not affect the current operation of Write Status Register, Program, Erase.
Figure 1. Serial Modes Supported (for Normal Serial mode)
CPOL CPHA
shift in
shift out
SCLK
SCLK
(Serial mode 0)
(Serial mode 3)
0
1
0
1
SI
MSB
SO
MSB
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while
not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial
mode is supported.
P/N: PM2130
Rev. 1.6, October 21, 2016
13
MX25L6433F
9. HOLD FEATURE
HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop
the operation of write status register, programming, or erasing in progress.
The operation of HOLD requires Chip Select (CS#) keeping low and starts on falling edge of HOLD# pin signal
while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not
start until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while
Serial Clock(SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not end until
Serial Clock being low).
Figure 2. Hold Condition Operation
CS#
SCLK
HOLD#
SI/SIO0
Don’t care
Valid Data
Don’t care
Bit 6
Valid Data
Valid Data
SO/SIO1
(internal)
Bit 7
Bit 5
SO/SIO1
(External)
High_Z
High_Z
Bit 7
Bit 6
Bit 5
Bit 6
Bit 7
CS#
SCLK
HOLD#
SI/SIO0
Don’t care
Valid Data
Don’t care
Valid Data
Valid Data
SO/SIO1
(internal)
Bit 7
Bit 6
Bit 5
Bit 5
Bit 4
Bit 3
Bit 3
SO/SIO1
(External)
High_Z
High_Z
Bit 6
Bit 4
Bit 7
During the HOLD operation, the Serial Data Output (SO) is high impedance when Hold# pin goes low and will
keep high impedance until Hold# pin goes high. The Serial Data Input (SI) is don't care if both Serial Clock (SCLK)
and Hold# pin goes low and will keep the state until SCLK goes low and Hold# pin goes high. If Chip Select (CS#)
drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with
chip, the HOLD# must be at high and CS# must be at low.
Note: The HOLD feature is disabled during Quad I/O mode.
P/N: PM2130
Rev. 1.6, October 21, 2016
14
MX25L6433F
10. COMMAND DESCRIPTION
Table 4. Command Sets
Read Commands
I/O
1
1
2
2
4
4
2READ
(2 x I/O read
command)
DREAD
(1I / 2O read
command)
4READ
(4 x I/O read
command)
READ
(normal read)
FAST READ
(fast read data)
QREAD (1I/4O
read command)
Command
1st byte
03 (hex)
ADD1(8)
ADD2(8)
ADD3(8)
0B (hex)
ADD1(8)
ADD2(8)
ADD3(8)
Dummy(8)
BB (hex)
ADD1(4)
ADD2(4)
ADD3(4)
Dummy*
3B (hex)
ADD1(8)
ADD2(8)
ADD3(8)
Dummy(8)
EB (hex)
ADD1(2)
ADD2(2)
ADD3(2)
Dummy*
6B (hex)
ADD1(8)
ADD2(8)
ADD3(8)
Dummy(8)
2
nd byte
3rd byte
4th byte
5th byte
n bytes read out n bytes read out n bytes read out n bytes read out Quad I/O read
until CS# goes
high
until CS# goes
high
by 2 x I/O until
CS# goes high
by Dual Output with configurable
until CS# goes
high
dummy cycles
Action
Note: *Dummy cycle number will be different, depending on the bit6 (DC) setting of Configuration Register.
Please refer to "Configuration Register" Table.
P/N: PM2130
Rev. 1.6, October 21, 2016
15
MX25L6433F
Other Commands
WRSR
(write status/
configuration page program) (sector erase)
register)
01 (hex)
Values
Values
RDCR (read
configuration
register)
WREN
WRDI
RDSR (read
4PP (quad
SE
Command
(write enable) (write disable) status register)
1st byte
06 (hex)
04 (hex)
05 (hex)
15 (hex)
38 (hex)
ADD1
ADD2
ADD3
20 (hex)
ADD1
ADD2
ADD3
2
nd byte
3rd byte
4th byte
sets the (WEL) resets the to read out the to read out the to write new quad input to to erase the
write enable
latch bit
(WEL) write values of the values of the values of the program the
enable latch status register configuration configuration/ selected page
selected
sector
Action
bit
register
status register
PGM/ERS
Suspend
(Suspends
Program/
Erase)
BE 32K
(block erase
32KB)
BE
PP
(page
program)
RDP (Release
from deep
power down)
CE
(chip erase)
DP (Deep
power down)
Command
(block erase
64KB)
1st byte
52 (hex)
ADD1
ADD2
D8 (hex)
ADD1
ADD2
60 or C7 (hex)
02 (hex)
ADD1
ADD2
ADD3
B9 (hex)
AB (hex)
75/B0 (hex)
2
nd byte
3rd byte
4th byte
ADD3
ADD3
to erase the
to erase the to erase whole to program the enters deep release from program/erase
selected 32KB selected 64KB
chip
selected page power down
deep power
down mode
operation is
interrupted
by suspend
command
block
block
mode
Action
PGM/ERS
Resume
(Resumes (read identific-
Program/
Erase)
REMS (read
electronic
RDID
WRSCUR
(write security
register)
RES (read
ENSO (enter
EXSO (exit
Command
electronic ID) manufacturer secured OTP) secured OTP)
& device ID)
ation)
1st byte
7A/30 (hex)
9F (hex)
AB (hex)
90 (hex)
B1 (hex)
C1 (hex)
2F (hex)
2
nd byte
x
x
x
x
x
3rd byte
4th byte
ADD
to continue
performing the
suspended
outputs
JEDEC
ID: 1-byte
to read out
output the
to enter the
to exit the
to set the
lockdown
bit as
1-byte Device Manufacturer 8K-bit secured 8K-bit secured
ID ID & Device ID OTP mode OTP mode
program/erase Manufacturer
"1" (once
lockdown,
cannot
Action
sequence
ID & 2-byte
Device ID
be update)
P/N: PM2130
Rev. 1.6, October 21, 2016
16
MX25L6433F
NOP
SBL (Set Burst
(No
Command
(byte)
RDSCUR (read
security register) (Reset Enable) (Reset Memory)
RSTEN
RST
RDSFDP
Length)
Operation)
1st byte
2B (hex)
66 (hex)
99 (hex)
5A (hex)
ADD1(8)
ADD2(8)
ADD3(8)
Dummy(8)
Read SFDP
mode
C0/77 (hex)
00 (hex)
2
nd byte
3rd byte
4th byte
5th byte
to read value of
security register
to set Burst
length
(Note 2)
Action
Note 1: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the
hidden mode.
Note 2: The RSTEN command must be executed before executing the RST command. If any other command is issued in-
between RSTEN and RST, the RST command will be ignored.
P/N: PM2130
Rev. 1.6, October 21, 2016
17
MX25L6433F
10-1. Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP,
4PP, SE, BE, BE32K, CE, and WRSR which are intended to change the device content, should be set every time
after the WREN instruction setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→ CS# goes
high.
The SIO[3:1] are don't care.
Figure 3. Write Enable (WREN) Sequence (Command 06)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
06h
SI
High-Z
SO
P/N: PM2130
Rev. 1.6, October 21, 2016
18
MX25L6433F
10-2. Write Disable (WRDI)
The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.
The sequence of issuing WRDI instruction is: CS# goes low→ sending WRDI instruction code→ CS# goes high.
The WEL bit is reset by following situations:
- Power-up
- WRDI command completion
- WRSR command completion
- PP command completion
- 4PP command completion
- SE command completion
- BE32K command completion
- BE command completion
- CE command completion
- PGM/ERS Suspend command completion
- Soft Reset command completion
- WRSCUR command completion
Figure 4. Write Disable (WRDI) Sequence (Command 04)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
04h
SI
High-Z
SO
P/N: PM2130
Rev. 1.6, October 21, 2016
19
MX25L6433F
10-3. Read Identification (RDID)
The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The
Macronix Manufacturer ID and Device ID are listed as table of "Table 9. ID Definitions".
The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code → 24-bits ID data
out on SO→ to end RDID operation can use CS# to high at any time during data out.
While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the
cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby
stage.
Figure 5. Read Identification (RDID) Sequence (Command 9F)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
28 29 30 31
SCLK
SI
Command
9Fh
Manufacturer Identification
Device Identification
High-Z
SO
7
6
5
3
2
1
0
15 14 13
MSB
3
2
1
0
MSB
P/N: PM2130
Rev. 1.6, October 21, 2016
20
MX25L6433F
10-4. Read Status Register (RDSR)
The RDSR instruction is for reading Status Register. The Read Status Register can be read at any time (even
in program/erase/write status register condition) and continuously. It is recommended to check the Write in
Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is
in progress.
The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register
data out on SO.
The SIO[3:1] are don't care.
Figure 6. Read Status Register (RDSR) Sequence (Command 05)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI
command
05h
Status Register Out
Status Register Out
High-Z
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
P/N: PM2130
Rev. 1.6, October 21, 2016
21
MX25L6433F
10-5. Read Configuration Register (RDCR)
The RDCR instruction is for reading Configuration Register Bits. The Read Configuration Register can be read
at any time (even in program/erase/write configuration register condition). It is recommended to check the Write
in Progress (WIP) bit before sending a new instruction when a program, erase, or write configuration register
operation is in progress.
The sequence of issuing RDCR instruction is: CS# goes low→ sending RDCR instruction code→ Configuration
Register data out on SO.
The SIO[3:1] are don't care.
Figure 7. Read Configuration Register (RDCR) Sequence
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Mode 3
Mode 0
SCLK
SI
command
15h
Configuration register Out
Configuration register Out
High-Z
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
P/N: PM2130
Rev. 1.6, October 21, 2016
22
MX25L6433F
Status Register
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/
write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write
status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/
write status register cycle.
WEL bit. The Write Enable Latch (WEL) bit is a volatile bit that is set to “1” by the WREN instruction. WEL
needs to be set to “1” before the device can accept program and erase instructions, otherwise the program and
erase instructions are ignored. WEL automatically clears to “0” when a program or erase operation completes.
To ensure that both WIP and WEL are “0” and the device is ready for the next program or erase operation, it
is recommended that WIP be confirmed to be “0” before checking that WEL is also “0”. If a program or erase
instruction is applied to a protected memory area, the instruction will be ignored and WEL will clear to “0”.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected
area (as defined in "Table 1. Protected Area Sizes") of the device to against the program/erase instruction
without hardware protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the
Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to
against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip Erase (CE) instructions (only if all
Block Protect bits set to 0, the CE instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default.
Which is un-protected.
QE bit. The Quad Enable (QE) bit is a non-volatile bit with a factory default of “0”. When QE is “0”, Quad mode
commands are ignored; pins WP#/SIO2 and HOLD#/SIO3 function as WP# and HOLD#, respectively. When QE is “1”,
Quad mode is enabled and Quad mode commands are supported along with Single and Dual mode commands.
Pins WP#/SIO2 and HOLD#/SIO3 function as SIO2 and SIO3, respectively, and their alternate pin functions are
disabled. Enabling Quad mode also disables the HPM and HOLD features.
SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, default value is "0". SRWD bit is
operated together with Write Protection (WP#/SIO2) pin for providing hardware protection mode. The hardware
protection mode requires SRWD sets to 1 and WP#/SIO2 pin signal is low stage. In the hardware protection
mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and
Block Protect bits (BP3, BP2, BP1, BP0) are read only. The SRWD bit defaults to be "0".
Table 5. Status Register
bit7
bit6
bit5
BP3
(level of
protected
block)
bit4
BP2
(level of
protected
block)
bit3
BP1
(level of
protected
block)
bit2
BP0
(level of
protected
block)
bit1
bit0
SRWD (Status
Register Write
Disable)
QE
(Quad
Enable)
WEL
(write enable
latch)
WIP
(write in
progress bit)
1=status
register write
disabled
0=status
register write
enabled
1= Quad
Enable
0=not Quad
Enable
1=write
enable
0=not write 0=not in write
1=write
operation
(note 1)
(note 1)
(note 1)
(note 1)
enable
operation
Non-volatile Non-volatile Non-volatile Non-volatile Non-volatile Non-volatile
bit bit bit bit bit bit
Note 1: Please refer to "Table 1. Protected Area Sizes".
volatile bit
volatile bit
P/N: PM2130
Rev. 1.6, October 21, 2016
23
MX25L6433F
Configuration Register
The Configuration Register is able to change the default status of Flash memory. Flash memory will be configured
after the CR bit is set.
ODS bit
The output driver strength ODS bit are volatile bits, which indicate the output driver level of the device. The
Output Driver Strength is defaulted=1 when delivered from factory. To write the ODS bit requires the Write Status
Register (WRSR) instruction to be executed.
TB bit
The Top/Bottom (TB) bit is a OTP bit. The Top/Bottom (TB) bit is used to configure the Block Protect area by BP
bit (BP3, BP2, BP1, BP0), starting from TOP or Bottom of the memory array. The TB bit is defaulted as “0”, which
means Top area protect. When it is set as “1”, the protect area will change to Bottom area of the memory device.
To write the TB bit requires the Write Status Register (WRSR) instruction to be executed.
Table 6. Configuration Register
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
TB
DC
Reserved
(Dummy
Cycle)
Reserved
Reserved (top/bottom Reserved
Reserved
ODS
selected)
0=Top area
protect
1=Bottom
area protect
(Default=0)
0,Output driver
strength=1
2READ/
4READ
Dummy
Cycle
x
x
x
x
x
x
x
x
x
x
1,Output driver
strength=1/4
(Default=0)
volatile
OTP
volatile
Note: Please refer to "Table 7. Dummy Cycle and Frequency Table", with "Don't Care" on other Reserved
Configuration Registers.
Table 7. Dummy Cycle and Frequency Table
Numbers of Dummy
DC
Freq. (MHz)
Cycles
≦
80 @ 2.65V
VCC < 3V
0 (default)
4
8
≧
104 @ VCC
3V
2READ
4READ
1
0 (default)
1
133
≦
80 @ 2.65V
VCC < 3V
6
≧
104 @ VCC
3V
10
133
P/N: PM2130
Rev. 1.6, October 21, 2016
24
MX25L6433F
10-6. Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits and Configuration Register Bits. Before
sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write
Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2,
BP1, BP0) bits to define the protected area of memory (as shown in "Table 1. Protected Area Sizes"). The WRSR
also can set or reset the Quad enable (QE) bit and set or reset the Status Register Write Disable (SRWD) bit in
accordance with Write Protection (WP#/SIO2) pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of the
status register. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered.
The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status
Register data on SI→ CS# goes high.
Figure 8. Write Status Register (WRSR) Sequence (Command 01)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Mode 3
Mode 0
SCLK
command
01h
Status
Register In
Configuration
Register In
SI
4
15 14
13
12 11
10 9
8
2
1
0
7
6
5
3
MSB
High-Z
SO
P/N: PM2130
Rev. 1.6, October 21, 2016
25
MX25L6433F
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The
Write in Progress (WIP) bit still can be checked out during the Write Status Register cycle is in progress. The
WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write
Enable Latch (WEL) bit is reset.
Table 8. Protection Modes
Mode
Status register condition
WP# and SRWD bit status
Memory
Status register can be written
in (WEL bit is set to "1") and
the SRWD, BP0-BP3
Software protection
mode (SPM)
WP#=1 and SRWD bit=0, or
WP#=0 and SRWD bit=0, or
WP#=1 and SRWD=1
The protected area cannot
be programmed or erased.
bits can be changed
The SRWD, BP0-BP3, TB of
status register bits cannot be
changed
Hardware protection
mode (HPM)
The protected area cannot
be programmed or erased.
WP#=0, SRWD bit=1
Note: As defined by the values in the Block Protect (BP3, BP2, BP1, BP0, TB) bits of the Status Register, as
shown in "Table 1. Protected Area Sizes".
As the table above showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode
(HPM):
Software Protected Mode (SPM):
-
When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can
change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1,
BP0, is at software protected mode (SPM).
-
When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values
of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software
protected mode (SPM)
Hardware Protected Mode (HPM):
-
When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the
hardware protected mode (HPM). The data of the protected area is protected by software protected mode by
BP3, BP2, BP1, BP0, TB and hardware protected mode by the WP#/SIO2 to against data modification.
Note:
To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is
entered. If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be
entered; only can use software protected mode via BP3, BP2, BP1, BP0, TB.
If the system goes into four I/O mode, the feature of HPM will be disabled.
P/N: PM2130
Rev. 1.6, October 21, 2016
26
MX25L6433F
Figure 9. WRSR flow
start
WREN command
RDSR command
No
WEL=1?
Yes
WRSR command
Write status register data
RDSR command
No
WIP=0?
Yes
RDSR command
Read WEL=0, BP[3:0], QE,
and SRWD data
No
Verify OK?
Yes
WRSR successfully
WRSR fail
P/N: PM2130
Rev. 1.6, October 21, 2016
27
MX25L6433F
10-7. Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out
on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The
address is automatically increased to the next higher address after each byte data is shifted out, so the whole
memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest
address has been reached.
The sequence of issuing READ instruction is: CS# goes low→ sending READ instruction code→3-byte address
on SI →data out on SO→ to end READ operation can use CS# to high at any time during data out.
Figure 10. Read Data Bytes (READ) Sequence (Command 03)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
03
24 ADD Cycles
A23 A22 A21
MSB
A3 A2 A1 A0
SI
Data Out 2
Data Out 1
High-Z
D7 D6 D5 D4 D3 D2 D1 D0 D7
MSB MSB
SO
P/N: PM2130
Rev. 1.6, October 21, 2016
28
MX25L6433F
10-8. Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be
at any location. The address is automatically increased to the next higher address after each byte data is shifted
out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to
0 when the highest address has been reached.
The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code→
3-byte address on SI→1-dummy byte (default) address on SI→ data out on SO→ to end FAST_READ operation
can use CS# to high at any time during data out. (Please refer to "Figure 11. Read at Higher Speed (FAST_
READ) Sequence (Command 0B)")
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
Figure 11. Read at Higher Speed (FAST_READ) Sequence (Command 0B)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
SCLK
Command
0Bh
24 BIT ADDRESS
SI
23 22 21
3
2
1
0
High-Z
SO
CS#
47
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
SCLK
Dummy Cycle
7
6
5
4
3
2
0
1
SI
DATA OUT 2
DATA OUT 1
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
SO
MSB
MSB
MSB
P/N: PM2130
Rev. 1.6, October 21, 2016
29
MX25L6433F
10-9. Dual Read Mode (DREAD)
The DREAD instruction enable double throughput of Serial NOR Flash in read mode. The address is latched on
rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at
a maximum frequency fT. The first address byte can be at any location. The address is automatically increased
to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single
DREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once
writing DREAD instruction, the following data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing DREAD instruction is: CS# goes low
sending DREAD instruction
3-byte address
→
→
on SI
8-bit dummy cycle
data out interleave on SIO1 & SIO0
to end DREAD operation can use CS# to
→
→
→
high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
Figure 12. Dual Read Mode Sequence (Command 3B)
CS#
30 31 32
39 40 41 42 43 44 45
0
1
2
3
4
5
6
7
8
9
SCLK
…
…
Data Out
Data Out
1
8 dummy
cycle
Command
24 ADD Cycle
2
…
A23 A22
A1 A0
D4 D2
D6 D4
D7 D5
3B
D6
D7
D0
SI/SIO0
High Impedance
D1
D5 D3
SO/SIO1
P/N: PM2130
Rev. 1.6, October 21, 2016
30
MX25L6433F
10-10. 2 x I/O Read Mode (2READ)
The 2READ instruction enables Double Transfer Rate of Serial NOR Flash in read mode. The address is latched
on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of
SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically
increased to the next higher address after each byte data is shifted out, so the whole memory can be read out
at a single 2READ instruction. The address counter rolls over to 0 when the highest address has been reached.
Once writing 2READ instruction, the following address/dummy/data out will perform as 2-bit instead of previous
1-bit.
The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 24-bit address
interleave on SIO1 & SIO0→ 4 dummy cycles(default) on SIO1 & SIO0→ data out interleave on SIO1 & SIO0→
to end 2READ operation can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
Figure 13. 2 x I/O Read Mode Sequence (Command BB)
CS#
28 29
18 19 20 21 22 23 24 25 26 27
0
1
2
3
4
5
6
7
8
9
SCLK
…
Data Out
Data Out
Configurable
Dummy cycles
Command
12 ADD Cycle
2
1
…
A22 A20
A23 A21
A2 A0
P0
D4 D2
D6 D4
D7 D5
P2
BB(hex)
D6
D7
D0
D1
SI/SIO0
High Impedance
…
A3 A1 P3
P1
D5 D3
SO/SIO1
Note: SI/SIO0 or SO/SIO1 should be kept "0h" or "Fh" in the first two dummy cycles. In other words, P2=P0 or
P3=P1 is necessary.
P/N: PM2130
Rev. 1.6, October 21, 2016
31
MX25L6433F
10-11. Quad Read Mode (QREAD)
The QREAD instruction enable quad throughput of Serial NOR Flash in read mode. A Quad Enable (QE) bit of
status Register must be set to "1" before sending the QREAD instruction. The address is latched on rising edge
of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum
frequency fQ. The first address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single QREAD
instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing
QREAD instruction, the following data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing QREAD instruction is: CS# goes low
sending QREAD instruction → 3-byte address
→
on SI
8-bit dummy cycle
data out interleave on SIO3, SIO2, SIO1 & SIO0
to end QREAD operation can
→
→
→
use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
Figure 14. Quad Read Mode Sequence (Command 6B)
CS#
29 30 31 32 33
38 39 40 41 42
0
1
2
3
4
5
6
7
8
9
SCLK
…
…
Data
Out 2
Data
Out 3
Command
6B
8 dummy cycles
24 ADD Cycles
Data
Out 1
…
A23A22
A2 A1 A0
D4 D0 D4 D0 D4
SI/SIO0
High Impedance
High Impedance
High Impedance
SO/SIO1
D5 D1 D5 D1 D5
D6 D2 D6 D2 D6
WP#/SIO2
HOLD#/SIO3
D7 D3 D7 D3 D7
P/N: PM2130
Rev. 1.6, October 21, 2016
32
MX25L6433F
10-12. 4 x I/O Read Mode (4READ)
The 4READ instruction enables quad throughput of Serial NOR Flash in read mode. A Quad Enable (QE) bit of
status Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge
of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum
frequency fQ. The first address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single 4READ
instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing
4READ instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing 4READ instruction is: CS# goes low sending 4READ instruction 24-bit address
→
→
interleave on SIO3, SIO2, SIO1 & SIO0 2+4 dummy cycles (default) data out interleave on SIO3, SIO2, SIO1
→
→
& SIO0 to end 4READ operation can use CS# to high at any time during data out. (Please refer to the figure
→
below)
Figure 15. 4 x I/O Read Mode Sequence (Command EB)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
n
SCLK
Conꢀgurable
Dummy cycles
8 Bit Instruction
EBh
6 Address cycles
Data Output
(Note 3)
Performance
enhance
indicator (Note 1&2)
data
bit4, bit0, bit4....
address
bit20, bit16..bit0
P4 P0
P5 P1
P6 P2
P7 P3
SI/SIO0
High Impedance
High Impedance
High Impedance
address
bit21, bit17..bit1
data
bit5 bit1, bit5....
SO/SIO1
address
bit22, bit18..bit2
data
bit6 bit2, bit6....
WP#/SIO2
HOLD#/SIO3
address
bit23, bit19..bit3
data
bit7 bit3, bit7....
Notes:
1. Hi-impedance is inhibited for the two clock cycles.
2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited.
3. The Configurable Dummy Cycle is set by Configuration Register Bit. Please see "Dummy Cycle and
Frequency Table"
P/N: PM2130
Rev. 1.6, October 21, 2016
33
MX25L6433F
Another sequence of issuing 4READ instruction especially useful in random access is : CS# goes low→ sending
4READ instruction→ 3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 →performance enhance toggling
bit P[7:0]→ 4 dummy cycles → data out until CS# goes high → CS# goes low (reduce 4READ instruction) →
24-bit random access address (Please refer to "Figure 16. 4 x I/O Read enhance performance Mode Sequence
(Command EB) (SPI Mode)" ).
In the performance-enhancing mode (Notes of "Figure 16. 4 x I/O Read enhance performance Mode Sequence
(Command EB) (SPI Mode)"), P[7:4] must be toggling with P[3:0]; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh can
make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0];
likewise P[7:0]=FFh, 00h, AAh or 55h. These commands will reset the performance enhance mode. And
afterwards CS# is raised and then lowered, the system then will return to normal operation.
While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
P/N: PM2130
Rev. 1.6, October 21, 2016
34
MX25L6433F
10-13. Performance Enhance Mode
The device could waive the command cycle bits if the two cycle bits after address cycle toggles. (Please note
"Figure 16. 4 x I/O Read enhance performance Mode Sequence (Command EB) (SPI Mode)")
Performance enhance mode is supported for 4READ mode.
“EBh” commands support enhance mode.
After entering enhance mode, following CS# go high, the device will stay in the read mode and treat CS# go low
of the first clock as address instead of command cycle.
To exit enhance mode, a new fast read command whose first two dummy cycles is not toggle then exit. Or issue
”FFh” data cycles to exit enhance mode.
Figure 16. 4 x I/O Read enhance performance Mode Sequence (Command EB) (SPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
n
SCLK
Conꢀgurable
Dummy cycles
8 Bit Instruction
EBh
6 Address cycles
Data Output
(Note 2)
Performance
enhance
indicator (Note1)
data
bit4, bit0, bit4....
address
bit20, bit16..bit0
P4 P0
P5 P1
P6 P2
P7 P3
SI/SIO0
High Impedance
High Impedance
High Impedance
address
bit21, bit17..bit1
data
bit5 bit1, bit5....
SO/SIO1
address
bit22, bit18..bit2
data
bit6 bit2, bit6....
WP#/SIO2
HOLD#/SIO3
address
bit23, bit19..bit3
data
bit7 bit3, bit7....
CS#
n+1
...........
n+7......n+9 ........... n+13
...........
SCLK
Conꢀgurable
Dummy cycles
6 Address cycles
address
Data Output
(Note 2)
Performance
enhance
indicator (Note1)
data
bit4, bit0, bit4....
P4 P0
P5 P1
P6 P2
P7 P3
SI/SIO0
bit20, bit16..bit0
address
bit21, bit17..bit1
data
bit5 bit1, bit5....
SO/SIO1
address
bit22, bit18..bit2
data
bit6 bit2, bit6....
WP#/SIO2
HOLD#/SIO3
address
bit23, bit19..bit3
data
bit7 bit3, bit7....
Notes:
1. Performance enhance mode, if P7≠P3 & P6≠P2 & P5≠P1 & P4≠P0 (Toggling), ex: A5, 5A, 0F, if not using
performance enhance recommend to keep 1 or 0 in performance enhance indicator.
Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF.
2. The Configurable Dummy Cycle is set by Configuration Register Bit. Please refer to "Dummy Cycle and
Frequency Table"
P/N: PM2130
Rev. 1.6, October 21, 2016
35
MX25L6433F
10-14. Burst Read
The Burst Read feature allows applications to fill a cache line with a fixed length of data without using multiple
read commands. Burst Read is disabled by default at power-up or reset. Burst Read is enabled by setting
the Burst Length. When the Burst Length is set, reads will wrap on the selected boundary (8/16/32/64-bytes)
containing the initial target address. For example if an 8-byte Wrap Depth is selected, reads will wrap on the
8-byte-page-aligned boundary containing the initial read address.
To set the Burst Length, drive CS# low → send SET BURST LENGTH instruction code → send WRAP CODE →
drive CS# high. Refer to the table below for valid 8-bit Wrap Codes and their corresponding Wrap Depth.
Data
00h
01h
02h
03h
1xh
Wrap Around
Wrap Depth
8-byte
Yes
Yes
Yes
Yes
No
16-byte
32-byte
64-byte
X
Once Burst Read is enabled, it will remain enabled until the device is power-cycled or reset. The 4READ read
command supports the wrap around feature after Burst Read is enabled. To change the wrap depth, resend the
Burst Read instruction with the appropriate Wrap Code. To disable Burst Read, send the Burst Read instruction
with Wrap Code 1xh. “EBh" supports wrap around feature after wrap around is enabled.
Figure 17. Burst Read
CS#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Mode 3
Mode 0
SCLK
SIO
D7
D6
D5
D4
D3
D2
D1
D0
C0h or 77h
P/N: PM2130
Rev. 1.6, October 21, 2016
36
MX25L6433F
10-15. Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used
for any 4K-byte sector. A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL)
bit before sending the Sector Erase (SE). Any address of the sector (see "Table 3. Memory Organization" ) is a
valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the least
significant bit of the address has been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing SE instruction is: CS# goes low → sending SE instruction code→ 3-byte address on SI
→CS# goes high.
The SIO[3:1] are don't care.
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets during the tSE
timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
sector is protected by BP3~0, the array data will be protected (no change) and the WEL bit still be reset.
Figure 18. Sector Erase (SE) Sequence (Command 20)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
20h
24 Bit Address
SI
23 22
MSB
2
1
0
P/N: PM2130
Rev. 1.6, October 21, 2016
37
MX25L6433F
10-16. Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used
for 64K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write
Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (Please refer to "Table
3. Memory Organization") is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at
the byte boundary (the least significant bit of address byte has been latched-in); otherwise, the instruction will be
rejected and not executed.
The sequence of issuing BE instruction is: CS# goes low → sending BE instruction code → 3-byte address on
SI → CS# goes high.
The SIO[3:1] are don't care.
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during the tBE
timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
block is protected by BP3~0, the array data will be protected (no change) and the WEL bit still be reset.
Figure 19. Block Erase (BE) Sequence (Command D8)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
D8h
24 Bit Address
SI
23 22
MSB
2
0
1
P/N: PM2130
Rev. 1.6, October 21, 2016
38
MX25L6433F
10-17. Block Erase (BE32K)
The Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1". The instruction is used
for 32K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable
Latch (WEL) bit before sending the Block Erase (BE32K). Any address of the block (see "Table 3. Memory
Organization" ) is a valid address for Block Erase (BE32K) instruction. The CS# must go high exactly at the byte
boundary (the least significant bit of address byte has been latched-in); otherwise, the instruction will be rejected
and not executed.
The sequence of issuing BE32K instruction is: CS# goes low → sending BE32K instruction code → 3-byte
address on SI → CS# goes high.
The SIO[3:1] are don't care.
The self-timed Block Erase Cycle time (tBE32K) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during
the tBE32K timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is
cleared. If the block is protected by BP3~0, the array data will be protected (no change) and the WEL bit still be
reset.
Figure 20. Block Erase 32KB (BE32K) Sequence (Command 52)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
52h
24 Bit Address
SI
23 22
MSB
2
0
1
P/N: PM2130
Rev. 1.6, October 21, 2016
39
MX25L6433F
10-18. Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN)
instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The
CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The sequence of issuing CE instruction is: CS# goes low → sending CE instruction code → CS# goes high.
The SIO[3:1] are don't care.
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Chip Erase cycle is in progress. The WIP sets during the tCE
timing, and clears when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
chip is protected the Chip Erase (CE) instruction will not be executed, but WEL will be reset.
Figure 21. Chip Erase (CE) Sequence (Command 60 or C7)
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
60h or C7h
P/N: PM2130
Rev. 1.6, October 21, 2016
40
MX25L6433F
10-19. Page Program (PP)
The Page Program (PP) instruction is for programming memory bits to "0". One to 256 bytes can be sent to the
device to be programmed. A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL)
bit before sending the Page Program (PP). If more than 256 data bytes are sent to the device, only the last 256
data bytes will be accepted and the previous data bytes will be disregarded. The Page Program instruction
requires that all the data bytes fall within the same 256-byte page. The low order address byte A[7:0] specifies
the starting address within the selected page. Bytes that will cross a page boundary will wrap to the beginning of
the selected page. The device can accept (256 minus A[7:0]) data bytes without wrapping. If 256 data bytes are
going to be programmed, A[7:0] should be set to 0.
The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on
SI→ at least 1-byte on data on SI→ CS# goes high.
The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte
boundary (the latest eighth bit of data being latched in), otherwise, the instruction will be rejected and will not be
executed.
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Page Program cycle is in progress. The WIP sets during the
tPP timing, and clears when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is cleared.
If the page is protected by BP3~0, the array data will be protected (no change) and the WEL bit will still be reset.
The SIO[3:1] are don't care.
Figure 22. Page Program (PP) Sequence (Command 02)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
02h
24-Bit Address
Data Byte 1
23 22 21
MSB
3
2
1
0
7
6
5
4
3
2
0
1
SI
MSB
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
Data Byte 2
Data Byte 3
Data Byte 256
7
6
5
4
3
2
0
7
6
5
4
3
2
0
7
6
5
4
3
2
0
1
1
1
SI
MSB
MSB
MSB
P/N: PM2130
Rev. 1.6, October 21, 2016
41
MX25L6433F
10-20. 4 x I/O Page Program (4PP)
The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN)
instruction must be executed to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set
to "1" before sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0,
SIO1, SIO2, and SIO3, which can raise programmer performance and the effectiveness of application of lower
clock less than f4PP. For system with faster clock, the Quad page program cannot provide more performance,
because the required internal page program time is far more than the time data flows in. Therefore, we suggest
that while executing this command (especially during sending data), user can slow the clock speed down to f4PP
below. The other function descriptions are as same as standard page program.
The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on
SIO[3:0]→ at least 1-byte on data on SIO[3:0]→ CS# goes high.
If the page is protected by BP3~0, the array data will be protected (no change) and the WEL bit will still be reset.
Figure 23. 4 x I/O Page Program (4PP) Sequence (Command 38)
CS#
524 525
10 11 12 13 14 15 16 17
0
1
2
3
4
5
6
7
8
9
SCLK
…
…
Data
Byte 256
Data Data
Byte 1 Byte 2
Command
38
6 ADD cycles
D4 D0 D4 D0
D4 D0
A20 A16 A12 A8 A4 A0
SI/SIO0
…
…
…
D5 D1 D5 D1
D6 D2 D6 D2
D7 D3 D7 D3
D5 D1
D6 D2
D7 D3
SO/SIO1
A21 A17 A13 A9 A5 A1
A22 A18 A14 A10 A6 A2
WP#/SIO2
HOLD#/SIO3
A23 A19 A15 A11 A7 A3
P/N: PM2130
Rev. 1.6, October 21, 2016
42
MX25L6433F
The Program/Erase function instruction function flow is as follows:
Figure 24. Program/Erase Flow(1) with read array data
Start
WREN command
RDSR command*
No
WEL=1?
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
No
WIP=0?
Yes
Read array data
(same address of PGM/ERS)
No
Verify OK?
Yes
Program/erase fail
Program/erase successfully
Program/erase
another block?
Yes
* Issue RDSR to check BP[3:0].
No
Program/erase completed
P/N: PM2130
Rev. 1.6, October 21, 2016
43
MX25L6433F
Figure 25. Program/Erase Flow(2) without read array data
Start
WREN command
RDSR command*
No
WEL=1?
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
No
WIP=0?
Yes
RDSCUR command
Yes
P_FAIL/E_FAIL=1?
No
Program/erase fail
Program/erase successfully
Program/erase
another block?
Yes
* Issue RDSR to check BP[3:0].
No
Program/erase completed
P/N: PM2130
Rev. 1.6, October 21, 2016
44
MX25L6433F
10-21. Deep Power-down (DP)
The Deep Power-down (DP) instruction places the device into a minimum power consumption state, Deep
Power-down mode, in which the quiescent current is reduced from ISB1 to ISB2.
The sequence of issuing DP instruction: CS# goes low→ send DP instruction code→ CS# goes high. The CS#
must go high at the byte boundary (after exactly eighth bits of the instruction code have been latched-in);
otherwise the instruction will not be executed. SIO[3:1] are "don't care".
After CS# goes high there is a delay of tDP before the device transitions from Stand-by mode to Deep Power-
down mode and before the current reduces from ISB1 to ISB2. Once in Deep Power-down mode, all instructions
will be ignored except Release from Deep Power-down (RDP).
The device exits Deep Power-down mode and returns to Stand-by mode if it receives a Release from Deep
Power-down (RDP) instruction, power-cycle, or reset.
Figure 26. Deep Power-down (DP) Sequence (Command B9)
CS#
tDP
0
1
2
3
4
5
6
7
SCLK
SI
Command
B9h
Stand-by Mode
Deep Power-down Mode
P/N: PM2130
Rev. 1.6, October 21, 2016
45
MX25L6433F
10-22. Release from Deep Power-down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is completed by driving Chip Select (CS#) High. When
Chip Select (CS#) is driven High, the device is put in the standby Power mode. If the device was not previously in
the Deep Power-down mode, the transition to the standby Power mode is immediate. If the device was previously
in the Deep Power-down mode, though, the transition to the standby Power mode is delayed by tRES2, and Chip
Select (CS#) must remain High for at least tRES2(max), as specified in "Table 18. AC Characteristics". Once in
the standby mode, the device waits to be selected, so that it can receive, decode and execute instructions.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as "Table 9.
ID Definitions". This is not the same as RDID instruction. It is not recommended to use for new design. For new
design, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to
be executed, only except the device is in progress of program/erase/write cycles; there's no effect on the current
program/erase/write cycles in progress.
The SIO[3:1] are don't care when during this mode.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs
repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not
previously in Deep Power-down mode, the device transition to standby mode is immediate. If the device was
previously in Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must
remain to high at least tRES2(max). Once in the standby mode, the device waits to be selected, so it can
receive, decode, and execute instruction.
The RDP instruction is for releasing from Deep Power-down Mode.
Figure 27. Read Electronic Signature (RES) Sequence (Command AB)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38
SCLK
Command
ABh
t
3 Dummy Bytes
RES2
SI
23 22 21
MSB
3
2
1
0
Electronic Signature Out
High-Z
7
6
5
4
3
2
0
1
SO
MSB
Deep Power-down Mode
Stand-by Mode
P/N: PM2130
Rev. 1.6, October 21, 2016
46
MX25L6433F
Figure 28. Release from Deep Power-down (RDP) Sequence
CS#
t
RES1
0
1
2
3
4
5
6
7
Mode 3
Mode 0
SCLK
SI
Command
ABh
High-Z
SO
Deep Power-down Mode
Stand-by Mode
P/N: PM2130
Rev. 1.6, October 21, 2016
47
MX25L6433F
10-23. Read Electronic Manufacturer ID & Device ID (REMS)
The REMS instruction returns both the JEDEC assigned manufacturer ID and the device ID. The Device ID
values are listed in "Table 9. ID Definitions".
The REMS instruction is initiated by driving the CS# pin low and sending the instruction code "90h" followed by
two dummy bytes and one address byte (A7-A0). After which the manufacturer ID for Macronix (C2h) and the
device ID are shifted out on the falling edge of SCLK with the most significant bit (MSB) first. If the address byte
is 00h, the manufacturer ID will be output first, followed by the device ID. If the address byte is 01h, then the
device ID will be output first, followed by the manufacturer ID. While CS# is low, the manufacturer and device IDs
can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high.
Figure 29. Read Electronic Manufacturer & Device ID (REMS) Sequence
CS#
0
1
2
3
4
5
6
7
8
9 10
Mode 3
Mode 0
SCLK
Command
90h
2 Dummy Bytes
SI
15 14 13
3
2
1
0
High-Z
SO
CS#
47
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
SCLK
ADD (1)
7
6
5
4
3
2
0
1
SI
Manufacturer ID
Device ID
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
SO
MSB
MSB
MSB
Notes:
(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first.
P/N: PM2130
Rev. 1.6, October 21, 2016
48
MX25L6433F
Table 9. ID Definitions
Command Type
MX25L6433F
Memory type
20
Electronic ID
16
Manufacturer ID
Memory density
RDID
RES
C2
17
Manufacturer ID
Device ID
16
REMS
C2
10-24. Enter Secured OTP (ENSO)
The ENSO instruction is for entering the additional 8K-bit Secured OTP mode. While the device is in 8K-bit
Secured OTP mode, array access is not available. The additional 8K-bit Secured OTP is independent from main
array, which may use to store unique serial number for system identifier. After entering the Secured OTP mode,
and then follow standard read or program procedure to read out the data or update data.
The Secured OTP data cannot be updated again once it is lock-down.
The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP
mode→ CS# goes high.
The SIO[3:1] are don't care.
Please note that WRSR/WRSCUR/CE/BE/SE/BE32K commands are not acceptable during the access of secure
OTP region, once Security OTP is locked down, only read related commands are valid.
10-25. Exit Secured OTP (EXSO)
The EXSO instruction is for exiting the additional 8K-bit Secured OTP mode.
The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP
mode→ CS# goes high.
The SIO[3:1] are don't care.
P/N: PM2130
Rev. 1.6, October 21, 2016
49
MX25L6433F
10-26. Read Security Register (RDSCUR)
The RDSCUR instruction is for reading the value of Security Register. The Read Security Register can be read at
any time (even in program/erase/write status register/write security register condition) and continuously.
The sequence of issuing RDSCUR instruction is : CS# goes low→ sending RDSCUR instruction → Security
Register data out on SO→ CS# goes high.
The SIO[3:1] are don't care.
Figure 30. Read Security Register (RDSCUR) Sequence (Command 2B)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI
command
2B
Security Register Out
Security Register Out
High-Z
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
P/N: PM2130
Rev. 1.6, October 21, 2016
50
MX25L6433F
The definition of the Security Register is as below:
Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory before ex-
factory or not. When it is "0", it indicates non-factory lock; "1" indicates factory- lock.
Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for
customer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 1st 4K-bit
Secured OTP area cannot be updated any more.
Program Suspend Status bit. Program Suspend Bit (PSB) indicates the status of Program Suspend operation.
Users may use PSB to identify the state of flash memory. After the flash memory is suspended by Program
Suspend command, PSB is set to "1". PSB is cleared to "0" after program operation resumes.
Erase Suspend Status bit. Erase Suspend Bit (ESB) indicates the status of Erase Suspend operation. Users
may use ESB to identify the state of flash memory. After the flash memory is suspended by Erase Suspend
command, ESB is set to "1". ESB is cleared to "0" after erase operation resumes.
Program Fail Flag bit. While a program failure happened, the Program Fail Flag bit would be set. If the program
operation fails on a protected memory region, this bit will also be set. This bit can be the failure indication of
one or more program operations. This fail flag bit will be cleared automatically after the next successful program
operation.
Erase Fail Flag bit. While an erase failure happened, the Erase Fail Flag bit would be set. If the erase operation
fails on a protected memory region, this bit will also be set. This bit can be the failure indication of one or more
erase operations. This fail flag bit will be cleared automatically after the next successful erase operation.
Table 10. Security Register Definition
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
LDSO
Secured OTP
Indicator bit
(2nd 4K-bit
ESB (Erase PSB (Program
(lock-down
Reserved
E_FAIL
P_FAIL
Reserved
Suspend
status)
Suspend
status)
1st 4K-bit
Secured OTP) Secured OTP)
0=normal
Erase
succeed
0=normal
Program
succeed
0 = not
lockdown
not suspended 1 = lock-down
(cannot
0=Erase
is not
suspended
0=Program is
0 = nonfactory
lock
1 = factory
lock
Reserved
Reserved
1=indicate
Erase failed
(default=0)
1=indicate
Program
failed
1=Program
is suspended
(default=0)
program/
erase
OTP)
1=Erase is
suspended
(default=0)
(default=0)
non-volatile
non-volatile
non-volatile
volatile bit
Read Only
volatile bit volatile bit volatile bit
Read Only Read Only
volatile bit
Read Only
bit
bit
bit
Reserved
OTP
Read Only
P/N: PM2130
Rev. 1.6, October 21, 2016
51
MX25L6433F
10-27. Write Security Register (WRSCUR)
The WRSCUR instruction is for changing the values of Security Register Bits. Unlike write status register, the
WREN instruction is required before sending WRSCUR instruction. The WRSCUR instruction may change the
values of bit1 (LDSO bit) for customer to lock-down the 1st 4K-bit Secured OTP area. Once the LDSO bit is set
to "1", the 1st 4K-bit Secured OTP area cannot be updated any more.
The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes
high.
The SIO[3:1] are don't care.
The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
Figure 31. Write Security Register (WRSCUR) Sequence (Command 2F) (SPI mode)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
2F
SI
High-Z
SO
P/N: PM2130
Rev. 1.6, October 21, 2016
52
MX25L6433F
10-28. Program Suspend and Erase Suspend
The Suspend instruction interrupts a Page Program, Sector Erase, or Block Erase operation to allow access to
the memory array. After the program or erase operation has entered the suspended state, the memory array can
be read except for the page being programmed or the sector or block being erased ("Table 11. Readable Area of
Memory While a Program or Erase Operation is Suspended").
Table 11. Readable Area of Memory While a Program or Erase Operation is Suspended
Suspended Operation
Page Program
Readable Region of Memory Array
All but the Page being programmed
All but the 4KB Sector being erased
All but the 32KB Block being erased
All but the 64KB Block being erased
Sector Erase (4KB)
Block Erase (32KB)
Block Erase (64KB)
When the Serial NOR Flash receives the Suspend instruction, there is a latency of tPSL or tESL ("Figure 32.
Suspend to Read Latency") before the Write Enable Latch (WEL) bit clears to “0” and the PSB or ESB sets to
“1”, after which the device is ready to accept one of the commands listed in "Table 12. Acceptable Commands
During Program/Erase Suspend after tPSL/tESL" (e.g. FAST READ). Refer to "Table 18. AC Characteristics" for
tPSL and tESL timings. "Table 13. Acceptable Commands During Suspend (tPSL/tESL not required)" lists the
commands for which the tPSL and tESL latencies do not apply. For example, RDSR, RDSCUR, RSTEN, and
RST can be issued at any time after the Suspend instruction.
Security Register bit 2 (PSB) and bit 3 (ESB) can be read to check the suspend status. The PSB (Program
Suspend Bit) sets to “1” when a program operation is suspended. The ESB (Erase Suspend Bit) sets to “1”
when an erase operation is suspended. The PSB or ESB clears to “0” when the program or erase operation is
resumed.
Table 12. Acceptable Commands During Program/Erase Suspend after tPSL/tESL
Suspend Type
Command Name
Command Code
Program Suspend
Erase Suspend
READ
FAST READ
DREAD
QREAD
2READ
4READ
RDSFDP
RDID
03h
0Bh
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
3Bh
6Bh
BBh
EBh
5Ah
9Fh
REMS
90h
ENSO
B1h
EXSO
C1h
WREN
RESUME
PP
06h
7Ah or 30h
02h
•
4PP
38h
P/N: PM2130
Rev. 1.6, October 21, 2016
53
MX25L6433F
Table 13. Acceptable Commands During Suspend (tPSL/tESL not required)
Suspend Type
Command Name
Command Code
Program Suspend
Erase Suspend
WRDI
RDSR
RDCR
RDSCUR
RES
04h
05h
15h
2Bh
ABh
66h
99h
00h
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
RSTEN
RST
NOP
Figure 32. Suspend to Read Latency
tPSL / tESL
Read Command
Suspend Command
CS#
tPSL: Program Latency
tESL: Erase Latency
Figure 33. Resume to Suspend Latency
tPRS / tERS
Suspend
Resume
Command
CS#
Command
tPRS: Program Resume to another Suspend
tERS: Erase Resume to another Suspend
P/N: PM2130
Rev. 1.6, October 21, 2016
54
MX25L6433F
10-28-1. Erase Suspend to Program
The “Erase Suspend to Program” feature allows Page Programming while an erase operation is suspended.
Page Programming is permitted in any unprotected memory except within the sector of a suspended Sector
Erase operation or within the block of a suspended Block Erase operation. The Write Enable (WREN) instruction
must be issued before any Page Program instruction.
A Page Program operation initiated within a suspended erase cannot itself be suspended and must be allowed
to finish before the suspended erase can be resumed. The Status Register can be polled to determine the status
of the Page Program operation. The WEL and WIP bits of the Status Register will remain “1” while the Page
Program operation is in progress and will both clear to “0” when the Page Program operation completes.
Figure 34. Suspend to Program Latency
tPSL / tESL
Suspend Command
Program Command
CS#
tPSL: Program Latency
tESL: Erase Latency
10-29. Program Resume and Erase Resume
The Resume instruction resumes a suspended Page Program, Sector Erase, or Block Erase operation. Before
issuing the Resume instruction to restart a suspended erase operation, make sure that there is no Page Program
operation in progress.
Immediately after the Serial NOR Flash receives the Resume instruction, the WEL and WIP bits are set to “1” and
the PSB or ESB is cleared to “0”. The program or erase operation will continue until finished ("Figure 35. Resume
to Read Latency") or until another Suspend instruction is received. A resume-to-suspend latency of tPRS or tERS
must be observed before issuing another Suspend instruction ("Figure 33. Resume to Suspend Latency").
Please note that the Resume instruction will be ignored if the Serial NOR Flash is in “Performance Enhance
Mode”. Make sure the Serial NOR Flash is not in “Performance Enhance Mode” before issuing the Resume
instruction.
Figure 35. Resume to Read Latency
tSE/tBE/tBE32K/tPP
Read Command
Resume Command
CS#
P/N: PM2130
Rev. 1.6, October 21, 2016
55
MX25L6433F
10-30. No Operation (NOP)
The "No Operation" command is only able to terminate the Reset Enable (RSTEN) command and will not affect
any other command.
10-31. Software Reset (Reset-Enable (RSTEN) and Reset (RST))
The Software Reset operation combines two instructions: Reset-Enable (RSTEN) command and Reset (RST)
command. It returns the device to a standby mode. All the volatile bits and settings will be cleared then, which
makes the device return to the default status as power on.
To execute Reset command (RST), the Reset-Enable (RSTEN) command must be executed first to perform the
Reset operation. If there is any other command to interrupt after the Reset-Enable command, the Reset-Enable
will be invalid.
If the Reset command is executed during program or erase operation, the operation will be disabled, the data
under processing could be damaged or lost.
The reset time is different depending on the last operation. Longer latency time is required to recover from a
program operation than from other operations.
Figure 36. Software Reset Recovery
Stand-by Mode
66
99
CS#
tRCR
tRCP
tRCE
Mode
P/N: PM2130
Rev. 1.6, October 21, 2016
56
MX25L6433F
10-32. Read SFDP Mode (RDSFDP)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the
functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These
parameter tables can be interrogated by host system software to enable adjustments needed to accommodate
divergent features from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC
Standard, JESD68 on CFI.
The sequence of issuing RDSFDP instruction is CS# goes low→send RDSFDP instruction (5Ah)→send 3
address bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP operation
can use CS# to high at any time during data out.
SFDP is a JEDEC Standard, JESD216.
Figure 37. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
SCLK
Command
5Ah
24 BIT ADDRESS
SI
23 22 21
3
2
1
0
High-Z
SO
CS#
47
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
SCLK
Dummy Cycle
7
6
5
4
3
2
0
1
SI
DATA OUT 2
DATA OUT 1
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
SO
MSB
MSB
MSB
P/N: PM2130
Rev. 1.6, October 21, 2016
57
MX25L6433F
Table 14. Signature and Parameter Identification Data Values
SFDP Table (JESD216) below is for MX25L6433FM2I-08G, MX25L6433FMI-08G, MX25L6433FZNI-08G,
MX25L6433FXCI-08G, MX25L6433FBBI-08G, MX25L6433FZ2I-08G, MX25L6433FM2I-08Q, MX25L6433FMI-
08Q, MX25L6433FZNI-08Q, MX25L6433FXCI-08Q, MX25L6433FBBI-08Q and MX25L6433FZ2I-08Q
Add (h) DW Add Data (h/b) Data
Description
Comment
(Byte)
(Bit)
(Note1)
(h)
00h
07:00
53h
53h
01h
02h
03h
04h
05h
15:08
23:16
31:24
07:00
15:08
46h
44h
50h
00h
01h
46h
44h
50h
00h
01h
SFDP Signature
Fixed: 50444653h
S F D P M in o r R e v is io n N u m b e r
SFDP Major Revision Number
Start from 00h
Start from 01h
This number is 0-based. Therefore,
0 indicates 1 parameter header.
Number of Parameter Headers
Unused
06h
07h
08h
09h
0Ah
0Bh
23:16
31:24
07:00
15:08
23:16
31:24
01h
FFh
00h
00h
01h
09h
01h
FFh
00h
00h
01h
09h
00h: it indicates a JEDEC specified
header.
ID number (JEDEC)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length
(in double word)
Start from 00h
Start from 01h
How many DWORDs in the
Parameter table
0Ch
0Dh
0Eh
07:00
15:08
23:16
30h
00h
00h
30h
00h
00h
First address of JEDEC Flash
Parameter table
Parameter Table Pointer (PTP)
Unused
0Fh
10h
11h
12h
13h
31:24
07:00
15:08
23:16
31:24
FFh
C2h
00h
01h
04h
FFh
C2h
00h
01h
04h
ID number
(Macronix manufacturer ID)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
it indicates Macronix manufacturer
ID
Start from 00h
Start from 01h
Parameter Table Length
(in double word)
How many DWORDs in the
Parameter table
14h
15h
16h
07:00
15:08
23:16
60h
00h
00h
60h
00h
00h
First address of Macronix Flash
Parameter table
Parameter Table Pointer (PTP)
Unused
17h
31:24
FFh
FFh
P/N: PM2130
Rev. 1.6, October 21, 2016
58
MX25L6433F
Table 15. Parameter Table (0): JEDEC Flash Parameter Tables
SFDP Table below is for MX25L6433FM2I-08G, MX25L6433FMI-08G, MX25L6433FZNI-08G, MX25L6433FXCI-
08G, MX25L6433FBBI-08G, MX25L6433FZ2I-08G, MX25L6433FM2I-08Q, MX25L6433FMI-08Q,
MX25L6433FZNI-08Q, MX25L6433FXCI-08Q, MX25L6433FBBI-08Q and MX25L6433FZ2I-08Q
Add (h) DW Add Data (h/b) Data
Description
Comment
(Byte)
(Bit)
(Note1)
(h)
00: Reserved, 01: 4KB erase,
10: Reserved,
11: not support 4KB erase
Block/Sector Erase sizes
Write Granularity
01:00
01b
0: 1Byte, 1: 64Byte or larger
02
03
1b
0b
Write Enable Instruction Required 0: not required
for Writing to Volatile Status
Registers
1: required 00h to be written to the
status register
30h
E5h
0: use 50h opcode,
1: use 06h opcode
Write Enable Opcode Select for
Writing to Volatile Status Registers
Note: If target flash status register is
nonvolatile, then bits 3 and 4 must
be set to 00b.
04
0b
Contains 111b and can never be
changed
Unused
07:05
111b
4KB Erase Opcode
31h
32h
33h
15:08
20h
20h
F1h
FFh
(1-1-2) Fast Read (Note2)
0=not support 1=support
16
1b
Address Bytes Number used in
addressing flash array
00: 3Byte only, 01: 3 or 4Byte,
10: 4Byte only, 11: Reserved
18:17
00b
0b
Double Transfer Rate (DTR)
Clocking
0=not support 1=support
19
(1-2-2) Fast Read
(1-4-4) Fast Read
(1-1-4) Fast Read
Unused
0=not support 1=support
0=not support 1=support
0=not support 1=support
20
21
1b
1b
22
1b
23
1b
Unused
31:24
FFh
Flash Memory Density
37h:34h 31:00
03FF FFFFh
(1-4-4) Fast Read Number of Wait 0 0000b: Not supported; 0 0100b: 4
04:00
38h
0 0100b
states (Note3)
0 0110b: 6; 0 1000b: 8
44h
EBh
08h
6Bh
(1-4-4) Fast Read Number of
Mode Bits (Note4)
Mode Bits:
000b: Not supported; 010b: 2 bits
07:05
010b
EBh
(1-4-4) Fast Read Opcode
39h
3Ah
3Bh
15:08
20:16
(1-1-4) Fast Read Number of Wait 0 0000b: Not supported; 0 0100b: 4
0 1000b
states
0 0110b: 6; 0 1000b: 8
(1-1-4) Fast Read Number of
Mode Bits
Mode Bits:
000b: Not supported; 010b: 2 bits
23:21
31:24
000b
(1-1-4) Fast Read Opcode
6Bh
P/N: PM2130
Rev. 1.6, October 21, 2016
59
MX25L6433F
SFDP Table below is for MX25L6433FM2I-08G, MX25L6433FMI-08G, MX25L6433FZNI-08G, MX25L6433FXCI-
08G, MX25L6433FBBI-08G, MX25L6433FZ2I-08G, MX25L6433FM2I-08Q, MX25L6433FMI-08Q,
MX25L6433FZNI-08Q, MX25L6433FXCI-08Q, MX25L6433FBBI-08Q and MX25L6433FZ2I-08Q
Add (h) DW Add Data (h/b) Data
Description
Comment
(Byte)
(Bit)
(Note1)
(h)
(1-1-2) Fast Read Number of Wait 0 0000b: Not supported; 0 0100b: 4
04:00
0 1000b
states
0 0110b: 6; 0 1000b: 8
3Ch
08h
(1-1-2) Fast Read Number of
Mode Bits
Mode Bits:
000b: Not supported; 010b: 2 bits
07:05
15:08
20:16
000b
3Bh
(1-1-2) Fast Read Opcode
3Dh
3Eh
3Fh
3Bh
04h
BBh
(1-2-2) Fast Read Number of Wait 0 0000b: Not supported; 0 0100b: 4
0 0100b
states
0 0110b: 6; 0 1000b: 8
(1-2-2) Fast Read Number of
Mode Bits
Mode Bits:
000b: Not supported; 010b: 2 bits
23:21
000b
(1-2-2) Fast Read Opcode
(2-2-2) Fast Read
Unused
31:24
00
BBh
0b
0=not support 1=support
0=not support 1=support
03:01
04
111b
0b
40h
EEh
(4-4-4) Fast Read
Unused
07:05
111b
FFh
FFh
Unused
43h:41h 31:08
45h:44h 15:00
FFh
FFh
Unused
(2-2-2) Fast Read Number of Wait 0 0000b: Not supported; 0 0100b: 4
20:16
46h
0 0000b
000b
states
0 0110b: 6; 0 1000b: 8
00h
(2-2-2) Fast Read Number of
Mode Bits
Mode Bits:
000b: Not supported; 010b: 2 bits
23:21
(2-2-2) Fast Read Opcode
Unused
47h
31:24
FFh
FFh
FFh
FFh
49h:48h 15:00
(4-4-4) Fast Read Number of Wait 0 0000b: Not supported; 0 0100b: 4
20:16
4Ah
0 0000b
states
0 0110b: 6; 0 1000b: 8
00h
(4-4-4) Fast Read Number of
Mode Bits
Mode Bits:
000b: Not supported; 010b: 2 bits
23:21
000b
FFh
0Ch
20h
0Fh
52h
10h
D8h
00h
FFh
(4-4-4) Fast Read Opcode
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
53h
31:24
07:00
15:08
23:16
31:24
07:00
15:08
23:16
31:24
FFh
0Ch
20h
0Fh
52h
10h
D8h
00h
FFh
Sector/block size = 2^N bytes (Note5)
0Ch: 4KB; 0Fh: 32KB; 10h: 64KB
Sector Type 1 Size
Sector Type 1 erase Opcode
Sector Type 2 Size
Sector/block size = 2^N bytes
00h: N/A; 0Fh: 32KB; 10h: 64KB
Sector Type 2 erase Opcode
Sector Type 3 Size
Sector/block size = 2^N bytes
00h: N/A; 0Fh: 32KB; 10h: 64KB
Sector Type 3 erase Opcode
Sector Type 4 Size
00h: N/A, This sector type doesn't
exist
Sector Type 4 erase Opcode
P/N: PM2130
Rev. 1.6, October 21, 2016
60
MX25L6433F
Table 16. Parameter Table (1): Macronix Flash Parameter Tables
SFDP Table below is for MX25L6433FM2I-08G, MX25L6433FMI-08G, MX25L6433FZNI-08G, MX25L6433FXCI-
08G, MX25L6433FBBI-08G, MX25L6433FZ2I-08G, MX25L6433FM2I-08Q, MX25L6433FMI-08Q,
MX25L6433FZNI-08Q, MX25L6433FXCI-08Q, MX25L6433FBBI-08Q and MX25L6433FZ2I-08Q
Add (h) DW Add Data (h/b) Data
Description
Comment
2000h=2.000V
2700h=2.700V
3600h=3.600V
(Byte)
(Bit)
(Note1)
(h)
07:00
15:08
00h
36h
00h
36h
Vcc Supply Maximum Voltage
61h:60h
1650h=1.650V, 1750h=1.750V
2250h=2.250V, 2300h=2.300V
2350h=2.350V, 2650h=2.650V
2700h=2.700V
23:16
31:24
50h
26h
50h
26h
Vcc Supply Minimum Voltage
63h:62h
H/W Reset# pin
H/W Hold# pin
0=not support 1=support
0=not support 1=support
0=not support 1=support
0=not support 1=support
00
01
02
03
0b
1b
1b
1b
Deep Power Down Mode
S/W Reset
Reset Enable (66h) should be
issued before Reset Opcode
1001 1001b
S/W Reset Opcode
65h:64h 11:04
F99Eh
(99h)
Program Suspend/Resume
Erase Suspend/Resume
Unused
0=not support 1=support
0=not support 1=support
12
13
14
15
1b
1b
1b
Wrap-Around Read mode
Wrap-Around Read mode Opcode
0=not support 1=support
1b
66h
67h
23:16
77h
77h
64h
08h:support 8B wrap-around read
16h:8B&16B
32h:8B&16B&32B
Wrap-Around Read data length
Individual block lock
31:24
64h
64h:8B&16B&32B&64B
0=not support 1=support
00
01
0b
1b
Individual block lock bit
(Volatile/Nonvolatile)
0=Volatile 1=Nonvolatile
1111 1111b
Individual block lock Opcode
09:02
(FFh)
Individual block lock Volatile
protect bit default protect status
0=protect 1=unprotect
10
1b
CFFEh
6Bh:68h
Secured OTP
Read Lock
Permanent Lock
Unused
0=not support 1=support
0=not support 1=support
0=not support 1=support
11
12
1b
0b
13
0b
15:14
31:16
11b
FFh
FFh
Unused
FFh
FFh
Unused
6Fh:6Ch 31:00
MX25L6433FM2I-08G-SFDP_2016-10-11,SF10
P/N: PM2130
Rev. 1.6, October 21, 2016
61
MX25L6433F
Note 1: h/b is hexadecimal or binary.
Note 2: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x),
address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1),
(2-2-2), and (4-4-4)
Note 3: Wait States is required dummy clock cycles after the address bits or optional mode bits.
Note 4: Mode Bits is optional control bits that follow the address bits. These bits are driven by the system
controller if they are specified. (eg,read performance enhance toggling bits)
Note 5: 4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h
Note 6: All unused and undefined area data is blank FFh for SFDP Tables that are defined in Parameter
Identification Header. All other areas beyond defined SFDP Table are reserved by Macronix.
P/N: PM2130
Rev. 1.6, October 21, 2016
62
MX25L6433F
11. POWER-ON STATE
The device is at the following states after power-up:
- Standby mode
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage until the VCC reaches the following
levels:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal Power-on Reset (POR) circuit may protect the device from data corruption and inadvertent data
change during power up state.
For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is
not guaranteed. The read, write, erase, and program command should be sent after the time delay:
- tVSL after VCC reached VCC minimum level
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is
recommended. (generally around 0.1uF)
P/N: PM2130
Rev. 1.6, October 21, 2016
63
MX25L6433F
12. Electrical Specifications
12-1. Absolute Maximum Ratings
RATING
VALUE
Ambient Operating Temperature
Storage Temperature
Applied Input Voltage
Applied Output Voltage
VCC to Ground Potential
Industrial grade
-40°C to 85°C
-65°C to 150°C
-0.5V to 4.6V
-0.5V to 4.6V
-0.5V to 4.6V
NOTICE:
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device. This is stress rating only and functional operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended period may affect reliability.
2. Specifications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see
the figures below.
Figure 39. Maximum Positive Overshoot Waveform
Figure 38. Maximum Negative Overshoot Waveform
20ns
20ns
20ns
Vss
Vcc + 2.0V
Vss-2.0V
Vcc
20ns
20ns
20ns
12-2. Capacitance TA = 25°C, f = 1.0 MHz
Symbol Parameter
Min.
Typ.
Max.
Unit
pF
Conditions
VIN = 0V
CIN
Input Capacitance
6
8
COUT Output Capacitance
pF
VOUT = 0V
P/N: PM2130
Rev. 1.6, October 21, 2016
64
MX25L6433F
Figure 40. Input Test Waveforms and Measurement Level
Input timing reference level
Output timing reference level
0.8VCC
0.7VCC
0.3VCC
AC
Measurement
Level
0.5VCC
0.2VCC
Note: Input pulse rise and fall time are <2.4ns
Figure 41. Output Loading
DEVICE UNDER
TEST
2.7K ohm
+3.3V
CL
6.2K ohm
DIODES=IN3064
OR EQUIVALENT
CL=30/15pF Including jig capacitance
P/N: PM2130
Rev. 1.6, October 21, 2016
65
MX25L6433F
Table 17. DC Characteristics
Temperature = -40°C to 85°C for Industrial grade, VCC = 2.65V ~ 3.6V
Symbol Parameter
Notes Min.
Typ.
Max.
Units Test Conditions
VCC = VCC Max,
uA
ILI
Input Load Current
Output Leakage Current
1
± 2
VIN = VCC or GND
VCC = VCC Max,
VOUT = VCC or GND
ILO
1
1
± 2
50
20
uA
ISB1 VCC Standby Current
10
3
uA VIN = VCC or GND, CS# = VCC
Deep Power-down
Current
ISB2
uA VIN = VCC or GND, CS# = VCC
fQ=133MHz (4 x I/O read)
mA SCLK=0.1VCC/0.9VCC,
SO=Open
10
17
5
ICC1 VCC Read
1
1
f=50MHz,
mA SCLK=0.1VCC/0.9VCC,
SO=Open
2.5
VCC Program Current
Program in Progress, CS# =
VCC
ICC2
(PP)
10
10
10
10
15
15
15
15
mA
VCC Write Status
ICC3
Program status register in
mA
Register (WRSR) Current
progress, CS#=VCC
VCC Sector Erase
ICC4
1
1
mA Erase in Progress, CS#=VCC
mA Erase in Progress, CS#=VCC
Current (SE)
VCC Chip Erase Current
ICC5
(CE)
VIL
Input Low Voltage
Input High Voltage
-0.5
0.8
V
V
VIH
0.7VCC
VCC+0.4
VOL
Output Low Voltage
0.4
V
V
IOL = 1.6mA
IOH = -100uA
VOH Output High Voltage
VCC-0.2
Notes :
1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and
speeds).
2. Typical value is calculated by simulation.
3. The value guaranteed by characterization, not 100% tested in production.
P/N: PM2130
Rev. 1.6, October 21, 2016
66
MX25L6433F
Table 18. AC Characteristics
Temperature = -40°C to 85°C for Industrial grade, VCC = 2.65V ~ 3.6V
Symbol Alt. Parameter
Min.
Typ. Max. Unit
Clock Frequency for the following instructions:
fSCLK
fC FAST_READ, PP, SE, BE32K, BE, CE, RES, WREN,
D.C.
133 MHz
WRDI, RDID, RDSR, WRSR
fRSCLK
fTSCLK
f4PP
fR Clock Frequency for READ instructions
fT Clock Frequency for 2READ/DREAD instructions
fQ Clock Frequency for 4READ/QREAD instructions
Clock Frequency for 4PP (Quad page program)
Normal Read
50 MHz
133 MHz
133 MHz
133 MHz
9
ns
ns
ns
tCH(1)
tCLH Clock High Time
(fRSCLK)
Others (fSCLK) 45% x (1/fSCLK)
Normal Read
9
tCL(1)
tCLL Clock Low Time
(fRSCLK)
Others (fSCLK) 45% x (1/fSCLK)
ns
V/ns
V/ns
ns
ns
ns
tCLCH (2)
tCHCL(2)
Clock Rise Time (peak to peak)
Clock Fall Time (peak to peak)
0.1
0.1
tSLCH tCSS CS# Active Setup Time (relative to SCLK)
tCHSL CS# Not Active Hold Time (relative to SCLK)
tDVCH tDSU Data In Setup Time
4
4
2
tCHDX
tCHSH
tSHCH
tDH Data In Hold Time
3
4
4
15
ns
ns
ns
ns
CS# Active Hold Time (relative to SCLK)
CS# Not Active Setup Time (relative to SCLK)
Read
tSHSL tCSH CS# Deselect Time
Write/Erase/
Program
50
ns
2.65V-3.6V
3.0V-3.6V
10
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
us
us
us
tSHQZ (2) tDIS Output Disable Time
tHLCH
tCHHH
tHHCH
tCHHL
HOLD# Setup Time (relative to SCLK)
5
5
5
5
HOLD# Hold Time (relative to SCLK)
HOLD Setup Time (relative to SCLK)
HOLD Hold Time (relative to SCLK)
HOLD to Output Low-Z
Loading=30pF
HOLD# to Output High-Z
Loading=30pF
2.65V-3.6V
3.0V-3.6V
2.65V-3.6V
3.0V-3.6V
Loading: 15pF
Loading: 30pF
10
8
10
8
6
8
tHHQX
tHLQZ
tCLQV
tLZ
tHZ
tV
Clock Low to Output Valid
VCC=2.65V~3.6V
tCLQX
tWHSL (3)
tSHWL (3)
tESL (4)
tHO Output Hold Time
Write Protect Setup Time
1
20
100
Write Protect Hold Time
Erase Suspend Latency
Program Suspend Latency
20
20
tPSL (4)
tPRS (5)
tERS (6)
Latency between Program Resume and next Suspend
Latency between Erase Resume and next Suspend
0.3
0.3
100
200
P/N: PM2130
Rev. 1.6, October 21, 2016
67
MX25L6433F
Symbol Alt. Parameter
Min.
20
20
Typ.
Max. Unit
tRCR
tRCP
tRCE
tDP
Recovery Time from Read
Recovery Time from Program
Recovery Time from Erase
CS# High to Deep Power-down Mode
CS# High to Standby Mode without Electronic Signature
Read
us
us
ms
12
10
us
tRES1
100
us
tRES2
tW
tBP
tPP
tSE
tBE32K
tBE
tCE
CS# High to Standby Mode with Electronic Signature Read
Write Status Register Cycle Time
Byte-Program
100
40
50
1.2
200
0.6
1
us
ms
us
ms
ms
s
s
s
ms
10
0.33
25
0.14
0.25
20
Page Program Cycle Time
Sector Erase Cycle Time (4KB)
Block Erase Cycle Time (32KB)
Block Erase Cycle Time (64KB)
Chip Erase Cycle Time
60
1
tWSR
Write Security Register Time
Notes:
1. tCH + tCL must be greater than or equal to 1/ fC.
2. The value guaranteed by characterization, not 100% tested in production.
3. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
4. Latency time is required to complete Erase/Program Suspend operation until WIP bit is "0".
5. For tPRS, minimum timing must be observed before issuing the next program suspend command. However,
a period equal to or longer than the typical timing is required in order for the program operation to make
progress.
6. For tERS, minimum timing must be observed before issuing the next erase suspend command. However, a
period equal to or longer than the typical timing is required in order for the erase operation to make progress.
P/N: PM2130
Rev. 1.6, October 21, 2016
68
MX25L6433F
13. TIMING ANALYSIS
Figure 42. Serial Input Timing
tSHSL
tSHCH
tCHCL
CS#
tCHSL
tSLCH
tCHSH
SCLK
tDVCH
tCHDX
tCLCH
MSB
LSB
SI
High-Z
SO
Figure 43. Output Timing
CS#
tCH
SCLK
tCLQV
tCLQV
tCL
tSHQZ
tCLQX
SO
tCLQX
LSB
ADDR.LSB IN
SI
P/N: PM2130
Rev. 1.6, October 21, 2016
69
MX25L6433F
Figure 44. Hold Timing
CS#
tHLCH
tCHHH
tCHHL
tHLQZ
tHHCH
SCLK
tHHQX
SO
HOLD#
Figure 45. WP# Setup Timing and Hold Timing during WRSR when SRWD=1
WP#
tSHWL
tWHSL
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12
13 14
15
SCLK
01
SI
High-Z
SO
P/N: PM2130
Rev. 1.6, October 21, 2016
70
MX25L6433F
14. OPERATING CONDITIONS
At Device Power-Up and Power-Down
AC timing illustrated in "Figure 46. AC Timing at Device Power-Up" and "Figure 47. Power-Down Sequence"
are for the supply voltages and the control signals at device power-up and power-down. If the timing in the
figures is ignored, the device will not operate correctly.
During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be
selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.
Figure 46. AC Timing at Device Power-Up
VCC(min)
VCC
GND
tVR
tSHSL
CS#
tSHCH
tSLCH
tCHSL
tCHSH
SCLK
tDVCH
tCHCL
tCHDX
tCLCH
MSB IN
LSB IN
SI
High Impedance
SO
Symbol
tVR
Parameter
VCC Rise Time
Notes
Min.
Max.
500000
Unit
us/V
1
Notes :
1. Sampled, not 100% tested.
2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer
to "Table 18. AC Characteristics".
P/N: PM2130
Rev. 1.6, October 21, 2016
71
MX25L6433F
Figure 47. Power-Down Sequence
During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.
VCC
CS#
SCLK
Figure 48. Power-up Timing
V
CC
V
(max)
CC
Chip Selection is Not Allowed
V
(min)
CC
Device is fully accessible
tVSL
V
WI
time
P/N: PM2130
Rev. 1.6, October 21, 2016
72
MX25L6433F
Figure 49. Power Up/Down and Voltage Drop
For Power-down to Power-up operation, the VCC of flash device must below VPWD for at least tPWD timing.
Please check the table below for more detail.
VCC
VCC (max.)
Chip Select is not allowed
VCC (min.)
tVSL
Full Device
Access
Allowed
(max.)
V
PWD
tPWD
Time
Table 19. Power-Up/Down Voltage and Timing
Symbol Parameter
Min.
Max.
Unit
us
V
tVSL
VWI
VPWD
VCC(min.) to device operation
Write Inhibit Voltage
800
1.5
2.5
0.9
VCC voltage needed to below VPWD for ensuring initialization will occur
V
tPWD The minimum duration for ensuring initialization will occur
VCC VCCPower Supply
300
us
V
2.65
3.6
Note: These parameters are characterized only.
14-1. Initial Delivery State
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status
Register contains 00h (all Status Register bits are 0).
P/N: PM2130
Rev. 1.6, October 21, 2016
73
MX25L6433F
15. ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ.(1)
Max.(2)
40
Unit
ms
ms
s
Write Status Register Cycle Time
Sector Erase Time (4KB)
Block Erase Time (64KB)
Block Erase Time (32KB)
Chip Erase Time
25
0.25
0.14
20
200
1
0.6
60
s
s
Byte Program Time (via page program command)
Page Program Time
10
50
us
0.33
100,000
1.2
ms
cycles
Erase/Program Cycle
Notes:
1. Typical program and erase time assumes the following conditions: 25°C, 3.3V, and checkerboard pattern.
2. Under worst conditions of 85°C and 2.65V.
3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming
command.
16. DATA RETENTION
Parameter
Condition
Min.
Max.
Unit
Data retention
55˚C
20
years
17. LATCH-UP CHARACTERISTICS
Min.
Max.
Input Voltage with respect to GND on all power pins, SI, CS#
Input Voltage with respect to GND on SO
Current
-1.0V
-1.0V
-100mA
2 VCCmax
VCC + 1.0V
+100mA
Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.
P/N: PM2130
Rev. 1.6, October 21, 2016
74
MX25L6433F
18. ORDERING INFORMATION
Please contact Macronix regional sales for the latest product selection and available form factors.
PART NO.
CLOCK (MHz)
TEMPERATURE
PACKAGE
Remark
8-SOP
(200mil)
16-SOP
(300mil)
8-WSON
(8x6mm)
8-WSON
(6x5mm)
24-TFBGA
(6x8mm)
MX25L6433FM2I-08G
133
-40°C to 85°C
MX25L6433FMI-08G
MX25L6433FZ2I-08G
MX25L6433FZNI-08G
MX25L6433FXCI-08G
MX25L6433FBBI-08G
MX25L6433FM2I-08Q
MX25L6433FMI-08Q
MX25L6433FZNI-08Q
133
133
133
133
133
133
133
133
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40 C to 85 C
WLCSP
°
°
8-SOP
(200mil)
16-SOP
(300mil)
8-WSON
(6x5mm)
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
P/N: PM2130
Rev. 1.6, October 21, 2016
75
MX25L6433F
19. PART NAME DESCRIPTION
MX
M2
08
25
L
6433F
I
G
OPTION:
G/Q: RoHS Compliant & Halogen-free
Manufacturing Location
SPEED:
08: 133MHz
TEMPERATURE RANGE:
I: Industrial (-40° C to 85° C)
PACKAGE:
M2: 200mil 8-SOP
M: 300mil 16-SOP
ZN: 6x5mm 8-WSON
Z2: 8x6mm 8-WSON
XC: 6x8mm 24-TFBGA
BB: WLCSP
DENSITY & MODE:
6433F: 64Mb standard type
TYPE:
L: 3V
DEVICE:
25: Serial NOR Flash
P/N: PM2130
Rev. 1.6, October 21, 2016
76
MX25L6433F
20. PACKAGE INFORMATION
20-1.
8-pin SOP (200mil)
P/N: PM2130
Rev. 1.6, October 21, 2016
77
MX25L6433F
20-2.
16-pin SOP (300mil)
P/N: PM2130
Rev. 1.6, October 21, 2016
78
MX25L6433F
20-3.
8-WSON (8x6mm)
P/N: PM2130
Rev. 1.6, October 21, 2016
79
MX25L6433F
20-4.
8-WSON (6x5mm)
P/N: PM2130
Rev. 1.6, October 21, 2016
80
MX25L6433F
20-5.
24 ball TFBGA (6x8mm)
P/N: PM2130
Rev. 1.6, October 21, 2016
81
MX25L6433F
21. REVISION HISTORY
Revision No. Description
Page
Date
1.0
1. Removed document status "ADVANCED INFORMATION"
All
OCT/27/2014
2. Revised AC value: tRCR (min) = 20us.
P65
3. Modified ordering information descriptions.
1. Added command ENSO, EXSO, and WRSCUR.
P5,7,72-73,79
P13,16,19,
50-51
1.1
NOV/21/2014
2. Added content of Additional 8K-bit bit security OTP.
3. Updated suspend/resume descriptions.
4. Modified tCH/tCL formula.
P4,11,52,59-62
P54-56,69
P68
5. Removed 8-WSON (8x6mm) package.
P5,7,76,77
P76
P76
P8
P54
6. Updated the ordering information of MX25L6433FZNI-08G.
1. Updated the ordering information of MX25L6433FMI-08G.
2. Modified BLOCK DIAGRAM.
1.2
1.3
1.4
DEC/31/2014
MAR/17/2015
MAR/10/2016
"Table 12. Acceptable Commands During Program/Erase Suspend after tPSL/tESL".
3. Modified
1. Updated the ordering information of MX25L6433FXCI-08G
2. Added VCC range on the DC and AC characteristics
table titles.
1. Modified SRWD bit and QE bit descriptions.
2. Added MX25L6433FZ2I-08G.
P76
P67-68
P23
P5,7,75-76,79
3. Added a statement for product ordering information.
4. Modified Performance Enhance Mode Reset descriptions.
5. Modified Deep Power-down (DP) descriptions.
6. Modified REMS descriptions.
P75
P35
P45
P48
1.5
1. Added 08Q part names of 8-SOP,16-SOP,6x5mm 8-WSON
2. Updated tVR values.
3. Updated 8-WSON (8x6mm) package outline
P75,76
P71,73
P79
P36,41
P76
OCT/11/2016
OCT/21/2016
4.
Description modifications.
1.6
1. Updated "19. PART NAME DESCRIPTION".
P/N: PM2130
Rev. 1.6, October 21, 2016
82
MX25L6433F
Except for customized products which has been expressly identified in the applicable agreement, Macronix's
products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or
household applications only, and not for use in any applications which may, directly or indirectly, cause death,
personal injury, or severe property damages. In the event Macronix products are used in contradicted to their
target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its
actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or
distributors shall be released from any and all liability arisen therefrom.
Copyright© Macronix International Co., Ltd. 2014~2016. All rights reserved, including the trademarks and
tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit,
NBiit, Macronix NBit, eLiteFlash, HybridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC,
Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich Audio, Rich Book, Rich TV, and FitCAM. The names
and brands of third party referred thereto (if any) are for identification purposes only.
For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
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