MX25L6439EM2I10G [Macronix]
64M-BIT [x 1 / x 4] CMOS MXSMIO® (SERIAL MULTI I/O) FLASH MEMORY;
| 型号： | MX25L6439EM2I10G |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | 64M-BIT [x 1 / x 4] CMOS MXSMIO® (SERIAL MULTI I/O) FLASH MEMORY |
| 文件： | 总90页 (文件大小：1102K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MX25L6439E
MX25L6439E
HIGH PERFORMANCE
SERIAL FLASH SPECIFICATION
P/N: PM1842
REV. 1.2, NOV. 06, 2013
1
MX25L6439E
Contents
1. FEATURES ........................................................................................................................................................ 4
2. GENERAL DESCRIPTION ............................................................................................................................... 6
Table 1. Additional Features ..................................................................................................................6
3. PIN CONFIGURATION ...................................................................................................................................... 7
4. PIN DESCRIPTION............................................................................................................................................ 7
5. BLOCK DIAGRAM............................................................................................................................................. 8
6. DATA PROTECTION.......................................................................................................................................... 9
Table 2. Protected Area Sizes..............................................................................................................10
Table 3. 4K-bit Secured OTP Definition ...............................................................................................11
7. MEMORY ORGANIZATION............................................................................................................................. 12
Table 4. Memory Organization .............................................................................................................12
8. DEVICE OPERATION...................................................................................................................................... 13
9. HOLD FEATURE.............................................................................................................................................. 14
10. Quad Peripheral Interface (QPI) Read Mode.............................................................................................. 15
10-1. Enable QPI mode ................................................................................................................................15
10-2. Reset QPI mode ..................................................................................................................................15
10-3. Fast QPI Read mode (FASTRDQ).......................................................................................................16
11. COMMAND DESCRIPTION........................................................................................................................... 17
Table 5. Command Sets.......................................................................................................................17
11-1. Write Enable (WREN)..........................................................................................................................20
11-2. Write Disable (WRDI)...........................................................................................................................21
11-3. Read Identification (RDID)...................................................................................................................22
11-4. Read Status Register (RDSR).............................................................................................................23
11-5. Write Status Register (WRSR).............................................................................................................26
Table 6. Protection Modes....................................................................................................................27
11-6. Read Data Bytes (READ) ....................................................................................................................29
11-7. Read Data Bytes at Higher Speed (FAST_READ) ..............................................................................30
11-8. Quad Read Mode (QREAD) ................................................................................................................31
11-9. 4 x I/O Read Mode (4READ) ...............................................................................................................32
11-10. Performance Enhance Mode...............................................................................................................34
11-11. Performance Enhance Mode Reset.....................................................................................................36
11-12. Burst Read...........................................................................................................................................37
11-13. Sector Erase (SE)................................................................................................................................38
11-14. Block Erase (BE) .................................................................................................................................39
11-15. Block Erase (BE32K)...........................................................................................................................40
11-16. Chip Erase (CE)...................................................................................................................................41
11-17. Page Program (PP) .............................................................................................................................42
11-18. 4 x I/O Page Program (4PP)................................................................................................................43
11-19. Continuous Program mode (CP mode)................................................................................................46
11-20. Deep Power-down (DP).......................................................................................................................48
11-21. Release from Deep Power-down (RDP), Read Electronic Signature (RES) .......................................49
11-22. Read Electronic Signature (RES) ........................................................................................................50
11-23. QPI ID Read (QPIID) ...........................................................................................................................51
Table 7. ID Definitions .........................................................................................................................51
11-24. Enter Secured OTP (ENSO)................................................................................................................51
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MX25L6439E
11-25. Exit Secured OTP (EXSO)...................................................................................................................51
11-26. Read Security Register (RDSCUR).....................................................................................................52
Table 8. Security Register Definition ....................................................................................................53
11-27. Write Security Register (WRSCUR).....................................................................................................54
11-28. Write Protection Selection (WPSEL)....................................................................................................54
11-29. Single Block Lock/Unlock Protection (SBLK/SBULK)..........................................................................58
11-30. Read Block Lock Status (RDBLOCK)..................................................................................................61
11-31. Gang Block Lock/Unlock (GBLK/GBULK) ...........................................................................................62
11-32. Program/ Erase Suspend/ Resume.....................................................................................................63
11-33. Erase Suspend ....................................................................................................................................63
11-34. Program Suspend................................................................................................................................64
11-35. Write-Resume......................................................................................................................................65
11-36. No Operation (NOP) ............................................................................................................................66
11-37. Software Reset (Reset-Enable (RSTEN) and Reset (RST)) ...............................................................66
11-38. Reset Quad I/O (RSTQIO)...................................................................................................................66
11-39. Read SFDP Mode (RDSFDP)..............................................................................................................67
Table 9. Signature and Parameter Identification Data Values .............................................................68
Table 10. Parameter Table (0): JEDEC Flash Parameter Tables.........................................................69
Table 11. Parameter Table (1): Macronix Flash Parameter Tables.......................................................71
12. POWER-ON STATE....................................................................................................................................... 73
13. ELECTRICAL SPECIFICATIONS.................................................................................................................. 74
13-1. ABSOLUTE MAXIMUM RATINGS.......................................................................................................74
13-2. CAPACITANCE TA = 25°C, f = 1.0 MHz..............................................................................................74
Table 12. DC CHARACTERISTICS .....................................................................................................76
Table 13. AC CHARACTERISTICS......................................................................................................77
14. TIMING ANALYSIS ........................................................................................................................................ 79
Table 14. Power-Up Timing .................................................................................................................81
14-1. INITIAL DELIVERY STATE..................................................................................................................81
15. OPERATING CONDITIONS........................................................................................................................... 82
16. ERASE AND PROGRAMMING PERFORMANCE........................................................................................ 84
17. DATA RETENTION ........................................................................................................................................ 84
18. LATCH-UP CHARACTERISTICS.................................................................................................................. 84
19. ORDERING INFORMATION.......................................................................................................................... 85
20. PART NAME DESCRIPTION......................................................................................................................... 86
21. PACKAGE INFORMATION............................................................................................................................ 87
22. REVISION HISTORY ..................................................................................................................................... 89
P/N: PM1842
REV. 1.2, NOV. 06, 2013
3
MX25L6439E
64M-BIT [x 1 / x 4] CMOS MXSMIO® (SERIAL MULTI I/O) FLASH MEMORY
1. FEATURES
GENERAL
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• 67,108,864 x 1 bit structure or 16,777,216 x 4 bits (four I/O mode) structure
• 2048 Equal Sectors with 4K bytes each
- Any Sector can be erased individually
• 256 Equal Blocks with 32K bytes each
- Any Block can be erased individually
• 128 Equal Blocks with 64K bytes each
- Any Block can be erased individually
• Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
VCC = 2.7~3.6V
- Normal read
- 50MHz
- Fast read
- 1 I/O: 104MHz with 8 dummy cycles
- 4 I/O: Up to 104MHz
- Configurable dummy cycle number for 4 I/O read operation
- Fast read (QPI Mode)
- 4 I/O: 54MHz with 4 dummy cycles
- 4 I/O: 86MHz with 6 dummy cycles
- 4 I/O: 104MHz with 8 dummy cycles
- Fast program time: 0.7ms(typ.) and 3ms(max.)/page (256-byte per page)
- Byte program time: 12us (typical)
- 8/16/32/64 byte Wrap-Around Burst Read Mode
- Fast erase time: 30ms (typ.)/sector (4K-byte per sector) ; 0.25s(typ.) /block (64K-byte per block); 20s(typ.) /
chip
• Low Power Consumption
- Low active read current: 19mA(max.) at 104MHz, 10mA(max.) at 33MHz
- Low active programming current: 15mA (typ.)
- Low active sector erase current: 10mA (typ.)
- Low standby current: 15uA (typ.)
- Deep Power-down current: 1uA (typ.)
• Typical 100,000 erase/program cycles
• 20 years data retention
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REV. 1.2, NOV. 06, 2013
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MX25L6439E
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- BP0-BP3 block group protect
- Flexible individual block protect when OTP WPSEL=1
- Additional 4K bits secured OTP for unique identifier
• Auto Erase and Auto Program Algorithms
Automatically erases and verifies data at selected sector
-
-
Automatically programs and verifies data at selected page by an internal algorithm that automatically times
the program pulse width (Any page to be programmed should have page in the erased state first.)
• Status Register Feature
• Command Reset
• Program/Erase Suspend
• Program/Erase Resume
• Electronic Identification
JEDEC 1-byte Manufacturer ID and 2-byte Device ID
- RES command for 1-byte Device ID
-
• Support Serial Flash Discoverable Parameters (SFDP) mode
HARDWARE FEATURES
• SCLK Input
Serial clock input
• SI/SIO0
-
Serial Data Input or Serial Data Input/Output for 4 x I/O mode
• SO/SIO1
-
Serial Data Output or Serial Data Input/Output for 4 x I/O mode
• WP#/SIO2
-
Hardware write protection or serial data Input/Output for 4 x I/O mode
• HOLD#/SIO3
-
To pause the device without deselecting the device or serial data Input/Output for 4 x I/O mode
• PACKAGE
-
8-pin SOP (200mil)
-
-
-
8-pin VSOP (200mil)
All devices are RoHS Compliant and Halogen-free
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REV. 1.2, NOV. 06, 2013
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MX25L6439E
2. GENERAL DESCRIPTION
MX25L6439E is 64Mb bits serial Flash memory, which is configured as 8,388,608 x 8 internally. When it is in
four I/O mode, the structure becomes 16,777,216 bits x 4. MX25L6439E feature a serial peripheral interface and
software protocol allowing operation on a simple 3-wire bus while it is in single I/O mode. The three bus signals
are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is
enabled by CS# input.
MX25L6439E, MXSMIO® (Serial Multi I/O) flash memory, provides sequential read operation on whole chip and
multi-I/O features.
When it is in quad I/O mode, the SI pin, SO pin, WP# pin and HOLD# pin become SIO0 pin, SIO1 pin, SIO2 pin
and SIO3 pin for address/dummy bits input and data Input/Output.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the
specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis, and erase command is executed on sector (4K-byte), block (32K-byte/64K-byte), or whole chip ba-
sis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status
read command can be issued to detect completion status of a program or erase operation via WIP bit.
When the device is not in operation and CS# is high, it is put in standby mode.
The MX25L6439E utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after
100,000 program and erase cycles.
Table 1. Additional Features
Numbers of Dummy Cycles
4 I/O
86*
6
8
104
Note: *means default status
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REV. 1.2, NOV. 06, 2013
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MX25L6439E
3. PIN CONFIGURATION
8-PIN SOP (200mil)
4. PIN DESCRIPTION
SYMBOL
DESCRIPTION
CS#
Chip Select
Serial Data Input (for 1xI/O)/ Serial Data
Input & Output (for 4xI/O mode)
Serial Data Output (for 1xI/O)/Serial
Data Input & Output (for 4xI/O mode)
Clock Input
1
2
3
4
CS#
SO/SIO1
WP#/SIO2
GND
VCC
8
7
6
5
SI/SIO0
HOLD#/SIO3
SCLK
SI/SIO0
SO/SIO1
SCLK
Write protection or Serial Data Input &
Output (for 4xI/O mode)
WP#/SIO2
8-PIN VSOP (200mil)
To pause the device without deselecting
the device or Serial data Input/Output
for 4 x I/O mode
HOLD#/
SIO3
1
2
3
4
CS#
SO/SIO1
WP#/SIO2
GND
VCC
8
7
6
5
HOLD#/SIO3
VCC
GND
+ 3.0V Power Supply
Ground
SCLK
SI/SIO0
Note:
1. The HOLD# pin is internal pull high.
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REV. 1.2, NOV. 06, 2013
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MX25L6439E
5. BLOCK DIAGRAM
Address
Generator
Memory Array
Page Buffer
Y-Decoder
Data
Register
SI/SIO0
SRAM
Buffer
Sense
Amplifier
CS#
WP#/SIO2
HOLD#/SIO3
Mode
Logic
State
Machine
HV
Generator
SCLK
Clock Generator
Output
Buffer
SO/SIO1
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MX25L6439E
6. DATA PROTECTION
During power transition, there may be some false system level signals which result in inadvertent erasure or pro-
gramming. The device is designed to protect itself from these accidental write cycles.
The state machine will be reset as standby mode automatically during power up. In addition, the control register
architecture of the device constrains that the memory contents can only be changed after specific command se-
quences have completed successfully.
In the following, there are several features to protect the system from the accidental write cycles during VCC
power-up and power-down or from system noise.
• Valid command length checking: The command length will be checked whether it is at byte base and complet-
ed on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other command to change data. The WEL bit will return to reset stage under following situation:
- Power-up
- WRDI command completion
- WRSR command completion
- PP command completion
- 4PP command completion
- SE command completion
- BE32K command completion
- BE command completion
- CE command completion
- PGM/ERS Suspend command completion
- Softreset command completion
- WRSCUR command completion
- WPSEL command completion
- SBLK command completion
- SBULK command completion
- GBLK command completion
- GBULK command completion
• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from
writing all commands except Release from Deep Power Down mode command (RDP) and Read Electronic
Signature command (RES).
I. Block lock protection
- The Software Protected Mode (SPM) uses (TB, BP3, BP2, BP1, BP0) bits to allow part of memory to be
protected as read only. The protected area definition is shown as table of "Table 2. Protected Area Sizes", the
protected areas are more flexible which may protect various areas by setting value of TB, BP0-BP3 bits.
- The Hardware Protected Mode (HPM) uses WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and SRWD
bit. If the system goes into four I/O or QPI mode, the feature of HPM will be disabled.
- MX25L6439E provides individual block (or sector) write protect & unprotect. User may enter the mode with
WPSEL command and conduct individual block (or sector) write protect with SBLK instruction, or SBULK for
individual block (or sector) unprotect. Under the mode, user may conduct whole chip (all blocks) protect with
GBLK instruction and unlock the whole chip with GBULK instruction.
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REV. 1.2, NOV. 06, 2013
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MX25L6439E
Table 2. Protected Area Sizes
Protected Area Sizes (TB bit = 0)
Status bit
Protect Level
64Mb
BP3
0
BP2
0
BP1
0
BP0
0
0 (none)
0
0
0
1
1 (1block, block 127th)
0
0
1
0
2 (2blocks, block 126th-127th)
3 (4blocks, block 124th-127th)
4 (8blocks, block 120th-127th)
5 (16blocks, block 112th-127th)
6 (32blocks, block 96th-127th)
7 (64blocks, block 64th-127th)
8 (128blocks, protect all)
9 (128blocks, protect all)
10 (128blocks, protect all)
11 (128blocks, protect all)
12 (128blocks, protect all)
13 (128blocks, protect all)
14 (128blocks, protect all)
15 (128blocks, protect all)
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Protected Area Sizes (TB bit = 1)
Status bit
Protect Level
64Mb
BP3
0
BP2
0
BP1
0
BP0
0
0 (none)
0
0
0
1
1 (1block, block 0th)
0
0
1
0
2 (2blocks, block 0th-1st)
3 (4blocks, block 0th-3rd)
4 (8blocks, block 0th-7th)
5 (16blocks, block 0th-15th)
6 (32blocks, block 0th-31st)
7 (64blocks, block 0th-63rd)
8 (128blocks, protect all)
9 (128blocks, protect all)
10 (128blocks, protect all)
11 (128blocks, protect all)
12 (128blocks, protect all)
13 (128blocks, protect all)
14 (128blocks, protect all)
15 (128blocks, protect all)
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Note: The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP3, BP2, BP1,
BP0) are 0.
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REV. 1.2, NOV. 06, 2013
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MX25L6439E
II. Additional 4K-bit secured OTP for unique identifier: to provide 4K-bit One-Time Program area for setting
device unique serial number - Which may be set by factory or system maker.
- Security register bit 0 indicates whether the chip is locked by factory or not.
- To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with ENSO command), and
going through normal program procedure, and then exiting 4K-bit secured OTP mode by writing EXSO com-
mand.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register)
command to set customer lock-down bit1 as "1". Please refer to table of "Table 8. Security Register Defini-
tion" for security register bit definition and table of "Table 3. 4K-bit Secured OTP Definition" for address range
definition.
Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit Secured
OTP mode, array access is not allowed.
Table 3. 4K-bit Secured OTP Definition
Address range
xxx000~xxx00F
xxx010~xxx1FF
Size
Standard Factory Lock
ESN (electrical serial number)
N/A
Customer Lock
128-bit
3968-bit
Determined by customer
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MX25L6439E
7. MEMORY ORGANIZATION
Table 4. Memory Organization
Block(64K-byte) Block(32K-byte) Sector (4K-byte)
Address Range
2047
7FF000h
7FFFFFh
255
individual 16 sectors
lock/unlock unit:4K-byte
2040
2039
7F8000h
7F7000h
7F8FFFh
7F7FFFh
127
254
253
252
251
250
2032
2031
7F0000h
7EF000h
7F0FFFh
7EFFFFh
2024
2023
7E8000h
7E7000h
7E8FFFh
7E7FFFh
126
individual block
lock/unlock unit:64K-byte
2016
2015
7E0000h
7DF000h
7E0FFFh
7DFFFFh
2008
2007
7D8000h
7D7000h
7D8FFFh
7D7FFFh
125
2000
7D0000h
7D0FFFh
individual block
lock/unlock unit:64K-byte
47
02F000h
02FFFFh
5
4
3
2
1
0
40
39
028000h
027000h
028FFFh
027FFFh
2
1
individual block
lock/unlock unit:64K-byte
32
31
020000h
01F000h
020FFFh
01FFFFh
24
23
018000h
017000h
018FFFh
017FFFh
16
15
010000h
00F000h
010FFFh
00FFFFh
8
7
008000h
007000h
008FFFh
007FFFh
individual 16 sectors
lock/unlock unit:4K-byte
0
0
000000h
000FFFh
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MX25L6439E
8. DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended op-
eration.
2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby
mode until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z.
3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until
next CS# rising edge.
4. For standard single data rate serial mode, input data is latched on the rising edge of Serial Clock(SCLK) and
data shifts out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as "Figure 1.
Serial Modes Supported (for Normal Serial mode)".
5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, RDSFDP, W4READ, 4READ,
QREAD, RDBLOCK, RES, and QPIID, the shifted-in instruction sequence is followed by a data-out sequence.
After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI,
WRSR, SE, BE, BE32K, CE, PP, 4PP, WPSEL, SBLK, SBULK, GBLK, GBULK, Suspend, Resume, NOP,
RSTEN, RST, EQIO, RSTQIO, ENSO, EXSO, WRSCUR, the CS# must go high exactly at the byte boundary;
otherwise, the instruction will be rejected and not executed.
6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is ne-
glected and not affect the current operation of Write Status Register, Program, Erase.
Figure 1. Serial Modes Supported (for Normal Serial mode)
CPOL CPHA
shift in
shift out
SCLK
SCLK
(Serial mode 0)
(Serial mode 3)
0
1
0
1
SI
MSB
SO
MSB
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while
not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial
mode is supported.
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9. HOLD FEATURE
HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop
the operation of write status register, programming, or erasing in progress.
The operation of HOLD requires Chip Select (CS#) keeping low and starts on falling edge of HOLD# pin signal
while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not
start until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while
Serial Clock(SCLK) signal is being low( if Serial Clock signal is not being low, HOLD operation will not end until
Serial Clock being low).
Figure 2. Hold Condition Operation
CS#
SCLK
HOLD#
Hold
Hold
Condition
(standard)
Condition
(non-standard)
The Serial Data Output (SO) is high impedance, both Serial Data Input (SI) and Serial Clock (SCLK) are don't
care during the HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal
logic of the device. To re-start communication with chip, the HOLD# must be at high and CS# must be at low.
Note: The HOLD feature is disabled during Quad I/O mode.
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10. Quad Peripheral Interface (QPI) Read Mode
QPI protocol enables user to take full advantage of Quad I/O Serial Flash by providing the Quad I/O interface in
command cycles, address cycles and as well as data output cycles.
10-1. Enable QPI mode
By issuing 35H command, the QPI mode is enable.
Figure 3. Enable QPI Sequence (Command 35H)
CS#
MODE 3
MODE 0
2
3
4
5
6
7
0
1
SCLK
SIO0
35
SIO[3:1]
10-2. Reset QPI mode
By issuing F5H command, the device is reset to 1-I/O SPI mode.
Figure 4. Reset QPI Mode (Command F5H)
CE#
SCLK
SIO[3:0]
F5
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10-3. Fast QPI Read mode (FASTRDQ)
To increase the code transmission speed, the device provides a "Fast QPI Read Mode" (FASTRDQ). By issuing
command code EBH, the FASTRDQ mode is enable. The number of dummy cycle increase from 4 to 6 cycles.
The read cycle frequency will increase from 54MHz to 86MHz.
Figure 5. Fast QPI Read Mode (FASTRDQ) (Command EBH)
CS#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MODE 3
MODE 0
MODE 3
MODE 0
SCLK
EB
SIO[3:0]
H0 L0 H1 L1 H2 L2 H3 L3
A5 A4 A3 A2 A1 A0
X
X
X
X
X
X
MSB
Data Out
24-bit Address
(Note)
Data In
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11. COMMAND DESCRIPTION
Table 5. Command Sets
Read Commands
I/O
1
1
4
4
4
4
4
Read Mode
SPI
SPI
SPI
SPI
SPI
QPI
QPI
FAST READ
(fast read
data)
0B (hex)
ADD1(8)
ADD2(8)
ADD3(8)
Dummy(8)
4READ
QREAD
(1I/4O read
command)
6B (hex)
ADD1(8)
ADD2(8)
ADD3(8)
Dummy(8)
FAST READ
(fast read
data)
4READ
READ
(normal read)
Command
W4READ
(4 x I/O read
command)
EB (hex)
ADD1(2)
ADD2(2)
ADD3(2)
Dummy*
Quad I/O
read with
configurable
dummy cycles
(4 x I/O read
command)
EB (hex)
ADD1(2)
ADD2(2)
ADD3(2)
Dummy*
Quad I/O
read with
configurable
dummy cycles
1st byte
2nd byte
3rd byte
4th byte
5th byte
03 (hex)
ADD1(8)
ADD2(8)
ADD3(8)
E7 (hex)
ADD1(2)
ADD2(2)
ADD3(2)
Dummy(4)
0B (hex)
ADD1(2)
ADD2(2)
ADD3(2)
Dummy(4)
n bytes read
out until CS#
goes high
n bytes read n bytes read Quad I/O read
out until CS# out until CS# with 4 dummy
goes high
goes high
cycles
Action
Note: *Dummy cycle number will be different, depending on the bit7 (DC) setting of Configuration Register.
Please refer to "Configuration Register" Table.
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MX25L6439E
Other Commands
WRSR*
(write status/
configuration page program) (sector erase)
register)
RDCR* (read
configuration
register)
WREN*
WRDI *
RDSR * (read
4PP (quad
SE *
Command
(write enable) (write disable) status register)
1st byte
2nd byte
3rd byte
4th byte
06 (hex)
04 (hex)
05 (hex)
15 (hex)
01 (hex)
Values
Values
38 (hex)
ADD1
ADD2
ADD3
20 (hex)
ADD1
ADD2
ADD3
sets the (WEL) resets the to read out the to read out the to write new quad input to to erase the
write enable
latch bit
(WEL) write values of the values of the values of the program the
enable latch status register configuration configuration/ selected page
selected
sector
Action
bit
register
status register
PGM/ERS
RDP (Release Suspend *
BE 32K * (block BE * (block
erase 32KB) erase 64KB)
CE * (chip
erase)
PP * (page
program)
DP (Deep
power down)
Command
from deep
(Suspends
Program/
Erase)
power down)
1st byte
2nd byte
3rd byte
4th byte
52 (hex)
ADD1
ADD2
D8 (hex)
ADD1
ADD2
60 or C7 (hex)
02 (hex)
ADD1
ADD2
ADD3
B9 (hex)
AB (hex)
75 (hex)
ADD3
ADD3
to erase the
to erase the to erase whole to program the enters deep release from program/erase
selected 32KB selected 64KB
chip
selected page power down
mode
deep power
down mode
operation is
interrupted
by suspend
command
block
block
Action
PGM/ERS
Resume *
(Resumes (read identific-
Program/
Erase)
RDID
RES * (read ENSO * (enter
electronic ID) secured OTP)
Command
ation)
1st byte
2nd byte
3rd byte
4th byte
7A (hex)
9F (hex)
AB (hex)
B1 (hex)
x
x
x
to continue
performing the
suspended
outputs
JEDEC
ID: 1-byte
to read out
1-byte Device 4K-bit secured
ID OTP mode
to enter the
program/erase Manufacturer
Action
sequence
ID & 2-byte
Device ID
P/N: PM1842
REV. 1.2, NOV. 06, 2013
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MX25L6439E
RDSCUR *
(read security (write security
WRSCUR *
SBULK *
(single block (block protect
unlock)
39 (hex)
ADD1
RDBLOCK *
Command
(byte)
EXSO * (exit
secured OTP)
SBLK * (single
block lock
GBLK * (gang
block lock)
register)
2B (hex)
register)
2F (hex)
read)
3C (hex)
ADD1
ADD2
ADD3
1st byte
2nd byte
3rd byte
4th byte
C1 (hex)
36 (hex)
ADD1
ADD2
7E (hex)
ADD2
ADD3
ADD3
to exit the
4K-bit secured of security
OTP mode register
to read value to set the lock-
down bit as
individual
block
individual
block
(64K-byte)
or sector
(4K-byte)
unprotect
read individual whole chip
block or sector write protect
write protect
"1" (once lock- (64K-byte)
down, cannot or sector
be update) (4K-byte) write
protect
Action
status
RST *
RSTEN *
EQIO
RSTQIO
QPIID
COMMAND GBULK * (gang NOP * (No
(Reset
(Enable Quad (Reset Quad
(byte)
block unlock)
Operation) (Reset Enable)
(QPI ID Read)
Memory)
I/O)
I/O)
1st byte
2nd byte
3rd byte
4th byte
Action
98 (hex)
00 (hex)
66 (hex)
99 (hex)
35 (hex)
F5 (hex)
AF (hex)
whole chip
unprotect
Entering the Exiting the QPI
QPI mode mode
ID in QPI
interface
SBL *
(Set Burst
Length)
77 (hex)
Value
WPSEL *
(Write Protect
Selection)
68 (hex)
COMMAND
(byte)
RDSFDP *
1st byte
2nd byte
3rd byte
4th byte
5th byte
Action
5A (hex)
ADD1(8)
ADD2(8)
ADD3(8)
Dummy(8)
n bytes read
out until CS#
goes high
to set Burst
length
to enter
and enable
individal block
protect mode
Note 1: Command set highlighted with (*) are supported both in SPI and QPI mode.
Note 2: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the
hidden mode.
Note 3: Before executing RST command, RSTEN command must be executed. If there is any other command to interfere,
the reset operation will be disabled.
P/N: PM1842
REV. 1.2, NOV. 06, 2013
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MX25L6439E
11-1. Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP,
4PP, CP, SE, BE, BE32K, CE, WRSR, SBLK, SBULK, GBLK and GBULK, which are intended to change the de-
vice content, should be set every time after the WREN instruction setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→ CS# goes
high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
in SPI mode.
Figure 6. Write Enable (WREN) Sequence (Command 06) (SPI Mode)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
06h
SI
High-Z
SO
Figure 7. Write Enable (WREN) Sequence (Command 06) (QPI Mode)
CS#
0
1
SCLK
Command
SIO[3:0]
06h
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REV. 1.2, NOV. 06, 2013
20
MX25L6439E
11-2. Write Disable (WRDI)
The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.
The sequence of issuing WRDI instruction is: CS# goes low→ sending WRDI instruction code→ CS# goes high.
The WEL bit is reset by following situations:
- Power-up
- WRDI command completion
- WRSR command completion
- PP command completion
- 4PP command completion
- SE command completion
- BE32K command completion
- BE command completion
- CE command completion
- PGM/ERS Suspend command completion
- Softreset command completion
- WRSCUR command completion
- WPSEL command completion
- SBLK command completion
- SBULK command completion
- GBLK command completion
- GBULK command completion
Figure 8. Write Disable (WRDI) Sequence (Command 04) (SPI Mode)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
04h
SI
High-Z
SO
Figure 9. Write Disable (WRDI) Sequence (Command 04) (QPI Mode)
CS#
0
1
SCLK
Command
SIO[3:0]
04h
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REV. 1.2, NOV. 06, 2013
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MX25L6439E
11-3. Read Identification (RDID)
The RDID instruction is for reading the Manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Ma-
cronix Manufacturer ID is C2(hex), the memory type ID is 25(hex) as the first-byte Device ID, and the individual
Device ID of second-byte ID are listed as table of "Table 7. ID Definitions".
The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code → 24-bits ID data
out on SO→ to end RDID operation can use CS# to high at any time during data out.
While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the
cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby
stage.
Figure 10. Read Identification (RDID) Sequence (Command 9F) (SPI mode only)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
28 29 30 31
SCLK
SI
Command
9Fh
Manufacturer Identification
Device Identification
High-Z
SO
7
6
5
3
2
1
0
15 14 13
MSB
3
2
1
0
MSB
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MX25L6439E
11-4. Read Status Register (RDSR)
The RDSR instruction is for reading Status Register. The Read Status Register can be read at any time (even
in program/erase/write status register condition) and continuously. It is recommended to check the Write in
Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is
in progress.
The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register
data out on SO.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
Figure 11. Read Status Register (RDSR) Sequence (Command 05) (SPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI
command
05h
Status Register Out
Status Register Out
High-Z
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
Figure 12. Read Status Register (RDSR) Sequence (Command 05) (QPI Mode)
CS#
0
1
2
3
4
5
6
7
8
N
SCLK
SIO[3:0]
05h
H0 L0 H0 L0 H0 L0
H1 L1
MSB
LSB
Status Byte Status Byte Status Byte
Status Byte
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MX25L6439E
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/
write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write
status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/
write status register cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write en-
able latch. When WEL bit sets to "1", which means the internal write enable latch is set, the device can accept
program/erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable
latch; the device will not accept program/erase/write status register instruction. The program/erase command will
be ignored and will reset WEL bit if it is applied to a protected memory area. To ensure both WIP bit & WEL bit are
both set to 0 and available for next program/erase/operations, WIP bit needs to be confirm to be 0 before polling
WEL bit. After WIP bit confirmed, WEL bit needs to be confirm to be 0.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protect-
ed area (as defined in "Table 2. Protected Area Sizes") of the device to against the program/erase instruction
without hardware protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the
Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to
against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip Erase (CE) instructions (only if all
Block Protect bits set to 0, the CE instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default.
Which is un-protected.
QE bit. The Quad Enable (QE) bit, non-volatile bit, while it is "0" (factory default), it performs non-Quad and WP#
is enable. While QE is "1", it performs Quad I/O mode and WP# is disabled. In the other word, if the system goes
into four I/O mode (QE=1), the feature of HPM will be disabled. While in QPI mode, QE bit is not required for set-
ting.
SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, default value is "0". SRWD bit is oper-
ated together with Write Protection (WP#/SIO2) pin for providing hardware protection mode. The hardware pro-
tection mode requires SRWD sets to 1 and WP#/SIO2 pin signal is low stage. In the hardware protection mode,
the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block
Protect bits (BP3, BP2, BP1, BP0) are read only. The SRWD bit defaults to be "0".
Status Register
bit7
SRWD
(status
bit6
bit5
BP3
(level of
protected
block)
bit4
BP2
(level of
protected
block)
bit3
BP1
(level of
protected
block)
bit2
BP0
(level of
protected
block)
bit1
bit0
QE
(Quad
Enable)
WEL
(write enable
latch)
WIP
(write in
progress bit)
register write
protect)
1= Quad
Enable
0=not Quad
Enable
1=write
enable
0=not write 0=not in write
1=write
operation
1=status
register write
disable
(note 1)
(note 1)
(note 1)
(note 1)
enable
operation
Non-volatile Non-volatile Non-volatile Non-volatile Non-volatile Non-volatile
bit bit bit bit bit bit
volatile bit
volatile bit
Note: see the "Table 2. Protected Area Sizes".
P/N: PM1842
REV. 1.2, NOV. 06, 2013
24
MX25L6439E
Configuration Register
The Configuration Register is able to change the default status of Flash memory. Flash memory will be configured
after the CR bit is set.
TB bit
The Top/Bottom (TB) bit is a non-volatile OTP bit. The Top/Bottom (TB) bit is used to configure the Block Protect
area by BP bit (BP3, BP2, BP1, BP0), starting from TOP or Bottom of the memory array. The TB bit is defaulted as “0”,
which means Top area protect. When it is set as “1”, the protect area will change to Bottom area of the memory
device. To write the TB bit requires the Write Status Register (WRSR) instruction to be executed.
Configuration Register
bit7
DC
bit6
bit5
bit4
bit3
TB
bit2
bit1
bit0
(Dummy
Cycle)
Reserved
Reserved
Reserved
(top/bottom
selected)
0=Top area
protect
Reserved
Reserved
Reserved
(Note)
x
x
x
x
x
x
1=Bottom
area protect
(Default=0)
OTP
x
x
x
x
x
x
Volatile bit
Note: See "Dummy Cycle and Frequency Table", with "Don't Care" on other Reserved Configuration Registers.
Dummy Cycle and Frequency Table
Numbers of Dummy
DC
Quad I/O Fast Read
clock cycles
1
8
6
104
86
0 (default)
P/N: PM1842
REV. 1.2, NOV. 06, 2013
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MX25L6439E
11-5. Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits and Configuration Register Bits. Be-
fore sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the
Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3,
BP2, BP1, BP0) bits to define the protected area of memory (as shown in "Table 2. Protected Area Sizes"). The
WRSR also can set or reset the Quad enable (QE) bit and set or reset the Status Register Write Disable (SRWD)
bit in accordance with Write Protection (WP#/SIO2) pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of
the status register. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is en-
tered.
The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Regis-
ter data on SI→ CS# goes high.
Figure 13. Write Status Register (WRSR) Sequence (Command 01) (SPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Mode 3
Mode 0
SCLK
command
01h
Status
Register In
Configuration
Register In
SI
4
15 14
13
12 11
10 9
8
2
1
0
7
6
5
3
MSB
High-Z
SO
Note : Also supported in QPI mode with command and subsequent input/output in Quad I/O mode.
Figure 14. Write Status Register (WRSR) Sequence (Command 01) (QPI Mode)
CS#
SCLK
12
13
8
9
4
5
0
1
C4, C0
C5, C1
SIO0
SIO1
10
11
2
3
14
15
C6, C2
C7, C3
6
7
SIO2
SIO3
Configuration
Register IN
Status
Register IN
Command
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MX25L6439E
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The
Write in Progress (WIP) bit still can be checked out during the Write Status Register cycle is in progress. The
WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write En-
able Latch (WEL) bit is reset.
Table 6. Protection Modes
Mode
Status register condition
WP# and SRWD bit status
Memory
Status register can be written
in (WEL bit is set to "1") and
the SRWD, BP0-BP3
Software protection
mode (SPM)
WP#=1 and SRWD bit=0, or
WP#=0 and SRWD bit=0, or
WP#=1 and SRWD=1
The protected area cannot
be programmed or erased.
bits can be changed
The SRWD, BP0-BP3 of
status register bits cannot be
changed
Hardware protection
mode (HPM)
The protected area cannot
be programmed or erased.
WP#=0, SRWD bit=1
Note: As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown
in "Table 2. Protected Area Sizes".
As the table above showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode
(HPM):
Software Protected Mode (SPM):
-
-
When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can
change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1,
BP0, is at software protected mode (SPM).
When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values
of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software
protected mode (SPM)
Hardware Protected Mode (HPM):
-
When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hard-
ware protected mode (HPM). The data of the protected area is protected by software protected mode by BP3,
BP2, BP1, BP0 and hardware protected mode by the WP#/SIO2 to against data modification.
Note:
To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is
entered. If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be en-
tered; only can use software protected mode via BP3, BP2, BP1, BP0.
If the system goes into four I/O or QPI mode, the feature of HPM will be disabled.
P/N: PM1842
REV. 1.2, NOV. 06, 2013
27
MX25L6439E
Figure 15. WRSR flow
start
WREN command
RDSR command
No
WEL=1?
Yes
WRSR command
Write status register data
RDSR command
No
WIP=0?
Yes
RDSR command
Read WEL=0, BP[3:0], QE,
and SRWD data
No
Verify OK?
Yes
WRSR successfully
WRSR fail
P/N: PM1842
REV. 1.2, NOV. 06, 2013
28
MX25L6439E
11-6. Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out
on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The ad-
dress is automatically increased to the next higher address after each byte data is shifted out, so the whole
memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest ad-
dress has been reached.
The sequence of issuing READ instruction is: CS# goes low→ sending READ instruction code→3-byte address
on SI →data out on SO→ to end READ operation can use CS# to high at any time during data out.
Figure 16. Read Data Bytes (READ) Sequence (Command 03)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
03
24 ADD Cycles
A23 A22 A21
MSB
A3 A2 A1 A0
SI
Data Out 2
Data Out 1
High-Z
D7 D6 D5 D4 D3 D2 D1 D0 D7
MSB MSB
SO
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MX25L6439E
11-7. Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be
at any location. The address is automatically increased to the next higher address after each byte data is shifted
out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to
0 when the highest address has been reached.
Read on SPI Mode The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ
instruction code→ 3-byte address on SI→1-dummy byte (default) address on SI→ data out on SO→ to end
FAST_READ operation can use CS# to high at any time during data out. (Please refer to waveform next page)
Read on QPI Mode The sequence of issuing FAST_READ instruction in QPI mode is: CS# goes low→ send-
ing FAST_READ instruction, 2 cycles→ 24-bit address interleave on SIO3, SIO2, SIO1 & SIO0→4 dummy
cycles→data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end QPI FAST_READ operation can use CS# to
high at any time during data out. (Please refer to waveform next page)
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
Figure 17. Read at Higher Speed (FAST_READ) Sequence (Command 0B) (SPI Mode) (104MHz)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
SCLK
Command
0Bh
24 BIT ADDRESS
SI
23 22 21
3
2
1
0
High-Z
SO
CS#
47
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
SCLK
Dummy Cycle
7
6
5
4
3
2
0
1
SI
DATA OUT 2
DATA OUT 1
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
SO
MSB
MSB
MSB
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REV. 1.2, NOV. 06, 2013
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MX25L6439E
Figure 18. Read at Higher Speed (FAST_READ) Sequence (Command 0B) (QPI Mode) (54MHz)
CS#
MODE 3
MODE 0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCLK
Command
Add Add Add Add Add Add
X
X
0Bh
SIO(3:0)
X
X
H0 L0 H1 L1
MSB LSB MSB LSB
Data Out 1 Data Out 2
24 BIT ADDRESS
Data In
11-8. Quad Read Mode (QREAD)
The QREAD instruction enable quad throughput of Serial Flash in read mode. The address is latched on rising
edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a
maximum frequency fQ. The first address byte can be at any location. The address is automatically increased
to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single
QREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writ-
ing QREAD instruction, the following data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing QREAD instruction is: CS# goes low
sending QREAD instruction → 3-byte address
→
on SI
8-bit dummy cycle
data out interleave on SO3, SO2, SO1 & SO0
to end QREAD operation can
→
→
→
use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any im-
pact on the Program/Erase/Write Status Register current cycle.
Figure 19. Quad Read Mode Sequence (Command 6B)
CS#
29 30 31 32 33
38 39 40 41 42
0
1
2
3
4
5
6
7
8
9
SCLK
…
…
Data
Out 2
Data
Out 3
Command
6B
8 dummy cycles
24 ADD Cycles
Data
Out 1
…
A23A22
A2 A1 A0
D4 D0 D4 D0 D4
SI/SO0
High Impedance
High Impedance
High Impedance
SO/SO1
D5 D1 D5 D1 D5
D6 D2 D6 D2 D6
WP#/SO2
HOLD#/SO3
D7 D3 D7 D3 D7
P/N: PM1842
REV. 1.2, NOV. 06, 2013
31
MX25L6439E
11-9. 4 x I/O Read Mode (4READ)
The 4READ instruction enables quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of sta-
tus Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of
SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum
frequency fQ. The first address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single 4READ in-
struction. The address counter rolls over to 0 when the highest address has been reached. Once writing 4READ
instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit.
4 x I/O Read on SPI Mode (4READ) The sequence of issuing 4READ instruction is: CS# goes low sending
→
4READ instruction 24-bit address interleave on SIO3, SIO2, SIO1 & SIO0 2+4 dummy cycles (default) data
→
→
→
out interleave on SIO3, SIO2, SIO1 & SIO0 to end 4READ operation can use CS# to high at any time during
→
data out. (Please refer to figure below)
W4READ instruction (E7) is also available is SPI mode for 4 I/O read. The sequence is similar to 4READ, but
with only 4 dummy cycles. The clock rate runs at 54MHz.
4 x I/O Read on QPI Mode (4READ) The 4READ instruction also support on QPI command mode. The se-
quence of issuing 4READ instruction QPI mode is: CS# goes low sending 4READ instruction 24-bit address
→
→
interleave on SIO3, SIO2, SIO1 & SIO0 2+4 dummy cycles (default) data out interleave on SIO3, SIO2, SIO1
→
→
& SIO0 to end 4READ operation can use CS# to high at any time during data out.
→
Figure 20. 4 x I/O Read Mode Sequence (Command EB) (SPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
n
SCLK
Conꢀgurable
Dummy cycles
8 Bit Instruction
EBh
6 Address cycles
Data Output
(Note 3)
Performance
enhance
indicator (Note 2)
data
bit4, bit0, bit4....
address
bit20, bit16..bit0
P4 P0
P5 P1
P6 P2
P7 P3
SI/SIO0
High Impedance
High Impedance
High Impedance
address
bit21, bit17..bit1
data
bit5 bit1, bit5....
SO/SIO1
address
bit22, bit18..bit2
data
bit6 bit2, bit6....
WP#/SIO2
HOLD#/SIO3
address
bit23, bit19..bit3
data
bit7 bit3, bit7....
Note:
1. Hi-impedance is inhibited for the two clock cycles.
2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited.
3. The Configurable Dummy Cycle is set by Configuration Register Bit. Please see "Dummy Cycle and Fre-
quency Table"
P/N: PM1842
REV. 1.2, NOV. 06, 2013
32
MX25L6439E
Figure 21. 4 x I/O Read Mode Sequence (Command EB) (QPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MODE 3
MODE 0
MODE 3
MODE 0
SCLK
EB
Data In
SIO[3:0]
X
X
X
X
H0 L0 H1 L1 H2 L2 H3 L3
A5 A4 A3 A2 A1 A0
X
X
MSB
Data Out
Configurable
Dummy cycle
24-bit Address
(Note)
Another sequence of issuing 4READ instruction especially useful in random access is : CS# goes low→ sending
4READ instruction→ 3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 →performance enhance toggling
bit P[7:0]→ 4 dummy cycles → data out until CS# goes high → CS# goes low (reduce 4READ instruction) →
24-bit random access address (Please refer to "Figure 22. 4 x I/O Read enhance performance Mode Sequence
(Command EB) (SPI Mode)").
In the performance-enhancing mode (Notes of "Figure 22. 4 x I/O Read enhance performance Mode Sequence
(Command EB) (SPI Mode)"), P[7:4] must be toggling with P[3:0]; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh can
make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0];
likewise P[7:0]=FFh, 00h, AAh or 55h. These commands will reset the performance enhance mode. And after-
wards CS# is raised and then lowered, the system then will return to normal operation.
While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any im-
pact on the Program/Erase/Write Status Register current cycle.
P/N: PM1842
REV. 1.2, NOV. 06, 2013
33
MX25L6439E
11-10. Performance Enhance Mode
The device could waive the command cycle bits if the two cycle bits after address cycle toggles. (Please note
"Figure 22. 4 x I/O Read enhance performance Mode Sequence (Command EB) (SPI Mode)")
Performance enhance mode is supported in both SPI and QPI mode for 4READ mode.
In QPI mode, “EBh”, “0Bh” and SPI “EBh”, “E7h” commands support enhance mode.
After entering enhance mode, following CS# go high, the device will stay in the read mode and treat CS# go low
of the first clock as address instead of command cycle.
To exit enhance mode, a new fast read command whose first two dummy cycles is not toggle then exit. Or issue
”FFh” data cycles to exit enhance mode.
Figure 22. 4 x I/O Read enhance performance Mode Sequence (Command EB) (SPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
n
SCLK
Conꢀgurable
Dummy cycles
8 Bit Instruction
EBh
6 Address cycles
Data Output
(Note 2)
Performance
enhance
indicator (Note1)
data
bit4, bit0, bit4....
address
bit20, bit16..bit0
P4 P0
P5 P1
P6 P2
P7 P3
SI/SIO0
High Impedance
High Impedance
High Impedance
address
bit21, bit17..bit1
data
bit5 bit1, bit5....
SO/SIO1
address
bit22, bit18..bit2
data
bit6 bit2, bit6....
WP#/SIO2
HOLD#/SIO3
address
bit23, bit19..bit3
data
bit7 bit3, bit7....
CS#
n+1
...........
n+7......n+9 ........... n+13
...........
SCLK
Conꢀgurable
Dummy cycles
6 Address cycles
address
Data Output
(Note 2)
Performance
enhance
indicator (Note1)
data
bit4, bit0, bit4....
P4 P0
P5 P1
P6 P2
P7 P3
SI/SIO0
bit20, bit16..bit0
address
bit21, bit17..bit1
data
bit5 bit1, bit5....
SO/SIO1
address
bit22, bit18..bit2
data
bit6 bit2, bit6....
WP#/SIO2
HOLD#/SIO3
address
bit23, bit19..bit3
data
bit7 bit3, bit7....
Note:
1. Performance enhance mode, if P7≠P3 & P6≠P2 & P5≠P1 & P4≠P0 (Toggling), ex: A5, 5A, 0F, if not using
performance enhance recommend to keep 1 or 0 in performance enhance indicator.
Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF
2. The Configurable Dummy Cycle is set by Configuration Register Bit. Please see "Dummy Cycle and
Frequency Table"
P/N: PM1842
REV. 1.2, NOV. 06, 2013
34
MX25L6439E
Figure 23. 4 x I/O Read enhance performance Mode Sequence (Command EB) (QPI Mode)
CS#
MODE 3
MODE 0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
SCLK
EBh
SIO[3:0]
X
X
X
X
H0 L0 H1 L1
MSB LSB MSB LSB
A5 A4 A3 A2 A1 A0
P(7:4)P(3:0)
Data In
performance
enhance
Data Out
indicator
Configurable Dummy cycles
(Note)
CS#
SCLK
n+1 .............
MODE 0
SIO[3:0]
X
X
X
X
H0 L0 H1 L1
MSB LSB MSB LSB
A5 A4 A3 A2 A1 A0
P(7:4)P(3:0)
6 Address cycles
performance
enhance
Data Out
indicator
Configurable Dummy cycles
(Note)
Note: The Configurable Dummy Cycle is set by Configuration Register Bit. Please see "Dummy Cycle and
Frequency Table"
P/N: PM1842
REV. 1.2, NOV. 06, 2013
35
MX25L6439E
11-11. Performance Enhance Mode Reset
To conduct the Performance Enhance Mode Reset operation in SPI mode, FFh data cycle, 8 clocks, should be
issued in 1I/O sequence. In QPI Mode, FFFFFFFFh data cycle, 8 clocks, in 4I/O should be issued.
If the system controller is being Reset during operation, the flash device will return to the standard SPI operation.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
Figure 24. Performance Enhance Mode Reset for Fast Read Quad I/O (SPI Mode)
Mode Bit Reset
for Quad I/O
CS#
Mode 3
Mode 3
０
1
2
3
4
5
6
7
SCLK
Mode ０
Mode ０
FFh
SIO0
SIO1
SIO2
Don’t Care
Don’t Care
Don’t Care
SIO3
Figure 25. Performance Enhance Mode Reset for Fast Read Quad I/O (QPI Mode)
Mode Bit Reset
for Quad I/O
CS#
Mode 3
Mode 3
Mode ０
０
1
2
3
4
5
6
7
SCLK
Mode ０
FFFFFFFFh
SIO[3:0]
P/N: PM1842
REV. 1.2, NOV. 06, 2013
36
MX25L6439E
11-12. Burst Read
The device supports Burst Read in both SPI and QPI mode.
To set the Burst length, following command operation is required
Issuing command: “77h” in the first Byte (8-clocks), following 4 clocks defining wrap around enable with “0h” and
disable with“1h”.
Next 4 clocks is to define wrap around depth. Definition as following table:
Data
00h
01h
02h
03h
1xh
Wrap Around
Wrap Depth
8-byte
Yes
Yes
Yes
Yes
No
16-byte
32-byte
64-byte
X
The wrap around unit is defined within the 256Byte page, with random initial address. It’s defined as “wrap-
around mode disable” for the default state of the device. To exit wrap around, it is required to issue another
“77” command in which data=‘1xh”. Otherwise, wrap around status will be retained until power down or reset
command. To change wrap around depth, it is requried to issue another “77” command in which data=“0xh”. QPI
“0Bh” “EBh” and SPI “EBh” “E7h” support wrap around feature after wrap around enable. Burst read is supported
in both SPI and QPI mode. The Device ID default without Burst read.
SPI Mode
CS#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Mode 3
Mode 0
SCLK
SIO
D7
D6
D5
D4
D3
D2
D1
D0
77h
QPI Mode
CS#
0
1
2
3
Mode 3
Mode 0
SCLK
77h
H0
L0
SIO[3:0]
MSB LSB
Note: MSB=Most Significant Bit
LSB=Least Significant Bit
P/N: PM1842
REV. 1.2, NOV. 06, 2013
37
MX25L6439E
11-13. Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used
for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL)
bit before sending the Sector Erase (SE). Any address of the sector (see "Table 4. Memory Organization" ) is a
valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the latest
eighth of address byte has been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing SE instruction is: CS# goes low → sending SE instruction code→ 3-byte address on SI
→CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't
care when during SPI mode.
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked out during the Sector Erase cycle is in progress. The WIP sets 1 during
the tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset.
If the sector is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected
(no change) and the WEL bit still be reset.
Figure 26. Sector Erase (SE) Sequence (Command 20) (SPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
20h
24 Bit Address
SI
23 22
MSB
2
1
0
Figure 27. Sector Erase (SE) Sequence (Command 20) (QPI Mode)
CS#
0
1
2
3
4
5
6
7
SCLK
24 BIT ADDRESS
Command
A20 A16 A12 A8 A4 A0
MSB LSB
SIO[3:0]
20h
P/N: PM1842
REV. 1.2, NOV. 06, 2013
38
MX25L6439E
11-14. Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for
64K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch
(WEL) bit before sending the Block Erase (BE). Any address of the block (see "Table 4. Memory Organization")
is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the lat-
est eighth of address byte has been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE instruction is: CS# goes low → sending BE instruction code → 3-byte address on
SI → CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked out during the Sector Erase cycle is in progress. The WIP sets 1 during
the tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset.
If the block is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no
change) and the WEL bit still be reset.
Figure 28. Block Erase (BE) Sequence (Command D8) (SPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
D8h
24 Bit Address
SI
23 22
MSB
2
0
1
Figure 29. Block Erase (BE) Sequence (Command D8) (QPI Mode)
CS#
0
1
2
3
4
5
6
7
SCLK
24 BIT ADDRESS
Command
A20 A16 A12 A8 A4 A0
MSB
SIO[3:0]
D8h
P/N: PM1842
REV. 1.2, NOV. 06, 2013
39
MX25L6439E
11-15. Block Erase (BE32K)
The Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1". The instruction is
used for 32K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write En-
able Latch (WEL) bit before sending the Block Erase (BE32K). Any address of the block (see "Table 4. Memory
Organization" ) is a valid address for Block Erase (BE32K) instruction. The CS# must go high exactly at the byte
boundary (the latest eighth of address byte has been latched-in); otherwise, the instruction will be rejected and
not executed.
The sequence of issuing BE32K instruction is: CS# goes low → sending BE32K instruction code → 3-byte ad-
dress on SI → CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
The self-timed Block Erase Cycle time (tBE32K) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be checked out during the Sector Erase cycle is in progress. The WIP sets 1
during the tBE32K timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL)
bit is reset. If the block is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be
protected (no change) and the WEL bit still be reset.
Figure 30. Block Erase 32KB (BE32K) Sequence (Command 52) (SPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
52h
24 Bit Address
SI
23 22
MSB
2
0
1
Figure 31. Block Erase 32KB (BE32K) Sequence (Command 52) (QPI Mode)
CS#
0
1
2
3
4
5
6
7
SCLK
24 BIT ADDRESS
Command
A20 A16 A12 A8 A4 A0
MSB
SIO[3:0]
52h
P/N: PM1842
REV. 1.2, NOV. 06, 2013
40
MX25L6439E
11-16. Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) in-
struction must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS#
must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The sequence of issuing CE instruction is: CS# goes low → sending CE instruction code → CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked out during the Chip Erase cycle is in progress. The WIP sets 1 during the
tCE timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
chip is protected the Chip Erase (CE) instruction will not be executed, but WEL will be reset.
Figure 32. Chip Erase (CE) Sequence (Command 60 or C7) (SPI Mode)
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
60h or C7h
Figure 33. Chip Erase (CE) Sequence (Command 60 or C7) (QPI Mode)
CS#
0
1
SCLK
Command
60h or C7h
SIO[3:0]
P/N: PM1842
REV. 1.2, NOV. 06, 2013
41
MX25L6439E
11-17. Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction
must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device
programs only the last 256 data bytes sent to the device. The last address byte (the 8 least significant address
bits, A7-A0) should be set to 0 for 256 bytes page program. If A7-A0 are not all zero, transmitted data that
exceed page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently
selected page. If the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the
request page and previous data will be disregarded. If the data bytes sent to the device has not exceeded 256,
the data will be programmed at the request address of the page. There will be no effort on the other data bytes of
the same page.
The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on
SI→ at least 1-byte on data on SI→ CS# goes high.
The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte
boundary (the latest eighth bit of data being latched in), otherwise, the instruction will be rejected and will not be
executed.
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be checked out during the Page Program cycle is in progress. The WIP sets 1
during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit
is reset. If the page is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be
protected (no change) and the WEL bit will still be reset.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
Figure 34. Page Program (PP) Sequence (Command 02) (SPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
02h
24-Bit Address
Data Byte 1
23 22 21
MSB
3
2
1
0
7
6
5
4
3
2
0
1
SI
MSB
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
Data Byte 2
Data Byte 3
Data Byte 256
7
6
5
4
3
2
0
7
6
5
4
3
2
0
7
6
5
4
3
2
0
1
1
1
SI
MSB
MSB
MSB
P/N: PM1842
REV. 1.2, NOV. 06, 2013
42
MX25L6439E
Figure 36. Page Program (PP) Sequence (Command 02) (QPI Mode)
CS#
MODE 3
MODE 0
0
1
2
SCLK
24 BIT ADDRESS
Command
02h
SIO[3:0]
H0 L0 H1 L1 H2 L2 H3 L3
H255 L255
A5 A4 A3 A2 A1 A0
......
Data Byte Data Byte Data Byte Data Byte
Data Byte
256
Data In
1
2
3
4
11-18. 4 x I/O Page Program (4PP)
The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN)
instruction must execute to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1"
before sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1,
SIO2, and SIO3, which can raise programmer performance and the effectiveness of application of lower clock
less than 104MHz. For system with faster clock, the Quad page program cannot provide more actual favors,
because the required internal page program time is far more than the time data flows in. Therefore, we suggest
that while executing this command (especially during sending data), user can slow the clock speed down to
104MHz below. The other function descriptions are as same as standard page program.
The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on
SIO[3:0]→ at least 1-byte on data on SIO[3:0]→ CS# goes high.
If the page is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no
change) and the WEL bit will still be reset.
Figure 35. 4 x I/O Page Program (4PP) Sequence (Command 38)
CS#
524 525
10 11 12 13 14 15 16 17
0
1
2
3
4
5
6
7
8
9
SCLK
…
…
Data
Byte 256
Data Data
Byte 1 Byte 2
Command
38
6 ADD cycles
D4 D0 D4 D0
D4 D0
A20 A16 A12 A8 A4 A0
SI/SIO0
…
…
…
D5 D1 D5 D1
D6 D2 D6 D2
D7 D3 D7 D3
D5 D1
D6 D2
D7 D3
SO/SIO1
A21 A17 A13 A9 A5 A1
A22 A18 A14 A10 A6 A2
WP#/SIO2
HOLD#/SIO3
A23 A19 A15 A11 A7 A3
P/N: PM1842
REV. 1.2, NOV. 06, 2013
43
MX25L6439E
The Program/Erase function instruction function flow is as follows:
Figure 37. Program/Erase Flow(1) with read array data
Start
WREN command
RDSR command*
No
WEL=1?
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
No
WIP=0?
Yes
Read array data
(same address of PGM/ERS)
No
Verify OK?
Yes
Program/erase fail
Program/erase successfully
Program/erase
another block?
Yes
* Issue RDSR to check BP[3:0].
* If WPSEL=1, issue RDBLOCK to check the block status.
No
Program/erase completed
P/N: PM1842
REV. 1.2, NOV. 06, 2013
44
MX25L6439E
Figure 38. Program/Erase Flow(2) without read array data
Start
WREN command
RDSR command*
No
WEL=1?
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
No
WIP=0?
Yes
RDSCUR command
Yes
REGPFAIL/REGEFAIL=1?
No
Program/erase fail
Program/erase successfully
Program/erase
another block?
Yes
* Issue RDSR to check BP[3:0].
* If WPSEL=1, issue RDBLOCK to check the block status.
No
Program/erase completed
P/N: PM1842
REV. 1.2, NOV. 06, 2013
45
MX25L6439E
11-19. Continuous Program mode (CP mode)
The CP mode may enhance program performance by automatically increasing address to the next higher ad-
dress after each byte data has been programmed.
The Continuous Program (CP) instruction is for multiple bytes program to Flash. A write Enable (WREN) in-
struction must execute to set the Write Enable Latch (WEL) bit before sending the Continuous Program (CP)
instruction. CS# requires to go high before CP instruction is executing. After CP instruction and address input,
two bytes of data is input sequentially from MSB(bit7) to LSB(bit0). The first byte data will be programmed to the
initial address range with A0=0 and second byte data with A0=1. If only one byte data is input, the CP mode will
not process. If more than two bytes data are input, the additional data will be ignored and only two byte data are
valid. Any byte to be programmed should be in the erase state (FF) first. It will not roll over during the CP mode,
once the last unprotected address has been reached, the chip will exit CP mode and reset write Enable Latch bit
(WEL) as "0" and CP mode bit as "0". Please check the WIP bit status if it is not in write progress before enter-
ing next valid instruction. During CP mode, the valid commands are CP command (AD hex), WRDI command (04
hex), RDSR command (05 hex), and RDSCUR command (2B hex). And the WRDI command is valid after com-
pletion of a CP programming cycle, which means the WIP bit=0.
The sequence of issuing CP instruction is : CS# goes low → sending CP instruction code → 3-byte address on
SI pin → two data bytes on SI → CS# goes high to low → sending CP instruction and then continue two data
bytes are programmed → CS# goes high to low → till last desired two data bytes are programmed → CS# goes
high to low →sending WRDI (Write Disable) instruction to end CP mode → send RDSR instruction to verify if
CP mode word program ends, or send RDSCUR to check bit4 to verify if CP mode ends.
Three methods to detect the completion of a program cycle during CP mode:
1) Software method-I: by checking WIP bit of Status Register to detect the completion of CP mode.
2) Software method-II: by waiting for a tBP time out to determine if it may load next valid command or not.
3) Hardware method: by writing ESRY (enable SO to output RY/BY#) instruction to detect the completion of a
program cycle during CP mode. The ESRY instruction must be executed before CP mode execution. Once
it is enable in CP mode, the CS# goes low will drive out the RY/BY# status on SO, "0" indicates busy stage,
"1" indicates ready stage, SO pin outputs tri-state if CS# goes high. DSRY (disable SO to output RY/BY#)
instruction to disable the SO to output RY/BY# and return to status register data output during CP mode.
Please note that the ESRY/DSRY commands are not accepted unless the completion of CP mode.
If the page is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be pro-
tected (no change) and the WEL bit will still be reset.
P/N: PM1842
REV. 1.2, NOV. 06, 2013
46
MX25L6439E
Figure 39. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD)
CS#
SCLK
SI
20 2122 23 24
0
1
30 31 31 32
47 48
0
7
7
8
0
6
7 8
0
1
6 7 8 9
Command
AD (hex)
data in
Byte n-1, Byte n
Valid
Command (1)
data in
04 (hex)
05 (hex)
24-bit address
Byte 0, Byte1
high impedance
status (2)
S0
Notes:
(1) During CP mode, the valid commands are CP command (AD hex), WRDI command (04 hex), RDSR
command (05 hex), RDSCUR command (2B hex), RSTEN command (66 hex) and RST command (99hex).
(2) Once an internal programming operation begins, CS# goes low will drive the status on the SO pin and CS#
goes high will return the SO pin to tri-state.
(3) To end the CP mode, either reaching the highest unprotected address or sending Write Disable (WRDI)
command (04 hex) may achieve it and then it is recommended to send RDSR command (05 hex) to verify if
CP mode is ended. Please be noticed that Software reset and Hardware reset can end the CP mode.
P/N: PM1842
REV. 1.2, NOV. 06, 2013
47
MX25L6439E
11-20. Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to en-
tering the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2. The Deep Power-down
mode requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is
not active and all Write/Program/Erase instructions are ignored. When CS# goes high, it's only in standby mode
not deep power-down mode. It's different from Standby mode.
The sequence of issuing DP instruction is: CS# goes low→ sending DP instruction code→ CS# goes high.
The SIO[3:1] are don't care when during this mode.
Once the DP instruction is set, all instructions will be ignored except the Release from Deep Power-down mode (RDP)
and Read Electronic Signature (RES) instruction. (those instructions allow the ID being reading out). When
Power-down, the deep power-down mode automatically stops, and when power-up, the device automatically is
in standby mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of
instruction code has been latched-in); otherwise, the instruction will not be executed. As soon as Chip Select (CS#)
goes high, a delay of tDP is required before entering the Deep Power-down mode and reducing the current to
ISB2.
Figure 40. Deep Power-down (DP) Sequence (Command B9)
CS#
tDP
0
1
2
3
4
5
6
7
SCLK
SI
Command
B9h
Stand-by Mode
Deep Power-down Mode
P/N: PM1842
REV. 1.2, NOV. 06, 2013
48
MX25L6439E
11-21. Release from Deep Power-down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When
Chip Select (CS#) is driven High, the device is put in the standby Power mode. If the device was not previously
in the Deep Power-down mode, the transition to the standby Power mode is immediate. If the device was previ-
ously in the Deep Power-down mode, though, the transition to the standby Power mode is delayed by tRES2,
and Chip Select (CS#) must remain High for at least tRES2(max), as specified in "Table 13. AC CHARACTER-
ISTICS". Once in the standby mode, the device waits to be selected, so that it can receive, decode and execute
instructions.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as "Table 7.
ID Definitions". This is not the same as RDID instruction. It is not recommended to use for new design. For new
design, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to
be executed, only except the device is in progress of program/erase/write cycles; there's no effect on the current
program/erase/write cycles in progress.
The SIO[3:1] are don't care when during this mode.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeat-
edly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previous-
ly in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously
in Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high
at least tRES2(max). Once in the standby mode, the device waits to be selected, so it can receive, decode, and
execute instruction.
The RDP instruction is for releasing from Deep Power-down Mode.
Figure 41. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command
AB)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38
SCLK
Command
ABh
t
3 Dummy Bytes
RES2
SI
23 22 21
MSB
3
2
1
0
Electronic Signature Out
High-Z
7
6
5
4
3
2
0
1
SO
MSB
Deep Power-down Mode
Stand-by Mode
P/N: PM1842
REV. 1.2, NOV. 06, 2013
49
MX25L6439E
11-22. Read Electronic Signature (RES)
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as "Table 7.
ID Definitions" . This is not the same as RDID instruction. It is not recommended to use for new design. For new
design, please use RDID instruction. For RES instruction, there's no effect on the current program/erase/write
cycles in progress.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeat-
edly if continuously send the additional clock cycles on SCLK while CS# is at low.
Figure 42. Read Electronic Signature (RES) Sequence (Command AB) (SPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38
SCLK
Command
ABh
t
3 Dummy Bytes
RES2
SI
23 22 21
MSB
3
2
1
0
Electronic Signature Out
High-Z
7
6
5
4
3
2
0
1
SO
MSB
Stand-by Mode
Figure 43. Read Electronic Signature (RES) Sequence (Command AB) (QPI Mode)
CS#
MODE 3
tRES2
0
1
2
3
4
5
6
7
SCLK
MODE 0
24 BIT ADDRESS
Command
ABh
SIO[3:0]
H0 L0
MSB LSB
Data Out
A5 A4 A3 A2 A1 A0
Data In
Stand-by Mode
P/N: PM1842
REV. 1.2, NOV. 06, 2013
50
MX25L6439E
11-23. QPI ID Read (QPIID)
User can execute this ID Read instruction to identify the Device ID and Manufacturer ID. The sequence of issue
QPIID instruction is CS# goes low→sending QPI ID instruction→→Data out on SO→CS# goes high. Most
significant bit (MSB) first.
After the command cycle, the device will immediately output data on the falling edge of SCLK. The manufacturer
ID, memory type, and device ID data byte will be output continuously, until the CS# goes high.
Table 7. ID Definitions
Command Type
MX25L6439E
memory type
25
manufacturer ID
C2
memory density
37
RDID/QPIID
electronic ID
37
RES
11-24. Enter Secured OTP (ENSO)
The ENSO instruction is for entering the additional 4K-bit Secured OTP mode. The additional 4K-bit Secured
OTP is independent from main array, which may use to store unique serial number for system identifier. After
entering the Secured OTP mode, and then follow standard read or program procedure to read out the data or up-
date data. The Secured OTP data cannot be updated again once it is lock-down.
The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP
mode→ CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
Please note that WRSR/WRSCUR/WPSEL/SBLK/GBLK/SBULK/GBULK/CE/BE/SE/BE32K commands are not
acceptable during the access of secure OTP region, once Security OTP is locked down, only read related com-
mands are valid.
11-25. Exit Secured OTP (EXSO)
The EXSO instruction is for exiting the additional 4K-bit Secured OTP mode.
The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP
mode→ CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
P/N: PM1842
REV. 1.2, NOV. 06, 2013
51
MX25L6439E
11-26. Read Security Register (RDSCUR)
The RDSCUR instruction is for reading the value of Security Register. The Read Security Register can be read
at any time (even in program/erase/write status register/write security register condition) and continuously.
The sequence of issuing RDSCUR instruction is : CS# goes low→ sending RDSCUR instruction → Security
Register data out on SO→ CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't
care when during SPI mode.
Figure 44. Read Security Register (RDSCUR) Sequence (Command 2B) (SPI mode)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI
command
2B
Security Register Out
Security Register Out
High-Z
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
The definition of the Security Register is as below:
Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory before ex- factory
or not. When it is "0", it indicates non-factory lock; "1" indicates factory- lock.
Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for cus-
tomer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 4K-bit Secured
OTP area cannot be updated any more. While it is in 4K-bit Secured OTP mode, array access is not allowed.
Program Suspend Status bit. Program Suspend Bit (PSB) indicates the status of Program Suspend operation.
Users may use PSB to identify the state of flash memory. After the flash memory is suspended by Program Sus-
pend command, PSB is set to "1". PSB is cleared to "0" after program operation resumes
Erase Suspend Status bit. Erase Suspend Bit (ESB) indicates the status of Erase Suspend operation. Users
may use ESB to identify the state of flash memory. After the flash memory is suspended by Erase Suspend com-
mand, ESB is set to "1". ESB is cleared to "0" after erase operation resumes.
P/N: PM1842
REV. 1.2, NOV. 06, 2013
52
MX25L6439E
Program Fail Flag bit. While a program failure happened, the Program Fail Flag bit would be set. If the program
operation fails on a protected memory region or locked OTP region, this bit will also be set. This bit can be the
failure indication of one or more program operations. This fail flag bit will be cleared automatically after the next
successful program operation.
Erase Fail Flag bit. While an erase failure happened, the Erase Fail Flag bit would be set. If the erase opera-
tion fails on a protected memory region or locked OTP region, this bit will also be set. This bit can be the failure
indication of one or more erase operations. This fail flag bit will be cleared automatically after the next successful
erase operation.
Write Protection Select bit. The Write Protection Select bit indicates that WPSEL has been executed success-
fully. Once this bit has been set (WPSEL=1), all the blocks or sectors will be write-protected after the power-
on every time. Once WPSEL has been set, it cannot be changed again, which means it's only for individual WP
mode.
Under the individual block protection mode (WPSEL=1), hardware protection is performed by driving WP#=0.
Once WP#=0, all array blocks/sectors are protected regardless of the contents of SRAM lock bits.
Table 8. Security Register Definition
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
LDSO
(lock-down
4K-bit Se- Secured OTP
cured OTP)
Erase
Suspend
status
Program
Suspend
status
4K-bit
WPSEL
E_FAIL
P_FAIL
Reserved
0 = not
lockdown
0=normal
Erase
succeed
0=normal
Program
succeed
0=normal
WP mode
0 =
nonfactory
lock
0=Erase
is not
suspended suspended
0=Program
is not
1 = lock-
down
(cannot
program/
erase
1=individual
WP mode
(default=0)
Reserved
volatile bit
1=indicate
Erase failed
(default=0)
1=indicate
Program
failed
1 = factory
lock
1=Erase is 1=Program
suspended is suspended
(default=0) (default=0)
(default=0)
OTP)
non-volatile
bit
non-volatile non-volatile
volatile bit
Read Only
volatile bit
Read Only
volatile bit
Read Only
volatile bit
Read Only
bit
bit
OTP
OTP
Read Only
P/N: PM1842
REV. 1.2, NOV. 06, 2013
53
MX25L6439E
11-27. Write Security Register (WRSCUR)
The WRSCUR instruction is for changing the values of Security Register Bits. Unlike write status register, the
WREN instruction is not required before sending WRSCUR instruction. The WRSCUR instruction may change
the values of bit1 (LDSO bit) for customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is set
to "1", the Secured OTP area cannot be updated any more.
The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes
high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
Figure 45. Write Security Register (WRSCUR) Sequence (Command 2F) (SPI mode)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
2F
SI
High-Z
SO
11-28. Write Protection Selection (WPSEL)
There are two write protection methods, (1) BP protection mode (2) individual block protection mode. If WP-
SEL=0, flash is under BP protection mode. If WPSEL=1, flash is under individual block protection mode. The
default value of WPSEL is “0”. WPSEL command can be used to set WPSEL=1. Please note that WPSEL is an
OTP bit. Once WPSEL is set to 1, there is no chance to recovery WPSEL back to “0”. If the flash is put on
BP mode, the individual block protection mode is disabled. Contrarily, if flash is on the individual block protection
mode, the BP mode is disabled.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't
care when during SPI mode.
Every time after the system is powered-on, and the Security Register bit 7 is checked to be WPSEL=1,
all the blocks or sectors will be write protected by default. User may only unlock the blocks or sectors via
SBULK and GBULK instruction. Program or erase functions can only be operated after the Unlock instruction is
conducted.
BP protection mode, WPSEL=0:
ARRAY is protected by BP3~BP0 and BP3~BP0 bits are protected by “SRWD=1 and WP#=0”, where SRWD is
bit 7 of status register that can be set by WRSR command.
P/N: PM1842
REV. 1.2, NOV. 06, 2013
54
MX25L6439E
Individual block protection mode, WPSEL=1:
Blocks are individually protected by their own SRAM lock bits which are set to “1” after power up. SBULK and
SBLK command can set SRAM lock bit to “0” and “1”. When the system accepts and executes WPSEL instruc-
tion, the bit 7 in security register will be set. It will activate SBLK, SBULK, RDBLOCK, GBLK, GBULK etc instruc-
tions to conduct block lock protection and replace the original Software Protect Mode (SPM) use (BP3~BP0)
indicated block methods. Under the individual block protection mode (WPSEL=1), hardware protection is per-
formed by driving WP#=0. Once WP#=0, all array blocks/sectors are protected regardless of the contents of
SRAM lock bits.
Execution of WREN (Write Enable) instruction is required before issuing WPSEL instruction.
The sequence of issuing WPSEL instruction is: CS# goes low → sending WPSEL instruction to enter the indi-
vidual block protect mode → CS# goes high.
Figure 46. Write Protection Selection (WPSEL) Sequence (Command 68) (SPI mode)
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
68
WPSEL instruction function flow is as follows:
Figure 47. BP and SRWD if WPSEL=0
WPB pin
BP3 BP2 BP1 BP0
SRWD
64KB
64KB
(1) BP3~BP0 is used to define the protection group region.
(The protected area size see "Table 2. Protected Area Sizes" )
(2) “SRWD=1 and WPB=0” is used to protect BP3~BP0. In this
case, SRWD and BP3~BP0 of status register bits can not be
changed by WRSR
64KB
.
.
.
64KB
P/N: PM1842
REV. 1.2, NOV. 06, 2013
55
MX25L6439E
Figure 48. The individual block lock mode is effective after setting WPSEL=1
4KB
4KB
SRAM
SRAM
• Power-Up: All SRAM bits=1 (all blocks are default protected).
All arrays cannot be programmed/erased
TOP 4KBx16
Sectors
• SBLK/SBULK(36h/39h):
- SBLK(36h) : Set SRAM bit=1 (protect) : array can not be
programmed /erased
4KB
SRAM
SRAM
- SBULK(39h): Set SRAM bit=0 (unprotect): array can be
programmed /erased
64KB
- All top 4KBx16 sectors and bottom 4KBx16 sectors
and other 64KB uniform blocks can be protected and
unprotected SRAM bits individually by SBLK/SBULK
command set.
SRAM
Uniform
64KB blocks
• GBLK/ GBULK(7Eh/98h):
- GBLK(7Eh):Set all SRAM bits=1,whole chip are protected
and cannot be programmed / erased.
- GBULK(98h):Set all SRAM bits=0,whole chip are
unprotected and can be programmed / erased.
- All sectors and blocks SRAM bits of whole chip can be
protected and unprotected at one time by GBLK/GBULK
command set.
64KB
4KB
SRAM
SRAM
Bottom
4KBx16
Sectors
• RDBLOCK(3Ch):
- use RDBLOCK mode to check the SRAM bits status after
SBULK /SBLK/GBULK/GBLK command set.
4KB
SBULK / SBLK / GBULK / GBLK / RDBLOCK
P/N: PM1842
REV. 1.2, NOV. 06, 2013
56
MX25L6439E
Figure 49. WPSEL Flow
start
RDSCUR(2Bh) command
Yes
WPSEL=1?
No
WPSEL disable,
block protected by BP[3:0]
WPSEL(68h) command
RDSR command
No
WIP=0?
Yes
RDSCUR(2Bh) command
No
WPSEL=1?
Yes
WPSEL set successfully
WPSEL set fail
WPSEL enable.
Block protected by individual lock
(SBLK, SBULK, … etc).
P/N: PM1842
REV. 1.2, NOV. 06, 2013
57
MX25L6439E
11-29. Single Block Lock/Unlock Protection (SBLK/SBULK)
These instructions are only effective after WPSEL was executed. The SBLK instruction is for write protection a
specified block(or sector) of memory, using A23-A16 or (A23-A12) address bits to assign a 64Kbytes block (or
4K bytes sector) to be protected as read only. The SBULK instruction will cancel the block (or sector) write pro-
tection state. This feature allows user to stop protecting the entire block (or sector) through the chip unprotect
command (GBULK).
The WREN (Write Enable) instruction is required before issuing SBLK/SBULK instruction.
The sequence of issuing SBLK/SBULK instruction is: CS# goes low → send SBLK/SBULK (36h/39h) instruction
→ send 3 address bytes assign one block (or sector) to be protected on SI pin → CS# goes high.
The CS# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not be execut-
ed.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't
care when during SPI mode.
Figure 50. Single Block Lock/Unlock Protection (SBLK/SBULK) Sequence (Command 36/39) (SPI mode)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
36/39
24 Bit Address
Cycles
A23 A22
A2 A1 A0
SI
MSB
P/N: PM1842
REV. 1.2, NOV. 06, 2013
58
MX25L6439E
SBLK/SBULK instruction function flow is as follows:
Figure 51. Block Lock Flow
Start
RDSCUR(2Bh) command
No
WPSEL=1?
WPSEL command
Yes
WREN command
SBLK command
( 36h + 24bit address )
RDSR command
No
WIP=0?
Yes
RDBLOCK command
( 3Ch + 24bit address )
No
Data = FFh ?
Yes
Block lock successfully
Block lock fail
Yes
Lock another block?
No
Block lock completed
P/N: PM1842
REV. 1.2, NOV. 06, 2013
59
MX25L6439E
Figure 52. Block Unlock Flow
start
RDSCUR(2Bh) command
No
WPSEL=1?
Yes
WPSEL command
WREN command
SBULK command
( 39h + 24bit address )
RDSR command
WIP=0?
No
Yes
Yes
Unlock another block?
Unlock block completed
P/N: PM1842
REV. 1.2, NOV. 06, 2013
60
MX25L6439E
11-30. Read Block Lock Status (RDBLOCK)
This instruction is only effective after WPSEL was executed. The RDBLOCK instruction is for reading the status
of protection lock of a specified block(or sector), using A23-A16 (or A23-A12) address bits to assign a 64K bytes
block (4K bytes sector) and read protection lock status bit which the first byte of Read-out cycle. The status bit
is"1" to indicate that this block has been protected, that user can read only but cannot write/program /erase this
block. The status bit is "0" to indicate that this block hasn't be protected, and user can read and write this block.
The sequence of issuing RDBLOCK instruction is: CS# goes low → send RDBLOCK (3Ch) instruction → send
3 address bytes to assign one block on SI pin → read block's protection lock status bit on SO pin → CS# goes
high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
Figure 53. Read Block Protection Lock Status (RDBLOCK) Sequence (Command 3C) (SPI mode)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
3C
24 ADD Cycles
SI
A23 A22 A21
MSB
A3 A2 A1 A0
Block Protection Lock status out
High-Z
D7 D6 D5 D4 D3 D2 D1 D0
MSB
SO
P/N: PM1842
REV. 1.2, NOV. 06, 2013
61
MX25L6439E
11-31. Gang Block Lock/Unlock (GBLK/GBULK)
These instructions are only effective after WPSEL was executed. The GBLK/GBULK instruction is for enable/
disable the lock protection block of the whole chip.
The WREN (Write Enable) instruction is required before issuing GBLK/GBULK instruction.
The sequence of issuing GBLK/GBULK instruction is: CS# goes low → send GBLK/GBULK (7Eh/98h) instruc-
tion → CS# goes high.
The CS# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be ex-
ecuted.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't
care when during SPI mode.
Figure 54. Gang Block Lock/Unlock (GBLK/GBULK) Sequence (Command 7E/98) (SPI mode)
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
7E/98
P/N: PM1842
REV. 1.2, NOV. 06, 2013
62
MX25L6439E
11-32. Program/ Erase Suspend/ Resume
The device allow the interruption of Sector-Erase, Block-Erase or Page-Program operations and conduct other
operations. Details as follows.
To enter the suspend/ resume mode: issuing 75h for suspend; 7Ah for resume (SPI/QPI all acceptable)
Read security register bit2 (PSB) and bit3 (ESB) to check suspend ready information.
Suspend to suspend ready timing: 20us.
Resume to another suspend timing: 1ms.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
11-33. Erase Suspend
Erase suspend allow the interruption of all erase operations.
After erase suspend, WEL bit will be clear, only read related, resume command can be accepted. (including: 03h,
0Bh, BBh, EBh, E7h, 9Fh, AFh, 90h, 05h, 2Bh, B1h, C1h, 5Ah, 3Ch, 7Ah, 66h, 77h, 35h, F5h, 00h, ABh)
For erase suspend to program operation, a Write Enable (WREN) instruction must execute to set the Write
Enable Latch (WEL) bit before starting the operation. Please note that the programming command (38, 02) can
be accepted under conditions as follows:
The bank is divided into 16 banks in this device, each bank's density is 4Mb. While conducting erase suspend in
one bank, the programming operation that follows can only be conducted in one of the other banks and cannot
be conducted in the bank executing the suspend operation. The boundaries of the banks are illustrated as below
table.
MX25L6439E
BANK (4M bit)
Address Range
780000h-7FFFFFh
700000h-77FFFFh
680000h-6FFFFFh
600000h-67FFFFh
580000h-5FFFFFh
500000h-57FFFFh
480000h-4FFFFFh
400000h-47FFFFh
380000h-3FFFFFh
300000h-37FFFFh
280000h-2FFFFFh
200000h-27FFFFh
180000h-1FFFFFh
100000h-17FFFFh
080000h-0FFFFFh
000000h-07FFFFh
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
P/N: PM1842
REV. 1.2, NOV. 06, 2013
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MX25L6439E
Please be noticed that software reset command is not accepted after erase suspend command, but user still can
issue hardware reset function.
After issue erase suspend command, latency time 20us is needed before issue another command.
Erase Suspend Bit (ESB) indicates the status of Erase Suspend operation. Users may use ESB to identify the
state of flash memory. After the flash memory is suspended by Erase Suspend command, ESB is set to "1". ESB
is cleared to "0" after erase operation resumes.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
When ESB is issued, the Write Enable Latch (WEL) bit will be reset. Please refer to "Figure 55. Suspend to Read
Latency" for Suspend to Read latency.
11-34. Program Suspend
Program suspend allows the interruption of all program operations.
After program suspend, WEL bit will be cleared, only read related, resume and reset command can be accepted.
(including: 03h, 0Bh, BBh, EBh, E7h, 9Fh, AFh, 90h, 05h, 2Bh, B1h, C1h, 5Ah, 3Ch, 7Ah, 66h, 99h, 77h, 35h,
F5h, 00h, ABh )
After issue program suspend command, latency time 20us is needed before issue another command.
For "Suspend to Read", "Resume to Read", "Resume to Suspend" timing specification please note.
Program Suspend Bit (PSB) indicates the status of Program Suspend operation. Users may use PSB to identify
the state of flash memory. After the flash memory is suspended by Program Suspend command, PSB is set to
"1". PSB is cleared to "0" after program operation resumes
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
P/N: PM1842
REV. 1.2, NOV. 06, 2013
64
MX25L6439E
11-35. Write-Resume
The Write operation is being resumed when Write-Resume instruction issued. ESB or PSB (suspend status bit)
in Status register will be changed back to “0”
The operation of Write-Resume is as follows: CS# drives low → send write resume command cycle (7Ah) →
drive CS# high. By polling Busy Bit in status register, the internal write operation status could be checked to be
completed or not. The user may also wait the time lag of tSE, tBE, tBE32K, tPP for Sector-erase, Block-erase or
Page-programming. WREN (command "06" is not required to issue before resume. Resume to another suspend
operation requires latency time of 1ms.
When Erase Suspend is being resumed, the WEL bit need to be set again if user desire to conduct the program
or erase operation.
Please note that, if "performance enhance mode" is executed during suspend operation, the device can not
be resume. To restart the write command, disable the "performance enhance mode" is required. After the
"performance enhance mode" is disable, the write-resume command is effective.
Figure 55. Suspend to Read Latency
Program latency : 20us
Erase latency:20us
Suspend Command
[75]
Read Command
CS#
Figure 56. Resume to Read Latency
tSE/tBE/tBE32K/tPP
Resume Command
Read Command
CS#
[7A]
Figure 57. Resume to Suspend Latency
1ms
Suspend
Command
[75]
Resume Command
CS#
[7A]
P/N: PM1842
REV. 1.2, NOV. 06, 2013
65
MX25L6439E
11-36. No Operation (NOP)
The "No Operation" command is only able to terminate the Reset Enable (RSTEN) command and will not affect
any other command.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
11-37. Software Reset (Reset-Enable (RSTEN) and Reset (RST))
The Software Reset operation combines two instructions: Reset-Enable (RSTEN) command and Reset (RST)
command. It returns the device to a standby mode. All the volatile bits and settings will be cleared then, which
makes the device return to the default status as power on.
To execute Reset command (RST), the Reset-Enable (RSTEN) command must be executed first to perform the
Reset operation. If there is any other command to interrupt after the Reset-Enable command, the Reset-Enable
will be invalid.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
If the Reset command is executed during program or erase operation, the operation will be disabled, the data un-
der processing could be damaged or lost.
The reset time is different depending on the last operation. Longer latency time is required to recover from a pro-
gram operation than from other operations.
Figure 58. Software Reset Recovery
Stand-by Mode
66
99
CS#
tRCR
tRCP
tRCE
Mode
tRCR: 200ns (Recovery Time from Read)
tRCP: 20us (Recovery Time from Program)
tRCE: 12ms (Recovery Time from Erase)
11-38. Reset Quad I/O (RSTQIO)
The Reset Quad I/O instruction, F5H, resets the device to 1-bit SPI protocol operation. To execute a Reset Quad
I/O operation, the host drives CS# low, sends the Reset Quad I/O command cycle (F5h) then, drives CS# high.
QPI (2 clocks) command cycle can accept by this instruction.
Note:
For EQIO and RSTQIO commands, CS# high width has to follow "write spec" tSHSL for next instruction.
P/N: PM1842
REV. 1.2, NOV. 06, 2013
66
MX25L6439E
11-39. Read SFDP Mode (RDSFDP)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the
functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These
parameter tables can be interrogated by host system software to enable adjustments needed to accommodate
divergent features from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC
Standard, JESD68 on CFI.
The sequence of issuing RDSFDP instruction is same as CS# goes low→send RDSFDP instruction (5Ah)→send
3 address bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP operation
can use CS# to high at any time during data out.
SFDP is a JEDEC Standard, JESD216.
Figure 59. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
SCLK
Command
5Ah
24 BIT ADDRESS
SI
23 22 21
3
2
1
0
High-Z
SO
CS#
47
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
SCLK
Dummy Cycle
7
6
5
4
3
2
0
1
SI
DATA OUT 2
DATA OUT 1
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
SO
MSB
MSB
MSB
P/N: PM1842
REV. 1.2, NOV. 06, 2013
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MX25L6439E
Table 9. Signature and Parameter Identification Data Values
Description Comment
Add (h) DW Add Data (h/b) Data
(Byte)
(Bit)
(Note1)
(h)
00h
07:00
53h
53h
01h
02h
03h
04h
05h
15:08
23:16
31:24
07:00
15:08
46h
44h
50h
00h
01h
46h
44h
50h
00h
01h
SFDP Signature
Fixed: 50444653h
SFDP Minor Revision Number
SFDP Major Revision Number
Start from 00h
Start from 01h
This number is 0-based. Therefore,
0 indicates 1 parameter header.
Number of Parameter Headers
Unused
06h
07h
08h
09h
0Ah
0Bh
23:16
31:24
07:00
15:08
23:16
31:24
01h
FFh
00h
00h
01h
09h
01h
FFh
00h
00h
01h
09h
00h: it indicates a JEDEC specified
header.
ID number (JEDEC)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length
(in double word)
Start from 00h
Start from 01h
How many DWORDs in the
Parameter table
0Ch
0Dh
0Eh
07:00
15:08
23:16
30h
00h
00h
30h
00h
00h
First address of JEDEC Flash
Parameter table
Parameter Table Pointer (PTP)
Unused
0Fh
10h
11h
12h
13h
31:24
07:00
15:08
23:16
31:24
FFh
C2h
00h
01h
04h
FFh
C2h
00h
01h
04h
ID number
(Macronix manufacturer ID)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
it indicates Macronix manufacturer
ID
Start from 00h
Start from 01h
Parameter Table Length
(in double word)
How many DWORDs in the
Parameter table
14h
15h
16h
07:00
15:08
23:16
60h
00h
00h
60h
00h
00h
First address of Macronix Flash
Parameter table
Parameter Table Pointer (PTP)
Unused
17h
31:24
FFh
FFh
P/N: PM1842
REV. 1.2, NOV. 06, 2013
68
MX25L6439E
Table 10. Parameter Table (0): JEDEC Flash Parameter Tables
Add (h) DW Add Data (h/b) Data
Description
Comment
(Byte)
(Bit)
(Note1)
(h)
00: Reserved, 01: 4KB erase,
10: Reserved,
11: not support 4KB erase
Block/Sector Erase sizes
Write Granularity
01:00
01b
0: 1Byte, 1: 64Byte or larger
02
03
1b
0b
Write Enable Instruction Required 0: not required
for Writing to Volatile Status
1: required 00h to be written to the
Registers
status register
30h
E5h
0: use 50h opcode,
1: use 06h opcode
Write Enable Opcode Select for
Writing to Volatile Status Registers
Note: If target flash status register is
nonvolatile, then bits 3 and 4 must
be set to 00b.
04
0b
Contains 111b and can never be
changed
Unused
07:05
111b
4KB Erase Opcode
31h
32h
33h
15:08
16
20h
0b
20h
E0h
FFh
(1-1-2) Fast Read (Note2)
0=not support 1=support
Address Bytes Number used in
addressing flash array
00: 3Byte only, 01: 3 or 4Byte,
10: 4Byte only, 11: Reserved
18:17
19
00b
0b
Double Transfer Rate (DTR)
Clocking
0=not support 1=support
(1-2-2) Fast Read
(1-4-4) Fast Read
(1-1-4) Fast Read
Unused
0=not support 1=support
0=not support 1=support
0=not support 1=support
20
21
0b
1b
22
1b
23
1b
Unused
31:24
FFh
Flash Memory Density
37h:34h 31:00
03FF FFFFh
(1-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
04:00
38h
0 0100b
states (Note3)
Clocks) not support
44h
(1-4-4) Fast Read Number of
Mode Bits (Note4)
000b: Mode Bits not support
07:05
010b
EBh
(1-4-4) Fast Read Opcode
39h
3Ah
3Bh
15:08
20:16
EBh
08h
6Bh
(1-1-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
0 1000b
states
Clocks) not support
(1-1-4) Fast Read Number of
Mode Bits
000b: Mode Bits not support
23:21
31:24
000b
6Bh
(1-1-4) Fast Read Opcode
P/N: PM1842
REV. 1.2, NOV. 06, 2013
69
MX25L6439E
Add (h) DW Add Data (h/b) Data
Description
Comment
(Byte)
(Bit)
(Note1)
(h)
(1-1-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy
04:00
0 0000b
states
Clocks) not support
3Ch
00h
(1-1-2) Fast Read Number of
Mode Bits
000b: Mode Bits not support
07:05
15:08
20:16
000b
FFh
(1-1-2) Fast Read Opcode
3Dh
3Eh
3Fh
FFh
00h
FFh
(1-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy
0 0000b
states
Clocks) not support
(1-2-2) Fast Read Number of
Mode Bits
000b: Mode Bits not support
23:21
000b
(1-2-2) Fast Read Opcode
(2-2-2) Fast Read
Unused
31:24
00
FFh
0b
0=not support 1=support
0=not support 1=support
03:01
04
111b
1b
40h
FEh
(4-4-4) Fast Read
Unused
07:05
111b
FFh
FFh
Unused
43h:41h 31:08
45h:44h 15:00
FFh
FFh
Unused
(2-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy
20:16
46h
0 0000b
000b
states
Clocks) not support
00h
(2-2-2) Fast Read Number of
Mode Bits
000b: Mode Bits not support
23:21
(2-2-2) Fast Read Opcode
Unused
47h
31:24
FFh
FFh
FFh
FFh
49h:48h 15:00
(4-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
20:16
4Ah
0 0100b
states
Clocks) not support
44h
(4-4-4) Fast Read Number of
Mode Bits
000b: Mode Bits not support
23:21
010b
EBh
0Ch
20h
0Fh
52h
10h
D8h
00h
FFh
(4-4-4) Fast Read Opcode
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
53h
31:24
07:00
15:08
23:16
31:24
07:00
15:08
23:16
31:24
EBh
0Ch
20h
0Fh
52h
10h
D8h
00h
FFh
Sector/block size = 2^N bytes (Note5)
0x00b: this sector type doesn't exist
Sector Type 1 Size
Sector Type 1 erase Opcode
Sector Type 2 Size
Sector/block size = 2^N bytes
0x00b: this sector type doesn't exist
Sector Type 2 erase Opcode
Sector Type 3 Size
Sector/block size = 2^N bytes
0x00b: this sector type doesn't exist
Sector Type 3 erase Opcode
Sector Type 4 Size
Sector/block size = 2^N bytes
0x00b: this sector type doesn't exist
Sector Type 4 erase Opcode
P/N: PM1842
REV. 1.2, NOV. 06, 2013
70
MX25L6439E
Table 11. Parameter Table (1): Macronix Flash Parameter Tables
Add (h) DW Add Data (h/b) Data
Description
Comment
2000h=2.000V
2700h=2.700V
3600h=3.600V
(Byte)
(Bit)
(Note1)
(h)
07:00
15:08
00h
36h
00h
36h
Vcc Supply Maximum Voltage
61h:60h
1650h=1.650V
2250h=2.250V
2350h=2.350V
2700h=2.700V
23:16
31:24
00h
27h
00h
27h
Vcc Supply Minimum Voltage
H/W Reset# pin
63h:62h
0=not support 1=support
00
0b
H/W Hold# pin
0=not support 1=support
0=not support 1=support
0=not support 1=support
01
02
03
1b
1b
1b
Deep Power Down Mode
S/W Reset
Reset Enable (66h) should be
issued before Reset Opcode
1001 1001b
(99h)
65h:64h
F99Eh
S/W Reset Opcode
11:04
Program Suspend/Resume
Erase Suspend/Resume
Unused
0=not support 1=support
0=not support 1=support
12
13
1b
1b
14
1b
Wrap-Around Read mode
Wrap-Around Read mode Opcode
0=not support 1=support
15
1b
66h
67h
23:16
77h
77h
64h
08h:support 8B wrap-around read
16h:8B&16B
32h:8B&16B&32B
Wrap-Around Read data length
31:24
64h
64h:8B&16B&32B&64B
Individual block lock
0=not support 1=support
00
01
1b
0b
Individual block lock bit
(Volatile/Nonvolatile)
0=Volatile 1=Nonvolatile
Individual block lock Opcode
09:02 0011 0110b
Individual block lock Volatile
protect bit default protect status
0=protect 1=unprotect
10
0b
C8D9h
6Bh:68h
Secured OTP
Read Lock
Permanent Lock
Unused
0=not support 1=support
0=not support 1=support
0=not support 1=support
11
12
1b
0b
13
0b
15:14
31:16
11b
FFh
FFh
Unused
FFh
FFh
Unused
6Fh:6Ch 31:00
P/N: PM1842
REV. 1.2, NOV. 06, 2013
71
MX25L6439E
Note 1: h/b is hexadecimal or binary.
Note 2: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x),
address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1),
(2-2-2), and (4-4-4)
Note 3: Wait States is required dummy clock cycles after the address bits or optional mode bits.
Note 4: Mode Bits is optional control bits that follow the address bits. These bits are driven by the system
controller if they are specified. (eg,read performance enhance toggling bits)
Note 5: 4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h
Note 6: All unused and undefined area data is blank FFh.
P/N: PM1842
REV. 1.2, NOV. 06, 2013
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MX25L6439E
12. POWER-ON STATE
The device is at below states when power-up:
- Standby mode
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage unless the VCC achieves below cor-
rect level:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal Power-on Reset (POR) circuit may protect the device from data corruption and inadvertent data
change during power up state.
For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is
not guaranteed. The read, write, erase, and program command should be sent after the time delay:
- tVSL after VCC reached VCC minimum level
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommend-
ed. (generally around 0.1uF)
P/N: PM1842
REV. 1.2, NOV. 06, 2013
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MX25L6439E
13. ELECTRICAL SPECIFICATIONS
13-1. ABSOLUTE MAXIMUM RATINGS
RATING
VALUE
Ambient Operating Temperature
Storage Temperature
Applied Input Voltage
Applied Output Voltage
VCC to Ground Potential
Industrial grade
-40°C to 85°C
-65°C to 150°C
-0.5V to VCC+0.5V
-0.5V to VCC+0.5V
-0.5V to 4.0V
NOTICE:
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. This is stress rating only and functional operational sections of this specification is not implied. Expo-
sure to absolute maximum rating conditions for extended period may affect reliability.
2. Specifications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see
the figures below.
Figure 61. Maximum Positive Overshoot Waveform
Figure 60. Maximum Negative Overshoot Waveform
20ns
20ns
20ns
Vcc + 2.0V
Vcc
Vss
Vss-2.0V
20ns
20ns
20ns
13-2. CAPACITANCE TA = 25°C, f = 1.0 MHz
Symbol Parameter
Min.
Typ.
Max.
Unit
pF
Conditions
VIN = 0V
CIN
Input Capacitance
6
8
COUT Output Capacitance
pF
VOUT = 0V
P/N: PM1842
REV. 1.2, NOV. 06, 2013
74
MX25L6439E
Figure 62. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL
Input timing reference level
Output timing reference level
0.8VCC
0.2VCC
0.7VCC
0.3VCC
AC
Measurement
Level
0.5VCC
Note: Input pulse rise and fall time are <5ns
Figure 63. OUTPUT LOADING
DEVICE UNDER
TEST
2.7K ohm
+3.3V
CL
6.2K ohm
DIODES=IN3064
OR EQUIVALENT
CL=30/15pF Including jig capacitance
P/N: PM1842
REV. 1.2, NOV. 06, 2013
75
MX25L6439E
Table 12. DC CHARACTERISTICS
Temperature = -40°C to 85°C for Industrial grade
Symbol Parameter
Notes Min.
Typ.
Max. Units Test Conditions
VCC = VCC Max,
VIN = VCC or GND
VCC = VCC Max,
VOUT = VCC or GND
ILI
Input Load Current
Output Leakage Current
1
± 2
uA
uA
ILO
1
1
± 2
50
25
ISB1 VCC Standby Current
15
1
uA VIN = VCC or GND, CS# = VCC
uA VIN = VCC or GND, CS# = VCC
Deep Power-down
Current
ISB2
f=104MHz (4 x I/O read)
mA SCLK=0.1VCC/0.9VCC,
SO=Open
35
19
25
10
f=104MHz (1 x I/O read)
mA SCLK=0.1VCC/0.9VCC,
SO=Open
ICC1 VCC Read
1
1
fQ=86MHz (4 x I/O read)
mA SCLK=0.1VCC/0.9VCC,
SO=Open
f=33MHz,
mA SCLK=0.1VCC/0.9VCC,
SO=Open
VCC Program Current
Program in Progress, CS# =
VCC
ICC2
(PP)
15
15
10
15
25
20
25
25
mA
VCC Write Status
ICC3
Program status register in
mA
Register (WRSR) Current
progress, CS#=VCC
VCC Sector Erase
ICC4
1
1
mA Erase in Progress, CS#=VCC
mA Erase in Progress, CS#=VCC
Current (SE)
VCC Chip Erase Current
ICC5
(CE)
VIL
Input Low Voltage
Input High Voltage
-0.5
0.8
V
V
VIH
0.7VCC
VCC+0.4
VOL
Output Low Voltage
0.4
V
V
IOL = 1.6mA
IOH = -100uA
VOH Output High Voltage
Notes :
VCC-0.2
1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and
speeds).
2. Typical value is calculated by simulation.
3. The value guaranteed by characterization, not 100% tested in production.
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MX25L6439E
Table 13. AC CHARACTERISTICS
Temperature = -40°C to 85°C for Industrial grade
Symbol Alt. Parameter
Min.
Typ.
Max. Unit
Clock Frequency for the following instructions:
fSCLK
fC FAST_READ, PP, SE, BE, CE, RES, WREN, WRDI, RDID,
RDSR, WRSR
D.C.
104
MHz
fRSCLK
fTSCLK
f4PP
fR Clock Frequency for READ instructions
fQ Clock Frequency for 4READ/QREAD instructions (4)
Clock Frequency for 4PP (Quad page program)
Others
50
86
104
MHz
MHz
MHz
4.5
9
ns
ns
(fSCLK: 104MHz)
Normal Read
(fRSCLK: 50MHz)
tCH(1) tCLH Clock High Time
Others (fSCLK)
Normal Read (fRSCLK)
4.5
9
0.1
0.1
4
4
2
3
4
ns
ns
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCL(1)
tCLL Clock Low Time
Clock Rise Time (3) (peak to peak)
Clock Fall Time (3) (peak to peak)
tCLCH
tCHCL
tSLCH tCSS CS# Active Setup Time (relative to SCLK)
tCHSL CS# Not Active Hold Time (relative to SCLK)
tDVCH tDSU Data In Setup Time
tCHDX
tCHSH
tSHCH
tDH Data In Hold Time
CS# Active Hold Time (relative to SCLK)
CS# Not Active Setup Time (relative to SCLK)
Read
4
15
50
tSHSL(3) tCSH CS# Deselect Time
Write/Erase/Program
2.7V-3.6V
3.0V-3.6V
10
8
tSHQZ
tDIS Output Disable Time
tHLCH
tCHHH
tHHCH
tCHHL
HOLD# Setup Time (relative to SCLK)
HOLD# Hold Time (relative to SCLK)
HOLD Setup Time (relative to SCLK)
HOLD Hold Time (relative to SCLK)
5
5
5
5
2.7V-3.6V
3.0V-3.6V
2.7V-3.6V
3.0V-3.6V
1 I/O
10
8
10
8
HOLD to Output Low-Z
Loading=30pF
tHHQX
tLZ
HOLD# to Output High-Z
Loading=30pF
tHLQZ
tHZ
tV
5
Loading:
10pF
4 I/O
7.5
ns
Clock Low to Output Valid
VCC=2.7V~3.6V
1 I/O
4 I/O
1 I/O
4 I/O
6
8
7
8
ns
ns
ns
ns
ns
ns
ns
us
Loading:
15pF
tCLQV
Loading:
30pF
tCLQX
tWHSL
tSHWL
tDP
tHO Output Hold Time
Write Protect Setup Time
Write Protect Hold Time
CS# High to Deep Power-down Mode
1
20
100
10
CS# High to Standby Mode without Electronic Signature
Read
CS# High to Standby Mode with Electronic Signature Read
tRES1
tRES2
100
100
us
us
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REV. 1.2, NOV. 06, 2013
77
MX25L6439E
Symbol Alt. Parameter
Min.
Typ.
Max.
40
50
3
200
1.6
2
80
1
1
Unit
ms
us
ms
ms
s
s
s
ms
ms
tW
tBP
Write Status Register Cycle Time
Byte-Program
12
0.7
30
0.14
0.25
20
tPP
tSE
tBE32K
tBE
tCE
Page Program Cycle Time
Sector Erase Cycle Time (4KB)
Block Erase Cycle Time (32KB)
Block Erase Cycle Time (64KB)
Chip Erase Cycle Time
tWPS
tWSR
Write Protection Selection Time
Write Security Register Time
Notes:
1. tCH + tCL must be greater than or equal to 1/ fC.
2. The value guaranteed by characterization, not 100% tested in production.
3. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
4. For 4READ instruction, when dummy cycle=6 (in both SPI & QPI mode), clock rate is 86MHz, and when dum-
my cycle=8 (in both SPI & QPI mode), clock rate is 104MHz.
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REV. 1.2, NOV. 06, 2013
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MX25L6439E
14. TIMING ANALYSIS
Figure 64. Serial Input Timing
tSHSL
tSHCH
tCHCL
CS#
tCHSL
tSLCH
tCHSH
SCLK
tDVCH
tCHDX
tCLCH
MSB
LSB
SI
High-Z
SO
Figure 65. Output Timing
CS#
tCH
SCLK
tCLQV
tCLQV
tCL
tSHQZ
tCLQX
SO
tCLQX
LSB
ADDR.LSB IN
SI
P/N: PM1842
REV. 1.2, NOV. 06, 2013
79
MX25L6439E
Figure 66. Hold Timing
CS#
tHLCH
tCHHH
tCHHL
tHLQZ
tHHCH
tHHQX
SCLK
SO
HOLD#
Figure 67. WP# Setup Timing and Hold Timing during WRSR when SRWD=1
WP#
tSHWL
tWHSL
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12
13 14
15
SCLK
01
SI
High-Z
SO
P/N: PM1842
REV. 1.2, NOV. 06, 2013
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MX25L6439E
Figure 68. Power-Up Timing
V
CC
V
(max)
CC
Chip Selection is Not Allowed
V
(min)
CC
Device is fully accessible
tVSL
time
Note: VCC (max.) is 3.6V and VCC (min.) is 2.7V.
Table 14. Power-Up Timing
Symbol Parameter
Min.
Max.
Unit
tVSL(1)
VCC(min) to CS# low
300
us
Note: The parameter is characterized only.
14-1. INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status
Register contains 00h (all Status Register bits are 0).
P/N: PM1842
REV. 1.2, NOV. 06, 2013
81
MX25L6439E
15. OPERATING CONDITIONS
At Device Power-Up and Power-Down
AC timing illustrated in "Figure 69. AC Timing at Device Power-Up" and "Figure 70. Power-Down Sequence"
are for the supply voltages and the control signals at device power-up and power-down. If the timing in the fig-
ures is ignored, the device will not operate correctly.
During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be
selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.
Figure 69. AC Timing at Device Power-Up
VCC(min)
VCC
GND
tVR
tSHSL
CS#
tSHCH
tSLCH
tCHSL
tCHSH
SCLK
tDVCH
tCHCL
tCHDX
tCLCH
MSB IN
LSB IN
SI
High Impedance
SO
Symbol
tVR
Parameter
VCC Rise Time
Notes
Min.
20
Max.
500000
Unit
us/V
1
Notes :
1. Sampled, not 100% tested.
2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer
to "Table 13. AC CHARACTERISTICS".
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REV. 1.2, NOV. 06, 2013
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MX25L6439E
Figure 70. Power-Down Sequence
During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.
VCC
CS#
SCLK
P/N: PM1842
REV. 1.2, NOV. 06, 2013
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MX25L6439E
16. ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ. (1)
Max. (2)
Unit
ms
ms
s
Write Status Register Cycle Time
Sector Erase Time (4KB)
Block Erase Time (32KB)
Block Erase Time (64KB)
Chip Erase Time
40
200
1.6
2
30
0.14
0.25
20
s
80
50
3
s
Byte Program Time (via page program command)
Page Program Time
12
us
0.7
ms
cycles
Erase/Program Cycle
100,000
Notes:
1. Typical program and erase time assumes the following conditions: 25°C, 3.3V, and checker board pattern.
2. Under worst conditions of 85°C and 2.7V.
3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming com-
mand.
17. DATA RETENTION
Parameter
Condition
Min.
Max.
Unit
Data retention
55˚C
20
years
18. LATCH-UP CHARACTERISTICS
Min.
Max.
Input Voltage with respect to GND on all power pins, SI, CS#
Input Voltage with respect to GND on SO
Current
-1.0V
-1.0V
-100mA
2 VCCmax
VCC + 1.0V
+100mA
Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.
P/N: PM1842
REV. 1.2, NOV. 06, 2013
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MX25L6439E
19. ORDERING INFORMATION
PART NO.
CLOCK (MHz)
TEMPERATURE
PACKAGE
8-SOP
(200mil)
8-VSOP
(200mil)
Remark
MX25L6439EM2I-10G *
104
104
-40°C~85°C
MX25L6439EMBI-10G
* Advanced Information
-40°C~85°C
P/N: PM1842
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MX25L6439E
20. PART NAME DESCRIPTION
MX M2
25 L 6439E
I
10 G
OPTION:
G: RoHS Compliant and Halogen-free
SPEED:
10: 104MHz
TEMPERATURE RANGE:
I: Industrial (-40° C to 85° C)
PACKAGE:
M2: 200mil 8-SOP
MB: 200mil 8-VSOP
DENSITY & MODE:
6439E: 64Mb standard type
TYPE:
L: 3V
DEVICE:
25: Serial Flash
P/N: PM1842
REV. 1.2, NOV. 06, 2013
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MX25L6439E
21. PACKAGE INFORMATION
P/N: PM1842
REV. 1.2, NOV. 06, 2013
87
MX25L6439E
P/N: PM1842
REV. 1.2, NOV. 06, 2013
88
MX25L6439E
22. REVISION HISTORY
Revision No. Description
Page
All
P4
Date
JUN/22/2012
OCT/09/2012
0.00
1.0
1. Initial released
1. Removed "Advanced Information" status
2. Updated tSLCH, tCHSL, tCHSH, tSHCH value in AC
Characteristics Table
P75
1.1
1.2
1. Modified Erase Suspend section
P62
JAN/23/2013
NOV/06/2013
1. Updated parameters for DC/AC Characteristics
2. Updated Erase and Programming Performance
3. Modified Absolute Maximum Ratings & Capacitance table
P4,76,78
P4,84
P74
P/N: PM1842
REV. 1.2, NOV. 06, 2013
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MX25L6439E
Except for customized products which has been expressly identified in the applicable agreement, Macronix's
products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or
household applications only, and not for use in any applications which may, directly or indirectly, cause death,
personal injury, or severe property damages. In the event Macronix products are used in contradicted to their
target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its
actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or
distributors shall be released from any and all liability arisen therefrom.
Copyright© Macronix International Co., Ltd. 2012~2013. All rights reserved, including the trademarks and
tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit,
NBiit, Macronix NBit, eLiteFlash, HybridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC,
Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich Audio, Rich Book, Rich TV, and FitCAM. The names
and brands of third party referred thereto (if any) are for identification purposes only.
For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
90
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