MX25L6445EM [Macronix]
HIGH PERFORMANCE SERIAL FLASH SPECIFICATION; 高性能串行闪存规格
| 型号： | MX25L6445EM |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | HIGH PERFORMANCE SERIAL FLASH SPECIFICATION |
| 文件： | 总72页 (文件大小：2176K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MX25L6445E
MX25L6445E
HIGH PERFORMANCE
SERIAL FLASH SPECIFICATION
P/N: PM1736
REV. 1.8, DEC. 26, 2011
1
MX25L6445E
Contents
FEATURES ..................................................................................................................................................................5
GENERAL DESCRIPTION .........................................................................................................................................7
Table 1. Additional Features ..............................................................................................................................7
PIN CONFIGURATION ................................................................................................................................................8
PIN DESCRIPTION......................................................................................................................................................8
BLOCK DIAGRAM.......................................................................................................................................................9
DATA PROTECTION..................................................................................................................................................10
Table 2. Protected Area Sizes.......................................................................................................................... 11
Table 3. 4K-bit Secured OTP Definition............................................................................................................ 11
Memory Organization...............................................................................................................................................12
Table 4. Memory Organization .........................................................................................................................12
DEVICE OPERATION................................................................................................................................................13
Figure 1-1. Serial Modes Supported (for Normal Serial mode)........................................................................ 13
Figure 1-2. Serial Modes Supported (for Double Transfer Rate serial read mode)..........................................13
COMMAND DESCRIPTION.......................................................................................................................................14
Table 5. Command Sets...................................................................................................................................14
(1) Write Enable (WREN).................................................................................................................................16
(2) Write Disable (WRDI)..................................................................................................................................16
(3) Read Identification (RDID)..........................................................................................................................16
(4) Read Status Register (RDSR)....................................................................................................................17
(5) Write Status Register (WRSR)....................................................................................................................18
Protection Modes .............................................................................................................................................18
(6) Read Data Bytes (READ) ...........................................................................................................................19
(7) Read Data Bytes at Higher Speed (FAST_READ) .....................................................................................19
(8) Fast Double Transfer Rate Read (FASTDTRD)..........................................................................................19
(9) 2 x I/O Read Mode (2READ) ......................................................................................................................19
(10) 2 x I/O Double Transfer Rate Read Mode (2DTRD)................................................................................. 20
(11) 4 x I/O Read Mode (4READ).....................................................................................................................20
(12) 4 x I/O Double Transfer Rate Read Mode (4DTRD)................................................................................. 21
(13) Sector Erase (SE).....................................................................................................................................21
(14) Block Erase (BE).......................................................................................................................................22
(15) Block Erase (BE32K)................................................................................................................................22
(16) Chip Erase (CE)........................................................................................................................................22
(17) Page Program (PP)...................................................................................................................................23
(18) 4 x I/O Page Program (4PP).....................................................................................................................23
Program/Erase Flow(1) with read array data ...................................................................................................24
Program/Erase Flow(2) without read array data ..............................................................................................25
(19) Continuously program mode (CP mode) ..................................................................................................26
(20) Deep Power-down (DP)............................................................................................................................27
(21) Release from Deep Power-down (RDP), Read Electronic Signature (RES) ............................................27
(22) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4), (REMS4D)....................... 27
Table 6. ID Definitions .....................................................................................................................................28
(23) Enter Secured OTP (ENSO).....................................................................................................................28
(24) Exit Secured OTP (EXSO)........................................................................................................................28
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REV. 1.8, DEC. 26, 2011
2
MX25L6445E
(25) Read Security Register (RDSCUR) ..........................................................................................................28
Security Register Definition..............................................................................................................................29
(26) Write Security Register (WRSCUR)..........................................................................................................29
(27) Write Protection Selection (WPSEL).........................................................................................................30
BP and SRWD if WPSEL=0 .............................................................................................................................30
The individual block lock mode is effective after setting WPSEL=1................................................................. 31
WPSEL Flow ....................................................................................................................................................32
(28) Single Block Lock/Unlock Protection (SBLK/SBULK)............................................................................... 33
Block Lock Flow ...............................................................................................................................................33
Block Unlock Flow............................................................................................................................................34
(29) Read Block Lock Status (RDBLOCK).......................................................................................................35
(30) Gang Block Lock/Unlock (GBLK/GBULK).................................................................................................35
(31) Clear SR Fail Flags (CLSR)......................................................................................................................35
(32) Enable SO to Output RY/BY# (ESRY)......................................................................................................35
(33) Disable SO to Output RY/BY# (DSRY).....................................................................................................35
(34) Read SFDP Mode (RDSFDP)...................................................................................................................36
POWER-ON STATE...................................................................................................................................................42
ELECTRICAL SPECIFICATIONS..............................................................................................................................43
ABSOLUTE MAXIMUM RATINGS...................................................................................................................43
Figure 2. Maximum Negative Overshoot Waveform ........................................................................................43
CAPACITANCE TA = 25°C, f = 1.0 MHz...........................................................................................................43
Figure 3. Maximum Positive Overshoot Waveform..........................................................................................43
Figure 4. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL............................................................ 44
Figure 5. OUTPUT LOADING .........................................................................................................................44
Table 10. DC CHARACTERISTICS .................................................................................................................45
Table 11. AC CHARACTERISTICS ..................................................................................................................46
Timing Analysis........................................................................................................................................................48
Figure 6. Serial Input Timing ............................................................................................................................48
Figure 7. Output Timing....................................................................................................................................48
Figure 8. Serial Input Timing for Double Transfer Rate Mode.......................................................................... 49
Figure 9. Serial Output Timing for Double Transfer Rate Mode....................................................................... 49
Figure 10. WP# Setup Timing and Hold Timing during WRSR when SRWD=1............................................... 50
Figure 11. Write Enable (WREN) Sequence (Command 06) ........................................................................... 50
Figure 12. Write Disable (WRDI) Sequence (Command 04)............................................................................ 50
Figure 13. Read Identification (RDID) Sequence (Command 9F).................................................................... 51
Figure 14. Read Status Register (RDSR) Sequence (Command 05).............................................................. 51
Figure 15. Write Status Register (WRSR) Sequence (Command 01)............................................................. 51
Figure 16. Read Data Bytes (READ) Sequence (Command 03) .................................................................... 52
Figure 17. Read at Higher Speed (FAST_READ) Sequence (Command 0B) ................................................ 52
Figure 18. Fast DT Read (FASTDTRD) Sequence (Command 0D)................................................................. 52
Figure 19. 2 x I/O Read Mode Sequence (Command BB)...............................................................................53
Figure 20. Fast Dual I/O DT Read (2DTRD) Sequence (Command BD)......................................................... 53
Figure 21. 4 x I/O Read Mode Sequence (Command EB)...............................................................................54
Figure 22. 4 x I/O Read Enhance Performance Mode Sequence (Command EB)..........................................54
Figure 23. Fast Quad I/O DT Read (4DTRD) Sequence (Command ED)........................................................ 55
Figure 24. Fast Quad I/O DT Read (4DTRD) Enhance Performance Sequence (Command ED)................... 55
P/N: PM1736
REV. 1.8, DEC. 26, 2011
3
MX25L6445E
Figure 25. Sector Erase (SE) Sequence (Command 20)................................................................................56
Figure 26. Block Erase (BE/BE32K) Sequence (Command D8/52)................................................................ 56
Figure 27. Chip Erase (CE) Sequence (Command 60 or C7)......................................................................... 56
Figure 28. Page Program (PP) Sequence (Command 02).............................................................................. 57
Figure 29. 4 x I/O Page Program (4PP) Sequence (Command 38)................................................................ 57
Figure 30. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD)................. 58
Figure 31. Deep Power-down (DP) Sequence (Command B9)....................................................................... 58
Figure 32. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB)
.........................................................................................................................................................................59
Figure 33. Release from Deep Power-down (RDP) Sequence (Command AB) .............................................59
Figure 34. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF or CF)..
.........................................................................................................................................................................60
Figure 35. Write Protection Selection (WPSEL) Sequence (Command 68).................................................... 60
Figure 36. Single Block Lock/Unlock Protection (SBLK/SBULK) Sequence (Command 36/39)..................... 61
Figure 37. Read Block Protection Lock Status (RDBLOCK) Sequence (Command 3C)................................ 61
Figure 38. Gang Block Lock/Unlock (GBLK/GBULK) Sequence (Command 7E/98)...................................... 61
Figure 39. Power-up Timing.............................................................................................................................62
Table 12. Power-Up Timing .............................................................................................................................62
INITIAL DELIVERY STATE...............................................................................................................................62
OPERATING CONDITIONS.......................................................................................................................................63
Figure 40. AC Timing at Device Power-Up.......................................................................................................63
Figure 41. Power-Down Sequence ..................................................................................................................64
ERASE AND PROGRAMMING PERFORMANCE....................................................................................................65
DATA RETENTION ....................................................................................................................................................65
LATCH-UP CHARACTERISTICS..............................................................................................................................65
ORDERING INFORMATION......................................................................................................................................66
PART NAME DESCRIPTION.....................................................................................................................................67
PACKAGE INFORMATION........................................................................................................................................68
REVISION HISTORY .................................................................................................................................................71
P/N: PM1736
REV. 1.8, DEC. 26, 2011
4
MX25L6445E
64M-BIT [x 1/x 2/x 4] CMOS MXSMIOTM (SERIAL MULTI I/O) FLASH MEMORY
FEATURES
GENERAL
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• 64Mb: 67,108,864 x 1 bit structure or 33,554,432 x 2 bits (two I/O mode) structure or 16,777,216 x 4 bits (four I/
O mode) structure
• 2048 Equal Sectors with 4K bytes each
- Any Sector can be erased individually
• 256 Equal Blocks with 32K bytes each
- Any Block can be erased individually
• 128 Equal Blocks with 64K bytes each
- Any Block can be erased individually
• Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
VCC = 2.7~3.6V
- Normal read
- 50MHz
- Fast read (Normal Serial Mode)
- 1 I/O: 104MHz with 8 dummy cycles
- 2 I/O: 70MHz with 4 dummy cycles
- 4 I/O: 70MHz with 6 dummy cycles
- Fast read (Double Transfer Rate Mode)
- 1 I/O: 50MHz with 6 dummy cycles
- 2 I/O: 50MHz with 6 dummy cycles
- 4 I/O: 50MHz with 8 dummy cycles
- Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)
- Byte program time: 9us (typical)
- Continuously Program mode (automatically increase address under word program mode)
- Fast erase time: 60ms (typ.)/sector (4K-byte per sector) ; 0.7s(typ.) /block (64K-byte per block); 50s(typ.) /chip
• Low Power Consumption
- Low active read current: 19mA(max.) at 104MHz, 15mA(max.) at 66MHz and 10mA(max.) at 33MHz
- Low active programming current: 25mA (max.)
- Low active erase current: 25mA (max.)
- Low standby current: 50uA (max.)
- Deep power down current: 20uA (max.)
• Typical 100,000 erase/program cycles
• 20 years data retention
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
P/N: PM1736
REV. 1.8, DEC. 26, 2011
5
MX25L6445E
• Advanced Security Features
- BP0-BP3 block group protect
- Flexible individual block protect when OTP WPSEL=1
- Additional 4K bits secured OTP for unique identifier
• Auto Erase and Auto Program Algorithms
Automatically erases and verifies data at selected sector
-
-
Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse width (Any page to be programed should have page in the erased state first.)
• Status Register Feature
• Electronic Identification
JEDEC 1-byte Manufacturer ID and 2-byte Device ID
- RES command for 1-byte Device ID
-
- REMS, REMS2, REMS4 and REMS4D commands for 1-byte Manufacturer ID and 1-byte Device ID
• Support Serial Flash Discoverable Parameters (SFDP) mode
HARDWARE FEATURES
• SCLK Input
Serial clock input
• SI/SIO0
-
Serial Data Input or Serial Data Input/Output for 2 x I/O mode and 4 x I/O mode
• SO/SIO1
-
Serial Data Output or Serial Data Input/Output for 2 x I/O mode and 4 x I/O mode
• WP#/SIO2
-
Hardware write protection or serial data Input/Output for 4 x I/O mode
• NC/SIO3
-
NC pin or serial data Input/Output for 4 x I/O mode
• PACKAGE
-
16-pin SOP (300mil)
-
-
-
8-WSON (8 x 6mm)
8-pin SOP (200mil)
- All devices are RoHS Compliant
P/N: PM1736
REV. 1.8, DEC. 26, 2011
6
MX25L6445E
GENERAL DESCRIPTION
MX25L6445E is 67,108,864 bits serial Flash memory, which is configured as 8,388,608 x 8 internally. When it is in
two or four I/O mode, the structure becomes 33,554,432 bits x 2 or 16,777,216 bits x 4. The MX25L6445E features
a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals
are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is ena-
bled by CS# input.
MX25L6445E provides high performance read mode, which may latch address and data on both rising and falling
edge of clock. By using this high performance read mode, the data throughput may be doubling. Moreover, the per-
formance may reach direct code execution, the RAM size of the system may be reduced and further saving system
cost.
MX25L6445E, MXSMIOTM (Serial Multi I/O) flash memory, provides sequential read operation on the whole chip and
multi-I/O features.
When it is in dual I/O mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and
data output. When it is in quad I/O mode, the SI pin, SO pin, WP# pin and NC pin become SIO0 pin, SIO1 pin, SIO2
pin and SIO3 pin for address/dummy bits input and data Input/Output.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the speci-
fied page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis, or word basis. Continuously Program mode and erase command are executed on 4K-byte sector, 32K-
byte/64K-byte block, or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via the WIP bit.
When the device is not in operation and CS# is high, it is put in standby mode and draws less than 100uA DC cur-
rent.
The MX25L6445E utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after
100,000 program and erase cycles.
Table 1. Additional Features
Protection and Security
Flexible or
Read Performance
1 I/O DT
Additional
Features
2 I/O DT
Read
(50 MHz)
4 I/O DT
Read
(50 MHz)
Individual block
(or sector)
4K-bit
1 I/O Read 2 I/O Read 4 I/O Read
Part
Read
secured OTP (104 MHz)
(70 MHz)
(70 MHz)
Name
(50 MHz)
protection
MX25L6445E
V
V
V
V
V
V
V
V
Additional
Features
Identifier
RES
(command: AB
hex)
REMS
(command: 90
hex)
REMS2
(command: EF
hex)
REMS4
(command: DF
hex)
REMS4D
(command: CF
hex)
RDID
(command: 9F
hex)
Part
Name
MX25L6445E
16 (hex)
C2 16 (hex)
C2 16 (hex)
C2 16 (hex)
C2 16 (hex)
C2 20 17 (hex)
P/N: PM1736
REV. 1.8, DEC. 26, 2011
7
MX25L6445E
PIN CONFIGURATION
16-PIN SOP (300mil)
PIN DESCRIPTION
SYMBOL
DESCRIPTION
CS#
Chip Select
1
2
3
4
5
6
7
8
SCLK
SI/SIO0
NC
NC/SIO3
VCC
NC
16
15
14
13
12
11
10
9
Serial Data Input (for 1xI/O)/ Serial Data
Input & Output (for 2xI/O or 4xI/O mode)
Serial Data Output (for 1xI/O)/Serial
SI/SIO0
NC
NC
NC
NC
NC
NC
SO/SIO1 Data Input & Output (for 2xI/O or 4xI/O
mode)
GND
WP#/SIO2
CS#
SO/SIO1
SCLK
Clock Input
Write protection: connect to GND or
WP#/SIO2 Serial Data Input & Output (for 4xI/O
mode)
8-PIN SOP (200mil)
NC pin (Not connect) or Serial Data
Input & Output (for 4xI/O mode)
+ 3.3V Power Supply
Ground
No Connection
NC/SIO3
1
2
3
4
CS#
SO/SIO1
WP#/SIO2
GND
VCC
8
7
6
5
NC/SIO3
SCLK
VCC
GND
NC
SI/SIO0
8-WSON (8x6mm)
1
2
3
4
VCC
CS#
SO/SIO1
WP#/SIO2
GND
8
NC/SIO3
SCLK
7
6
5
SI/SIO0
P/N: PM1736
REV. 1.8, DEC. 26, 2011
8
MX25L6445E
BLOCK DIAGRAM
Address
Generator
Memory Array
Page Buffer
Y-Decoder
Data
Register
SI/SIO0
SRAM
Buffer
Sense
Amplifier
CS#
WP#/SIO2
NC/SIO3
Mode
Logic
State
Machine
HV
Generator
SCLK
Clock Generator
Output
Buffer
SO/SIO1
P/N: PM1736
REV. 1.8, DEC. 26, 2011
9
MX25L6445E
DATA PROTECTION
MX25L6445E is designed to offer protection against accidental erasure or programming caused by spurious system
level signals that may exist during power transition. During power up the device automatically resets the state ma-
chine in the standby mode. In addition, with its control register architecture, alteration of the memory contents only
occurs after successful completion of specific command sequences. The device also incorporates several features
to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise.
• Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before is-
suing other commands to change data. The WEL bit will return to reset stage under following situations:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP, 4PP) command completion
- Continuously Program mode (CP) instruction completion
- Sector Erase (SE) command completion
- Block Erase (BE, BE32K) command completion
- Chip Erase (CE) command completion
- Single Block Lock/Unlock (SBLK/SBULK) instruction completion
- Gang Block Lock/Unlock (GBLK/GBULK) instruction completion
•
Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from
writing all commands except Release from Deep Power Down mode command (RDP) and Read Electronic Sig-
nature command (RES).
I. Block lock protection
- The Software Protected Mode (SPM) uses (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected
as read only. The protected area definition is shown as table of "Protected Area Sizes", the protected areas are
more flexible which may protect various area by setting value of BP0-BP3 bits. Please refer to table of "Protect-
ed Area Sizes".
- The Hardware Protected Mode (HPM) uses WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and SRWD
bit. If the system goes into four I/O mode, the feature of HPM will be disabled.
- MX25L6445E provides individual block (or sector) write protect & unprotect. User may enter the mode with
WPSEL command and conduct individual block (or sector) write protect with SBLK instruction, or SBULK for
individual block (or sector) unprotect. Under the mode, user may conduct whole chip (all blocks) protect with
GBLK instruction and unlock the whole chip with GBULK instruction.
P/N: PM1736
REV. 1.8, DEC. 26, 2011
10
MX25L6445E
Table 2. Protected Area Sizes
Status bit
Protection Area
BP3
0
BP2
0
BP1
0
BP0
0
64Mb
0 (none)
0
0
0
1
1 (2 blocks, block 126th-127th)
2 (4 blocks, block 124th-127th)
3 (8 blocks, block 120th-127th)
4 (16 blocks, block 112nd-127th)
5 (32 blocks, block 96th-127th)
6 (64 blocks, block 64th-127th)
7 (128 blocks, all)
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
8 (128 blocks, all)
1
0
0
1
9 (128 blocks, all)
1
0
1
0
10 (128 blocks, all)
1
0
1
1
11 (128 blocks, all)
1
1
0
0
12 (128 blocks, all)
1
1
0
1
13 (128 blocks, all)
1
1
1
0
14 (128 blocks, all)
1
1
1
1
15 (128 blocks, all)
Note: The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP3, BP2, BP1, BP0) are 0.
II. Additional 4K-bit secured OTP for unique identifier: to provide 4K-bit One-Time Program area for setting de-
vice unique serial number - Which may be set by factory or system maker. Please refer to Table 3. 4K-bit Se-
cured OTP Definition.
- Security register bit 0 indicates whether the chip is locked by factory or not.
- To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with ENSO command), and going
through normal program procedure, and then exiting 4K-bit secured OTP mode by writing EXSO command.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register)
command to set customer lock-down bit1 as "1". Please refer to table of "Security Register Definition" for secu-
rity register bit definition and table of "4K-bit Secured OTP Definition" for address range definition.
- Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit Se-
cured OTP mode, array access is not allowed.
Table 3. 4K-bit Secured OTP Definition
Address range
xxx000~xxx00F
xxx010~xxx1FF
Size
Standard Factory Lock
ESN (electrical serial number)
N/A
Customer Lock
128-bit
3968-bit
Determined by customer
P/N: PM1736
REV. 1.8, DEC. 26, 2011
11
MX25L6445E
Memory Organization
Table 4. Memory Organization
Block(64K-byte) Block(32K-byte) Sector (4K-byte)
Address Range
2047
7FF000h
7FFFFFh
255
individual 16 sectors
lock/unlock unit:4K-byte
2040
2039
7F8000h
7F7000h
7F8FFFh
7F7FFFh
127
254
253
252
251
250
2032
2031
7F0000h
7EF000h
7F0FFFh
7EFFFFh
2024
2023
7E8000h
7E7000h
7E8FFFh
7E7FFFh
126
individual block
lock/unlock unit:64K-byte
2016
2015
7E0000h
7DF000h
7E0FFFh
7DFFFFh
2008
2007
7D8000h
7D7000h
7D8FFFh
7D7FFFh
125
2000
7D0000h
7D0FFFh
individual block
lock/unlock unit:64K-byte
47
02F000h
02FFFFh
5
4
3
2
1
0
40
39
028000h
027000h
028FFFh
027FFFh
2
1
individual block
lock/unlock unit:64K-byte
32
31
020000h
01F000h
020FFFh
01FFFFh
24
23
018000h
017000h
018FFFh
017FFFh
16
15
010000h
00F000h
010FFFh
00FFFFh
8
7
008000h
007000h
008FFFh
007FFFh
individual 16 sectors
lock/unlock unit:4K-byte
0
0
000000h
000FFFh
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REV. 1.8, DEC. 26, 2011
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MX25L6445E
DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended opera-
tion.
2. When incorrect command is inputted to this device, it enters standby mode and remains in standby mode until
next CS# falling edge. In standby mode, SO pin of the device is High-Z.
3. When correct command is inputted to this device, it enters active mode and remains in active mode until next
CS# rising edge.
4. For standard single data rate serial mode, input data is latched on the rising edge of Serial Clock (SCLK) and
data is shifted out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as Figure
1-1. For high performance (Double Transfer Rate Read serial mode), data is latched on both rising and falling
edge of clock and data shifts out on both rising and falling edge of clock as Figure 1-2.
5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, RDSFDP, 2READ, 4READ, FAST-
DTRD, 2DTRD, 4DTRD, RDBLOCK, RES, REMS, REMS2, REMS4, and REMS4D the shifted-in instruction se-
quence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the
following instructions: WREN, WRDI, WRSR, SE, BE, BE32K, HPM, CE, PP, CP, 4PP, RDP, DP, WPSEL, SBLK,
SBULK, GBLK, GBULK, ENSO, EXSO, WRSCUR, ENPLM, EXPLM, ESRY, DSRY and CLSR the CS# must go
high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
6. While a Write Status Register, Program or Erase operation is in progress, access to the memory array is neglect-
ed and will not affect the current operation of Write Status Register, Program, Erase.
Figure 1-1. Serial Modes Supported (for Normal Serial mode)
CPOL CPHA
shift in
shift out
SCLK
SCLK
(Serial mode 0)
(Serial mode 3)
0
1
0
1
SI
MSB
SO
MSB
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is
supported.
Figure 1-2. Serial Modes Supported (for Double Transfer Rate serial read mode)
data
in
data
in
data data
out out
CPOL CPHA
SCLK
SCLK
(Serial mode 0)
(Serial mode 3)
0
1
0
1
SI
MSB
SO
P/N: PM1736
REV. 1.8, DEC. 26, 2011
13
MX25L6445E
COMMAND DESCRIPTION
Table 5. Command Sets
RDSR
WRSR
FASTDTRD
(fast DT
read)
4DTRD
(Quad I/O DT
Read)
COMMAND WREN (write WRDI (write RDID (read
2DTRD (Dual
I/O DT Read)
(read status (write status
(byte)
enable)
disable)
identification)
register)
05
register)
01
Command
(hex)
06
04
9F
0D
ADD(12)
6
BD
ADD(6)
6
ED
ADD(3)
1+7
Input
Data(8)
Cycles
Dummy
Cycles
sets the
(WEL) write (WEL) write
enable latch enable latch ID: 1-byte of the status the status
resets the
outputs
JEDEC
to read out to write new n bytes read n bytes read n bytes read
the values values to out (Double out (Double out (Double
Transfer Transfer Transfer
Rate) until Rate) by 2xI/ Rate) by 4xI/
bit
bit
Manufacturer
ID & 2-byte
Device ID
register
register
Action
CS# goes
high
O until CS# O until CS#
goes high
goes high
2READ (2
x I/O read
(Read SFDP) command)
Note1
FAST READ
(fast read
data)
4READ (4
x I/O read
command)
4PP (quad
page
program)
COMMAND READ (read
RDSFDP
SE (sector
erase)
BE (block
erase 64KB)
(byte)
data)
Command
(hex)
03
0B
ADD(24)
8
5A
ADD(24)
8
BB
ADD(12)
4
EB
ADD(6)
2+4
38
20
D8
Input
ADD(6)+
Data(512)
ADD(24)
ADD(24)
ADD(24)
Cycles
Dummy
Cycles
n bytes read n bytes read Read SFDP n bytes read n bytes read quad input to erase the to erase the
out until CS# out until CS#
goes high goes high
mode
out by 2 x I/ out by 4 x I/ to program
O until CS# O until CS# the selected
selected
sector
selected
64KB block
Action
goes high
goes high
page
CP
RDP
(Release
REMS (read
electronic
COMMAND BE 32K (block CE (chip
PP (Page (Continuously DP (Deep
RES (read
(byte)
erase 32KB)
erase)
program)
program
mode)
power down) from deep electronic ID) manufacturer
power down)
& device ID)
Command
(hex)
52
60 or C7
02
AD
B9
AB
AB
24
90
Input
ADD(24)+
Data(2048)
ADD(24)+
Data(16)
ADD(24)
ADD(24)
Cycles
Dummy
Cycles
to erase the
selected
32KB block
to erase
whole chip the selected
page
to program continously enters deep release from to read out
output the
program
whole chip,
the address is
automatically
increase
power down deep power 1-byte Device Manufacturer
mode
down mode
ID
ID & Device
ID
Action
P/N: PM1736
REV. 1.8, DEC. 26, 2011
14
MX25L6445E
REMS4D
(read ID for
4x I/O DT
mode)
ESRY
REMS2 (read REMS4 (read
ID for 2x I/O ID for 4x I/O
ENSO (enter EXSO (exit
RDSCUR
(read security (write security
WRSCUR
COMMAND
(byte)
(enable SO
to output RY/
BY#)
secured
OTP)
secured
OTP)
mode)
mode)
register)
2B
register)
2F
Command
(hex)
EF
DF
CF
B1
C1
70
Input
ADD(24)
ADD(24)
ADD(24)
Cycles
Dummy
Cycles
output the
Manufacturer Manufact-
output the
output the
Manufact-
to enter
the 4K-bit
to exit the 4K- to read value to set the to enable SO
bit Secured of security lock-down bit to output RY/
ID & Device
ID
urer ID &
device ID
urer ID & Secured OTP OTP mode
register
as "1" (once BY# during
Device ID
mode
lock-down,
cannot be
updated)
CP mode
Action
DSRY
HPM (High
Perform-
ance Enable
Mode)
CLSR (Clear
SR Fail
WPSEL (write SBLK (single
SBULK
RDBLOCK
COMMAND (disable SO
GBLK (gang
block lock)
protection
selection)
block lock) (single block (block protect
*Note 2
(byte)
to output RY/
BY#)
Flags)
unlock)
read)
Command
(hex)
80
30
A3
68
36
39
3C
7E
Input
ADD(24)
ADD(24)
ADD(24)
Cycles
Dummy
Cycles
to disable SO clear security Quad I/O
to enter
individual
individual
read
whole chip
to output RY/ register bit 6 high Perform- and enable block (64K- block (64K-
individual
block or
sector write
write protect
BY# during
CP mode
and bit 5
ance mode
individal
block protect sector (4K-
byte) or
byte) or
sector
Action
mode
byte) write
protect
(4K-byte) protect status
unprotect
COMMAND GBULK (gang
(byte)
Command
(hex)
block unlock)
98
Input
Cycles
Dummy
Cycles
whole
chip
unprotect
Action
Notes:
1. It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden
mode.
2: In individual block write protection mode, all blocks/sectors are locked as defualt.
P/N: PM1736
REV. 1.8, DEC. 26, 2011
15
MX25L6445E
(1) Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP,
CP, SE, BE, BE32K, CE, WRSR, SBLK, SBULK, GBLK and GBULK, which are intended to change the device con-
tent, should be set every time after the WREN instruction setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→ CS# goes high.
(Please refer to Figure 11)
(2) Write Disable (WRDI)
The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.
The sequence of issuing WRDI instruction is: CS# goes low→ sending WRDI instruction code→ CS# goes high. (Please
refer to Figure 12)
The WEL bit is reset by following situations:
- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP, 4PP) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase (BE, BE32K) instruction completion
- Chip Erase (CE) instruction completion
- Continuously Program mode (CP) instruction completion
- Single Block Lock/Unlock (SBLK/SBULK) instruction completion
- Gang Block Lock/Unlock (GBLK/GBULK) instruction completion
(3) Read Identification (RDID)
The RDID instruction is for reading the Manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC
Manufacturer ID is C2(hex), the memory type ID is 20(hex) as the first-byte Device ID, and the individual Device ID
of second-byte ID are listed as table of "ID Definitions". (Please refer to Table 6)
The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code → 24-bits ID data out
on SO→ to end RDID operation can use CS# to high at any time during data out. (Please refer to Figure 13)
While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cy-
cle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.
P/N: PM1736
REV. 1.8, DEC. 26, 2011
16
MX25L6445E
(4) Read Status Register (RDSR)
The RDSR instruction is for reading Status Register. The Read Status Register can be read at any time (even in
program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP)
bit before sending a new instruction when a program, erase, or write status register operation is in progress.
The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register
data out on SO (Please refer to Figure 14).
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write
status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status
register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status
register cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable
latch. When WEL bit sets to "1", which means the internal write enable latch is set, the device can accept program/
erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the de-
vice will not accept program/erase/write status register instruction. The program/erase command will be ignored and
will reset WEL bit if it is applied to a protected memory area.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area (as
defined in Table 2) of the device to against the program/erase instruction without hardware protection mode being
set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to
be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE),
Block Erase (BE) and Chip Erase (CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be
executed).
QE bit. The Quad Enable (QE) bit, non-volatile bit, while it is "0" (factory default), it performs non-Quad and WP# is
enable. While QE is "1", it performs Quad I/O mode and WP# is disabled. In the other word, if the system goes into
four I/O mode (QE=1), the feature of HPM will be disabled.
SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, default value is "0". SRWD bit is operat-
ed together with Write Protection (WP#/SIO2) pin for providing hardware protection mode. The hardware protection
mode requires SRWD sets to 1 and WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write
Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP3,
BP2, BP1, BP0) are read only.
Status Register
bit7
bit6
bit5
BP3
(level of
protected
block)
bit4
BP2
(level of
protected
block)
bit3
BP1
(level of
protected
block)
bit2
BP0
(level of
protected
block)
bit1
bit0
SRWD (status
register write
protect)
QE
(Quad
Enable)
WEL
(write enable
latch)
WIP
(write in
progress bit)
1= Quad
Enable
0=not Quad
Enable
1=write
enable
0=not write 0=not in write
1=write
operation
1=status
register write
disable
(note 1)
(note 1)
(note 1)
(note 1)
enable
operation
Non-volatile Non-volatile Non-volatile Non-volatile Non-volatile Non-volatile
bit bit bit bit bit bit
volatile bit
volatile bit
Note: see the Table 2 "Protected Area Size" in page 11.
P/N: PM1736
REV. 1.8, DEC. 26, 2011
17
MX25L6445E
(5) Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the
Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in ad-
vance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to define the pro-
tected area of memory (as shown in Table 2). The WRSR also can set or reset the Quad enable (QE) bit and set or
reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#/SIO2) pin signal, but
has no effect on bit1(WEL) and bit0 (WIP) of the status register. The WRSR instruction cannot be executed once the
Hardware Protected Mode (HPM) is entered.
The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register
data on SI→ CS# goes high. (Please refer to Figure 15)
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1
during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL)
bit is reset.
Protection Modes
Mode
Status register condition
WP# and SRWD bit status
Memory
Status register can be written
in (WEL bit is set to "1") and
the SRWD, BP0-BP3
Software protection
mode(SPM)
WP#=1 and SRWD bit=0, or
WP#=0 and SRWD bit=0, or
WP#=1 and SRWD=1
The protected area
cannot
be program or erase.
bits can be changed
The SRWD, BP0-BP3 of
status register bits cannot be
changed
The protected area
cannot
be program or erase.
Hardware protection
mode (HPM)
WP#=0, SRWD bit=1
Note: As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in Table 2.
As the table above showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM):
Software Protected Mode (SPM):
-
When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can
change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1,
BP0, is at software protected mode (SPM).
-
When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values of
SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software pro-
tected mode (SPM)
Hardware Protected Mode (HPM):
-
When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware
protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2,
BP1, BP0 and hardware protected mode by the WP#/SIO2 to against data modification.
Note:
To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered.
If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be entered; only
can use software protected mode via BP3, BP2, BP1, BP0.
If the system goes into four I/O mode, the feature of HPM will be disabled.
P/N: PM1736
REV. 1.8, DEC. 26, 2011
18
MX25L6445E
(6) Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on
the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address
is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can
be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been
reached.
The sequence of issuing READ instruction is: CS# goes low→ sending READ instruction code→3-byte address on
SI →data out on SO→ to end READ operation can use CS# to high at any time during data out. (Please refer to Fig-
ure 16)
(7) Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at
any location. The address is automatically increased to the next higher address after each byte data is shifted out,
so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when
the highest address has been reached.
The sequence of issuing FAST_READ instruction is: CS# goes low→sending FAST_READ instruction code→3-byte
address on SI→ 1-dummy byte (default) address on SI→data out on SO→ to end FAST_READ operation can use
CS# to high at any time during data out. (Please refer to Figure 17)
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any im-
pact on the Program/Erase/Write Status Register current cycle.
(8) Fast Double Transfer Rate Read (FASTDTRD)
The FASTDTRD instruction is for doubling reading data out, signals are triggered on both rising and falling edge of
clock. The address is latched on both rising and falling edge of SCLK, and data of each bit shifts out on both rising
and falling edge of SCLK at a maximum frequency fC2. The 2-bit address can be latched-in at one clock, and 2-bit
data can be read out at one clock, which means one bit at rising edge of clock, the other bit at falling edge of clock.
The first address byte can be at any location.
The address is automatically increased to the next higher address after each byte data is shifted out, so the whole
memory can be read out at a single FASTDTRD instruction. The address counter rolls over to 0 when the highest
address has been reached.
The sequence of issuing FASTDTRD instruction is: CS# goes low → sending FASTDTRD instruction code (1bit
per clock) → 3-byte address on SI (2-bit per clock) → 6-dummy clocks (default) on SI → data out on SO (2-bit per
clock) → to end FASTDTRD operation can use CS# to high at any time during data out. (Please refer to Figure 18)
While Program/Erase/Write Status Register cycle is in progress, FASTDTRD instruction is rejected without any im-
pact on the Program/Erase/Write Status Register current cycle.
(9) 2 x I/O Read Mode (2READ)
The 2READ instruction enables Double Transfer Rate of Serial Flash in read mode. The address is latched on rising
edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maxi-
P/N: PM1736
REV. 1.8, DEC. 26, 2011
19
MX25L6445E
mum frequency fT. The first address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ instruc-
tion. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ instruc-
tion, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 24-bit address in-
terleave on SIO1 & SIO0→ 4-bit dummy cycle on SIO1 & SIO0→ data out interleave on SIO1 & SIO0→ to end
2READ operation can use CS# to high at any time during data out (Please refer to Figure 19 for 2 x I/O Read Mode
Timing Waveform).
While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
(10) 2 x I/O Double Transfer Rate Read Mode (2DTRD)
The 2DTRD instruction enables Double Transfer Rate throughput on dual I/O of Serial Flash in read mode. The ad-
dress (interleave on dual I/O pins) is latched on both rising and falling edge of SCLK, and data (interleave on dual
I/O pins) shift out on both rising and falling edge of SCLK at a maximum frequency fT2. The 4-bit address can be
latched-in at one clock, and 4-bit data can be read out at one clock, which means two bits at rising edge of clock,
the other two bits at falling edge of clock. The first address byte can be at any location.
The address is automatically increased to the next higher address after each byte data is shifted out, so the whole
memory can be read out at a single 2DTRD instruction. The address counter rolls over to 0 when the highest ad-
dress has been reached. Once writing 2DTRD instruction, the following address/dummy/ data out will perform as
4-bit instead of previous 1-bit.
The sequence of issuing 2DTRD instruction is: CS# goes low → sending 2DTRD instruction (1-bit per clock) → 24-
bit address interleave on SIO1 & SIO0 (4-bit per clock) → 6-bit dummy clocks on SIO1 & SIO0 → data out inter-
leave on SIO1 & SIO0 (4-bit per clock) → to end 2DTRD operation can use CS# to high at any time during data
out (Please refer to Figure 20 for 2 x I/O Double Transfer Rate Read Mode Timing Waveform).
While Program/Erase/Write Status Register cycle is in progress, 2DTRD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
(11) 4 x I/O Read Mode (4READ)
The 4READ instruction enables quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status
Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCLK,
and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency
fQ. The first address byte can be at any location. The address is automatically increased to the next higher address
after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The ad-
dress counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the fol-
lowing address/dummy/data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing 4READ instruction is: CS# goes low→ sending 4READ instruction→ 24-bit address in-
terleave on SIO3, SIO2, SIO1 & SIO0→ 6 dummy cycles → data out interleave on SIO3, SIO2, SIO1 & SIO0→ to
end 4READ operation can use CS# to high at any time during data out (Please refer to Figure 21 for 4 x I/O Read
Mode Timing Waveform).
Another sequence of issuing 4READ instruction especially useful in random access is : CS# goes low→ sending 4
READ instruction→ 3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 →performance enhance toggling bit
P/N: PM1736
REV. 1.8, DEC. 26, 2011
20
MX25L6445E
P[7:0]→ 4 dummy cycles → data out still CS# goes high → CS# goes low (reduce 4Read instruction) → 24-bit ran-
dom access address (Please refer to Figure 22 for 4x I/O Read Enhance Performance Mode timing waveform).
In the performance-enhancing mode (Notes of Figure. 22), P[7:4] must be toggling with P[3:0]; likewise P[7:0]=A5h,
5Ah, F0h or 0Fh can make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer
toggling with P[3:0]; likewise P[7:0]=FFh, 00h, AAh or 55h. These commands will reset the performance enhance
mode. And afterwards CS# is raised and then lowered, the system then will return to normal operation.
While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
(12) 4 x I/O Double Transfer Rate Read Mode (4DTRD)
The 4DTRD instruction enables Double Transfer Rate throughput on quad I/O of Serial Flash in read mode. A Quad
Enable (QE) bit of status Register must be set to "1" before sending the 4DTRD instruction. The address (interleave
on 4 I/O pins) is latched on both rising and falling edge of SCLK, and data (interleave on 4 I/O pins) shift out on
both rising and falling edge of SCLK at a maximum frequency fQ2. The 8-bit address can be latched-in at one clock,
and 8-bit data can be read out at one clock, which means four bits at rising edge of clock, the other four bits at fall-
ing edge of clock. The first address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single 4DTRD instruc-
tion. The address counter rolls over to 0 when the highest address has been reached. Once writing 4DTRD instruc-
tion, the following address/dummy/data out will perform as 8-bit instead of previous 1-bit.
The sequence of issuing 4DTRD instruction is: CS# goes low → sending 4DTRD instruction (1-bit per clock) → 24-
bit address interleave on SIO3, SIO2, SIO1 & SIO0 (8-bit per clock) → 8 dummy clocks → data out interleave on
SIO3, SIO2, SIO1 & SIO0 (8-bit per clock) → to end 4DTRD operation can use CS# to high at any time during data
out (Please refer to Figure 23 for 4 x I/O Read Mode Double Transfer Rate Timing Waveform).
Another sequence of issuing enhanced mode of 4DTRD instruction especially useful in random access is: CS# goes
low → sending 4DTRD instruction (1-bit per clock) → 3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 (8-bit
per clock) → performance enhance toggling bit P[7:0] → 7 dummy clocks → data out(8-bit per clock) still CS#
goes high → CS# goes low (eliminate 4 Read instruction) → 24-bit random access address (Please refer to Figure
24 for 4x I/O Double Transfer Rate read enhance performance mode timing waveform).
While Program/Erase/Write Status Register cycle is in progress, 4DTRD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
(13) Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for
any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before
sending the Sector Erase (SE). Any address of the sector (see Table 4) is a valid address for Sector Erase (SE) in-
struction. The CS# must go high exactly at the byte boundary (the least significant bit of the address been latched-
in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing SE instruction is: CS# goes low → sending SE instruction code→ 3-byte address on SI
→CS# goes high. (Please refer to Figure 25)
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets during the tSE
timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
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21
MX25L6445E
sector is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no
change) and the WEL bit still be reset.
(14) Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for
64K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable Latch
(WEL) bit before sending the Block Erase (BE). Any address of the block (see Table 4) is a valid address for Block
Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of address byte
been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE instruction is: CS# goes low → sending BE instruction code → 3-byte address on SI
→ CS# goes high. (Please refer to Figure 26)
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during the tBE tim-
ing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the block
is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no change)
and the WEL bit still be reset.
(15) Block Erase (BE32K)
The Block Erase (BE32) instruction is for erasing the data of the chosen block to be "1". The instruction is used
for 32K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable
Latch (WEL) bit before sending the Block Erase (BE32). Any address of the block (see Table 4) is a valid address
for Block Erase (BE32) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of
address byte been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE32 instruction is: CS# goes low → sending BE32 instruction code → 3-byte address on
SI → CS# goes high. (Please refer to Figure 26)
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during the tBE tim-
ing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the block
is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no change)
and the WEL bit still be reset.
(16) Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruc-
tion must be executed to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must
go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The sequence of issuing CE instruction is: CS# goes low → sending CE instruction code → CS# goes high. (Please
refer to Figure 27)
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Chip Erase cycle is in progress. The WIP sets during the tCE tim-
ing, and clears when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the chip is
protected, the Chip Erase (CE) instruction will not be executed, but WEL will be reset.
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(17) Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction
must be executed to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device
programs only the last 256 data bytes sent to the device. If the entire 256 data bytes are going to be programmed,
A7-A0 (the eight least significant address bits) should be set to 0. If the eight least significant address bits (A7-A0)
are not all 0, all transmitted data going beyond the end of the current page are programmed from the start address
of the same page (from the address A7-A0 are all 0). If more than 256 bytes are sent to the device, the data of the
last 256-byte is programmed at the requested page and previous data will be disregarded. If less than 256 bytes
are sent to the device, the data is programmed at the requested address of the page without effect on other address
of the same page.
The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→
at least 1-byte on data on SI→ CS# goes high. (Please refer to Figure 28)
The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte
boundary( the latest eighth bit of data being latched in), otherwise, the instruction will be rejected and will not be
executed.
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Page Program cycle is in progress. The WIP sets during the tPP
timing, and clears when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If
the page is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no
change) and the WEL bit will still be reset.
(18) 4 x I/O Page Program (4PP)
The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN)
instruction must be executed to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1"
before sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1, SIO2,
and SIO3, which can raise programer performance and and the effectiveness of application of lower clock less
than 20MHz. For system with faster clock, the Quad page program cannot provide more performance, because
the required internal page program time is far more than the time data flows in. Therefore, we suggest that while
executing this command (especially during sending data), user can slow the clock speed down to 20MHz below.
The other function descriptions are as same as standard page program.
The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on
SIO[3:0]→ at least 1-byte on data on SIO[3:0]→ CS# goes high. (Please refer to Figure 29)
If the page is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no
change) and the WEL bit will still be reset.
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The Program/Erase function instruction function flow is as follows:
Program/Erase Flow(1) with read array data
Start
WREN command
RDSR command*
No
WREN=1?
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
No
WIP=0?
Yes
Read array data
(same address of PGM/ERS)
No
Verify OK?
Yes
Program/erase fail
Program/erase successfully
CLSR(30h) command
Program/erase
another block?
Yes
* Issue RDSR to check BP[3:0].
* If WPSEL=1, issue RDBLOCK to check the block status.
No
Program/erase completed
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Program/Erase Flow(2) without read array data
Start
WREN command
RDSR command*
No
WREN=1?
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
No
WIP=0?
Yes
RDSCUR command
Yes
P_FAIL/E_FAIL=1?
No
Program/erase fail
Program/erase successfully
CLSR(30h) command
Program/erase
another block?
Yes
* Issue RDSR to check BP[3:0].
* If WPSEL=1, issue RDBLOCK to check the block status.
No
Program/erase completed
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(19) Continuously program mode (CP mode)
The CP mode may enhance program performance by automatically increasing address to the next higher address
after each byte data has been programmed.
The Continuously program (CP) instruction is for multiple byte program to Flash. A write Enable (WREN) instruction
must execute to set the Write Enable Latch (WEL) bit before sending the Continuously program (CP) instruction.
CS# requires to go high before CP instruction is executing. After CP instruction and address input, two bytes of
data is input sequentially from MSB(bit7) to LSB(bit0). The first byte data will be programmed to the initial address
range with A0=0 and second byte data with A0=1. If only one byte data is input, the CP mode will not process. If
more than two bytes data are input, the additional data will be ignored and only two byte data are valid. Any byte to
be programmed should be in the erase state (FF) first. It will not roll over during the CP mode, once the last unpro-
tected address has been reached, the chip will exit CP mode and reset write Enable Latch bit (WEL) as "0" and CP
mode bit as "0". Please check the WIP bit status if it is not in write progress before entering next valid instruction.
During CP mode, the valid commands are CP command (AD hex), WRDI command (04 hex), RDSR command (05
hex), and RDSCUR command (2B hex). And the WRDI command is valid after completion of a CP programming cy-
cle, which means the WIP bit=0.
The sequence of issuing CP instruction is : CS# goes low → sending CP instruction code → 3-byte address on SI
pin → two data bytes on SI → CS# goes high to low → sending CP instruction and then continue two data bytes
are programmed → CS# goes high to low → till last desired two data bytes are programmed → CS# goes high to
low →sending WRDI (Write Disable) instruction to end CP mode → send RDSR instruction to verify if CP mode
word program ends, or send RDSCUR to check bit4 to verify if CP mode ends. (Please refer to Figure 30 of CP
mode timing waveform)
Two methods to detect the completion of a program cycle during CP mode:
1) Software method-I: by checking WIP bit of Status Register to detect the completion of CP mode.
2) Software method-II: by waiting for a tBP time out to determine if it may load next valid command or not.
3) Hardware method: by writing ESRY (enable SO to output RY/BY#) instruction to detect the completion of a
program cycle during CP mode. The ESRY instruction must be executed before CP mode execution. Once it is
enable in CP mode, the CS# goes low will drive out the RY/BY# status on SO, "0" indicates busy stage, "1" indi-
cates ready stage, SO pin outputs tri-state if CS# goes high. DSRY (disable SO to output RY/BY#) instruction to
disable the SO to output RY/BY# and return to status register data output during CP mode. Please note that the
ESRY/DSRY command are not accepted unless the completion of CP mode.
If the page is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no
change) and the WEL bit will still be reset.
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(20) Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device to minimum power consumption (the standby cur-
rent is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction
to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are
ignored. When CS# goes high, the device is only in standby mode, not deep power-down mode. It's different from
Standby mode.
The sequence of issuing DP instruction is: CS# goes low→ sending DP instruction code→ CS# goes high. (Please
refer to Figure 31)
Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP)
and Read Electronic Signature (RES) instruction. (those instructions allow the ID being reading out). When Power-
down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby
mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction
code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay
of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2.
(21) Release from Deep Power-down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is completed by driving Chip Select (CS#) High. When Chip
Select (CS#) is driven High, the device is put in the Standby Power mode. If the device was not previously in the
Deep Power-down mode, the transition to the standby Power mode is immediate. If the device was previously in the
Deep Power-down mode, though, the transition to the standby Power mode is delayed by tRES2, and Chip Select (CS#)
must remain High for at least tRES2(max), as specified in Table 11. Once in the standby mode, the device waits to
be selected, so that it can receive, decode and execute instructions.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of
ID Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new
design, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be
executed, only except the device is in progress of program/erase/write cycles; there's no effect on the current pro-
gram/erase/write cycles in progress. The sequence is shown as Figure 32, 33.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeat-
edly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously
in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in
Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at
least tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and
execute instruction.
The RDP instruction is for releasing from Deep Power-down Mode.
(22) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4), (REMS4D)
The REMS, REMS2, REMS4 and REMS4D instruction provides both the JEDEC assigned Manufacturer ID and the
specific Device ID.
The instruction is initiated by driving the CS# pin low and shift the instruction code "90h", "CFh", "DFh" or "EFh" fol-
lowed by two dummy bytes and one bytes address (A7~A0). After which, the Manufacturer ID for MXIC (C2h) and
the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 34.
The Device ID values are listed in table of ID Definitions. If the one-byte address is initially set to 01h, then the De-
vice ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read
continuously, alternating from one to the other. The instruction is completed by driving CS# high.
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Table 6. ID Definitions
Command Type
RDID
MX25L6445E
memory type
20
electronic ID
16
manufacturer ID
C2
memory density
17
RES
manufacturer ID
C2
device ID
16
REMS/REMS2/REMS4/REMS4D
(23) Enter Secured OTP (ENSO)
The ENSO instruction is for entering the additional 4K-bit Secured OTP mode. While device is in 4K-bit Secured
OTP mode, main array access is not available. The additional 4K-bit Secured OTP is independent from main array,
and may be used to store unique serial number for system identifier. After entering the Secured OTP mode, follow
standard read or program procedure to read out the data or update data. The Secured OTP data cannot be updat-
ed again once it is lock-down.
The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP
mode→ CS# goes high.
Please note that WRSR/WRSCUR/WPSEL/SBLK/GBLK/SBULK/GBULK/CE/BE/SE/BE32K commands are not ac-
ceptable during the access of secure OTP region, once Security OTP is lock down, only read related commands
are valid.
(24) Exit Secured OTP (EXSO)
The EXSO instruction is for exiting the additional 4K-bit Secured OTP mode.
The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP
mode→ CS# goes high.
(25) Read Security Register (RDSCUR)
The RDSCUR instruction is for reading the value of Security Register. The Read Security Register can be read at
any time (even in program/erase/write status register/write security register condition) and continuously.
The sequence of issuing RDSCUR instruction is : CS# goes low→ sending RDSCUR instruction → Security Regis-
ter data out on SO→ CS# goes high.
The definition of the Security Register is as below:
Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory before ex- factory
or not. When it is "0", it indicates non-factory lock; "1" indicates factory- lock.
Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for cus-
tomer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 4K-bit Secured
OTP area cannot be updated any more.
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Continuously Program Mode( CP mode) bit. The Continuously Program Mode bit indicates the status of CP
mode, "0" indicates not in CP mode; "1" indicates in CP mode.
Program Fail Flag bit. While a program failure happened, the Program Fail Flag bit would be set. This bit will also
be set when the user attempts to program a protected main memory region or a locked OTP region. This bit can in-
dicate whether one or more of program operations fail, and can be reset by command CLSR (30h).
Erase Fail Flag bit. While a erase failure happened, the Erase Fail Flag bit would be set. This bit will also be set
when the user attempts to erase a protected main memory region or a locked OTP region. This bit can indicate
whether one or more of erase operations fail, and can be reset by command CLSR (30h).
Write Protection Select bit. The Write Protection Select bit indicates that WPSEL has been executed successfully.
Once this bit has been set (WPSEL=1), all the blocks or sectors will be write-protected after the power-on every
time. Once WPSEL has been set, it cannot be changed again, which means it's only for individual WP mode.
Under the individual block protection mode (WPSEL=1), hardware protection is performed by driving WP#=0. Once
WP#=0 all array blocks/sectors are protected regardless of the contents of SRAM lock bits.
Security Register Definition
bit7
bit6
bit5
bit4
bit3
x
bit2
x
bit1
bit0
Continuously
Program
mode
(CP mode)
LDSO
(lock-down
4K-bit Se- Secured OTP
cured OTP)
4K-bit
WPSEL
E_FAIL
P_FAIL
0 = not
0=normal
Erase
succeed
1=indicate
Erase failed
(default=0)
0=normal
Program
succeed
1=indicate
Program
failed
0=normal
WP mode
1=individual
WP mode
(default=0)
lockdown
1 = lock-
down
(cannot
program/
erase
0 =
nonfactory
lock
1 = factory
lock
0=normal
Program
mode
1=CP mode
(default=0)
reserved
reserved
(default=0)
OTP)
non-volatile
bit
non-volatile non-volatile
volatile bit
Read Only
volatile bit
Read Only
volatile bit
Read Only
volatile bit
Read Only
volatile bit
Read Only
bit
bit
OTP
OTP
Read Only
(26) Write Security Register (WRSCUR)
The WRSCUR instruction is for changing the values of Security Register Bits. Unlike write status register, the WREN
instruction is not required before sending WRSCUR instruction. The WRSCUR instruction may change the values
of bit1 (LDSO bit) for customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is set to "1", the Se-
cured OTP area cannot be updated any more.
The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high.
The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
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(27) Write Protection Selection (WPSEL)
There are two write protection methods, (1) BP protection mode (2) individual block protection mode. If WPSEL=0,
flash is under BP protection mode . If WPSEL=1, flash is under individual block protection mode. The default value
of WPSEL is “0”. WPSEL command can be used to set WPSEL=1. Please note that WPSEL is an OTP bit. Once
WPSEL is set to 1, there is no chance to recovery WPSEL back to “0”. If the flash is put on BP mode, the indi-
vidual block protection mode is disabled. Contrarily, if flash is on the individual block protection mode, the BP mode
is disabled.
Every time after the system is powered-on the Security Register bit 7 is checked. If WPSEL=1, all the blocks
and sectors will be write protected by default. User may only unlock the blocks or sectors via SBULK and
GBULK instructions. Program or erase functions can only be operated after the Unlock instruction is executed.
BP protection mode, WPSEL=0:
ARRAY is protected by BP3~BP0 and BP3~BP0 bits are protected by “SRWD=1 and WP#=0”, where SRWD is bit 7
of status register that can be set by WRSR command.
Individual block protection mode, WPSEL=1:
Blocks are individually protected by their own SRAM lock bits which are set to “1” after power up. SBULK and SBLK
command can set SRAM lock bit to “0” and “1”. When the system accepts and executes WPSEL instruction, bit 7 in
the security register will be set. It will activate SBLK, SBULK, RDBLOCK, GBLK, GBULK etc instructions to conduct
block lock protection and replace the original Software Protect Mode (SPM) use (BP3~BP0) indicated block meth-
ods. Under the individual block protection mode (WPSEL=1), hardware protection is performed by driving WP#=0.
Once WP#=0 all array blocks/sectors are protected regardless of the contents of SRAM lock bits.
The sequence of issuing WPSEL instruction is: CS# goes low → sending WPSEL instruction to enter the individual
block protect mode → CS# goes high.
WPSEL instruction function flow is as follows:
BP and SRWD if WPSEL=0
WP# pin
BP3 BP2 BP1 BP0
SRWD
64KB
64KB
64KB
(1) BP3~BP0 is used to define the protection group region.
(The protected area size see Table 2)
(2) “SRWD=1 and WP#=0” is used to protect BP3~BP0. In this
case, SRWD and BP3~BP0 of status register bits can not
be changed by WRSR
.
.
.
64KB
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The individual block lock mode is effective after setting WPSEL=1
4KB
4KB
SRAM
SRAM
• Power-Up: All SRAM bits=1 (all blocks are default protected).
All array cannot be programmed/erased
TOP 4KBx16
Sectors
• SBLK/SBULK(36h/39h):
- SBLK(36h): Set SRAM bit=1 (protect): array can not be
programmed/erased
4KB
SRAM
SRAM
- SBULK(39h): Set SRAM bit=0 (unprotect): array can be
programmed/erased
64KB
- All the top 4KBx16 sectors and bottom 4KBx16 sectors
and other 64KB uniform blocks can be protected and
unprotected with SRAM bits individually by SBLK/SBULK
command set.
SRAM
Uniform
64KB blocks
• GBLK/ GBULK(7Eh/98h):
- GBLK(7Eh): Set all SRAM bits=1, the whole chip is
protected and cannot be programmed/erased.
- GBULK(98h): Set all SRAM bits=0, the whole chip is
unprotected and can be programmed/erased.
- All sectors and blocks SRAM bits of the whole chip can be
protected and unprotected at one time by GBLK/GBULK
command set.
64KB
4KB
SRAM
SRAM
Bottom
4KBx16
Sectors
• RDBLOCK(3Ch):
- use RDBLOCK mode to check the SRAM bits status after
SBULK/SBLK/GBULK/GBLK command set.
4KB
SBULK / SBLK / GBULK / GBLK / RDBLOCK
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WPSEL Flow
start
RDSCUR(2Bh) command
Yes
WPSEL=1?
No
WPSEL disable,
block protected by BP[3:0]
WPSEL(68h) command
RDSR command
No
WIP=0?
Yes
RDSCUR(2Bh) command
No
WPSEL=1?
Yes
WPSEL set successfully
WPSEL set fail
WPSEL enable.
Block protected by individual lock
(SBLK, SBULK, … etc).
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(28) Single Block Lock/Unlock Protection (SBLK/SBULK)
These instructions are only effective after WPSEL was executed. The SBLK instruction is for write protection a spec-
ified block(or sector) of memory, using A23-A16 or (A23-A12) address bits to assign a 64Kbyte block (or 4K bytes
sector) to be protected as read only. The SBULK instruction will cancel the block (or sector) write protection state.
This feature allows user to stop protecting the entire block (or sector) through the chip unprotect command (GBULK).
The WREN (Write Enable) instruction is required before issuing SBLK/SBULK instruction.
The sequence of issuing SBLK/SBULK instruction is: CS# goes low → send SBLK/SBULK (36h/39h) instruction →
send 3 address bytes assign one block (or sector) to be protected on SI pin → CS# goes high. (Please refer to Fig-
ure 36)
The CS# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not be executed.
SBLK/SBULK instruction function flow is as follows:
Block Lock Flow
Start
RDSCUR(2Bh) command
No
WPSEL=1?
WPSEL command
Yes
WREN command
SBLK command
( 36h + 24bit address )
RDSR command
No
WIP=0?
Yes
RDBLOCK command
( 3Ch + 24bit address )
No
Data = FFh ?
Yes
Block lock successfully
Block lock fail
Yes
Lock another block?
No
Block lock completed
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Block Unlock Flow
start
RDSCUR(2Bh) command
No
WPSEL=1?
Yes
WPSEL command
WREN command
SBULK command
( 39h + 24bit address )
RDSR command
WIP=0?
No
Yes
Yes
Unlock another block?
Unlock block completed?
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(29) Read Block Lock Status (RDBLOCK)
This instruction is only effective after WPSEL was executed. The RDBLOCK instruction is for reading the status of
protection lock of a specified block (or sector), using A23-A16 (or A23-A12) address bits to assign a 64K bytes block (4K
bytes sector) and read protection lock status bit which the first byte of Read-out cycle. The status bit is"1" to indicate
that this block has be protected, that user can read only but cannot write/program /erase this block. The status bit is
"0" to indicate that this block hasn't be protected, and user can read and write this block.
The sequence of issuing RDBLOCK instruction is: CS# goes low → send RDBLOCK (3Ch) instruction → send 3 ad-
dress bytes to assign one block on SI pin → read block's protection lock status bit on SO pin → CS# goes high. (Please
refer to Figure 37)
(30) Gang Block Lock/Unlock (GBLK/GBULK)
These instructions are only effective after WPSEL was executed. The GBLK/GBULK instruction is for enable/disable
the lock protection block of the whole chip.
The WREN (Write Enable) instruction is required before issuing GBLK/GBULK instruction.
The sequence of issuing GBLK/GBULK instruction is: CS# goes low → send GBLK/GBULK (7Eh/98h) instruction →
CS# goes high. (Please refer to Figure 38)
The CS# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed.
(31) Clear SR Fail Flags (CLSR)
The CLSR instruction is for resetting the Program/Erase Fail Flag bit of Security Register. It should be executed be-
fore program/erase another block during programming/erasing flow without read array data.
The sequence of issuing CLSR instruction is: CS# goes low → send CLSR instruction code → CS# goes high.
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
(32) Enable SO to Output RY/BY# (ESRY)
The ESRY instruction is for outputting the ready/busy status to SO during CP mode.
The sequence of issuing ESRY instruction is: CS# goes low → sending ESRY instruction code → CS# goes high.
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
(33) Disable SO to Output RY/BY# (DSRY)
The DSRY instruction is for resetting ESRY during CP mode. The ready/busy status will not output to SO after
DSRY issued.
The sequence of issuing DSRY instruction is: CS# goes low → send DSRY instruction code → CS# goes high.
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
P/N: PM1736
REV. 1.8, DEC. 26, 2011
35
MX25L6445E
(34) Read SFDP Mode (RDSFDP)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional
and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables
can be interrogated by host system software to enable adjustments needed to accommodate divergent features
from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on
CFI.
The sequence of issuing RDSFDP instruction is same as FAST_READ: CS# goes low→send RDSFDP instruction
(5Ah)→send 3 address bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP
operation can use CS# to high at any time during data out.
SFDP is a standard of JEDEC. JESD216. v1.0.
Read Serial Flash Discoverable Parameter (RDSFDP) Sequence
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
SCLK
Command
5Ah
24 BIT ADDRESS
SI
23 22 21
3
2
1
0
High-Z
SO
CS#
47
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
SCLK
Dummy Cycle
7
6
5
4
3
2
0
1
SI
DATA OUT 2
DATA OUT 1
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
SO
MSB
MSB
MSB
P/N: PM1736
REV. 1.8, DEC. 26, 2011
36
MX25L6445E
Table 7. Signature and Parameter Identification Data Values
Description Comment
Add (h) DW Add Data (h/b)
Data
(h)
(Byte)
(Bit)
(Note1)
00h
07:00
53h
53h
46h
44h
50h
00h
01h
01h
01h
02h
03h
04h
05h
06h
15:08
23:16
31:24
07:00
15:08
23:16
46h
44h
50h
00h
01h
01h
SFDP Signature
Fixed: 50444653h
SFDP Minor Revision Number
SFDP Major Revision Number
Number of Parameter Headers
Start from 00h
Start from 01h
Start from 00h
Contains 0xFFh and can never be
changed
00h: it indicates a JEDEC specified
header.
Unused
07h
08h
09h
0Ah
0Bh
31:24
07:00
15:08
23:16
31:24
FFh
00h
00h
01h
09h
FFh
00h
00h
01h
09h
ID number (JEDEC)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length
(in double word)
Start from 0x00h
Start from 0x01h
How many DWORDs in the
Parameter table
0Ch
0Dh
0Eh
07:00
15:08
23:16
30h
00h
00h
30h
00h
00h
First address of JEDEC Flash
Parameter table
Parameter Table Pointer (PTP)
Unused
Contains 0xFFh and can never be
changed
it indicates Macronix manufacturer
ID
0Fh
10h
11h
12h
13h
31:24
07:00
15:08
23:16
31:24
FFh
C2h
00h
01h
04h
FFh
C2h
00h
01h
04h
ID number
(Macronix manufacturer ID)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Start from 0x00h
Start from 0x01h
Parameter Table Length
(in double word)
How many DWORDs in the
Parameter table
14h
15h
16h
07:00
15:08
23:16
60h
00h
00h
60h
00h
00h
First address of Macronix Flash
Parameter table
Parameter Table Pointer (PTP)
Unused
Contains 0xFFh and can never be
changed
17h
31:24
FFh
FFh
P/N: PM1736
REV. 1.8, DEC. 26, 2011
37
MX25L6445E
Table 8. Parameter Table (0): JEDEC Flash Parameter Tables
Add (h) DW Add Data (h/b)
Data
(h)
Description
Comment
(Byte)
(Bit)
(Note1)
00: Reserved, 01: 4KB erase,
10: Reserved,
Block/Sector Erase sizes
01:00
01b
11: not suport 4KB erase
Write Granularity
0: 1Byte, 1: 64Byte or larger
02
03
1b
0b
Write Enable Instruction
Requested for Writing to Volatile 1: Volatitle status bit
0: Nonvolatitle status bit
Status Registers
(BP status register bit)
30h
E5h
0: use 50h opcode,
1: use 06h opcode
Write Enable Opcode Select for
Writing to Volatile Status Registers
Note: If target flash status register is
nonvolatile, then bits 3 and 4 must
be set to 00b.
04
0b
Contains 111b and can never be
changed
Unused
07:05
111b
4KB Erase Opcode
31h
32h
33h
15:08
16
20h
0b
20h
B8h
FFh
(1-1-2) Fast Read (Note2)
0=not support 1=support
Address Bytes Number used in
addressing flash array
00: 3Byte only, 01: 3 or 4Byte,
10: 4Byte only, 11: Reserved
18:17
19
00b
1b
Double Transfer Rate (DTR)
Clocking
0=not support 1=support
(1-2-2) Fast Read
(1-4-4) Fast Read
(1-1-4) Fast Read
Unused
0=not support 1=support
0=not support 1=support
0=not support 1=support
20
21
1b
1b
22
0b
23
1b
Unused
31:24
FFh
Flash Memory Density
37h:34h 31:00
03FFFFFFh
(1-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
04:00
38h
0 0100b
states (Note3)
Clocks) not support
44h
EBh
00h
FFh
(1-4-4) Fast Read Number of
Mode Bits (Note4)
000b: Mode Bits not support
07:05
010b
EBh
(1-4-4) Fast Read Opcode
39h
3Ah
3Bh
15:08
20:16
(1-1-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
0 0000b
states
Clocks) not support
(1-1-4) Fast Read Number of
Mode Bits
000b: Mode Bits not support
23:21
31:24
000b
FFh
(1-1-4) Fast Read Opcode
P/N: PM1736
REV. 1.8, DEC. 26, 2011
38
MX25L6445E
Add (h) DW Add Data (h/b)
Data
(h)
Description
Comment
(Byte)
(Bit)
(Note1)
(1-1-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy
04:00
0 0000b
states
Clocks) not support
3Ch
00h
0xFFh
04h
(1-1-2) Fast Read Number of
Mode Bits
000b: Mode Bits not support
07:05
15:08
20:16
000b
0xFFh
(1-1-2) Fast Read Opcode
3Dh
3Eh
3Fh
(1-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy
0 0100b
states
Clocks) not support
(1-2-2) Fast Read Number of
Mode Bits
000b: Mode Bits not support
23:21
000b
(1-2-2) Fast Read Opcode
(2-2-2) Fast Read
Unused
31:24
00
BBh
0b
BBh
0=not support 1=support
0=not support 1=support
03:01
04
111b
0b
40h
EEh
(4-4-4) Fast Read
Unused
07:05
111b
0xFFh
0xFFh
Unused
43h:41h 31:08
45h:44h 15:00
0xFFh
0xFFh
Unused
(2-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy
20:16
46h
0 000b
000b
states
Clocks) not support
00h
(2-2-2) Fast Read Number of
Mode Bits
000b: Mode Bits not support
23:21
(2-2-2) Fast Read Opcode
Unused
47h
31:24
FFh
FFh
49h:48h 15:00
0xFFh
0xFFh
(4-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
20:16
4Ah
0 0000b
states
Clocks) not support
00h
(4-4-4) Fast Read Number of
Mode Bits
000b: Mode Bits not support
23:21
000b
FFh
0Ch
20h
0Fh
52h
10h
D8h
00h
FFh
(4-4-4) Fast Read Opcode
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
53h
31:24
07:00
15:08
23:16
31:24
07:00
15:08
23:16
31:24
FFh
0Ch
20h
0Fh
52h
10h
D8h
00h
FFh
Sector/block size = 2^N bytes (Note5)
0x00b: this sector type doesn't exist
Sector Type 1 Size
Sector Type 1 erase Opcode
Sector Type 2 Size
Sector/block size = 2^N bytes
0x00b: this sector type doesn't exist
Sector Type 2 erase Opcode
Sector Type 3 Size
Sector/block size = 2^N bytes
0x00b: this sector type doesn't exist
Sector Type 3 erase Opcode
Sector Type 4 Size
Sector/block size = 2^N bytes
0x00b: this sector type doesn't exist
Sector Type 4 erase Opcode
P/N: PM1736
REV. 1.8, DEC. 26, 2011
39
MX25L6445E
Table 9. Parameter Table (1): Macronix Flash Parameter Tables
Add (h) DW Add Data (h/b)
Data
(h)
Description
Comment
2000h=2.000V
2700h=2.700V
3600h=3.600V
(Byte)
(Bit)
(Note1)
07:00
15:08
00h
36h
00h
36h
Vcc Supply Maximum Voltage
61h:60h
1650h=1.650V
2250h=2.250V
2350h=2.350V
2700h=2.700V
23:16
31:24
00h
27h
00h
27h
Vcc Supply Minimum Voltage
HW Reset# pin
63h:62h
0=not support 1=support
00
0b
HW Hold# pin
0=not support 1=support
0=not support 1=support
0=not support 1=support
01
02
03
0b
1b
0b
Deep Power Down Mode
SW Reset
Reset Enable (66h) should be issued
before Reset command
1111 1111b
(FFh)
65h:64h
4FF4h
SW Reset Opcode
11:04
Program Suspend/Resume
Erase Suspend/Resume
Unused
0=not support 1=support
0=not support 1=support
12
13
0b
0b
14
1b
Wrap-Around Read mode
Wrap-Around Read mode Opcode
0=not support 1=support
15
0b
66h
67h
23:16
0xFFh
0xFFh
0xFFh
08h:support 8B wrap-around read
16h:8B&16B
32h:8B&16B&32B
Wrap-Around Read data length
31:24
0xFFh
64h:8B&16B&32B&64B
Individual block lock
0=not support 1=support
0=Volatile 1=Nonvolatile
00
01
1b
0b
Individual block lock bit
(Volatile/Nonvolatile)
0011 0110b
(36h)
Individual block lock Opcode
09:02
10
Individual block lock Volatile
protect bit default protect status
0=protect 1=unprotect
0b
C8D9h
6Bh:68h
Secured OTP
Read Lock
Permanent Lock
Unused
0=not support 1=support
0=not support 1=support
0=not support 1=support
11
12
1b
0b
13
0b
15:14
31:16
11b
Unused
0xFFh
0xFFh
0xFFh
0xFFh
Unused
6Fh:6Ch 31:00
P/N: PM1736
REV. 1.8, DEC. 26, 2011
40
MX25L6445E
Note 1: h/b is hexadecimal or binary.
Note 2: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x),
address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1), (2-2-2),
and (4-4-4)
Note 3: Wait States is required dummy clock cycles after the address bits or optional mode bits.
Note 4: Mode Bits is optional control bits that follow the address bits. These bits are driven by the system controller
if they are specified. (eg,read performance enhance toggling bits)
Note 5: 4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h
Note 6: Memory within the SFDP address space that has not yet been defined or used, default to all 0xFFh.
P/N: PM1736
REV. 1.8, DEC. 26, 2011
41
MX25L6445E
POWER-ON STATE
The device is at the following states after power-up:
- Standby mode ( please note it is not Deep Power-down mode)
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage until the VCC reaches the following levels:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal Power-on Reset (POR) circuit may protect the device from data corruption and inadvertent data change
during power up state.
For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not
guaranteed. The read, write, erase, and program command should be sent after the time delay:
- tVSL after VCC reached VCC minimum level
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.
Please refer to the figure of "Power-up Timing".
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended.
(generally around 0.1uF)
P/N: PM1736
REV. 1.8, DEC. 26, 2011
42
MX25L6445E
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
RATING
VALUE
Ambient Operating Temperature
Storage Temperature
Applied Input Voltage
Applied Output Voltage
VCC to Ground Potential
Industrial grade
-40°C to 85°C
-65°C to 150°C
-0.5V to 4.6V
-0.5V to 4.6V
-0.5V to 4.6V
NOTICE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is stress rating only and functional operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended period may affect reliability.
2. Specifications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see Figure 2, 3.
Figure 3. Maximum Positive Overshoot Waveform
Figure 2. Maximum Negative Overshoot Waveform
20ns
20ns
20ns
Vss
Vcc + 2.0V
Vss-2.0V
Vcc
20ns
20ns
20ns
CAPACITANCE TA = 25°C, f = 1.0 MHz
Symbol Parameter
Min.
Typ.
Max.
10
Unit
pF
Conditions
VIN = 0V
CIN
Input Capacitance
COUT Output Capacitance
8
pF
VOUT = 0V
P/N: PM1736
REV. 1.8, DEC. 26, 2011
43
MX25L6445E
Figure 4. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL
Input timing reference level
Output timing reference level
0.8VCC
0.2VCC
0.7VCC
0.3VCC
AC
Measurement
Level
0.5VCC
Note: Input pulse rise and fall time are <5ns
Figure 5. OUTPUT LOADING
DEVICE UNDER
TEST
2.7K ohm
+3.3V
CL
6.2K ohm
DIODES=IN3064
OR EQUIVALENT
CL=30/15pF Including jig capacitance
P/N: PM1736
REV. 1.8, DEC. 26, 2011
44
MX25L6445E
Table 10. DC CHARACTERISTICS
Symbol Parameter
Notes
Min.
Max.
± 2
Units Test Conditions
ILI
Input Load Current
1
1
1
uA VCC = VCC Max, VIN = VCC or GND
uA VCC = VCC Max, VOUT=VCC or GND
uA VIN = VCC or GND, CS# = VCC
ILO
Output Leakage Current
± 2
ISB1 VCC Standby Current
50
Deep Power-down
Current
ISB2
20
22
19
17
15
10
25
uA VIN = VCC or GND, CS# = VCC
fQ=70MHz (4 x I/O read)
mA
SCLK=0.1VCC/0.9VCC, SO=Open
f=104MHz
SCLK=0.1VCC/0.9VCC, SO=Open
mA
fT=70MHz (2 x I/O read)
mA
ICC1 VCC Read
1
1
SCLK=0.1VCC/0.9VCC, SO=Open
f=66MHz
SCLK=0.1VCC/0.9VCC, SO=Open
mA
f=33MHz,
SCLK=0.1VCC/0.9VCC, SO=Open
mA
VCC Program Current
ICC2
(PP)
mA Program in Progress, CS# = VCC
VCC Write Status
ICC3
Program status register in progress,
CS#=VCC
20
25
mA
Register (WRSR) Current
VCC Sector Erase
Current (SE)
ICC4
1
1
mA Erase in Progress, CS#=VCC
mA Erase in Progress, CS#=VCC
VCC Chip Erase Current
ICC5
(CE)
20
VIL
Input Low Voltage
Input High Voltage
-0.5
0.8
V
V
VIH
0.7VCC VCC+0.4
VOL
Output Low Voltage
0.4
V
V
IOL = 1.6mA
IOH = -100uA
VOH Output High Voltage
Notes :
VCC-0.2
1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds).
2. Typical value is calculated by simulation.
P/N: PM1736
REV. 1.8, DEC. 26, 2011
45
MX25L6445E
Table 11. AC CHARACTERISTICS
Symbol Alt. Parameter
Min.
Typ.
Max.
Unit
Clock Frequency for the following instructions:
fSCLK
fC FAST_READ, PP, SE, BE, CE, DP, RES, RDP,
WREN, WRDI, RDID, RDSR, WRSR
D.C.
104
MHz
fRSCLK
fR Clock Frequency for READ instructions
fT Clock Frequency for 2READ instructions
50
70
70
85
50
50
50
20
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
VCC=2.7V-3.6V
VCC=3.0V-3.6V
fQ Clock Frequency for 4READ instructions
fTSCLK
fC2 Clock Frequency for FASTDTRD instructions
fT2 Clock Frequency for 2DTRD instructions
fQ2 Clock Frequency for 4DTRD instructions
Clock Frequency for 4PP (Quad page program)
f4PP
Fast_Read
Read
4.5
9
tCH(1)
tCLH Clock High Time
ns
Fast_Read
Read
4.5
9
0.1
0.1
5
ns
ns
V/ns
V/ns
ns
tCL(1)
tCLL Clock Low Time
tCLCH(2)
tCHCL(2)
Clock Rise Time (3) (peak to peak)
Clock Fall Time (3) (peak to peak)
tSLCH tCSS CS# Active Setup Time (relative to SCLK)
tCHSL CS# Not Active Hold Time (relative to SCLK)
tDVCH tDSU Data In Setup Time
5
2
ns
ns
tCHDX
tCHSH
tSHCH
tDH Data In Hold Time
5
5
5
ns
ns
ns
CS# Active Hold Time (relative to SCLK)
CS# Not Active Setup Time (relative to SCLK)
Read
Write/Erase/
Program
15
ns
tSHSL(3) tCSH CS# Deselect Time
50
ns
VCC=2.7V-3.6V
VCC=3.0V-3.6V
10
8
ns
ns
ns
tSHQZ(2) tDIS Output Disable Time
1 I/O
9
Loading: 15pF
Clock Low to Output Valid
tCLQV
tV
2 I/O & 4 I/O
Loading: 30pF 2 I/O & 4 I/O
9.5
12
ns
ns
VCC=2.7V~3.6V
Clock Low to Output Valid (DTR mode)
VCC=2.7V~3.6V, Loading: 15pF
1 I/O, 2 I/O &
4 I/O
tCLQV2 tV2
9.5
ns
tCLQX
tWHSL
tSHWL
tDP(2)
tHO Output Hold Time
2
20
100
ns
ns
ns
us
Write Protect Setup Time
Write Protect Hold Time
CS# High to Deep Power-down Mode
10
CS# High to Standby Mode without Electronic Signature
Read
CS# High to Standby Mode with Electronic Signature Read
Write Status Register Cycle Time
Byte-Program
tRES1(2)
100
us
tRES2(2)
tW
tBP
tPP
tSE
tBE
100
100
300
5
300
2
us
ms
us
ms
ms
s
40
9
1.4
60
0.5
0.7
Page Program Cycle Time
Sector Erase Cycle Time (4KB)
Block Erase Cycle Time (32KB)
Block Erase Cycle Time (64KB)
tBE
2
s
P/N: PM1736
REV. 1.8, DEC. 26, 2011
46
MX25L6445E
Symbol Alt. Parameter
Min.
Typ.
50
Max.
80
1
Unit
s
ms
ms
tCE
Chip Erase Cycle Time
tWPS
tWSR
Write Protection Selection Time
Write Security Register Time
1
Notes:
1. tCH + tCL must be greater than or equal to 1/ fC.
2. Value guaranteed by characterization, not 100% tested in production.
3. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
P/N: PM1736
REV. 1.8, DEC. 26, 2011
47
MX25L6445E
Timing Analysis
Figure 6. Serial Input Timing
tSHSL
tSHCH
tCHCL
CS#
tCHSL
tSLCH
tCHSH
SCLK
tDVCH
tCHDX
tCLCH
MSB
LSB
SI
High-Z
SO
Figure 7. Output Timing
CS#
tCH
SCLK
tCLQV
tCLQV
tCL
tSHQZ
tCLQX
SO
tCLQX
LSB
ADDR.LSB IN
SI
P/N: PM1736
REV. 1.8, DEC. 26, 2011
48
MX25L6445E
Figure 8. Serial Input Timing for Double Transfer Rate Mode
tSHSL
tSHCH
tCHCL
CS#
tSLCH
tCHSL
tCHSH
SCLK
tDVCH
tDVCH
tCHDX
tCHDX
MSB
tCLCH
LSB
SI
High-Z
SO
Figure 9. Serial Output Timing for Double Transfer Rate Mode
CS#
tCH
SCLK
tCLQV2
tCLQV2
tCLQX
tCLQV2
tCL
tSHQZ
tCLQX
LSB
SO
SI
ADDR.LSB IN
P/N: PM1736
REV. 1.8, DEC. 26, 2011
49
MX25L6445E
Figure 10. WP# Setup Timing and Hold Timing during WRSR when SRWD=1
WP#
CS#
tSHWL
tWHSL
0
1
2
3
4
5
6
7
8
9
10 11 12
13 14
15
SCLK
01
SI
High-Z
SO
Figure 11. Write Enable (WREN) Sequence (Command 06)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
06
SI
High-Z
SO
Figure 12. Write Disable (WRDI) Sequence (Command 04)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
04
SI
High-Z
SO
P/N: PM1736
REV. 1.8, DEC. 26, 2011
50
MX25L6445E
Figure 13. Read Identification (RDID) Sequence (Command 9F)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
28 29 30 31
SCLK
SI
Command
9F
Manufacturer Identification
Device Identification
High-Z
SO
D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13
D3 D2 D1 D0
MSB
MSB
Figure 14. Read Status Register (RDSR) Sequence (Command 05)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI
command
05
Status Register Out
High-Z
D7 D6 D5 D4 D3 D2 D1 D0
MSB
SO
Figure 15. Write Status Register (WRSR) Sequence (Command 01)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
Status
Register In
command
01
SI
D7 D6 D5 D4 D3 D2 D1 D0
MSB
High-Z
SO
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MX25L6445E
Figure 16. Read Data Bytes (READ) Sequence (Command 03)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
03
24 ADD Cycles
A23 A22 A21
MSB
A3 A2 A1 A0
SI
Data Out 2
Data Out 1
High-Z
D7 D6 D5 D4 D3 D2 D1 D0 D7
MSB MSB
SO
Figure 17. Read at Higher Speed (FAST_READ) Sequence (Command 0B)
CS#
47
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
28 29 30 31
0
1
2
3
4
5
6
7
8
9
10
SCLK
Command
0B
8 Dummy Cycles
24 ADD Cycles
SI
A23 A22 A21
A3 A2 A1 A0
Data Out 1
Data Out 2
High-Z
SO
D7 D6 D5 D4 D3 D2 D1 D0 D7
MSB
Figure 18. Fast DT Read (FASTDTRD) Sequence (Command 0D)
CS#
8
7
25
26
27
28
29
19
0
SCLK
6 Dummy
Cycles
Command
12 ADD Cycles
Data Out
2
Data Out
1
A23
A1 A0
A22
0D
SI/SIO0
D7 D6 D5 D4 D3 D2 D1 D0 D7
SO/SIO1
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MX25L6445E
Figure 19. 2 x I/O Read Mode Sequence (Command BB)
CS#
28 29
18 19 20 21 22 23 24 25 26 27
0
1
2
3
4
5
6
7
8
9
SCLK
Data Out
Data Out
4 dummy
cycle
Command
12 ADD Cycle
2
1
A22 A20
A23 A21
A2 A0
P0
D4 D2
D6 D4
D7 D5
P2
BB(hex)
D6
D7
D0
D1
SI/SIO0
High Impedance
A3 A1 P3
P1
D5 D3
SO/SIO1
Note: SI/SIO0 or SO/SIO1 should be kept "0h" or "Fh" in the first two dummy cycles. In other words, P2=P0 or
P3=P1 is necessary.
Figure 20. Fast Dual I/O DT Read (2DTRD) Sequence (Command BD)
CS#
0
7
8
13
14
19
20
21
22
23
SCLK
Data Out
1
6 Dummy
Cycles
Command
6 ADD Cycles
Data Out
2
SI/SIO0
P2 P0
P3 P1
BD
A22 A20
A2 A0
A3 A1
D6 D4 D2 D0 D6 D4 D2 D0 D6
D7 D5 D3 D1 D7 D5 D3 D1 D7
A23 A21
SO/SIO1
Note: SI/SIO0 or SO/SIO1 should be kept "0h" or "Fh" in the first two dummy cycles. In other words, P2=P0 or
P3=P1 is necessary.
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MX25L6445E
Figure 21. 4 x I/O Read Mode Sequence (Command EB)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22
SCLK
4 dummy
cycles
Data
Out 2
Data
Out 3
Command
EB
6 ADD Cycles
Data
Out 1
Performance
Enhance
Indicator
(Note1, 2)
A20 A16 A12 A8 A4 A0
D4 D0 D4 D0 D4
P4 P0
P5 P1
P6 P2
P7 P3
SI/SIO0
High Impedance
High Impedance
High Impedance
SO/SIO1
WP#/SIO2
NC/SIO3
D5 D1 D5 D1 D5
D6 D2 D6 D2 D6
A21 A17 A13 A9 A5 A1
A22 A18 A14 A10 A6 A2
A23 A19 A15 A11 A7 A3
D7 D3 D7 D3 D7
Notes:
1. Hi-impedance is inhibited for the two clock cycles.
2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) will result in entering the performance enhance mode.
Figure 22. 4 x I/O Read Enhance Performance Mode Sequence (Command EB)
CS#
n+1
n+7
n+9
n+13
0
1
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
4 dummy
cycles
6 ADD Cycles
Command
6 ADD
Cycles
Data
Out 2
Data
Out 1
4 dummy
cycles
Data
Out 3
Data
Out 2
Data
Out 1
Performance
enhance
indicator (Note)
Performance
enhance
indicator (Note)
A20 A16 A12 A8 A4 A0
D4 D0 D4 D0
A20
A0
P4 P0
P4 P0
EB
D4 D0 D4 D0 D4
SI/SIO0
SO/SIO1
WP#/SIO2
NC/SIO3
High Impedance
High Impedance
High Impedance
D5 D1 D5 D1
D6 D2 D6 D2
A21 A17 A13 A9 A5 A1
A22 A18 A14 A10 A6 A2
A21
A22
A1
A2
P5 P1
P6 P2
P7 P3
P5 P1
P6 P2
P7 P3
D5 D1 D5 D1 D5
D6 D2 D6 D2 D6
A23 A19 A15 A11 A7 A3
D7 D3 D7 D3
A23
A3
D7 D3 D7 D3 D7
Notes:
1. Performance enhance mode: if P7≠P3 & P6≠P2 & P5≠P1 & P4≠P0 (Toggling), ex: A5, 5A, F0, 0F.
2. Reset the performance enhance mode: if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 55, 00, FF.
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MX25L6445E
Figure 23. Fast Quad I/O DT Read (4DTRD) Sequence (Command ED)
CS#
0
7
8
9
10
11
18
19
20
SCLK
Command
7 Dummy
cycles
1 cycle
Performance
3 ADD Cycles
Enhance Indicator
(Note1,2)
SI/SIO0
ED
A20 A16
A21 A17
A4 A0 P4 P0
D4 D0 D4 D0 D4
D5 D1 D5 D1 D5
P5
A5 A1
A6 A2
P1
SO/SIO1
P2
P3
A22 A18
A23 A19
P6
P7
WP#/SIO2
NC/SIO3
D6 D2 D6 D2 D6
D7 D3 D7 D3 D7
A3
A7
Notes:
1. Hi-impedance is inhibited for this clock cycle.
2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) will result in entering the performance enhance mode.
Figure 24. Fast Quad I/O DT Read (4DTRD) Enhance Performance Sequence (Command ED)
CS#
10
11
18
19
20
0
7
8
9
SCLK
1 cycle
1 cycle
Performance
enhance
3 ADD Cycles
3 ADD Cycles
Command
7 Dummy Data Out Data Out
7 Dummy Data Out Data Out
Performance
enhance
cycles
1
2
cycles
1
2
indicator (Note)
indicator (Note)
SI/SIO0
A0
A0
A20 A16
A21 A17
A4
P4 P0
P5 P1
P6 P2
P7 P3
D4 D0 D4 D0
D5 D1 D5 D1
D6 D2 D6 D2
D7 D3 D7 D3
A20 A16
A4
A5
A6
A7
P4 P0
P5 P1
P6 P2
P7 P3
D4 D0 D4 D0 D4
D5 D1 D5 D1 D5
D6 D2 D6 D2 D6
D7 D3 D7 D3 D7
ED (hex)
A1
A2
A1
A2
A21 A17
A22 A18
A23 A19
SO/SIO1
A5
A6
A7
WP#/SIO2
NC/SIO3
A22 A18
A23 A19
A3
A3
Note: Performance enhance, if P7≠P3 & P6≠P2 & P5≠P1 & P4≠P0 (Toggle)
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MX25L6445E
Figure 25. Sector Erase (SE) Sequence (Command 20)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
…
24 ADD Cycles
Command
20
…
A23 A22
A2 A1 A0
SI
MSB
Figure 26. Block Erase (BE/BE32K) Sequence (Command D8/52)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
…
24 ADD Cycles
Command
D8/52
…
A23 A22
A2 A1 A0
SI
MSB
Figure 27. Chip Erase (CE) Sequence (Command 60 or C7)
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
60 or C7
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MX25L6445E
Figure 28. Page Program (PP) Sequence (Command 02)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
02
24 ADD Cycles
Data Byte 1
Data Byte 256
A23 A22 A21
MSB
A3 A2 A1 A0
D7 D6 D5 D4 D3 D2
MSB
D0
D1
D7 D6 D5 D4 D3 D2 D1 D0
SI
Figure 29. 4 x I/O Page Program (4PP) Sequence (Command 38)
CS#
524 525
10 11 12 13 14 15 16 17
0
1
2
3
4
5
6
7
8
9
SCLK
Data
Byte 256
Data Data
Byte 1 Byte 2
Command
38
6 ADD cycles
D4 D0 D4 D0
D4 D0
A20 A16 A12 A8 A4 A0
SI/SIO0
D5 D1 D5 D1
D6 D2 D6 D2
D7 D3 D7 D3
D5 D1
D6 D2
D7 D3
SO/SIO1
WP#/SIO2
NC/SIO3
A21 A17 A13 A9 A5 A1
A22 A18 A14 A10 A6 A2
A23 A19 A15 A11 A7 A3
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MX25L6445E
Figure 30. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD)
CS#
SCLK
SI
20 2122 23 24
0
1
30 31 31 32
47 48
0
7
7
8
0
6
7 8
0
1
6 7 8 9
Command
AD (hex)
data in
Byte n-1, Byte n
Valid
Command (1)
data in
04 (hex)
05 (hex)
24-bit address
Byte 0, Byte1
high impedance
status (2)
S0
Notes:
(1) During CP mode, the valid commands are CP command (AD hex), WRDI command (04 hex), RDSR command
(05 hex), and RDSCUR command (2B hex).
(2) Once an internal programming operation begins, CS# goes low will drive the status on the SO pin and CS#
goes high will return the SO pin to tri-state.
(3) To end the CP mode, either reaching the highest unprotected address or sending Write Disable (WRDI) com-
mand (04 hex) may achieve it and then it is recommended to send RDSR command (05 hex) to verify if CP
mode is ended.
Figure 31. Deep Power-down (DP) Sequence (Command B9)
CS#
t
DP
0
1
2
3
4
5
6
7
SCLK
SI
Command
B9
Stand-by Mode
Deep Power-down Mode
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MX25L6445E
Figure 32. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38
39
SCLK
Command
AB
24 ADD Cycles
t
RES2
…
SI
A23 A22 A21
MSB
A3 A2 A1 A0
Electronic Signature Out
High-Z
D7
D1
D0
D6 D5 D4 D3 D2
SO
MSB
Deep Power-down Mode
Stand-by Mode
Figure 33. Release from Deep Power-down (RDP) Sequence (Command AB)
CS#
t
RES1
0
1
2
3
4
5
6
7
SCLK
SI
Command
AB
High-Z
SO
Deep Power-down Mode
Stand-by Mode
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REV. 1.8, DEC. 26, 2011
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MX25L6445E
Figure 34. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF or CF)
CS#
0
1
2
3
4
5
6
7
8
9
10
47
30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
28
29
SCLK
Command
90
24 ADD Cycles
SI
A0
A1
A3 A2
A23 A22 A21
Manufacturer ID
Device ID
High-Z
SO
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
MSB
MSB
MSB
Notes:
1. A0=0 will output the Manufacturer ID first and A0=1 will output Device ID first. A1~A23 is don't care.
2. Instruction is either 90(hex) or EF(hex) or DF(hex) or CF(hex).
Figure 35. Write Protection Selection (WPSEL) Sequence (Command 68)
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
68
P/N: PM1736
REV. 1.8, DEC. 26, 2011
60
MX25L6445E
Figure 36. Single Block Lock/Unlock Protection (SBLK/SBULK) Sequence (Command 36/39)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
36/39
24 Bit Address
Cycles
A23 A22
A2 A1 A0
SI
MSB
Figure 37. Read Block Protection Lock Status (RDBLOCK) Sequence (Command 3C)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
3C
24 ADD Cycles
SI
A23 A22 A21
MSB
A3 A2 A1 A0
Block Protection Lock status out
High-Z
D7 D6 D5 D4 D3 D2 D1 D0
MSB
SO
Figure 38. Gang Block Lock/Unlock (GBLK/GBULK) Sequence (Command 7E/98)
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
7E/98
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MX25L6445E
Figure 39. Power-up Timing
V
CC
V
(max)
CC
Chip Selection is Not Allowed
V
(min)
CC
Device is fully accessible
tVSL
time
Note: VCC (max.) is 3.6V and VCC (min.) is 2.7V.
Table 12. Power-Up Timing
Symbol
Parameter
Min.
Max.
Unit
tVSL(1)
VCC(min) to CS# low
300
us
Note: The parameter is characterized only.
INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status
Register contains 00h (all Status Register bits are 0).
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MX25L6445E
OPERATING CONDITIONS
At Device Power-Up and Power-Down
AC timing illustrated in Figure 40 and Figure 41 are for the supply voltages and the control signals at device power-
up and power-down. If the timing in the figures is ignored, the device will not operate correctly.
During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be
selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.
Figure 40. AC Timing at Device Power-Up
VCC(min)
VCC
GND
tVR
tSHSL
CS#
tSHCH
tSLCH
tCHSL
tCHSH
SCLK
tDVCH
tCHCL
tCHDX
tCLCH
MSB IN
LSB IN
SI
High Impedance
SO
Symbol
tVR
Parameter
VCC Rise Time
Notes
Min.
20
Max.
500000
Unit
us/V
1
Notes :
1. Sampled, not 100% tested.
2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to
"AC CHARACTERISTICS" table.
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MX25L6445E
Figure 41. Power-Down Sequence
During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.
VCC
CS#
SCLK
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MX25L6445E
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ. (1)
40
Max. (2)
Unit
ms
ms
s
Write Status Register Cycle Time
Sector Erase Time (4KB)
Block Erase Time (64KB)
Block Erase Time (32KB)
Chip Erase Time
100
300
2
60
0.7
0.5
2
s
50
80
300
5
s
Byte Program Time (via page program command)
Page Program Time
9
us
1.4
ms
cycles
Erase/Program Cycle
100,000
Notes:
1. Typical program and erase time assumes the following conditions: 25°C, 3.3V, and checker board pattern.
2. Under worst conditions of 85°C and 2.7V.
3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming com-
mand.
DATA RETENTION
Parameter
Condition
Min.
Max.
Unit
Data retention
55˚C
20
years
LATCH-UP CHARACTERISTICS
Min.
Max.
Input Voltage with respect to GND on all power pins, SI, CS#
Input Voltage with respect to GND on SO
Current
-1.0V
-1.0V
-100mA
2 VCCmax
VCC + 1.0V
+100mA
Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.
P/N: PM1736
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MX25L6445E
ORDERING INFORMATION
PART NO.
CLOCK
(MHz)
TEMPERATURE
-40°C~85°C
-40°C~85°C
-40°C~85°C
PACKAGE
Remark
RoHS
Compliant
RoHS
Compliant
RoHS
16-SOP
(300mil)
MX25L6445EMI-10G
MX25L6445EM2I-10G
MX25L6445EZNI-10G
104
104
104
8-SOP
(200mil)
8-WSON
(8x6mm)
Compliant
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MX25L6445E
PART NAME DESCRIPTION
MX 25 L 6445E
M
I
10 G
OPTION:
G: RoHS Compliant
SPEED:
10: 104MHz
TEMPERATURE RANGE:
I: Industrial (-40° C to 85° C)
PACKAGE:
M: 300mil 16-SOP
M2: 200mil 8-SOP
ZN: 8x6mm 8-WSON
DENSITY & MODE:
6445E: 64Mb standard type
TYPE:
L: 3V
DEVICE:
25: Serial Flash
P/N: PM1736
REV. 1.8, DEC. 26, 2011
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MX25L6445E
PACKAGE INFORMATION
P/N: PM1736
REV. 1.8, DEC. 26, 2011
68
MX25L6445E
P/N: PM1736
REV. 1.8, DEC. 26, 2011
69
MX25L6445E
P/N: PM1736
REV. 1.8, DEC. 26, 2011
70
MX25L6445E
REVISION HISTORY
Revision No. Description
Page
P5
Date
MAY/19/2009
1.0
1. Removed "Preliminary"
2. Merge MX25L6445E and MX25L12845E together
3. Add CFI mode content
4. Align waveform format
All
P37
All
5. Modify tCH/tCL value, from rev0.06 tCH/tCL=5.5ns
to rev1.0 tCH/tCL(FAST_READ/READ)=4.5/9ns
6. Change command table format
7. Added "DATA RETENTION" Condition
8. Modified sector erase time from 90ms to 60ms
P43,45
P15,16
P66
P5,43,46,
P66
9. Modified 128Mb chip erase time (max) from 512s to 200s
1. Added 128M 8-WSON EPN
2. Change RDCFI command from A5 to 5A
1. Added DMC Code content table
2. Removed MX25L12845EZNI-10G advanced information remark
3. Changed the naming "CFI mode" as "DMC mode"
1. Corrected error
P46,66
P67
P16,37
P37~39
P69
1.1
1.2
JUL/16/2009
OCT/21/2009
All
1.3
P8,43,44,54 APR/01/2010
P68
2. Added wording "e.g. Vcc and CS# ramp up simultaneously"
3. Modified low active read and standby current consumption
and deep power down current consumption
P67
P5,43~44,69
4. Deleted parallel mode condition
P43
5. Modified table of "Read DMC mode (RDDMC)"
6. Added "Input Test Waveforms And Measurement Level"
7. Modified tSLCH, tSHCH from 8ns to 5ns
P37~39
P42
P45,47
1.4
1.5
1. Removed DMC sequence description & content table
2. Revised low active read current spec
P6,14,16,37 JUL/14/2010
P5
3. Revised Table 7-1 and Table 7-2
P40-41
1. Removed MX25L12845E information from the previous combined
version of MX25L6445E/MX25L12845E
All
AUG/19/2011
2. Modified description for RoHS compliance
P6,60,61
3. Revised Figure 18. Fast DT Read (FASTDTRD) Sequence
Figure 20. Fast Dual I/O DT Read (2DTRD) Sequence;
Figure 23. Fast Quad I/O DT Read (4DTRD) Sequence; and
Figure 24. Fast Quad I/O DT Read (4DTRD) Enhance Performance.
4. Corrected ILO TEST CONDITIONS in Table 7
5. Revised Storage Temperature
P46,47,49
P39
P37
1.6
1. Changed Quad I/O Read Frequency from 80MHz@VCC=3.0V~3.6V P40
to 85MHz@VCC=3.0V~3.6V
SEP/13/2011
1.7
1.8
1. Revised the description in The individual block lock mode
1. Modified Input Capacitance
P31
P43
OCT/05/2011
DEC/26/2011
2. Modified Figure 41. Power-Down Sequence
3. Added Read SFDP (RDSFDP) Mode
P64
P6,13,14,
P36~41
P66
4. Changed ordering information format
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Except for customized products which has been expressly identified in the applicable agreement, Macronix's
products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or
household applications only, and not for use in any applications which may, directly or indirectly, cause death,
personal injury, or severe property damages. In the event Macronix products are used in contradicted to their
target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its
actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or
distributors shall be released from any and all liability arisen therefrom.
Copyright© Macronix International Co., Ltd. 2009~2011. All rights reserved.
Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, NBiit, Macronix NBit, eLiteFlash,
XtraROM, Phines, BE-SONOS, KSMC, Kingtech, MXSMIO, Macronix vEE are trademarks or registered
trademarks of Macronix International Co., Ltd. The names and brands of other companies are for identification
purposes only and may be claimed as the property of the respective companies.
For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com
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