MX25U12843GBBI00_技术文档

ADVANCED INFORMATION

MX25U12843G

1.8V, 128M-BIT [x 1/x 2/x 4]

CMOS MXSMIO^®(SERIAL MULTI I/O)

FLASH MEMORY

Key Features

• Protocol Support - Single I/O, Dual I/O and Quad I/O

• Support DTR (Double Transfer Rate) Mode

• Support clock frequency up to 133MHz

• Quad Peripheral Interface (QPI) Read / Program Mode

Macronix Proprietary

P/N: PM2705

Rev. 0.00, February 26, 2019

1

ADVANCED INFORMATION

MX25U12843G

Contents

1. FEATURES ..............................................................................................................................................................4

2. GENERAL DESCRIPTION .....................................................................................................................................5

Table 1. Read performance Comparison ....................................................................................................5

3. PIN CONFIGURATIONS .........................................................................................................................................6

4. PIN DESCRIPTION..................................................................................................................................................6

5. BLOCK DIAGRAM...................................................................................................................................................7

6. DATA PROTECTION................................................................................................................................................8

Table 2. Protected Area Sizes.....................................................................................................................9

Table 3. 4K-bit Secured OTP Deﬁnition ....................................................................................................10

7. Memory Organization........................................................................................................................................... 11

Table 4. Memory Organization ..................................................................................................................11

8. DEVICE OPERATION............................................................................................................................................12

8-1. Quad Peripheral Interface (QPI) Read Mode .......................................................................................... 15

9. COMMAND DESCRIPTION...................................................................................................................................16

Table 5. Command Set..............................................................................................................................16

9-1. Write Enable (WREN).............................................................................................................................. 20

9-2. Write Disable (WRDI)............................................................................................................................... 21

9-3. Factory Mode Enable (FMEN)................................................................................................................. 22

9-4. Read Identiﬁcation (RDID)....................................................................................................................... 23

9-5. Release from Deep Power-down (RDP), Read Electronic Signature (RES) ........................................... 24

9-6. Read Electronic Manufacturer ID & Device ID (REMS)........................................................................... 26

9-7. QPI ID Read (QPIID) ............................................................................................................................... 27

Table 6. ID Deﬁnitions ..............................................................................................................................27

9-8. Read Status Register (RDSR)................................................................................................................. 28

9-9. Read Conﬁguration Register (RDCR)...................................................................................................... 29

Table 7. Status Register............................................................................................................................32

Table 8. Conﬁguration Register.................................................................................................................33

Table 9. Output Driver Strength Table.......................................................................................................34

Table 10. Dummy Cycle and Frequency Table (MHz)...............................................................................34

9-10. Write Status Register (WRSR)................................................................................................................. 35

Table 11. Protection Modes.......................................................................................................................36

9-11. Read Data Bytes (READ) ........................................................................................................................ 39

9-12. Read Data Bytes at Higher Speed (FAST_READ) .................................................................................. 40

9-13. Dual Output Read Mode (DREAD).......................................................................................................... 42

9-14. 2 x I/O Read Mode (2READ) ................................................................................................................... 43

9-15. Quad Read Mode (QREAD) .................................................................................................................... 44

9-16. 4 x I/O Read Mode (4READ) ................................................................................................................... 45

9-17. 4 x I/O Double Transfer Rate Read Mode (4DTRD)................................................................................ 48

9-18. Preamble Bit ........................................................................................................................................... 50

9-19. Burst Read............................................................................................................................................... 54

9-20. Performance Enhance Mode................................................................................................................... 55

9-21. Sector Erase (SE).................................................................................................................................... 58

9-22. Block Erase (BE32K)............................................................................................................................... 59

9-23. Block Erase (BE) ..................................................................................................................................... 60

9-24. Chip Erase (CE)....................................................................................................................................... 61

9-25. Page Program (PP) ................................................................................................................................. 62

9-26. 4 x I/O Page Program (4PP).................................................................................................................... 64

9-27. Deep Power-down (DP)........................................................................................................................... 65

9-28. Enter Secured OTP (ENSO).................................................................................................................... 66

9-29. Exit Secured OTP (EXSO)....................................................................................................................... 66

Macronix Proprietary

P/N: PM2705

Rev. 0.00, February 26, 2019

2

ADVANCED INFORMATION

MX25U12843G

9-30. Read Security Register (RDSCUR)......................................................................................................... 66

9-31. Write Security Register (WRSCUR)......................................................................................................... 66

Table 12. Security Register Deﬁnition .......................................................................................................67

9-32. Write Protection Selection (WPSEL)........................................................................................................ 68

9-33. Single Block Lock/Unlock Protection (SBLK/SBULK).............................................................................. 71

9-34. Read Block Lock Status (RDBLOCK)...................................................................................................... 73

9-35. Gang Block Lock/Unlock (GBLK/GBULK) ............................................................................................... 73

9-36. Program Suspend and Erase Suspend .................................................................................................. 74

Table 13. Readable Area of Memory While a Program or Erase Operation is Suspended.......................74

Table 14. Acceptable Commands During Program/Erase Suspend after tPSL/tESL................................75

Table 15. Acceptable Commands During Suspend (tPSL/tESL not required)...........................................75

9-37. Program Resume and Erase Resume..................................................................................................... 76

9-38. No Operation (NOP) ................................................................................................................................ 77

9-39. Software Reset (Reset-Enable (RSTEN) and Reset (RST)) ................................................................... 77

9-40. Read SFDP Mode (RDSFDP).................................................................................................................. 79

10. RESET..................................................................................................................................................................80

Table 16. Reset Timing-(Power On)..........................................................................................................80

Table 17. Reset Timing-(Other Operation) ................................................................................................80

11. POWER-ON STATE .............................................................................................................................................81

12. ELECTRICAL SPECIFICATIONS........................................................................................................................82

Table 18. ABSOLUTE MAXIMUM RATINGS ............................................................................................82

Table 19. CAPACITANCE TA = 25°C, f = 1.0 MHz....................................................................................82

Table 20. DC CHARACTERISTICS (Temperature = -40 C to 85 C, VCC = 1.65V - 2.0V) ......................84

°

Table 21. AC CHARACTERISTICS (Temperature = -40 C to 85 C, VCC = 1.65V - 2.0V) .....................85

°

13. OPERATING CONDITIONS.................................................................................................................................87

Table 22. Power-Up/Down Voltage and Timing ........................................................................................89

13-1. INITIAL DELIVERY STATE...................................................................................................................... 89

14. ERASE AND PROGRAMMING PERFORMANCE..............................................................................................90

15. ERASE AND PROGRAMMING PERFORMANCE (Factory Mode) ..................................................................90

16. DATA RETENTION ..............................................................................................................................................91

17. LATCH-UP CHARACTERISTICS........................................................................................................................91

18. ORDERING INFORMATION................................................................................................................................92

19. PART NAME DESCRIPTION...............................................................................................................................93

20. PACKAGE INFORMATION..................................................................................................................................94

20-1. 8-land WSON (6x5mm)............................................................................................................................ 94

20-2. 8-pin SOP (200mil) .................................................................................................................................. 95

20-3. 16-ball WLCSP (Ball Diameter 0.30mm) ................................................................................................. 96

Macronix Proprietary

P/N: PM2705

Rev. 0.00, February 26, 2019

3

ADVANCED INFORMATION

MX25U12843G

1.8V 128M-BIT [x 1/x 2/x 4] CMOS MXSMIO^®(SERIAL MULTI I/O)

FLASH MEMORY

1. FEATURES

GENERAL

•

Command Reset

•

Supports Serial Peripheral Interface -- Mode 0 and

Mode 3

Program/Erase Suspend and Resume operation

Electronic Identiﬁcation

•

Single Power Supply Operation

- 1.65 to 2.0 volt for read, erase, and program op-

erations

JEDEC 1-byte manufacturer ID and 2-byte device

ID

-

- RES command for 1-byte Device ID

- REMS command for 1-byte manufacturer ID and

1-byte device ID

Support Serial Flash Discoverable Parameters

(SFDP) mode

•

134,217,728 x 1 bit structure

or 67,108,864 x 2 bits (two I/O mode) structure

or 33,554,432 x 4 bits (four I/O mode) structure

Protocol Support

•

- Single I/O, Dual I/O and Quad I/O

Latch-up protected to 100mA from -1V to Vcc +1V

Low Vcc write inhibit is from 1.0V to 1.4V

Fast read for SPI mode

HARDWARE FEATURES

•

SCLK Input

- Serial clock input

•

SI/SIO0

- Support clock frequency up to 133MHz

- Support Fast Read, 2READ, DREAD, 4READ,

QREAD instructions

- Support DTR (Double Transfer Rate) Mode

- Conﬁgurable dummy cycle number for fast read

operation

Quad Peripheral Interface (QPI) available

Equal Sectors with 4K byte each, or Equal Blocks

with 32K byte each or Equal Blocks with 64K byte

each

- Any Block can be erased individually

Programming:

- Serial Data Input or Serial Data Input/Output for 2

x I/O read mode and 4 x I/O read mode

SO/SIO1

- Serial Data Output or Serial Data Input/Output for

2 x I/O read mode and 4 x I/O read mode

WP#/SIO2

- Hardware Write Protection or Serial Data Input/

Output for 4 x I/O read mode

RESET#/SIO3

- Hardware Reset pin or Serial Data Input/Output for

4 x I/O read mode

•

PACKAGE

- 256byte page buffer

- 8-pin SOP (200mil)

- Quad Input/Output page program(4PP) to enhance

program performance

Typical 100,000 erase/program cycles

20 years data retention

- 16-ball WLCSP (Ball Diameter 0.30mm)

- All devices are RoHS Compliant and Halogen-

free

•

SOFTWARE FEATURES

•

Input Data Format

- 1-byte Command code

•

Advanced Security Features

- Block lock protection

The BP0-BP3 and T/B status bits deﬁne the size of

the area to be protected against program and erase

instructions

- Individual sector protection function (Solid Protect)

Additional 4K bit security OTP

•

Features unique identiﬁer

Factory locked identiﬁable, and customer lockable

-

Macronix Proprietary

P/N: PM2705

Rev. 0.00, February 26, 2019

4

ADVANCED INFORMATION

MX25U12843G

2. GENERAL DESCRIPTION

MX25U12843G is 128Mb bits Serial NOR Flash memory, which is conﬁgured as 16,777,216 x 8 internally. When

it is in two or four I/O mode, the structure becomes 67,108,864 bits x 2 or 33,554,432 bits x 4. MX25U12843G

features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in

single I/O mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO).

Serial access to the device is enabled by CS# input.

When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits

input and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# and RESET# pin become SIO0

pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output.

The MX25U12843G MXSMIO^®(Serial Multi I/O) provides sequential read operation on the whole chip.

After program/erase command is issued, auto program/erase algorithms which program/erase and verify the

speciﬁed page or sector/block locations will be executed. Program command is executed on byte basis, or page (256

bytes) basis, or word basis. Erase command is executed on 4K-byte sector, 32K-byte block, or 64K-byte block, or

whole chip basis.

To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read

command can be issued to detect completion status of a program or erase operation via WIP bit.

Advanced security features enhance the protection and security functions, please see security features section for

more details.

When the device is not in operation and CS# is high, it is put in standby mode.

The MX25U12843G utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after

100,000 program and erase cycles.

Table 1. Read performance Comparison

SPI

QPI

Numbers

of Dummy

Cycles

Dual Output Quad Output Dual I/O

Quad I/O Quad I/O DT Quad IO Quad I/O DT

Fast Read

(MHz)

Fast Read

(MHz)

Fast Read

(MHz)

Fast Read

(MHz)

Fast Read

(MHz)

Read

(MHz)

Fast Read

(MHz)

Read

(MHz)

4

-

84*

66

-

66

-

6

8

-

133*

-

133*

-

114*

-

114

-

84*

104

120

54*

66

84

84*

104

120

54*

66

84

10

Notes:

1. * mean default status.

Macronix Proprietary

P/N: PM2705

Rev. 0.00, February 26, 2019

5

ADVANCED INFORMATION

MX25U12843G

3. PIN CONFIGURATIONS

8-PIN SOP (200mil)

4. PIN DESCRIPTION

SYMBOL

DESCRIPTION

CS#

Chip Select

Serial Data Input (for 1 x I/O)/ Serial

Data Input & Output (for 2xI/O or

4xI/O read mode)

Serial Data Output (for 1 x I/O)/

Serial Data Input & Output (for 2xI/O

or 4xI/O read mode)

1

2

3

4

CS#

SO/SIO1

WP#/SIO2

GND

VCC

8

7

6

5

SI/SIO0

RESET#/SIO3

SCLK

SI/SIO0

SO/SIO1

SCLK

Clock Input

Write Protection Active Low or Serial

WP#*/SIO2 Data Input & Output (for 4xI/O read

mode)

Hardware Reset Pin Active low or

RESET#*/SIO3 Serial Data Input & Output (for 4xI/O

read mode)

16-BALL BGA (WLCSP) TOP View

1

2

3

4

VCC

GND

NC

+ 1.8V Power Supply

Ground

No Connection

A

B

*Note: The pin of RESET#/SIO3 or WP#/SIO2 will

remain internal pull up function while this

pin is not physically connected in system

conﬁguration.

NC

CS#

VCC

RESET#/SIO3 SO/SIO1

NC

However, the internal pull up function will be

disabled if the system has physical connection

to RESET#/SIO3 or WP#/SIO2 pin.

C

D

SCLK

WP#/SIO2

GND

NC

SI/SIO0

Macronix Proprietary

P/N: PM2705

Rev. 0.00, February 26, 2019

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ADVANCED INFORMATION

MX25U12843G

5. BLOCK DIAGRAM

Address

Generator

Memory Array

Y-Decoder

SI/SIO0

SO/SIO1

SIO2 *

Data

Register

SIO3 *

WP# *

SRAM

Buffer

Sense

Amplifier

HOLD# *

RESET# *

CS#

Mode

Logic

State

Machine

HV

Generator

SCLK

Clock Generator

Output

Buffer

* Depends on part number options.

Macronix Proprietary

P/N: PM2705

Rev. 0.00, February 26, 2019

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ADVANCED INFORMATION

MX25U12843G

6. DATA PROTECTION

During power transition, there may be some false system level signals which result in inadvertent erasure or

programming. The device is designed to protect itself from these accidental write cycles.

The state machine will be reset as standby mode automatically during power up. In addition, the control register

architecture of the device constrains that the memory contents can only be changed after speciﬁc command

sequences have completed successfully.

In the following, there are several features to protect the system from the accidental write cycles during VCC power-

up and power-down or from system noise.

• Valid command length checking: The command length will be checked whether it is at byte base and completed

on byte boundary.

• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before

other command to change data.

•

Deep Power Down Mode: By entering deep power down mode, the ﬂash device also is under protected from

writing all commands except Release from deep power down mode command (RDP) and Read Electronic

Signature command (RES), and softreset command.

Advanced Security Features: there are some protection and security features which protect content from

inadvertent write and hostile access.

Macronix Proprietary

P/N: PM2705

Rev. 0.00, February 26, 2019

8

ADVANCED INFORMATION

MX25U12843G

I. Block lock protection

- The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0 and T/B) bits to allow part of memory to

be protected as read only. The protected area deﬁnition is shown as "Table 2. Protected Area Sizes", the

protected areas are more ﬂexible which may protect various area by setting value of BP0-BP3 bits.

- The Hardware Protected Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and Status

Register Write Protect bit.

- In four I/O and QPI mode, the feature of HPM will be disabled.

Table 2. Protected Area Sizes

Protected Area Sizes (T/B bit = 0)

Status bit

Protect Level

128Mb

BP3

0

BP2

BP1

0

BP0

0

1

0

1

0 (none)

0

1

1 (1 block, protected block 255^th)

2 (2 blocks, block 254^th-255^th)

3 (4 blocks, block 252^nd-255^th)

4 (8 blocks, block 248^th-255^th)

5 (16 blocks, block 240^th-255^th)

6 (32 blocks, block 224^th-255^th)

7 (64 blocks, block 192^nd-255^th)

8 (128 blocks, block 128^th-255^th)

9 (256 blocks, protected all)

10 (256 blocks, protected all)

11 (256 blocks, protected all)

12 (256 blocks, protected all)

13 (256 blocks, protected all)

14 (256 blocks, protected all)

15 (256 blocks, protected all)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Protected Area Sizes (T/B bit = 1)

Status bit

Protect Level

128Mb

BP3

0

BP2

0

BP1

0

BP0

0

0 (none)

0

1

1 (1 block, protected block 0^th)

2 (2 blocks, protected block 0^th-1^st)

3 (4 blocks, protected block 0^th-3^rd)

4 (8 blocks, protected block 0^th-7^th)

0

1

0

1

0

1

0

1

0

1

5 (16 blocks, protected block 0^th-15^th)

6 (32 blocks, protected block 0^th-31^st)

7 (64 blocks, protected block 0^th-63^rd)

8 (128 blocks, protected block 0^th-127^th)

9 (256 blocks, protected all)

0

1

0

1

0

1

0

1

0

1

0

10 (256 blocks, protected all)

1

0

1

11 (256 blocks, protected all)

1

0

12 (256 blocks, protected all)

1

0

1

13 (256 blocks, protected all)

1

0

14 (256 blocks, protected all)

1

15 (256 blocks, protected all)

Macronix Proprietary

P/N: PM2705

Rev. 0.00, February 26, 2019

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ADVANCED INFORMATION

MX25U12843G

II. Additional 4K-bit secured OTP for unique identiﬁer: to provide 4K-bit one-time program area for setting

device unique serial number - Which may be set by factory or system customer.

- Security register bit 0 indicates whether the secured OTP area is locked by factory or not.

- To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with Enter Security OTP command),

and going through normal program procedure, and then exiting 4K-bit secured OTP mode by writing Exit

Security OTP command.

- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register)

command to set customer lock-down bit1 as "1". Please refer to "Table 12. Security Register Deﬁnition" for

security register bit deﬁnition and "Table 3. 4K-bit Secured OTP Deﬁnition" for address range deﬁnition.

- Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit secured

OTP mode, array access is not allowed.

Table 3. 4K-bit Secured OTP Deﬁnition

Address range

xxx000-xxx00F

xxx010-xxx1FF

Size

Standard Factory Lock

ESN (electrical serial number)

N/A

Customer Lock

128-bit

3968-bit

Determined by customer

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P/N: PM2705

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ADVANCED INFORMATION

MX25U12843G

7. Memory Organization

Table 4. Memory Organization

Block(64K-byte) Block(32K-byte)

Sector

4095

Address Range

FFF000h

FFFFFFh

511

individual 16 sectors

lock/unlock unit:4K-byte

4088

4087

FF8000h

FF7000h

FF8FFFh

FF7FFFh

255

510

509

508

507

506

4080

4079

FF0000h

FEF000h

FF0FFFh

FEFFFFh

4072

4071

FE8000h

FE7000h

FE8FFFh

FE7FFFh

254

individual block

lock/unlock unit:64K-byte

4064

4063

FE0000h

FDF000h

FE0FFFh

FDFFFFh

4056

4055

FD8000h

FD7000h

FD8FFFh

FD7FFFh

253

4048

FD0000h

FD0FFFh

individual block

lock/unlock unit:64K-byte

47

02F000h

02FFFFh

5

4

3

2

1

0

40

39

028000h

027000h

028FFFh

027FFFh

2

1

individual block

lock/unlock unit:64K-byte

32

31

020000h

01F000h

020FFFh

01FFFFh

24

23

018000h

017000h

018FFFh

017FFFh

16

15

010000h

00F000h

010FFFh

00FFFFh

individual 16 sectors

lock/unlock unit:4K-byte

8

7

008000h

007000h

008FFFh

007FFFh

0

000000h

000FFFh

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MX25U12843G

8. DEVICE OPERATION

1. Before a command is issued, status register should be checked to ensure device is ready for the intended

operation.

2. When incorrect command is inputted to this device, it enters standby mode and remains in standby mode until

next CS# falling edge. In standby mode, SO pin of this device should be High-Z.

3. When correct command is inputted to this device, it enters active mode and remains in active mode until next

CS# rising edge.

4. Input data is latched on the rising edge of Serial Clock (SCLK) and data is shifted out on the falling edge of

SCLK. The difference of Serial mode 0 and mode 3 is shown as "Figure 1. Serial Modes Supported".

5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, 2READ, DREAD, 4READ,

W4READ, QREAD, RDSFDP, RES, REMS, QPIID, RDBLOCK, RDCR, the shifted-in instruction sequence is

followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following

instructions: WREN, WRDI, WRSR, SE, BE32K, BE, CE, PP, 4PP, DP, ENSO, EXSO, WRSCUR, WPSEL,

SBLK, SBULK, GBLK, GBULK, SUSPEND, RESUME, NOP, RSTEN, RST, EQIO, RSTQIO the CS# must go

high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.

6. While a Write Status Register, Program or Erase operation is in progress, access to the memory array is

neglected and will not affect the current operation of Write Status Register, Program, Erase.

Figure 1. Serial Modes Supported

CPOL CPHA

shift in

shift out

SCLK

(Serial mode 0)

(Serial mode 3)

0

1

0

1

SI

MSB

SO

MSB

Note:

CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not

transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is

supported.

Macronix Proprietary

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ADVANCED INFORMATION

MX25U12843G

Figure 2. Serial Input Timing (STR mode)

tSHSL

tSHCH

tCHCL

CS#

tCHSL

tSLCH

tCHSH

SCLK

tDVCH

tCHDX

tCLCH

MSB

LSB

SI

High-Z

SO

Figure 3. Serial Input Timing (DTR mode)

tSHSL

CS#

tSLCH

tDVCH

tSHCH

tCHSL

tCLSH

SCLK

tCHCL

tCLDX

tDVCL

tCLCH

tCHDX

MSB

SIO[3:0]

LSB

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ADVANCED INFORMATION

MX25U12843G

Figure 4. Output Timing (STR mode)

CS#

tCH

SCLK

tCLQV

tCL

tSHQZ

tCLQX

LSB

SO

SI

ADDR.LSB IN

Figure 5. Output Timing (DTR mode)

CS#

tCH

SCLK

tCLQV

tCLQX

tCL

tSHQZ

tCLQX

SIO0

SIO1

SIO2

SIO3

tQVD

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ADVANCED INFORMATION

MX25U12843G

8-1. Quad Peripheral Interface (QPI) Read Mode

QPI protocol enables user to take full advantage of Quad I/O Serial NOR Flash by providing the Quad I/O interface

in command cycles, address cycles and as well as data output cycles.

Enable QPI mode

By issuing EQIO(35h) command, the QPI mode is enabled. After QPI mode is enabled, the device enters quad

mode (4-4-4) without QE bit status changed.

Figure 6. Enable QPI Sequence

CS#

MODE 3

MODE 0

2

3

4

5

6

7

0

1

SCLK

SIO0

35h

SIO[3:1]

Reset QPI (RSTQIO)

To reset the QPI mode, the RSTQIO (F5h) command is required. After the RSTQIO command is issued, the device

returns from QPI mode (4 I/O interface in command cycles) to SPI mode (1 I/O interface in command cycles).

Note:

For EQIO and RSTQIO commands, CS# high width has to follow "From Write/Erase/Program to Read Status

Register" speciﬁcation of tSHSL (as deﬁned by "Table 21. AC CHARACTERISTICS (Temperature = -40°C to 85°C,

VCC = 1.65V - 2.0V)") for next instruction.

Figure 7. Reset QPI Mode

CS#

SCLK

SIO[3:0]

F5h

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ADVANCED INFORMATION

MX25U12843G

9. COMMAND DESCRIPTION

Table 5. Command Set

Read/Write Array Commands

2READ

4READ

QREAD

Command

(byte)

READ

FAST READ

DREAD

(1I 2O read)

(2 x I/O read

(4 x I/O read

W4READ

(normal read) (fast read data)

(1I 4O read)

command)^{(Note 1)}

command)^{(Note 5)}

Mode

Address Bytes

1st byte

SPI

3

SPI/QPI

3

SPI

3

SPI

3

SPI/QPI

3

SPI/QPI

3

SPI

3

03 (hex)

ADD1

ADD2

ADD3

0B (hex)

ADD1

ADD2

ADD3

BB (hex)

ADD1

ADD2

ADD3

3B (hex)

ADD1

ADD2

ADD3

EB (hex)

ADD1

ADD2

ADD3

E7 (hex)

ADD1

ADD2

ADD3

6B (hex)

ADD1

ADD2

ADD3

2nd byte

3rd byte

4th byte

Dummy(8)/(4)

Dummy(10)/

(8)/(6)/(4)

5th byte

Dummy(8)/(4)

Dummy(8)

Dummy(4)

Dummy(8)

(Note 6)

Data Cycles

n bytes read

out until CS# out until CS# out by 2 x I/O

n bytes read

out by Dual

n bytes read

out by 4 x I/O read for with 4 out by Quad

Quad I/O

n bytes read

goes high

until CS# goes output until until CS# goes dummy cycles output until

Action

high

CS# goes high

high

CS# goes high

4PP

(quad page

program)

BE 32K

(block erase

32KB)

BE

Command

(byte)

4DTRD (Quad

I/O DT Read) (page program)

PP

SE

CE

(chip erase)

(block erase

64KB)

(sector erase)

Mode

Address Bytes

1st byte

SPI/QPI

3

SPI/QPI

3

SPI

3

SPI/QPI

3

SPI/QPI

3

SPI/QPI

3

SPI/QPI

0

ED (hex)

ADD1

ADD2

ADD3

02 (hex)

38 (hex)

ADD1

ADD2

ADD3

20 (hex)

ADD1

ADD2

ADD3

52 (hex)

ADD1

ADD2

ADD3

D8 (hex)

ADD1

ADD2

ADD3

60 or C7 (hex)

2nd byte

3rd byte

4th byte

Dummy(10)/

(8)/(6)

5th byte

1-256

Data Cycles

n bytes read to program the quad input to

out (Double selected page program the selected sector selected 32K selected block

to erase the

to erase the to erase whole

chip

Transfer Rate)

by 4xI/O until

CS# goes high

selected page

block

Action

* Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in conﬁguration register.

Macronix Proprietary

P/N: PM2705

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16

ADVANCED INFORMATION

MX25U12843G

Register/Setting Commands

RDCR

(read

WRSR

(write status/

FMEN

RDSR

WPSEL

(Write Protect

Selection)

Command

(byte)

WREN

WRDI

(factory mode (read status

(write enable) (write disable)

conﬁguration conﬁguration

enable)

register)

SPI/QPI

15 (hex)

register)

SPI/QPI

01 (hex)

Values

Mode

1st byte

SPI/QPI

06 (hex)

SPI/QPI

04 (hex)

SPI/QPI

41 (hex)

SPI/QPI

05 (hex)

SPI/QPI

68 (hex)

2nd byte

3rd byte

4th byte

Values

5th byte

Data Cycles

1-2

sets the (WEL)

write enable

latch bit

resets the

(WEL) write

enable latch bit

enable factory to read out the to read out the to write new

to enter and

mode

values of the values of the values of the enable individal

status register conﬁguration

status/

conﬁguration

register

block protect

mode

Action

register

PGM/ERS

Suspend

(Suspends

Program/

Erase)

PGM/ERS

Resume

RDP (Release

from deep

power down)

SBL

(Set Burst

Length)

Command

(byte)

EQIO

(Enable QPI)

RSTQIO

(Reset QPI)

DP (Deep

(Resumes

power down)

Program/

Erase)

Mode

1st byte

SPI

QPI

SPI/QPI

B9 (hex)

SPI/QPI

AB (hex)

SPI/QPI

C0 (hex)

35 (hex)

F5 (hex)

75 or B0 (hex) 7A or 30 (hex)

2nd byte

3rd byte

4th byte

5th byte

Data Cycles

Entering the Exiting the QPI

QPI mode mode

enters deep

power down

mode

release from

deep power

down mode

to set Burst

length

Action

Macronix Proprietary

P/N: PM2705

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ADVANCED INFORMATION

MX25U12843G

ID/Security Commands

REMS

(read electronic

manufacturer (QPI ID Read)

& device ID)

RDID

(read identiﬁc-

RES

(read

electronic ID)

ENSO

EXSO

Command

(byte)

QPIID

RDSFDP

(enter secured (exit secured

ation)

OTP)

Mode

Address Bytes

1st byte

SPI

0

SPI/QPI

0

SPI

0

QPI

0

SPI/QPI

3

SPI/QPI

0

SPI/QPI

0

9F (hex)

AB (hex)

90 (hex)

AF (hex)

5A (hex)

B1 (hex)

C1 (hex)

2nd byte

3rd byte

x

ADD1

ADD2

4th byte

ADD1

ADD3

Dummy(8)^{(Note 5)}

5th byte

Data Cycles

outputs JEDEC to read out

output the

ID in QPI

interface

Read SFDP

mode

to enter the

4K-bit secured 4K-bit secured

OTP mode

to exit the

ID: 1-byte

Manufacturer

ID & 2-byte

Device ID

1-byte Device Manufacturer

ID

ID & Device

OTP mode

Action

ID^{(Note 2)}

RDSCUR

WRSCUR

SBLK

SBULK

(single block (block protect

unlock)

SPI/QPI

3

RDBLOCK

GBLK

(gang block

lock)

GBULK

(gang block

unlock)

Command

(byte)

(read security (write security (single block

register)

SPI/QPI

0

register)

SPI/QPI

0

lock

SPI/QPI

3

read)

SPI/QPI

3

Mode

Address Bytes

1st byte

SPI/QPI

0

36 (hex)

39 (hex)

3C (hex)

2B (hex)

2F (hex)

7E (hex)

98 (hex)

ADD1

ADD2

ADD3

ADD1

ADD2

ADD3

ADD1

ADD2

ADD3

2nd byte

3rd byte

4th byte

5th byte

Data Cycles

to read value to set the lock- individual block individual block read individual

whole chip

unprotect

of security

register

down bit as

"1" (once lock-

(64K-byte)

or sector

(64K-byte)

or sector

(4K-byte)

unprotect

block or sector write protect

write protect

Action

down, cannot (4K-byte) write

be updated) protect

status

Macronix Proprietary

P/N: PM2705

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18

ADVANCED INFORMATION

MX25U12843G

Reset Commands

Command

NOP

RSTEN

RST

(byte)

(No Operation) (Reset Enable) (Reset Memory)

Mode

SPI/QPI

00 (hex)

SPI/QPI

66 (hex)^{(Note 4)}

SPI/QPI

99 (hex)

1st byte

2nd byte

3rd byte

4th byte

5th byte

Action

Note 1: The count base is 4-bit for ADD(2) and Dummy(2) because of 2 x I/O. And the MSB is on SO/SIO1 which is different

from 1 x I/O condition.

Note 2: ADD=00H will output the manufacturer ID ﬁrst and ADD=01H will output device ID ﬁrst.

Note 3: It is not recommended to adopt any other code not in the command deﬁnition table, which will potentially enter the hid-

den mode.

Note 4: The RSTEN command must be executed before executing the RST command. If any other command is issued in-be-

tween RSTEN and RST, the RST command will be ignored.

Note 5: The number in parentheses after "Dummy" stands for how many clock cycles it has. Dummy cycle number will be

different, depending on the bit7 (DC) setting of Conﬁguration Register. Please refer to "Table 8. Conﬁguration Register".

Note 6: The fast read command (0Bh) when under QPI mode, the dummy cycle is 4 clocks.

Macronix Proprietary

P/N: PM2705

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19

ADVANCED INFORMATION

MX25U12843G

9-1. Write Enable (WREN)

The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP,

SE, BE32K, BE, CE, and WRSR, which are intended to change the device content WEL bit should be set every time

after the WREN instruction setting the WEL bit.

The sequence of issuing WREN instruction is: CS# goes low→sending WREN instruction code→ CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care in

SPI mode.

Figure 8. Write Enable (WREN) Sequence (SPI Mode)

CS#

0

1

2

3

4

5

6

7

Mode 3

Mode 0

SCLK

Command

06h

SI

High-Z

SO

Figure 9. Write Enable (WREN) Sequence (QPI Mode)

CS#

0

1

Mode 3

SCLK

Mode 0

Command

SIO[3:0]

06h

Macronix Proprietary

P/N: PM2705

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ADVANCED INFORMATION

MX25U12843G

9-2. Write Disable (WRDI)

The Write Disable (WRDI) instruction is to reset Write Enable Latch (WEL) bit.

The sequence of issuing WRDI instruction is: CS# goes low→sending WRDI instruction code→CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care in

SPI mode.

The WEL bit is reset by following situations:

- Power-up

- Reset# pin driven low

- WRDI command completion

- WRSR command completion

- PP command completion

- 4PP command completion

- SE command completion

- BE32K command completion

- BE command completion

- CE command completion

- PGM/ERS Suspend command completion

- Softreset command completion

- WRSCUR command completion

- WPSEL command completion

- GBLK command completion

- GBULK command completion

Figure 10. Write Disable (WRDI) Sequence (SPI Mode)

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

SCLK

Command

04h

SI

High-Z

SO

Macronix Proprietary

P/N: PM2705

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ADVANCED INFORMATION

MX25U12843G

Figure 11. Write Disable (WRDI) Sequence (QPI Mode)

CS#

0

1

Mode 3

SCLK

Mode 0

Command

SIO[3:0]

04h

9-3. Factory Mode Enable (FMEN)

The Factory Mode Enable (FMEN) instruction is for enhance Program and Erase performance for increase factory

production throughput. The FMEN instruction need to combine with the instructions which are intended to change

the device content, like PP, 4PP, SE, BE32K, BE, and CE.

The sequence of issuing FMEN instruction is: CS# goes low→sending FMEN instruction code→ CS# goes high. A

valid factory mode operation need to included three sequences: WREN instruction → FMEN instruction→ Program

or Erase instruction.

Suspend command is not acceptable under factory mode.

The FMEN is reset by following situations

- Power-up

- Reset# pin driven low

- PP command completion

- 4PP command completion

- SE command completion

- BE32K command completion

- BE command completion

- CE command completion

- Softreset command completion

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care in

SPI mode.

Figure 12. Factory Mode Enable (FMEN) Sequence (SPI Mode)

CS#

0

1

2

3

4

5

6

7

Mode 3

Mode 0

SCLK

Command

41h

SI

High-Z

SO

Macronix Proprietary

P/N: PM2705

Rev. 0.00, February 26, 2019

22

ADVANCED INFORMATION

MX25U12843G

Figure 14. Factory Mode Enable (FMEN) Sequence (QPI Mode)

CS#

0

1

Mode 3

Mode 0

SCLK

Command

SIO[3:0]

41h

9-4. Read Identiﬁcation (RDID)

The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Macronix

Manufacturer ID and Device ID are listed as "Table 6. ID Deﬁnitions".

The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code→24-bits ID data out

on SO→ to end RDID operation can drive CS# to high at any time during data out.

While Program/Erase operation is in progress, it will not decode the RDID instruction, therefore there's no effect on

the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby

stage.

Figure 13. Read Identiﬁcation (RDID) Sequence (SPI mode only)

CS#

0

1

2

3

4

5

6

7

8

9

10

13 14 15 16 17 18

28 29 30 31

Mode 3

Mode 0

SCLK

SI

Command

9Fh

Manufacturer Identification

Device Identification

High-Z

SO

7

6

5

2

1

0

15 14 13

MSB

3

2

1

0

MSB

Macronix Proprietary

P/N: PM2705

Rev. 0.00, February 26, 2019

23

ADVANCED INFORMATION

MX25U12843G

9-5. Release from Deep Power-down (RDP), Read Electronic Signature (RES)

The Release from Deep Power-down (RDP) instruction is completed by driving Chip Select (CS#) High. When Chip

Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the

Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously

in the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES1, and

Chip Select (CS#) must remain High for at least tRES1(max), as speciﬁed in "Table 21. AC CHARACTERISTICS

(Temperature = -40°C to 85°C, VCC = 1.65V - 2.0V)". Once in the Stand-by Power mode, the device waits to be

selected, so that it can receive, decode and execute instructions. The RDP instruction is only for releasing from

Deep Power Down Mode. Reset# pin goes low will release the Flash from deep power down mode.

RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as "Table 6.

ID Deﬁnitions". This is not the same as RDID instruction. It is not recommended to use for new design. For new

design, please use RDID instruction.

Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in

progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly

if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in

Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in Deep

Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least

tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute

instruction.

Figure 15. Read Electronic Signature (RES) Sequence (SPI Mode)

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38

SCLK

Command

ABh

t

3 Dummy Bytes

RES2

SI

23 22 21

MSB

3

2

1

0

Electronic Signature Out

High-Z

7

6

5

4

3

2

0

1

SO

MSB

Deep Power-down Mode

Stand-by Mode

Macronix Proprietary

P/N: PM2705

Rev. 0.00, February 26, 2019

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ADVANCED INFORMATION

MX25U12843G

Figure 16. Read Electronic Signature (RES) Sequence (QPI Mode)

CS#

MODE 3

0

1

2

3

4

5

6

7

SCLK

MODE 0

3 Dummy Bytes

Command

ABh

SIO[3:0]

X

H0 L0

MSB LSB

Data Out

Data In

Stand-by Mode

Deep Power-down Mode

Figure 17. Release from Deep Power-down (RDP) Sequence (SPI Mode)

CS#

t

RES1

0

1

2

3

4

5

6

7

Mode 3

Mode 0

SCLK

SI

Command

ABh

High-Z

SO

Deep Power-down Mode

Stand-by Mode

Figure 18. Release from Deep Power-down (RDP) Sequence (QPI Mode)

CS#

t

RES1

Mode 3

Mode 0

0

1

SCLK

Command

SIO[3:0]

ABh

Deep Power-down Mode

Stand-by Mode

Macronix Proprietary

P/N: PM2705

Rev. 0.00, February 26, 2019

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ADVANCED INFORMATION

MX25U12843G

9-6. Read Electronic Manufacturer ID & Device ID (REMS)

The REMS instruction returns both the JEDEC assigned manufacturer ID and the device ID. The Device ID values

are listed in "Table 6. ID Deﬁnitions".

The REMS instruction is initiated by driving the CS# pin low and sending the instruction code "90h" followed by two

dummy bytes and one address byte (A7-A0). After which the manufacturer ID for Macronix (C2h) and the device ID

are shifted out on the falling edge of SCLK with the most signiﬁcant bit (MSB) ﬁrst. If the address byte is 00h, the

manufacturer ID will be output ﬁrst, followed by the device ID. If the address byte is 01h, then the device ID will be

output ﬁrst, followed by the manufacturer ID. While CS# is low, the manufacturer and device IDs can be read

continuously, alternating from one to the other. The instruction is completed by driving CS# high.

Figure 19. Read Electronic Manufacturer & Device ID (REMS) Sequence (SPI Mode only)

CS#

0

1

2

3

4

5

6

7

8

9 10

Mode 3

Mode 0

SCLK

Command

90h

2 Dummy Bytes

SI

15 14 13

3

2

1

0

High-Z

SO

CS#

47

28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

SCLK

ADD (1)

7

6

5

4

3

2

0

1

SI

Manufacturer ID

Device ID

7

6

5

4

3

2

1

0

7

6

5

4

3

2

0

1

SO

MSB

Notes: (1) ADD=00H will output the manufacturer's ID ﬁrst and ADD=01H will output device ID ﬁrst.

Macronix Proprietary

P/N: PM2705

Rev. 0.00, February 26, 2019

26

ADVANCED INFORMATION

MX25U12843G

9-7. QPI ID Read (QPIID)

User can execute this QPIID Read instruction to identify the Device ID and Manufacturer ID. The sequence of issue

QPIID instruction is CS# goes low→sending QPI ID instruction→Data out on SO→CS# goes high. Most signiﬁcant

bit (MSB) ﬁrst.

After the command cycle, the device will immediately output data on the falling edge of SCLK. The manufacturer ID,

memory type, and device ID data byte will be output continuously, until the CS# goes high.

Table 6. ID Deﬁnitions

Command Type

MX25U12843G

Manufacturer ID

C2

Memory Type

Memory Density

38

RDID

RES

9Fh

25

Electronic ID

38

Device ID

38

ABh

90h

AFh

Manufacturer ID

REMS

QPIID

C2

Manufacturer ID

C2

Memory Type

25

Memory Density

38

Macronix Proprietary

P/N: PM2705

Rev. 0.00, February 26, 2019

27

ADVANCED INFORMATION

MX25U12843G

9-8. Read Status Register (RDSR)

The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even

in program/erase/write status register condition). It is recommended to check the Write in Progress (WIP) bit before

sending a new instruction when a program, erase, or write status register operation is in progress.

The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register data

out on SO.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

Figure 20. Read Status Register (RDSR) Sequence (SPI Mode)

CS#

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

Mode 3

Mode 0

SCLK

SI

command

05h

Status Register Out

High-Z

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

MSB

Figure 21. Read Status Register (RDSR) Sequence (QPI Mode)

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

N

SCLK

SIO[3:0]

05h

H0 L0 H0 L0 H0 L0

H0 L0

MSB

LSB

Status Byte Status Byte Status Byte

Status Byte

Macronix Proprietary

P/N: PM2705

Rev. 0.00, February 26, 2019

28

ADVANCED INFORMATION

MX25U12843G

9-9. Read Conﬁguration Register (RDCR)

The RDCR instruction is for reading Conﬁguration Register Bits. The Read Conﬁguration Register can be read at

any time (even in program/erase/write conﬁguration register condition). It is recommended to check the Write in

Progress (WIP) bit before sending a new instruction when a program, erase, or write conﬁguration register operation

is in progress.

The sequence of issuing RDCR instruction is: CS# goes low→ sending RDCR instruction code→ Conﬁguration

Register data out on SO.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

Figure 22. Read Conﬁguration Register (RDCR) Sequence (SPI Mode)

CS#

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

Mode 3

Mode 0

SCLK

SI

command

15h

Configuration register Out

High-Z

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

MSB

Figure 23. Read Conﬁguration Register (RDCR) Sequence (QPI Mode)

CS#

Mode 3

Mode 0

N

0

1

2

3

4

5

6

7

SCLK

SIO[3:0]

15h

H0 L0 H0 L0 H0 L0

H0 L0

MSB

LSB

Config. Byte Config. Byte Config. Byte

Config. Byte

Macronix Proprietary

P/N: PM2705

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ADVANCED INFORMATION

MX25U12843G

For user to check if Program/Erase operation is ﬁnished or not, RDSR instruction ﬂow are shown as follows:

Figure 24. Program/Erase ﬂow with read array data

start

WREN command

RDSR command*

No

WEL=1?

Yes

Program/erase command

Write program data/address

(Write erase address)

RDSR command

No

WIP=0?

Yes

RDSR command

Read WEL=0, BP[3:0], QE,

and SRWD data

Read array data

(same address of PGM/ERS)

No

Verify OK?

Yes

Program/erase successfully

Program/erase fail

Yes

Program/erase

another block?

* Issue RDSR to check BP[3:0].

* If WPSEL = 1, issue RDBLOCK to check the block status.

No

Program/erase completed

Macronix Proprietary

P/N: PM2705

Rev. 0.00, February 26, 2019

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ADVANCED INFORMATION

MX25U12843G

Figure 25. Program/Erase ﬂow without read array data (read P_FAIL/E_FAIL ﬂag)

start

WREN command

RDSR command*

No

WEL=1?

Yes

Program/erase command

Write program data/address

(Write erase address)

RDSR command

No

WIP=0?

Yes

RDSR command

Read WEL=0, BP[3:0], QE,

and SRWD data

RDSCUR command

P_FAIL/E_FAIL =1 ?

Yes

No

Program/erase successfully

Program/erase fail

Yes

Program/erase

another block?

* Issue RDSR to check BP[3:0].

* If WPSEL = 1, issue RDBLOCK to check the block status.

No

Program/erase completed

Macronix Proprietary

P/N: PM2705

Rev. 0.00, February 26, 2019

31

ADVANCED INFORMATION

MX25U12843G

Status Register

The deﬁnition of the status register bits is as below:

WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write

status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status

register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status

register cycle.

WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable

latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/

erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the

device will not accept program/erase/write status register instruction. The program/erase command will be ignored

if it is applied to a protected memory area. To ensure both WIP bit & WEL bit are both set to 0 and available for next

program/erase/operations, WIP bit needs to be conﬁrm to be 0 before polling WEL bit. After WIP bit conﬁrmed, WEL

bit needs to be conﬁrm to be 0.

BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area

(as deﬁned in "Table 2. Protected Area Sizes") of the device to against the program/erase instruction without hardware

protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR)

instruction to be executed. Those bits deﬁne the protected area of the memory to against Page Program (PP), Sector

Erase (SE), Block Erase 32KB (BE32K), Block Erase (BE) and Chip Erase (CE) instructions (only if Block Protect bits

(BP3:BP0) set to 0, the CE instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default. Which is un-

protected.

QE bit. The Quad Enable (QE) bit is a non-volatile bit with a factory default of “0”. When QE is “0”, Quad mode

commands are ignored; pins WP#/SIO2 and the RESET#/SIO3 of 8-pin package function as WP# and RESET#,

respectively. When QE is “1”, Quad mode is enabled and Quad mode commands are supported along with Single

and Dual mode commands. Pins WP#/SIO2 and the RESET#/SIO3 of 8-pin package function as SIO2 and SIO3,

respectively, and their alternate pin functions are disabled. Enabling Quad mode also disables the HPM feature and

the RESET feature of 8-pin package.

SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection

(WP#/SIO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and

WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is

no longer accepted for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only. The

SRWD bit defaults to be "0".

Table 7. Status Register

bit7

bit6

bit5

BP3

(level of

protected

block)

bit4

BP2

(level of

protected

block)

bit3

BP1

(level of

protected

block)

bit2

BP0

(level of

protected

block)

bit1

bit0

SRWD (status

register write

protect)

QE

(Quad

Enable)

WEL

(write enable

latch)

WIP

(write in

progress bit)

1=status

register write

disabled

0=status

register write

enabled

1=Quad

Enabled

0=not Quad

Enabled

1=write

enable

0=not write 0=not in write

1=write

operation

(note 1)

enable

operation

Non-volatile Non-volatile Non-volatile Non-volatile Non-volatile Non-volatile

bit bit bit bit bit bit

Note 1: Please refer to "Table 2. Protected Area Sizes".

volatile bit

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MX25U12843G

Conﬁguration Register

The Conﬁguration Register is able to change the default status of Flash memory. Flash memory will be conﬁgured

after the CR bit is set.

ODS bit

The output driver strength (ODS2, ODS1, ODS0) bits are volatile bits, which indicate the output driver level (as

deﬁned in "Table 9. Output Driver Strength Table") of the device. The Output Driver Strength is defaulted as 30

Ohms when delivered from factory. To write the ODS bits requires the Write Status Register (WRSR) instruction to

be executed.

TB bit

The Top/Bottom (TB) bit is a non-volatile OTP bit. The Top/Bottom (TB) bit is used to conﬁgure the Block Protect

area by BP bit (BP3, BP2, BP1, BP0), starting from TOP or Bottom of the memory array. The TB bit is defaulted as

“0”, which means Top area protect. When it is set as “1”, the protect area will change to Bottom area of the memory

device. To write the TB bits requires the Write Status Register (WRSR) instruction to be executed.

PBE bit

The Preamble Bit Enable (PBE) bit is a volatile bit. It is used to enable or disable the preamble bit data pattern

output on dummy cycles. The PBE bit is defaulted as “0”, which means preamble bit is disabled. When it is set as “1”,

the preamble bit will be enabled, and inputted into dummy cycles. To write the PBE bits requires the Write Status

Register (WRSR) instruction to be executed.

Table 8. Conﬁguration Register

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

DC1

DC0

PBE

TB

ODS 2

ODS 1

ODS 0

(Dummy

cycle 1)

(Dummy

cycle 0)

Reserved (Preamble bit (top/bottom (output driver (output driver (output driver

Enable)

selected)

strength)

0=Top area

protect

0=Disabled

(Note 2)

(Note 1)

x

1=Bottom

1=Enabled area protect

(Default=0)

volatile bit

OTP

volatile bit

Note 1: Please refer to "Table 9. Output Driver Strength Table"

Note 2: Please refer to "Table 10. Dummy Cycle and Frequency Table (MHz)"

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Table 9. Output Driver Strength Table

ODS2

ODS1

ODS0

Resistance (Ohm)

Reserved

Note

0

1

0

1

0

1

0

1

0

1

0

1

0

1

90 Ohms

45 Ohms

Reserved

Impedance at VCC/2

15 Ohms

30 Ohms (Default)

Table 10. Dummy Cycle and Frequency Table (MHz)

(STR Mode)

Numbers of Dummy

Dual Output Fast

Quad Output Fast

Read

DC[1:0]

Fast Read

clock cycles

Read

Don't care

00 (default)

8

133

114

Numbers of Dummy

DC[1:0]

Dual IO Fast Read

clock cycles

00 (default)

4

8

4

8

84

114

84

01

10

11

114

Numbers of Dummy

clock cycles

DC[1:0]

FAST READ(QPI)

Don't care

00 (default)

4

66

Numbers of Dummy

Quad IO Fast Read

DC[1:0]

Quad IO Fast Read

clock cycles

(QPI)

00 (default)

6

4

8

84

66

104

120

84

66

104

120

01

10

11

10

(DTR Mode)

Numbers of Dummy

DC[1:0]

Quad IO DTR Read

clock cycles

00 (default)

6

8

54

66

84

01

10

11

10

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9-10. Write Status Register (WRSR)

The WRSR instruction is for changing the values of Status Register Bits and Conﬁguration Register Bits. Before

sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write

Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2,

BP1, BP0) bits to deﬁne the protected area of memory (as shown in "Table 2. Protected Area Sizes"). The WRSR

also can set or reset the Quad enable (QE) bit and set or reset the Status Register Write Disable (SRWD) bit in

accordance with Write Protection (WP#/SIO2) pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of the status

register. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered.

The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register

data on SI→CS# goes high.

The CS# must go high exactly at the 8 bits or 16 bits data boundary; otherwise, the instruction will be rejected and

not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes

high. The Write in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress.

The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write

Enable Latch (WEL) bit is reset.

Figure 26. Write Status Register (WRSR) Sequence (SPI Mode)

CS#

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Mode 3

Mode 0

SCLK

command

01h

Status

Register In

Configuration

Register In

SI

4

15 14

13

12 11

10 9

8

2

1

0

7

6

5

3

MSB

High-Z

SO

Note: The CS# must go high exactly at 8 bits or 16 bits data boundary to completed the write register command.

Figure 27. Write Status Register (WRSR) Sequence (QPI Mode)

CS#

Mode 3

Mode 0

Mode 3

Mode 0

0

1

2

3

4

5

SCLK

CR in

SR in

Command

01h

H0 L0 H1 L1

SIO[3:0]

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Software Protected Mode (SPM):

-

When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can

change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is deﬁned by BP3, BP2, BP1,

BP0 and T/B bit, is at software protected mode (SPM).

-

When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values

of SRWD, BP3, BP2, BP1, BP0. The protected area, which is deﬁned by BP3, BP2, BP1, BP0 and T/B bit, is at

software protected mode (SPM)

Note:

If SRWD bit=1 but WP#/SIO2 is low, it is impossible to write the Status Register even if the WEL bit has previously

been set. It is rejected to write the Status Register and not be executed.

Hardware Protected Mode (HPM):

-

When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware

protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2,

BP1, BP0 and T/B bit and hardware protected mode by the WP#/SIO2 to against data modiﬁcation.

Note:

To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered.

If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be entered; only

can use software protected mode via BP3, BP2, BP1, BP0 and T/B bit.

If the system enter QPI or set QE=1, the feature of HPM will be disabled.

Table 11. Protection Modes

Mode

Status register condition

WP# and SRWD bit status

Memory

Status register can be written

in (WEL bit is set to "1") and

the SRWD, BP0-BP3

Software protection

mode (SPM)

WP#=1 and SRWD bit=0, or

WP#=0 and SRWD bit=0, or

WP#=1 and SRWD=1

The protected area

cannot

be program or erase.

bits can be changed

The SRWD, BP0-BP3 of

status register bits cannot be

changed

The protected area

cannot

be program or erase.

Hardware protection

mode (HPM)

WP#=0, SRWD bit=1

Note:

1. As deﬁned by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in

"Table 2. Protected Area Sizes".

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Figure 28. WRSR ﬂow

start

WREN command

RDSR command

No

WEL=1?

Yes

WRSR command

Write status register data

RDSR command

No

WIP=0?

Yes

RDSR command

Read WEL=0, BP[3:0], QE,

and SRWD data

No

Verify OK?

Yes

WRSR successfully

WRSR fail

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Figure 29. WP# Setup Timing and Hold Timing during WRSR when SRWD=1

WP#

CS#

tSHWL

tWHSL

0

1

2

3

4

5

6

7

8

9

10 11 12

13 14

15

SCLK

01h

SI

High-Z

SO

Note: WP# must be kept high until the embedded operation ﬁnish.

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9-11. Read Data Bytes (READ)

The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on

the falling edge of SCLK at a maximum frequency fR. The ﬁrst address byte can be at any location. The address

is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can

be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been

reached.

The sequence of issuing READ instruction is: CS# goes low→sending READ instruction code→ 3-byte address on

SI→ data out on SO→to end READ operation can use CS# to high at any time during data out.

Figure 30. Read Data Bytes (READ) Sequence (SPI Mode only)

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38 39

SCLK

command

03h

24-Bit Address

23 22 21

MSB

3

2

1

0

SI

Data Out 1

Data Out 2

High-Z

2

7

6

5

4

3

1

7

0

SO

MSB

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9-12. Read Data Bytes at Higher Speed (FAST_READ)

The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and

data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The ﬁrst address byte can be at

any location. The address is automatically increased to the next higher address after each byte data is shifted out,

so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when

the highest address has been reached.

Read on SPI Mode The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ

instruction code→ 3-byte address on SI→ 8 dummy cycles → data out on SO→ to end FAST_READ operation can

use CS# to high at any time during data out.

Read on QPI Mode The sequence of issuing FAST_READ instruction in QPI mode is: CS# goes low→ sending

FAST_READ instruction, 2 cycles→ 24-bit address interleave on SIO3, SIO2, SIO1 & SIO0→4 dummy cycles

→data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end QPI FAST_READ operation can use CS# to high at any

time during data out.

While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any

impact on the Program/Erase/Write Status Register current cycle.

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Figure 31. Read at Higher Speed (FAST_READ) Sequence (SPI Mode)

CS#

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31

Mode 3

Mode 0

SCLK

Command

0Bh

24-Bit Address

SI

23 22 21

3

2

1

0

High-Z

SO

CS#

47

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

SCLK

8 Dummy

Cycles

7

6

5

4

3

2

0

1

SI

DATA OUT 2

DATA OUT 1

7

6

5

4

3

2

1

0

7

6

5

4

3

2

0

1

SO

MSB

Figure 32. Read at Higher Speed (FAST_READ) Sequence (QPI Mode)

CS#

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Mode 3

Mode 0

SCLK

Command

0Bh

SIO(3:0)

X

H0 L0 H1 L1

MSB LSB MSB LSB

Data Out 1 Data Out 2

A5 A4 A3 A2 A1 A0

24-Bit Address

X

4 Dummy

Cycles

Data In

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9-13. Dual Output Read Mode (DREAD)

The DREAD instruction enable double throughput of Serial NOR Flash in read mode. The address is latched on

rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a

maximum frequency fT. The ﬁrst address byte can be at any location. The address is automatically increased to the

next higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD

instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD

instruction, the following data out will perform as 2-bit instead of previous 1-bit.

The sequence of issuing DREAD instruction is: CS# goes low

sending DREAD instruction 3-byte address on

→

SIO0 8 dummy cycles on SIO0

data out interleave on SIO1 & SIO0

to end DREAD operation can use CS#

→

to high at any time during data out.

While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact

on the Program/Erase/Write Status Register current cycle.

Figure 33. Dual Read Mode Sequence

CS#

30 31 32

39 40 41 42 43 44 45

0

1

2

3

4

5

6

7

8

9

SCLK

…

24 ADD Cycle

…

8 Dummy

Cycles

Data Out

1

Command

2

…

A23 A22

A1 A0

D4 D2

D6 D4

D7 D5

3B

D6

D7

D0

SI/SIO0

High Impedance

D1

D5 D3

SO/SIO1

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9-14. 2 x I/O Read Mode (2READ)

The 2READ instruction enable double throughput of Serial NOR Flash in read mode. The address is latched on

rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a

maximum frequency fT. The ﬁrst address byte can be at any location. The address is automatically increased to the

next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ

instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ

instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit.

The sequence of issuing 2READ instruction is: CS# goes low sending 2READ instruction 3-byte address

→

interleave on SIO1 & SIO0 4 dummy cycles (default) on SIO1 & SIO0 data out interleave on SIO1 & SIO0 to

→

end 2READ operation can use CS# to high at any time during data out.

While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact

on the Program/Erase/Write Status Register current cycle.

Figure 34. 2 x I/O Read Mode Sequence (SPI Mode only)

CS#

Mode 3

Mode 0

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

10

17 18 19 20 21 22 23 24 25 26 27 28 29 30

SCLK

Data

Configurable

Dummy Cycle

12 ADD Cycles

Command

Out 1

Out 2

D6 D4 D2 D0 D6 D4 D2 D0

A22 A20 A18

A23 A21 A19

A4 A2 A0

BBh

SI/SIO0

D7 D5 D3 D1 D7 D5 D3 D1

A5 A3 A1

SO/SIO1

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9-15. Quad Read Mode (QREAD)

The QREAD instruction enable quad throughput of Serial NOR Flash in read mode. A Quad Enable (QE) bit of

status Register must be set to "1" before sending the QREAD instruction. The address is latched on rising edge

of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum

frequency fQ. The ﬁrst address byte can be at any location. The address is automatically increased to the next

higher address after each byte data is shifted out, so the whole memory can be read out at a single QREAD

instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing QREAD

instruction, the following data out will perform as 4-bit instead of previous 1-bit.

The sequence of issuing QREAD instruction is: CS# goes low

sending QREAD instruction → 3-byte address on

→

SI

8 dummy cycles

data out interleave on SIO3, SIO2, SIO1 & SIO0

to end QREAD operation can use

→

CS# to high at any time during data out.

While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any impact

on the Program/Erase/Write Status Register current cycle.

Figure 35. Quad Read Mode Sequence

CS#

29 30 31 32 33

38 39 40 41 42

0

1

2

3

4

5

6

7

8

9

SCLK

…

Data

Out 1

Data Data

Out 2 Out 3

8 dummy cycles

Command

6B

24 ADD Cycles

…

A23A22

A2 A1 A0

D4 D0 D4 D0 D4

SIO0

SIO1

SIO2

SIO3

High Impedance

D5 D1 D5 D1 D5

D6 D2 D6 D2 D6

D7 D3 D7 D3 D7

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9-16. 4 x I/O Read Mode (4READ)

The 4READ instruction enable quad throughput of Serial NOR Flash in read mode. A Quad Enable (QE) bit of status

Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCLK,

and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency

fQ. The ﬁrst address byte can be at any location. The address is automatically increased to the next higher address

after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address

counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following

address/dummy/data out will perform as 4-bit instead of previous 1-bit.

4 x I/O Read on SPI Mode (4READ) The sequence of issuing 4READ instruction is: CS# goes low sending

→

4READ instruction 3-byte address interleave on SIO3, SIO2, SIO1 & SIO0 6 dummy cycles (Default) data out

→

interleave on SIO3, SIO2, SIO1 & SIO0 to end 4READ operation can use CS# to high at any time during data out.

→

Figure 36. 4 x I/O Read Mode Sequence (SPI Mode)

CS#

23 24

10 11 12 13 14 15 16 17 18 19 20 21 22

Mode 3

Mode 0

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

SCLK

Data

6 ADD Cycles

Command

Performance

enhance

Out 1

Out 2 Out 3

indicator (Note 1 & 2)

Configurable

Dummy Cycle (Note 3)

A20 A16 A12 A8 A4 A0

D4 D0 D4 D0 D4 D0

P4 P0

EBh

SIO0

SIO1

SIO2

SIO3

A21 A17 A13 A9 A5 A1

A22 A18 A14 A10 A6 A2

D5 D1 D5 D1 D5 D1

D6 D2 D6 D2 D6 D2

P5 P1

P6 P2

A23 A19 A15 A11 A7 A3

D7 D3 D7 D3 D7 D3

P7 P3

Notes:

1. Hi-impedance is inhibited for the two clock cycles.

2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited.

3. Conﬁguration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in

conﬁguration register.

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4 x I/O Read on QPI Mode (4READ) The 4READ instruction also support on QPI command mode. The sequence

of issuing 4READ instruction QPI mode is: CS# goes low sending 4READ instruction 3-byte address interleave

→

on SIO3, SIO2, SIO1 & SIO0 6 dummy cycles (Default) data out interleave on SIO3, SIO2, SIO1 & SIO0 to

→

end 4READ operation can use CS# to high at any time during data out.

While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact

on the Program/Erase/Write Status Register current cycle.

Figure 37. 4 x I/O Read Mode Sequence (QPI Mode)

CS#

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

MODE 3

MODE 0

MODE 3

MODE 0

SCLK

EB

SIO[3:0]

H0 L0 H1 L1 H2 L2 H3 L3

A5 A4 A3 A2 A1 A0

24-bit Address

X

MSB

Data Out

Configurable

Dummy Cycle

Data In

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W4READ instruction (E7h) is also available for 4 I/O read. Please refer to "Figure 38. W4READ (Quad Read with 4

dummy cycles) Sequence (SPI Mode)" and .

W4READ on SPI Mode

The sequence of issuing W4READ instruction is: CS# goes low→ send W4READ instruction→ 3-byte address

interleave on SIO3, SIO2, SIO1 & SIO0→ 4 dummy cycles →data out interleave on SIO3, SIO2, SIO1 & SIO0→ to

end W4READ operation, pull CS# high at any time during data out.

W4READ on QPI Mode

The W4READ instruction also supports QPI command mode. The sequence of issuing W4READ instruction QPI

mode is: CS# goes low→ send W4READ instruction→ 3-byte address interleave on SIO3, SIO2, SIO1 & SIO0→

4 dummy cycles →data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end W4READ operation, pull CS# high at

any time during data out.

Figure 38. W4READ (Quad Read with 4 dummy cycles) Sequence (SPI Mode)

CS#

Mode 3

０

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23

SCLK

Mode ０

4 Dummy

Cycles

Data Data Data

Out 1 Out 2 Out 3

Command

E7h

6 ADD Cycles

D4 D0 D4 D0 D4 D0

D4

A20 A16 A12 A8 A4 A0

SIO0

SIO1

SIO2

D5 D1 D5 D1 D5 D1

D6 D2 D6 D2 D6 D2

D5

D6

A21 A17 A13 A9 A5 A1

A22 A18 A14 A10 A6 A2

A23 A19 A15 A11 A7 A3

D7 D3 D7 D3 D7 D3

D7

SIO3

Figure 39. W4READ (Quad Read with 4 dummy cycles) Sequence (QPI Mode)

CS#

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

MODE 3

MODE 0

MODE 3

MODE 0

SCLK

E7h

Data In

SIO[3:0]

H0 L0 H1 L1 H2 L2 H3 L3

A5 A4 A3 A2 A1 A0

24-bit Address

X

4 Dummy

Cycles

MSB

Data Out

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ADVANCED INFORMATION

MX25U12843G

9-17. 4 x I/O Double Transfer Rate Read Mode (4DTRD)

The 4DTRD instruction enables Double Transfer Rate throughput on quad I/O of Serial NOR Flash in read mode. A

Quad Enable (QE) bit of status Register must be set to "1" before sending the 4DTRD instruction. The address (interleave

on 4 I/O pins) is latched on both rising and falling edge of SCLK, and data (interleave on 4 I/O pins) shift out on

both rising and falling edge of SCLK. The 8-bit address can be latched-in at one clock, and 8-bit data can be read

out at one clock, which means four bits at rising edge of clock, the other four bits at falling edge of clock. The ﬁrst

address byte can be at any location. The address is automatically increased to the next higher address after each

byte data is shifted out, so the whole memory can be read out at a single 4DTRD instruction. The address counter

rolls over to 0 when the highest address has been reached. Once writing 4DTRD instruction, the following address/

dummy/data out will perform as 8-bit instead of previous 1-bit.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

While Program/Erase/Write Status Register cycle is in progress, 4DTRD instruction is rejected without any impact

on the Program/Erase/Write Status Register current cycle.

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MX25U12843G

Figure 40. Fast Quad I/O DT Read (4DTRD) Sequence (SPI Mode)

CS#

0

7

8

9

10

11

16

17

18

Mode 3

Mode 0

SCLK

…

Performance

Enhance Indicator

Command

3 ADD Cycles

Configurable

Dummy Cycle

…

SIO0

SIO1

EDh

A20 A16

A21 A17

A4 A0 P4 P0

D4 D0 D4 D0 D4

D5 D1 D5 D1 D5

…

P5

A5 A1

A6 A2

P1

…

P2

P3

A22 A18

A23 A19

P6

P7

SIO2

SIO3

D6 D2 D6 D2 D6

D7 D3 D7 D3 D7

A3

A7

Notes:

1. Hi-impedance is inhibited for this clock cycle.

2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) will result in entering the performance enhance mode.

3. Conﬁguration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in

conﬁguration register.

Figure 41. Fast Quad I/O DT Read (4DTRD) Sequence (QPI Mode)

CS#

0

1

2

3

4

5

10

11

12

Mode 3

Mode 0

SCLK

…

Command

3 ADD Cycles

A16 A12 A8

Performance

Enhance Indicator

Configurable

Dummy Cycle

A20

|

A4

|

A0

|

SIO[3:0]

EDh

P1 P0

H0 L0 H1 L1 H2

A23

A19 A15 A11

A7

A3

Note:

1. Conﬁguration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in

conﬁguration register.

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ADVANCED INFORMATION

MX25U12843G

9-18. Preamble Bit

The Preamble Bit data pattern supports system/memory controller to determine valid window of data output more

easily and improve data capture reliability while the ﬂash memory is running in high frequency.

Preamble Bit data pattern can be enabled or disabled by setting the bit4 of Conﬁguration register (Preamble bit

Enable bit). Once the CR<4> is set, the preamble bit is inputted into dummy cycles.

Enabling preamble bit will not affect the function of enhance mode bit. In Dummy cycles, performance enhance

mode bit still operates with the same function. Preamble bit will output after performance enhance mode bit.

The preamble bit is a ﬁxed 8-bit data pattern (00110100). While dummy cycle number reaches 10, the complete

8 bits will start to output right after the performance enhance mode bit. While dummy cycle is not sufﬁcient of 10

cycles, the rest of the preamble bits will be cut. For example, 8 dummy cycles will cause 6 preamble bits to output,

and 6 dummy cycles will cause 4 preamble bits to output.

Figure 42. SDR 1I/O (10DC)

CS#

SCLK

…

Dummy

cycle

Command

cycle

Address cycle

Preamble bits

…

An

A0

CMD

SI

…

SO

7

6

5

4

3

2

1

0

D7 D6

Figure 43. SDR 1I/O (8DC)

CS#

SCLK

…

Dummy cycle

Preamble bits

Command

cycle

Address cycle

…

SI

CMD

An

A0

…

7

6

5

4

3

2

D7 D6 D5 D4

SO

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ADVANCED INFORMATION

MX25U12843G

Figure 44. SDR 2I/O (10DC)

CS#

SCLK

…

Dummy cycle

Preamble bits

Command

cycle

Address cycle

Toggle

bits

…

A(n-1)

A0

A1

CMD

SIO0

7

6

5

4

3

2

1

0

D6 D4 D2 D0

…

An

D7 D5 D3 D1

SIO1

Figure 45. SDR 2I/O (8DC)

CS#

SCLK

…

Dummy cycle

Preamble bits

Command

cycle

Address cycle

Toggle

bits

…

A(n-1)

A0

A1

CMD

SIO0

SIO1

7

6

5

4

3

2

D6 D4 D2 D0

…

An

D7 D5 D3 D1

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MX25U12843G

Figure 46. SDR 4I/O (10DC)

CS#

SCLK

…

Dummy cycle

Preamble bits

Command

cycle

Address cycle

Toggle

bits

…

A(n-3)

A0

A1

CMD

7

6

5

4

3

2

1

0

D4 D0

SIO0

SIO1

…

A(n-2)

A(n-1)

An

D5

D1

A2

A3

7

6

5

4

3

2

1

0

D6 D2

D7 D3

SIO2

SIO3

Figure 47. SDR 4I/O (8DC)

CS#

SCLK

…

Dummy cycle

Preamble bits

Command

cycle

Address cycle

Toggle

bits

…

A(n-3)

A0

A1

CMD

7

6

5

4

3

2

D4 D0

SIO0

SIO1

SIO2

…

A(n-2)

A(n-1)

An

2

D5

D1

A2

A3

D6 D2

D7 D3

…

7

6

5

4

3

SIO3

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MX25U12843G

Figure 48. DTR4IO (6DC)

CS#

SCLK

…

Dummy cycle

Preamble bits

Command

cycle

Address cycle

Toggle

Bits

…

A0

7

6

5

4

3

2

1

0

D4 D0 D4 D0 D4 D0 D4 D0

D5 D1 D5 D1 D5 D1 D5 D1

CMD

SIO0

SIO1

SIO2

A(n-3)

A(n-2)

A(n-1)

…

A1

A2

7

6

5

4

3

2

1

0

D6 D2 D6 D2 D6 D2 D6 D2

D7 D3 D7 D3 D7 D3 D7 D3

A3

…

SIO3

An

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ADVANCED INFORMATION

MX25U12843G

9-19. Burst Read

The Burst Read feature allows applications to ﬁll a cache line with a ﬁxed length of data without using multiple read

commands. Burst Read is disabled by default at power-up or reset. Burst Read is enabled by setting the Burst

Length. When the Burst Length is set, reads will wrap on the selected boundary (8/16/32/64-bytes) containing the

initial target address. For example if an 8-byte Wrap Depth is selected, reads will wrap on the 8-byte-page-aligned

boundary containing the initial read address.

To set the Burst Length, drive CS# low → send SET BURST LENGTH instruction code → send WRAP CODE →

drive CS# high. Refer to the table below for valid 8-bit Wrap Codes and their corresponding Wrap Depth.

Data

00h

01h

02h

03h

1xh

Wrap Around

Wrap Depth

8-byte

Yes

No

16-byte

32-byte

64-byte

X

Once Burst Read is enabled, it will remain enabled until the device is power-cycled or reset. The SPI and QPI mode

4READ read commands support the wrap around feature after Burst Read is enabled. To change the wrap depth,

resend the Burst Read instruction with the appropriate Wrap Code. To disable Burst Read, send the Burst Read

instruction with Wrap Code 1xh. QPI “0Bh” “EBh” and SPI “EBh” “E7h” support wrap around feature after wrap

around is enabled. Both SPI (8 clocks) and QPI (2 clocks) command cycle can be accepted by this instruction. The

SIO[3:1] are don't care during SPI mode.

Figure 49. Burst Read - SPI Mode

CS#

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Mode 3

Mode 0

SCLK

SIO

D7

D6

D5

D4

D3

D2

D1

D0

C0h

Figure 50. Burst Read - QPI Mode

CS#

0

1

2

3

Mode 3

Mode 0

SCLK

C0h

H0

L0

SIO[3:0]

MSB LSB

Note: MSB=Most Signiﬁcant Bit

LSB=Least Signiﬁcant Bit

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MX25U12843G

9-20. Performance Enhance Mode

The device could waive the command cycle bits if the two cycle bits after address cycle toggles.

Performance enhance mode is supported in both SPI and QPI mode.

In QPI mode, "EBh" and SPI “EBh” commands support enhance mode. The performance enhance mode is not

supported in dual I/O mode.

To enter performance-enhancing mode, P[7:4] must be toggling with P[3:0]; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh

can make this mode continue and skip the next 4READ instruction. To leave enhance mode, P[7:4] is no longer

toggling with P[3:0]; likewise P[7:0]=FFh, 00h, AAh or 55h along with CS# is afterwards raised and then lowered.

Issuing ”FFh” data cycle can also exit enhance mode. The system then will leave performance enhance mode and

return to normal operation.

After entering enhance mode, following CS# go high, the device will stay in the read mode and treat CS# go low of

the ﬁrst clock as address instead of command cycle.

This sequence of issuing 4READ instruction especially useful in random access: CS# goes low→send 4READ

instruction→3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0→performance enhance toggling bit P[7:0]→

4 dummy cycles (Default) →data out until CS# goes high → CS# goes low (The following 4READ instruction is not

allowed, hence 8 cycles of 4READ can be saved comparing to normal 4READ mode) → 3-bytes random access

address.

To conduct the Performance Enhance Mode Reset operation in SPI mode, FFh data should be issued in 1I/O

sequence. In QPI Mode, FFFFFFFFh data cycle, in 4 I/O should be issued.

If the system controller is being Reset during operation, the ﬂash device will return to the standard SPI operation.

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ADVANCED INFORMATION

MX25U12843G

Figure 51. 4 x I/O Read Performance Enhance Mode Sequence (SPI Mode)

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22

n

SCLK

Data

Out 2

Data

Out n

Command

6 ADD Cycles

Performance

enhance

Out 1

indicator (Note 1)

Configurable

Dummy Cycle (Note 2)

P4 P0

D4 D0 D4 D0

D4 D0

A20 A16 A12 A8 A4 A0

EBh

SIO0

SIO1

SIO2

A21 A17 A13 A9 A5 A1

A22 A18 A14 A10 A6 A2

D5 D1 D5 D1

D6 D2 D6 D2

D5 D1

D6 D2

P5 P1

P6 P2

A23 A19 A15 A11 A7 A3

D7 D3 D7 D3

D7 D3

P7 P3

SIO3

CS#

n+1

...........

n+7......n+9 ........... n+13

...........

Mode 3

Mode 0

SCLK

Data

Out 1

Data

Out 2

Data

Out n

6 ADD Cycles

Performance

enhance

indicator (Note 1)

Configurable

Dummy Cycle (Note 2)

D4 D0 D4 D0

D4 D0

P4 P0

A20 A16 A12 A8 A4 A0

SIO0

SIO1

SIO2

SIO3

D5 D1 D5 D1

D6 D2 D6 D2

D5 D1

D6 D2

A21 A17 A13 A9 A5 A1

A22 A18 A14 A10 A6 A2

P5 P1

P6 P2

D7 D3 D7 D3

D7 D3

A23 A19 A15 A11 A7 A3

P7 P3

Notes:

1. If not using performance enhance recommend to keep 1 or 0 in performance enhance indicator.

Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF.

2. Conﬁguration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in

conﬁguration register.

Macronix Proprietary

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ADVANCED INFORMATION

MX25U12843G

Figure 52. 4 x I/O Read Performance Enhance Mode Sequence (QPI Mode)

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

SCLK

EBh

SIO[3:0]

X

H0 L0 H1 L1

MSB LSB MSB LSB

A5 A4 A3 A2 A1 A0

P(7:4)P(3:0)

Data In

Data Out

performance

enhance

indicator

Configurable

Dummy Cycle (Note 1)

CS#

SCLK

n+1 .............

Mode 0

SIO[3:0]

X

H0 L0 H1 L1

MSB LSB MSB LSB

A5 A4 A3 A2 A1 A0

P(7:4)P(3:0)

Data Out

6 Address cycles

performance

enhance

indicator

Configurable

Dummy Cycle (Note 1)

Note:

1. Conﬁguration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in

conﬁguration register.

2. Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF.

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MX25U12843G

9-21. Sector Erase (SE)

The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used

for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit

before sending the Sector Erase (SE). Any address of the sector (Please refer to "Table 4. Memory Organization")

is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the least

signiﬁcant bit of the address byte been latched-in); otherwise, the instruction will be rejected and not executed.

The sequence of issuing SE instruction is: CS# goes low→ sending SE instruction code→ 3-byte on SI→ CS# goes

high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in

Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets 1 during the tSE

timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the

sector is protected by BP3, BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the sector.

Figure 53. Sector Erase (SE) Sequence (SPI Mode)

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

29 30 31

SCLK

24-Bit Address

Command

20h

SI

A23 A22

A2 A1 A0

MSB

Figure 54. Sector Erase (SE) Sequence (QPI Mode)

CS#

Mode 3

0

1

2

3

4

5

6

7

SCLK

Mode 0

24-Bit Address

Command

SIO[3:0]

20h A5 A4 A3 A2 A1 A0

MSB

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MX25U12843G

9-22. Block Erase (BE32K)

The Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1". The instruction is used

for 32K-byte block erase operation. A Write Enable (WREN) instruction be executed to set the Write Enable Latch

(WEL) bit before sending the Block Erase (BE32K). Any address of the block (as shown in "Table 4. Memory

Organization") is a valid address for Block Erase (BE32K) instruction. The CS# must go high exactly at the byte

boundary (the least signiﬁcant bit of address byte been latched-in); otherwise, the instruction will be rejected and not

executed.

Address bits [Am-A15] (Am is the most signiﬁcant address) select the 32KB block address.

The sequence of issuing BE32K instruction is: CS# goes low→ sending BE32K instruction code→ 3-byte address

on SI→CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

The self-timed Block Erase Cycle time (tBE32K) is initiated as soon as Chip Select (CS#) goes high. The Write in

Progress (WIP) bit still can be checked while during the Block Erase cycle is in progress. The WIP sets during the

tBE32K timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If

the block is protected by BP3, BP2, BP1, BP0 bits, the Block Erase (BE32K) instruction will not be executed on the

block.

Figure 55. Block Erase 32KB (BE32K) Sequence (SPI Mode)

CS#

0

1

2

3

4

5

6

7

8

9

29 30 31

Mode 3

Mode 0

SCLK

Command

52h

24-Bit Address

SI

A23 A22

A2

A0

A1

MSB

Figure 56. Block Erase 32KB (BE32K) Sequence (QPI Mode)

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

SCLK

24-Bit Address

Command

SIO[3:0]

52h A5 A4 A3 A2 A1 A0

MSB

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MX25U12843G

9-23. Block Erase (BE)

The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used

for 64K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable

Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (Please refer to "Table 4. Memory

Organization") is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the

least signiﬁcant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed.

The sequence of issuing BE instruction is: CS# goes low→ sending BE instruction code→ 3-byte address on SI→

CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in

Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during the tBE

timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the

block is protected by BP3, BP2, BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the block.

Figure 57. Block Erase (BE) Sequence (SPI Mode)

CS#

0

1

2

3

4

5

6

7

8

9

29 30 31

Mode 3

Mode 0

SCLK

Command

D8h

24-Bit Address

SI

A23 A22

A2

A0

A1

MSB

Figure 58. Block Erase (BE) Sequence (QPI Mode)

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

SCLK

24-Bit Address

Command

SIO[3:0]

D8h A5 A4 A3 A2 A1 A0

MSB

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MX25U12843G

9-24. Chip Erase (CE)

The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN)

instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS#

must go high exactly at the byte boundary, otherwise the instruction will be rejected and not executed.

The sequence of issuing CE instruction is: CS# goes low→sending CE instruction code→CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in

Progress (WIP) bit still can be checked while the Chip Erase cycle is in progress. The WIP sets during the tCE

timing, and clears when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared.

When the chip is under "Block protect (BP) Mode" (WPSEL=0). The Chip Erase (CE) instruction will not be

executed, if one (or more) sector is protected by BP3-BP0 bits. It will be only executed when BP3-BP0 all set to "0".

When the chip is under "Advances Sector Protect Mode" (WPSEL=1). The Chip Erase (CE) instruction will be

executed on unprotected block. The protected Block will be skipped. If one (or more) 4K byte sector was protected

in top or bottom 64K byte block, the protected block will also skip the chip erase command.

Figure 59. Chip Erase (CE) Sequence (SPI Mode)

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

SCLK

SI

Command

60h or C7h

Figure 60. Chip Erase (CE) Sequence (QPI Mode)

CS#

0

1

Mode 3

Mode 0

SCLK

Command

60h or C7h

SIO[3:0]

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MX25U12843G

9-25. Page Program (PP)

The Page Program (PP) instruction is for programming memory bits to "0". One to 256 bytes can be sent to the

device to be programmed. A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL)

bit before sending the Page Program (PP). If more than 256 data bytes are sent to the device, only the last 256

data bytes will be accepted and the previous data bytes will be disregarded. The Page Program instruction requires

that all the data bytes fall within the same 256-byte page. The low order address byte A[7:0] speciﬁes the starting

address within the selected page. Bytes that will cross a page boundary will wrap to the beginning of the selected

page. The device can accept (256 minus A[7:0]) data bytes without wrapping. If 256 data bytes are going to be

programmed, A[7:0] should be set to 0.

The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→ at

least 1-byte on data on SI→ CS# goes high.

The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte

boundary( the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be

executed.

The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in

Progress (WIP) bit still can be checked while the Page Program cycle is in progress. The WIP sets during the tPP

timing, and clears when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the

page is protected by BP3, BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

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Figure 61. Page Program (PP) Sequence (SPI Mode)

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38 39

SCLK

Command

02h

Data Byte 1

24-Bit Address

23 22 21

MSB

3

2

1

0

7

6

5

4

3

2

0

1

SI

MSB

CS#

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

SCLK

Data Byte 2

Data Byte 3

Data Byte 256

7

6

5

4

3

2

0

7

6

5

4

3

2

0

7

6

5

4

3

2

0

1

SI

MSB

Figure 62. Page Program (PP) Sequence (QPI Mode)

CS#

Mode 3

Mode 0

0

1

2

SCLK

Command

02h

24-Bit Address

H255 L255

SIO[3:0]

H0 L0 H1 L1 H2 L2 H3 L3

Data Byte Data Byte Data Byte Data Byte

A5 A4 A3 A2 A1 A0

......

Data Byte

256

Data In

1

2

3

4

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9-26. 4 x I/O Page Program (4PP)

The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN)

instruction must be executed to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to

"1" before sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1,

SIO2, and SIO3 as address and data input, which can improve programmer performance and the effectiveness of

application. The other function descriptions are as same as standard page program.

The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on

SIO[3:0]→ at least 1-byte on data on SIO[3:0]→CS# goes high.

If the page is protected by BP3, BP2, BP1, BP0 bits, the Quad Page Program (4PP) instruction will not be executed.

Figure 63. 4 x I/O Page Program (4PP) Sequence (SPI Mode only)

CS#

10 11 12 13 14 15 16 17 18 19 20 21

Data Data Data Data

0

1

2

3

4

5

6

7

8

9

Mode 3

Mode 0

SCLK

Command

38h

6 Address cycle

Byte 1 Byte 2 Byte 3 Byte 4

A16

A8 A4 A0

A12

A20

4

0

4

0

4

0

4

0

SIO0

SIO1

SIO2

SIO3

A21 A17 A13 A9 A5 A1

5

6

7

1

2

3

5

6

7

1

2

3

5

6

7

1

2

3

5

6

7

1

2

3

A22

A14 A10 A6 A2

A18

A7

A23 A19 A15 A11

A3

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9-27. Deep Power-down (DP)

The Deep Power-down (DP) instruction places the device into a minimum power consumption state, Deep Power-

down mode, in which the quiescent current is reduced from ISB1 to ISB2.

The sequence of issuing DP instruction: CS# goes low→ send DP instruction code→ CS# goes high. The CS# must

go high at the byte boundary (after exactly eighth bits of the instruction code have been latched-in); otherwise the

instruction will not be executed. Both SPI (8 clocks) and QPI (2 clocks) command cycle can be accepted by this

instruction. SIO[3:1] are "don't care".

After CS# goes high there is a delay of tDP before the device transitions from Stand-by mode to Deep Power-down

mode and before the current reduces from ISB1 to ISB2. Once in Deep Power-down mode, all instructions will be

ignored except Release from Deep Power-down (RDP).

The device exits Deep Power-down mode and returns to Stand-by mode if it receives a Release from Deep

Powerdown (RDP) instruction, power-cycle, or reset. Please refer to "Figure 17. Release from Deep Power-down (RDP)

Sequence (SPI Mode)" and "Figure 18. Release from Deep Power-down (RDP) Sequence (QPI Mode)".

Figure 64. Deep Power-down (DP) Sequence (SPI Mode)

CS#

t

DP

0

1

2

3

4

5

6

7

Mode 3

Mode 0

SCLK

SI

Command

B9h

Stand-by Mode

Deep Power-down Mode

Figure 65. Deep Power-down (DP) Sequence (QPI Mode)

CS#

t

DP

Mode 3

Mode 0

0

1

SCLK

Command

SIO[3:0]

B9h

Stand-by Mode

Deep Power-down Mode

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9-28. Enter Secured OTP (ENSO)

The ENSO instruction is for entering the additional 4K-bit secured OTP mode. While device is in 4K-bit secured

OTPmode, main array access is not available. The additional 4K-bit secured OTP is independent from main array

and may be used to store unique serial number for system identiﬁer. After entering the Secured OTP mode, follow

standard read or program procedure to read out the data or update data. The Secured OTP data cannot be updated

again once it is lock-down.

The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP

mode→ CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

Please note that after issuing ENSO command user can only access secure OTP region with standard read or

program procedure. Furthermore, once security OTP is lock down, only read related commands are valid.

9-29. Exit Secured OTP (EXSO)

The EXSO instruction is for exiting the additional 4K-bit secured OTP mode.

The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP

mode→ CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

9-30. Read Security Register (RDSCUR)

The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read

at any time (even in program/erase/write status register/write security register condition) and continuously.

The sequence of issuing RDSCUR instruction is : CS# goes low→sending RDSCUR instruction→Security Register

data out on SO→ CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

9-31. Write Security Register (WRSCUR)

The WRSCUR instruction is for changing the values of Security Register Bits. The WREN (Write Enable) instruction

is required before issuing WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO

bit) for customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area

cannot be updated any more.

The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.

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Security Register

The deﬁnition of the Security Register bits is as below:

Write Protection Selection bit. Please reference to "

Write Protection Selection bit

"

Erase Fail bit. The Erase Fail bit is a status ﬂag, which shows the status of last Erase operation. It will be set to "1",

if the erase operation fails. It will be set to "0", if the last operation is success. Please note that it will not interrupt or

stop any operation in the ﬂash memory.

Program Fail bit. The Program Fail bit is a status ﬂag, which shows the status of last Program operation. It will be

set to "1", if the program operation fails or the program region is protected. It will be set to "0", if the last operation is

success. Please note that it will not interrupt or stop any operation in the ﬂash memory.

Erase Suspend bit. Erase Suspend Bit (ESB) indicates the status of Erase Suspend operation. Users may use

ESB to identify the state of ﬂash memory. After the ﬂash memory is suspended by Erase Suspend command, ESB

is set to "1". ESB is cleared to "0" after erase operation resumes.

Program Suspend bit. Program Suspend Bit (PSB) indicates the status of Program Suspend operation. Users may

use PSB to identify the state of ﬂash memory. After the ﬂash memory is suspended by Program Suspend command,

PSB is set to "1". PSB is cleared to "0" after program operation resumes.

Secured OTP Indicator bit. The Secured OTP indicator bit shows the Secured OTP area is locked by factory or

not. When it is "0", it indicates non-factory lock; "1" indicates factory-lock.

Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for

customer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 4K-bit Secured

OTP area cannot be updated any more. While it is in 4K-bit secured OTP mode, main array access is not allowed.

Table 12. Security Register Deﬁnition

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

ESB

(Erase

PSB

(Program

LDSO

(indicate if

Secured OTP

indicator bit

WPSEL

E_FAIL

P_FAIL

Reserved

Suspend bit) Suspend bit) lock-down)

0=normal

Program

succeed

1=indicate

Program

failed

0 = not lock-

0=Block Lock (BP) 0=normal

0=Erase

is not

suspended suspended

1= Erase 1= Program

suspended suspended

0=Program

is not

down

1 = lock-down

(cannot

0 = non-

factory

lock

1 = factory

lock

protection mode

Erase

succeed

1=Individual Block 1=indicate

Protection mode Erase failed

-

program/

erase

OTP)

(default=0)

Volatile bit

(default=0)

Volatile bit

(default=0)

Non-volatile

bit

Non-volatile bit

(OTP)

Non-volatile

bit (OTP)

Volatile bit Volatile bit Volatile bit

(OTP)

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9-32. Write Protection Selection (WPSEL)

There are two write protection methods provided on this device, (1) Block Protection (BP) mode or (2) Individual

Block Protection mode. The protection modes are mutually exclusive. The WPSEL bit selects which protection mode

is enabled. If WPSEL=0 (factory default), BP mode is enabled and Individual Block Protection mode is disabled. If

WPSEL=1, Individual Block Protection mode is enabled and BP mode is disabled. The WPSEL command is used

to set WPSEL=1. A WREN command must be executed to set the WEL bit before sending the WPSEL command.

Please note that the WPSEL bit is an OTP bit. Once WPSEL is set to “1”, it cannot be programmed back to “0”.

When WPSEL = 0: Block Lock (BP) protection mode,

The memory array is write protected by the BP3-BP0 bits as in "Figure 66. BP and SRWD if WPSEL=0".

When WPSEL =1: Individual Block Protection mode,

Blocks are individually protected by their own SRAM lock bits. On power-up, all blocks are write protected by the

SRAM bits by default. The Individual Block Protection instructions SBLK, SBULK, RDBLOCK, GBLK, and GBULK

are activated. The BP3-BP0 bits of the Status Register are disabled and have no effect. Hardware protection is

performed by driving WP#=0. Once WP#=0 all blocks and sectors are write protected regardless of the state of

each SRAM lock bit. Please refer to "Figure 67. The individual block lock mode is effective after setting WPSEL=1".

The sequence of issuing WPSEL instruction is: CS# goes low → send WPSEL instruction to enable the Individual

Block Protect mode → CS# goes high. Please refer to "Figure 68. Write Protection Selection (WPSEL) Sequence

(Command 68h)".

Figure 66. BP and SRWD if WPSEL=0

WP# pin

BP3 BP2 BP1 BP0

SRWD

64KB

(1) BP3-BP0 is used to deﬁne the protection group region.

(For the protected area size, please refer to "Table 2.

Protected Area Sizes")

(2) “SRWD=1 and WP#=0” is used to protect BP3-BP0. In this

case, SRWD and BP3-BP0 of status register bits can not

be changed by WRSR command.

.

64KB

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Figure 67. The individual block lock mode is effective after setting WPSEL=1

4KB

SRAM

• Power-Up: All SRAM bits=1 (all blocks are default protected).

All array cannot be programmed/erased

TOP 4KBx16

Sectors

• SBLK/SBULK(36h/39h):

- SBLK(36h): Set SRAM bit=1 (protect) : array can not be

programmed/erased

4KB

SRAM

- SBULK(39h): Set SRAM bit=0 (unprotect): array can be

programmed/erased

64KB

- All top 4KBx16 sectors and bottom 4KBx16 sectors

and other 64KB uniform blocks can be protected and

unprotected by SRAM bits individually by SBLK/SBULK

command set.

SRAM

Uniform

64KB blocks

• GBLK/GBULK(7Eh/98h):

- GBLK(7Eh): Set all SRAM bits=1, whole chip is protected

and cannot be programmed/erased.

- GBULK(98h): Set all SRAM bits=0, whole chip is

unprotected and can be programmed/erased.

- All sectors and blocks SRAM bits of whole chip can be

protected and unprotected at one time by GBLK/GBULK

command set.

64KB

4KB

SRAM

Bottom

4KBx16

Sectors

• RDBLOCK(3Ch):

- use RDBLOCK mode to check the SRAM bits status after

SBULK /SBLK/GBULK/GBLK command set.

4KB

SBULK / SBLK / GBULK / GBLK / RDBLOCK

Figure 68. Write Protection Selection (WPSEL) Sequence (Command 68h)

CS#

0

1

2

3

4

5

6

7

SCLK

SI

Command

68

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Figure 69. WPSEL Flow

start

WREN command

RDSCUR(2Bh) command

WPSEL=1?

Yes

No

WPSEL disable,

block protected by BP[3:0]

WPSEL(68h) command

RDSR command

WIP=0?

No

Yes

RDSCUR(2Bh) command

No

WPSEL=1?

Yes

WPSEL set successfully

WPSEL set fail

WPSEL enable.

Block protected by individual lock

(SBLK, SBULK, … etc).

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9-33. Single Block Lock/Unlock Protection (SBLK/SBULK)

These instructions are only effective if WPSEL=1. The SBLK instruction is for write protection a speciﬁed block (or

sector) of memory, using A_MAX-A16 or (A_MAX-A12) address bits to assign a 64Kbyte block (or 4K bytes sector) to be

protected as read only. The SBULK instruction will cancel the block (or sector) write protection state. This feature

allows user to stop protecting the entire block (or sector) through the chip unprotect command (GBULK).

The WREN (Write Enable) instruction is required before issuing SBLK/SBULK instruction.

The sequence of issuing SBLK/SBULK instruction is: CS# goes low → send SBLK/SBULK (36h/39h)

instruction→send 3-byte address assign one block (or sector) to be protected on SI pin → CS# goes high. The CS#

must go high exactly at the byte boundary, otherwise the instruction will be rejected and not be executed.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care"

in SPI mode.

SBLK/SBULK instruction function ﬂow is as follows:

Figure 70. Block Lock Flow

Start

RDSCUR(2Bh) command

No

WPSEL=1?

WPSEL command

Yes

WREN command

SBLK command

( 36h + 24bit address )

RDSR command

No

WIP=0?

Yes

RDBLOCK command

( 3Ch + 24bit address )

No

Data = FFh ?

Yes

Block lock successfully

Block lock fail

Yes

Lock another block?

No

Block lock completed

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Figure 71. Block Unlock Flow

start

RDSCUR(2Bh) command

No

WPSEL=1?

Yes

WPSEL command

WREN command

SBULK command

( 39h + 24bit address )

RDSR command

No

WIP=0?

Yes

RDBLOCK command to verify

( 3Ch + 24bit address )

Yes

Data = FF ?

No

Block unlock successfully

Block unlock fail

Yes

Unlock another block?

Unlock block completed?

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9-34. Read Block Lock Status (RDBLOCK)

This instruction is only effective if WPSEL=1. The RDBLOCK instruction is for reading the status of protection lock

of a speciﬁed block (or sector), using A_MAX-A16 (or A_MAX-A12) address bits to assign a 64K bytes block (4K bytes

sector) and read protection lock status bit which the ﬁrst byte of Read-out cycle. The status bit is"1" to indicate that

this block has be protected, that user can read only but cannot write/program /erase this block. The status bit is "0"

to indicate that this block hasn't be protected, and user can read and write this block.

The sequence of issuing RDBLOCK instruction is: CS# goes low → send RDBLOCK (3Ch) instruction → send

3-byte address to assign one block on SI pin → read block's protection lock status bit on SO pin → CS# goes high.

This instruction are accepted in both SPI and QPI mode. The SIO[3:1] are "don't care" in SPI mode.

9-35. Gang Block Lock/Unlock (GBLK/GBULK)

These instructions are only effective if WPSEL=1. The GBLK and GBULK instructions provide a quick method to

enable/disable the lock protection block of the whole chip at once.

The WREN (Write Enable) instruction is required before issuing the GBLK/GBULK instruction.

The sequence of issuing GBLK/GBULK instruction is: CS# goes low → send GBLK/GBULK (7Eh/98h) instruction

→CS# goes high.

This instruction are accepted in both SPI and QPI mode. The SIO[3:1] are "don't care" in SPI mode.

The CS# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed.

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9-36. Program Suspend and Erase Suspend

The Suspend instruction interrupts a Page Program, Sector Erase, or Block Erase operation to allow access to the

memory array.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

After the program or erase operation has entered the suspended state, the memory array can be read except for the

page being programmed or the sector or block being erased ("Table 13. Readable Area of Memory While a Program

or Erase Operation is Suspended").

Table 13. Readable Area of Memory While a Program or Erase Operation is Suspended

Suspended Operation

Page Program

Readable Region of Memory Array

All but the Page being programmed

All but the 4KB Sector being erased

All but the 32KB Block being erased

All but the 64KB Block being erased

Sector Erase (4KB)

Block Erase (32KB)

Block Erase (64KB)

When the Serial NOR Flash receives the Suspend instruction, there is a latency of tPSL or tESL ("Figure 72.

Suspend to Read Latency") before the Write Enable Latch (WEL) bit clears to “0” and the PSB or ESB sets to

“1”, after which the device is ready to accept one of the commands listed in "Table 14. Acceptable Commands

During Program/Erase Suspend after tPSL/tESL" (e.g. FAST READ). Refer to "Table 21. AC CHARACTERISTICS

(Temperature = -40°C to 85°C, VCC = 1.65V - 2.0V)" for tPSL and tESL timings.

"Table 15. Acceptable Commands During Suspend (tPSL/tESL not required)" lists the commands for which the tPSL

and tESL latencies do not apply. For example, RDSR, RDSCUR, RSTEN, and RST can be issued at any time after

the Suspend instruction.

Security Register bit 2 (PSB) and bit 3 (ESB) can be read to check the suspend status (please refer to "Table 12.

Security Register Deﬁnition"). The PSB (Program Suspend Bit) sets to “1” when a program operation is suspended.

The ESB (Erase Suspend Bit) sets to “1” when an erase operation is suspended. The PSB or ESB clears to “0”

when the program or erase operation is resumed.

Figure 72. Suspend to Read Latency

tPSL / tESL

Read Command

Suspend Command

CS#

tPSL: Program Latency

tESL: Erase Latency

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Table 14. Acceptable Commands During Program/Erase Suspend after tPSL/tESL

Suspend Type

Command Name

Command Code

Program Suspend

Erase Suspend

READ

FAST READ

DREAD

QREAD

2READ

4READ

W4READ

RDSFDP

RDID

03h

0Bh

•

3Bh

6Bh

BBh

EBh

E7h

5Ah

9Fh

QPIID

AFh

90h

REMS

ENSO

B1h

EXSO

C1h

06h

WREN

EQIO

35h

RSTQIO

RESUME

SBL

F5h

7Ah or 30h

C0h

02h

PP

4PP

38h

Table 15. Acceptable Commands During Suspend (tPSL/tESL not required)

Suspend Type

Command Name

Command Code

Program Suspend

Erase Suspend

WRDI

RDSR

RDCR

RDSCUR

RES

04h

05h

15h

2Bh

ABh

66h

99h

00h

•

RSTEN

RST

NOP

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Figure 73. Resume to Suspend Latency

tPRS / tERS

Resume Command

Suspend Command

CS#

tPRS: Program Resume to another Suspend

tERS: Erase Resume to another Suspend

9-37. Program Resume and Erase Resume

The Resume instruction resumes a suspended Page Program, Sector Erase, or Block Erase operation. Before

issuing the Resume instruction to restart a suspended erase operation, make sure that there is no Page Program

operation in progress.

Immediately after the Serial NOR Flash receives the Resume instruction, the WEL and WIP bits are set to “1” and

the PSB or ESB is cleared to “0”. The program or erase operation will continue until ﬁnished ("Figure 74. Resume to

Read Latency") or until another Suspend instruction is received. A resume-to-suspend latency of tPRS or tERS must

be observed before issuing another Suspend instruction ("Figure 73. Resume to Suspend Latency").

Please note that the Resume instruction will be ignored if the Serial NOR Flash is in “Performance Enhance Mode”.

Make sure the Serial NOR Flash is not in “Performance Enhance Mode” before issuing the Resume instruction.

Figure 74. Resume to Read Latency

tSE / tBE / tPP

Resume Command

Read Command

CS#

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9-38. No Operation (NOP)

The “No Operation” command is only able to terminate the Reset Enable (RSTEN) command and will not affect any

other command.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

during SPI mode.

9-39. Software Reset (Reset-Enable (RSTEN) and Reset (RST))

The Software Reset operation combines two instructions: Reset-Enable (RSTEN) command and Reset (RST)

command. It returns the device to standby mode. All the volatile bits and settings will be cleared then, which makes

the device return to the default status as power on.

To execute Reset command (RST), the Reset-Enable (RSTEN) command must be executed ﬁrst to perform the

Reset operation. If there is any other command to interrupt after the Reset-Enable command, the Reset-Enable will

be invalid.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

If the Reset command is executed during program or erase operation, the operation will be disabled, the data under

processing could be damaged or lost.

The reset time is different depending on the last operation. For details, please refer to "Table 17. Reset Timing-

(Other Operation)" for tREADY2.

Macronix Proprietary

P/N: PM2705

Rev. 0.00, February 26, 2019

77

ADVANCED INFORMATION

MX25U12843G

Figure 75. Software Reset Recovery

Stand-by Mode

66

99

CS#

tReady2

Mode

Note: Refer to "Table 17. Reset Timing-(Other Operation)" for tREADY2 data.

Figure 76. Reset Sequence (SPI mode)

tSHSL

CS#

Mode 3

Mode 0

Mode 3

Mode 0

SCLK

SIO0

Command

66h

Command

99h

Figure 77. Reset Sequence (QPI mode)

tSHSL

CS#

MODE 3

MODE 0

MODE 3

MODE 0

SCLK

MODE 0

Command

SIO[3:0]

66h

99h

Macronix Proprietary

P/N: PM2705

Rev. 0.00, February 26, 2019

78

ADVANCED INFORMATION

MX25U12843G

9-40. Read SFDP Mode (RDSFDP)

The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional

and feature capabilities of serial ﬂash devices in a standard set of internal parameter tables. These parameter tables

can be interrogated by host system software to enable adjustments needed to accommodate divergent features

from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on

CFI.

The sequence of issuing RDSFDP instruction is CS# goes low→send RDSFDP instruction (5Ah)→send 3 address

bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP operation can use CS#

to high at any time during data out.

SFDP is a JEDEC standard, JESD216B.

For SFDP register values detail, please contact local Macronix sales channel.

Figure 78. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence

CS#

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31

SCLK

Command

5Ah

24 BIT ADDRESS

SI

23 22 21

3

2

1

0

High-Z

SO

CS#

47

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

SCLK

Dummy Cycle

7

6

5

4

3

2

0

1

SI

DATA OUT 2

DATA OUT 1

7

6

5

4

3

2

1

0

7

6

5

4

3

2

0

1

SO

MSB

Macronix Proprietary

P/N: PM2705

Rev. 0.00, February 26, 2019

79

ADVANCED INFORMATION

MX25U12843G

10. RESET

Driving the RESET# pin low for a period of tRLRH or longer will reset the device. After reset cycle, the device is at

the following states:

- Standby mode

- All the volatile bits such as WEL/WIP/SRAM lock bit will return to the default status as power on.

- 3-byte address mode

If the device is under programming or erasing, driving the RESET# pin low will also terminate the operation and data

could be lost. During the resetting cycle, the SO data becomes high impedance and the current will be reduced to

minimum.

Figure 79. RESET Timing

CS#

tRHSL

SCLK

tRH

tRS

RESET#

tRLRH

tREADY1 / tREADY2

Table 16. Reset Timing-(Power On)

Symbol Parameter

tRHSL Reset# high before CS# low

Min.

10

Typ.

Max.

Unit

us

tRS

tRH

Reset# setup time

Reset# hold time

15

ns

tRLRH Reset# low pulse width

10

us

tREADY1 Reset Recovery time

35

us

Table 17. Reset Timing-(Other Operation)

Symbol Parameter

tRHSL Reset# high before CS# low

Min.

10

Typ.

Max.

Unit

us

tRS

tRH

Reset# setup time

Reset# hold time

15

ns

tRLRH Reset# low pulse width

10

us

Reset Recovery time (During instruction decoding)

Reset Recovery time (for read operation)

40

35

us

Reset Recovery time (for program operation)

tREADY2 Reset Recovery time(for SE4KB operation)

Reset Recovery time (for BE64K/BE32KB operation)

Reset Recovery time (for Chip Erase operation)

Reset Recovery time (for WRSR operation)

310

12

25

100

40

us

ms

Macronix Proprietary

P/N: PM2705

Rev. 0.00, February 26, 2019

80

ADVANCED INFORMATION

MX25U12843G

11. POWER-ON STATE

The device is at the following states after power-up:

- Standby mode (please note it is not deep power-down mode)

- Write Enable Latch (WEL) bit is reset

The device must not be selected during power-up and power-down stage until the VCC reaches the following levels:

- VCC minimum at power-up stage and then after a delay of tVSL

- GND at power-down

Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.

An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change

during power up state. When VCC is lower than VWI (POR threshold voltage value), the internal logic is reset and

the ﬂash device has no response to any command.

For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not

guaranteed. The write, erase, and program command should be sent after the below time delay:

- tVSL after VCC reached VCC minimum level

The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.

Please refer to the "Figure 87. Power-up Timing".

Note:

- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is

recommended. (generally around 0.1uF)

- At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response to

any command. The data corruption might occur during this stage if a write, program, erase cycle is in progress.

Macronix Proprietary

P/N: PM2705

Rev. 0.00, February 26, 2019

81

ADVANCED INFORMATION

MX25U12843G

12. ELECTRICAL SPECIFICATIONS

Table 18. ABSOLUTE MAXIMUM RATINGS

RATING

VALUE

Ambient Operating Temperature

Storage Temperature

Applied Input Voltage

Applied Output Voltage

VCC to Ground Potential

Industrial grade

-40°C to 85°C

-65°C to 150°C

-0.5V to VCC+0.5V

-0.5V to 2.5V

NOTICE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage

to the device. This is stress rating only and functional operational sections of this speciﬁcation is not implied.

Exposure to absolute maximum rating conditions for extended period may affect reliability.

2. Speciﬁcations contained within the following tables are subject to change.

3. During voltage transitions, all pins may overshoot to VCC+1.0V or -1.0V for period up to 20ns.

Figure 80. Maximum Negative Overshoot Waveform

Figure 81. Maximum Positive Overshoot Waveform

20ns

0V

VCC+1.0V

-1.0V

2.0V

20ns

Table 19. CAPACITANCE TA = 25°C, f = 1.0 MHz

Symbol Parameter

Min.

Typ.

Max.

Unit

pF

Conditions

VIN = 0V

CIN

Input Capacitance

6

8

COUT Output Capacitance

pF

VOUT = 0V

Macronix Proprietary

P/N: PM2705

Rev. 0.00, February 26, 2019

82

ADVANCED INFORMATION

MX25U12843G

Figure 82. DATA INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL

Input timing reference level

Output timing reference level

0.8VCC

0.1VCC

0.7VCC

0.2VCC

AC

Measurement

Level

0.5VCC

Note: Input pulse rise and fall time are <5ns

Figure 83. OUTPUT LOADING

25K ohm

DEVICE UNDER

+1.8V

TEST

CL

25K ohm

CL=30pF Including jig capacitance

Figure 84. SCLK TIMING DEFINITION

tCLCH

tCHCL

VIH (Min.)

0.5VCC

VIL (Max.)

tCH

tCL

1/fSCLK

Macronix Proprietary

P/N: PM2705

Rev. 0.00, February 26, 2019

83

ADVANCED INFORMATION

MX25U12843G

Table 20. DC CHARACTERISTICS (Temperature = -40 C to 85 C, VCC = 1.65V - 2.0V)

°

Symbol Parameter

Notes

Min.

Typ.

Max.

Units Test Conditions

VCC = VCC Max,

uA

ILI

Input Load Current

Output Leakage Current

1

±2

70

15

VIN = VCC or GND

VCC = VCC Max,

uA

ILO

1

VOUT = VCC or GND

VIN = VCC or GND,

CS# = VCC

ISB1 VCC Standby Current

15

uA

Deep Power-down

Current

VIN = VCC or GND,

CS# = VCC

ISB2

1.5

uA

f=133MHz, (4 x I/O read)

mA SCLK=0.1VCC/0.9VCC,

SO=Open

25

20

15

f=104MHz, (4 x I/O read)

mA SCLK=0.1VCC/0.9VCC,

SO=Open

ICC1 VCC Read

1

12

f=84MHz,

mA SCLK=0.1VCC/0.9VCC,

SO=Open

VCC Program Current

Program in Progress,

CS# = VCC

ICC2

(PP)

20

10

25

20

mA

VCC Write Status

ICC3

Program status register in

mA

Register (WRSR) Current

progress, CS#=VCC

VCC Sector/Block (32K,

ICC4 64K) Erase Current

(SE/BE/BE32K)

Erase in Progress,

CS#=VCC

1

18

20

25

mA

VCC Chip Erase Current

Erase in Progress,

CS#=VCC

ICC5

(CE)

mA

VIL

VIH

VOL

Input Low Voltage

Input High Voltage

Output Low Voltage

-0.5

0.2VCC

VCC+0.4

0.2

V

0.7VCC

V

IOL = 100uA

IOH = -100uA

VOH Output High Voltage

Notes :

VCC-0.2

1. Typical values at VCC = 1.8V, T = 25 C. These currents are valid for all product versions (package and speeds).

°

2. Typical value is calculated by simulation.

Macronix Proprietary

P/N: PM2705

Rev. 0.00, February 26, 2019

84

ADVANCED INFORMATION

MX25U12843G

Table 21. AC CHARACTERISTICS (Temperature = -40 C to 85 C, VCC = 1.65V - 2.0V)

°

Symbol Alt. Parameter

Min.

D.C.

Typ. Max. Unit

133 MHz

fSCLK

fC Clock Frequency for all commands (except Read)

fR Clock Frequency for READ instructions

fRSCLK

50 MHz

fT Clock Frequency for 2READ/DREAD instructions

MHz

Please refer to "Table 10.

Dummy Cycle and Frequency

Table (MHz)"

fTSCLK

tCH⁽¹⁾

fQ Clock Frequency for 4READ/QREAD instructions

MHz

> 50MHz 45% x (1/fSCLK)

ns

Others

(fSCLK)

tCLH Clock High Time

≤ 50MHz

7

ns

Normal Read (fRSCLK)

> 50MHz 45% x (1/fSCLK)

Others

(fSCLK)

tCL⁽¹⁾

tCLL Clock Low Time

≤ 50MHz

7

ns

Normal Read (fRSCLK)

Clock Rise Time (peak to peak)

Clock Fall Time (peak to peak)

7

0.1

5

ns

V/ns

ns

tCLCH⁽²⁾

tCHCL⁽²⁾

tSLCH tCSS CS# Active Setup Time (relative to SCLK)

tCHSL

CS# Not Active Hold Time (relative to SCLK)

5

ns

tDVCH/

tDVCL

tCHDX/

tCLDX

tDSU Data In Setup Time

2

3

ns

tDH Data In Hold Time

tCHSH

tSHCH

CS# Active Hold Time (relative to SCLK)

CS# Not Active Setup Time (relative to SCLK)

5

7

ns

From Read to next Read

From Write/Erase/Program

to Read Status Register

tSHSL tCSH CS# Deselect Time

30

ns

tSHQZ⁽²⁾tDIS Output Disable Time

8

6

ns

us

Loading: 30pF

Loading: 15pF

Loading: 30pF

Loading: 15pF

Clock Low to Output Valid

tCLQV

tV

Loading: 30pF/15pF

tHO Output Hold Time

Write Protect Setup Time

1

tCLQX

tWHSL⁽³⁾

tSHWL⁽³⁾

tDP⁽²⁾

20

100

10

Write Protect Hold Time

CS# High to Deep Power-down Mode

CS# High to Standby Mode without Electronic Signature

Read

CS# High to Standby Mode with Electronic Signature

Read

Write Status/Conﬁguration Register Cycle Time

Byte-Program

Page Program Cycle Time

tRES1⁽²⁾

30

us

tRES2⁽²⁾

30

40

30

3

tW

tBP

tPP

ms

us

ms

18

0.5

45

tSE

Sector Erase Cycle Time

400 ms

tBE32

tBE

tCE

Block Erase (32KB) Cycle Time

Block Erase (64KB) Cycle Time

Chip Erase Cycle Time

220 1000 ms

450 2000 ms

120

150

s

tQVD⁽⁵⁾

tESL⁽⁶⁾

tPSL⁽⁶⁾

tPRS⁽⁷⁾

tERS⁽⁸⁾

Data Output Valid Time Difference among all SIO pins

Erase Suspend Latency

Program Suspend Latency

Latency between Program Resume and next Suspend

Latency between Erase Resume and next Suspend

600 ps

25

us

0.3

100

Macronix Proprietary

P/N: PM2705

Rev. 0.00, February 26, 2019

85

ADVANCED INFORMATION

MX25U12843G

Notes:

1. tCH + tCL must be greater than or equal to 1/ Frequency.

2. The value guaranteed by characterization, not 100% tested in production.

3. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.

4. Test condition is shown as "Figure 82. DATA INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL" and

"Figure 83. OUTPUT LOADING".

5. Not 100% tested.

6. Latency time is required to complete Erase/Program Suspend operation until WIP bit is "0".

7. For tPRS, minimum timing must be observed before issuing the next program suspend command. However, a

period equal to or longer than the typical timing is required in order for the program operation to make progress.

8. For tERS, minimum timing must be observed before issuing the next erase suspend command. However, a

period equal to or longer than the typical timing is required in order for the erase operation to make progress.

Macronix Proprietary

P/N: PM2705

Rev. 0.00, February 26, 2019

86

ADVANCED INFORMATION

MX25U12843G

13. OPERATING CONDITIONS

At Device Power-Up and Power-Down

AC timing illustrated in "Figure 85. AC Timing at Device Power-Up" and "Figure 86. Power-Down Sequence" are

for the supply voltages and the control signals at device power-up and power-down. If the timing in the ﬁgures is

ignored, the device will not operate correctly.

During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be

selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.

Figure 85. AC Timing at Device Power-Up

VCC(min)

VCC

GND

tVR

tSHSL

CS#

tSHCH

tSLCH

tCHSL

tCHSH

SCLK

tDVCH

tCHCL

tCHDX

tCLCH

MSB IN

LSB IN

SI

High Impedance

SO

Symbol

Parameter

Notes

Min.

Max.

Unit

tVR

VCC Rise Time

1

500000

us/V

Notes:

1. Sampled, not 100% tested.

2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the ﬁgure, please refer to

"Table 21. AC CHARACTERISTICS (Temperature = -40°C to 85°C, VCC = 1.65V - 2.0V)".

Macronix Proprietary

P/N: PM2705

Rev. 0.00, February 26, 2019

87

ADVANCED INFORMATION

MX25U12843G

Figure 86. Power-Down Sequence

During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.

VCC

CS#

SCLK

Figure 87. Power-up Timing

V

CC

V

(max)

CC

Chip Selection is Not Allowed

V

(min)

CC

Device is fully accessible

tVSL

V

WI

time

Macronix Proprietary

P/N: PM2705

Rev. 0.00, February 26, 2019

88

ADVANCED INFORMATION

MX25U12843G

Figure 88. Power Up/Down and Voltage Drop

When powering down the device, VCC must drop below V_PWDfor at least tPWD to ensure the device will initialize

correctly during power up. Please refer to "Figure 88. Power Up/Down and Voltage Drop" and "Table 22. Power-Up/

Down Voltage and Timing" below for more details.

VCC

VCC (max.)

Chip Select is not allowed

VCC (min.)

tVSL

Full Device

Access

Allowed

(max.)

V

PWD

tPWD

Time

Table 22. Power-Up/Down Voltage and Timing

Symbol Parameter

Min.

Max.

Unit

us

V

tVSL

VWI

V_PWD

VCC(min.) to device operation

Write Inhibit Voltage

1200

1.0

1.4

0.9

VCC voltage needed to below V_PWDfor ensuring initialization will occur

V

tPWD The minimum duration for ensuring initialization will occur

VCC VCCPower Supply

300

us

V

1.65

2.0

Note: These parameters are characterized only.

13-1. INITIAL DELIVERY STATE

The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status

Register contains 00h (all Status Register bits are 0).

Macronix Proprietary

P/N: PM2705

Rev. 0.00, February 26, 2019

89

ADVANCED INFORMATION

MX25U12843G

14. ERASE AND PROGRAMMING PERFORMANCE

Parameter

Min.

Typ. ⁽¹⁾

Max. ⁽²⁾

40

Unit

ms

s

Write Status Register Cycle Time

Sector Erase Cycle Time (4KB)

Block Erase Cycle Time (32KB)

Block Erase Cycle Time (64KB)

Chip Erase Cycle Time

45

0.22

0.45

120

400

1

2

s

150

30

s

Byte Program Time (via page program command)

Page Program Time

18

us

0.5

3

ms

cycles

Erase/Program Cycle

100,000

Note:

1. Typical program and erase time assumes the following conditions: 25 C, 1.8V, and checkerboard pattern.

°

2. Under worst conditions of 85 C and 1.65V.

°

3. System-level overhead is the time required to execute the ﬁrst-bus-cycle sequence for the programming

command.

15. ERASE AND PROGRAMMING PERFORMANCE (Factory Mode)

Parameter

Min.

Typ.

20

Max.

Unit

ms

s

Sector Erase Cycle Time (4KB)

Block Erase Cycle Time (32KB)

Block Erase Cycle Time (64KB)

Chip Erase Cycle Time

Page Program Time

0.1

0.2

50

s

0.3

ms

cycles

Erase/Program Cycle

50

Notice:

1. Factory Mode must be operated in 20°C to 45°C and VCC 1.8V-2.0V.

2. In Factory mode, the Erase/Program operation should not exceed 50 cycles, and "ERASE AND PROGRAMMING

PERFORMANCE" 100k cycles will not be affected.

3. During factory mode, Suspend command (75h or B0h) cannot be executed.

Macronix Proprietary

P/N: PM2705

Rev. 0.00, February 26, 2019

90

ADVANCED INFORMATION

MX25U12843G

16. DATA RETENTION

Parameter

Condition

Min.

Max.

Unit

Data retention

55˚C

20

years

17. LATCH-UP CHARACTERISTICS

Min.

Max.

Input Voltage with respect to GND on all power pins

Input Current on all non-power pins

1.5 VCCmax

-100mA

+100mA

Test conditions: VCC = VCCmax, one pin at a time (compliant to JEDEC JDESD78 standard).

Macronix Proprietary

P/N: PM2705

Rev. 0.00, February 26, 2019

91

ADVANCED INFORMATION

MX25U12843G

18. ORDERING INFORMATION

Please contact Macronix regional sales for the latest product selection and available form factors.

PART NO.

MX25U12843GM2I00

MX25U12843GBBI00

TEMPERATURE

PACKAGE

Remark

-40 C to 85 C

8-SOP (200mil)

16-Ball WLCSP

°

-40 C to 85 C

Ball Diameter 0.30mm

°

Macronix Proprietary

P/N: PM2705

Rev. 0.00, February 26, 2019

92

ADVANCED INFORMATION

MX25U12843G

19. PART NAME DESCRIPTION

MX 25 U 12843G M2

I

00

MODEL CODE:

00: STR, x1 I/O enable

TEMPERATURE RANGE:

I: Industrial (-40°C to 85°C)

PACKAGE:

M2: 8-pin SOP (200mil)

BB: 16-WLCSP, Ball Diameter 0.30mm

DENSITY & MODE:

12843G: 128Mb

TYPE:

U: 1.8V

DEVICE:

25: Serial NOR Flash

Macronix Proprietary

P/N: PM2705

Rev. 0.00, February 26, 2019

93

ADVANCED INFORMATION

MX25U12843G

20. PACKAGE INFORMATION

20-1. 8-pin SOP (200mil)

Macronix Proprietary

P/N: PM2705

Rev. 0.00, February 26, 2019

94

ADVANCED INFORMATION

MX25U12843G

20-2. 16-ball WLCSP (Ball Diameter 0.30mm)

CS#

NC

VCC

NC

SO/SIO1 RESET#/SIO3 NC

NC

WP#/SIO2 SCLK

NC

GND

SI/SIO0

Please contact local Macronix sales channel for complete package dimensions.

Macronix Proprietary

P/N: PM2705

Rev. 0.00, February 26, 2019

95

MX25U12843G

Except for customized products which has been expressly identiﬁed in the applicable agreement, Macronix's

products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or

household applications only, and not for use in any applications which may, directly or indirectly, cause death,

personal injury, or severe property damages. In the event Macronix products are used in contradicted to their

target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualiﬁed for its

actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or

distributors shall be released from any and all liability arisen therefrom.

thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, Nbit, Macronix NBit,

HybridNVM, HybridFlash, HybridXFlash, XtraROM, KH Logo, BE-SONOS, KSMC, Kingtech, MXSMIO,

Macronix vEE, RichBook, Rich TV, OctaRAM, OctaBus, OctaFlash, FitCAM, ArmorFlash. The names and

brands of third party referred thereto (if any) are for identiﬁcation purposes only.

For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and speciﬁcations without notice.

96


型号：	MX25U12843GBBI00
厂家：	MACRONIX INTERNATIONAL
描述：	Flash,
文件：	总96页 (文件大小：1163K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MX25U12843GBBI00 [Macronix]

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