MX25U1633FM1I_技术文档

MX25U1633F

1.8V, 16M-BIT [x 1/x 2/x 4]

CMOS MXSMIO^®(SERIAL MULTI I/O)

FLASH MEMORY

Key Features

• 1.65V-2V for Read, Erase and Program Operations

• HOLD feature

• High Voltage Operation (Applied Vhv at WP# pin)

• Multi I/O Support - Single I/O, Dual I/O and Quad I/O

• Program Suspend/Resume & Erase Suspend/Resume

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

1

MX25U1633F

Contents

1. FEATURES ..............................................................................................................................................................4

2. GENERAL DESCRIPTION .....................................................................................................................................5

Table 1. Additional Feature..........................................................................................................................5

3. PIN CONFIGURATIONS .........................................................................................................................................6

4. PIN DESCRIPTION..................................................................................................................................................6

5. BLOCK DIAGRAM...................................................................................................................................................7

6. DATA PROTECTION................................................................................................................................................8

Table 2. Protected Area Sizes.....................................................................................................................9

Table 3. 8K-bit Secured OTP Deﬁnition ....................................................................................................10

7. MEMORY ORGANIZATION................................................................................................................................... 11

Table 4. Memory Organization ..................................................................................................................11

8. DEVICE OPERATION............................................................................................................................................12

9. HOLD FEATURE....................................................................................................................................................14

10. COMMAND DESCRIPTION.................................................................................................................................15

Table 5. Command Set..............................................................................................................................15

10-1. Write Enable (WREN).............................................................................................................................. 18

10-2. Write Disable (WRDI)............................................................................................................................... 19

10-3. Read Identiﬁcation (RDID)....................................................................................................................... 20

10-4. Read Electronic Signature (RES) ............................................................................................................ 21

10-5. Read Electronic Manufacturer ID & Device ID (REMS)........................................................................... 22

10-6. ID Read.................................................................................................................................................... 23

Table 6. ID Deﬁnitions ..............................................................................................................................23

10-7. Read Status Register (RDSR)................................................................................................................. 24

10-8. Read Conﬁguration Register (RDCR)...................................................................................................... 25

Table 7. Status Register............................................................................................................................28

10-9. Write Status Register (WRSR)................................................................................................................. 30

Table 8. Protection Modes.........................................................................................................................31

10-10. Read Data Bytes (READ) ........................................................................................................................ 34

10-11. Read Data Bytes at Higher Speed (FAST_READ) .................................................................................. 35

10-12. Dual Read Mode (DREAD)...................................................................................................................... 36

10-13. 2 x I/O Read Mode (2READ) ................................................................................................................... 37

10-14. Quad Read Mode (QREAD) .................................................................................................................... 38

10-15. 4 x I/O Read Mode (4READ) ................................................................................................................... 39

10-16. Burst Read............................................................................................................................................... 41

10-17. Performance Enhance Mode................................................................................................................... 42

10-18. Sector Erase (SE).................................................................................................................................... 44

10-19. Block Erase (BE32K)............................................................................................................................... 45

10-20. Block Erase (BE) ..................................................................................................................................... 46

10-21. Chip Erase (CE)....................................................................................................................................... 47

10-22. Page Program (PP) ................................................................................................................................. 48

10-23. 4 x I/O Page Program (4PP).................................................................................................................... 49

10-24. Deep Power-down (DP)........................................................................................................................... 50

10-25. Enter Secured OTP (ENSO).................................................................................................................... 51

10-26. Exit Secured OTP (EXSO)....................................................................................................................... 51

10-27. Read Security Register (RDSCUR)......................................................................................................... 51

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

2

MX25U1633F

Table 9. Security Register Deﬁnition .........................................................................................................52

10-28. Write Security Register (WRSCUR)......................................................................................................... 53

10-29. Program Suspend and Erase Suspend ................................................................................................... 54

Table 10. Readable Area of Memory While a Program or Erase Operation is Suspended.......................54

Table 11. Acceptable Commands During Program/Erase Suspend after tPSL/tESL................................54

Table 12. Acceptable Commands During Suspend (tPSL/tESL not required)...........................................55

10-30. Program Resume and Erase Resume..................................................................................................... 56

10-31. No Operation (NOP) ................................................................................................................................ 57

10-32. Software Reset (Reset-Enable (RSTEN) and Reset (RST)) ................................................................... 57

10-33. High Voltage Operation............................................................................................................................ 59

10-34. Read SFDP Mode (RDSFDP).................................................................................................................. 60

11. POWER-ON STATE .............................................................................................................................................61

12. ELECTRICAL SPECIFICATIONS........................................................................................................................62

Table 13. Absolute Maximum Ratings.......................................................................................................62

Table 14. Capacitance...............................................................................................................................62

Table 15. DC Characteristics.....................................................................................................................64

Table 16. AC Characteristics.....................................................................................................................65

13. OPERATING CONDITIONS.................................................................................................................................67

Table 17. Power-Up/Down Voltage and Timing.........................................................................................69

13-1. Initial Delivery State................................................................................................................................. 69

14. ERASE AND PROGRAMMING PERFORMANCE..............................................................................................70

15. LATCH-UP CHARACTERISTICS........................................................................................................................70

16. ORDERING INFORMATION................................................................................................................................71

17. PART NAME DESCRIPTION...............................................................................................................................72

18. PACKAGE INFORMATION..................................................................................................................................73

18-1. 8-land USON (2x3mm) ............................................................................................................................ 73

18-2. 8-pin SOP (200mil) .................................................................................................................................. 74

18-3. 8-pin SOP (150mil) .................................................................................................................................. 75

19. REVISION HISTORY ...........................................................................................................................................76

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

3

MX25U1633F

16M-BIT [x 1/x 2/x 4] CMOS MXSMIO^®(SERIAL MULTI I/O)

FLASH MEMORY

1. FEATURES

GENERAL

Automatically programs and veriﬁes data at

-

•

Supports Serial Peripheral Interface -- Mode 0 and

Mode 3

selected page by an internal algorithm that

automatically times the program pulse widths (Any

page to be programed should have page in the

erased state ﬁrst)

•

16,777,216 x 1 bit structure or 8,388,608 x 2 bits (two

I/O mode) structure or 4,194,304 x 4 bits (four I/O

mode) structure

•

Status Register Feature

Command Reset

Program/Erase Suspend and Program/Erase

Resume

•

Equal Sectors with 4K byte each, Equal Blocks with

32K byte each, or Equal Blocks with 64K byte each

- Any Block can be erased individually

Single Power Supply Operation

- Operation Voltage: 1.65V-2.0V for Read, Erase and

Program Operations

•

Electronic Identiﬁcation

JEDEC 1-byte manufacturer ID and 2-byte device

ID

- RES command for 1-byte Device ID

- REMS command for 1-byte manufacturer ID and

1-byte device ID

-

Latch-up protected to 100mA from -1V to Vcc +1V

PERFORMANCE

•

Support Serial Flash Discoverable Parameters

(SFDP) mode

•

High Performance

- Fast read

- 1 I/O: 80MHz with 8 dummy cycles

- 2 I/O: 80MHz with 4 dummy cycles,

equivalent to 160MHz

Support Unique ID (Please contact local Macronix

sales for detail information)

- 4 I/O: 80MHz with 2+4 dummy cycles,

equivalent to 320MHz

HARDWARE FEATURES

•

SCLK Input

- Fast program and erase time

- 8/16/32/64 byte Wrap-Around Burst Read Mode

Low Power Consumption

Minimum 100,000 erase/program cycles

20 years data retention

- Serial clock input

SI/SIO0

•

- Serial Data Input or Serial Data Input/Output for 2

x I/O read mode and 4 x I/O read mode

SO/SIO1

- Serial Data Output or Serial Data Input/Output for

2 x I/O read mode and 4 x I/O read mode

WP#/SIO2

- Hardware write protection or serial data Input/

Output for 4 x I/O read mode

HOLD#/SIO3

- HOLD feature, to pause the device without

deselecting the device or Serial input & Output for 4

x I/O read mode

•

SOFTWARE FEATURES

•

Input Data Format

- 1-byte Command code

•

Advanced Security Features

- Block lock protection

The BP0-BP3 status bit deﬁnes the size of the area

to be software protection against program and erase

instructions

• Additional 8K bits secured OTP

•

PACKAGE

- 8-land USON (2x3mm)

- Features unique identiﬁer.

- Factory locked identiﬁable and customer lockable

- 8-pin SOP (200mil)

•

Auto Erase and Auto Program Algorithm

- 8-pin SOP (150mil)

Automatically erases and veriﬁes data at selected

sector or block

-

- All devices are RoHS Compliant and Halogen-

free

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

4

MX25U1633F

2. GENERAL DESCRIPTION

MX25U1633F is 16Mb bits Serial NOR Flash memory, which is conﬁgured as 2,097,152 x 8 internally. When it is

in four I/O mode, the structure becomes 4,194,304 bits x 4 or 8,388,608 bits x 2. MX25U1633F features a serial

peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single I/O mode.

The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access

to the device is enabled by CS# input.

When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits

input and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# pin and HOLD# pin become SIO0

pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output.

The MX25U1633F MXSMIO^®(Serial Multi I/O) provides sequential read operation on the whole chip.

After program/erase command is issued, auto program/erase algorithms which program/erase and verify the

speciﬁed page or sector/block locations will be executed. Program command is executed on byte basis, or page (256

bytes) basis, or word basis. Erase command is executed on 4K-byte sector, or 32KB block (32K-byte), or 64K-byte

block, or whole chip basis.

To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read

command can be issued to detect completion status of a program or erase operation via WIP bit.

Advanced security features enhance the protection and security functions, please see security features section for

more details.

The MX25U1633F utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after

100,000 program and erase cycles.

Table 1. Additional Feature

Protection and Security

Flexible Block Protection (BP0-BP3)

8K-bit security OTP

MX25U1633F

V

Fast Read

Performance

MX25U1633F

I/O

1 I/O

8

1I/2O

8

2 I/O

4

1I/4O

8

4 I/O

6

Dummy Cycle

Frequency

80MHz

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

5

MX25U1633F

3. PIN CONFIGURATIONS

8-LAND USON (2x3mm)

4. PIN DESCRIPTION

SYMBOL

DESCRIPTION

CS#

Chip Select

1

2

3

4

VCC

CS#

SO/SIO1

WP#/SIO2

GND

8

7

6

5

Serial Data Input (for 1 x I/O)/ Serial

Data Input & Output (for 4xI/O read

mode)

HOLD#/SIO3

SCLK

SI/SIO0

Serial Data Output (for 1 x I/O)/ Serial

Data Input & Output (for 4xI/O read

mode)

SO/SIO1

SCLK

Clock Input

Write Protection Active Low or Serial

WP#/SIO2 Data Input & Output (for 4xI/O read

mode)

8-PIN SOP (200mil, 150mil)

To pause the device without

HOLD#/SIO3 deselecting the device or Serial Data

Input & Output (for 4xI/O read mode)

1

2

3

4

CS#

SO/SIO1

WP#/SIO2

GND

VCC

8

7

6

5

HOLD#/SIO3

SCLK

VCC

Power Supply

SI/SIO0

GND

Ground

Note:

1. The pin of HOLD#/SIO3 or WP#/SIO2 will remain

internal pull up function while this pin is not

physically connected in system conﬁguration.

However, the internal pull up function will be

disabled if the system has physical connection to

HOLD#/SIO3 or WP#/SIO2 pin.

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

6

MX25U1633F

5. BLOCK DIAGRAM

Address

Generator

Memory Array

Y-Decoder

SI/SIO0

SO/SIO1

SIO2 *

Data

Register

SIO3 *

WP# *

SRAM

Buffer

Sense

Amplifier

HOLD# *

RESET# *

CS#

Mode

Logic

State

Machine

HV

Generator

SCLK

Clock Generator

Output

Buffer

* Depends on part number options.

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

7

MX25U1633F

6. DATA PROTECTION

During power transition, there may be some false system level signals which result in inadvertent erasure or

programming. The device is designed to protect itself from these accidental write cycles.

The state machine will be reset as standby mode automatically during power up. In addition, the control register

architecture of the device constrains that the memory contents can only be changed after speciﬁc command

sequences have completed successfully.

In the following, there are several features to protect the system from the accidental write cycles during VCC power-

up and power-down or from system noise.

•

Power-on reset: to avoid sudden power switch by system power supply transition, the power-on reset may

protect the Flash.

• Valid command length checking: The command length will be checked whether it is at byte base and completed

on byte boundary.

• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before

issuing other commands to change data.

•

Deep Power Down Mode: By entering deep power down mode, the ﬂash device is under protected from writing

all commands except toggling the CS#. For more detail please see "10-24. Deep Power-down (DP)".

Advanced Security Features: there are some protection and security features which protect content from

inadvertent write and hostile access.

I. Block lock protection

- The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected

as read only. The protected area deﬁnition is shown as "Table 2. Protected Area Sizes", the protected areas are

more ﬂexible which may protect various area by setting value of BP0-BP3 bits.

- The Hardware Protected Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and Status

Register Write Protect (SRWD) bit. If the system goes into four I/O mode, the feature of HPM will be disabled.

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

8

MX25U1633F

Table 2. Protected Area Sizes

Protected Area Sizes (TB bit = 0)

Status bit

Protect Level

BP3

0

BP2

0

BP1

0

BP0

0

16Mb

0 (none)

1 (1block, block 31^st)

0

1

0

1

0

2 (2blocks, block 30^th-31^st)

3 (4blocks, block 28^th-31^st)

4 (8blocks, block 24^th-31^st)

5 (16blocks, block 16^th-31^st)

6 (32blocks, protect all)

7 (32blocks, protect all)

8 (32blocks, protect all)

9 (32blocks, protect all)

10 (32blocks, protect all)

11 (32blocks, protect all)

12 (32blocks, protect all)

13 (32blocks, protect all)

14 (32blocks, protect all)

15 (32blocks, protect all)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Protected Area Sizes (TB bit = 1)

Status bit

Protect Level

16Mb

BP3

0

BP2

0

BP1

0

BP0

0

0 (none)

1 (1block, block 0^th)

0

1

0

1

0

2 (2blocks, block 0^th-1^st)

3 (4blocks, block 0^th-3^rd)

4 (8blocks, block 0^th-7^th)

5 (16blocks, block 0^th-15^th)

6 (32blocks, protect all)

7 (32blocks, protect all)

8 (32blocks, protect all)

9 (32blocks, protect all)

10 (32blocks, protect all)

11 (32blocks, protect all)

12 (32blocks, protect all)

13 (32blocks, protect all)

14 (32blocks, protect all)

15 (32blocks, protect all)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Note: The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP3, BP2, BP1,

BP0) are 0.

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

9

MX25U1633F

II. Additional 8K-bit secured OTP for unique identiﬁer: to provide 8K-bit One-Time Program area for setting device

unique serial number - Which may be set by factory or system maker.

The 8K-bit secured OTP area is composed of two rows of 4K-bit. Customer could lock the ﬁrst 4K-bit OTP area

and factory could lock the other.

- Security register bit 0 indicates whether the second 4K-bit is locked by factory or not.

- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register)

command to set customer lock-down bit1 as "1". Please refer to "Table 9. Security Register Deﬁnition" for

security register bit deﬁnition and "Table 3. 8K-bit Secured OTP Deﬁnition" for address range deﬁnition.

- To program 8K-bit secured OTP by entering secured OTP mode (with ENSO command), and going through

normal program procedure, and then exiting secured OTP mode by writing EXSO command.

Note: Once lock-down whatever by factory or customer, the corresponding secured area cannot be changed any

more. While in 8K-bit Secured OTP mode, array access is not allowed.

Table 3. 8K-bit Secured OTP Deﬁnition

Address range

xxx000~xxx1FF

xxx200~xxx3FF

Size

Customer Lock

Determined by customer

N/A

Standard Factory Lock

N/A

4096-bit

Determined by factory

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

10

MX25U1633F

7. MEMORY ORGANIZATION

Table 4. Memory Organization

Block(64K-byte) Block(32K-byte) Sector (4K-byte)

Address Range

511

1FF000h

1FFFFFh

63

504

503

1F8000h

1F7000h

1F8FFFh

1F7FFFh

31

62

61

60

59

58

496

495

1F0000h

1EF000h

1F0FFFh

1EFFFFh

488

487

1E8000h

1E7000h

1E8FFFh

1E7FFFh

30

480

479

1E0000h

1DF000h

1E0FFFh

1DFFFFh

472

471

1D8000h

1D7000h

1D8FFFh

1D7FFFh

29

464

1D0000h

1D0FFFh

47

02F000h

02FFFFh

5

4

3

2

1

0

40

39

028000h

027000h

028FFFh

027FFFh

2

1

32

31

020000h

01F000h

020FFFh

01FFFFh

24

23

018000h

017000h

018FFFh

017FFFh

16

15

010000h

00F000h

010FFFh

00FFFFh

8

7

008000h

007000h

008FFFh

007FFFh

0

000000h

000FFFh

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

11

MX25U1633F

8. DEVICE OPERATION

1. Before a command is issued, status register should be checked to ensure device is ready for the intended

operation.

2. When incorrect command is inputted to this device, it enters standby mode and remains in standby mode until

next CS# falling edge. In standby mode, SO pin of the device is High-Z.

3. When correct command is inputted to this device, it enters active mode and remains in active mode until next

CS# rising edge.

4. Input data is latched on the rising edge of Serial Clock (SCLK) and data shifts out on the falling edge of SCLK.

The difference of Serial mode 0 and mode 3 is shown as "Figure 1. Serial Modes Supported".

5. For the following instructions: RDID, RDSR, RDCR, RDSCUR, READ, FAST_READ, DREAD, 2READ, 4READ,

QREAD, RDSFDP, RES, REMS, the shifted-in instruction sequence is followed by a data-out sequence. After

any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE,

BE, BE32K, CE, PP, 4PP, DP, ENSO, EXSO, WRSCUR, SUSPEND, RESUME, NOP, RSTEN, RST, the CS#

must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.

6. While a Write Status Register, Program or Erase operation is in progress, access to the memory array is

neglected and will not affect the current operation of Write Status Register, Program, Erase.

Figure 1. Serial Modes Supported

CPOL CPHA

shift in

shift out

SCLK

(Serial mode 0)

(Serial mode 3)

0

1

0

1

SI

MSB

SO

MSB

Note:

CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not

transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is

supported.

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

12

MX25U1633F

Figure 2. Serial Input Timing

tSHSL

tSHCH

tCHCL

CS#

tCHSL

tSLCH

tCHSH

SCLK

tDVCH

tCHDX

tCLCH

MSB

LSB

SI

High-Z

SO

Figure 3. Output Timing

CS#

tCH

SCLK

tCLQV

tCL

tSHQZ

tCLQX

SO

tCLQX

LSB

ADDR.LSB IN

SI

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

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MX25U1633F

9. HOLD FEATURE

HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the

operation of write status register, programming, or erasing in progress.

The operation of HOLD requires Chip Select (CS#) keeping low and starts on falling edge of HOLD# pin signal

while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start

until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Serial

Clock(SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not end until Serial

Clock being low).

Figure 4. Hold Condition Operation

CS#

SCLK

HOLD#

SI/SIO0

Don’t care

Valid Data

Don’t care

Bit 6

Valid Data

SO/SIO1

(internal)

Bit 7

Bit 5

SO/SIO1

(External)

High_Z

Bit 7

Bit 6

Bit 5

Bit 6

Bit 7

CS#

SCLK

HOLD#

SI/SIO0

Don’t care

Valid Data

Don’t care

Valid Data

SO/SIO1

(internal)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

SO/SIO1

(External)

High_Z

Bit 6

Bit 4

Bit 7

During the HOLD operation, the Serial Data Output (SO) is high impedance when Hold# pin goes low and will keep

high impedance until Hold# pin goes high. The Serial Data Input (SI) is don't care if both Serial Clock (SCLK) and

Hold# pin goes low and will keep the state until SCLK goes low and Hold# pin goes high. If Chip Select (CS#) drives

high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the

HOLD# must be at high and CS# must be at low.

Note: The HOLD feature is disabled during Quad I/O mode.

Macronix Proprietary

P/N: PM2437

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MX25U1633F

10. COMMAND DESCRIPTION

Table 5. Command Set

Read/Write Array Commands

I/O

1

2

4

2READ

(2 x I/O read

command)

DREAD

(1I / 2O read

command)

Command

(byte)

READ

FAST READ

4READ

(4 x I/O read)

QREAD

(1I/4O read)

(normal read) (fast read data)

1st byte

2nd byte

3rd byte

4th byte

5th byte

03 (hex)

ADD1

ADD2

ADD3

0B (hex)

ADD1

BB (hex)

ADD1

3B (hex)

ADD1

EB (hex)

ADD1

6B (hex)

ADD1

ADD2

ADD3

Dummy

n bytes read

Dummy

n bytes read

Dummy

n bytes read

out until CS# out until CS# out by 2 x I/O

goes high goes high

n bytes read Quad I/O read n bytes read

out by Dual with 6 dummy out by Quad

until CS# goes Output until

cycles

output until

Action

high

CS# goes high

Mode

1

4

1

4PP

(quad page

program)

BE 32K

(block erase

32KB)

BE

Command

(byte)

PP

SE

CE

(chip erase)

RDSFDP

(Read SFDP)

(block erase

64KB)

(page program)

(sector erase)

1st byte

2nd byte

3rd byte

4th byte

5th byte

02 (hex)

ADD1

ADD2

ADD3

38 (hex)

ADD1

ADD2

ADD3

20 (hex)

ADD1

ADD2

ADD3

52 (hex)

ADD1

ADD2

ADD3

D8 (hex)

ADD1

60 or C7 (hex)

5A (hex)

ADD1

ADD2

ADD3

Dummy

to program the quad input to

to erase the

to erase the to erase whole Read SFDP

selected page program the selected sector selected 32KB selected block

chip

mode

selected page

block

Action

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

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MX25U1633F

Register/Setting Commands

PGM/ERS

Suspend

(Suspends

RDSR

(read status

register)

RDCR (read

conﬁguration

register)

WRSR

(write status

register)

Command

(byte)

WREN

(write enable)

WRDI

(write disable)

Program/Erase)

1st byte

2nd byte

3rd byte

4th byte

5th byte

06 (hex)

04 (hex)

05 (hex)

15 (hex)

01 (hex)

Values

75 or B0 (hex)

sets the (WEL) resets the (WEL) to read out the

to read out the

values of the

conﬁguration

register

to write new

values of the

conﬁguration/

status register

program/erase

operation is

interrupted

by suspend

command

write enable latch write enable latch

values of the

bit

status register

Action

PGM/ERS

Resume

(Resumes

DP

Command

(byte)

SBL

(Deep power

down)

(Set Burst Length)

Program/Erase)

1st byte

2nd byte

3rd byte

4th byte

5th byte

7A or 30 (hex)

B9 (hex)

C0 (hex)

Value

to continue

performing the

suspended

enters deep

power down

mode

to set Burst length

Action

program/erase

sequence

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

16

MX25U1633F

ID/Reset Commands

REMS (read

electronic

RDID

(read identiﬁc-

RDSCUR

(read security (write security

WRSCUR

Command

(byte)

RES (read

ENSO (enter EXSO (exit

electronic ID) manufacturer secured OTP) secured OTP)

& device ID)

ation)

register)

2B (hex)

register)

2F (hex)

1st byte

2nd byte

3rd byte

4th byte

5th byte

9F (hex)

AB (hex)

90 (hex)

B1 (hex)

C1 (hex)

x

ADD^{(Note 1)}

outputs JEDEC to read out

output the

to enter the

to exit the

to read value to set the lock-

ID: 1-byte

Manufacturer

ID & 2-byte

Device ID

1-byte Device Manufacturer 8K-bit secured 8K-bit secured of security

down bit as

"1" (once lock-

down, cannot

be update)

ID

ID & Device ID OTP mode

OTP mode

register

Action

RST

(Reset

Memory)

COMMAND

(byte)

NOP

RSTEN

(No Operation) (Reset Enable)

1st byte

2nd byte

3rd byte

4th byte

5th byte

00 (hex) 66 (hex)

99 (hex)

Action

(Note 3)

Note 1: ADD=00H will output the manufacturer ID ﬁrst and ADD=01H will output device ID ﬁrst.

Note 2: It is not recommended to adopt any other code not in the command deﬁnition table, which will potentially enter the

hidden mode.

Note 3: The RSTEN command must be executed before executing the RST command. If any other command is issued

in-between RSTEN and RST, the RST command will be ignored.

Macronix Proprietary

P/N: PM2437

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MX25U1633F

10-1. Write Enable (WREN)

The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP,

SE, BE32K, BE, CE, and WRSR, which are intended to change the device content WEL bit should be set every time

after the WREN instruction setting the WEL bit.

The sequence of issuing WREN instruction is: CS# goes low→sending WREN instruction code→ CS# goes high.

The SIO[3:1] are "don't care" .

Figure 5. Write Enable (WREN) Sequence

CS#

0

1

2

3

4

5

6

7

Mode 3

Mode 0

SCLK

Command

06h

SI

High-Z

SO

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

18

MX25U1633F

10-2. Write Disable (WRDI)

The Write Disable (WRDI) instruction is to reset Write Enable Latch (WEL) bit.

The sequence of issuing WRDI instruction is: CS# goes low→sending WRDI instruction code→CS# goes high.

The SIO[3:1] are "don't care".

The WEL bit is reset by following situations:

- Power-up

- Reset# pin driven low

- Completion of Write Disable (WRDI) instruction

- Completion of Write Status Register (WRSR) instruction

- Completion of Page Program (PP) instruction

- Completion of Quad Page Program (4PP) instruction

- Completion of Sector Erase (SE) instruction

- Completion of Block Erase 32KB (BE32K) instruction

- Completion of Block Erase (BE) instruction

- Completion of Chip Erase (CE) instruction

- Program/Erase Suspend

- Completion of Softreset command

- Completion of Write Security Register (WRSCUR) command

Figure 6. Write Disable (WRDI) Sequence

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

SCLK

Command

04h

SI

High-Z

SO

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

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MX25U1633F

10-3. Read Identiﬁcation (RDID)

The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Macronix

Manufacturer ID and Device ID are listed as "Table 6. ID Deﬁnitions".

The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code→24-bits ID data out

on SO→ to end RDID operation can drive CS# to high at any time during data out.

While Program/Erase operation is in progress, it will not decode the RDID instruction, therefore there's no effect on

the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby

stage.

Figure 7. Read Identiﬁcation (RDID) Sequence

CS#

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18

28 29 30 31

Mode 3

Mode 0

SCLK

SI

Command

9Fh

Manufacturer Identification

Device Identification

High-Z

SO

7

6

5

3

2

1

0

15 14 13

MSB

3

2

1

0

MSB

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

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MX25U1633F

10-4. Read Electronic Signature (RES)

RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as "Table 6.

ID Deﬁnitions". This is not the same as RDID instruction. It is not recommended to use for new design. For new

design, please use RDID instruction.

The SIO[3:1] are "don't care".

The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly

if continuously send the additional clock cycles on SCLK while CS# is at low.

Figure 8. Read Electronic Signature (RES) Sequence

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38

SCLK

Command

ABh

3 Dummy Bytes

SI

23 22 21

MSB

3

2

1

0

Electronic Signature Out

High-Z

7

6

5

4

3

2

0

1

SO

MSB

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

21

MX25U1633F

10-5. Read Electronic Manufacturer ID & Device ID (REMS)

The REMS instruction returns both the JEDEC assigned manufacturer ID and the device ID. The Device ID values

are listed in "Table 6. ID Deﬁnitions".

The REMS instruction is initiated by driving the CS# pin low and sending the instruction code "90h" followed by two

dummy bytes and one address byte (A7~A0). After which the manufacturer ID for Macronix (C2h) and the device

ID are shifted out on the falling edge of SCLK with the most signiﬁcant bit (MSB) ﬁrst. If the address byte is 00h,

the manufacturer ID will be output ﬁrst, followed by the device ID. If the address byte is 01h, then the device ID will

be output ﬁrst, followed by the manufacturer ID. While CS# is low, the manufacturer and device IDs can be read

continuously, alternating from one to the other. The instruction is completed by driving CS# high.

Figure 9. Read Electronic Manufacturer & Device ID (REMS) Sequence

CS#

0

1

2

3

4

5

6

7

8

9 10

Mode 3

Mode 0

SCLK

Command

90h

2 Dummy Bytes

SI

15 14 13

3

2

1

0

High-Z

SO

CS#

47

28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

SCLK

ADD (1)

7

6

5

4

3

2

0

1

SI

Manufacturer ID

Device ID

7

6

5

4

3

2

1

0

7

6

5

4

3

2

0

1

SO

MSB

Notes:

(1) ADD=00H will output the manufacturer's ID ﬁrst and ADD=01H will output device ID ﬁrst.

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

22

MX25U1633F

10-6. ID Read

User can execute this ID Read instruction to identify the Device ID and Manufacturer ID. The sequence of issuing

RDID instruction is: CS# goes low→ sending RDID instruction code→24-bits ID data out on SO→ to end RDID

operation can drive CS# to high at any time during data out.

After the command cycle, the device will immediately output data on the falling edge of SCLK. The manufacturer ID,

memory type, and device ID data byte will be output continuously, until the CS# goes high.

While Program/Erase operation is in progress, it will not decode the RDID instruction, therefore there's no effect on

the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby

stage.

Table 6. ID Deﬁnitions

Command Type

MX25U1633F

Manufacturer ID

C2

Memory type

Memory density

35

RDID

25

Electronic ID

35

RES

Manufacturer ID

C2

Device ID

35

REMS

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

23

MX25U1633F

10-7. Read Status Register (RDSR)

The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even

in program/erase/write status register condition). It is recommended to check the Write in Progress (WIP) bit before

sending a new instruction when a program, erase, or write status register operation is in progress.

The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register data

out on SO.

The SIO[3:1] are "don't care".

Figure 10. Read Status Register (RDSR) Sequence

CS#

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

Mode 3

Mode 0

SCLK

SI

command

05h

Status Register Out

High-Z

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

MSB

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

24

MX25U1633F

10-8. Read Conﬁguration Register (RDCR)

The RDCR instruction is for reading Conﬁguration Register Bits. The Read Conﬁguration Register can be read

at any time (even in program/erase/write conﬁguration register condition). It is recommended to check the Write

in Progress (WIP) bit before sending a new instruction when a program, erase, or write conﬁguration register

operation is in progress.

The sequence of issuing RDCR instruction is: CS# goes low→ sending RDCR instruction code→ Conﬁguration

Register data out on SO.

The SIO[3:1] are don't care.

Figure 11. Read Conﬁguration Register (RDCR) Sequence

CS#

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

Mode 3

Mode 0

SCLK

SI

command

15h

Configuration register Out

High-Z

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

MSB

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

25

MX25U1633F

For user to check if Program/Erase operation is ﬁnished or not, RDSR instruction ﬂow are shown as follows:

Figure 12. Program/Erase ﬂow with read array data

start

WREN command

RDSR command*

No

WEL=1?

Yes

Program/erase command

Write program data/address

(Write erase address)

RDSR command

No

WIP=0?

Yes

RDSR command

Read WEL=0, BP[3:0], QE,

and SRWD data

Read array data

(same address of PGM/ERS)

No

Verify OK?

Yes

Program/erase successfully

Program/erase fail

Yes

Program/erase

another block?

* Issue RDSR to check BP[3:0].

No

Program/erase completed

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

26

MX25U1633F

Figure 13. Program/Erase ﬂow without read array data (read P_FAIL/E_FAIL ﬂag)

start

WREN command

RDSR command*

No

WEL=1?

Yes

Program/erase command

Write program data/address

(Write erase address)

RDSR command

No

WIP=0?

Yes

RDSR command

Read WEL=0, BP[3:0], QE,

and SRWD data

RDSCUR command

P_FAIL/E_FAIL =1 ?

Yes

No

Program/erase successfully

Program/erase fail

Yes

Program/erase

another block?

* Issue RDSR to check BP[3:0].

No

Program/erase completed

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

27

MX25U1633F

Status Register

The deﬁnition of the status register bits is as below:

WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write

status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status

register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status

register cycle.

WEL bit. The Write Enable Latch (WEL) bit is a volatile bit that is set to “1” by the WREN instruction. WEL needs to be

set to “1” before the device can accept program and erase instructions, otherwise the program and erase instructions

are ignored. WEL automatically clears to “0” when a program or erase operation completes. To ensure that both WIP

and WEL are “0” and the device is ready for the next program or erase operation, it is recommended that WIP be

conﬁrmed to be “0” before checking that WEL is also “0”. If a program or erase instruction is applied to a protected

memory area, the instruction will be ignored and WEL will clear to “0”.

BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area (as

deﬁned in "Table 2. Protected Area Sizes") of the device to against the program/erase instruction without hardware

protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR)

instruction to be executed. Those bits deﬁne the protected area of the memory to against Page Program (PP), Sector

Erase (SE), Block Erase (BE/BE32K) and Chip Erase (CE) instructions (only if Block Protect bits (BP3:BP0) set to 0,

the CE instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default, which is un-protected.

QE bit. The Quad Enable (QE) bit is a non-volatile bit with a factory default of “0”. When QE is “0”, Quad mode

commands are ignored; pins WP#/SIO2 and HOLD#/SIO3 function as WP# and HOLD#, respectively. When QE is

“1”, Quad mode is enabled and Quad mode commands are supported along with Single and Dual mode commands.

Pins WP#/SIO2 and HOLD#/SIO3 function as SIO2 and SIO3, respectively, and their alternate pin functions are

disabled. Enabling Quad mode also disables the HPM and HOLD features.

SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection

(WP#/SIO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and

WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is

no longer accepted for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only. The

SRWD bit defaults to be "0".

Table 7. Status Register

bit7

bit6

bit5

BP3

(level of

protected

block)

bit4

BP2

(level of

protected

block)

bit3

BP1

(level of

protected

block)

bit2

BP0

(level of

protected

block)

bit1

bit0

SRWD (status

register write

protect)

QE

(Quad

Enable)

WEL

(write enable

latch)

WIP

(write in

progress bit)

1=status

register write

disabled

0=status

register write

enabled

1=Quad

Enable

0=not Quad

Enable

1=write

enable

0=not write 0=not in write

1=write

operation

(note 1)

enable

operation

Non-volatile Non-volatile Non-volatile Non-volatile Non-volatile

Non-volatile bit

volatile bit

bit

Note 1: Please refer to the "Table 2. Protected Area Sizes".

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

28

MX25U1633F

Conﬁguration Register

The Conﬁguration Register is able to change the default status of Flash memory. Flash memory will be conﬁgured

after the CR bit is set.

TB bit

The Top/Bottom (TB) bit is a non-volatile OTP bit. The Top/Bottom (TB) bit is used to conﬁgure the Block Protect

area by BP bit (BP3, BP2, BP1, BP0), starting from TOP or Bottom of the memory array. The TB bit is defaulted as

“0”, which means Top area protect. When it is set as “1”, the protect area will change to Bottom area of the memory

device. To write the TB bit requires the Write Status Register (WRSR) instruction to be executed.

Conﬁguration Register

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

TB

DC

Reserved

(Dummy

Cycle)

Reserved

(top/bottom

selected)

0=Top area

protect

1=Bottom

area protect

(Default=0)

OTP

Reserved

2READ/

4READ

Dummy

Cycle

x

Volatile bit

Dummy Cycle Table

Numbers of Dummy

Cycles

DC

0 (default)

4

8

2READ

4READ

1

0 (default)

1

6

10

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

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MX25U1633F

10-9. Write Status Register (WRSR)

The WRSR instruction is for changing the values of Status Register Bits and Conﬁguration Register Bits. Before

sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write

Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2,

BP1, BP0) bits to deﬁne the protected area of memory (as shown in "Table 2. Protected Area Sizes"). The WRSR

also can set or reset the Quad enable (QE) bit and set or reset the Status Register Write Disable (SRWD) bit in

accordance with Write Protection (WP#/SIO2) pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of the status

register. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered.

The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register

data on SI→CS# goes high.

The CS# must go high exactly at the 8 bits or 16 bits data boundary; otherwise, the instruction will be rejected and

not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes

high. The Write in Progress (WIP) bit still can be checked during the Write Status Register cycle is in progress. The

WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable

Latch (WEL) bit is reset. For more detail please check "Table 16. AC Characteristics".

Figure 14. Write Status Register (WRSR) Sequence

CS#

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Mode 3

Mode 0

SCLK

command

01h

Status

Register In

Configuration

Register In

SI

4

15 14

13

12 11

10 9

8

2

1

0

7

6

5

3

MSB

High-Z

SO

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

30

MX25U1633F

Software Protected Mode (SPM):

-

When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can

change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is deﬁned by BP3, BP2, BP1,

BP0, is at software protected mode (SPM).

-

When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values

of SRWD, BP3, BP2, BP1, BP0. The protected area, which is deﬁned by BP3, BP2, BP1, BP0, is at software

protected mode (SPM)

Note:

If SRWD bit=1 but WP#/SIO2 is low, it is impossible to write the Status Register even if the WEL bit has previously

been set. It is rejected to write the Status Register and not be executed.

Hardware Protected Mode (HPM):

-

When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware

protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2,

BP1, BP0 and hardware protected mode by the WP#/SIO2 to against data modiﬁcation.

Note:

To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered.

If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be entered; only can

use software protected mode via BP3, BP2, BP1, BP0.

Table 8. Protection Modes

Mode

Status register condition

WP# and SRWD bit status

Memory

Status register can be written

in (WEL bit is set to "1") and

the SRWD, BP0-BP3

Software protection

mode (SPM)

WP#=1 and SRWD bit=0, or

WP#=0 and SRWD bit=0, or

WP#=1 and SRWD=1

The protected area

cannot

be program or erase.

bits can be changed

The SRWD, BP0-BP3 of

status register bits cannot be

changed

The protected area

cannot

be program or erase.

Hardware protection

mode (HPM)

WP#=0, SRWD bit=1

Note:

1. As deﬁned by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in

"Table 2. Protected Area Sizes".

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

31

MX25U1633F

Figure 15. WRSR ﬂow

start

WREN command

RDSR command

No

WEL=1?

Yes

WRSR command

Write status register

data

RDSR command

No

WIP=0?

Yes

RDSR command

Read WEL=0, BP[3:0], QE,

and SRWD data

No

Verify OK?

Yes

WRSR successfully

WRSR fail

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

32

MX25U1633F

Figure 16. WP# Setup Timing and Hold Timing during WRSR when SRWD=1

WP#

CS#

tSHWL

tWHSL

0

1

2

3

4

5

6

7

8

9

10 11 12

13 14

15

SCLK

01h

SI

High-Z

SO

Note: WP# must be kept high until the embedded operation ﬁnish.

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

33

MX25U1633F

10-10. Read Data Bytes (READ)

The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on

the falling edge of SCLK at a maximum frequency fR. The ﬁrst address byte can be at any location. The address

is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can

be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been

reached.

The sequence of issuing READ instruction is: CS# goes low→sending READ instruction code→ 3-byte address on

SI→ data out on SO→to end READ operation can use CS# to high at any time during data out.

Figure 17. Read Data Bytes (READ) Sequence

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38 39

SCLK

command

03h

24-Bit Address

23 22 21

MSB

3

2

1

0

SI

Data Out 1

Data Out 2

High-Z

2

7

6

5

4

3

1

7

0

SO

MSB

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

34

MX25U1633F

10-11.Read Data Bytes at Higher Speed (FAST_READ)

The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and

data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The ﬁrst address byte can be at

any location. The address is automatically increased to the next higher address after each byte data is shifted out,

so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when

the highest address has been reached.

The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code→

3-byte address on SI→1-dummy byte (default) address on SI→ data out on SO→ to end FAST_READ operation

can use CS# to high at any time during data out.

While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any

impact on the Program/Erase/Write Status Register current cycle.

Figure 18. Read at Higher Speed (FAST_READ) Sequence

CS#

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31

Mode 3

Mode 0

SCLK

Command

0Bh

24-Bit Address

SI

23 22 21

3

2

1

0

High-Z

SO

CS#

47

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

SCLK

Dummy Cycle

7

6

5

4

3

2

0

1

SI

DATA OUT 2

DATA OUT 1

7

6

5

4

3

2

1

0

7

6

5

4

3

2

0

1

SO

MSB

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

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MX25U1633F

10-12. Dual Read Mode (DREAD)

The DREAD instruction enable double throughput of Serial NOR Flash in read mode. The address is latched on

rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at

a maximum frequency fT. The ﬁrst address byte can be at any location. The address is automatically increased

to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single

DREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once

writing DREAD instruction, the following data out will perform as 2-bit instead of previous 1-bit.

The sequence of issuing DREAD instruction is: CS# goes low

sending DREAD instruction

3-byte address

→

on SI

8-bit dummy cycle

data out interleave on SIO1 & SIO0

to end DREAD operation can use CS# to

→

high at any time during data out.

While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any

impact on the Program/Erase/Write Status Register current cycle.

Figure 19. Dual Read Mode (DREAD) Sequence

CS#

30 31 32

39 40 41 42 43 44 45

0

1

2

3

4

5

6

7

8

9

SCLK

…

Data Out

1

8 dummy

cycle

Command

24 ADD Cycle

2

…

A23 A22

A1 A0

D4 D2

D6 D4

D7 D5

3B

D6

D7

D0

SI/SIO0

High Impedance

D1

D5 D3

SO/SIO1

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

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MX25U1633F

10-13. 2 x I/O Read Mode (2READ)

The 2READ instruction enables Double Transfer Rate of Serial NOR Flash in read mode. The address is latched

on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of

SCLK at a maximum frequency fT. The ﬁrst address byte can be at any location. The address is automatically

increased to the next higher address after each byte data is shifted out, so the whole memory can be read out

at a single 2READ instruction. The address counter rolls over to 0 when the highest address has been reached.

Once writing 2READ instruction, the following address/dummy/data out will perform as 2-bit instead of previous

1-bit.

The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 24-bit address

interleave on SIO1 & SIO0→ 4-bit dummy cycle on SIO1 & SIO0→ data out interleave on SIO1 & SIO0→ to end

2READ operation can use CS# to high at any time during data out.

While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any

impact on the Program/Erase/Write Status Register current cycle.

Figure 20. 2 x I/O Read Mode (2READ) Sequence

CS#

28 29

18 19 20 21 22 23 24 25 26 27

0

1

2

3

4

5

6

7

8

9

SCLK

…

Data Out

4 dummy

cycle

Command

12 ADD Cycle

2

1

…

A22 A20

A23 A21

A2 A0

P0

D4 D2

D6 D4

D7 D5

P2

BB(hex)

D6

D7

D0

D1

SI/SIO0

High Impedance

…

A3 A1 P3

P1

D5 D3

SO/SIO1

Note: SI/SIO0 or SO/SIO1 should be kept "0h" or "Fh" in the ﬁrst two dummy cycles. In other words, P2=P0 or

P3=P1 is necessary.

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

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MX25U1633F

10-14. Quad Read Mode (QREAD)

The QREAD instruction enable quad throughput of Serial NOR Flash in read mode. A Quad Enable (QE) bit of

status Register must be set to "1" before sending the QREAD instruction. The address is latched on rising edge

of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum

frequency fQ. The ﬁrst address byte can be at any location. The address is automatically increased to the next

higher address after each byte data is shifted out, so the whole memory can be read out at a single QREAD

instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing

QREAD instruction, the following data out will perform as 4-bit instead of previous 1-bit.

The sequence of issuing QREAD instruction is: CS# goes low

sending QREAD instruction → 3-byte address

→

on SI

8-bit dummy cycle

data out interleave on SIO3, SIO2, SIO1 & SIO0

to end QREAD operation can

→

use CS# to high at any time during data out.

While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any

impact on the Program/Erase/Write Status Register current cycle.

Figure 21. Quad Read Mode (QREAD) Sequence

CS#

29 30 31 32 33

38 39 40 41 42

0

1

2

3

4

5

6

7

8

9

SCLK

…

Data

Out 2

Data

Out 3

Command

6B

8 dummy cycles

24 ADD Cycles

Data

Out 1

…

A23A22

A2 A1 A0

D4 D0 D4 D0 D4

SI/SIO0

SO/SIO1

SIO2

High Impedance

D5 D1 D5 D1 D5

D6 D2 D6 D2 D6

SIO3

D7 D3 D7 D3 D7

Macronix Proprietary

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38

MX25U1633F

10-15. 4 x I/O Read Mode (4READ)

The 4READ instruction enable quad throughput of Serial NOR Flash in read mode. A Quad Enable (QE) bit of status

Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCLK,

and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency

fQ. The ﬁrst address byte can be at any location. The address is automatically increased to the next higher address

after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address

counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following

address/dummy/data out will perform as 4-bit instead of previous 1-bit.

The sequence of issuing 4READ instruction is: CS# goes low

sending 4READ instruction

24-bit address

→

interleave on SIO3, SIO2, SIO1 & SIO0 2+4 dummy cycles data out interleave on SIO3, SIO2, SIO1 & SIO0 to

→

end 4READ operation can use CS# to high at any time during data out.

Another sequence of issuing 4READ instruction especially useful in random access is : CS# goes low sending

→

4READ instruction 3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 performance enhance toggling

→

bit P[7:0] 4 dummy cycles data out still CS# goes high

CS# goes low (reduce 4READ instruction) 24-bit

→

random access address.

In the performance-enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh

can make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0];

likewise P[7:0]=FFh,00h,AAh or 55h and afterwards CS# is raised and then lowered, the system then will escape

from performance enhance mode and return to normal operation.

While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact

on the Program/Erase/Write Status Register current cycle.

Macronix Proprietary

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Rev. 1.1, February 23, 2018

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MX25U1633F

Figure 22. 4 x I/O Read Mode Sequence

CS#

23 24

10 11 12 13 14 15 16 17 18 19 20 21 22

Mode 3

Mode 0

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

SCLK

Data

Out 1

Data

Out 2 Out 3

Data

4 Dummy

Cycles

Command

EBh

6 ADD Cycles

Performance

enhance

indicator (Note)

A20 A16 A12 A8 A4 A0

D4 D0 D4 D0 D4 D0

P4 P0

SIO0

SIO1

SIO2

SIO3

A21 A17 A13 A9 A5 A1

A22 A18 A14 A10 A6 A2

D5 D1 D5 D1 D5 D1

D6 D2 D6 D2 D6 D2

P5 P1

P6 P2

A23 A19 A15 A11 A7 A3

D7 D3 D7 D3 D7 D3

P7 P3

Note:

1. Hi-impedance is inhibited for the two clock cycles.

2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited.

Macronix Proprietary

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Rev. 1.1, February 23, 2018

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MX25U1633F

10-16. Burst Read

This device supports Burst Read.

To set the Burst length, following command operation is required

Issuing command: “C0h” in the ﬁrst Byte (8-clocks), following 4 clocks deﬁning wrap around enable with “0h” and

disable with“1h”.

Next 4 clocks is to deﬁne wrap around depth. Deﬁnition as following table:

Data

00h

01h

02h

03h

1xh

Wrap Around

Wrap Depth

8-byte

Yes

No

16-byte

32-byte

64-byte

X

The wrap around unit is deﬁned within the 256Byte page, with random initial address. It’s deﬁned as “wrap-around

mode disable” for the default state of the device. To exit wrap around, it is required to issue another “C0h” command

in which data=‘1xh”. Otherwise, wrap around status will be retained until power down or reset command. To change

wrap around depth, it is requried to issue another “C0h” command in which data=“0xh”. “EBh” supports wrap around

feature after wrap around enable. The device is default without Burst read.

Figure 23. Burst Read

CS#

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Mode 3

Mode 0

SCLK

SIO

D7

D6

D5

D4

D3

D2

D1

D0

C0h

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Rev. 1.1, February 23, 2018

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MX25U1633F

10-17. Performance Enhance Mode

The device could waive the command cycle bits if the two cycle bits after address cycle toggles.

“EBh” command supports enhance mode. The performance enhance mode is not supported in dual I/O mode.

After entering enhance mode, following CS# go high, the device will stay in the read mode and treat CS# go low of

the ﬁrst clock as address instead of command cycle.

To exit enhance mode, a new fast read command whose ﬁrst two dummy cycles is not toggle then exit. Or issue

”FFh” command to exit enhance mode.

Notice: Performance Enhance can only be operated in high performance mode.

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

42

MX25U1633F

Figure 24. 4 x I/O Read Performance Enhance Mode Sequence

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22

n

SCLK

Data

Out 1

Data

Out 2

Data

Out n

4 Dummy

Cycles

Command

EBh

6 ADD Cycles

Performance

enhance

indicator (Note)

P4 P0

D4 D0 D4 D0

D4 D0

A20 A16 A12 A8 A4 A0

SIO0

SIO1

SIO2

SIO3

A21 A17 A13 A9 A5 A1

A22 A18 A14 A10 A6 A2

D5 D1 D5 D1

D6 D2 D6 D2

D5 D1

D6 D2

P5 P1

P6 P2

A23 A19 A15 A11 A7 A3

D7 D3 D7 D3

D7 D3

P7 P3

CS#

n+1

...........

n+7......n+9 ........... n+13

...........

Mode 3

Mode 0

SCLK

4 Dummy

Cycles

Data

Out 1

Data

Out 2

Data

Out n

6 ADD Cycles

Performance

enhance

indicator (Note)

D4 D0 D4 D0

D4 D0

P4 P0

A20 A16 A12 A8 A4 A0

SIO0

SIO1

SIO2

SIO3

D5 D1 D5 D1

D6 D2 D6 D2

D5 D1

D6 D2

A21 A17 A13 A9 A5 A1

A22 A18 A14 A10 A6 A2

P5 P1

P6 P2

D7 D3 D7 D3

D7 D3

A23 A19 A15 A11 A7 A3

P7 P3

Note:

1. Performance enhance mode, if P7≠P3 & P6≠P2 & P5≠P1 & P4≠P0 (Toggling), ex: A5, 5A, 0F, if not using

performance enhance recommend to keep 1 or 0 in performance enhance indicator.

2. Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

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MX25U1633F

10-18. Sector Erase (SE)

The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used

for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit

before sending the Sector Erase (SE). Any address of the sector (Please refer to "Table 4. Memory Organization")

is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the latest

eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed.

Address bits [Am-A12] (Am is the most signiﬁcant address) select the sector address.

The sequence of issuing SE instruction is: CS# goes low→ sending SE instruction code→ 3-byte address on SI→

CS# goes high.

The SIO[3:1] are "don't care".

The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in

Progress (WIP) bit still can be checked during the Sector Erase cycle is in progress. The WIP sets 1 during the

tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If

the sector is protected by BP3, BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the

sector.

Figure 25. Sector Erase (SE) Sequence

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

29 30 31

SCLK

24-Bit Address

Command

20h

SI

23 22

MSB

2

1

0

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

44

MX25U1633F

10-19. Block Erase (BE32K)

The Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1". The instruction is used

for 32K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable

Latch (WEL) bit before sending the Block Erase (BE32K). Any address of the block (see "Table 4. Memory

Organization") is a valid address for Block Erase (BE32K) instruction. The CS# must go high exactly at the byte

boundary (the least signiﬁcant bit of address byte has been latched-in); otherwise, the instruction will be rejected

and not executed.

The sequence of issuing BE32K instruction is: CS# goes low → sending BE32K instruction code → 3-byte

address on SI → CS# goes high.

The SIO[3:1] are don't care.

The self-timed Block Erase Cycle time (tBE32K) is initiated as soon as Chip Select (CS#) goes high. The Write

in Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during

the tBE32K timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is

cleared. If the block is protected by BP3~0, the array data will be protected (no change) and the WEL bit still be

reset.

Figure 26. Block Erase 32KB (BE32K) Sequence

CS#

0

1

2

3

4

5

6

7

8

9

29 30 31

SCLK

Command

52h

24 Bit Address

SI

23 22

MSB

2

0

1

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

45

MX25U1633F

10-20. Block Erase (BE)

The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for

64K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL)

bit before sending the Block Erase (BE). Any address of the block (Please refer to "Table 4. Memory Organization")

is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the latest

eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed.

The sequence of issuing BE instruction is: CS# goes low→ sending BE instruction code→ 3-byte address on SI→

CS# goes high.

The SIO[3:1] are "don't care".

The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in

Progress (WIP) bit still can be checked during the Block Erase cycle is in progress. The WIP sets 1 during the tBE

timing, and sets 0 when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the block

is protected by BP3, BP2, BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the block.

Figure 27. Block Erase (BE) Sequence

CS#

0

1

2

3

4

5

6

7

8

9

29 30 31

Mode 3

Mode 0

SCLK

Command

D8h

24-Bit Address

SI

23 22

MSB

2

0

1

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

46

MX25U1633F

10-21. Chip Erase (CE)

The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN)

instruction must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS#

must go high exactly at the byte boundary, otherwise the instruction will be rejected and not executed.

The sequence of issuing CE instruction is: CS# goes low→sending CE instruction code→CS# goes high.

The SIO[3:1] are "don't care".

The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in

Progress (WIP) bit still can be checked during the Chip Erase cycle is in progress. The WIP sets 1 during the

tCE timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the

chip is protected by BP3, BP2, BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only

executed when BP3, BP2, BP1, BP0 all set to "0".

Figure 28. Chip Erase (CE) Sequence

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

SCLK

SI

Command

60h or C7h

Macronix Proprietary

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Rev. 1.1, February 23, 2018

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MX25U1633F

10-22. Page Program (PP)

The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction

must be executed to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device

programs only the last 256 data bytes sent to the device. The last address byte (the 8 least signiﬁcant address

bits, A7-A0) should be set to 0 for 256 bytes page program. If A7-A0 are not all zero, transmitted data that exceed

page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently selected

page. If the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the request page

and previous data will be disregarded. If the data bytes sent to the device has not exceeded 256, the data will be

programmed at the request address of the page. There will be no effort on the other data bytes of the same page.

The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→ at

least 1-byte on data on SI→ CS# goes high.

The CS# must be kept low during the whole Page Program cycle; The CS# must go high exactly at the byte boundary (the

latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed.

The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in

Progress (WIP) bit still can be checked during the Page Program cycle is in progress. The WIP sets 1 during the

tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the

page is protected by BP3, BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed.

The SIO[3:1] are "don't care".

Figure 29. Page Program (PP) Sequence

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38 39

SCLK

Command

02h

Data Byte 1

24-Bit Address

23 22 21

MSB

3

2

1

0

7

6

5

4

3

2

0

1

SI

MSB

CS#

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

SCLK

Data Byte 2

Data Byte 3

Data Byte 256

7

6

5

4

3

2

0

7

6

5

4

3

2

0

7

6

5

4

3

2

0

1

SI

MSB

Macronix Proprietary

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Rev. 1.1, February 23, 2018

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MX25U1633F

10-23. 4 x I/O Page Program (4PP)

The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN)

instruction must execute to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1" before

sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1, SIO2, and

SIO3 as address and data input, which can improve programmer performance and the effectiveness of application.

The 4PP operation frequency supports as fast as f4PP. The other function descriptions are as same as standard

page program.

The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on

SIO[3:0]→ at least 1-byte on data on SIO[3:0]→CS# goes high.

Figure 30. 4 x I/O Page Program (4PP) Sequence

CS#

10 11 12 13 14 15 16 17 18 19 20 21

Data Data Data Data

0

1

2

3

4

5

6

7

8

9

Mode 3

Mode 0

SCLK

Command

38h

6 ADD cycles

Byte 1 Byte 2 Byte 3 Byte 4

A16 A12 A8 A4 A0

A20

D4 D0 D4 D0 D4 D0

D0

D4

SIO0

SIO1

SIO2

SIO3

A21 A17 A13 A9 A5 A1

A22 A18 A14 A10 A6 A2

D5 D1 D5 D1 D5 D1 D5 D1

D6 D2 D6 D2 D6 D2 D6 D2

A23 A19 A15 A11 A7 A3 D7 D3 D7 D3 D7 D3 D7 D3

Macronix Proprietary

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MX25U1633F

10-24. Deep Power-down (DP)

The Deep Power-down (DP) instruction places the device into a minimum power consumption state, Deep Power

down mode, in which the quiescent current is reduced from ISB1 to ISB2.

The sequence of issuing DP instruction: CS# goes low→ send DP instruction code→ CS# goes high. The CS# must

go high at the byte boundary; otherwise the instruction will not be executed. SIO[3:1] are "don't care".

After CS# goes high there is a delay of tDP before the device transitions from Stand-by mode to Deep Power-down

mode and the current reduces from ISB1 to ISB2. Once in Deep Power-down mode, all instructions will be ignored.

CS# must not be pulsed low until the device has been in Deep Power-down mode for a minimum of tDPDD. The

device exits Deep Power-down mode and returns to Stand-by mode if CS# pulses low for tCRDP or if the device is

power-cycled or hardware reset. After CS# goes high, there is a delay of tRDP before the device transitions from

Deep Power-down mode back to Stand-by mode.

Figure 31. Deep Power-down (DP) Sequence and Release from Deep Power-down Sequence

tCRDP

CS#

tDP

tDPDD

tRDP

0

1

2

3

4

5

6

7

Mode 3

Mode 0

SCLK

SI

Command

B9h

Stand-by Mode

Deep Power-down Mode

Stand-by Mode

Macronix Proprietary

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MX25U1633F

10-25. Enter Secured OTP (ENSO)

The ENSO instruction is for entering the additional 8K-bit secured OTP mode. The additional 8K-bit secured OTP is

independent from main array, which may use to store unique serial number for system identiﬁer. After entering the

Secured OTP mode, and then follow standard read or program procedure to read out the data or update data. The

Secured OTP data cannot be updated again once it is lock-down.

The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP

mode→ CS# goes high.

The SIO[3:1] are "don't care".

Please note that WRSR/WRSCUR commands are not acceptable during the access of secure OTP region, once

security OTP is lock down, only read related commands are valid.

10-26. Exit Secured OTP (EXSO)

The EXSO instruction is for exiting the additional 8K-bit secured OTP mode.

The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP

mode→ CS# goes high.

The SIO[3:1] are "don't care".

10-27. Read Security Register (RDSCUR)

The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read

at any time (even in program/erase/write status register/write security register condition) and continuously.

The sequence of issuing RDSCUR instruction is : CS# goes low→sending RDSCUR instruction→Security Register

data out on SO→ CS# goes high.

The SIO[3:1] are "don't care".

The deﬁnition of the Security Register bits is as below:

Secured OTP Indicator bit. The Secured OTP indicator bit shows the secured OTP area is locked by factory before

ex- factory or not. When it is "0", it indicates non-factory lock; "1" indicates factory-lock.

Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for

customer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 1^st4K-bit

Secured OTP area cannot be update any more. While it is in 8K-bit secured OTP mode, main array access is not

allowed.

Program Suspend Status bit. Program Suspend Bit (PSB) indicates the status of Program Suspend operation.

Users may use PSB to identify the state of ﬂash memory. After the ﬂash memory is suspended by Program Suspend

command, PSB is set to "1". PSB is cleared to "0" after program operation resumes.

Erase Suspend Status bit. Erase Suspend Bit (ESB) indicates the status of Erase Suspend operation. Users may

use ESB to identify the state of ﬂash memory. After the ﬂash memory is suspended by Erase Suspend command,

ESB is set to "1". ESB is cleared to "0" after erase operation resumes.

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Program Fail Flag bit. The Program Fail bit shows the status of the last Program operation. The bit will be set to "1"

if the program operation failed or the program region was protected. It will be automatically cleared to "0" if the next

program operation succeeds. Please note that it will not interrupt or stop any operation in the ﬂash memory.

Erase Fail Flag bit. The Erase Fail bit shows the status of last Erase operation. The bit will be set to "1" if the erase

operation failed or the erase region was protected. It will be automatically cleared to "0" if the next erase operation

succeeds. Please note that it will not interrupt or stop any operation in the ﬂash memory.

Table 9. Security Register Deﬁnition

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

LDSO

(lock-down 1^st

4K-bit Secured

OTP)

Secured OTP

Indicator bit

(2^nd4K-bit

ESB

(Erase

PSB

(Program

Reserved

E_FAIL

P_FAIL

Reserved

Suspend bit) Suspend bit)

Secured OTP)

0=normal

Program

succeed

1=indicate

Program

failed

0 = not

lockdown

0=normal

Erase

succeed

1=indicate

Erase failed

(default=0)

0=Erase

is not

suspended suspended

1= Erase 1= Program

suspended suspended

(default=0)

Volatile bit

Read Only

0=Program

is not

0 = nonfactory

lock

-

1 = lock-down

(cannot

program/erase

OTP)

1 = factory

lock

(default=0)

x

Volatile bit

Read Only

Volatile bit

Read Only

Volatile bit

Volatile bit non-volatile bit non-volatile bit

Read Only OTP Read Only

Figure 32. Read Security Register (RDSCUR) Sequence

CS#

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

SCLK

SI

command

2Bh

Security register Out

High-Z

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

MSB

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10-28. Write Security Register (WRSCUR)

The WRSCUR instruction is for changing the values of Security Register Bits. The WREN (Write Enable) instruction

is required before issuing WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO bit)

for customer to lock-down the 1^st4K-bit Secured OTP area. Once the LDSO bit is set to "1", the 1^st4K-bit Secured

OTP area cannot be updated any more.

The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high.

The SIO[3:1] are "don't care".

The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.

Figure 33. Write Security Register (WRSCUR) Sequence

CS#

0

1

2

3

4

5

6

7

Mode 3

Mode 0

SCLK

Command

2Fh

SI

High-Z

SO

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10-29. Program Suspend and Erase Suspend

The Suspend instruction interrupts a Page Program, Sector Erase, or Block Erase operation to allow access to

the memory array. After the program or erase operation has entered the suspended state, the memory array can

be read except for the page being programmed or the sector or block being erased ("Table 10. Readable Area of

Memory While a Program or Erase Operation is Suspended").

Table 10. Readable Area of Memory While a Program or Erase Operation is Suspended

Suspended Operation

Page Program

Readable Region of Memory Array

All but the Page being programmed

All but the 4KB Sector being erased

All but the 32KB Block being erased

All but the 64KB Block being erased

Sector Erase (4KB)

Block Erase (32KB)

Block Erase (64KB)

When the Serial NOR Flash receives the Suspend instruction, there is a latency of tPSL or tESL ("Figure 35.

Suspend to Read/Program Latency") before the Write Enable Latch (WEL) bit clears to “0” and the PSB or ESB sets

to “1”, after which the device is ready to accept one of the commands listed in "Table 11. Acceptable Commands

During Program/Erase Suspend after tPSL/tESL" (e.g. FAST READ). Refer to "Table 16. AC Characteristics" for

tPSL and tESL timings.

"Table 12. Acceptable Commands During Suspend (tPSL/tESL not required)" lists the commands for which the tPSL

and tESL latencies do not apply. For example, RDSR, RDSCUR, RSTEN, and RST can be issued at any time after

the Suspend instruction.

Security Register bit 2 (PSB) and bit 3 (ESB) can be read to check the suspend status. The PSB (Program Suspend

Bit) sets to “1” when a program operation is suspended. The ESB (Erase Suspend Bit) sets to “1” when an erase

operation is suspended. The PSB or ESB clears to “0” when the program or erase operation is resumed.

Table 11. Acceptable Commands During Program/Erase Suspend after tPSL/tESL

Suspend Type

Command Name

Command Code

Program Suspend

Erase Suspend

READ

FAST READ

DREAD

QREAD

2READ

4READ

RDSFDP

RDID

03h

0Bh

3Bh

6Bh

BBh

EBh

5Ah

9Fh

90h

B1h

C1h

C0h

06h

•

REMS

ENSO

EXSO

SBL

WREN

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Acceptable Commands During Program/Erase Suspend after tPSL/tESL - Continued

Suspend Type

Command Name

Command Code

Program Suspend

Erase Suspend

RESUME

PP

7Ah or 30h

02h

•

4PP

38h

Table 12. Acceptable Commands During Suspend (tPSL/tESL not required)

Suspend Type

Command Name

Command Code

Program Suspend

Erase Suspend

WRDI

RDSR

RDCR

RDSCUR

RES

04h

05h

15h

2Bh

ABh

66h

99h

00h

•

RSTEN

RST

NOP

Figure 34. Resume to Suspend Latency

tPRS/tERS

Suspend

Command

Resume Command

CS#

tPRS: Program Resume to another Suspend

tERS: Erase Resume to another Suspend

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10-29-1.

Erase Suspend to Program

The “Erase Suspend to Program” feature allows Page Programming while an erase operation is suspended. Page

Programming is permitted in any unprotected memory except within the sector of a suspended Sector Erase

operation or within the block of a suspended Block Erase operation. The Write Enable (WREN) instruction must be

issued before any Page Program instruction.

A Page Program operation initiated within a suspended erase cannot itself be suspended and must be allowed to

ﬁnish before the suspended erase can be resumed. The Status Register can be polled to determine the status of

the Page Program operation. The WEL and WIP bits of the Status Register will remain “1” while the Page Program

operation is in progress and will both clear to “0” when the Page Program operation completes.

Figure 35. Suspend to Read/Program Latency

tPSL/tESL

Suspend Command

Read/Program Command

CS#

tPSL: Program latency

tESL: Erase latency

Notes:

1. Please note that Program only available after the Erase-Suspend operation

2. To check suspend ready information, please read security register bit2(PSB) and bit3(ESB)

10-30. Program Resume and Erase Resume

The Resume instruction resumes a suspended Page Program, Sector Erase, or Block Erase operation. Before

issuing the Resume instruction to restart a suspended erase operation, make sure that there is no Page Program

operation in progress.

Immediately after the Serial NOR Flash receives the Resume instruction, the WEL and WIP bits are set to “1” and

the PSB or ESB is cleared to “0”. The program or erase operation will continue until ﬁnished ("Figure 36. Resume to

Read Latency") or until another Suspend instruction is received. A resume-to-suspend latency of tPRS or tERS must

be observed before issuing another Suspend instruction ("Figure 34. Resume to Suspend Latency").

Please note that the Resume instruction will be ignored if the Serial NOR Flash is in “Performance Enhance Mode”.

Make sure the Serial NOR Flash is not in “Performance Enhance Mode” before issuing the Resume instruction.

Figure 36. Resume to Read Latency

tSE/tBE/tPP

Resume Command

Read Command

CS#

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10-31. No Operation (NOP)

The "No Operation" command is only able to terminate the Reset Enable (RSTEN) command and will not affect any

other command.

The SIO[3:1] are don't care.

10-32. Software Reset (Reset-Enable (RSTEN) and Reset (RST))

The Software Reset operation combines two instructions: Reset-Enable (RSTEN) command and Reset (RST)

command. It returns the device to a standby mode. All the volatile bits and settings will be cleared then, which

makes the device return to the default status as power on.

To execute Reset command (RST), the Reset-Enable (RSTEN) command must be executed ﬁrst to perform the

Reset operation. If there is any other command to interrupt after the Reset-Enable command, the Reset-Enable will

be invalid.

The SIO[3:1] are "don't care".

If the Reset command is executed during program or erase operation, the operation will be disabled, the data under

processing could be damaged or lost.

The reset time is different depending on the last operation. Longer latency time is required to recover from a

program operation than from other operations.

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Figure 37. Software Reset Recovery

Stand-by Mode

66

99

CS#

tReady2

Mode

Note: Refer to "Table 16. AC Characteristics" for tREADY2 data.

Figure 38. Reset Sequence

tSHSL

CS#

Mode 3

Mode 0

Mode 3

Mode 0

SCLK

SIO0

Command

66h

Command

99h

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10-33. High Voltage Operation

The ﬂash device supports High Voltage Operation. This opeartion allows user can have better performance in

following Program/Erase operation.

To enable High Voltage Opeartion, WP#/SIO2 need to apply Vhv during whole operation. If the voltage can not

sustain in Vhv range, the Program/Erase opeation might be failed. CS# can only go low after tVSL1+tVhv +tVhv2

timing during High Voltage Operation. WP# can only start to go low after whole Erase/Program Operation has been

done.

To check the operation status, user may check the status of WIP bit.

Figure 39. High Voltage Operation Diagram

Vcc (min.)

Vcc

GND

tVSL1

Vhv

(7V ~ 8V)

WP#

tVhv2

Vcc

tVhv(Note 1)

tVhv(Note 2)

GND

Vcc

CS#

Standby Mode

GND

Note 1: Please note that the CS# can only go low after tVSL1+tVhv +tVhv2 timing during High Voltage Operation.

Note 2: Please note that the WP# can only start to go low after whole Erase/Program Operation has been done.

To check the operation status, user may check the status of WIP bit.

Note 3: tVhv(min.) = 250ns, tVSL 1(min.) = 800us; tVhv2(min.) = 0ns

Note 4: Vhv range is 7V(min.) ≤ Vhv ≤ 8(max.)

Note 5: The High Voltage Operation can only work during Vcc(min.) ≤ Vcc ≤ 2.0V

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10-34. Read SFDP Mode (RDSFDP)

The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional

and feature capabilities of serial ﬂash devices in a standard set of internal parameter tables. These parameter tables

can be interrogated by host system software to enable adjustments needed to accommodate divergent features

from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on

CFI.

The sequence of issuing RDSFDP instruction is same as FAST_READ: CS# goes low→send RDSFDP instruction

(5Ah)→send 3 address bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP

operation can use CS# to high at any time during data out.

SFDP is a JEDEC Standard, JESD216B.

For SFDP register values detail, please contact local Macronix sales channel for Application Note.

Figure 40. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence

CS#

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31

SCLK

Command

5Ah

24 BIT ADDRESS

SI

23 22 21

3

2

1

0

High-Z

SO

CS#

47

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

SCLK

Dummy Cycle

7

6

5

4

3

2

0

1

SI

DATA OUT 2

DATA OUT 1

7

6

5

4

3

2

1

0

7

6

5

4

3

2

0

1

SO

MSB

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11. POWER-ON STATE

The device is at the following states after power-up:

- Standby mode (please note it is not deep power-down mode)

- Write Enable Latch (WEL) bit is reset

The device must not be selected during power-up and power-down stage until the VCC reaches the following levels:

- VCC minimum at power-up stage and then after a delay of tVSL

- GND at power-down

Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.

An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change

during power up state. When VCC is lower than VWI (POR threshold voltage value), the internal logic is reset and

the ﬂash device has no response to any command.

For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not

guaranteed. The write, erase, and program command should be sent after the below time delay:

- tVSL after VCC reached VCC minimum level

The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.

Please refer to the "Figure 48. Power-up Timing".

Note:

- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is

recommended. (generally around 0.1uF)

- At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response to

any command. The data corruption might occur during this stage if a write, program, erase cycle is in progress.

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12. ELECTRICAL SPECIFICATIONS

Table 13. Absolute Maximum Ratings

Rating

Value

Ambient Operating Temperature

Storage Temperature

Applied Input Voltage

Applied Output Voltage

VCC to Ground Potential

Industrial grade

-40°C to 85°C

-65°C to 150°C

-0.5V to VCC+0.5V

-0.5V to 2.5V

NOTICE:

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to

the device. This is stress rating only and functional operational sections of this speciﬁcation is not implied.

Exposure to absolute maximum rating conditions for extended period may affect reliability.

2. Speciﬁcations contained within the following tables are subject to change.

3. During voltage transitions, all pins may overshoot to VCC+1.0V or -1.0V for period up to 20ns.

Figure 42. Maximum Positive Overshoot Waveform

Figure 41. Maximum Negative Overshoot Waveform

20ns

0V

VCC+1.0V

-1.0V

2.0V

20ns

Table 14. Capacitance

TA = 25°C, f = 1.0 MHz

Symbol Parameter

Min.

Typ.

Max.

Unit

pF

Conditions

VIN = 0V

CIN

Input Capacitance

6

8

COUT Output Capacitance

pF

VOUT = 0V

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Figure 43. Input Test Waveforms and Measurement Level

Input timing reference level

0.8VCC

Output timing reference level

0.7VCC

AC

Measurement

Level

0.5VCC

0.3VCC

0.2VCC

Note: Input pulse rise and fall time are <5ns

Figure 44. Output Loading

25K ohm

DEVICE UNDER

TEST

VCC

CL

25K ohm

CL=15/30pF Including jig capacitance

Figure 45. SCLK TIMING DEFINITION

tCLCH

tCHCL

VIH (Min.)

0.5VCC

VIL (Max.)

tCH

tCL

1/fSCLK

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Table 15. DC Characteristics

Symbol Parameter

Notes

Min.

Typ.

Max.

Units Test Conditions

VCC = VCC Max,

uA

ILI

Input Load Current

1

±2

VIN = VCC or GND

VCC = VCC Max,

uA

ILO

Output Leakage Current

1

±2

30

50

2

VOUT = VCC or GND

Leakage Current while

WP# at Vhv

Iwph

uA VCC < 2.1V

VIN = VCC or GND,

CS# = VCC

ISB1 VCC Standby Current

9

uA

Deep Power-down

Current

VIN = VCC or GND,

CS# = VCC

ISB2

0.2

uA

f=80MHz

3.8

4.2

6.5

9

mA SCLK=0.1VCC/0.9VCC,

SO=Open

f=80MHz (2x I/O)

mA SCLK=0.1VCC/0.9VCC,

SO=Open

f=33MHz (4x I/O)

mA SCLK=0.1VCC/0.9VCC,

SO=Open

ICC1 VCC Read

1

f=80MHz (4x I/O)

mA SCLK=0.1VCC/0.9VCC,

SO=Open

VCC Program Current

Program in Progress,

CS# = VCC

ICC2

(PP)

5.8

3.5

10

mA

VCC Write Status

ICC3

Program status register in

mA

Register (WRSR) Current

progress, CS#=VCC

VCC Sector/Block (64K)

ICC4 Erase Current

(SE/BE)

Erase in Progress,

CS#=VCC

1

3.5

4

10

mA

VCC Chip Erase Current

Erase in Progress,

CS#=VCC

ICC5

(CE)

10

8

mA

High Voltage Applied at

WP# pin

Vhv

7

V

Test Condition, VCC=2.0V

VIL

VIH

VOL

Input Low Voltage

Input High Voltage

Output Low Voltage

-0.5

0.2VCC

VCC+0.4

0.2

V

0.8VCC

IOL = 100uA

IOH = -100uA

VOH Output High Voltage

VCC-0.2

Notes :

1. Device operation range: 1.65V-2.0V, Typical values at VCC = 1.8V, T = 25 C.

°

These currents are valid for all product versions (package and speeds).

2. Typical value is calculated by simulation.

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Table 16. AC Characteristics

Symbol

Alt. Parameter

Clock Frequency for the following instructions:

Min.

Typ.⁽²⁾Max. Unit

fSCLK

fC FAST_READ, RDSFDP, PP, SE, BE32K, BE, CE, DP,

D.C.

80

MHz

RES, WREN, WRDI, RDID, RDSR, WRSR⁽⁸⁾

fRSCLK

fTSCLK

f4PP

fR Clock Frequency for READ instructions

33

80

MHz

ns

fT Clock Frequency for 2READ/DREAD instructions

fQ Clock Frequency for 4READ/QREAD instructions

Clock Frequency for 4PP (Quad page program)

Others (fSCLK)

Normal Read (fRSCLK)

45%x (1/fSCLK)

tCH⁽¹⁾

tCLH Clock High Time

13

ns

Others (fSCLK)

Normal Read (fRSCLK)

45%x (1/fSCLK)

ns

V/ns

ns

tCL⁽¹⁾

tCLL Clock Low Time

13

0.1

5

2

3

5

tCLCH⁽¹⁰⁾

tCHCL⁽¹⁰⁾

tSLCH

Clock Rise Time (peak to peak)

Clock Fall Time (peak to peak)

tCSS CS# Active Setup Time (relative to SCLK)

CS# Not Active Hold Time (relative to SCLK)

tDSU Data In Setup Time

tCHSL

tDVCH

tCHDX

tCHSH

tSHCH

tDH Data In Hold Time

CS# Active Hold Time (relative to SCLK)

CS# Not Active Setup Time (relative to SCLK)

From Read to next Read

ns

tSHSL

tCSH CS# Deselect Time

From Write/Erase/Program

to Read Status Register

30

ns

tSHQZ⁽¹⁰⁾tDIS Output Disable Time

8

6

ns

us

Loading: 30pF

Loading: 15pF

Clock Low to Output Valid

tCLQV

tV

Loading: 30pF/15pF

tHO Output Hold Time

HOLD# Active Setup Time (relative to SCLK)

tCLQX

tHLCH

tCHHH

tHHCH

tCHHL

tHHQX

tHLQZ

tWHSL⁽³⁾

tSHWL ⁽³⁾

tDP

0

8

HOLD# Active Hold Time (relative to SCLK)

HOLD# Not Active Setup Time (relative to SCLK)

HOLD# Not Active Hold Time (relative to SCLK)

tLZ HOLD# to Output Low-Z

10

tHZ HOLD# to Output High-Z

Write Protect Setup Time

Write Protect Hold Time

CS# High to Deep Power-down Mode

Delay Time for Release from Deep Power-Down

Mode once entering Deep Power-Down Mode

CS# Toggling Time before Release from Deep

Power-Down Mode

Recovery Time for Release from deep power down

mode

Write Status Register Cycle Time

Reset Recovery time (During instruction decoding)

Reset Recovery time (for read operation)

Reset Recovery time (for program operation)

Reset Recovery time(for SE4KB operation)

Reset Recovery time (for BE32K/64K operation)

Reset Recovery time (for Chip Erase operation)

Reset Recovery time (for WRSR operation)

10

tDPDD

tCRDP

30

20

45

us

ns

us

tRDP

tW

9.5

20

ms

us

30

80

12

0.1

us

tREADY2

ms

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Symbol Alt. Parameter

Min.

Typ.⁽²⁾

Max.

40

Unit

us

ms

s

tESL ⁽⁹⁾

tPSL ⁽⁹⁾

Erase Suspend Latency

Program Suspend Latency

(4)

tPRS

Latency between Program Resume and next Suspend

Latency between Erase Resume and next Suspend

Byte-Program

Byte-Program (Applied Vhv at WP# pin)

Page Program Cycle Time

Page Program Cycle Time (Applied Vhv at WP# pin)

Sector Erase Cycle Time

Sector Erase Cycle Time (Applied Vhv at WP# pin)

Block Erase (32KB) Cycle Time

Block Erase (32KB) Cycle Time (Applied Vhv at WP# pin)

Block Erase (64KB) Cycle Time

Block Erase (64KB) Cycle Time (Applied Vhv at WP# pin)

Chip Erase Cycle Time

0.3

tERS⁽⁵⁾

32

0.85

0.6

40

100

4

3.6

240

210

1.5

1.05

3

tBP

tPP

tSE

36

0.24

0.22

0.48

0.43

13

tBE32K

tBE

s

2.1

38

34

tCE

Chip Erase Cycle Time (Applied Vhv at WP# pin)

12

s

Notes:

1. tCH + tCL must be greater than or equal to 1/ Frequency.

2. Typical values given for TA=25 C. Not 100% tested.

°

3. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.

4. Program operation may be interrupted as often as system request. The minimum timing of tPRS must be

observed before issuing the next program suspend command. However, in order for an Program operation to

make progress, tPRS ≥ 100us must be included in resume-to-suspend loop(s). Not 100% tested.

5. Erase operation may be interrupted as often as system request. The minimum timing of tERS must be observed

before issuing the next erase suspend command. However, in order for an Erase operation to make progress,

tERS ≥ 280us must be included in resume-to-suspend loop(s). The details are described in Macronix application

notes. Not 100% tested.

6. If the address range is within 4Mb, the 4READ/QREAD clock rate could achieve to 16MHz for 4READ/QREAD

operation. If user wants to keep 4READ/QREAD at 16MHz for address range that is more than 4Mb, it is

necessary to re-issue 4READ/QREAD command again after each 4Mb boundary.

7. Test condition is shown as "Figure 43. Input Test Waveforms and Measurement Level", "Figure 44. Output

Loading".

8. WRSR speed max. is 33MHz .

9. Latency time is required to complete Erase/Program Suspend operation until WIP bit is "0".

10. The value guaranteed by characterization, not 100% tested in production.

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

66

MX25U1633F

13. OPERATING CONDITIONS

At Device Power-Up and Power-Down

AC timing illustrated in "Figure 46. AC Timing at Device Power-Up" and "Figure 47. Power-Down Sequence" are

for the supply voltages and the control signals at device power-up and power-down. If the timing in the ﬁgures is

ignored, the device will not operate correctly.

During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be

selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.

Figure 46. AC Timing at Device Power-Up

VCC(min)

VCC

GND

tVR

tSHSL

CS#

tSHCH

tSLCH

tCHSL

tCHSH

SCLK

tDVCH

tCHCL

tCHDX

tCLCH

MSB IN

LSB IN

SI

High Impedance

SO

Symbol

Parameter

Notes

Min.

Max.

Unit

tVR

VCC Rise Time

1

500000

us/V

Notes:

1. Sampled, not 100% tested.

2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the ﬁgure, please refer to

"Table 16. AC Characteristics".

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

67

MX25U1633F

Figure 47. Power-Down Sequence

During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.

VCC

CS#

SCLK

Figure 48. Power-up Timing

V

CC

V

(max)

CC

Chip Selection is Not Allowed

V

(min)

CC

Device is fully accessible

tVSL

V

WI

time

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

68

MX25U1633F

Figure 49. Power Up/Down and Voltage Drop

When powering down the device, VCC must drop below V_PWDfor at least tPWD to ensure the device will initialize

correctly during power up. Please refer to "Figure 49. Power Up/Down and Voltage Drop" and "Table 17. Power-

Up/Down Voltage and Timing" below for more details.

VCC

VCC (max.)

Chip Select is not allowed

VCC (min.)

tVSL

Full Device

Access

Allowed

(max.)

V

PWD

tPWD

Time

Table 17. Power-Up/Down Voltage and Timing

Symbol Parameter

Min.

800

1.0

Max.

Unit

us

V

tVSL

VWI

VCC(min.) to device operation

Write Inhibit Voltage

1.5

0.4

0.9

Deep Power Mode

others

V

VCC voltage needed to below V_PWDfor

ensuring initialization will occur

V_PWD

V

tPWD The minimum duration for ensuring initialization will occur

300

us

Note: These parameters are characterized only.

13-1. Initial Delivery State

The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status

Register contains 00h (all Status Register bits are 0).

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

69

MX25U1633F

14. ERASE AND PROGRAMMING PERFORMANCE

PARAMETER

Min.

Typ.⁽¹⁾

9.5

Max.⁽²⁾

20

Unit

ms

s

Write Status Register Cycle Time

Sector Erase Cycle Time (4KB)

40

240

210

1.5

1.05

3

Sector Erase Cycle Time (4KB) (Applied Vhv at WP# pin)

Block Erase Cycle Time (32KB)

36

0.24

0.22

0.48

0.43

13

Block Erase Cycle Time (32KB) (Applied Vhv at WP# pin)

Block Erase Cycle Time (64KB)

s

Block Erase Cycle Time (64KB) (Applied Vhv at WP# pin)

Chip Erase Cycle Time

2.1

38

s

Chip Erase Cycle Time (Applied Vhv at WP# pin)

Byte Program Time

12

32⁽⁴⁾

34

s

100

4

us

ms

cycles

Byte Program Time (Applied Vhv at WP# pin)

Page Program Time

32

0.85⁽⁴⁾

0.6

Page Program Time (Applied Vhv at WP# pin)

Erase/Program Cycle

3.6

100,000

Notes:

1. Typical erase assumes the following conditions: 25 C, typical operation voltage and all zero pattern.

°

2. Under worst conditions of 85 C and minimum operation voltage.

°

3. System-level overhead is the time required to execute the ﬁrst-bus-cycle sequence for the programming

command.

4. Typical program assumes the following conditions: 25 C, typical VCC, and checkerboard pattern.

°

15. LATCH-UP CHARACTERISTICS

Min.

Max.

Input Voltage with respect to GND on all power pins, SI, CS#

Input Voltage with respect to GND on SO

Current

-1.0V

2 VCCmax

VCC + 1.0V

+100mA

-100mA

Includes all pins except VCC. Test conditions: typical operation voltage, one pin at a time.

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

70

MX25U1633F

16. ORDERING INFORMATION

Please contact Macronix regional sales for the latest product selection and available form factors.

PART NO.

MX25U1633FZUI

MX25U1633FM2I

MX25U1633FM1I

Voltage

Package

Temperature

-40 C to 85 C

Remark

1.65V-2.0V

8-USON (2x3mm)

8-SOP (200mil)

8-SOP (150mil)

°

-40 C to 85 C

°

-40 C to 85 C

°

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

71

MX25U1633F

17. PART NAME DESCRIPTION

MX 25U 1633F ZU

I

TEMPERATURE RANGE:

I: Industrial (-40°C to 85°C)

PACKAGE:

ZU: 8-USON (2x3mm)

M2: 8-SOP(200mil)

M1: 8-SOP(150mil)

DENSITY & MODE:

1633F: 16Mb

DEVICE:

25U: 1.8V Serial NOR Flash

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

72

MX25U1633F

18. PACKAGE INFORMATION

18-1. 8-land USON (2x3mm)

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

73

MX25U1633F

18-2. 8-pin SOP (200mil)

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

74

MX25U1633F

18-3. 8-pin SOP (150mil)

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

75

MX25U1633F

19. REVISION HISTORY

Revision No. Description

Page

P63

Date

SEP/26/2016

0.01

1. Updated Deep Power-down Current (ISB2) values

1.0

1. Removed "Advanced Information" to align with the

product status

All

FEB/22/2017

2. Updated the note for the internal pull up status of

HOLD#/SIO3 and WP#/SIO2

P6

3. Content correction

4. Added MX25U1633FM2I

P16,25,30,39

P4,6,70-71,73

1.1

1. Added MX25U1633FM1I.

P4,6,71-72,75 FEB/23/2018

2. Added "Macronix Proprietary" footnote.

3. Added WRSCUR and RDSCUR command figures.

4. Added "Figure 45. SCLK TIMING DEFINITION".

5. Content correction.

All

P52-53

P63

P1,28,30

P73-74

6. Format modification.

Macronix Proprietary

P/N: PM2437

Rev. 1.1, February 23, 2018

76

MX25U1633F

Except for customized products which have been expressly identiﬁed in the applicable agreement, Macronix's

products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or

household applications only, and not for use in any applications which may, directly or indirectly, cause death,

personal injury, or severe property damages. In the event Macronix products are used in contradicted to their target

usage above, the buyer shall take any and all actions to ensure said Macronix's product qualiﬁed for its actual use

in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or distributors

shall be released from any and all liability arisen therefrom.

tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, Nbit, Macronix

NBit, HybridNVM, HybridFlash, HybridXFlash, XtraROM, KH Logo, BE-SONOS, KSMC, Kingtech, MXSMIO,

Macronix vEE, Macronix MAP, RichBook, Rich TV, OctaRAM, OctaBus, OctaFlash, and FitCAM. The names and

brands of third party referred thereto (if any) are for identiﬁcation purposes only.

For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and speciﬁcations without notice.

77


型号：	MX25U1633FM1I
厂家：	MACRONIX INTERNATIONAL
描述：	Flash,
文件：	总77页 (文件大小：1118K)
中文：	中文翻译
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MX25U1633FM1I [Macronix]

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