MX25U2033EM1I12G [Macronix]
2M-BIT [x 1/x 2/x 4] 1.8V CMOS MXSMIO® (SERIAL MULTI I/O) FLASH MEMORY;
| 型号： | MX25U2033EM1I12G |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | 2M-BIT [x 1/x 2/x 4] 1.8V CMOS MXSMIO® (SERIAL MULTI I/O) FLASH MEMORY |
| 文件： | 总68页 (文件大小：840K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MX25U2033E
MX25U2033E DATASHEET
P/N: PM1743
REV. 1.3, NOV. 14, 2013
1
MX25U2033E
Contents
1. FEATURES ..............................................................................................................................................................5
Table 1. Additional Feature Comparison.......................................................................................................7
2. PIN CONFIGURATIONS .........................................................................................................................................8
3. PIN DESCRIPTION..................................................................................................................................................8
4. BLOCK DIAGRAM...................................................................................................................................................9
5. DATA PROTECTION..............................................................................................................................................10
Table 2. Protected Area Sizes..................................................................................................................... 11
Table 3. 4K-bit Secured OTP Definition ...................................................................................................... 11
6. MEMORY ORGANIZATION...................................................................................................................................12
Table 4. Memory Organization....................................................................................................................12
7. DEVICE OPERATION............................................................................................................................................13
Figure 1. Serial Modes Supported..............................................................................................................13
8. HOLD FEATURE....................................................................................................................................................14
Figure 2. Hold Condition Operation ...........................................................................................................14
9. COMMAND DESCRIPTION...................................................................................................................................15
Table 5. Command Set ...............................................................................................................................15
9-1. Write Enable (WREN).................................................................................................................................17
9-2. Write Disable (WRDI) .................................................................................................................................17
9-3. Read Identification (RDID)..........................................................................................................................17
9-4. Read Status Register (RDSR)....................................................................................................................17
Table 6. Status Register..............................................................................................................................21
9-5. Write Status Register (WRSR) ...................................................................................................................22
Table 7. Protection Modes ..........................................................................................................................22
9-6. Read Data Bytes (READ)...........................................................................................................................23
9-7. Read Data Bytes at Higher Speed (FAST_READ).....................................................................................23
9-8. 2 x I/O Read Mode (2READ)......................................................................................................................23
9-9. 4 x I/O Read Mode (4READ)......................................................................................................................24
9-10.Performance Enhance Mode......................................................................................................................25
9-11. Sector Erase (SE).......................................................................................................................................25
9-12.Block Erase (BE32K)..................................................................................................................................26
9-13.Block Erase (BE) ........................................................................................................................................26
9-14.Chip Erase (CE) .........................................................................................................................................26
9-15.Page Program (PP) ....................................................................................................................................27
9-16.4 x I/O Page Program (4PP).......................................................................................................................27
9-17.Deep Power-down (DP)..............................................................................................................................27
9-18.Release from Deep Power-down (RDP), Read Electronic Signature (RES)..............................................28
9-19.Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4)............................................28
Table 8. ID Definitions ................................................................................................................................29
9-20.Enter Secured OTP (ENSO).......................................................................................................................29
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9-21.Exit Secured OTP (EXSO)..........................................................................................................................29
9-22.Read Security Register (RDSCUR)............................................................................................................29
Table 9. Security Register Definition...........................................................................................................30
9-23.Write Security Register (WRSCUR) ...........................................................................................................30
9-24.Write Protection Selection (WPSEL) ..........................................................................................................30
Figure 3. WPSEL Flow ...............................................................................................................................31
9-25.Single Block Lock/Unlock Protection (SBLK/SBULK).................................................................................32
Figure 4. Block Lock Flow ..........................................................................................................................32
Figure 5. Block Unlock Flow.......................................................................................................................33
9-26.Read Block Lock Status (RDBLOCK).........................................................................................................34
9-27.Gang Block Lock/Unlock (GBLK/GBULK) ..................................................................................................34
9-28.Read SFDP Mode (RDSFDP) ....................................................................................................................35
Figure 6. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence.............................................35
Table 10. Signature and Parameter Identification Data Values ..................................................................36
Table 11. Parameter Table (0): JEDEC Flash Parameter Tables ................................................................37
Table 12. Parameter Table (1): Macronix Flash Parameter Tables .............................................................39
10. POWER-ON STATE.............................................................................................................................................41
11. ELECTRICAL SPECIFICATIONS........................................................................................................................42
11-1. Absolute Maximum Ratings........................................................................................................................42
Figure 7. Maximum Negative Overshoot Waveform...................................................................................42
11-2. Capacitance................................................................................................................................................42
Figure 8. Maximum Positive Overshoot Waveform ....................................................................................42
Figure 9. Input Test Waveforms and Measurement Level ..........................................................................43
Figure 10. Output Loading..........................................................................................................................43
Table 13. DC Characteristics ......................................................................................................................44
Table 14. AC Characteristics.......................................................................................................................45
12. TIMING ANALYSIS ..............................................................................................................................................46
Figure 11. Serial Input Timing.....................................................................................................................46
Figure 12. Output Timing............................................................................................................................46
Figure 13. WP# Setup Timing and Hold Timing during WRSR when SRWD=1.........................................47
Figure 14. Write Enable (WREN) Sequence (Command 06) .....................................................................47
Figure 15. Write Disable (WRDI) Sequence (Command 04)......................................................................48
Figure 16. Read Identification (RDID) Sequence (Command 9F) .............................................................48
Figure 17. Read Status Register (RDSR) Sequence (Command 05) .......................................................48
Figure 18. Write Status Register (WRSR) Sequence (Command 01).......................................................49
Figure 19. Read Data Bytes (READ) Sequence (Command 03) (50MHz)................................................49
Figure 20. Read at Higher Speed (FAST_READ) Sequence (Command 0B) ..........................................50
Figure 21. 2 x I/O Read Mode Sequence (Command BB) .........................................................................50
Figure 22. 4 x I/O Read Mode Sequence (Command EB) ........................................................................51
Figure 23. 4 x I/O Read Enhance Performance Mode Sequence (Command EB) ....................................52
Figure 24. Page Program (PP) Sequence (Command 02) .......................................................................53
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Figure 25. 4 x I/O Page Program (4PP) Sequence (Command 38) ..........................................................53
Figure 26. Sector Erase (SE) Sequence (Command 20) ..........................................................................54
Figure 27. Block Erase 32KB (BE32K) Sequence (Command 52)............................................................54
Figure 28. Block Erase (BE) Sequence (Command D8) ...........................................................................54
Figure 29. Chip Erase (CE) Sequence (Command 60 or C7) ...................................................................54
Figure 30. Deep Power-down (DP) Sequence (Command B9).................................................................55
Figure 31. RDP and Read Electronic Signature (RES) Sequence (Command AB) ..................................55
Figure 32. Release from Deep Power-down (RDP) Sequence (Command AB)........................................56
Figure 33. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90/EF/DF) .......... 56
Figure 34. Read Security Register (RDSCUR) Sequence (Command 2B)................................................57
Figure 35. Write Security Register (WRSCUR) Sequence (Command 2F)................................................57
Figure 36. Power-up Timing .......................................................................................................................58
Table 15. Power-Up Timing and VWI Threshold.........................................................................................58
13. OPERATING CONDITIONS.................................................................................................................................59
Figure 37. AC Timing at Device Power-Up.................................................................................................59
Figure 38. Power-Down Sequence.............................................................................................................60
14. ERASE AND PROGRAMMING PERFORMANCE..............................................................................................61
15. DATA RETENTION ..............................................................................................................................................61
16. LATCH-UP CHARACTERISTICS........................................................................................................................61
17. ORDERING INFORMATION................................................................................................................................62
18. PART NAME DESCRIPTION...............................................................................................................................63
19. PACKAGE INFORMATION..................................................................................................................................64
20. REVISION HISTORY ...........................................................................................................................................67
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MX25U2033E
®
2M-BIT [x 1/x 2/x 4] 1.8V CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY
1. FEATURES
GENERAL
• Single Power Supply Operation
- 1.65 to 2.0 volt for read, erase, and program operations
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• 2,097,152 x 1 bits structure or 1,048,576 x 2 bits (Two I/O read mode) structure or 524,288 x 4 bits (Four I/O
read mode) structure
• 64 Equal Sectors with 4K byte each
- Any Sector can be erased individually
•
8 Equal Blocks with 32K byte each
- Any Block can be erased individually
• 4 Equal Blocks with 64K byte each
- Any Block can be erased individually
• Program Capability
- Byte base
- Page base (256 bytes)
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
- Fast read
- 1 I/O: 80MHz with 8 dummy cycles
- 2 I/O: 80MHz with 4 dummy cycles, equivalent to 160MHz
- 4 I/O: 70MHz with 6 dummy cycles, equivalent to 280MHz;
- Fast program time: 1.2ms (typ.) and 3ms (max.)/page (256-byte per page)
- Byte program time: 10us (typ.)
- Fast erase time
- 30ms(typ.) and 200ms(max.)/sector (4K-byte per sector)
- 200ms(typ.) and 1000ms(max.)/block (32K-byte per block)
- 500ms(typ.) and 2000ms(max.)/block (64K-byte per block)
- 1.25.s(typ.) and 2.5s(max.)/chip
• Low Power Consumption
- Low active read current: 12mA(max.) at 80MHz, 7mA(max.) at 33MHz
- Low active erase/programming current: 25mA (max.)
- Low standby current: 8uA (typ.)/30uA (max.)
• Low Deep Power Down current: 8uA(max.)
• Typical 100,000 erase/program cycles
• 20 years data retention
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block lock protection
The BP0-BP2 status bit defines the size of the area to be software protection against program and erase instruc-
tions
- Additional 4K-bit secured OTP for unique identifier
• Auto Erase and Auto Program Algorithm
Automatically erases and verifies data at selected sector or block
Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse widths (Any page to be programed should have page in the erased state first).
-
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• Status Register Feature
•
Electronic Identification
- JEDEC 1-byte manufacturer ID and 2-byte device ID
- RES command for 1-byte Device ID
- REMS, REMS2 and REMS4 commands for 1-byte manufacturer ID and 1-byte device ID
• Support Serial Flash Discoverable Parameters (SFDP) mode
HARDWARE FEATURES
• SCLK Input
- Serial clock input
• SI/SIO0
- Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
• SO/SIO1
- Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
• WP#/SIO2
- Hardware write protection or serial data Input/Output for 4 x I/O read mode
• HOLD#/SIO3
- HOLD feature, to pause the device without deselecting the device or serial data Input/Output for 4 x I/O read
mode
• PACKAGE
- 8-pin SOP (150mil)
- 8-land USON (4x4mm)
- 8-land WSON (6x5mm)
- All devices are RoHS Compliant and Halogen-free
GENERAL DESCRIPTION
The MX25U2033E is 2,097,152 bit serial Flash memory, which is configured as 1,048,576 x 2 internally. The
MX25U2033E features a serial peripheral interface and software protocol allowing operation on a simple 4-wire bus
while it is in single I/O mode. The four bus signals are a clock input (SCLK), a serial data input (SI), a serial data
output (SO) and a chip select (CS#). Serial access to the device is enabled by CS# input.
When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits
input and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# pin and HOLD# pin become SIO0
pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output.
The MX25U2033E MXSMIO® (Serial Multi I/O) provides sequential read operation on the whole chip.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the
specified page or sector/block locations will be executed. Program command is executed on byte basis, or page
(256 bytes) basis. Erase command is executed on 4K-byte sector, 32K-byte block, or 64K-byte block, or whole chip
basis.
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To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via the WIP bit.
Advanced security features enhance the protection and security functions, please see security features section for
more details.
When the device is not in operation and CS# is high, it is put in standby mode and typically draws 25uA DC current.
The MX25U2033E utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after
100,000 program and erase cycles.
Table 1. Additional Feature Comparison
Protection and Security
Read Performance
Identifier
Additional
Features
REMS/
REMS2/
REMS4
(Command:
90/EF/DF
hex)
Flexible
Block
Protection
(BP0-BP2)
RES
RDID
(Command:
9F hex)
Individual
Protect
4K-bit
secured OTP
Part
Name
2 I/O Read 4 I/O Read (Command:
AB hex)
C2 32 (hex) C2 25 32
(if ADD=0) (hex)
MX25U2033E
V
V
V
V
V
32 (hex)
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2. PIN CONFIGURATIONS
8-LAND USON (4x4mm)
8-PIN SOP (150mil)
1
2
3
4
VCC
CS#
SO/SIO1
WP#/SIO2
GND
8
7
6
5
1
2
3
4
CS#
SO/SIO1
WP#/SIO2
GND
VCC
8
7
6
5
HOLD#/SIO3
SCLK
HOLD#/SIO3
SCLK
SI/SIO0
SI/SIO0
8-LAND WSON (6x5mm)
3. PIN DESCRIPTION
SYMBOL DESCRIPTION
1
VCC
CS#
8
CS#
Chip Select
2
3
4
HOLD#/SIO3
SCLK
SO/SIO1
WP#/SIO2
GND
7
6
5
Serial Data Input (for 1 x I/O)/ Serial
Data Input & Output (for 2xI/O or 4xI/
O read mode)
SI/SIO0
SI/SIO0
Serial Data Output (for 1 x I/O)/ Serial
Data Input & Output (for 2xI/O or 4xI/
O read mode)
SO/SIO1
SCLK
Clock Input
Hardware write protection: connect to
WP#/SIO2 GND or Serial Data Input & Output (for
4x I/O read mode)
To pause the device without
HOLD#/SIO3 deselecting the device or Serial Data
Input & Output (for 4x I/O read mode)
VCC
+ 1.8V Power Supply
GND
Ground
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4. BLOCK DIAGRAM
Address
Generator
Memory Array
Page Buffer
Data
Register
SI/SIO0
Y-Decoder
SRAM
Buffer
Sense
Amplifier
CS#
WP#/SIO2
HOLD#/SIO3
Mode
Logic
State
Machine
HV
Generator
SCLK
Clock Generator
Output
Buffer
SO/SIO1
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5. DATA PROTECTION
During power transition, there may be some false system level signals which result in inadvertent erasure or pro-
gramming. The device is designed to protect itself from these accidental write cycles.
The state machine will be reset as standby mode automatically during power up. In addition, the control register ar-
chitecture of the device constrains that the memory contents can only be changed after specific command sequenc-
es have completed successfully.
In the following, there are several features to protect the system from the accidental write cycles during VCC pow-
erup and power-down or from system noise.
•
•
Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.
Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before is-
suing other commands to change data. The WEL bit will return to resetting stage while the following conditions
occurred:
- Power-up
- Completion of Write Disable (WRDI) command
- Completion of Write Status Register (WRSR) command
- Completion of Page Program (PP) command
- Completion of Quad page program (4PP) command
- Completion of Sector Erase (SE) command
- Completion of Block Erase 32KB (BE32K) command
- Completion of Block Erase (BE) command
- Completion of Chip Erase (CE) command
- Completion of Write Protection Select (WPSEL) command
- Completion of Write Security Register (WRSCUR) command
- Completion of Single Block Lock/Unlock (SBLK/SBULK) command
- Completion of Gang Block Lock/Unlock (GBLK/GBULK) command
•
•
Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writ-
ing all commands except Release from deep power down mode command (RDP) and Read Electronic Signature
command (RES).
Advanced Security Features: there are some protection and security features which protect content from inad-
vertent write and hostile access.
I. Block lock protection
- The Software Protected Mode (SPM) use (BP2, BP1, BP0) bits to allow part of memory to be protected as read
only. The protected area definition is shown as table of "Table 2. Protected Area Sizes", the protected areas are
more flexible which may protect various area by setting value of BP0-BP2 bits.
Please refer to table of "Table 2. Protected Area Sizes".
- The Hardware Protected Mode (HPM) use WP#/SIO2 to protect the (BP2, BP1, BP0) bits and SRWD bit. If the
system goes into four I/O read mode, the feature of HPM will be disabled.
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Table 2. Protected Area Sizes
Status Bit
Protect Level
BP2
0
BP1
0
BP0
0
0 (none, not protected)
0
0
1
1 (1 block, protected block 3)
2 (2 blocks, protected blocks 2~3)
3 (4 blocks, protected all blocks)
4 (4 blocks, protected all blocks)
5 (2 blocks, protected blocks 0~1)
6 (3 blocks, protected blocks 0~2)
7 (4 blocks, protected all blocks)
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
II. Additional 4K-bit secured OTP for unique identifier: to provide 4K-bit One-Time Program area for setting de-
vice unique serial number - Which may be set by factory or system maker. Please refer to "Table 3. 4K-bit Se-
cured OTP Definition".
- Security register bit 0 indicates whether the chip is locked by factory or not.
- To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with ENSO command), and going
through normal program procedure, and then exiting 4K-bit secured OTP mode by writing EXSO command.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register)
command to set customer lock-down bit1 as "1". Please refer to "Table 9. Security Register Definition" for secu-
rity register bit definition and "Table 3. 4K-bit Secured OTP Definition" for address range definition.
Note:
Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit Secured OTP
mode, array access is not allowed.
Table 3. 4K-bit Secured OTP Definition
Address range
Size
Standard Factory Lock
Customer Lock
xxx000~xxx00F
xxx010~xxx1FF
128-bit
ESN (electrical serial number)
N/A
Determined by customer
3968-bit
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6. MEMORY ORGANIZATION
Table 4. Memory Organization
Block
(64KB)
Block
(32KB)
Sector
(4KB)
Address Range
03F000h 03FFFFh
63
:
48
47
:
32
31
:
▲
7
|
6
Individual Sector Lock/Unlock
3
2
1
:
:
▼
030000h
02F000h
:
030FFFh
02FFFFh
:
▲
5
|
4
020000h
01F000h
:
020FFFh
01FFFFh
:
Individual Block Lock/Unlock
3
|
▼
▲
2
16
15
:
2
1
010000h
00F000h
:
002000h
001000h
000000h
010FFFh
00FFFFh
:
002FFFh
001FFFh
000FFFh
1
|
0
Individual Sector Lock/Unlock
0
▼
0
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7. DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended op-
eration.
2. When incorrect command is inputted to this device, it enters standby mode and remains in standby mode until
next CS# falling edge. In standby mode, SO pin of the device is High-Z.
3. When correct command is inputted to this device, it enters active mode and remains in active mode until next
CS# rising edge.
4. Input data is latched on the rising edge of Serial Clock (SCLK) and data is shifted out on the falling edge of
SCLK. The difference of Serial mode 0 and mode 3 is shown as "Figure 1. Serial Modes Supported" .
5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, RDSFDP, 2READ, 4READ, RES,
REMS, REMS2, and REMS4, the shifted-in instruction sequence is followed by a data-out sequence. After any
bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE,
BE32K, BE, CE, PP, 4PP, RDP, DP, WPSEL, SBLK, SBULK, GBLK, GBULK,ENSO, EXSO, and WRSCUR, the
CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
6. While a Write Status Register, Program or Erase operation is in progress, access to the memory array is ne-
glected and will not affect the current operation of WRSCUR, WPSEL Write Status Register, Program and Erase.
Figure 1. Serial Modes Supported
CPOL CPHA
shift in
shift out
SCLK
SCLK
(Serial mode 0)
(Serial mode 3)
0
1
0
1
SI
MSB
SO
MSB
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is
supported.
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8. HOLD FEATURE
HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the
operation of write status register, programming, or erasing in progress.
The operation of HOLD requires Chip Select (CS#) keeping low and starts on falling edge of HOLD# pin signal while
Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start until Se-
rial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Serial Clock (SCLK)
signal is being low (if Serial Clock signal is not being low, HOLD operation will not end until Serial Clock being low),
see "Figure 2. Hold Condition Operation".
Figure 2. Hold Condition Operation
CS#
SCLK
HOLD#
Hold
Hold
Condition
(standard)
Condition
(non-standard)
The Serial Data Output (SO) is high impedance, both Serial Data Input (SI) and Serial Clock (SCLK) are don't care
during the HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of
the device. To re-start communication with chip, the HOLD# must be at high and CS# must be at low.
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9. COMMAND DESCRIPTION
Table 5. Command Set
Read Commands
I/O
1
1
1
2
4
2READ
(2 x I/O read
command)
4READ
(4 x I/O read
command)
Command
(byte)
READ
FAST READ
RDSFDP
(normal read) (fast read data) (Read SFDP)
Clock rate
(MHz)
50
80
80
80
70
1st byte
2nd byte
3rd byte
4th byte
5th byte
03 (hex)
AD1
AD2
0B (hex)
AD1
AD2
AD3
Dummy
n bytes read
5A (hex)
AD1
AD2
BB (hex)
AD1
AD2
AD3
Dummy
n bytes read
EB (hex)
AD1
AD2
AD3
Dummy
n bytes read
AD3
AD3
Dummy
Read SFDP
mode
n bytes read
out until CS# out until CS#
goes high goes high
out by 2 x I/O out by 4 x I/O
until CS# goes until CS# goes
Action
high
high
Program/Erase Commands
RDSR
(read status
register)
WRSR
(write status
register)
01 (hex)
Values
BE 32K
(block erase
32KB)
52 (hex)
AD1
BE
(block erase
64KB)
D8 (hex)
AD1
Command
(byte)
WREN
WRDI
SE
(write enable) (write disable)
(sector erase)
1st byte
2nd byte
3rd byte
4th byte
06 (hex)
04 (hex)
05 (hex)
20 (hex)
AD1
AD2
AD2
AD3
AD2
AD3
AD3
sets the (WEL)
write enable
latch bit
resets the
(WEL) write
enable latch bit status register status register
to read out the to write new
values of the values of the selected sector selected 32KB selected block
block
to erase the
to erase the
to erase the
Action
RDP
(Release from
deep power
down)
4PP
(Quad page
program)
DP
Command
(byte)
CE
PP
(Deep power
down)
(chip erase) (page program)
1st byte
2nd byte
3rd byte
4th byte
60 or C7 (hex)
02 (hex)
AD1
AD2
38 (hex)
AD1
AD2
B9 (hex)
AB (hex)
AD3
AD3
to erase whole to program the quad input to
enters deep
power down
mode
release from
deep power
down mode
chip
selected page program the
selected page
Action
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MX25U2033E
Security/ID/Mode Setting/Reset Commands
Command
(byte)
RDID
(read
identific-
ation)
RES (read REMS (read REMS2 (read REMS4 (read ENSO (enter EXSO (exit
electronic
ID)
electronic ID for 2x I/O ID for 4x I/O
secured
OTP)
secured
OTP)
manufacturer
& device ID)
mode)
mode)
1st byte
2nd byte
3rd byte
4th byte
9F (hex)
AB (hex)
90 (hex)
EF (hex)
DF (hex)
B1 (hex)
C1 (hex)
x
x
x
x
x
X
X
ADD
x
x
ADD
ADD
outputs
JEDEC
to read out
output the
output the
output the
to enter
to exit
the 4K-bit
1-byte Device Manufacturer Manufacturer Manufacturer the 4K-bit
ID: 1-byte
Manufacturer
ID & 2-byte
Device ID
ID
ID & Device ID & Device ID & Device secured OTP secured OTP
ID ID ID mode mode
Action
Command
(byte)
RDSCUR
WRSCUR
SBLK
SBULK
RDBLOCK
GBLK
GBULK
(gang block
unlock)
(read security (write security (single block (single block (block protect (gang block
register)
2B (hex)
register)
2F (hex)
lock
36 (hex)
AD1
AD2
AD3
unlock)
39 (hex)
AD1
AD2
AD3
read)
3C (hex)
AD1
AD2
AD3
lock)
7E (hex)
1st byte
2nd byte
3rd byte
4th byte
Action
98 (hex)
to read value to set the lock- individual block individual block read individual
of security
register
whole chip
whole chip
unprotect
down bit as
(64K-byte) or (64K-byte) or block or sector write protect
"1" (once lock- sector (4K-byte) sector (4K-byte) write protect
down, cannot
be update)
write protect
unprotect
status
Command
(byte)
WPSEL
(Write Protect
Selection)
1st byte
2nd byte
3rd byte
4th byte
Action
68 (hex)
to enter and
enable individal
block protect
mode
Note
1: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first.
2: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the
hidden mode.
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MX25U2033E
9-1.
Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP,
SE, BE32K, BE, CE, WPSEL, WRSCUR, SBLK, SBULK, GBLK, GBULK and WRSR, which are intended to change
the device content WEL bit should be set every time after the WREN instruction setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low→sending WREN instruction code→ CS# goes high.
(Please refer to "Figure 14. Write Enable (WREN) Sequence (Command 06)")
9-2.
Write Disable (WRDI)
The Write Disable (WRDI) instruction is to reset Write Enable Latch (WEL) bit.
The sequence of issuing WRDI instruction is: CS# goes low→sending WRDI instruction code→CS# goes high.
(Please refer to "Figure 15. Write Disable (WRDI) Sequence (Command 04)")
The WEL bit is reset by following situations:
- Power-up
- Completion of Write Disable (WRDI) instruction
- Completion of Write Status Register (WRSR) instruction
- Completion of Page Program (PP) instruction
- Completion of Quad Page Program (4PP) instruction
- Completion of Sector Erase (SE) instruction
- Completion of Block Erase 32KB (BE32K) instruction
- Completion of Block Erase (BE) instruction
- Completion of Chip Erase (CE) instruction
- Completion of Write Protection Select (WPSEL) instruction
- Completion of Write Security Register (WRSCUR) instruction
- Completion of Single Block Lock/Unlock (SBLK/SBULK) instruction
- Completion of Gang Block Lock/Unlock (GBLK/GBULK) instruction
9-3.
Read Identification (RDID)
The RDID instruction is to read the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC Manu-
facturer ID is C2(hex), the memory type ID is 25(hex) as the first-byte device ID, and the individual device ID of
second-byte ID are listed as table of "ID Definitions". (Please refer to "Table 8. ID Definitions")
The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code→24-bits ID data out
on SO→ to end RDID operation can drive CS# to high at any time during data out. (Please refer to "Figure 16. Read
Identification (RDID) Sequence (Command 9F)")
While Program/Erase operation is in progress, it will not decode the RDID instruction, therefore there's no effect on
the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby
stage.
9-4.
Read Status Register (RDSR)
The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in
program/erase/WPSEL/WRSCUR/write status register condition). It is recommended to check the Write in Progress (WIP)
bit before sending a new instruction when a program, erase, or write status register operation is in progress.
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The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register data
out on SO. (Please refer to "Figure 17. Read Status Register (RDSR) Sequence (Command 05)")
For user to check if Program/Erase operation is finished or not, RDSR instruction flow are shown as follows:
Program/ Erase Flow with Read Array Data
start
WREN command
RDSR command*
No
WREN=1?
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
No
WIP=0?
Yes
RDSR command
Read WEL=0, BP[3:0], QE,
and SRWD data
Read array data
(same address of PGM/ERS)
No
Verify OK?
Yes
Program/erase successfully
Program/erase fail
Yes
Program/erase
another block?
* Issue RDSR to check BP[3:0].
* If WPSEL = 1, issue RDBLOCK to check the block status.
No
Program/erase completed
P/N: PM1743
REV. 1.3, NOV. 14, 2013
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MX25U2033E
Program/ Erase Flow without Read Array Data (read P_FAIL/E_FAIL flag)
start
WREN command
RDSR command*
No
WREN=1?
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
No
WIP=0?
Yes
RDSR command
Read WEL=0, BP[3:0], QE,
and SRWD data
RDSCUR command
Yes
P_FAIL/E_FAIL=1 ?
No
Program/erase successfully
Program/erase fail
Yes
Program/erase
another block?
* Issue RDSR to check BP[3:0].
* If WPSEL = 1, issue RDBLOCK to check the block status.
No
Program/erase completed
P/N: PM1743
REV. 1.3, NOV. 14, 2013
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MX25U2033E
WRSR Flow
start
WREN command
RDSR command
No
WREN=1?
Yes
WRSR command
Write status register data
RDSR command
No
WIP=0?
Yes
RDSR command
Read WEL=0, BP[3:0], QE,
and SRWD data
No
Verify OK?
Yes
WRSR successfully
WRSR fail
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REV. 1.3, NOV. 14, 2013
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MX25U2033E
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write sta-
tus register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register
progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register
cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable
latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/
erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device
will not accept program/erase/write status register instruction. The program/erase command will be ignored if it is ap-
plied to a protected memory area. To ensure both WIP bit & WEL bit are both set to 0 and available for next program/
erase/operations, WIP bit needs to be confirm to be 0 before polling WEL bit. After WIP bit confirmed, WEL bit needs
to be confirm to be 0.
BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area (as defined
in "Table 2. Protected Area Sizes") of the device to against the program/erase instruction without hardware protection
mode being set. To write the Block Protect (BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction
to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE),
Block Erase 32KB (BE32K), Block Erase (BE) and Chip Erase (CE) instructions (only if Block Protect bits (BP2:BP0)
set to 0, the CE instruction can be executed). The BP2, BP1, BP0 bits are "0" as default. Which is un-protected.
QE bit. The Quad Enable (QE) bit, non-volatile bit, while it is "0" (factory default), it performs non-Quad and WP# is
enable. While QE is "1", it performs Quad I/O mode and WP# is disabled. In the other word, if the system goes into
four I/O mode (QE=1), the features of HPM and HOLD will be disabled.
SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection
(WP#/SIO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and
WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is
no longer accepted for execution and the SRWD bit and Block Protect bits (BP2, BP1, BP0) are read only. The SRWD
bit defaults to be "0".
Table 6. Status Register
bit7
bit6
bit5
bit4
BP2
(level of
protected
block)
bit3
BP1
(level of
protected
block)
bit2
BP0
(level of
protected
block)
bit1
bit0
SRWD (status
register write
protect)
QE
(Quad
Enable)
WEL
(write enable
latch)
WIP
(write in
progress bit)
0
1=Quad
Enable
0=not Quad
Enable
1=write
enable
0=not write 0=not in write
1=write
operation
1=status
register write
disable
0
(note 1)
(note 1)
(note 1)
enable
operation
Non-volatile Non-volatile Non-volatile Non-volatile Non-volatile Non-volatile
bit bit bit bit bit bit
volatile bit
volatile bit
Note 1: see the "Table 2. Protected Area Sizes".
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MX25U2033E
9-5.
Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the
Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in ad-
vance. The WRSR instruction can change the value of Block Protect (BP2, BP1, BP0) bits to define the protected
area of memory (as shown in "Table 2. Protected Area Sizes"). The WRSR also can set or reset the Quad enable
(QE) bit and set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#/
SIO2) pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of the status register. The WRSR instruction cannot
be executed once the Hardware Protected Mode (HPM) is entered.
The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register
data on SI→CS# goes high. (Please refer to "Figure 18. Write Status Register (WRSR) Sequence (Command 01)"
)
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1
during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL)
bit is reset.
Table 7. Protection Modes
Mode
Status register condition
WP# and SRWD bit status
Memory
Status register can be written
in (WEL bit is set to "1") and
the SRWD, BP0-BP2
Software protection
mode (SPM)
WP#=1 and SRWD bit=0, or
WP#=0 and SRWD bit=0, or
WP#=1 and SRWD=1
The protected area
cannot
be program or erase.
bits can be changed
The SRWD, BP0-BP2 of
status register bits cannot be
changed
The protected area
cannot
be program or erase.
Hardware protection
mode (HPM)
WP#=0, SRWD bit=1
Note:
1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in "Table 2.
Protected Area Sizes".
As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM).
Software Protected Mode (SPM):
-
-
When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can
change the values of SRWD, BP2, BP1, BP0. The protected area, which is defined by BP2, BP1, BP0, is at
software protected mode (SPM).
When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values of
SRWD, BP2, BP1, BP0. The protected area, which is defined by BP2, BP1, BP0, is at software protected mode (SPM)
Note:
If SRWD bit=1 but WP#/SIO2 is low, it is impossible to write the Status Register even if the WEL bit has previously
been set. It is rejected to write the Status Register and not be executed.
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MX25U2033E
Hardware Protected Mode (HPM):
-
When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware
protected mode (HPM). The data of the protected area is protected by software protected mode by BP2, BP1,
BP0 and hardware protected mode by the WP#/SIO2 to against data modification.
Note:
To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered.
If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be entered; only
can use software protected mode via BP2, BP1, BP0.
If the system enter Quad I/O QE=1, the feature of HPM will be disabled.
9-6.
Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on
the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address
is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can
be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been
reached.
The sequence of issuing READ instruction is: CS# goes low→sending READ instruction code→ 3-byte address
on SI→ data out on SO→to end READ operation can use CS# to high at any time during data out. (Please refer to
"Figure 19. Read Data Bytes (READ) Sequence (Command 03) (50MHz)")
9-7.
Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at
any location. The address is automatically increased to the next higher address after each byte data is shifted out,
so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when
the highest address has been reached.
The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code→
3-byte address on SI→1-dummy byte (default) address on SI→ data out on SO→ to end FAST_READ operation
can use CS# to high at any time during data out. (Please refer to "Figure 20. Read at Higher Speed (FAST_READ)
Sequence (Command 0B)")
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any im-
pact on the Program/Erase/Write Status Register current cycle.
9-8.
2 x I/O Read Mode (2READ)
The 2READ instruction enable double throughput of Serial Flash in read mode. The address is latched on rising
edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maxi-
mum frequency fT. The first address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ instruc-
tion. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ instruc-
tion, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit.
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MX25U2033E
The sequence of issuing 2READ instruction is: CS# goes low sending 2READ instruction 24-bit address inter-
→
→
leave on SIO1 & SIO0 4 dummy cycles on SIO1 & SIO0 data out interleave on SIO1 & SIO0 to end 2READ
→
→
→
operation can use CS# to high at any time during data out (Please refer to "Figure 21. 2 x I/O Read Mode Sequence
(Command BB)").
While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact on
the Program/Erase/Write Status Register current cycle.
9-9.
4 x I/O Read Mode (4READ)
The 4READ instruction enable quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status Reg-
ister must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCLK, and
data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ.
The first address byte can be at any location. The address is automatically increased to the next higher address af-
ter each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address
counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following
address/dummy/data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing 4READ instruction is: CS# goes low sending 4READ instruction 24-bit address inter-
→
→
leave on SIO3, SIO2, SIO1 & SIO0 2+4 dummy cycles data out interleave on SIO3, SIO2, SIO1 & SIO0 to end
→
→
→
4READ operation can use CS# to high at any time during data out. (Please refer to "Figure 22. 4 x I/O Read Mode
Sequence (Command EB)")
While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact on
the Program/Erase/Write Status Register current cycle.
P/N: PM1743
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MX25U2033E
9-10. Performance Enhance Mode
The device could waive the command cycle bits if the two cycle bits after address cycle toggles. (Please note Figure
22. 4 x I/O Read Enhance Performance Mode Sequence (Command EB)")
After entering enhance mode, following CS# go high, the device will stay in the read mode and treat CS# go low of
the first clock as address instead of command cycle.
Another sequence of issuing 4READ instruction especially useful in random access is : CS# goes low sending 4
→
READ instruction 3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 performance enhance toggling bit
→
→
P[7:0] 4 dummy cycles data out still CS# goes high
CS# goes low (reduce 4Read instruction) 24-bit ran-
→
→
→
→
dom access address (Please refer to "Figure 23. 4 x I/O Read Enhance Performance Mode Sequence (Command
EB)").
In the performance-enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh can
make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0]; like-
wise P[7:0]=FFh,00h,AAh or 55h and afterwards CS# is raised and then lowered, the system then will escape from
performance enhance mode and return to normal operation.
9-11. Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for
any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before
sending the Sector Erase (SE). Any address of the sector (see "Table 4. Memory Organization") is a valid address
for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of the
address been latched-in); otherwise, the instruction will be rejected and not executed.
Address bits [Am-A12] (Am is the most significant address) select the sector address.
The sequence of issuing SE instruction is: CS# goes low→ sending SE instruction code→ 3-byte address on SI→
CS# goes high. (Please refer to "Figure 26. Sector Erase (SE) Sequence (Command 20)")
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets during the tSE
timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
sector is protected by BP2 ~ 0 (WPSEL=0) or by individual lock (WPSEL=1), the Sector Erase (SE) instruction will
not be executed on the sector.
P/N: PM1743
REV. 1.3, NOV. 14, 2013
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MX25U2033E
9-12. Block Erase (BE32K)
The Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1". The instruction is used
for 32K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable
Latch (WEL) bit before sending the Block Erase (BE32K). Any address of the block (see "Table 4. Memory Organi-
zation") is a valid address for Block Erase (BE32K) instruction. The CS# must go high exactly at the byte boundary (the
least significant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE32K instruction is: CS# goes low→ sending BE32K instruction code→ 3-byte address
on SI→CS# goes high. (Please refer to "Figure 27. Block Erase 32KB (BE32K) Sequence (Command 52)")
The self-timed Block Erase Cycle time (tBE32K) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while he Block Erase cycle is in progress. The WIP sets during the tBE32K
timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
block is protected by BP2 ~ 0 (WPSEL=0) or by individual lock (WPSEL=1), the Block Erase (tBE32K) instruction
will not be executed on the block.
9-13. Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used
for 64K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable
Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (Please refer to "Table 4. Memory
Organization") is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the
least significant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE instruction is: CS# goes low→ sending BE instruction code→ 3-byte address on SI→
CS# goes high. (Please refer to "Figure 28. Block Erase (BE) Sequence (Command D8)")
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during the tBE
timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
block is protected by BP2 ~ 0 (WPSEL=0) or by individual lock (WPSEL=1), the Block Erase (BE) instruction will not
be executed on the block.
9-14. Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruc-
tion must be executed to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must
go high exactly at the byte boundary, otherwise the instruction will be rejected and not executed.
The sequence of issuing CE instruction is: CS# goes low→sending CE instruction code→CS# goes high. (Please
refer to "Figure 29. Chip Erase (CE) Sequence (Command 60 or C7)")
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Chip Erase cycle is in progress. The WIP sets during the tCE tim-
ing, and clears when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the chip is
protected by BP2 ~ 0 (WPSEL=0) or by individual lock (WPSEL=1), the Chip Erase (CE) instruction will not be ex-
ecuted. It will be only executed when BP2, BP1, BP0 all set to "0".
P/N: PM1743
REV. 1.3, NOV. 14, 2013
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9-15. Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction
must be executed to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device pro-
grams only the last 256 data bytes sent to the device. If the entire 256 data bytes are going to be programmed, A7-
A0 (the eight least significant address bits) should be cleared. The last address byte (the 8 least significant address
bits, A7-A0) should be set to 0 for 256 bytes page program. If A7-A0 are not all zero, transmitted data that exceed
page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently selected
page. If the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the request page
and previous data will be disregarded. If the data bytes sent to the device has not exceeded 256, the data will be
programmed at the request address of the page. There will be no effort on the other data bytes of the same page.
The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→ at
least 1-byte on data on SI→ CS# goes high. (Please refer to "Figure 24. Page Program (PP) Sequence (Command
02)")
The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte
boundary (the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be ex-
ecuted.
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Page Program cycle is in progress. The WIP sets during the tPP
timing, and clears when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
page is protected by BP2 ~ 0 (WPSEL=0) or by individual lock (WPSEL=1), the Page Program (PP) instruction will
not be executed.
9-16. 4 x I/O Page Program (4PP)
The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN) in-
struction must be executed to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1"
before sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1, SIO2,
and SIO3 as address and data input, which can improve programmer performance and the effectiveness of applica-
tion of lower clock less than 70MHz. For system with faster clock, the Quad page program cannot provide more per-
formance, because the required internal page program time is far more than the time data flows in. Therefore, we
suggest that while executing this command (especially during sending data), user can slow the clock speed down to
70MHz below. The other function descriptions are as same as standard page program.
The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on
SIO[3:0]→ at least 1-byte on data on SIO[3:0]→CS# goes high. (Please refer to "Figure 25. 4 x I/O Page Program (4PP)
Sequence (Command 38)")
If the page protected by BP2 ~ 0 (WPSEL=0) or by individual lock (WPSEL=1), the Quad page program (4PP)
instruction will not be executed.
9-17. Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device to minimize the power consumption (the standby
current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruc-
tion to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction
are ignored.
The sequence of issuing DP instruction is: CS# goes low→sending DP instruction code→CS# goes high.
(Please refer to "Figure 30. Deep Power-down (DP) Sequence (Command B9)")
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Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP)
and Read Electronic Signature (RES) instruction. (Those instructions allow the ID being reading out). When Power-
down, or software reset command the deep power-down mode automatically stops, and when power-up, the device
automatically is in standby mode. For DP instruction the CS# must go high exactly at the byte boundary (the latest
eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#)
goes high, a delay of tDP is required before entering the Deep Power-down mode.
9-18. Release from Deep Power-down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is completed by driving Chip Select (CS#) High. When Chip
Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the
Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in
the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip Se-
lect (CS#) must remain High for at least tRES2 (max), as specified in "Table 14. AC Characteristics". AC Character-
istics. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute
instructions. The RDP instruction is only for releasing from Deep Power Down Mode.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID
Definitions on next page. This is not the same as RDID instruction. It is not recommended to use for new design.
For new design, please use RDID instruction.
The sequence is shown as "Figure 31. RDP and Read Electronic Signature (RES) Sequence (Command AB)" and
"Figure 32. Release from Deep Power-down (RDP) Sequence (Command AB)". Even in Deep power-down mode,
the RDP and RES are also allowed to be executed, only except the device is in progress of program/erase/write cy-
cle; there's no effect on the current program/erase/write cycle in progress.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeat-
edly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously
in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in
Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least
tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute
instruction.
9-19. Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4)
The REMS, REMS2 and REMS4 instruction provides both the JEDEC assigned Manufacturer ID and the specific
Device ID.
The instruction is initiated by driving the CS# pin low and shift the instruction code "90h", "DFh" or "EFh" followed
by two dummy bytes and one bytes address (A7~A0). After which, the Manufacturer ID for MXIC (C2h) and the De-
vice ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in "Figure 33. Read
Electronic Manufacturer & Device ID (REMS) Sequence (Command 90/EF/DF)". The Device ID values are listed in
table of ID Definitions. If the one-byte address is initially set to 01h, then the Device ID will be read first and then fol-
lowed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to
the other. The instruction is completed by driving CS# high.
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Table 8. ID Definitions
Command Type
MX25U2033E
memory type
25
electronic ID
32
manufacturer ID
C2
memory density
32
RDID (JEDEC ID)
RES
manufacturer ID
C2
device ID
32
REMS/REMS2/REMS4
9-20. Enter Secured OTP (ENSO)
The ENSO instruction is for entering the additional 4K-bit secured OTP mode. While device is in 4K-bit secured
OTP mode, main array access is not available. The additional 4K-bit secured OTP is independent from main array,
and may be used to store unique serial number for system identifier. After entering the Secured OTP mode, follow
standard read or program procedure to read out the data or update data. The Secured OTP data cannot be updated
again once it is lock-down.
The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP
mode→ CS# goes high.
Please note that WRSR/WRSCUR/WPSEL commands are not acceptable during the access of secure OTP region,
once security OTP is lock down, only read related commands are valid.
9-21. Exit Secured OTP (EXSO)
The EXSO instruction is for exiting the additional 4K-bit secured OTP mode.
The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP
mode→ CS# goes high.
9-22. Read Security Register (RDSCUR)
The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read
at any time (even in program/erase/write status register/write security register condition) and continuously.
The sequence of issuing RDSCUR instruction is : CS# goes low→sending RDSCUR instruction→Security Register
data out on SO→ CS# goes high. (Please see "Figure 34. Read Security Register (RDSCUR) Sequence (Command
2B)")
The definition of the Security Register bits is as below:
Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory or not. When it is
"0", it indicates non-factory lock; "1" indicates factory-lock.
Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for cus-
tomer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 4K-bit Secured OTP
area cannot be updated any more.
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Table 9. Security Register Definition
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
LDSO
(indicate if
lock-down)
Secured OTP
indicator bit
WPSEL
E_FAIL
P_FAIL
Reserved
Reserved
Reserved
0=normal
Program
succeed
1=indicate
Program
failed
0 = not lock-
down
1 = lock-down
(cannot
program/
erase
0=normal
Erase
succeed
1=individual
Erase failed
(default=0)
0=normal
WP mode
1=individual
mode
0 = non-
factory
lock
1 = factory
lock
-
-
-
(default=0)
(default=0)
OTP)
Non-volatile
bit
Non-volatile
bit (OTP)
Non-volatile
bit (OTP)
Volatile bit
Volatile bit
Volatile bit
Volatile bit
Volatile bit
(OTP)
9-23. Write Security Register (WRSCUR)
The WRSCUR instruction is for setting the values of Security Register Bits. The WREN (Write Enable) instruction is
required before issuing WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO bit)
for customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area
cannot be updated any more. The LDSO bit is an OTP bit. Once the LDSO bit is set, the value of LDSO bit can not
be altered any more.
The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high.
(Please see "Figure 35. Write Security Register (WRSCUR) Sequence (Command 2F)".)
The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
9-24. Write Protection Selection (WPSEL)
When the system accepts and executes WPSEL instruction, bit 7 in the security register will be set. The WREN (Write
Enable) instruction is required before issuing WPSEL instruction. It will activate SBLK, SBULK, RDBLOCK, GBLK,
GBULK etc instructions to conduct block lock protection and replace the original Software Protect Mode (SPM) use
(BP2~BP0) indicated block methods.
The sequence of issuing WPSEL instruction is: CS# goes low → sending WPSEL instruction to enter the individual
block protect mode→ CS# goes high.
Every time after the system is powered-on, the Security Register bit 7 is checked. If WPSEL=1, then all the blocks
and sectors will be write-protected by default. User may only unlock the blocks or sectors via SBULK and GBULK
instructions. Program or erase functions can only be operated after the Unlock instruction is executed.
Once WPSEL is set, it cannot be changed.
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WPSEL instruction function flow is as follows:
Figure 3. WPSEL Flow
start
WREN command
RDSCUR(2Bh) command
Yes
WPSEL=1?
No
WPSEL disable,
block protected by BP[3:0]
WPSEL(68h) command
RDSR command
No
WIP=0?
Yes
RDSCUR(2Bh) command
No
WPSEL=1?
Yes
WPSEL set successfully
WPSEL set fail
WPSEL enable.
Block protected by individual lock
(SBLK, SBULK,
… etc).
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9-25. Single Block Lock/Unlock Protection (SBLK/SBULK)
These instructions are only effective after WPSEL was executed. The SBLK instruction is for write protection a
specified block (or sector) of memory, using AMAX-A16 or (AMAX-A12) address bits to assign a 64Kbyte block (or 4K
bytes sector) to be protected as read only. The SBULK instruction will cancel the block (or sector) write protection
state. This feature allows user to stop protecting the entire block (or sector) through the chip unprotect command
(GBULK).
The WREN (Write Enable) instruction is required before issuing SBLK/SBULK instruction.
The sequence of issuing SBLK/SBULK instruction is: CS# goes low → send SBLK/SBULK (36h/39h)
instruction→send 3 address bytes assign one block (or sector) to be protected on SI pin → CS# goes high. The CS#
must go high exactly at the byte boundary, otherwise the instruction will be rejected and not be executed.
SBLK/SBULK instruction function flow is as follows:
Figure 4. Block Lock Flow
Start
RDSCUR(2Bh) command
No
WPSEL=1?
WPSEL command
Yes
WREN command
SBLK command
( 36h + 24bit address )
RDSR command
No
WIP=0?
Yes
RDBLOCK command
( 3Ch + 24bit address )
No
Data = FFh ?
Yes
Block lock successfully
Block lock fail
Yes
Lock another block?
No
Block lock completed
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Figure 5. Block Unlock Flow
start
RDSCUR(2Bh) command
No
WPSEL=1?
Yes
WPSEL command
WREN command
SBULK command
( 39h + 24bit address )
RDSR command
WIP=0?
No
Yes
Yes
Unlock another block?
Unlock block completed?
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9-26. Read Block Lock Status (RDBLOCK)
This instruction is only effective after WPSEL was executed. The RDBLOCK instruction is for reading the status
of protection lock of a specified block (or sector), using AMAX-A16 (or AMAX-A12) address bits to assign a 64K bytes
block (4K bytes sector) and read protection lock status bit which the first byte of Read-out cycle. The status bit is "1"
to indicate that this block has be protected, that user can read only but cannot write/program /erase this block. The
status bit is "0" to indicate that this block hasn't be protected, and user can read and write this block.
The sequence of issuing RDBLOCK instruction is: CS# goes low → send RDBLOCK (3Ch) instruction → send 3
address bytes to assign one block on SI pin → read block's protection lock status bit on SO pin → CS# goes high.
9-27. Gang Block Lock/Unlock (GBLK/GBULK)
These instructions are only effective after WPSEL was executed. The GBLK/GBULK instruction is for enable/disable
the lock protection block of the whole chip.
The WREN (Write Enable) instruction is required before issuing GBLK/GBULK instruction.
The sequence of issuing GBLK/GBULK instruction is: CS# goes low → send GBLK/GBULK (7Eh/98h) instruction
→CS# goes high.
The CS# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed.
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9-28. Read SFDP Mode (RDSFDP)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the
functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These
parameter tables can be interrogated by host system software to enable adjustments needed to accommodate
divergent features from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC
Standard, JESD68 on CFI.
The sequence of issuing RDSFDP instruction is CS# goes low→send RDSFDP instruction (5Ah)→send 3 address
bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP operation can use CS#
to high at any time during data out.
SFDP is a standard of JEDEC. JESD216. v1.0.
Figure 6. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
SCLK
Command
5Ah
24 BIT ADDRESS
SI
23 22 21
3
2
1
0
High-Z
SO
CS#
47
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
SCLK
Dummy Cycle
7
6
5
4
3
2
0
1
SI
DATA OUT 2
DATA OUT 1
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
SO
MSB
MSB
MSB
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Table 10. Signature and Parameter Identification Data Values
Add (h) DW Add Data (h/b) Data
Description
Comment
(Byte)
(Bit)
(Note1)
(h)
00h
07:00
53h
53h
01h
02h
03h
04h
05h
06h
15:08
23:16
31:24
07:00
15:08
23:16
46h
44h
50h
00h
01h
01h
46h
44h
50h
00h
01h
01h
SFDP Signature
Fixed: 50444653h
SFDP Minor Revision Number
SFDP Major Revision Number
Number of Parameter Headers
Start from 00h
Start from 01h
Start from 01h
Unused
07h
08h
09h
0Ah
0Bh
31:24
07:00
15:08
23:16
31:24
FFh
00h
00h
01h
09h
FFh
00h
00h
01h
09h
00h: it indicates a JEDEC specified
header.
ID number (JEDEC)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length
(in double word)
Start from 00h
Start from 01h
How many DWORDs in the
Parameter table
0Ch
0Dh
0Eh
07:00
15:08
23:16
30h
00h
00h
30h
00h
00h
First address of JEDEC Flash
Parameter table
Parameter Table Pointer (PTP)
Unused
0Fh
10h
11h
12h
13h
31:24
07:00
15:08
23:16
31:24
FFh
C2h
00h
01h
04h
FFh
C2h
00h
01h
04h
ID number
(Macronix manufacturer ID)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
it indicates Macronix manufacturer
ID
Start from 00h
Start from 01h
Parameter Table Length
(in double word)
How many DWORDs in the
Parameter table
14h
15h
16h
07:00
15:08
23:16
60h
00h
00h
60h
00h
00h
First address of Macronix Flash
Parameter table
Parameter Table Pointer (PTP)
Unused
17h
31:24
FFh
FFh
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Table 11. Parameter Table (0): JEDEC Flash Parameter Tables
Add (h) DW Add Data (h/b)
Data
(h)
Description
Comment
(Byte)
(Bit)
(Note1)
00: Reserved, 01: 4KB erase,
10: Reserved,
Block/Sector Erase sizes
01:00
01b
11: not suport 4KB erase
Write Granularity
0: 1Byte, 1: 64Byte or larger
02
03
1b
0b
Write Enable Instruction
Requested for Writing to Volatile 1: Volatitle status bit
0: Nonvolatitle status bit
Status Registers
(BP status register bit)
30h
E5h
0: use 50h opcode,
1: use 06h opcode
Write Enable Opcode Select for
Writing to Volatile Status Registers
Note: If target flash status register
is nonvolatile, then bits 3 and 4
must be set to 00b.
04
0b
Contains 111b and can never be
changed
Unused
07:05
111b
4KB Erase Opcode
31h
32h
33h
15:08
16
20h
0b
20h
B0h
FFh
(1-1-2) Fast Read (Note2)
0=not support 1=support
Address Bytes Number used in
addressing flash array
00: 3Byte only, 01: 3 or 4Byte,
10: 4Byte only, 11: Reserved
18:17
19
00b
0b
Double Transfer Rate (DTR)
Clocking
0=not support 1=support
(1-2-2) Fast Read
(1-4-4) Fast Read
(1-1-4) Fast Read
Unused
0=not support 1=support
0=not support 1=support
0=not support 1=support
20
21
1b
1b
22
0b
23
1b
Unused
31:24
FFh
Flash Memory Density
37h:34h 31:00
001FFFFFh
(1-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
04:00
38h
0 0100b
states (Note3)
Clocks) not support
44h
EBh
00h
FFh
(1-4-4) Fast Read Number of
Mode Bits (Note4)
000b: Mode Bits not support
07:05
010b
EBh
(1-4-4) Fast Read Opcode
39h
3Ah
3Bh
15:08
20:16
(1-1-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
0 0000b
states
Clocks) not support
(1-1-4) Fast Read Number of
Mode Bits
000b: Mode Bits not support
23:21
31:24
000b
FFh
(1-1-4) Fast Read Opcode
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Add (h) DW Add Data (h/b) Data
Description
Comment
(Byte)
(Bit)
(Note1)
(h)
(1-1-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy
04:00
0 0000b
states
Clocks) not support
3Ch
00h
(1-1-2) Fast Read Number of
Mode Bits
000b: Mode Bits not support
07:05
15:08
20:16
000b
FFh
(1-1-2) Fast Read Opcode
3Dh
3Eh
3Fh
FFh
04h
BBh
(1-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy
0 0100b
states
Clocks) not support
(1-2-2) Fast Read Number of
Mode Bits
000b: Mode Bits not support
23:21
000b
(1-2-2) Fast Read Opcode
(2-2-2) Fast Read
Unused
31:24
00
BBh
0b
0=not support 1=support
0=not support 1=support
03:01
04
111b
0b
40h
EEh
(4-4-4) Fast Read
Unused
07:05
111b
0xFFh
0xFFh
Unused
43h:41h 31:08
45h:44h 15:00
0xFFh
0xFFh
Unused
(2-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy
20:16
46h
0 0000b
000b
states
Clocks) not support
00h
(2-2-2) Fast Read Number of
Mode Bits
000b: Mode Bits not support
23:21
(2-2-2) Fast Read Opcode
Unused
47h
31:24
FFh
FFh
49h:48h 15:00
0xFFh
0xFFh
(4-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
20:16
4Ah
0 0000b
states
Clocks) not support
00h
(4-4-4) Fast Read Number of
Mode Bits
000b: Mode Bits not support
23:21
000b
FFh
0Ch
20h
0Fh
52h
10h
D8h
00h
FFh
(4-4-4) Fast Read Opcode
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
53h
31:24
07:00
15:08
23:16
31:24
07:00
15:08
23:16
31:24
FFh
0Ch
20h
0Fh
52h
10h
D8h
00h
FFh
Sector/block size = 2^N bytes (Note5)
0x00b: this sector type doesn't exist
Sector Type 1 Size
Sector Type 1 erase Opcode
Sector Type 2 Size
Sector/block size = 2^N bytes
0x00b: this sector type doesn't exist
Sector Type 2 erase Opcode
Sector Type 3 Size
Sector/block size = 2^N bytes
0x00b: this sector type doesn't exist
Sector Type 3 erase Opcode
Sector Type 4 Size
Sector/block size = 2^N bytes
0x00b: this sector type doesn't exist
Sector Type 4 erase Opcode
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Table 12. Parameter Table (1): Macronix Flash Parameter Tables
Add (h) DW Add Data (h/b)
Data
(h)
Description
Comment
2000h=2.000V
2700h=2.700V
3600h=3.600V
(Byte)
(Bit)
(Note1)
07:00
15:08
00h
20h
00h
20h
Vcc Supply Maximum Voltage
61h:60h
1650h=1.650V
2250h=2.250V
2350h=2.350V
2700h=2.700V
23:16
31:24
50h
16h
50h
16h
Vcc Supply Minimum Voltage
63h:62h
HW Reset# pin
0=not support 1=support
00
0b
HW Hold# pin
0=not support 1=support
0=not support 1=support
0=not support 1=support
01
02
03
1b
1b
0b
Deep Power Down Mode
SW Reset
Reset Enable (66h) should be
issued before Reset command
1111 1111b
(FFh)
65h:64h
4FF6h
SW Reset Opcode
11:04
Program Suspend/Resume
Erase Suspend/Resume
Unused
0=not support 1=support
0=not support 1=support
12
13
0b
0b
14
1b
Wrap-Around Read mode
Wrap-Around Read mode Opcode
0=not support 1=support
15
0b
66h
67h
23:16
FFh
FFh
FFh
08h:support 8B wrap-around read
16h:8B&16B
32h:8B&16B&32B
Wrap-Around Read data length
31:24
FFh
64h:8B&16B&32B&64B
Individual block lock
0=not support 1=support
00
01
1b
0b
Individual block lock bit
(Volatile/Nonvolatile)
0=Volatile 1=Nonvolatile
0011 0110b
(36h)
Individual block lock Opcode
09:02
10
Individual block lock Volatile
protect bit default protect status
0=protect 1=unprotect
0b
C8D9h
6Bh:68h
Secured OTP
Read Lock
Permanent Lock
Unused
0=not support 1=support
0=not support 1=support
0=not support 1=support
11
12
1b
0b
13
0b
15:14
31:16
11b
Unused
0xFFh
0xFFh
0xFFh
0xFFh
Unused
6Fh:6Ch 31:00
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MX25U2033E
Note 1: h/b is hexadecimal or binary.
Note 2: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x),
address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1), (2-2-2),
and (4-4-4)
Note 3: Wait States is required dummy clock cycles after the address bits or optional mode bits.
Note 4: Mode Bits is optional control bits that follow the address bits. These bits are driven by the system controller
if they are specified. (eg,read performance enhance toggling bits)
Note 5: 4KB=2^0Ch, 32KB=2^0Fh, 64KB=2^10h
Note 6: 0xFFh means all data is blank ("1b").
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MX25U2033E
10. POWER-ON STATE
The device is at the following states after power-up:
- Standby mode (please note it is not deep power-down mode)
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage until the VCC reaches the following levels
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change
during power up state. When VCC is lower than VWI (POR threshold voltage value), the internal logic is reset and
the flash device has no response to any command.
For further protection on the device, after VCC reaching the VWI level, a tPUW time delay is required before the
device is fully accessible for commands like write enable (WREN), page program (PP), quad page program (4PP),
sector erase (SE), block erase 32KB (BE32K), block erase (BE), chip erase (CE), WRSCUR and write status regis-
ter (WRSR). If the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The write,
erase, and program command should be sent after the below time delay:
- tPUW after VCC reached VWI level
- tVSL after VCC reached VCC minimum level
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL, even time of
tPUW has not passed.
Please refer to "Figure 36. Power-up Timing" .
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommend-
ed. (generally around 0.1uF)
- At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response to
any command. The data corruption might occur during this stage if a write, program, erase cycle is in progress.
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MX25U2033E
11. ELECTRICAL SPECIFICATIONS
11-1. Absolute Maximum Ratings
RATING
VALUE
Ambient Operating Temperature
Storage Temperature
Applied Input Voltage
Applied Output Voltage
VCC to Ground Potential
Industrial grade
-40°C to 85°C
-65°C to 150°C
-0.5V to VCC+0.5V
-0.5V to VCC+0.5V
-0.5V to 2.5V
NOTICE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage
to the device. This is stress rating only and functional operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended period may affect reliability.
2. Specifications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot to VCC+1.0V or -1.0V for period up to 20ns.
Figure 8. Maximum Positive Overshoot Waveform
Figure 7. Maximum Negative Overshoot Waveform
20ns
0V
VCC+1.0V
-1.0V
2.0V
20ns
11-2. Capacitance
TA = 25°C, f = 1.0 MHz
SYMBOL PARAMETER
CIN Input Capacitance
COUT Output Capacitance
MIN.
TYP
MAX.
UNIT
pF
CONDITIONS
VIN = 0V
6
8
pF
VOUT = 0V
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MX25U2033E
Figure 9. Input Test Waveforms and Measurement Level
Input timing referance level
Output timing referance level
0.8VCC
0.7VCC
AC
Measurement
Level
0.5VCC
0.3VCC
0.2VCC
Note: Input pulse rise and fall time are <5ns
Figure 10. Output Loading
25K ohm
DEVICE UNDER
TEST
+1.8V
CL
25K ohm
CL=30pF Including jig capacitance
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MX25U2033E
Table 13. DC Characteristics
Temperature = -40 C to 85 C, VCC = 1.65V ~ 2.0V
°
°
SYMBOL PARAMETER
NOTES
MIN.
TYP.
MAX.
UNITS TEST CONDITIONS
VCC = VCC Max,
uA
ILI
Input Load Current
Output Leakage Current
1
±2
VIN = VCC or GND
VCC = VCC Max,
uA
ILO
1
1
±2
30
8
VIN = VCC or GND
VIN = VCC or GND,
CS# = VCC
ISB1 VCC Standby Current
8
2
uA
Deep Power-down
Current
VIN = VCC or GND,
CS# = VCC
ISB2
uA
f=80MHz,
12
7
mA SCLK=0.1VCC/0.9VCC,
SO=Open
ICC1 VCC Read
1
1
f=33MHz,
mA SCLK=0.1VCC/0.9VCC,
SO=Open
VCC Program Current
Program in Progress,
CS# = VCC
ICC2
(PP)
20
8
25
20
mA
VCC Write Status
ICC3
Program status register in
mA
Register (WRSR) Current
progress, CS#=VCC
VCC Sector/Block (32K,
ICC4 64K) Erase Current
(SE/BE/BE32K)
Erase in Progress,
CS#=VCC
1
1
20
20
25
25
mA
VCC Chip Erase Current
Erase in Progress,
CS#=VCC
ICC5
(CE)
mA
VIL
VIH
VOL
Input Low Voltage
Input High Voltage
Output Low Voltage
-0.5
0.2VCC
VCC+0.4
0.2
V
V
0.8VCC
V
V
IOL = 100uA
IOH = -100uA
VOH Output High Voltage
VCC-0.2
Note 1. Typical values at VCC = 1.8V, T = 25 C. These currents are valid for all product versions (package and
°
speeds).
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MX25U2033E
Table 14. AC Characteristics
Temperature = -40 C to 85 C, VCC = 1.65V ~ 2.0V
°
°
Symbol
Alt. Parameter
Clock Frequency for the following instructions:
Min.
Typ.
Max.
Unit
fSCLK
fC FAST_READ, RDSFDP, PP, SE, BE, CE, DP, RES, RDP
WREN, WRDI, RDID, RDSR, WRSR
D.C.
80
MHz
fRSCLK
fTSCLK
f4PP
fR Clock Frequency for READ instructions
fT Clock Frequency for 2READ instructions
fQ Clock Frequency for 4READ instructions
Clock Frequency for 4PP (Quad page program)
Serial (fSCLK)
50
80
70
70
MHz
MHz
MHz
MHz
ns
6
9
7
6
9
tCH
tCLH Clock High Time
Normal Read (fRSCLK)
4PP (70MHz)
(1)
ns
ns
ns
Serial (fSCLK)
tCL
tCLL Clock Low Time
Clock Rise Time
Normal Read (fRSCLK)
4PP (70MHz)
(peak to peak)
(3)
(1)
7
tCLCH
tCHCL
0.1
0.1
7
5
2
5
5
7
12
30
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
us
us
ms
us
ms
ms
ms
ms
s
(2)
(2)
Clock Fall Time
(peak to peak)
(3)
tSLCH
tCHSL
tDVCH
tCHDX
tCHSH
tSHCH
tCSS CS# Active Setup Time (relative to SCLK)
CS# Not Active Hold Time (relative to SCLK)
tDSU Data In Setup Time
tDH Data In Hold Time
CS# Active Hold Time (relative to SCLK)
CS# Not Active Setup Time (relative to SCLK)
Read
Write/Erase/Program
tSHSL
tCSH CS# Deselect Time
(3)
tSHQZ
tDIS Output Disable Time
8
(2)
tHLCH
tCHHH
tHHCH
tCHHL
tHHQX
tHLQZ
HOLD# Active Setup Time (relative to SCLK)
HOLD# Active Hold Time (relative to SCLK)
HOLD# Not Active Setup Time (relative to SCLK)
HOLD# Not Active Hold Time (relative to SCLK)
tLZ HOLD# to Output Low-Z
4
4
4
4
8
8
8
6
tHZ HOLD# to Output High-Z
Loading: 30pF
Loading: 15pF
Clock Low to Output Valid
Loading: 30pF/15pF
tCLQV
tV
tCLQX
tWHSL
tSHWL
tHO Output Hold Time
Write Protect Setup Time
Write Protect Hold Time
0
20
100
tDP
CS# High to Deep Power-down Mode
CS# High to Standby Mode without Electronic Signature Read
CS# High to Standby Mode with Electronic Signature Read
Write Status Register Cycle Time
Byte-Program
Page Program Cycle Time
Sector Erase Cycle Time
Block Erase (32KB) Cycle Time
Block Erase (64KB) Cycle Time
Chip Erase Cycle Time
10
10
(2)
tRES1
tRES2
tW
(2)
(2)
10
40
30
3
200
1000
2000
2.5
tBP
tPP
tSE
tBE32
tBE
10
1.2
30
200
500
1.25
tCE
Notes:
1. tCH + tCL must be greater than or equal to 1/ Frequency.
2. Value guaranteed by characterization, not 100% tested in production.
3. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
4. Test condition is shown as "Figure 9. Input Test Waveforms and Measurement Level", "Figure 10. Output Load-
ing".
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MX25U2033E
12. TIMING ANALYSIS
Figure 11. Serial Input Timing
tSHSL
tSHCH
tCHCL
CS#
tCHSL
tSLCH
tCHSH
SCLK
tDVCH
tCHDX
tCLCH
MSB
LSB
SI
High-Z
SO
Figure 12. Output Timing
CS#
tCH
SCLK
tCLQV
tCLQV
tCL
tSHQZ
tCLQX
SO
tCLQX
LSB
ADDR.LSB IN
SI
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MX25U2033E
Figure 13. WP# Setup Timing and Hold Timing during WRSR when SRWD=1
WP#
CS#
tSHWL
tWHSL
0
1
2
3
4
5
6
7
8
9
10 11 12
13 14
15
SCLK
01h
SI
High-Z
SO
Figure 14. Write Enable (WREN) Sequence (Command 06)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
06h
SI
High-Z
SO
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MX25U2033E
Figure 15. Write Disable (WRDI) Sequence (Command 04)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
04h
SI
High-Z
SO
Figure 16. Read Identification (RDID) Sequence (Command 9F)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
28 29 30 31
SCLK
SI
Command
9Fh
Manufacturer Identification
Device Identification
15 14 13
High-Z
SO
7
6
5
3
2
1
0
3
2
1
0
MSB
MSB
Figure 17. Read Status Register (RDSR) Sequence (Command 05)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI
command
05h
Status Register Out
Status Register Out
High-Z
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
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MX25U2033E
Figure 18. Write Status Register (WRSR) Sequence (Command 01)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
command
01h
Status
Register In
SI
7
6
5
4
3
2
0
1
MSB
High-Z
SO
Figure 19. Read Data Bytes (READ) Sequence (Command 03) (50MHz)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
command
03h
24-Bit Address
23 22 21
MSB
3
2
1
0
SI
Data Out 1
Data Out 2
High-Z
2
7
6
5
4
3
1
7
0
SO
MSB
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MX25U2033E
Figure 20. Read at Higher Speed (FAST_READ) Sequence (Command 0B)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
SCLK
Command
0Bh
24 BIT ADDRESS
SI
23 22 21
3
2
1
0
High-Z
SO
CS#
47
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
SCLK
Configurable
Dummy Cycle
7
6
5
4
3
2
0
1
SI
DATA OUT 2
DATA OUT 1
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
SO
MSB
MSB
MSB
Figure 21. 2 x I/O Read Mode Sequence (Command BB)
CS#
0
1
2
3
4
5
6
7
8
9
10 11
18 19 20 21 22 23 24 25 26 27
SCLK
4 dummy
cycle
8 Bit Instruction
12 BIT Address
Data Output
data
address
bit22, bit20, bit18...bit0
BBh
SI/SIO0
bit6, bit4, bit2...bit0, bit6, bit4....
High Impedance
address
bit23, bit21, bit19...bit1
data
SO/SIO1
bit7, bit5, bit3...bit1, bit7, bit5....
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MX25U2033E
Figure 22. 4 x I/O Read Mode Sequence (Command EB)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
n
SCLK
4 dummy
cycles
8 Bit Instruction
6 Address cycles
Data Output
Performance
enhance
indicator (Note)
data
address
EBh
P4 P0
P5 P1
P6 P2
P7 P3
SI/SIO0
bit4, bit0, bit4....
bit20, bit16..bit0
High Impedance
High Impedance
High Impedance
address
bit21, bit17..bit1
data
bit5 bit1, bit5....
SO/SIO1
WP#/SIO2
NC/SIO3
address
bit22, bit18..bit2
data
bit6 bit2, bit6....
address
bit23, bit19..bit3
data
bit7 bit3, bit7....
Note:
1. Hi-impedance is inhibited for the two clock cycles.
2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited.
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MX25U2033E
Figure 23. 4 x I/O Read Enhance Performance Mode Sequence (Command EB)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
n
SCLK
4 dummy
cycles
8 Bit Instruction
6 Address cycles
Data Output
Performance
enhance
indicator (Note)
data
address
P4 P0
P5 P1
P6 P2
P7 P3
EBh
SI/SIO0
bit4, bit0, bit4....
bit20, bit16..bit0
High Impedance
High Impedance
High Impedance
address
bit21, bit17..bit1
data
bit5 bit1, bit5....
SO/SIO1
WP#/SIO2
NC/SIO3
address
bit22, bit18..bit2
data
bit6 bit2, bit6....
address
bit23, bit19..bit3
data
bit7 bit3, bit7....
CS#
n+1
...........
n+7......n+9 ........... n+13
...........
SCLK
4 dummy
cycles
6 Address cycles
Data Output
Performance
enhance
indicator (Note)
data
address
P4 P0
P5 P1
P6 P2
P7 P3
SI/SIO0
bit4, bit0, bit4....
bit20, bit16..bit0
address
bit21, bit17..bit1
data
bit5 bit1, bit5....
SO/SIO1
WP#/SIO2
NC/SIO3
address
bit22, bit18..bit2
data
bit6 bit2, bit6....
address
bit23, bit19..bit3
data
bit7 bit3, bit7....
Note: 1.xPerformance enhance mode, if P7≠P3 & P6≠P2 & P5≠P1 & P4≠P0 (Toggling), ex: A5, 5A, 0F,
performance enhance recommend to keep 1 or 0 in performance enhance indicator.
2. Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0 (Not Toggling), ex: AA,
00, FF
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MX25U2033E
Figure 24. Page Program (PP) Sequence (Command 02)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
02h
24-Bit Address
Data Byte 1
23 22 21
MSB
3
2
1
0
7
6
5
4
3
2
0
1
SI
MSB
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
Data Byte 2
Data Byte 3
Data Byte 256
7
6
5
4
3
2
0
7
6
5
4
3
2
0
7
6
5
4
3
2
0
1
1
1
SI
MSB
MSB
MSB
Figure 25. 4 x I/O Page Program (4PP) Sequence (Command 38)
CS#
10 11 12 13 14 15 16 17 18 19 20 21
Data Data Data Data
0
1
2
3
4
5
6
7
8
9
SCLK
Command
38h
6 Address cycle
Byte 1 Byte 2 Byte 3 Byte 4
16 12
8
9
4
0
20
4
0
4
0
4
0
4
0
SI/SIO0
21 17 13
5
6
7
1
2
3
SO/SIO1
WP#/SIO2
NC/SIO3
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
22 18 14 10
23 19 15 11
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MX25U2033E
Figure 26. Sector Erase (SE) Sequence (Command 20)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
20h
24 Bit Address
SI
23 22
MSB
2
1
0
Figure 27. Block Erase 32KB (BE32K) Sequence (Command 52)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
52h
24 Bit Address
SI
23 22
2
0
1
MSB
Figure 28. Block Erase (BE) Sequence (Command D8)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
D8h
24 Bit Address
2
SI
23 22
MSB
0
1
Figure 29. Chip Erase (CE) Sequence (Command 60 or C7)
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
60h or C7h
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MX25U2033E
Figure 30. Deep Power-down (DP) Sequence (Command B9)
CS#
t
DP
0
1
2
3
4
5
6
7
SCLK
SI
Command
B9h
Stand-by Mode
Deep Power-down Mode
Figure 31. RDP and Read Electronic Signature (RES) Sequence (Command AB)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38
SCLK
Command
ABh
t
3 Dummy Bytes
RES2
SI
23 22 21
MSB
3
2
1
0
Electronic Signature Out
High-Z
7
6
5
4
3
2
0
1
SO
MSB
Deep Power-down Mode
Stand-by Mode
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MX25U2033E
Figure 32. Release from Deep Power-down (RDP) Sequence (Command AB)
CS#
t
RES1
0
1
2
3
4
5
6
7
SCLK
Command
ABh
SI
High-Z
SO
Deep Power-down Mode
Stand-by Mode
Figure 33. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90/EF/DF)
CS#
0
1
2
3
4
5
6
7
8
9 10
SCLK
Command
90h
2 Dummy Bytes
SI
15 14 13
3
2
1
0
High-Z
SO
CS#
47
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
SCLK
ADD (1)
7
6
5
4
3
2
0
1
SI
Manufacturer ID
Device ID
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
SO
MSB
MSB
MSB
Notes:
(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first.
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MX25U2033E
Figure 34. Read Security Register (RDSCUR) Sequence (Command 2B)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI
command
2B
Security Register Out
Security Register Out
High-Z
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
Figure 35. Write Security Register (WRSCUR) Sequence (Command 2F)
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
2F
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MX25U2033E
Figure 36. Power-up Timing
V
CC
V
(max)
CC
Program, Erase and Write Commands are Ignored
Chip Selection is Not Allowed
V
(min)
CC
tVSL
Read Command is
Device is fully
accessible
Reset State
of the
Flash
allowed
V
WI
tPUW
time
Note: VCC (max.) is 2.0V and VCC (min.) is 1.65V.
Table 15. Power-Up Timing and VWI Threshold
Symbol
tVSL(1)
tPUW(1)
VWI(1)
Parameter
Min.
300
1
Max.
Unit
us
ms
V
VCC(min) to CS# low (VCC Rise Time)
Time delay to Write instruction
Command Inhibit Voltage
10
1.4
1.0
Note: 1. These parameters are characterized only.
INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status
Register contains 00h (all Status Register bits are 0).
P/N: PM1743
REV. 1.3, NOV. 14, 2013
58
MX25U2033E
13. OPERATING CONDITIONS
At Device Power-Up and Power-Down
AC timing illustrated in "Figure 37. AC Timing at Device Power-Up" and "Figure 38. Power-Down Sequence" are
for the supply voltages and the control signals at device power-up and power-down. If the timing in the figures is ig-
nored, the device will not operate correctly.
During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be
selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.
Figure 37. AC Timing at Device Power-Up
VCC(min)
VCC
GND
tVR
tSHSL
CS#
tSHCH
tSLCH
tCHSL
tCHSH
SCLK
tDVCH
tCHCL
tCHDX
tCLCH
MSB IN
LSB IN
SI
High Impedance
SO
Symbol
tVR
Parameter
VCC Rise Time
Notes
Min.
20
Max.
500000
Unit
us/V
1
Notes :
1. Sampled, not 100% tested.
2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to
"Table 14. AC Characteristics".
P/N: PM1743
REV. 1.3, NOV. 14, 2013
59
MX25U2033E
Figure 38. Power-Down Sequence
During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.
VCC
CS#
SCLK
P/N: PM1743
REV. 1.3, NOV. 14, 2013
60
MX25U2033E
14. ERASE AND PROGRAMMING PERFORMANCE
PARAMETER
Write Status Register Cycle Time
Sector Erase Cycle Time (4KB)
Block Erase Cycle Time (32KB)
Block Erase Cycle Time (64KB)
Chip Erase Cycle Time
Min.
TYP. (1)
Max. (2)
40
UNIT
ms
30
200
200
1000
2000
2.5
ms
ms
500
ms
1.25
10
s
Byte Program Time (via page program command)
Page Program Time
30
us
1.2
3
ms
Erase/Program Cycle
100,000
cycles
Note:
1. Typical program and erase time assumes the following conditions: 25 C, 1.8V, and checkerboard pattern.
°
2. Under worst conditions of 85 C and 1.65V.
°
3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming com-
mand.
15. DATA RETENTION
PARAMETER
Condition
Min.
Max.
UNIT
Data retention
55˚C
20
years
16. LATCH-UP CHARACTERISTICS
MIN.
-1.0V
MAX.
Input Voltage with respect to GND on all power pins, SI, CS#
Input Voltage with respect to GND on SO
2 VCCmax
VCC + 1.0V
+100mA
-1.0V
Current
-100mA
Includes all pins except VCC. Test conditions: VCC = 1.8V, one pin at a time.
P/N: PM1743
REV. 1.3, NOV. 14, 2013
61
MX25U2033E
17. ORDERING INFORMATION
PART NO.
CLOCK (MHz)
TEMPERATURE
-40 C~85 C
PACKAGE
Remark
8-SOP
(150mil)
8-USON
(4x4mm)
8-WSON
(6x5mm)
MX25U2033EM1I-12G
80
80
80
°
°
MX25U2033EZUI-12G
MX25U2033EZNI-12G
-40 C~85 C
° °
-40 C~85 C
°
°
P/N: PM1743
REV. 1.3, NOV. 14, 2013
62
MX25U2033E
18. PART NAME DESCRIPTION
MX 25 U 2033E M1
I
12 G
OPTION:
G: RoHS Compliant and Halogen-free
SPEED:
12: 80MHz
TEMPERATURE RANGE:
I: Industrial (-40°C to 85°C)
PACKAGE:
M1: 150mil 8-SOP
ZU: USON
ZN: WSON
DENSITY & MODE:
2033E: 2Mb
TYPE:
U: 1.8V
DEVICE:
25: Serial Flash
P/N: PM1743
REV. 1.3, NOV. 14, 2013
63
MX25U2033E
19. PACKAGE INFORMATION
P/N: PM1743
REV. 1.3, NOV. 14, 2013
64
MX25U2033E
P/N: PM1743
REV. 1.3, NOV. 14, 2013
65
MX25U2033E
P/N: PM1743
REV. 1.3, NOV. 14, 2013
66
MX25U2033E
20. REVISION HISTORY
Revision No. Description
Page
Date
0.00
1. Initial released
All
NOV/10/2011
1.0
1. Added "Advanced Information" for P/N: *MX25U2033EZUI-12G P56
1. Added SFDP content
1. Removed "Advanced Information" for P/N: MX25U2033EZUI-12G P62
FEB/24/2012
1.1
P35~40, 45 MAR/20/2012
1.2
JAN/04/2013
1.3
1. Updated parameters for DC Characteristics.
2. Updated Erase and Programming Performance.
3. Modified Absolute Maximum Ratings table.
P5,44
P5,45,61
P42
NOV/14/2013
P/N: PM1743
REV. 1.3, NOV. 14, 2013
67
MX25U2033E
Except for customized products which has been expressly identified in the applicable agreement, Macronix's products
are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applica-
tions only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe
property damages. In the event Macronix products are used in contradicted to their target usage above, the buyer shall
take any and all actions to ensure said Macronix's product qualified for its actual use in accordance with the applicable
laws and regulations; and Macronix as well as it’s suppliers and/or distributors shall be released from any and all liabil-
ity arisen therefrom.
Copyright© Macronix International Co., Ltd. 2012~2013. All rights reserved, including the trademarks and tradename
thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit, NBiit, Macronix NBit,
eLiteFlash, HybridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC, Kingtech, MXSMIO, Macronix
vEE, Macronix MAP, Rich Audio, Rich Book, Rich TV, and FitCAM. The names and brands of third party referred thereto (if
any) are for identification purposes only.
For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
68
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