MX25U25635FZ2I10G [Macronix]
1.8V 256M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY;
| 型号： | MX25U25635FZ2I10G |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | 1.8V 256M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY |
| 文件： | 总96页 (文件大小：1596K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MX25U25635F
MX25U25635F
DATASHEET
P/N: PM1712
MX25U25635F
Contents
1. FEATURES ..............................................................................................................................................................4
2. GENERAL DESCRIPTION .....................................................................................................................................6
Table 1. Read performance Comparison ....................................................................................................6
3. PIN CONFIGURATIONS .........................................................................................................................................7
4. PIN DESCRIPTION..................................................................................................................................................7
5. BLOCK DIAGRAM...................................................................................................................................................8
6. DATA PROTECTION................................................................................................................................................9
Table 2. Protected Area Sizes...................................................................................................................10
Table 3. 4K-bit Secured OTP Definition ....................................................................................................11
7. Memory Organization...........................................................................................................................................12
Table 4. Memory Organization ..................................................................................................................12
8. DEVICE OPERATION............................................................................................................................................13
8-1. 256Mb Address Protocol.......................................................................................................................... 15
8-2. Quad Peripheral Interface (QPI) Read Mode .......................................................................................... 16
9. COMMAND DESCRIPTION...................................................................................................................................17
Table 5. Command Set..............................................................................................................................17
9-1. Write Enable (WREN).............................................................................................................................. 22
9-2. Write Disable (WRDI)............................................................................................................................... 23
9-3. Read Identification (RDID)....................................................................................................................... 24
9-4. Release from Deep Power-down (RDP), Read Electronic Signature (RES) ........................................... 25
9-5. Read Electronic Manufacturer ID & Device ID (REMS)........................................................................... 27
9-6. QPI ID Read (QPIID) ............................................................................................................................... 28
Table 6. ID Definitions ..............................................................................................................................28
9-7. Read Status Register (RDSR)................................................................................................................. 29
9-8. Read Configuration Register (RDCR)...................................................................................................... 30
9-9. Write Status Register (WRSR)................................................................................................................. 36
Table 7. Protection Modes.........................................................................................................................37
9-10. Enter 4-byte mode (EN4B) ...................................................................................................................... 40
9-11. Exit 4-byte mode (EX4B) ......................................................................................................................... 40
9-12. Read Data Bytes (READ) ........................................................................................................................ 41
9-13. Read Data Bytes at Higher Speed (FAST_READ) .................................................................................. 42
9-14. Dual Output Read Mode (DREAD).......................................................................................................... 43
9-15. 2 x I/O Read Mode (2READ) ................................................................................................................... 44
9-16. Quad Read Mode (QREAD) .................................................................................................................... 45
9-17. 4 x I/O Read Mode (4READ) ................................................................................................................... 46
9-18. 4 Byte Address Command Set................................................................................................................. 48
9-19. Burst Read............................................................................................................................................... 50
9-20. Performance Enhance Mode................................................................................................................... 51
9-21. Performance Enhance Mode Reset......................................................................................................... 54
9-22. Fast Boot ................................................................................................................................................. 56
9-23. Sector Erase (SE).................................................................................................................................... 59
9-24. Block Erase (BE32K)............................................................................................................................... 60
P/N: PM1712
REV. 1.2, NOV. 28, 2013
2
MX25U25635F
9-25. Block Erase (BE) ..................................................................................................................................... 61
9-26. Chip Erase (CE)....................................................................................................................................... 62
9-27. Page Program (PP) ................................................................................................................................. 63
9-28. 4 x I/O Page Program (4PP).................................................................................................................... 65
9-29. Deep Power-down (DP)........................................................................................................................... 66
9-30. Enter Secured OTP (ENSO).................................................................................................................... 67
9-31. Exit Secured OTP (EXSO)....................................................................................................................... 67
9-32. Read Security Register (RDSCUR)......................................................................................................... 67
9-33. Write Security Register (WRSCUR)......................................................................................................... 67
Table 8. Security Register Definition .........................................................................................................68
9-34. Block Lock (BP) protection ...................................................................................................................... 68
9-35. Program/Erase Suspend/Resume .......................................................................................................... 69
9-36. Erase Suspend ....................................................................................................................................... 69
9-37. Program Suspend ................................................................................................................................... 69
9-38. Write-Resume.......................................................................................................................................... 71
9-39. No Operation (NOP) ................................................................................................................................ 71
9-40. Software Reset (Reset-Enable (RSTEN) and Reset (RST)) ................................................................... 71
9-41. Read SFDP Mode (RDSFDP).................................................................................................................. 73
Table 9. Signature and Parameter Identification Data Values ..................................................................74
Table 10. Parameter Table (0): JEDEC Flash Parameter Tables..............................................................75
Table 11. Parameter Table (1): Macronix Flash Parameter Tables............................................................77
10. RESET..................................................................................................................................................................79
Table 12. Reset Timing-(Power On)..........................................................................................................79
Table 13. Reset Timing-(Other Operation) ................................................................................................79
11. POWER-ON STATE .............................................................................................................................................80
12. ELECTRICAL SPECIFICATIONS........................................................................................................................81
Table 14. ABSOLUTE MAXIMUM RATINGS ............................................................................................81
Table 15. CAPACITANCE TA = 25°C, f = 1.0 MHz....................................................................................81
Table 16. DC CHARACTERISTICS (Temperature = -40 C to 85 C, VCC = 1.65V ~ 2.0V) .....................83
°
°
Table 17. AC CHARACTERISTICS (Temperature = -40 C to 85 C, VCC = 1.65V ~ 2.0V) .....................84
°
°
13. OPERATING CONDITIONS.................................................................................................................................86
Table 18. Power-Up Timing and VWI Threshold .......................................................................................87
Table 19. Power-Up/Down and Voltage Drop ...........................................................................................88
13-1. INITIAL DELIVERY STATE...................................................................................................................... 88
14. ERASE AND PROGRAMMING PERFORMANCE..............................................................................................89
15. DATA RETENTION ..............................................................................................................................................89
16. LATCH-UP CHARACTERISTICS........................................................................................................................89
17. ORDERING INFORMATION................................................................................................................................90
18. PART NAME DESCRIPTION...............................................................................................................................91
19. PACKAGE INFORMATION..................................................................................................................................92
20. REVISION HISTORY ...........................................................................................................................................95
P/N: PM1712
REV. 1.2, NOV. 28, 2013
3
MX25U25635F
1.8V 256M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O)
FLASH MEMORY
1. FEATURES
GENERAL
•
•
Serial Peripheral Interface compatible -- Mode 0 and Mode 3
Single Power Supply Operation
- 1.65 to 2.0 volt for read, erase, and program operations
256Mb: 268,435,456 x 1 bit structure or 134,217,728 x 2 bits (two I/O mode) structure or 67,108,864 x 4 bits (four
I/O mode) structure
•
•
Protocol Support
- Single I/O, Dual I/O and Quad I/O
•
•
•
Latch-up protected to 100mA from -1V to Vcc +1V
Low Vcc write inhibit is from 1.0V to 1.4V
Fast read for SPI mode
- Support clock frequency up to 108MHz for all protocols
- Support clock frequency up to 133MHz for all protocols (for MX25U25635FZ4I-08G only)
- Support Fast Read, 2READ, DREAD, 4READ, QREAD instructions.
- Configurable dummy cycle number for fast read operation
Quad Peripheral Interface (QPI) available
•
•
Equal Sectors with 4K byte each, or Equal Blocks with 32K byte each or Equal Blocks with 64K byte each
- Any Block can be erased individually
•
Programming :
- 256byte page buffer
- Quad Input/Output page program(4PP) to enhance program performance
Typical 100,000 erase/program cycles
20 years data retention
•
•
SOFTWARE FEATURES
•
Input Data Format
- 1-byte Command code
•
Advanced Security Features
- Block lock protection
The BP0-BP3 and T/B status bit defines the size of the area to be protection against program and erase instruc-
tions
•
Additional 4K bit security OTP
Features unique identifier
factory locked identifiable, and customer lockable
Command Reset
-
-
•
•
•
Program/Erase Suspend and Resume operation
Electronic Identification
JEDEC 1-byte manufacturer ID and 2-byte device ID
- RES command for 1-byte Device ID
-
- REMS command for 1-byte manufacturer ID and 1-byte device ID
Support Serial Flash Discoverable Parameters (SFDP) mode
•
HARDWARE FEATURES
•
SCLK Input
- Serial clock input
P/N: PM1712
REV. 1.2, NOV. 28, 2013
4
MX25U25635F
•
•
•
•
•
SI/SIO0
- Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
SO/SIO1
- Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
WP#/SIO2
- Hardware write protection or serial data Input/Output for 4 x I/O read mode
RESET#/SIO3
- Hardware Reset pin or Serial input & Output for 4 x I/O read mode
PACKAGE
-16-pin SOP (300mil)
-8-land WSON (8x6mm)
-8-land WSON (8x6mm 3.4 x 4.3EP)
- All devices are RoHS Compliant and Halogen-free
P/N: PM1712
REV. 1.2, NOV. 28, 2013
5
MX25U25635F
2. GENERAL DESCRIPTION
MX25U25635F is 256Mb bits serial Flash memory, which is configured as 33,554,432 x 8 internally. When it is in
two or four I/O mode, the structure becomes 134,217,728 bits x 2 or 67,108,864 bits x 4. MX25U25635F feature a
serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single I/O
mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial
access to the device is enabled by CS# input.
When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits in-
put and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# and RESET# pin become SIO0 pin,
SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output.
The MX25U25635F MXSMIO (Serial Multi I/O) provides sequential read operation on whole chip.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the speci-
fied page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis, or word basis for erase command is executed on sector (4K-byte), block (32K-byte), or block (64K-byte),
or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
When the device is not in operation and CS# is high, it is put in standby mode.
The MX25U25635F utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after
100,000 program and erase cycles.
Table 1. Read performance Comparison
Dual Output
Fast Read
(MHz)
Quad Output
Fast Read
(MHz)
Dual IO
Fast Read
(MHz)
Quad IO
Fast Read
(MHz)
Numbers of
Dummy Cycles
Fast Read
(MHz)
4
-
-
-
84*
108
108
133
70
6
8
108
108*
133
108
108*
133
84
84*
108
133
108*
133
10 (Note2)
Note 1 : * mean default status
Note 2 : Please note that only MX25U25635FZ4I-08G supports 133MHz with 10 dummy cycles. All other products
are not able to set DC[1:0] to 11b.
P/N: PM1712
REV. 1.2, NOV. 28, 2013
6
MX25U25635F
4. PIN DESCRIPTION
3. PIN CONFIGURATIONS
16-PIN SOP (300mil)
SYMBOL DESCRIPTION
CS#
Chip Select
1
2
3
4
5
6
7
8
SCLK
SI/SIO0
NC
DNU/SIO3
VCC
16
15
14
13
12
11
10
9
Serial Data Input (for 1 x I/O)/ Serial
Data Input & Output (for 2xI/O or 4xI/
O read mode)
Serial Data Output (for 1 x I/O)/ Serial
Data Input & Output (for 2xI/O or 4xI/
O read mode)
SI/SIO0
RESET#
NC
NC
NC
NC
NC
NC
GND
WP#/SIO2
CS#
SO/SIO1
SCLK
SO/SIO1
Clock Input
Write protection: connect to GND or
WP#/SIO2 Serial Data Input & Output (for 4xI/O
read mode)
8-WSON (8x6mm, 8x6mm 3.4 x 4.3EP)
Hardware Reset Pin Active low or
RESET#/SIO3 Serial Data Input & Output (for 4xI/O
read mode)
1
2
3
4
VCC
CS#
SO/SIO1
WP#/SIO2
GND
8
7
6
5
RESET#/SIO3
SCLK
Do Not Use or Serial Data Input &
DNU/SIO3
SI/SIO0
Output (for 4xI/O read mode)
VCC
GND
NC
+ 1.8V Power Supply
Ground
No Connection
Notes:
1. RESET# pin has internal pull up.
2. When using 1I/O or 2I/O (QE bit not enable), the
DNU/SIO3 pin of 16SOP can not connect to GND.
Please connect this pin to VCC.
P/N: PM1712
REV. 1.2, NOV. 28, 2013
7
MX25U25635F
5. BLOCK DIAGRAM
Address
Generator
Memory Array
Page Buffer
Data
Register
SI/SIO0
Y-Decoder
SRAM
Buffer
Sense
Amplifier
CS#
WP#/SIO2
RESET#/SIO3
Mode
Logic
State
Machine
HV
Generator
SCLK
Clock Generator
Output
Buffer
SO/SIO1
P/N: PM1712
REV. 1.2, NOV. 28, 2013
8
MX25U25635F
6. DATA PROTECTION
During power transition, there may be some false system level signals which result in inadvertent erasure or
programming. The device is designed to protect itself from these accidental write cycles.
The state machine will be reset as standby mode automatically during power up. In addition, the control register
architecture of the device constrains that the memory contents can only be changed after specific command
sequences have completed successfully.
In the following, there are several features to protect the system from the accidental write cycles during VCC power-
up and power-down or from system noise.
•
•
•
Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.
Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other command to change data.
Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writ-
ing all commands except Release from deep power down mode command (RDP) and Read Electronic Signature
command (RES), and softreset command.
P/N: PM1712
REV. 1.2, NOV. 28, 2013
9
MX25U25635F
I. Block lock protection
- The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0 and T/B) bits to allow part of memory to be
protected as read only. The protected area definition is shown as Table 2 Protected Area Sizes, the protected ar-
eas are more flexible which may protect various area by setting value of BP0-BP3 bits.
- The Hardware Proteced Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and Status Reg-
ister Write Protect bit.
- In four I/O and QPI mode, the feature of HPM will be disabled.
Table 2. Protected Area Sizes
Protected Area Sizes (T/B bit = 0)
Status bit
Protect Level
256Mb
BP3
0
BP2
BP1
0
BP0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0 (none)
0
0
1
1 (1 block, protected block 511st)
2 (2 blocks, protected block 510th~511st)
3 (4 blocks, protected block 508th~511st)
4 (8 blocks, protected block 504th~511st)
5 (16 blocks, protected block 496th~511st)
6 (32 blocks, protected block 480th~511st)
7 (64 blocks, protected block 448th~511st)
8 (128 blocks, protected block 384th~511st)
9 (256 blocks, protected block 256th~511st)
10 (512 blocks, protected all)
0
1
0
0
1
1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
11 (512 blocks, protected all)
1
0
0
12 (512 blocks, protected all)
1
0
1
13 (512 blocks, protected all)
1
1
0
14 (512 blocks, protected all)
1
1
1
15 (512 blocks, protected all)
Protected Area Sizes (T/B bit = 1)
Status bit
Protect Level
256Mb
BP3
0
BP2
0
BP1
0
BP0
0
0 (none)
0
0
0
1
1 (1 block, protected block 0th)
2 (2 blocks, protected block 0th~1th)
3 (4 blocks, protected block 0th~3rd)
4 (8 blocks, protected block 0th~7th)
5 (16 blocks, protected block 0th~15th)
6 (32 blocks, protected block 0th~31st)
7 (64 blocks, protected block 0th~63rd)
8 (128 blocks, protected block 0th~127th)
9 (256 blocks, protected block 0th~255th)
10 (512 blocks, protected all)
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
11 (512 blocks, protected all)
1
1
0
0
12 (512 blocks, protected all)
1
1
0
1
13 (512 blocks, protected all)
1
1
1
0
14 (512 blocks, protected all)
1
1
1
1
15 (512 blocks, protected all)
P/N: PM1712
REV. 1.2, NOV. 28, 2013
10
MX25U25635F
II. Additional 4K-bit secured OTP for unique identifier: to provide 4K-bit one-time program area for setting de-
vice unique serial number - Which may be set by factory or system customer.
- Security register bit 0 indicates whether the chip is locked by factory or not.
- To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with Enter Security OTP command),
and going through normal program procedure, and then exiting 4K-bit secured OTP mode by writing Exit Security
OTP command.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register) com-
mand to set customer lock-down bit1 as "1". Please refer to Table 8 of "security register definition" for security
register bit definition and Table 3 of "4K-bit secured OTP definition" for address range definition.
- Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit secured
OTP mode, array access is not allowed.
Table 3. 4K-bit Secured OTP Definition
Address range
xxx000~xxx00F
xxx010~xxx1FF
Size
Standard Factory Lock
ESN (electrical serial number)
N/A
Customer Lock
128-bit
3968-bit
Determined by customer
P/N: PM1712
REV. 1.2, NOV. 28, 2013
11
MX25U25635F
7. Memory Organization
Table 4. Memory Organization
Block(64K-byte) Block(32K-byte)
Sector
8191
Address Range
1FFF000h
1FFFFFFh
1023
individual 16 sectors
lock/unlock unit:4K-byte
8184
8183
1FF8000h
1FF7000h
1FF8FFFh
1FF7FFFh
511
1022
1021
1020
1019
1018
8176
8175
1FF0000h
1FEF000h
1FF0FFFh
1FEFFFFh
8168
8167
1FE8000h
1FE7000h
1FE8FFFh
1FE7FFFh
510
individual block
lock/unlock unit:64K-byte
8160
8159
1FE0000h
1FDF000h
1FE0FFFh
1FDFFFFh
8152
8151
1FD8000h
1FD7000h
1FD8FFFh
1FD7FFFh
509
8144
1FD0000h
1FD0FFFh
individual block
lock/unlock unit:64K-byte
47
002F000h
002FFFFh
5
4
3
2
1
0
40
39
0028000h
027000h
0028FFFh
0027FFFh
2
1
individual block
lock/unlock unit:64K-byte
32
31
0020000h
001F000h
0020FFFh
001FFFFh
24
23
0018000h
0017000h
0018FFFh
0017FFFh
16
15
0010000h
000F000h
0010FFFh
000FFFFh
individual 16 sectors
lock/unlock unit:4K-byte
8
7
0008000h
0007000h
0008FFFh
0007FFFh
0
0
0000000h
0000FFFh
P/N: PM1712
REV. 1.2, NOV. 28, 2013
12
MX25U25635F
8. DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended op-
eration.
2. When incorrect command is inputted to this device, this device becomes standby mode and keeps the standby
mode until next CS# falling edge. In standby mode, SO pin of this device should be High-Z.
3. When correct command is inputted to this device, this device becomes active mode and keeps the active mode
until next CS# rising edge.
4. Input data is latched on the rising edge of Serial Clock (SCLK) and data shifts out on the falling edge of SCLK.
The difference of Serial mode 0 and mode 3 is shown as "Serial Modes Supported".
5. For the following instructions: RDID, RDSR, RDSCUR, READ/READ4B, FAST_READ/FAST_READ4B,
2READ/2READ4B, DREAD/DREAD4B, 4READ/4READ4B, QREAD/QREAD4B, RDSFDP, RES, REMS, QPIID,
RDEAR, RDFBR, RDCR, the shifted-in instruction sequence is followed by a data-out sequence. After any bit
of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE/SE4B,
BE32K/BE32K4B, BE/BE4B, CE, PP/PP4B, 4PP/4PP4B, DP, ENSO, EXSO, WRSCUR, EN4B, EX4B, SUS-
PEND, RESUME, NOP, RSTEN, RST, EQIO, RSTQIO the CS# must go high exactly at the byte boundary; oth-
erwise, the instruction will be rejected and not executed.
6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglect-
ed and not affect the current operation of Write Status Register, Program, Erase.
Figure 1. Serial Modes Supported
CPOL CPHA
shift in
shift out
SCLK
SCLK
(Serial mode 0)
(Serial mode 3)
0
1
0
1
SI
MSB
SO
MSB
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is
supported.
P/N: PM1712
REV. 1.2, NOV. 28, 2013
13
MX25U25635F
Figure 2. Serial Input Timing
tSHSL
tSHCH
tCHCL
CS#
tCHSL
tSLCH
tCHSH
SCLK
tDVCH
tCHDX
tCLCH
MSB
LSB
SI
High-Z
SO
Figure 3. Output Timing
CS#
tCH
SCLK
tCLQV
tCLQV
tCL
tSHQZ
tCLQX
SO
tCLQX
LSB
ADDR.LSB IN
SI
P/N: PM1712
REV. 1.2, NOV. 28, 2013
14
MX25U25635F
8-1. 256Mb Address Protocol
The original 24 bit address protocol of serial Flash can only access density size below 128Mb. For the memory
device of 256Mb and above, the 32bit address is requested for access higher memory size. The MX25U25635F
provides three different methods to access the whole 256Mb density:
1. Command entry 4-byte address mode: Issue Enter 4-Byte mode command to set up the 4BYTE bit in
Configuration Register bit. After 4BYTE bit has been set, the number of address cycle become 32-bit.
2. Extended Address Register (EAR): configure the memory device into two 128Mb segments to select which one
is active through the EAR bit “0”.
3. 4-byte Address Command Set: When issuing 4-byte address command set, 4-byte address (A31-A0) is
requested after the instruction code. Please note that it is not necessary to issue EN4B command before issuing
any of 4-byte command set.
Enter 4-Byte Address Mode
In 4-byte Address mode, all instructions are 32-bits address clock cycles. By using EN4B and EX4B to enable and
disable the 4-byte address mode.
When 4-byte address mode is enabled, the EAR<0> becomes "don't care" for all instructions requiring 4-byte
address. The EAR function will be disabled when 4-byte mode is enabled.
Extended Address Register (Configurable)
The device provides an 8-bit volatile register for extended Address Register: it indentifies the extended address
(A31~A24) above 128Mb density by using original 3-byte address.
Extended Address Register (EAR)
Bit 7
A31
Bit 6
A30
Bit 5
A29
Bit 4
A28
Bit 3
A27
Bit 2
A26
Bit 1
A25
Bit 0
A24
For the MX25U25635F the A31 to A25 are Don’t Care. During EAR, reading these bits will read as 0. The bit 0 is
default as "0".
Figure 4. Top and Bottom 128M bits
Top 128Mb
EAR<0>= 1
01FFFFFFh
01000000h
00FFFFFFh
Bottom 128Mb
EAR<0>= 0 (default)
00000000h
When under EAR mode, Read, Program, Erase operates in the selected segment by using 3-byte address mode.
For the read operation, the whole array data can be continually read out with one command. Data output starts from
the selected top or bottom 128Mb, but it can cross the boundary. When the last byte of the segment is reached,
the next byte (in a continuous reading) is the first byte of the next segment. However, the EAR (Extended Address
Register) value does not change. The random access reading can only be operated in the selected segment.
The Chip erase command will erase the whole chip and is not limited by EAR selected segment.
P/N: PM1712
REV. 1.2, NOV. 28, 2013
15
MX25U25635F
8-2. Quad Peripheral Interface (QPI) Read Mode
QPI protocol enables user to take full advantage of Quad I/O Serial Flash by providing the Quad I/O interface in
command cycles, address cycles and as well as data output cycles.
Enable QPI mode
By issuing 35H command, the QPI mode is enable.
Figure 5. Enable QPI Sequence
CS#
MODE 3
MODE 0
2
3
4
5
6
7
0
1
SCLK
SIO0
35h
SIO[3:1]
Reset QPI (RSTQIO)
To reset the QPI mode, the RSTQIO (F5H) command is required. After the RSTQIO command is issued, the device
returns from QPI mode (4 I/O interface in command cycles) to SPI mode (1 I/O interface in command cycles).
Note:
For EQIO and RSTQIO commands, CS# high width has to follow "write spec" tSHSL for next instruction.
Figure 6. Reset QPI Mode
CS#
SCLK
SIO[3:0]
F5h
P/N: PM1712
REV. 1.2, NOV. 28, 2013
16
MX25U25635F
9. COMMAND DESCRIPTION
Table 5. Command Set
Read/Write Array Commands
4READ
4READ
2READ
(2 x I/O read
command)
Command
(byte)
READ
FAST READ
DREAD
(1I 2O read)
QREAD
(1I 4O read)
(4 I/O read start
from bottom
128Mb)
(4 I/O read start
from Top 128Mb)
(normal read) (fast read data)
Mode
Address Bytes
1st byte
SPI
3/4
SPI
3/4
SPI
3/4
SPI
3/4
SPI/QPI
3/4
SPI/QPI
3
SPI
3/4
03 (hex)
ADD1
ADD2
ADD3
0B (hex)
ADD1
ADD2
ADD3
Dummy*
BB (hex)
ADD1
ADD2
ADD3
Dummy*
3B (hex)
ADD1
ADD2
ADD3
Dummy*
EB (hex)
ADD1
EA (hex)
ADD1
ADD2
ADD3
Dummy*
6B (hex)
ADD1
ADD2
ADD3
Dummy*
2nd byte
3rd byte
ADD2
4th byte
ADD3
5th byte
Dummy*
Data Cycles
n bytes read
out until CS# out until CS# out by 2 x I/O
goes high
n bytes read
n bytes read
n bytes read Quad I/O read Quad I/O read n bytes read
out by Dual for bottom for Top 128Mb out by Quad
until CS# goes output until
goes high
128Mb with 6 with 6 dummy
cycles
output until
Action
high
CS# goes high dummy cycles
CS# goes high
4PP
(quad page
program)
BE 32K
(block erase
32KB)
BE
CE
Command
(byte)
PP
SE
(block erase
(chip erase)
64KB)
(page program)
(sector erase)
Mode
Address Bytes
1st byte
SPI/QPI
3/4
SPI
3/4
SPI/QPI
3/4
SPI/QPI
3/4
SPI/QPI
3/4
SPI/QPI
0
02 (hex)
38 (hex)
ADD1
ADD2
ADD3
20 (hex)
ADD1
ADD2
ADD3
52 (hex)
ADD1
ADD2
ADD3
D8 (hex)
ADD1
ADD2
ADD3
60 or C7 (hex)
2nd byte
3rd byte
4th byte
5th byte
1-256
1-256
Data Cycles
to program the quad input to
selected page program the selected sector selected 32K selected block
selected page block
to erase the
to erase the
to erase the to erase whole
chip
Action
* Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in configuration register.
P/N: PM1712
REV. 1.2, NOV. 28, 2013
17
MX25U25635F
Read/Write Array Commands (4 Byte Address Command Set)
Command
(byte)
READ4B
FAST READ4B
2READ4B
DREAD4B
4READ4B
QREAD4B
Mode
SPI
4
SPI
4
SPI
4
SPI
4
SPI/QPI
4
SPI
4
Address Bytes
1st byte
2nd byte
3rd byte
13 (hex)
0C (hex)
BC (hex)
3C (hex)
EC (hex)
6C (hex)
ADD1
ADD2
ADD3
ADD4
ADD1
ADD2
ADD3
ADD4
Dummy
ADD1
ADD2
ADD3
ADD4
Dummy
ADD1
ADD2
ADD3
ADD4
Dummy
ADD1
ADD2
ADD3
ADD4
Dummy
ADD1
ADD2
ADD3
ADD4
Dummy
4th byte
5th byte
6th byte
Data Cycles
read data byte by read data byte by read data byte by Read data byte by read data byte by Read data byte by
4 byte address 4 byte address 2 x I/O with 4 byte Dual Output with 4 x I/O with 4 byte Quad Output with
Action
address
4 byte address
address
4 byte address
BE4B
(block erase
64KB)
BE32K4B
(block erase
32KB)
SE4B
(Sector erase
4KB)
Command
(byte)
PP4B
4PP4B
Mode
SPI/QPI
4
SPI
4
SPI/QPI
4
SPI/QPI
4
SPI/QPI
4
Address Bytes
1st byte
2nd byte
3rd byte
12 (hex)
3E (hex)
DC (hex)
5C (hex)
21 (hex)
ADD1
ADD2
ADD3
ADD4
ADD1
ADD2
ADD3
ADD4
ADD1
ADD2
ADD3
ADD4
ADD1
ADD2
ADD3
ADD4
ADD1
ADD2
ADD3
ADD4
4th byte
5th byte
6th byte
Data Cycles
1-256
1-256
to program the
selected page
with 4byte
Quad input to
program the
selected page
with 4byte
to erase the
to erase the
to erase the
selected (64KB) selected (32KB) selected (4KB)
block with 4byte block with 4byte sector with 4byte
Action
address
address
address
address
address
P/N: PM1712
REV. 1.2, NOV. 28, 2013
18
MX25U25635F
Register/Setting Commands
RDCR
(read
WRSR
RDEAR
WREAR
RDSR
(read status
register)
Command
(byte)
WREN
WRDI
(write status/ (read extended (write extended
(write enable) (write disable)
configuration configuration
address
register)
address
register)
register)
SPI/QPI
15 (hex)
register)
SPI/QPI
01 (hex)
Values
Mode
1st byte
SPI/QPI
06 (hex)
SPI/QPI
04 (hex)
SPI/QPI
05 (hex)
SPI/QPI
C8 (hex)
SPI/QPI
C5 (hex)
2nd byte
3rd byte
4th byte
Values
5th byte
Data Cycles
1-2
1
sets the (WEL)
write enable
latch bit
resets the
(WEL) write
enable latch bit status register configuration
to read out the to read out the to write new read extended write extended
values of the values of the values of the
address
register
address
register
status/
configuration
register
Action
register
PGM/ERS
Suspend
(Suspends
Program/
Erase)
PGM/ERS
Resume
(Resumes
Program/
Erase)
EN4B
(enter 4-byte
mode)
EX4B
(exit 4-byte
mode)
Command
(byte)
EQIO
(Enable QPI)
RSTQIO
(Reset QPI)
DP (Deep
power down)
Mode
1st byte
SPI
QPI
SPI/QPI
B7 (hex)
SPI/QPI
E9 (hex)
SPI/QPI
SPI/QPI
SPI/QPI
B9 (hex)
35 (hex)
F5 (hex)
B0 (hex)
30 (hex)
2nd byte
3rd byte
4th byte
5th byte
Data Cycles
Entering the Exiting the QPI to enter 4-byte to exit 4-byte
enters deep
power down
mode
QPI mode
mode
mode and set mode and clear
Action
4BYTE bit as 4BYTE bit to
"1"
be "0"
RDP (Release
from deep
power down)
SBL
RDFBR
WRFBR
ESFBR
Command
(byte)
(Set Burst
Length)
SPI/QPI
(read fast boot (write fast boot (erase fast
register)
SPI
register)
SPI
boot register)
Mode
1st byte
SPI/QPI
SPI
AB (hex)
C0 (hex)
16(hex)
17(hex)
18(hex)
2nd byte
3rd byte
4th byte
5th byte
Data Cycles
1-4
4
release from
deep power
down mode
to set Burst
length
Action
P/N: PM1712
REV. 1.2, NOV. 28, 2013
19
MX25U25635F
ID/Security Commands
REMS
(read electronic
manufacturer & (QPI ID Read)
device ID)
RDID
RES
ENSO
EXSO
Command
(byte)
QPIID
(read identific- (read electronic
RDSFDP
(enter secured (exit secured
ation)
ID)
OTP)
OTP)
Mode
Address Bytes
SPI
0
SPI/QPI
0
SPI
0
QPI
0
SPI/QPI
3
SPI/QPI
0
SPI/QPI
0
1st byte
2nd byte
3rd byte
4th byte
5th byte
9F (hex)
AB (hex)
90 (hex)
AF (hex)
5A (hex)
B1 (hex)
C1 (hex)
x
x
x
ADD1
ADD2
x
ADD1 (Note 1)
ADD3
Dummy(8)(Note 4)
outputs JEDEC to read out
output the
ID in QPI
interface
Read SFDP
mode
to enter the
4K-bit secured 4K-bit secured
OTP mode OTP mode
to exit the
ID: 1-byte
Manufacturer
ID & 2-byte
Device ID
1-byte Device Manufacturer
ID
ID & Device ID
Action
RDSCUR
(read security (write security
WRSCUR
Command
(byte)
register)
SPI/QPI
0
register)
SPI/QPI
0
Mode
Address Bytes
1st byte
2nd byte
3rd byte
2B (hex)
2F (hex)
4th byte
5th byte
Data Cycles
to read value to set the lock-
of security
register
down bit as
"1" (once lock-
down, cannot
be updated)
Action
P/N: PM1712
REV. 1.2, NOV. 28, 2013
20
MX25U25635F
Reset Commands
RST
(Reset
Memory)
Command
(byte)
NOP
RSTEN
(No Operation) (Reset Enable)
Mode
SPI/QPI
00 (hex)
SPI/QPI
66 (hex) (Note 3) 99 (hex) (Note 3)
SPI/QPI
1st byte
2nd byte
3rd byte
4th byte
5th byte
Action
Note 1: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first.
Note 2: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hid-
den mode.
Note 3: Before executing RST command, RSTEN command must be executed. If there is any other command to interfere, the
reset operation will be disabled.
Note 4: The number in parentheses after "ADD" or "Data" stands for how many clock cycles it has. For example, "Data(8)"
represents there are 8 clock cycles for the data in. Please note the number after "ADD" are based on 3-byte address
mode, for 4-byte address mode, which will be increased.
P/N: PM1712
REV. 1.2, NOV. 28, 2013
21
MX25U25635F
9-1. Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP/
PP4B, 4PP/4PP4B, SE/SE4B, BE32K/BE32K4B, BE/BE4B, CE, WRSR, WREAR, WRFBR, ESFBR, and WRSCUR
which are intended to change the device content WEL bit should be set every time after the WREN instruction set-
ting the WEL bit. Please note that a Write Enable (WREN) instruction must be executed to set the Write Enable
Latch (WEL) bit before sending any of those instructions.
The sequence of issuing WREN instruction is: CS# goes low→sending WREN instruction code→ CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care in
SPI mode.
Figure 7. Write Enable (WREN) Sequence (SPI Mode)
CS#
0
1
2
3
4
5
6
7
Mode 3
Mode 0
SCLK
Command
06h
SI
High-Z
SO
Figure 8. Write Enable (WREN) Sequence (QPI Mode)
CS#
0
1
Mode 3
SCLK
Mode 0
Command
SIO[3:0]
06h
P/N: PM1712
REV. 1.2, NOV. 28, 2013
22
MX25U25635F
9-2. Write Disable (WRDI)
The Write Disable (WRDI) instruction is to reset Write Enable Latch (WEL) bit.
The sequence of issuing WRDI instruction is: CS# goes low→sending WRDI instruction code→CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care in
SPI mode.
The WEL bit is reset by following situations:
- Power-up
- Reset# pin driven low
- WRDI command completion
- WRSR command completion
- PP/PP4B command completion
- 4PP/4PP4B command completion
- SE/SE4B command completion
- BE32K/BE32K4B command completion
- BE/BE4B command completion
- CE command completion
- PGM/ERS Suspend command completion
- Softreset command completion
- WRSCUR command completion
- WREAR command completion
- WRFBR command completion
- ESFBR command completion
Figure 9. Write Disable (WRDI) Sequence (SPI Mode)
CS#
Mode 3
Mode 0
0
1
2
3
4
5
6
7
SCLK
Command
04h
SI
High-Z
SO
Figure 10. Write Disable (WRDI) Sequence (QPI Mode)
CS#
0
1
Mode 3
SCLK
Mode 0
Command
SIO[3:0]
04h
P/N: PM1712
REV. 1.2, NOV. 28, 2013
23
MX25U25635F
9-3. Read Identification (RDID)
The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Macro-
nix Manufacturer ID and Device ID are listed as Table 6 ID Definitions.
The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code→24-bits ID data out
on SO→ to end RDID operation can drive CS# to high at any time during data out.
While Program/Erase operation is in progress, it will not decode the RDID instruction, therefore there's no effect on
the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby
stage.
Figure 11. Read Identification (RDID) Sequence (SPI mode only)
CS#
0
1
2
3
4
5
6
7
8
9
10
13 14 15 16 17 18
28 29 30 31
Mode 3
Mode 0
SCLK
SI
Command
9Fh
Manufacturer Identification
Device Identification
High-Z
SO
7
6
5
2
1
0
15 14 13
MSB
3
2
1
0
MSB
P/N: PM1712
REV. 1.2, NOV. 28, 2013
24
MX25U25635F
9-4. Release from Deep Power-down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is completed by driving Chip Select (CS#) High. When Chip
Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the
Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in
the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip
Select (CS#) must remain High for at least tRES2(max), as specified in Table 17. AC Characteristics. Once in the
Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. The
RDP instruction is only for releasing from Deep Power Down Mode. Reset# pin goes low will release the Flash from
deep power down mode.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as Table 6 ID
Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new design,
please use RDID instruction.
Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in
progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeat-
edly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously
in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in
Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least
tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute
instruction.
Figure 12. Read Electronic Signature (RES) Sequence (SPI Mode)
CS#
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38
SCLK
Command
ABh
t
3 Dummy Bytes
RES2
SI
23 22 21
MSB
3
2
1
0
Electronic Signature Out
High-Z
7
6
5
4
3
2
0
1
SO
MSB
Deep Power-down Mode
Stand-by Mode
P/N: PM1712
REV. 1.2, NOV. 28, 2013
25
MX25U25635F
Figure 13. Read Electronic Signature (RES) Sequence (QPI Mode)
CS#
MODE 3
0
1
2
3
4
5
6
7
SCLK
MODE 0
3 Dummy Bytes
Command
ABh
SIO[3:0]
X
X
X
X
X
X
H0 L0
MSB LSB
Data Out
Data In
Stand-by Mode
Deep Power-down Mode
Figure 14. Release from Deep Power-down (RDP) Sequence (SPI Mode)
CS#
t
RES1
0
1
2
3
4
5
6
7
Mode 3
Mode 0
SCLK
SI
Command
ABh
High-Z
SO
Deep Power-down Mode
Stand-by Mode
Figure 15. Release from Deep Power-down (RDP) Sequence (QPI Mode)
CS#
t
RES1
Mode 3
Mode 0
0
1
SCLK
Command
SIO[3:0]
ABh
Deep Power-down Mode
Stand-by Mode
P/N: PM1712
REV. 1.2, NOV. 28, 2013
26
MX25U25635F
9-5. Read Electronic Manufacturer ID & Device ID (REMS)
The REMS instruction is an alternative to the Release from Power-down/Device ID instruction that provides both the
JEDEC assigned manufacturer ID and the specific device ID.
The REMS instruction is very similar to the Release from Power-down/Device ID instruction. The instruction is initi-
ated by driving the CS# pin low and shift the instruction code "90h" followed by two dummy bytes and one bytes ad-
dress (A7~A0). After which, the Manufacturer ID for Macronix (C2h) and the Device ID are shifted out on the falling
edge of SCLK with most significant bit (MSB) first. The Device ID values are listed in Table 6 of ID Definitions. If the
one-byte address is initially set to 01h, then the device ID will be read first and then followed by the Manufacturer
ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is
completed by driving CS# high.
Figure 16. Read Electronic Manufacturer & Device ID (REMS) Sequence (SPI Mode only)
CS#
0
1
2
3
4
5
6
7
8
9 10
Mode 3
Mode 0
SCLK
Command
90h
2 Dummy Bytes
SI
15 14 13
3
2
1
0
High-Z
SO
CS#
47
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
SCLK
ADD (1)
7
6
5
4
3
2
0
1
SI
Manufacturer ID
Device ID
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
SO
MSB
MSB
MSB
Notes:
(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first.
P/N: PM1712
REV. 1.2, NOV. 28, 2013
27
MX25U25635F
9-6. QPI ID Read (QPIID)
User can execute this ID Read (QPIID Read) instruction to identify the Device ID and Manufacturer ID. The
sequence of issue QPIID instruction is CS# goes low→sending QPI ID instruction→Data out on SO→CS# goes
high. Most significant bit (MSB) first.
After the command cycle, the device will immediately output data on the falling edge of SCLK. The manufacturer ID,
memory type, and device ID data byte will be output continuously, until the CS# goes high.
Table 6. ID Definitions
Command Type
MX25U25635F
Manufactory ID
C2
Memory type
Memory density
39
RDID
RES
9Fh
25
Electronic ID
39
Device ID
39
ABh
90h
AFh
Manufactory ID
REMS
QPIID
C2
Manufactory ID
C2
Memory type
25
Memory density
39
P/N: PM1712
REV. 1.2, NOV. 28, 2013
28
MX25U25635F
9-7. Read Status Register (RDSR)
The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even
in program/erase/write status register condition). It is recommended to check the Write in Progress (WIP) bit before
sending a new instruction when a program, erase, or write status register operation is in progress.
The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register data
out on SO.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
Figure 17. Read Status Register (RDSR) Sequence (SPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Mode 3
Mode 0
SCLK
SI
command
05h
Status Register Out
Status Register Out
High-Z
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
Figure 18. Read Status Register (RDSR) Sequence (QPI Mode)
CS#
Mode 3
Mode 0
0
1
2
3
4
5
6
7
N
SCLK
SIO[3:0]
05h
H0 L0 H0 L0 H0 L0
H0 L0
MSB
LSB
Status Byte Status Byte Status Byte
Status Byte
P/N: PM1712
REV. 1.2, NOV. 28, 2013
29
MX25U25635F
9-8. Read Configuration Register (RDCR)
The RDCR instruction is for reading Configuration Register Bits. The Read Configuration Register can be read at
any time (even in program/erase/write configuration register condition).
The sequence of issuing RDCR instruction is: CS# goes low→ sending RDCR instruction code→ Configuration Reg-
ister data out on SO.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
Figure 19. Read Configuration Register (RDCR) Sequence (SPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Mode 3
Mode 0
SCLK
SI
command
15h
Configuration register Out
Configuration register Out
High-Z
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
Figure 20. Read Configuration Register (RDCR) Sequence (QPI Mode)
CS#
Mode 3
Mode 0
N
0
1
2
3
4
5
6
7
SCLK
SIO[3:0]
15h
H0 L0 H0 L0 H0 L0
H0 L0
MSB
LSB
Config. Byte Config. Byte Config. Byte
Config. Byte
P/N: PM1712
REV. 1.2, NOV. 28, 2013
30
MX25U25635F
For user to check if Program/Erase operation is finished or not, RDSR instruction flow are shown as follows:
Figure 21. Program/Erase flow with read array data
start
WREN command
RDSR command*
No
WEL=1?
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
No
WIP=0?
Yes
RDSR command
Read WEL=0, BP[3:0], QE,
and SRWD data
Read array data
(same address of PGM/ERS)
No
Verify OK?
Yes
Program/erase successfully
Program/erase fail
Yes
Program/erase
another block?
* Issue RDSR to check BP[3:0].
No
Program/erase completed
P/N: PM1712
REV. 1.2, NOV. 28, 2013
31
MX25U25635F
Figure 22. Program/Erase flow without read array data (read P_FAIL/E_FAIL flag)
start
WREN command
RDSR command*
No
WEL=1?
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
No
WIP=0?
Yes
RDSR command
Read WEL=0, BP[3:0], QE,
and SRWD data
RDSCUR command
P_FAIL/E_FAIL =1 ?
Yes
No
Program/erase successfully
Program/erase fail
Yes
Program/erase
another block?
* Issue RDSR to check BP[3:0].
No
Program/erase completed
P/N: PM1712
REV. 1.2, NOV. 28, 2013
32
MX25U25635F
Status Register
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write sta-
tus register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register
progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register
cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable
latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/
erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device
will not accept program/erase/write status register instruction. The program/erase command will be ignored if it is ap-
plied to a protected memory area. To ensure both WIP bit & WEL bit are both set to 0 and available for next program/
erase/operations, WIP bit needs to be confirm to be 0 before polling WEL bit. After WIP bit confirmed, WEL bit needs
to be confirm to be 0.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area (as
defined in Table 2) of the device to against the program/erase instruction without hardware protection mode being set.
To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be ex-
ecuted. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block
Erase 32KB (BE32K), Block Erase (BE) and Chip Erase (CE) instructions (only if Block Protect bits (BP3:BP0) set to 0,
the CE instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default. Which is un-protected.
QE bit. The Quad Enable (QE) bit, non-volatile bit, while it is "0" (factory default), it performs non-Quad and WP#,
RESET# are enable. While QE is "1", it performs Quad I/O mode and WP#, RESET# are disabled. In the other
word, if the system goes into four I/O mode (QE=1), the feature of HPM and RESET will be disabled.
SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection
(WP#/SIO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and
WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is
no longer accepted for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only. The
SRWD bit defaults to be "0".
Status Register
bit7
bit6
bit5
BP3
(level of
protected
block)
bit4
BP2
(level of
protected
block)
bit3
BP1
(level of
protected
block)
bit2
BP0
(level of
protected
block)
bit1
bit0
SRWD (status
register write
protect)
QE
(Quad
Enable)
WEL
(write enable
latch)
WIP
(write in
progress bit)
1=Quad
Enable
0=not Quad
Enable
1=write
enable
0=not write 0=not in write
1=write
operation
1=status
register write
disable
(note 1)
(note 1)
(note 1)
(note 1)
enable
operation
Non-volatile Non-volatile Non-volatile Non-volatile Non-volatile Non-volatile
bit bit bit bit bit bit
volatile bit
volatile bit
Note 1: see the Table 2 "Protected Area Size".
P/N: PM1712
REV. 1.2, NOV. 28, 2013
33
MX25U25635F
Configuration Register
The Configuration Register is able to change the default status of Flash memory. Flash memory will be configured
after the CR bit is set.
DC bits
The dummy cycle (DC1, DC2) bits are volatile bits, which indicate the number of dummy cycles (as defined in
Dummy Cycle and Frequency Table ) of the device. The default Dummy Cycle bits are DC[1:0]=00. To write the
Dummy cycle bits requires the Write Status Register (WRSR) instruction to be executed. Please note that only
MX25U25635FZ4I-08G supports 133MHz with 10 dummy cycles. The value of DC[1:0] will not be changed when
users try to set all other products' DC[1:0] to 11b.
ODS bit
The output driver strength (ODS2, ODS1, ODS0) bits are volatile bits, which indicate the output driver level (as
defined in Output Driver Strength Table) of the device. The Output Driver Strength is defaulted as 30 Ohms when
delivered from factory. To write the ODS bits requires the Write Status Register (WRSR) instruction to be executed.
TB bit
The Top/Bottom (TB) bit is a non-volatile OTP bit. The Top/Bottom (TB) bit is used to configure the Block Protect
area by BP bit (BP3, BP2, BP1, BP0), starting from TOP or Bottom of the memory array. The TB bit is defaulted as
“0”, which means Top area protect. When it is set as “1”, the protect area will change to Bottom area of the memory
device. To write the TB bits requires the Write Status Register (WRSR) instruction to be executed.
4BYTE Indicator bit
By writing EN4B instruction, the 4BYTE bit may be set as "1" to access the address length of 32-bit for memory area
of higher density (large than 128Mb). The default state is "0" as the 24-bit address mode. The 4BYTE bit may be
cleared by power-off or writing EX4B instruction to reset the state to be "0".
Configuration Register
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DC1
DC0
TB
ODS 2
ODS 1
ODS 0
(Dummy
cycle 1)
(Dummy
cycle 0)
4 BYTE
Reserved
(top/bottom (output driver (output driver (output driver
selected)
strength)
strength)
strength)
0=3-byte
address
mode
0=Top area
protect
(note 2)
(note 2)
1=4-byte
address
mode
x
x
1=Bottom
area protect
(Default=0)
(note 1)
(note 1)
(note 1)
(Default=0)
volatile bit
volatile bit
volatile bit
OTP
volatile bit
volatile bit
volatile bit
Note 1: see "Output Driver Strength Table"
Note 2: see "Dummy Cycle and Frequency Table (MHz)"
P/N: PM1712
REV. 1.2, NOV. 28, 2013
34
MX25U25635F
Output Driver Strength Table
ODS2
ODS1
ODS0
Description
Reserved
90 Ohms
60 Ohms
45 Ohms
Note
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Impedance at VCC/2
Reserved
20 Ohms
15 Ohms
30 Ohms (Default)
Dummy Cycle and Frequency Table (MHz)
Numbers of Dummy
Dual Output Fast
Quad Output Fast
DC[1:0]
Fast Read
clock cycles
Read
108
108
108
133
Read
108
84
108
133
00 (default)
01
10
11 (Note)
8
6
8
108
108
108
133
10
Numbers of Dummy
DC[1:0]
Dual IO Fast Read
clock cycles
00 (default)
01
10
11(Note)
4
6
8
84
108
108
133
10
Numbers of Dummy
DC[1:0]
Quad IO Fast Read
clock cycles
00 (default)
01
6
4
84
70
10
11 (Note)
8
10
108
133
Note: Please note that only MX25U25635FZ4I-08G can support 133MHz with 10 dummy cycles.
All other products are not able to set DC[1:0] to 11b.
P/N: PM1712
REV. 1.2, NOV. 28, 2013
35
MX25U25635F
9-9. Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits and Configuration Register Bits. Before
sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write
Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1,
BP0) bits to define the protected area of memory (as shown in Table 2). The WRSR also can set or reset the Quad
enable (QE) bit and set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#/
SIO2) pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of the status register. The WRSR instruction cannot
be executed once the Hardware Protected Mode (HPM) is entered.
The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register
data on SI→CS# goes high.
The CS# must go high exactly at the 8 bits or 16 bits data boundary; otherwise, the instruction will be rejected and
not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes
high. The Write in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress.
The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write En-
able Latch (WEL) bit is reset.
Figure 23. Write Status Register (WRSR) Sequence (SPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Mode 3
Mode 0
SCLK
command
01h
Status
Register In
Configuration
Register In
SI
4
15 14
13
12 11
10 9
8
2
1
0
7
6
5
3
MSB
High-Z
SO
Note : The CS# must go high exactly at 8 bits or 16 bits data boundary to completed the write register command.
Figure 24. Write Status Register (WRSR) Sequence (QPI Mode)
CS#
Mode 3
Mode 0
Mode 3
Mode 0
0
1
2
3
4
5
SCLK
CR in
SR in
Command
01h
H0 L0 H1 L1
SIO[3:0]
P/N: PM1712
REV. 1.2, NOV. 28, 2013
36
MX25U25635F
Software Protected Mode (SPM):
-
When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can
change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1,
BP0 and T/B bit, is at software protected mode (SPM).
-
When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values
of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0 and T/B bit, is at
software protected mode (SPM)
Note:
If SRWD bit=1 but WP#/SIO2 is low, it is impossible to write the Status Register even if the WEL bit has previously
been set. It is rejected to write the Status Register and not be executed.
Hardware Protected Mode (HPM):
-
When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware
protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2,
BP1, BP0 and T/B bit and hardware protected mode by the WP#/SIO2 to against data modification.
Note:
To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered.
If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be entered; only
can use software protected mode via BP3, BP2, BP1, BP0 and T/B bit.
If the system enter QPI or set QE=1, the feature of HPM will be disabled.
Table 7. Protection Modes
Mode
Status register condition
WP# and SRWD bit status
Memory
Status register can be written
in (WEL bit is set to "1") and
the SRWD, BP0-BP3
Software protection
mode (SPM)
WP#=1 and SRWD bit=0, or
WP#=0 and SRWD bit=0, or
WP#=1 and SRWD=1
The protected area
cannot
be program or erase.
bits can be changed
The SRWD, BP0-BP3 of
status register bits cannot be
changed
The protected area
cannot
be program or erase.
Hardware protection
mode (HPM)
WP#=0, SRWD bit=1
Note:
1. As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in
Table 2.
P/N: PM1712
REV. 1.2, NOV. 28, 2013
37
MX25U25635F
Figure 25. WRSR flow
start
WREN command
RDSR command
No
WEL=1?
Yes
WRSR command
Write status register data
RDSR command
No
WIP=0?
Yes
RDSR command
Read WEL=0, BP[3:0], QE,
and SRWD data
No
Verify OK?
Yes
WRSR successfully
WRSR fail
P/N: PM1712
REV. 1.2, NOV. 28, 2013
38
MX25U25635F
Figure 26. WP# Setup Timing and Hold Timing during WRSR when SRWD=1
WP#
CS#
tSHWL
tWHSL
0
1
2
3
4
5
6
7
8
9
10 11 12
13 14
15
SCLK
01h
SI
High-Z
SO
P/N: PM1712
REV. 1.2, NOV. 28, 2013
39
MX25U25635F
9-10. Enter 4-byte mode (EN4B)
The EN4B instruction enables accessing the address length of 32-bit for the memory area of higher density (larger
than 128Mb). The device default is in 24-bit address mode; after sending out the EN4B instruction, the bit5 (4BYTE
bit) of configuration register will be automatically set to "1" to indicate the 4-byte address mode has been enabled.
Once the 4-byte address mode is enabled, the address length becomes 32-bit instead of the default 24-bit. There
are three methods to exit the 4-byte mode: writing exit 4-byte mode (EX4B) instruction, Reset or power-off.
All instructions are accepted normally, and just the address bit is changed from 24-bit to 32-bit.
The following command don't support 4bye address: 4READ for top 128Mb (EAh), RDSFDP, RES and REMS.
The sequence of issuing EN4B instruction is: CS# goes low → sending EN4B instruction to enter 4-byte mode
(automatically set 4BYTE bit as "1") → CS# goes high.
9-11. Exit 4-byte mode (EX4B)
The EX4B instruction is executed to exit the 4-byte address mode and return to the default 3-bytes address mode.
After sending out the EX4B instruction, the bit5 (4BYTE bit) of Configuration register will be cleared to be "0" to
indicate the exit of the 4-byte address mode. Once exiting the 4-byte address mode, the address length will return to
24-bit.
The sequence of issuing EX4B instruction is: CS# goes low→ sending EX4B instruction to exit 4-byte mode
(automatically clear the 4BYTE bit to be "0") → CS# goes high.
P/N: PM1712
REV. 1.2, NOV. 28, 2013
40
MX25U25635F
9-12. Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on
the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address
is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can
be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been
reached.
The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the
4-byte address read mode or to define EAR bit. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B)
Mode section.
The sequence of issuing READ instruction is: CS# goes low→sending READ instruction code→ 3-byte or 4-byte
address on SI→ data out on SO→to end READ operation can use CS# to high at any time during data out.
Figure 27. Read Data Bytes (READ) Sequence (SPI Mode only)
CS#
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
command
03h
24-Bit Address
(Note)
23 22 21
MSB
3
2
1
0
SI
Data Out 1
Data Out 2
High-Z
2
7
6
5
4
3
1
7
0
SO
MSB
Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the
address cycles will be increased.
P/N: PM1712
REV. 1.2, NOV. 28, 2013
41
MX25U25635F
9-13. Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at
any location. The address is automatically increased to the next higher address after each byte data is shifted out,
so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when
the highest address has been reached.
The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the
4-byte address read mode or to define EAR bit. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B)
Mode section.
Read on SPI Mode The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ
instruction code→ 3-byte or 4-byte address on SI→ 8 dummy cycles (default)→ data out on SO→ to end FAST_
READ operation can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any im-
pact on the Program/Erase/Write Status Register current cycle.
Figure 28. Read at Higher Speed (FAST_READ) Sequence (SPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
Mode 3
Mode 0
SCLK
Command
0Bh
24-Bit Address
(Note)
SI
23 22 21
3
2
1
0
High-Z
SO
CS#
47
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
SCLK
Configurable
Dummy Cycle
7
6
5
4
3
2
0
1
SI
DATA OUT 2
DATA OUT 1
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
SO
MSB
MSB
MSB
Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the
address cycles will be increased.
P/N: PM1712
REV. 1.2, NOV. 28, 2013
42
MX25U25635F
9-14. Dual Output Read Mode (DREAD)
The DREAD instruction enable double throughput of Serial Flash in read mode. The address is latched on rising
edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maxi-
mum frequency fT. The first address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD instruc-
tion. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruc-
tion, the following data out will perform as 2-bit instead of previous 1-bit.
The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the
4-byte address read mode or to define EAR bit. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B)
Mode section.
The sequence of issuing DREAD instruction is: CS# goes low
sending DREAD instruction 3-byte or 4-byte
→
→
address on SIO0 8 dummy cycles (default) on SIO0
data out interleave on SIO1 & SIO0
to end DREAD op-
→
→
→
eration can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
Figure 29. Dual Read Mode Sequence
CS#
30 31 32
39 40 41 42 43 44 45
0
1
2
3
4
5
6
7
8
9
SCLK
…
…
Data Out
Data Out
1
Configurable
Dummy Cycle
Command
24 ADD Cycle
2
…
A23 A22
A1 A0
D4 D2
D6 D4
D7 D5
3B
D6
D7
D0
SI/SIO0
High Impedance
D1
D5 D3
SO/SIO1
Notes:
1. Please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address
cycles will be increased.
P/N: PM1712
REV. 1.2, NOV. 28, 2013
43
MX25U25635F
9-15. 2 x I/O Read Mode (2READ)
The 2READ instruction enable double throughput of Serial Flash in read mode. The address is latched on rising
edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maxi-
mum frequency fT. The first address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ instruc-
tion. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ instruc-
tion, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit.
The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the
4-byte address read mode or to define EAR bit. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B)
Mode section.
The sequence of issuing 2READ instruction is: CS# goes low sending 2READ instruction 3-byte or 4-byte ad-
→
→
dress interleave on SIO1 & SIO0 4 dummy cycles (default) on SIO1 & SIO0 data out interleave on SIO1 &
→
→
SIO0 to end 2READ operation can use CS# to high at any time during data out.
→
While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
Figure 30. 2 x I/O Read Mode Sequence (SPI Mode only)
CS#
Mode 3
Mode 0
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
17 18 19 20 21 22 23 24 25 26 27 28 29 30
SCLK
Data
Data
Configurable
Dummy Cycle
12 ADD Cycles
(Note)
Command
Out 1
Out 2
D6 D4 D2 D0 D6 D4 D2 D0
A22 A20 A18
A4 A2 A0
BBh
SI/SIO0
D7 D5 D3 D1 D7 D5 D3 D1
A23 A21 A19
A5 A3 A1
SO/SIO1
Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the
address cycles will be increased.
P/N: PM1712
REV. 1.2, NOV. 28, 2013
44
MX25U25635F
9-16. Quad Read Mode (QREAD)
The QREAD instruction enable quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status
Register must be set to "1" before sending the QREAD instruction. The address is latched on rising edge of SCLK,
and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency
fQ. The first address byte can be at any location. The address is automatically increased to the next higher address
after each byte data is shifted out, so the whole memory can be read out at a single QREAD instruction. The ad-
dress counter rolls over to 0 when the highest address has been reached. Once writing QREAD instruction, the fol-
lowing data out will perform as 4-bit instead of previous 1-bit.
The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the
4-byte address read mode or to define EAR bit. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B)
Mode section.
The sequence of issuing QREAD instruction is: CS# goes low
sending QREAD instruction → 3-byte or 4-byte
→
address on SI
8 dummy cycle (Default)
data out interleave on SO3, SO2, SO1 & SO0
to end QREAD op-
→
→
→
eration can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
Figure 31. Quad Read Mode Sequence
CS#
29 30 31 32 33
38 39 40 41 42
0
1
2
3
4
5
6
7
8
9
SCLK
…
…
Configurable
dummy cycles
Data
Out 1
Data Data
Out 2 Out 3
Command
6B
24 ADD Cycles
…
A23A22
A2 A1 A0
D4 D0 D4 D0 D4
SIO0
SIO1
SIO2
SIO3
High Impedance
High Impedance
High Impedance
D5 D1 D5 D1 D5
D6 D2 D6 D2 D6
D7 D3 D7 D3 D7
Notes:
1. Please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address
cycles will be increased.
2. The MSB is on SIO3 which is different from 1 x I/O condition.
P/N: PM1712
REV. 1.2, NOV. 28, 2013
45
MX25U25635F
9-17. 4 x I/O Read Mode (4READ)
The 4READ instruction enable quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status Reg-
ister must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCLK, and
data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ.
The first address byte can be at any location. The address is automatically increased to the next higher address af-
ter each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address
counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following
address/dummy/data out will perform as 4-bit instead of previous 1-bit.
The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the
4-byte address read mode or to define EAR bit. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B)
Mode section.
4 x I/O Read on SPI Mode (4READ) The sequence of issuing 4READ instruction is: CS# goes low sending
→
4READ instruction 3-byte or 4-byte address interleave on SIO3, SIO2, SIO1 & SIO0 6 dummy cycles (Default)
→
→
data out interleave on SIO3, SIO2, SIO1 & SIO0 to end 4READ operation can use CS# to high at any time dur-
→
→
ing data out.
4 x I/O Read on QPI Mode (4READ) The 4READ instruction also support on QPI command mode. The sequence
of issuing 4READ instruction QPI mode is: CS# goes low sending 4READ instruction 3-byte or 4-byte address
→
→
interleave on SIO3, SIO2, SIO1 & SIO0 6 dummy cycles (Default) data out interleave on SIO3, SIO2, SIO1 &
→
→
SIO0 to end 4READ operation can use CS# to high at any time during data out.
→
While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
P/N: PM1712
REV. 1.2, NOV. 28, 2013
46
MX25U25635F
Figure 32. 4 x I/O Read Mode Sequence (SPI Mode)
CS#
23 24
10 11 12 13 14 15 16 17 18 19 20 21 22
Mode 3
Mode 0
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
SCLK
Data
Out 1
Data
Out 2 Out 3
Data
Command
EAh/EBh
6 ADD Cycles
Performance
enhance
indicator (Note 1)
Configurable
Dummy Cycle (Note 3)
A20 A16 A12 A8 A4 A0
D4 D0 D4 D0 D4 D0
P4 P0
SIO0
SIO1
SIO2
SIO3
A21 A17 A13 A9 A5 A1
A22 A18 A14 A10 A6 A2
D5 D1 D5 D1 D5 D1
D6 D2 D6 D2 D6 D2
P5 P1
P6 P2
A23 A19 A15 A11 A7 A3
D7 D3 D7 D3 D7 D3
P7 P3
Note:
1. Hi-impedance is inhibited for the two clock cycles.
2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited.
3. Configuration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in
configuration register.
4. Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the
address cycles will be increased.
5. The MSB is on SIO3 which is different from 1 x I/O condition
Figure 33. 4 x I/O Read Mode Sequence (QPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MODE 3
MODE 0
MODE 3
MODE 0
SCLK
EAh/EBh
Data In
SIO[3:0]
H0 L0 H1 L1 H2 L2 H3 L3
A5 A4 A3 A2 A1 A0
X
X
X
X
X
X
MSB
Data Out
24-bit Address
(Note)
Configurable
Dummy Cycle
Note:
1. Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address
cycles will be increased.
2. The MSB is on SIO3 which is different from 1 x I/O condition.
P/N: PM1712
REV. 1.2, NOV. 28, 2013
47
MX25U25635F
9-18. 4 Byte Address Command Set
The operation of 4-byte address command set was very similar to original 3-byte address command set. The
only different is all the 4-byte command set request 4-byte address (A31-A0) followed by instruction code. The
command set support 4-byte address including: READ4B, Fast_Read4B, DREAD4B, 2READ4B, QREAD4B,
4READ4B, PP4B, 4PP4B, SE4B, BE32K4B, BE4B. Please note that it is not necessary to issue EN4B command
before issuing any of 4-byte command set.
Figure 34. Read Data Bytes using 4 Byte Address Sequence (READ4B)
CS#
0
1
2
3
4
5
6
7
8
9
10
36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Command
13h
32-bit address
31 30 29
MSB
3
2
1
0
SI
DataOut 1
DataOut 2
7
High Impedance
2
SO
7
6
5
4
3
1
0
MSB
Figure 35. Read Data Bytes at Higher Speed using 4 Byte Address Sequence (Fase_Read4B)
CS#
0
1
2
3
4
5
6
7
8
9
10
36 37 38 39
SCLK
Command
0Ch
32-bit address
31 30 29
3
2
1
0
SI
High Impedance
SO
CS#
55
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54
SCLK
Configurable
Dummy cycles
SI
7
6
5
4
3
2
0
1
DATAOUT2
DATAOUT1
7
6
5
4
3
2
1
0
7
SO
7
6
5
4
3
2
0
1
MSB
MSB
MSB
P/N: PM1712
REV. 1.2, NOV. 28, 2013
48
MX25U25635F
Figure 36. 2 x I/O Fast Read using 4 Byte Address Sequence (2READ4B)
CS#
Mode 3
Mode 0
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
21 22 23 24 25 26 27 28 29 30 31 32 33 34
SCLK
Data
Data
Configurable
Dummy Cycle
16 ADD Cycles
Command
Out 1
Out 2
D6 D4 D2 D0 D6 D4 D2 D0
A30 A28 A26
A31 A29 A27
A4 A2 A0
BCh
SI/SIO0
D7 D5 D3 D1 D7 D5 D3 D1
A5 A3 A1
SO/SIO1
Figure 37. 4 I/O Fast Read using 4 Byte Address sequence (4READ4B)
CS#
23 24 25 26
9 10 11 12 13 14 15 16 17 18 19 20 21 22
Mode 3
Mode 0
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
SCLK
Command
8 ADD Cycles
Data
Out 1
Data
Out 2
Data
Out 3
Performance
enhance
indicator
Configurable
Dummy Cycle
A16
D4 D0 D4 D0 D4 D0
A28 A24
A29 A25
A20
A12 A8 A4 A0
P4 P0
P5 P1
P6 P2
P7 P3
ECh
SIO0
SIO1
SIO2
SIO3
A21 A17 A13 A9 A5 A1
D5 D1 D5 D1 D5 D1
D6 D2 D6 D2 D6 D2
A30 A26 A22 A18 A14 A10 A6 A2
A31 A27
A23 A19 A15 A11 A7 A3
D7 D3 D7 D3 D7 D3
P/N: PM1712
REV. 1.2, NOV. 28, 2013
49
MX25U25635F
9-19. Burst Read
This device supports Burst Read in both SPI and QPI mode.
To set the Burst length, following command operation is required to issue command: “C0h” in the first Byte (8-clocks),
following 4 clocks defining wrap around enable with “0h” and disable with“1h”.
The next 4 clocks are to define wrap around depth. Their definitions are as the following table:
Data
00h
01h
02h
03h
1xh
Wrap Around
Wrap Depth
8-byte
Yes
Yes
Yes
Yes
No
16-byte
32-byte
64-byte
X
The wrap around unit is defined within the 256Byte page, with random initial address. It is defined as “wrap-around
mode disable” for the default state of the device. To exit wrap around, it is required to issue another “C0” command
in which data=‘1xh”. Otherwise, wrap around status will be retained until power down or reset command. To change
wrap around depth, it is requried to issue another “C0” command in which data=“0xh”. QPI “EAh” “EBh” and SPI
"EAh" “EBh” support wrap around feature after wrap around is enabled. Burst read is supported in both SPI and QPI
mode. The device is default without Burst read.
Figure 38. SPI Mode
CS#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Mode 3
Mode 0
SCLK
SIO
D7
D6
D5
D4
D3
D2
D1
D0
C0h
Figure 39. QPI Mode
CS#
0
1
2
3
Mode 3
Mode 0
SCLK
C0h
H0
L0
SIO[3:0]
MSB LSB
Note: MSB=Most Significant Bit
LSB=Least Significant Bit
P/N: PM1712
REV. 1.2, NOV. 28, 2013
50
MX25U25635F
9-20. Performance Enhance Mode
The device could waive the command cycle bits if the two cycle bits after address cycle toggles.
Performance enhance mode is supported in both SPI and QPI mode.
In QPI mode, “EAh” “EBh” "ECh" and SPI "EAh" “EBh” "ECh" commands support enhance mode. The performance
enhance mode is not supported in dual I/O mode.
To enter performance-enhancing mode, P[7:4] must be toggling with P[3:0]; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh
can make this mode continue and skip the next 4READ instruction. To leave enhance mode, P[7:4] is no longer tog-
gling with P[3:0]; likewise P[7:0]=FFh, 00h, AAh or 55h along with CS# is afterwards raised and then lowered. Input
command "FFh(3-byte address mode)" or data "3FFh(4-byte address mode)" can also exit enhance mode. The sys-
tem then will leave performance enhance mode and return to normal operation.
After entering enhance mode, following CS# go high, the device will stay in the read mode and treat CS# go low of
the first clock as address instead of command cycle.
Another sequence of issuing 4READ instruction especially useful in random access is : CS# goes low sending 4
→
READ instruction 3-bytes or 4-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 performance enhance tog-
→
→
gling bit P[7:0] 4 dummy cycles (Default) data out still CS# goes high CS# goes low (reduce 4 Read instruc-
→
→
→
tion)
3-bytes or 4-bytes random access address.
→
P/N: PM1712
REV. 1.2, NOV. 28, 2013
51
MX25U25635F
Figure 40. 4 x I/O Read enhance performance Mode Sequence (SPI Mode)
CS#
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22
n
SCLK
Data
Data
Out 2
Data
Out n
Command
6 ADD Cycles
Performance
enhance
Out 1
indicator (Note 1)
Configurable
Dummy Cycle (Note 2)
P4 P0
D4 D0 D4 D0
D4 D0
A20 A16 A12 A8 A4 A0
EAh/EBh
SIO0
SIO1
SIO2
A21 A17 A13 A9 A5 A1
A22 A18 A14 A10 A6 A2
D5 D1 D5 D1
D6 D2 D6 D2
D5 D1
D6 D2
P5 P1
P6 P2
A23 A19 A15 A11 A7 A3
D7 D3 D7 D3
D7 D3
P7 P3
SIO3
CS#
n+1
...........
n+7......n+9 ........... n+13
...........
Mode 3
Mode 0
SCLK
Data
Out 1
Data
Out 2
Data
Out n
6 ADD Cycles
Performance
enhance
indicator (Note 1)
Configurable
Dummy Cycle (Note 2)
D4 D0 D4 D0
D4 D0
P4 P0
A20 A16 A12 A8 A4 A0
SIO0
SIO1
SIO2
SIO3
D5 D1 D5 D1
D6 D2 D6 D2
D5 D1
D6 D2
A21 A17 A13 A9 A5 A1
A22 A18 A14 A10 A6 A2
P5 P1
P6 P2
D7 D3 D7 D3
D7 D3
A23 A19 A15 A11 A7 A3
P7 P3
Notes:
1. If not using performance enhance recommend to keep 1 or 0 in performance enhance indicator.
2. Configuration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in
configuration register.
3. The MSB is on SIO3 which is different from 1 x I/O condition.
P/N: PM1712
REV. 1.2, NOV. 28, 2013
52
MX25U25635F
Figure 41. 4 x I/O Read enhance performance Mode Sequence (QPI Mode)
CS#
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
SCLK
EAh/EBh
SIO[3:0]
X
X
X
X
H0 L0 H1 L1
MSB LSB MSB LSB
A5 A4 A3 A2 A1 A0
P(7:4)P(3:0)
Data In
Data Out
performance
enhance
indicator
Configurable
Dummy Cycle (Note 1)
CS#
SCLK
n+1 .............
Mode 0
SIO[3:0]
X
X
X
X
H0 L0 H1 L1
MSB LSB MSB LSB
A5 A4 A3 A2 A1 A0
P(7:4)P(3:0)
Data Out
6 Address cycles
performance
enhance
indicator
Configurable
Dummy Cycle (Note 1)
Notes:
1. Configuration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in
configuration register.
2. Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address
cycles will be increased.
P/N: PM1712
REV. 1.2, NOV. 28, 2013
53
MX25U25635F
9-21. Performance Enhance Mode Reset
To conduct the Performance Enhance Mode Reset operation in SPI mode, FFh data cycle(8 clocks in 3-byte ad-
dress mode)/3FFh data cycle(10 clocks in 4-byte address mode), should be issued in 1I/O sequence. In QPI Mode,
FFFFFFFFh data cycle(8 clocks in 3-byte address mode)/FFFFFFFFFFh data cycle (10 clocks in 4-byte address
mode), in 4I/O should be issued.
If the system controller is being Reset during operation, the flash device will return to the standard SPI operation.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
Figure 42. Performance Enhance Mode Reset for Fast Read Quad I/O (SPI Mode)
Mode Bit Reset
for Quad I/O
CS#
Mode 3
Mode 3
０
1
2
3
4
5
6
7
SCLK
Mode ０
Mode ０
FFh
SIO0
SIO1
SIO2
Don’t Care
Don’t Care
Don’t Care
SIO3
Figure 43. Performance Enhance Mode Reset for Fast Read Quad I/O (QPI Mode)
Mode Bit Reset
for Quad I/O
CS#
Mode 3
Mode 3
０
1
2
3
4
5
6
7
SCLK
Mode ０
Mode ０
FFFFFFFFh
SIO[3:0]
P/N: PM1712
REV. 1.2, NOV. 28, 2013
54
MX25U25635F
Figure 44. Performance Enhance Mode Reset for Fast Read Quad I/O using 4Byte Address Sequence (SPI
Mode)
Mode Bit Reset
for Quad I/O
CS#
Mode 3
Mode 3
0
1
2
3
4
5
6
7
8
9
SCLK
Mode ０
Mode ０
3FFh
SIO0
SIO1
SIO2
Don’t Care
Don’t Care
Don’t Care
SIO3
Figure 45. Performance Enhance Mode Reset for Fast Read Quad I/O using 4Byte Address Sequence (QPI
Mode)
Mode Bit Reset
for Quad I/O
CS#
Mode 3
Mode 3
0
1
2
3
4
5
6
7
8
9
SCLK
Mode ０
Mode ０
SIO[3:0]
FFFFFFFFFFh
P/N: PM1712
REV. 1.2, NOV. 28, 2013
55
MX25U25635F
9-22. Fast Boot
The Fast Boot Feature provides the ability to automatically execute read operation after power on cycle or reset
without any read instruction.
A Fast Boot Register is provided on this device. It can enable the Fast Boot function and also define the number of
delay cycles and start address (where boot code being transferred). Instruction WRFBR (write fast boot register) and
ESFBR (erase fast boot register) can be used for the status configuration or alternation of the Fast Boot Register
bit. RDFBR (read fast boot register) can be used to verify the program state of the Fast Boot Register. The default
number of delay cycles is 13 cycles, and there is a 16bytes boundary address for the start of boot code access.
When CS# starts to go low, data begins to output from default address after the delay cycles (default as 13 cycles).
After CS# returns to go high, the device will go back to standard SPI mode and user can start to input command. In
the fast boot data out process from CS# goes low to CS# goes high, a minimum of one byte must be output.
Once Fast Boot feature has been enabled, the device will automatically start a read operation after power on cycle,
reset command, or hardware reset operation.
The fast Boot feature can support Single I/O and Quad I/O interface. If the QE bit of Status Register is “0”, the data
is output by Single I/O interface. If the QE bit of Status Register is set to “1”, the data is output by Quad I/O interface.
Fast Boot Register (FBR)
Bits
Description
FBSA (FastBoot Start
Address)
Bit Status
16 bytes boundary address for the start of boot
code access.
Default State
Type
Non-
Volatile
31 to 4
FFFFFFF
Non-
Volatile
3
2 to 1
0
x
1
11
1
00: 7 delay cycles
01: 9 delay cycles
10: 11 delay cycles
11: 13 delay cycles
0=FastBoot is enabled.
1=FastBoot is not enabled.
FBSD (FastBoot Start
Delay Cycle)
Non-
Volatile
Non-
Volatile
FBE (FastBoot Enable)
Note: If FBSD = 11, the maximum clock frequency for MX25U25635FZ4I-08G. is 133 MHz. All other products can
only support maximum clock frequency 108MHz when FBSD =11.
If FBSD = 10, the maximum clock frequency is 108 MHz
If FBSD = 01, the maximum clock frequency is 84 MHz
If FBSD = 00, the maximum clock frequency is 70 MHz
P/N: PM1712
REV. 1.2, NOV. 28, 2013
56
MX25U25635F
Figure 46. Fast Boot Sequence (QE=0)
CS#
0
-
n+1
n+13 n+15
n+12 n+14
n+10n+11
Mode 3
Mode 0
-
-
-
-
-
n
n+2
n+4 n+5 n+6
n+8 n+9
n+7
n+3
SCLK
SI
Delay Cycles
Don’t care or High Impedance
Data Out 1
Data Out 2
High Impedance
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
MSB
Note: If FBSD = 11, delay cycles is 13 and n is 12.
If FBSD = 10, delay cycles is 11 and n is 10.
If FBSD = 01, delay cycles is 9 and n is 8.
If FBSD = 00, delay cycles is 7 and n is 6.
Figure 47. Fast Boot Sequence (QE=1)
CS#
-
-
-
-
-
-
-
n
n+1 n+2 n+3 n+5 n+6 n+7 n+8 n+9
0
Mode 3
Mode 0
SCLK
Data
Out 1
Delay Cycles
Data
Data
Data
Out 3
Out 2
Out 4
High Impedance
4
0
0
4
4
4
0
4
0
SIO0
SIO1
SIO2
SIO3
High Impedance
High Impedance
High Impedance
5
6
7
1
5
6
7
1
5
6
1
5
6
7
1
2
3
5
6
7
2
3
2
3
2
3
7
MSB
Note: If FBSD = 11, delay cycles is 13 and n is 12.
If FBSD = 10, delay cycles is 11 and n is 10.
If FBSD = 01, delay cycles is 9 and n is 8.
If FBSD = 00, delay cycles is 7 and n is 6.
P/N: PM1712
REV. 1.2, NOV. 28, 2013
57
MX25U25635F
Figure 48. Read Fast Boot Register (RDFBR) Sequence
CS#
0
1
2
3
4
5
6
7
8
9
10
37 38 39 40 41
Mode 3
Mode 0
SCLK
Command
16h
SI
Data Out 1
Data Out 2
26 25 24 7 6
High-Z
SO
7
6
5
MSB
MSB
Figure 49. Write Fast Boot Register (WRFBR) Sequence
CS#
0
1
2
3
4
5
6
7
8
9
37 38 39
Mode 3
Mode 0
10
SCLK
Command
17h
Fast Boot Register
SI
7
6
26 25 24
5
MSB
High-Z
SO
Figure 50. Erase Fast Boot Register (ESFBR) Sequence
CS#
0
1
2
3
4
5
6
7
Mode 3
Mode 0
SCLK
Command
18h
SI
High-Z
SO
P/N: PM1712
REV. 1.2, NOV. 28, 2013
58
MX25U25635F
9-23. Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for
any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before
sending the Sector Erase (SE). Any address of the sector (see Table 4 memory organization) is a valid address for
Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of the
address byte been latched-in); otherwise, the instruction will be rejected and not executed.
Address bits [Am-A12] (Am is the most significant address) select the sector address.
The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the
4-byte address read mode or to define EAR bit. To enter the 4-byte address mode, please refer to the enter 4-byte
mode (EN4B) Mode section.
The sequence of issuing SE instruction is: CS# goes low→ sending SE instruction code→ 3-byte or 4-byte address
on SI→ CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets 1 during the tSE
timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
sector is protected by BP bits (Block Protect Mode), the Sector Erase (SE) instruction will not be executed on the
sector.
Figure 51. Sector Erase (SE) Sequence (SPI Mode)
CS#
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
24-Bit Address
(Note)
Command
20h
A23 A22
A2 A1 A0
SI
MSB
Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the
address cycles will be increased.
Figure 52. Sector Erase (SE) Sequence (QPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
SCLK
Mode 0
24-Bit Address
(Note)
Command
SIO[3:0]
20h A5 A4 A3 A2 A1 A0
MSB
Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the
address cycles will be increased.
P/N: PM1712
REV. 1.2, NOV. 28, 2013
59
MX25U25635F
9-24. Block Erase (BE32K)
The Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1". The instruction is used for
32K-byte block erase operation. A Write Enable (WREN) instruction be executed to set the Write Enable Latch (WEL)
bit before sending the Block Erase (BE32K). Any address of the block (see Table 4 memory organization) is a valid
address for Block Erase (BE32K) instruction. The CS# must go high exactly at the byte boundary (the least signifi-
cant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed.
Address bits [Am-A15] (Am is the most significant address) select the 32KB block address.
The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the
4-byte address read mode or to define EAR bit. To enter the 4-byte address mode, please refer to the enter 4-byte
mode (EN4B) Mode section.
The sequence of issuing BE32K instruction is: CS# goes low→ sending BE32K instruction code→ 3-byte or 4-byte
address on SI→CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
The self-timed Block Erase Cycle time (tBE32K) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while during the Block Erase cycle is in progress. The WIP sets during the
tBE32K timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If
the Block is protected by BP bits (Block Protect Mode), the Block Erase (BE32K) instruction will not be executed on
the block.
Figure 53. Block Erase 32KB (BE32K) Sequence (SPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
Mode 3
Mode 0
SCLK
Command
52h
24-Bit Address
(Note)
A23 A22
A2 A1 A0
SI
MSB
Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the
address cycles will be increased.
Figure 54. Block Erase 32KB (BE32K) Sequence (QPI Mode)
CS#
Mode 3
Mode 0
0
1
2
3
4
5
6
7
SCLK
24-Bit Address
(Note)
Command
SIO[3:0]
52h A5 A4 A3 A2 A1 A0
MSB
Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the
address cycles will be increased.
P/N: PM1712
REV. 1.2, NOV. 28, 2013
60
MX25U25635F
9-25. Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used
for 64K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable
Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (Please refer to Table 4 memory
organization) is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the
least significant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed.
The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the
4-byte address read mode or to define EAR bit. To enter the 4-byte address mode, please refer to the enter 4-byte
mode (EN4B) Mode section.
The sequence of issuing BE instruction is: CS# goes low→ sending BE instruction code→ 3-byte or 4-byte address
on SI→ CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during the tBE
timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the Block
is protected by BP bits (Block Protect Mode), the Block Erase (BE) instruction will not be executed on the block.
Figure 55. Block Erase (BE) Sequence (SPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
Mode 3
Mode 0
SCLK
Command
D8h
24-Bit Address
(Note)
A23 A22
A2 A1 A0
SI
MSB
Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the
address cycles will be increased.
Figure 56. Block Erase (BE) Sequence (QPI Mode)
CS#
Mode 3
Mode 0
0
1
2
3
4
5
6
7
SCLK
24-Bit Address
(Note)
Command
SIO[3:0]
D8h A5 A4 A3 A2 A1 A0
MSB
Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the
address cycles will be increased.
P/N: PM1712
REV. 1.2, NOV. 28, 2013
61
MX25U25635F
9-26. Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruc-
tion must be executed to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must
go high exactly at the byte boundary, otherwise the instruction will be rejected and not executed.
The sequence of issuing CE instruction is: CS# goes low→sending CE instruction code→CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Chip Erase cycle is in progress. The WIP sets during the tCE tim-
ing, and clears when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared.
When the chip is under "Block protect (BP) Mode". The Chip Erase (CE) instruction will not be executed, if one (or
more) sector is protected by BP3-BP0 bits. It will be only executed when BP3-BP0 all set to "0".
Figure 57. Chip Erase (CE) Sequence (SPI Mode)
CS#
Mode 3
Mode 0
0
1
2
3
4
5
6
7
SCLK
SI
Command
60h or C7h
Figure 58. Chip Erase (CE) Sequence (QPI Mode)
CS#
0
1
Mode 3
Mode 0
SCLK
Command
60h or C7h
SIO[3:0]
P/N: PM1712
REV. 1.2, NOV. 28, 2013
62
MX25U25635F
9-27. Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction
must be executed to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device pro-
grams only the last 256 data bytes sent to the device. The last address byte (the 8 least significant address bits,
A7-A0) should be set to 0 for 256 bytes page program. If A7-A0 are not all zero, transmitted data that exceed page
length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently selected page.
If the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the request page and
previous data will be disregarded. If the data bytes sent to the device has not exceeded 256, the data will be pro-
grammed at the request address of the page. There will be no effort on the other data bytes of the same page.
The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the
4-byte address read mode or to define EAR bit. To enter the 4-byte address mode, please refer to the enter 4-byte
mode (EN4B) Mode section.
The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte or 4-byte address
on SI→ at least 1-byte on data on SI→ CS# goes high.
The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte
boundary( the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be ex-
ecuted.
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Page Program cycle is in progress. The WIP sets during the tPP
timing, and clears when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
page is protected by BP bits (Block Protect Mode), the Page Program (PP) instruction will not be executed.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
P/N: PM1712
REV. 1.2, NOV. 28, 2013
63
MX25U25635F
Figure 59. Page Program (PP) Sequence (SPI Mode)
CS#
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
02h
Data Byte 1
24-Bit Address
(Note)
23 22 21
MSB
3
2
1
0
7
6
5
4
3
2
0
1
SI
MSB
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
Data Byte 2
Data Byte 3
Data Byte 256
7
6
5
4
3
2
0
7
6
5
4
3
2
0
7
6
5
4
3
2
0
1
1
1
SI
MSB
MSB
MSB
Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the
address cycles will be increased.
Figure 60. Page Program (PP) Sequence (QPI Mode)
CS#
Mode 3
Mode 0
0
1
2
SCLK
Command
02h
24-Bit Address
(Note)
H255 L255
SIO[3:0]
H0 L0 H1 L1 H2 L2 H3 L3
Data Byte Data Byte Data Byte Data Byte
A5 A4 A3 A2 A1 A0
......
Data Byte
256
Data In
1
2
3
4
Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the
address cycles will be increased.
P/N: PM1712
REV. 1.2, NOV. 28, 2013
64
MX25U25635F
9-28. 4 x I/O Page Program (4PP)
The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN) in-
struction must be executed to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1" be-
fore sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1, SIO2, and
SIO3 as address and data input, which can improve programmer performance and the effectiveness of application.
The other function descriptions are as same as standard page program.
The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the
4-byte address read mode or to define EAR bit. To enter the 4-byte address mode, please refer to the enter 4-byte
mode (EN4B) Mode section.
The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte or 4-byte ad-
dress on SIO[3:0]→ at least 1-byte on data on SIO[3:0]→CS# goes high.
If the page is protected by BP bits (Block Protect Mode), the Quad Page Program (4PP) instruction will not be
executed.
Figure 61. 4 x I/O Page Program (4PP) Sequence (SPI Mode only)
CS#
10 11 12 13 14 15 16 17 18 19 20 21
Data Data Data Data
0
1
2
3
4
5
6
7
8
9
Mode 3
Mode 0
SCLK
Command
38h
6 Address cycle
Byte 1 Byte 2 Byte 3 Byte 4
16 12
8
9
4
0
20
4
0
4
0
4
0
4
0
SIO0
SIO1
SIO2
SIO3
21 17 13
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
22 18 14 10
23 19 15 11
Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the
address cycles will be increased.
P/N: PM1712
REV. 1.2, NOV. 28, 2013
65
MX25U25635F
9-29. Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device to minimum power consumption (the standby cur-
rent is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction
to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are
ignored. When CS# goes high, it's only in deep power-down mode not standby mode. It's different from Standby
mode.
The sequence of issuing DP instruction is: CS# goes low→sending DP instruction code→CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP)
and Read Electronic Signature (RES) instruction and softreset command. (those instructions allow the ID being
reading out). When Power-down, or software reset command the deep power-down mode automatically stops, and
when power-up, the device automatically is in standby mode. For DP instruction the CS# must go high exactly at the
byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed.
As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode.
Figure 62. Deep Power-down (DP) Sequence (SPI Mode)
CS#
t
DP
0
1
2
3
4
5
6
7
Mode 3
Mode 0
SCLK
SI
Command
B9h
Stand-by Mode
Deep Power-down Mode
Figure 63. Deep Power-down (DP) Sequence (QPI Mode)
CS#
t
DP
Mode 3
Mode 0
0
1
SCLK
Command
SIO[3:0]
B9h
Stand-by Mode
Deep Power-down Mode
P/N: PM1712
REV. 1.2, NOV. 28, 2013
66
MX25U25635F
9-30. Enter Secured OTP (ENSO)
The ENSO instruction is for entering the additional 4K-bit secured OTP mode. While device is in 4K-bit secured
OTPmode, main array access is not available. The additional 4K-bit secured OTP is independent from main array
and may be used to store unique serial number for system identifier. After entering the Secured OTP mode, follow
standard read or program procedure to read out the data or update data. The Secured OTP data cannot be updated
again once it is lock-down.
The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP
mode→ CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
Please note that after issuing ENSO command user can only access secure OTP region with standard read or pro-
gram procedure. Furthermore, once security OTP is lock down, only read related commands are valid.
9-31. Exit Secured OTP (EXSO)
The EXSO instruction is for exiting the additional 4K-bit secured OTP mode.
The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP
mode→ CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
9-32. Read Security Register (RDSCUR)
The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read
at any time (even in program/erase/write status register/write security register condition) and continuously.
The sequence of issuing RDSCUR instruction is : CS# goes low→sending RDSCUR instruction→Security Register
data out on SO→ CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
9-33. Write Security Register (WRSCUR)
The WRSCUR instruction is for changing the values of Security Register Bits. The WREN (Write Enable) instruction
is required before issuing WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO
bit) for customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area
cannot be updated any more.
The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
P/N: PM1712
REV. 1.2, NOV. 28, 2013
67
MX25U25635F
Security Register
The definition of the Security Register bits is as below:
Erase Fail bit. The Erase Fail bit is a status flag, which shows the status of last Erase operation. It will be set to
"1", if the erase operation fails or the erase region is protected. It will be set to "0", if the last operation is success.
Please note that it will not interrupt or stop any operation in the flash memory.
Program Fail bit. The Program Fail bit is a status flag, which shows the status of last Program operation. It will be
set to "1", if the program operation fails or the program region is protected. It will be set to "0", if the last operation is
success. Please note that it will not interrupt or stop any operation in the flash memory.
Erase Suspend bit. Erase Suspend Bit (ESB) indicates the status of Erase Suspend operation. Users may use
ESB to identify the state of flash memory. After the flash memory is suspended by Erase Suspend command, ESB is
set to "1". ESB is cleared to "0" after erase operation resumes.
Program Suspend bit. Program Suspend Bit (PSB) indicates the status of Program Suspend operation. Users may
use PSB to identify the state of flash memory. After the flash memory is suspended by Program Suspend command,
PSB is set to "1". PSB is cleared to "0" after program operation resumes.
Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory or not. When it is
"0", it indicates non-factory lock; "1" indicates factory-lock.
Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for cus-
tomer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 4K-bit Secured OTP
area cannot be updated any more. While it is in 4K-bit secured OTP mode, main array access is not allowed.
Table 8. Security Register Definition
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ESB
(Erase
PSB
(Program
LDSO
(indicate if
Reserved
Secured OTP
indicator bit
E_FAIL
P_FAIL
Reserved
Suspend bit) Suspend bit) lock-down)
0=normal
Program
succeed
1=indicate
Program
failed
0 = not lock-
0=normal
Erase
succeed
1=indicate
Erase failed
(default=0)
0=Erase
is not
suspended suspended
1= Erase 1= Program
suspended suspended
0=Program
is not
down
1 = lock-down
(cannot
program/
erase
OTP)
Non-volatile
bit
0 = non-
factory
lock
1 = factory
lock
-
-
-
-
(default=0)
(default=0)
(default=0)
Non-volatile
bit (OTP)
Volatile bit
Volatile bit
Volatile bit
Volatile bit
(OTP)
9-34. Block Lock (BP) protection
In Block Lock (BP) protection mode,
Array is protected by BP3~BP0 and BP bits are protected by “SRWD=1 and WP#=0”, where SRWD is bit 7 of sta-
tus register that can be set by WRSR command. The protected area definition is shown as Table 2 Protected Area
Sizes, the protected areas are more flexible which may protect various area by setting value of BP0-BP3 bits.
P/N: PM1712
REV. 1.2, NOV. 28, 2013
68
MX25U25635F
9-35. Program/Erase Suspend/Resume
The device allow the interruption of Sector-Erase, Block-Erase or Page-Program operations and conduct other op-
erations.
After issue suspend command, the system can determine if the device has entered the Erase-Suspended mode
through Bit2 (PSB) and Bit3 (ESB) of security register. (please refer to "Table 8. Security Register Definition")
MX25U25635F
Suspend to suspend ready timing
20us
0.85us (Note 1)
100us
The minimum timing of Suspend Resume to another suspend
The typical timing of Program Suspend Resume to another suspend
The typical timing of Erase Suspend Resume to another suspend
200us
Note 1: The flash memory can accept another suspend command just after 0.85us from suspend resume. However,
if the timing is less than 100us from Program Suspend Resume or 200us from Erase Suspend Resume, the
content of flash memory might not be changed before the suspend command has been issued.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
9-36. Erase Suspend
Erase suspend allow the interruption of all erase operations. After the device has entered Erase-Suspended mode,
the system can read any sector(s) or Block(s) except those being erased by the suspended erase operation.
Reading the sector or Block being erase suspended is invalid.
After erase suspend, WEL bit will be clear, following commands can be accepted. (including: 03h, 0Bh, 3Bh, 6Bh,
BBh, EAh, EBh, 5Ah, C0h, 06h, 04h, 2Bh, 9Fh, AFh, 05h, ABh, 90h, 02h, 38h, B1h, C1h, B0h, 30h, 66h, 99h, 00h,
35h, F5h, 15h, 16h, 13h, 0Ch, BCh, 3Ch, ECh, 6Ch, 12h, 3Eh)
If the system issues an Erase Suspend command after the sector erase operation has already begun, the device will
not enter Erase-Suspended mode until 20us time has elapsed.
Erase Suspend Bit (ESB) indicates the status of Erase Suspend operation. Users may use ESB to identify the
state of flash memory. After the flash memory is suspended by Erase Suspend command, ESB is set to "1". ESB is
cleared to "0" after erase operation resumes.
9-37. Program Suspend
Program suspend allows the interruption of all program operations. After the device has entered Program-
Suspended mode, the system can read any sector(s) or Block(s) except those being programmed by the suspended
program operation. Reading the sector or Block being program suspended is invalid.
After program suspend, WEL bit will be cleared, only read related, resume and reset command can be accepted.
(including: 03h, 0Bh, 3Bh, 6Bh, BBh, EAh, EBh, 5Ah, C0h, 06h, 04h, 2Bh, 9Fh, AFh, 05h, ABh, 90h, B1h, C1h, B0h,
30h, 66h, 99h, 00h, 35h, F5h, 15h, 16h, 13h, 0Ch, BCh, 3Ch, ECh, 6Ch)
Program Suspend Bit (PSB) indicates the status of Program Suspend operation. Users may use PSB to identify the
state of flash memory. After the flash memory is suspended by Program Suspend command, PSB is set to "1". PSB
is cleared to "0" after program operation resumes.
P/N: PM1712
REV. 1.2, NOV. 28, 2013
69
MX25U25635F
Figure 64. Suspend to Read Latency
Program latency : 20us
Erase latency:20us
Suspend Command
Read Command
CS#
[B0]
Figure 65. Resume to Read Latency
TSE/TBE/TPP
Resume Command
[30]
Read Command
CS#
Figure 66. Resume to Suspend Latency
Program Suspend Resume latency: 100us
Erase Suspend Resume latency: 200us
Suspend
Command
[B0]
Resume Command
[30]
CS#
P/N: PM1712
REV. 1.2, NOV. 28, 2013
70
MX25U25635F
9-38. Write-Resume
The Write operation is being resumed when Write-Resume instruction issued. ESB or PSB (suspend status bit) in
Status register will be changed back to “0”
The operation of Write-Resume is as follows: CS# drives low → send write resume command cycle (30H) → drive
CS# high. By polling Busy Bit in status register, the internal write operation status could be checked to be completed
or not. The user may also wait the time lag of TSE, TBE, TPP for Sector-erase, Block-erase or Page-programming.
WREN (command "06" is not required to issue before resume. Resume to another suspend operation requires
latency time of 100us(from Program Suspend Resume)/200us(from Erase Suspend Resume).
Please note that, if "performance enhance mode" is executed during suspend operation, the device can not be
resume. To restart the write command, disable the "performance enhance mode" is required. After the "performance
enhance mode" is disable, the write-resume command is effective.
9-39. No Operation (NOP)
The “No Operation” command is only able to terminate the Reset Enable (RSTEN) command and will not affect any
other command.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
9-40. Software Reset (Reset-Enable (RSTEN) and Reset (RST))
The Software Reset operation combines two instructions: Reset-Enable (RSTEN) command and Reset (RST)
command. It returns the device to standby mode. All the volatile bits and settings will be cleared then, which makes
the device return to the default status as power on.
To execute Reset command (RST), the Reset-Enable (RSTEN) command must be executed first to perform the
Reset operation. If there is any other command to interrupt after the Reset-Enable command, the Reset-Enable will
be invalid.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
If the Reset command is executed during program or erase operation, the operation will be disabled, the data under
processing could be damaged or lost.
The reset time is different depending on the last operation. For details, please refer to "Table 13. Reset Timing-
(Other Operation)" for tREADY2.
P/N: PM1712
REV. 1.2, NOV. 28, 2013
71
MX25U25635F
Figure 67. Software Reset Recovery
Stand-by Mode
66
99
CS#
tREADY2
Mode
Note: Refer to "Table 13. Reset Timing-(Other Operation)" for tREADY2.
Figure 68. Reset Sequence (SPI mode)
tSHSL
CS#
Mode 3
Mode 0
Mode 3
Mode 0
SCLK
SIO0
Command
66h
Command
99h
Figure 69. Reset Sequence (QPI mode)
tSHSL
CS#
MODE 3
MODE 3
MODE 0
MODE 3
MODE 0
SCLK
MODE 0
Command
Command
SIO[3:0]
66h
99h
P/N: PM1712
REV. 1.2, NOV. 28, 2013
72
MX25U25635F
9-41. Read SFDP Mode (RDSFDP)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional
and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables
can be interrogated by host system software to enable adjustments needed to accommodate divergent features
from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on
CFI.
The sequence of issuing RDSFDP instruction is CS# goes low→send RDSFDP instruction (5Ah)→send 3 address
bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP operation can use CS#
to high at any time during data out.
SFDP is a JEDEC Standard, JESD216.
Figure 70. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
SCLK
Command
5Ah
24 BIT ADDRESS
SI
23 22 21
3
2
1
0
High-Z
SO
CS#
47
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
SCLK
Dummy Cycle
7
6
5
4
3
2
0
1
SI
DATA OUT 2
DATA OUT 1
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
SO
MSB
MSB
MSB
P/N: PM1712
REV. 1.2, NOV. 28, 2013
73
MX25U25635F
Table 9. Signature and Parameter Identification Data Values
Description Comment
Add (h) DW Add
Data
(h/b) note1
Data
(h)
(Byte)
(Bit)
00h
07:00
53h
46h
44h
50h
00h
01h
53h
46h
44h
50h
00h
01h
01h
02h
03h
04h
05h
15:08
23:16
31:24
07:00
15:08
SFDP Signature
Fixed: 50444653h
SFDP Minor Revision Number
SFDP Major Revision Number
Start from 00h
Start from 01h
This number is 0-based. Therefore,
0 indicates 1 parameter header.
Number of Parameter Headers
Unused
06h
07h
08h
09h
0Ah
0Bh
23:16
31:24
07:00
15:08
23:16
31:24
01h
FFh
00h
00h
01h
09h
01h
FFh
00h
00h
01h
09h
00h: it indicates a JEDEC specified
header.
ID number (JEDEC)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length
(in double word)
Start from 00h
Start from 01h
How many DWORDs in the
Parameter table
0Ch
0Dh
0Eh
07:00
15:08
23:16
30h
00h
00h
30h
00h
00h
First address of JEDEC Flash
Parameter table
Parameter Table Pointer (PTP)
Unused
0Fh
10h
11h
12h
13h
31:24
07:00
15:08
23:16
31:24
FFh
C2h
00h
01h
04h
FFh
C2h
00h
01h
04h
ID number
(Macronix manufacturer ID)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
it indicates Macronix manufacturer
ID
Start from 00h
Start from 01h
Parameter Table Length
(in double word)
How many DWORDs in the
Parameter table
14h
15h
16h
07:00
15:08
23:16
60h
00h
00h
60h
00h
00h
First address of Macronix Flash
Parameter table
Parameter Table Pointer (PTP)
Unused
17h
31:24
FFh
FFh
P/N: PM1712
REV. 1.2, NOV. 28, 2013
74
MX25U25635F
Table 10. Parameter Table (0): JEDEC Flash Parameter Tables
Add (h) DW Add
Data
(h/b) note1
Data
(h)
Description
Comment
(Byte)
(Bit)
00: Reserved, 01: 4KB erase,
10: Reserved,
11: not support 4KB erase
Block/Sector Erase sizes
Write Granularity
01:00
01b
1b
0: 1Byte, 1: 64Byte or larger
02
03
Write Enable Instruction Required 0: not required
for Writing to Volatile Status
1: required 00h to be written to the
0b
Registers
status register
30h
E5h
0: use 50h opcode,
1: use 06h opcode
Write Enable Opcode Select for
Writing to Volatile Status Registers
Note: If target flash status register is
nonvolatile, then bits 3 and 4 must
be set to 00b.
04
0b
Contains 111b and can never be
changed
Unused
07:05
111b
4KB Erase Opcode
31h
32h
33h
15:08
16
20h
1b
20h
F3h
FFh
(1-1-2) Fast Read(Note2)
0=not support 1=support
Address Bytes Number used in
addressing flash array
00: 3Byte only, 01: 3 or 4Byte,
10: 4Byte only, 11: Reserved
18:17
19
01b
0b
Double Transfer Rate (DTR)
Clocking
0=not support 1=support
(1-2-2) Fast Read
(1-4-4) Fast Read
(1-1-4) Fast Read
Unused
0=not support 1=support
0=not support 1=support
0=not support 1=support
20
21
1b
1b
22
1b
23
1b
Unused
31:24
FFh
Flash Memory Density
37h:34h 31:00
0FFF FFFFh
(1-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
04:00
38h
0 0100b
states (Note3)
Clocks) not support
44h
EBh
08h
6Bh
(1-4-4) Fast Read Number of
Mode Bits (Note4)
000b: Mode Bits not support
07:05
010b
EBh
(1-4-4) Fast Read Opcode
39h
3Ah
3Bh
15:08
20:16
(1-1-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
0 1000b
states
Clocks) not support
(1-1-4) Fast Read Number of
Mode Bits
000b: Mode Bits not support
23:21
31:24
000b
6Bh
(1-1-4) Fast Read Opcode
P/N: PM1712
REV. 1.2, NOV. 28, 2013
75
MX25U25635F
Add (h) DW Add
Data
(h/b) note1
Data
(h)
Description
Comment
(Byte)
(Bit)
(1-1-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy
04:00
0 1000b
states
Clocks) not support
3Ch
08h
3Bh
04h
BBh
(1-1-2) Fast Read Number of
Mode Bits
000b: Mode Bits not support
07:05
15:08
20:16
000b
3Bh
(1-1-2) Fast Read Opcode
3Dh
3Eh
3Fh
(1-2-2) Fast Read Number of Wait 0 0000b: Wait states(Dummy
0 0100b
states
Clocks) not support
(1-2-2) Fast Read Number of
Mode Bits
000b: Mode Bits not support
23:21
000b
(1-2-2) Fast Read Opcode
(2-2-2) Fast Read
Unused
31:24
00
BBh
0b
0=not support 1=support
0=not support 1=support
03:01
04
111b
1b
40h
FEh
(4-4-4) Fast Read
Unused
07:05
111b
FFh
FFh
Unused
43h : 41h 31:08
45h:44h 15:00
FFh
FFh
Unused
(2-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy
20:16
46h
0 0000b
000b
states
Clocks) not support
00h
(2-2-2) Fast Read Number of
Mode Bits
000b: Mode Bits not support
23:21
(2-2-2) Fast Read Opcode
Unused
47h
31:24
FFh
FFh
FFh
FFh
49h:48h 15:00
(4-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
20:16
4Ah
0 0100b
states
Clocks) not support
44h
(4-4-4) Fast Read Number of
Mode Bits
000b: Mode Bits not support
23:21
010b
EBh
0Ch
20h
0Fh
52h
10h
D8h
00h
FFh
(4-4-4) Fast Read Opcode
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
53h
31:24
07:00
15:08
23:16
31:24
07:00
15:08
23:16
31:24
EBh
0Ch
20h
0Fh
52h
10h
D8h
00h
FFh
Sector/block size = 2^N bytes (Note5)
0x00b: this sector type don't exist
Sector Type 1 Size
Sector Type 1 erase Opcode
Sector Type 2 Size
Sector/block size = 2^N bytes
0x00b: this sector type don't exist
Sector Type 2 erase Opcode
Sector Type 3 Size
Sector/block size = 2^N bytes
0x00b: this sector type don't exist
Sector Type 3 erase Opcode
Sector Type 4 Size
Sector/block size = 2^N bytes
0x00b: this sector type don't exist
Sector Type 4 erase Opcode
P/N: PM1712
REV. 1.2, NOV. 28, 2013
76
MX25U25635F
Table 11. Parameter Table (1): Macronix Flash Parameter Tables
Add (h) DW Add
Data
(h/b) note1
Data
(h)
Description
Comment
2000h=2.000V
2700h=2.700V
3600h=3.600V
(Byte)
(Bit)
07:00
15:08
00h
20h
00h
20h
Vcc Supply Maximum Voltage
61h:60h
1650h=1.650V
2250h=2.250V
2350h=2.350V
2700h=2.700V
23:16
31:24
50h
16h
50h
16h
Vcc Supply Minimum Voltage
H/W Reset# pin
63h:62h
0=not support 1=support
00
1b
H/W Hold# pin
0=not support 1=support
0=not support 1=support
0=not support 1=support
01
02
03
0b
1b
1b
Deep Power Down Mode
S/W Reset
Should be issue Reset Enable (66h)
before Reset Opcode
1001 1001b
(99h)
65h:64h
F99Dh
S/W Reset Opcode
11:04
Program Suspend/Resume
Erase Suspend/Resume
Unused
0=not support 1=support
0=not support 1=support
12
13
1b
1b
14
1b
Wrap-Around Read mode
Wrap-Around Read mode Opcode
0=not support 1=support
15
1b
66h
67h
23:16
C0h
C0h
64h
08h:support 8B wrap-around read
16h:8B&16B
32h:8B&16B&32B
Wrap-Around Read data length
31:24
64h
64h:8B&16B&32B&64B
Individual block lock
0=not support 1=support
00
01
0b
1b
Individual block lock bit
(Volatile/Nonvolatile)
0=Volatile 1=Nonvolatile
1111 1111b
(FFh)
Individual block lock Opcode
09:02
10
Individual block lock Volatile
protect bit default protect status
0=protect 1=unprotect
1b
CFFEh
6Bh:68h
Secured OTP
Read Lock
Permanent Lock
Unused
0=not support 1=support
0=not support 1=support
0=not support 1=support
11
12
1b
0b
13
0b
15:14
31:16
11b
FFh
FFh
Unused
FFh
FFh
Unused
6Fh:6Ch 31:00
P/N: PM1712
REV. 1.2, NOV. 28, 2013
77
MX25U25635F
Note 1: h/b is hexadecimal or binary.
Note 2: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x),
address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1), (2-2-2),
and (4-4-4)
Note 3: Wait States is required dummy clock cycles after the address bits or optional mode bits.
Note 4: Mode Bits is optional control bits that follow the address bits. These bits are driven by the system controller
if they are specified. (eg,read performance enhance toggling bits)
Note 5: 4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h
Note 6: All unused and undefined area data is blank FFh.
P/N: PM1712
REV. 1.2, NOV. 28, 2013
78
MX25U25635F
10. RESET
Driving the RESET# pin low for a period of tRLRH or longer will reset the device. After reset cycle, the device is at
the following states:
- Standby mode
- All the volatile bits such as WEL/WIP/SRAM lock bit will return to the default status as power on.
- 3-byte address mode
If the device is under programming or erasing, driving the RESET# pin low will also terminate the operation and data
could be lost. During the resetting cycle, the SO data becomes high impedance and the current will be reduced to
minimum.
Figure 71. RESET Timing
CS#
tRHSL
SCLK
tRH
tRS
RESET#
tRLRH
tREADY1 / tREADY2
Table 12. Reset Timing-(Power On)
Symbol Parameter
tRHSL Reset# high before CS# low
Min.
10
Typ.
Max.
Unit
us
tRS
tRH
Reset# setup time
Reset# hold time
15
15
ns
ns
tRLRH Reset# low pulse width
tREADY1 Reset Recovery time
10
35
us
us
Table 13. Reset Timing-(Other Operation)
Symbol Parameter
tRHSL Reset# high before CS# low
Min.
10
Typ.
Max.
Unit
us
tRS
tRH
Reset# setup time
Reset# hold time
15
15
ns
ns
tRLRH Reset# low pulse width
10
us
Reset Recovery time (During instruction decoding)
Reset Recovery time (for read operation)
40
40
us
us
Reset Recovery time (for program operation)
tREADY2 Reset Recovery time(for SE operation)
Reset Recovery time (for BE64K/BE32KB operation)
Reset Recovery time (for Chip Erase operation)
Reset Recovery time (for WRSR operation)
310
12
25
100
40
us
ms
ms
ms
ms
P/N: PM1712
REV. 1.2, NOV. 28, 2013
79
MX25U25635F
11. POWER-ON STATE
The device is at below states when power-up:
- Standby mode (please note it is not deep power-down mode)
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage unless the VCC achieves below correct
level:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change
during power up state. When VCC is lower than VWI (POR threshold voltage value), the internal logic is reset and
the flash device has no response to any command.
For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not
guaranteed. The write, erase, and program command should be sent after the below time delay:
- tVSL after VCC reached VCC minimum level
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.
Please refer to the "power-up timing".
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommend-
ed. (generally around 0.1uF)
- At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response
to any command. The data corruption might occur during the stage while a write, program, erase cycle is in
progress.
P/N: PM1712
REV. 1.2, NOV. 28, 2013
80
MX25U25635F
12. ELECTRICAL SPECIFICATIONS
Table 14. ABSOLUTE MAXIMUM RATINGS
RATING
VALUE
Ambient Operating Temperature
Storage Temperature
Applied Input Voltage
Applied Output Voltage
VCC to Ground Potential
Industrial grade
-40°C to 85°C
-65°C to 150°C
-0.5V to VCC+0.5V
-0.5V to VCC+0.5V
-0.5V to 2.5V
NOTICE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage
to the device. This is stress rating only and functional operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended period may affect reliability.
2. Specifications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot to VCC+1.0V or -1.0V for period up to 20ns.
Figure 73. Maximum Positive Overshoot Waveform
Figure 72. Maximum Negative Overshoot Waveform
20ns
0V
VCC+1.0V
-1.0V
2.0V
20ns
Table 15. CAPACITANCE TA = 25°C, f = 1.0 MHz
Symbol Parameter
Min.
Typ.
Max.
Unit
pF
Conditions
VIN = 0V
CIN
Input Capacitance
8
8
COUT Output Capacitance
pF
VOUT = 0V
P/N: PM1712
REV. 1.2, NOV. 28, 2013
81
MX25U25635F
Figure 74. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL
Input timing reference level
Output timing reference level
0.8VCC
0.2VCC
0.7VCC
0.3VCC
AC
Measurement
Level
0.5VCC
Note: Input pulse rise and fall time are <5ns
Figure 75. OUTPUT LOADING
25K ohm
+1.8V
DEVICE UNDER
TEST
CL
25K ohm
CL=30pF Including jig capacitance
P/N: PM1712
REV. 1.2, NOV. 28, 2013
82
MX25U25635F
Table 16. DC CHARACTERISTICS (Temperature = -40 C to 85 C, VCC = 1.65V ~ 2.0V)
°
°
Symbol Parameter
Notes
Min.
Typ.
Max.
Units Test Conditions
VCC = VCC Max,
uA
ILI
Input Load Current
Output Leakage Current
1
±2
±2
VIN = VCC or GND
VCC = VCC Max,
uA
ILO
1
1
VOUT = VCC or GND
VIN = VCC or GND,
CS# = VCC
ISB1 VCC Standby Current
20
100
20
uA
Deep Power-down
Current
VIN = VCC or GND,
CS# = VCC
ISB2
1.5
uA
f=133MHz, (4 x I/O read)
SCLK=0.1VCC/0.9VCC,
mA SO=Open
25
(for MX25U25635FZ4I-08G
only)
f=108Hz, (4 x I/O read)
mA SCLK=0.1VCC/0.9VCC,
SO=Open
ICC1 VCC Read
1
1
20
15
f=84MHz,
mA SCLK=0.1VCC/0.9VCC,
SO=Open
VCC Program Current
Program in Progress,
CS# = VCC
ICC2
(PP)
20
10
25
20
mA
VCC Write Status
ICC3
Program status register in
mA
Register (WRSR) Current
progress, CS#=VCC
VCC Sector/Block (32K,
ICC4 64K) Erase Current
(SE/BE/BE32K)
Erase in Progress,
CS#=VCC
1
1
20
20
25
25
mA
VCC Chip Erase Current
Erase in Progress,
CS#=VCC
ICC5
(CE)
mA
VIL
VIH
VOL
Input Low Voltage
Input High Voltage
Output Low Voltage
-0.5
0.3VCC
VCC+0.4
0.2
V
V
0.7VCC
V
V
IOL = 100uA
IOH = -100uA
VOH Output High Voltage
VCC-0.2
Notes :
1. Typical values at VCC = 1.8V, T = 25 C. These currents are valid for all product versions (package and speeds).
°
2. Typical value is calculated by simulation.
P/N: PM1712
REV. 1.2, NOV. 28, 2013
83
MX25U25635F
Table 17. AC CHARACTERISTICS (Temperature = -40 C to 85 C, VCC = 1.65V ~ 2.0V)
°
°
Symbol Alt. Parameter
Clock Frequency for the following instructions:
Min.
Typ.
Max. Unit
fSCLK
fC FAST_READ, RDSFDP, PP, SE, BE, CE, DP, RES, RDP,
WREN, WRDI, RDID, RDSR, WRSR
D.C.
108 (6) MHz
fRSCLK
fTSCLK
fR Clock Frequency for READ instructions
fT Clock Frequency for 2READ instructions
fQ Clock Frequency for 4READ instructions (5)
55
MHz
84 (6) MHz
84 (6) MHz
Others (fSCLK)
Normal Read (fRSCLK)
4.5/3.3 (7)
ns
ns
ns
tCH(1)
tCL(1)
tCLH Clock High Time
7
Others (fSCLK)
Normal Read (fRSCLK)
4.5/3.3 (7)
tCLL Clock Low Time
7
0.1
0.1
5
ns
tCLCH(2)
tCHCL(2)
Clock Rise Time (peak to peak)
Clock Fall Time (peak to peak)
V/ns
V/ns
ns
tSLCH tCSS CS# Active Setup Time (relative to SCLK)
tCHSL CS# Not Active Hold Time (relative to SCLK)
tDVCH tDSU Data In Setup Time
7
ns
2
ns
tCHDX
tCHSH
tSHCH
tDH Data In Hold Time
5
ns
CS# Active Hold Time (relative to SCLK)
CS# Not Active Setup Time (relative to SCLK)
Read
5
ns
5
ns
7
ns
tSHSL tCSH CS# Deselect Time
Write/Erase/Program
30
ns
tSHQZ(2) tDIS Output Disable Time
8
8
6
ns
ns
ns
ns
ns
ns
us
Loading: 30pF
Loading: 15pF
Clock Low to Output Valid
tCLQV
tV
Loading: 30pF/15pF
tHO Output Hold Time
Write Protect Setup Time
Write Protect Hold Time
tCLQX
tWHSL(3)
tSHWL(3)
tDP(2)
1
20
100
CS# High to Deep Power-down Mode
CS# High to Standby Mode without Electronic Signature
Read
CS# High to Standby Mode with Electronic Signature Read
Write Status/Configuration Register Cycle Time
Write Extended Address Register
Byte-Program
10
10
tRES1(2)
us
tRES2(2)
tW
10
40
us
ms
ns
tWREAR
tBP
40
12
30
3
us
tPP
Page Program Cycle Time
1
ms
ms
ms
ms
s
tSE
Sector Erase Cycle Time
45
200
1000
2000
320
tBE32
tBE
Block Erase (32KB) Cycle Time
Block Erase (64KB) Cycle Time
Chip Erase Cycle Time
200
400
200
tCE
P/N: PM1712
REV. 1.2, NOV. 28, 2013
84
MX25U25635F
Notes:
1. tCH + tCL must be greater than or equal to 1/ Frequency.
2. Typical values given for TA=25 C. Not 100% tested.
°
3. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
4. Test condition is shown as Figure 74 and Figure 75.
5. While programming consecutive bytes, Page Program instruction provides optimized timings by selecting to pro-
gram the whole 256 bytes or only a few bytes between 1~256 bytes.
6. By default dummy cycle value. Please refer to the "Table 1. Read performance Comparison". Please note that
only MX25U25635FZ4I-08G support 10 dummy cycles, which provide maximum clock rate=133MHz.
7. Please note that only MX25U25635FZ4I-08G supports tCH/tCL=3.3 ns. All other products can only support 4.5ns.
P/N: PM1712
REV. 1.2, NOV. 28, 2013
85
MX25U25635F
13. OPERATING CONDITIONS
At Device Power-Up and Power-Down
AC timing illustrated in Figure 76 and Figure 77 are for the supply voltages and the control signals at device power-
up and power-down. If the timing in the figures is ignored, the device will not operate correctly.
During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be
selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.
Figure 76. AC Timing at Device Power-Up
VCC(min)
VCC
GND
tVR
tSHSL
CS#
tSHCH
tSLCH
tCHSL
tCHSH
SCLK
tDVCH
tCHCL
tCHDX
tCLCH
MSB IN
LSB IN
SI
High Impedance
SO
Symbol
Parameter
Notes
Min.
Max.
Unit
tVR
VCC Rise Time
1
20
500000
us/V
Notes :
1. Sampled, not 100% tested.
2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to
Table 17 AC CHARACTERISTICS.
P/N: PM1712
REV. 1.2, NOV. 28, 2013
86
MX25U25635F
Figure 77. Power-Down Sequence
During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.
VCC
CS#
SCLK
Figure 78. Power-up Timing
V
CC
V
(max)
CC
Chip Selection is Not Allowed
V
(min)
CC
Device is fully accessible
tVSL
V
WI
time
Note: VCC (max.) is 2.0V and VCC (min.) is 1.65V.
Table 18. Power-Up Timing and VWI Threshold
Symbol Parameter
Min.
1500
1
Max.
Unit
us
V
tVSL(1)
VWI(1)
VCC(min) to CS# low (VCC Rise Time)
Command Inhibit Voltage
1.4
Note: 1. These parameters are characterized only.
P/N: PM1712
REV. 1.2, NOV. 28, 2013
87
MX25U25635F
Figure 79. Power Up/Down and Voltage Drop
For Power-down to Power-up operation, the VCC of flash device must below VPWD for at least tPWD timing. Please
check the table below for more detail.
VCC
VCC (max.)
Chip Select is not allowed
VCC (min.)
tVSL
Full Device
Access
Allowed
(max.)
V
PWD
tPWD
Time
Table 19. Power-Up/Down and Voltage Drop
Symbol Parameter
Min.
Max.
Unit
VCC voltage needed to below VPWD for ensuring initialization
will occur
VPWD
0.9
V
tPWD
tVSL
tVR
The minimum duration for ensuring initialization will occur
VCC(min.) to device operation
VCC Rise Time
300
1.5
us
ms
us/V
V
20
500000
2.0
VCC
VCCPower Supply
1.65
13-1. INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status
Register contains 00h (all Status Register bits are 0).
P/N: PM1712
REV. 1.2, NOV. 28, 2013
88
MX25U25635F
14. ERASE AND PROGRAMMING PERFORMANCE
Parameter
Min.
Typ. (1)
Max. (2)
40
Unit
ms
Write Status Register Cycle Time
Sector Erase Cycle Time (4KB)
Block Erase Cycle Time (32KB)
Block Erase Cycle Time (64KB)
Chip Erase Cycle Time
45
200
200
1000
2000
320
30
ms
ms
400
ms
200
s
Byte Program Time (via page program command)
Page Program Time
12 (5)
1 (5)
us
3
ms
Erase/Program Cycle
100,000
cycles
Note:
1. Typical erase assumes the following conditions: 25 C, 1.8V, and all zero pattern.
°
2. Under worst conditions of 85 C and 1.65V.
°
3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming com-
mand.
4. The maximum chip programming time is evaluated under the worst conditions of 0 C, VCC=1.8V, and 100K cy-
°
cle with 90% confidence level.
5. Typical program assumes the following conditions: 25 C, 1.8V, and checkerboard pattern.
°
15. DATA RETENTION
Parameter
Condition
Min.
Max.
Unit
Data retention
55˚C
20
years
16. LATCH-UP CHARACTERISTICS
Min.
Max.
Input Voltage with respect to GND on all power pins, SI, CS#
Input Voltage with respect to GND on SO
Current
-1.0V
-1.0V
2 VCCmax
VCC + 1.0V
+100mA
-100mA
Includes all pins except VCC. Test conditions: VCC = 1.8V, one pin at a time.
P/N: PM1712
REV. 1.2, NOV. 28, 2013
89
MX25U25635F
17. ORDERING INFORMATION
PART NO.
MX25U25635FMI-10G
MX25U25635FZ2I-10G
MX25U25635FZ4I-10G
MX25U25635FZ4I-08G
CLOCK (MHz) TEMPERATURE
PACKAGE
Remark
108
108
108
133
-40 C~85 C
16-SOP (300mil)
8-WSON (8x6mm)
°
°
-40 C~85 C
°
°
8-WSON
(8x6mm 3.4 x 4.3 EP)
-40 C~85 C
°
°
8-WSON
(8x6mm 3.4 x 4.3 EP)
-40 C~85 C
°
°
P/N: PM1712
REV. 1.2, NOV. 28, 2013
90
MX25U25635F
18. PART NAME DESCRIPTION
MX 25
U
25635F Z2
I
10 G
OPTION:
G: RoHS Compliant and Halogen-free
SPEED:
10: 108MHz
08: 133MHz
TEMPERATURE RANGE:
I: Industrial (-40°C to 85°C)
PACKAGE:
M: 16-SOP(300mil)
Z2: 8-WSON
Z4：8-WSON (3.4 x 4.3 EP)
DENSITY & MODE:
25635F: 256Mb
TYPE:
U: 1.8V
DEVICE:
25: Serial Flash
P/N: PM1712
REV. 1.2, NOV. 28, 2013
91
MX25U25635F
19. PACKAGE INFORMATION
P/N: PM1712
REV. 1.2, NOV. 28, 2013
92
MX25U25635F
P/N: PM1712
REV. 1.2, NOV. 28, 2013
93
MX25U25635F
P/N: PM1712
REV. 1.2, NOV. 28, 2013
94
MX25U25635F
20. REVISION HISTORY
Revision No. Description
Page
Date
0.01
1. Added RDCR, DREAD, QREAD, FastBoot, Advanced Sector
Protection, RDSFDP
P30,43,45,56, JUN/15/2012
P71,83~88
2. Modified Write Protection Selection (WPSEL), Power-on State, P68,69,90,98,
Power-up Timing, Ordering Information table P100
3. Modified Maximum Clock frequency, tCE, tVSL, tCH, tCL, tCLQX P4,6,94,98
4. Added new package: 8-land WSON (8x6 mm 3.4 x 4.3 EP)
P5,7,100,101,
P104
P85~86
P4 DEC/14/2012
P7
P93
P94
P96
P97
5. Revised SFDP table.
1.0
1. Removed "Advance Information"
2. Modified 16-SOP pin descriptions
3. Added ICC1 (max.) 25mA (f=133MHz)
4. Modified fRSCLK, tCH and tCL
5. Modified tVSL (min.) from 800us to 1500us
6. Added "Power Up/Down and Voltage Drop"
7. Modified content
P9,15,16,19,21,23,29-32,
P38,40,45,47,52,58,68,
P72-76,78-82,87
1.1
1.2
1. Removed Write Protection Selection (WPSEL),
Advanced Sector Protection
2. Modified VIL, RESET Timing table
3. Modified content
P19,23,68,77 MAR/06/2013
P72,79,83
P6,34,56,90
P35,56,90,91
4. Added MX25U25635FZ4I-08G
1. Added FFh at 6Fh:6Ch Addresses in SFDP Table
2. Modified VCC to Ground Potential
3. Updated ISB1, ISB2, and ICC3 in DC Table
4. Updated tPP, tSE, tBE32 and tBE in AC Table
5. Updated Erase time and Page Program time
6. Removed Advanced Information of MX25U25635FZ4I-08G
P77
P81
P83
P84
P89
P90
NOV/28/2013
P/N: PM1712
REV. 1.2, NOV. 28, 2013
95
MX25U25635F
Except for customized products which have been expressly identified in the applicable agreement, Macronix's
products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or
household applications only, and not for use in any applications which may, directly or indirectly, cause death,
personal injury, or severe property damages. In the event Macronix products are used in contradicted to their
target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its
actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or
distributors shall be released from any and all liability arisen therefrom.
Copyright© Macronix International Co., Ltd. 2011~2013. All rights reserved, including the trademarks and
tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit,
NBiit, Macronix NBit, eLiteFlash, HybridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC,
Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich Audio, Rich Book, Rich TV, and FitCAM. The names
and brands of third party referred thereto (if any) are for identification purposes only.
For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
96
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明