MX25U6435EZNI10G [Macronix]
64M-BIT [x 1/x 2/x 4] 1.8V CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY;
| 型号： | MX25U6435EZNI10G |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | 64M-BIT [x 1/x 2/x 4] 1.8V CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY |
| 文件： | 总83页 (文件大小：1174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MX25U6435E
MX25U6435E
DATASHEET
P/N: PM1561
REV. 1.5, NOV. 07, 2013
1
MX25U6435E
Contents
1. FEATURES ..............................................................................................................................................................6
2. GENERAL DESCRIPTION .....................................................................................................................................8
Table 1. Additional Feature Comparison .............................................................................................................9
3. PIN CONFIGURATIONS .......................................................................................................................................10
4. PIN DESCRIPTION................................................................................................................................................10
5. BLOCK DIAGRAM................................................................................................................................................. 11
6. DATA PROTECTION..............................................................................................................................................12
Table 2. Protected Area Sizes ...........................................................................................................................13
Table 3. 4K-bit Secured OTP Definition.............................................................................................................13
7. Memory Organization...........................................................................................................................................14
Table 4. Memory Organization (64Mb)..............................................................................................................14
8. DEVICE OPERATION............................................................................................................................................15
Figure 1. Serial Modes Supported.....................................................................................................................15
8-1. Quad Peripheral Interface (QPI) Read Mode...............................................................................................16
Figure 2. Enable QPI Sequence (Command 35H)............................................................................................16
Figure 3. Reset QPI Mode (Command F5H).....................................................................................................17
Figure 4. Fast QPI Read Mode (FASTRDQ) (Command EBH) .......................................................................17
9. COMMAND DESCRIPTION...................................................................................................................................18
Table 5. Command Set......................................................................................................................................18
9-1. Write Enable (WREN) ..................................................................................................................................20
9-2. Write Disable (WRDI)...................................................................................................................................20
9-3. Read Identification (RDID) ...........................................................................................................................20
9-4. Read Status Register (RDSR) .....................................................................................................................20
Figure 5. Program/ Erase flow with read array data..........................................................................................21
Figure 6. Program/ Erase flow without read array data (read P_FAIL/E_FAIL flag)..........................................22
Figure 7. WRSR flow.........................................................................................................................................23
Table 6. Status Register ....................................................................................................................................24
9-5. Write Status Register (WRSR).....................................................................................................................25
Table 7. Protection Modes.................................................................................................................................25
9-6. Read Data Bytes (READ).............................................................................................................................26
9-7. Read Data Bytes at Higher Speed (FAST_READ).......................................................................................26
9-8. 2 x I/O Read Mode (2READ)........................................................................................................................27
9-9. 4 x I/O Read Mode (4READ)........................................................................................................................27
9-10. Burst Read .................................................................................................................................................28
Table 8. Wrap Around Definition Table ..............................................................................................................28
Figure 8. SPI Mode ...........................................................................................................................................28
Figure 9. QPI Mode...........................................................................................................................................28
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9-11. Performance Enhance Mode......................................................................................................................29
9-12. Performance Enhance Mode Reset (FFh) .................................................................................................29
9-13. Sector Erase (SE) ......................................................................................................................................29
9-14. Block Erase (BE32K) .................................................................................................................................30
9-15. Block Erase (BE)........................................................................................................................................30
9-16. Chip Erase (CE).........................................................................................................................................30
9-17. Page Program (PP)....................................................................................................................................31
9-18. 4 x I/O Page Program (4PP) ......................................................................................................................31
9-19. Deep Power-down (DP) .............................................................................................................................32
9-20. Release from Deep Power-down (RDP), Read Electronic Signature (RES)..............................................32
9-21. Read Electronic Manufacturer ID & Device ID (REMS) ............................................................................. 33
9-22. QPI ID Read (QPIID)..................................................................................................................................33
Table 9. ID Definitions ......................................................................................................................................33
9-23. Enter Secured OTP (ENSO) ......................................................................................................................34
9-24. Exit Secured OTP (EXSO).........................................................................................................................34
9-25. Read Security Register (RDSCUR) ...........................................................................................................34
Table 10. Security Register Definition ...............................................................................................................35
9-26. Write Security Register (WRSCUR)...........................................................................................................35
9-27. Write Protection Selection (WPSEL)..........................................................................................................36
Figure 10. BP and SRWD if WPSEL=0.............................................................................................................36
Figure 11. The individual block lock mode is effective after setting WPSEL=1.................................................37
Figure 12. WPSEL Flow....................................................................................................................................38
9-28. Single Block Lock/Unlock Protection (SBLK/SBULK) ................................................................................39
Figure 13. Block Lock Flow ...............................................................................................................................39
Figure 14. Block Unlock Flow............................................................................................................................40
9-29. Read Block Lock Status (RDBLOCK) ........................................................................................................41
9-30. Gang Block Lock/Unlock (GBLK/GBULK)..................................................................................................41
9-31. Program/Erase Suspend/Resume .............................................................................................................41
9-32. Erase Suspend...........................................................................................................................................42
9-33. Program Suspend ......................................................................................................................................42
9-34. Write-Resume ............................................................................................................................................43
9-35. No Operation (NOP)...................................................................................................................................43
9-36. Software Reset (Reset-Enable (RSTEN) and Reset (RST))...................................................................... 43
9-37. Reset Quad I/O (RSTQIO).........................................................................................................................43
9-38. Read SFDP Mode (RDSFDP)....................................................................................................................44
Figure 15. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence..................................................44
Table 11. Signature and Parameter Identification Data Values .........................................................................45
Table 12. Parameter Table (0): JEDEC Flash Parameter Tables ......................................................................46
Table 13. Parameter Table (1): Macronix Flash Parameter Tables ...................................................................48
10. POWER-ON STATE.............................................................................................................................................50
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11. ELECTRICAL SPECIFICATIONS........................................................................................................................51
10-1. Absolute Maximum Ratings........................................................................................................................51
Figure 16. Maximum Negative Overshoot Waveform .......................................................................................51
11-1. Capacitance ...............................................................................................................................................51
Figure 17. Maximum Positive Overshoot Waveform.........................................................................................51
Figure 18. Input Test Waveforms and Measurement Level...............................................................................52
Figure 19. Output Loading.................................................................................................................................52
Table 14. DC Characteristics.............................................................................................................................53
Table 15. AC Characteristics .............................................................................................................................54
12. Timing Analysis..................................................................................................................................................55
Figure 20. Serial Input Timing ...........................................................................................................................55
Figure 21. Output Timing...................................................................................................................................55
Figure 22. WP# Setup Timing and Hold Timing during WRSR when SRWD=1................................................56
Figure 23. Write Enable (WREN) Sequence (Command 06) (SPI Mode).........................................................56
Figure 24. Write Enable (WREN) Sequence (Command 06) (QPI Mode) ........................................................56
Figure 25. Write Disable (WRDI) Sequence (Command 04) (SPI Mode) .........................................................57
Figure 26. Write Disable (WRDI) Sequence (Command 04) (QPI Mode).........................................................57
Figure 27. Read Identification (RDID) Sequence (Command 9F) (SPI mode only)..........................................57
Figure 28. Read Status Register (RDSR) Sequence (Command 05) (SPI Mode)............................................58
Figure 29. Read Status Register (RDSR) Sequence (Command 05) (QPI Mode)............................................58
Figure 30. Write Status Register (WRSR) Sequence (Command 01) (SPI Mode) ..........................................58
Figure 31. Write Status Register (WRSR) Sequence (Command 01) (QPI Mode)..........................................59
Figure 32. Read Data Bytes (READ) Sequence (Command 03) (SPI Mode only) (33MHz)............................ 59
Figure 33. Read at Higher Speed (FAST_READ) Sequence (Command 0B) (SPI Mode) (104MHz).............. 60
Figure 34. Read at Higher Speed (FAST_READ) Sequence (Command 0B) (QPI Mode) (84MHz)............... 60
Figure 35. 2 x I/O Read Mode Sequence (Command BB) (SPI Mode only) (84MHz) ......................................61
Figure 36. 4 x I/O Read Mode Sequence (Command EB) (SPI Mode) (104MHz)............................................61
Figure 37. 4 x I/O Read enhance performance Mode Sequence (Command EB) (SPI Mode) (104MHz)........ 62
Figure 38. 4 x I/O Read enhance performance Mode Sequence (Command EB) (QPI Mode) (104MHz)........ 63
Figure 39. Page Program (PP) Sequence (Command 02) (SPI Mode) ...........................................................63
Figure 40. Page Program (PP) Sequence (Command 02) (QPI Mode)...........................................................64
Figure 41. 4 x I/O Page Program (4PP) Sequence (Command 38) (SPI Mode only)...................................... 64
Figure 42. Sector Erase (SE) Sequence (Command 20) (SPI Mode)..............................................................65
Figure 43. Sector Erase (SE) Sequence (Command 20) (QPI Mode) .............................................................65
Figure 44. Block Erase 32KB (BE32K) Sequence (Command 52) (SPI Mode)...............................................65
Figure 45. Block Erase 32KB (BE32K) Sequence (Command 52) (QPI Mode)...............................................65
Figure 46. Block Erase (BE) Sequence (Command D8) (SPI Mode)...............................................................66
Figure 47. Block Erase (BE) Sequence (Command D8) (QPI Mode) ..............................................................66
Figure 48. Chip Erase (CE) Sequence (Command 60 or C7) (SPI Mode).......................................................66
Figure 49. Chip Erase (CE) Sequence (Command 60 or C7) (QPI Mode) ......................................................66
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Figure 50. Deep Power-down (DP) Sequence (Command B9) (SPI Mode) ....................................................67
Figure 51. Deep Power-down (DP) Sequence (Command B9) (QPI Mode)....................................................67
Figure 52. RDP and Read Electronic Signature (RES) Sequence (Command AB) (SPI Mode)...................... 67
Figure 53. Release from Deep Power-down (RDP) Sequence (Command AB) (SPI Mode)........................... 68
Figure 54. Release from Deep Power-down (RDP) Sequence (Command AB) (QPI Mode)........................... 68
Figure 55. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90) (SPI Mode only).. 69
Figure 56. Read Security Register (RDSCUR) Sequence (Command 2B) (SPI Mode).................................... 70
Figure 57. Read Security Register (RDSCUR) Sequence (Command 2B) (QPI Mode) ................................... 70
Figure 58. Write Security Register (WRSCUR) Sequence (Command 2F) (SPI Mode) ................................... 71
Figure 59. Write Security Register (WRSCUR) Sequence (Command 2F) (QPI Mode)................................... 71
Figure 60. Word Read Quad I/O (W4READ) Sequence (Command E7) (SPI Mode only, 84MHz).................. 72
Figure 61. Performance Enhance Mode Reset for Fast Read Quad I/O (SPI Mode) .......................................72
Figure 62. Performance Enhance Mode Reset for Fast Read Quad I/O (QPI Mode).......................................73
Figure 63. Reset Sequence (SPI mode) ...........................................................................................................73
Figure 64. Reset Sequence (QPI mode)...........................................................................................................73
Figure 65. Enable Quad I/O Sequence.............................................................................................................73
Figure 66. Suspend to Read Latency................................................................................................................74
Figure 67. Resume to Read Latency.................................................................................................................74
Figure 68. Resume to Suspend Latency...........................................................................................................74
Figure 69. Software Reset Recovery ................................................................................................................74
Figure 70. Power-up Timing ..............................................................................................................................75
Table 16. Power-Up Timing and VWI Threshold ...............................................................................................75
12-1. Initial Delivery State ...................................................................................................................................75
13. OPERATING CONDITIONS.................................................................................................................................76
Figure 71. AC Timing at Device Power-Up........................................................................................................76
Figure 72. Power-Down Sequence ...................................................................................................................77
14. ERASE AND PROGRAMMING PERFORMANCE..............................................................................................78
15. DATA RETENTION .............................................................................................................................................78
16. LATCH-UP CHARACTERISTICS........................................................................................................................78
17. ORDERING INFORMATION................................................................................................................................79
18. PART NAME DESCRIPTION...............................................................................................................................80
19. PACKAGE INFORMATION..................................................................................................................................81
20. REVISION HISTORY ...........................................................................................................................................82
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MX25U6435E
64M-BIT [x 1/x 2/x 4] 1.8V CMOS MXSMIO® (SERIAL MULTI I/O) FLASH MEMORY
1. FEATURES
GENERAL
•
Serial Peripheral Interface compatible -- Mode 0 and Mode 3
•
64Mb: 67,108,864 x 1 bit structure or 33,554,432 x 2 bits (two I/O mode) structure or 16,777,216 x 4 bits (four
I/O mode) structure
•
•
Equal Sectors with 4K byte each, or Equal Blocks with 32K byte each or Equal Blocks with 64K byte each
- Any Block can be erased individually
Single Power Supply Operation
- 1.65 to 2.0 volt for read, erase, and program operations
Latch-up protected to 100mA from -1V to Vcc +1V
Low Vcc write inhibit is from 1.0V to 1.4V
•
•
PERFORMANCE
•
High Performance
- Fast read for SPI mode
- 1 I/O: 104MHz with 8 dummy cycles
- 2 I/O: 84MHz with 4 dummy cycles, equivalent to 168MHz
- 4 I/O: 104MHz with 2+4 dummy cycles, equivalent to 416MHz
- Fast read for QPI mode
- 4 I/O: 84MHz with 2+2 dummy cycles, equivalent to 336MHz
- 4 I/O: 104MHz with 2+4 dummy cycles, equivalent to 416MHz
- Fast program time: 1.2ms(typ.) and 3ms(max.)/page (256-byte per page)
- Byte program time: 10us (typical)
- 8/16/32/64 byte Wrap-Around Burst Read Mode
- Fast erase time: 45ms (typ.)/sector (4K-byte per sector); 250ms(typ.)/block (32K-byte per block), 500ms(typ.) /
block (64K-byte per block); 36s(typ.) /chip
•
Low Power Consumption
- Low active read current: 20mA(typ.) at 104MHz, 15mA(typ.) at 84MHz
- Low active erase/programming current: 20mA (typ.)
- Standby current: 25uA (typ.)
•
•
•
Deep Power Down: 2uA(typ.)
Typical 100,000 erase/program cycles
20 years data retention
SOFTWARE FEATURES
•
Input Data Format
- 1-byte Command code
•
Advanced Security Features
- Block lock protection
The BP0-BP3 status bit defines the size of the area to be software protection against program and erase
instructions
- Additional 4k-bit secured OTP for unique identifier
Auto Erase and Auto Program Algorithm
•
Automatically erases and verifies data at selected sector or block
-
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MX25U6435E
•
•
•
•
Status Register Feature
Command Reset
Program/Erase Suspend
Electronic Identification
JEDEC 1-byte manufacturer ID and 2-byte device ID
- RES command for 1-byte Device ID
-
- REMS command for 1-byte manufacturer ID and 1-byte device ID
• Support Serial Flash Discoverable Parameters (SFDP) mode
HARDWARE FEATURES
•
•
•
•
•
•
SCLK Input
- Serial clock input
SI/SIO0
- Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
SO/SIO1
- Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
WP#/SIO2
- Hardware write protection or serial data Input/Output for 4 x I/O read mode
NC/SIO3
- No connection or Serial input & Output for 4 x I/O read mode
PACKAGE
- 8-land WSON (6x5mm)
- All devices are RoHS Compliant and Halogen-free
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2. GENERAL DESCRIPTION
MX25U6435E is 67,108,864 bits serial Flash memory, which is configured as 8,388,608 x 8 internally. When it is
in two or four I/O mode, the structure becomes 33,554,432 bits x 2 or 16,777,216 bits x 4. MX25U6435E feature a
serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single I/O
mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial
access to the device is enabled by CS# input.
When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits
input and data output. When it is in four I/O read mode, the SI pin, SO pin and WP# pin become SIO0 pin, SIO1
pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output.
The MX25U6435E MXSMIO® (Serial Multi I/O) provides sequential read operation on whole chip.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the
specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis, or word basis for erase command is executed on sector (4K-byte), block (32K-byte), or block (64K-byte),
or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
Advanced security features enhance the protection and security functions, please see security features section for
more details.
When the device is not in operation and CS# is high, it is put in standby mode and draws less than 30uA DC
current.
The MX25U6435E utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after
100,000 program and erase cycles.
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Table 1. Additional Feature Comparison
Read Performance
SPI
Additional
Protection and Security
Features
QPI
Flexible Block
Protection
(BP0-BP3)
Part
Name
4K-bit security
1 I/O
2 I/O
4 I/O
4 I/O
4 I/O
4 I/O
OTP
(104 MHz) (84 MHz) (84 MHz) (104 MHz) (84 MHz) (104 MHz)
MX25U6435E
V
V
V
V
V
V
V
V
Additional
Features
Identifier
RES
REMS
RDID
QPIID
(Command:
AF hex)
Part
Name
(command: (command: 90 (command:
AB hex)
hex)
9F hex)
C2 37 (hex)
(if ADD=0)
MX25U6435E
37 (hex)
C2 25 37
C2 25 37
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MX25U6435E
3. PIN CONFIGURATIONS
8-LAND WSON (6x5mm)
4. PIN DESCRIPTION
SYMBOL DESCRIPTION
CS#
Chip Select
Serial Data Input (for 1 x I/O)/ Serial
Data Input & Output (for 2xI/O or 4xI/
O read mode)
Serial Data Output (for 1 x I/O)/ Serial
Data Input & Output (for 2xI/O or 4xI/
O read mode)
1
2
3
4
VCC
CS#
SO/SIO1
WP#/SIO2
GND
8
7
6
5
SI/SIO0
NC/SIO3
SCLK
SI/SIO0
SO/SIO1
SCLK
Clock Input
Write protection: connect to GND or
WP#/SIO2 Serial Data Input & Output (for 4xI/O
read mode)
No Connection or Serial Data Input &
Output (for 4xI/O read mode)
NC/SIO3
VCC
+ 1.8V Power Supply
GND
Ground
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5. BLOCK DIAGRAM
Address
Generator
Memory Array
Page Buffer
Data
Register
SI/SIO0
Y-Decoder
SRAM
Buffer
Sense
Amplifier
CS#
WP#/SIO2
NC/SIO3
Mode
Logic
State
Machine
HV
Generator
SCLK
Clock Generator
Output
Buffer
SO/SIO1
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6. DATA PROTECTION
During power transition, there may be some false system level signals which result in inadvertent erasure or
programming. The device is designed to protect itself from these accidental write cycles.
The state machine will be reset as standby mode automatically during power up. In addition, the control register
architecture of the device constrains that the memory contents can only be changed after specific command
sequences have completed successfully.
In the following, there are several features to protect the system from the accidental write cycles during VCC power-
up and power-down or from system noise.
•
Power-on reset and tPUW: to avoid sudden power switch by system power supply transition, the power-on reset
and tPUW (internal timer) may protect the Flash.
• Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
issung other commands to change data. The WEL bit will return to reset stage under following situation:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP) command completion
- Quad I/O Page Program (4PP) command completion
- Sector Erase (SE) command completion
- Block Erase 32KB (BE32K) command completion
- Block Erase (BE) command completion
- Chip Erase (CE) command completion
- Program/Erase Suspend
- Softreset command completion
- Write Security Register (WRSCUR) command completion
- Write Protection Selection (WPSEL) command completion
•
•
Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from
writing all commands except Release from deep power down mode command (RDP) and Read Electronic
Signature command (RES) and softreset command.
Advanced Security Features: there are some protection and security features which protect content from
inadvertent write and hostile access.
I. Block lock protection
- The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected
as read only. The protected area definition is shown as "Table 2. Protected Area Sizes", the protected areas are
more flexible which may protect various area by setting value of BP0-BP3 bits.
- The Hardware Proteced Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and Status
Register Write Protect bit.
- In four I/O and QPI mode, the feature of HPM will be disabled.
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Table 2. Protected Area Sizes
Status bit
Protect Level
64Mb
BP3
0
BP2
0
BP1
0
BP0
0
0 (none)
0
0
0
1
1 (1 block, protected block 127th)
0
0
1
0
2 (2 blocks, protected block 126th~127th)
3 (4 blocks, protected block 124th~127th)
4 (8 blocks, protected block 120th~127th)
5 (16 blocks, protected block 112nd~127th)
6 (32 blocks, protected block 96th~127th)
7 (64 blocks, protected block 64th~127th)
8 (64 blocks, protected block 0th~63th)
9 (96 blocks, protected block 0th~95th)
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
10 (112 blocks, protected block 0th~111th)
11 (120 blocks, protected block 0th~119th)
12 (124 blocks, protected block 0th~123rd)
13 (126 blocks, protected block 0th~125th)
14 (127 blocks, protected block 0th~126th)
15 (128 blocks, protected all)
II. Additional 4K-bit secured OTP for unique identifier: to provide 4K-bit one-time program area for setting
device unique serial number - Which may be set by factory or system customer. Please refer to "Table 3. 4K-bit
Secured OTP Definition".
- Security register bit 0 indicates whether the chip is locked by factory or not.
- To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with Enter Security OTP (ENSO)
command), and going through normal program procedure, and then exiting 4K-bit secured OTP mode by writing
Exit Security OTP (EXSO) command.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register)
command to set customer lock-down bit1 as "1". Please refer to "Table 10. Security Register Definition" for
security register bit definition and "Table 3. 4K-bit Secured OTP Definition" for address range definition.
- Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit secured
OTP mode, array access is not allowed.
Table 3. 4K-bit Secured OTP Definition
Address range
xxx000~xxx00F
xxx010~xxx1FF
Size
Standard Factory Lock
ESN (electrical serial number)
N/A
Customer Lock
128-bit
3968-bit
Determined by customer
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7. Memory Organization
Table 4. Memory Organization (64Mb)
Block(64K-byte) Block(32K-byte) Sector (4K-byte)
Address Range
2047
7FF000h
7FFFFFh
255
individual 16 sectors
lock/unlock unit:4K-byte
2040
2039
7F8000h
7F7000h
7F8FFFh
7F7FFFh
127
254
253
252
251
250
2032
2031
7F0000h
7EF000h
7F0FFFh
7EFFFFh
2024
2023
7E8000h
7E7000h
7E8FFFh
7E7FFFh
126
individual block
lock/unlock unit:64K-byte
2016
2015
7E0000h
7DF000h
7E0FFFh
7DFFFFh
2008
2007
7D8000h
7D7000h
7D8FFFh
7D7FFFh
125
2000
7D0000h
7D0FFFh
individual block
lock/unlock unit:64K-byte
47
02F000h
02FFFFh
5
4
3
2
1
0
40
39
028000h
027000h
028FFFh
027FFFh
2
1
individual block
lock/unlock unit:64K-byte
32
31
020000h
01F000h
020FFFh
01FFFFh
24
23
018000h
017000h
018FFFh
017FFFh
16
15
010000h
00F000h
010FFFh
00FFFFh
8
7
008000h
007000h
008FFFh
007FFFh
individual 16 sectors
lock/unlock unit:4K-byte
0
0
000000h
000FFFh
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8. DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended
operation.
2. When incorrect command is inputted to this device, it enters standby mode and remains in standby mode until
next CS# falling edge. In standby mode, SO pin of the device is High-Z.
3. When correct command is inputted to this device, it enters active mode and remains in active mode until next
CS# rising edge.
4. Input data is latched on the rising edge of Serial Clock (SCLK) and data is shifted out on the falling edge of
SCLK. The difference of Serial mode 0 and mode 3 is shown as "Figure 1. Serial Modes Supported".
5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, RDSFDP, 2READ, 4READ, RES,
REMS, SQIID, RDBLOCK, the shifted-in instruction sequence is followed by a data-out sequence. After any bit
of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE32K,
BE, CE, PP, 4PP, DP, ENSO, EXSO, WRSCUR, WPSEL, SBLK, SBULK, GBULK, SUSPEND, RESUME, NOP,
RSTEN, RST, EQIO, RSTQIO the CS# must go high exactly at the byte boundary; otherwise, the instruction will
be rejected and not executed.
6. While a Write Status Register, Program or Erase operation is in progress, access to the memory array is
neglected and will not affect the current operation of Write Status Register, Program, Erase.
Figure 1. Serial Modes Supported
CPOL CPHA
shift in
shift out
SCLK
SCLK
(Serial mode 0)
(Serial mode 3)
0
1
0
1
SI
MSB
SO
MSB
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is
supported.
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8-1. Quad Peripheral Interface (QPI) Read Mode
QPI protocol enables user to take full advantage of Quad I/O Serial Flash by providing the Quad I/O interface in
command cycles, address cycles and as well as data output cycles.
Enable QPI mode
By issuing 35H command, the QPI mode is enabled.
Figure 2. Enable QPI Sequence (Command 35H)
CS#
MODE 3
MODE 0
2
3
4
5
6
7
0
1
SCLK
SIO0
35
SIO[3:1]
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Reset QPI mode
By issuing F5H command, the device is reset to 1-I/O SPI mode.
Figure 3. Reset QPI Mode (Command F5H)
CE#
SCLK
SIO[3:0]
F5
Fast QPI Read mode (FASTRDQ)
To increase the code transmission speed, the device provides a "Fast QPI Read Mode" (FASTRDQ). By issuing
command code EBH, the FASTRDQ mode is enabled. The number of dummy cycle increase from 4 to 6 cycles. The
read cycle frequency will increase from 84MHz to 104MHz.
Figure 4. Fast QPI Read Mode (FASTRDQ) (Command EBH)
CS#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MODE 3
MODE 0
MODE 3
MODE 0
SCLK
EB
SIO[3:0]
H0 L0 H1 L1 H2 L2 H3 L3
A5 A4 A3 A2 A1 A0
X
X
X
X
X
X
MSB
Data In
Data Out
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9. COMMAND DESCRIPTION
Table 5. Command Set
Read Commands
I/O
1
1
1
2
4
4
4
4
Read Mode
SPI
SPI
SPI
SPI
SPI
SPI
QPI
QPI
2READ (2
x I/O read
(Read SFDP) command)
Note1
4READ *
(4 x I/O read
command)
Note1
4READ *
(4 x I/O read
command)
Note1
FAST READ
* (fast read
data)
FAST READ
* (fast read
data)
Command
(byte)
READ
(normal read)
RDSFDP
W4READ
Clock rate
(MHz)
33
104
104
84
84
104
84
104
1st byte
2nd byte
3rd byte
4th byte
5th byte
03 (hex)
AD1(8)
AD2(8)
AD3(8)
0B (hex)
AD1(8)
AD2(8)
AD3(8)
Dummy(8)
5A (hex)
AD1(8)
AD2(8)
AD3(8)
Dummy(8)
BB (hex)
AD1(4)
AD2(4)
AD3(4)
Dummy(4)
E7 (hex)
AD1(2)
AD2(2)
EB (hex)
AD1(2)
AD2(2)
AD3(2)
Dummy(6)
Quad I/O n bytes read Quad I/O
read with out until CS# read with
6 dummy
cycles in
104MHz
0B (hex)
AD1(2)
AD2(2)
AD3(2)
Dummy(4)
EB (hex)
AD1(2)
AD2(2)
AD3(2)
Dummy(6)
AD3(2)
Dummy(4)
Quad I/O
read with
4 dummy
cycles in
84MHz
n bytes read n bytes read Read SFDP n bytes read
out until CS# out until CS#
goes high goes high
mode
out by 2 x I/
O until CS#
goes high
goes high
6 dummy
cycles in
104MHz
Action
Program/Erase Commands
Command
(byte)
WREN*
WRDI *
RDSR * (read WRSR * (write
4PP (quad
SE *
BE 32K * (block
(write enable) (write disable) status register) status register) page program) (sector erase) erase 32KB)
1st byte
2nd byte
3rd byte
4th byte
06 (hex)
04 (hex)
05 (hex)
01 (hex)
Values
38 (hex)
AD1
AD2
20 (hex)
AD1
AD2
52 (hex)
AD1
AD2
AD3
AD3
AD3
sets the (WEL)
write enable
latch bit
resets the
(WEL) write
to read out the to write new
values of the values of the
quad input to
program the selected sector selected 32K
to erase the
to erase the
Action
enable latch bit status register status register selected page
block
PGM/ERS
RDP * (Release Suspend *
PGM/ERS
Resume *
(Resumes
Program/
Erase)
Command
(byte)
BE * (block
erase 64KB)
CE * (chip
erase)
PP * (page
program)
DP * (Deep
power down)
from deep
(Suspends
Program/
Erase)
power down)
1st byte
2nd byte
3rd byte
4th byte
D8 (hex)
AD1
AD2
60 or C7 (hex)
02 (hex)
AD1
AD2
B9 (hex)
AB (hex)
B0 (hex)
30 (hex)
AD3
AD3
to erase the to erase whole to program the enters deep
release from
deep power
down mode
selected block
chip
selected page power down
Action
mode
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REV. 1.5, NOV. 07, 2013
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MX25U6435E
Security/ID/Mode Setting/Reset Commands
REMS (read
electronic
RDID
RES (read
RDSCUR *
(read security (write security
WRSCUR *
ENSO * (enter EXSO * (exit
Command (byte) (read identific-
electronic ID) manufacturer secured OTP) secured OTP)
& device ID)
ation)
register)
2B (hex)
register)
2F (hex)
1st byte
2nd byte
3rd byte
4th byte
5th byte
9F (hex)
AB (hex)
90 (hex)
B1 (hex)
C1 (hex)
x
x
x
x
x
ADD (Note 2)
outputs JEDEC to read out
output the
to enter the to exit the 4K- to read value to set the lock-
ID: 1-byte
Manufact-urer
ID & 2-byte
Device ID
1-byte Device Manufacturer 4K-bit secured bit secured
of security
register
down bit as
"1" (once lock-
down, cannot
be update)
ID
ID & Device ID OTP mode
OTP mode
Action
SBULK *
(single block (block protect
unlock)
39 (hex)
AD1
RDBLOCK *
COMMAND
(byte)
SBLK * (single
block lock
GBLK * (gang GBULK * (gang NOP * (No
RSTEN *
block lock)
block unlock)
Operation) (Reset Enable)
read)
3C (hex)
AD1
AD2
AD3
1st byte
2nd byte
3rd byte
4th byte
Action
36 (hex)
AD1
AD2
AD3
individual
block (64K-
7E (hex)
98 (hex)
00 (hex)
66 (hex)
AD2
AD3
individual block read individual whole chip
(64K-byte) or block or sector write protect
whole chip
unprotect
byte) or sector sector (4K-
(4K-byte) write byte) unprotect
protect
write protect
status
RST *
(Reset
Memory)
EQIO
RSTQIO
SBL *
(Set Burst
Length)
C0 (hex)
Value
WPSEL *
(Write Protect
Selection)
68 (hex)
COMMAND
(byte)
QPIID
(QPI ID Read)
(Enable Quad (Reset Quad I/
I/O)
35 (hex)
O)
F5 (hex)
1st byte
2nd byte
3rd byte
4th byte
Action
99 (hex)
AF (hex)
Entering the Exiting the QPI
QPI mode mode
ID in QPI
interface
to set Burst
length
to enter
and enable
individal block
protect mode
Note 1: Command set highlighted with (*) are supported both in SPI and QPI mode.
Note 2: The count base is 4-bit for ADD(2) and Dummy(2) because of 2 x I/O. And the MSB is on SI/SIO1 which is different from
1 x I/O condition.
Note 3: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first.
Note 4: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hid-
den mode.
Note 5: Before executing RST command, RSTEN command must be executed. If there is any other command to interfere, the
reset operation will be disabled.
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9-1. Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP,
SE, BE32K, BE, CE, and WRSR, which are intended to change the device content WEL bit should be set every time
after the WREN instruction setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low→sending WREN instruction code→ CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
in SPI mode. (Please refer to "Figure 23. Write Enable (WREN) Sequence (Command 06) (SPI Mode)" and "Figure
24. Write Enable (WREN) Sequence (Command 06) (QPI Mode)")
9-2. Write Disable (WRDI)
The Write Disable (WRDI) instruction is to reset Write Enable Latch (WEL) bit.
The sequence of issuing WRDI instruction is: CS# goes low→sending WRDI instruction code→CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care in
SPI mode. (Please refer to "Figure 26. Write Disable (WRDI) Sequence (Command 04) (QPI Mode)" and
"Figure 25. Write Disable (WRDI) Sequence (Command 04) (SPI Mode)" )
The WEL bit is reset by following situations:
- Power-up
- Completion of Write Disable (WRDI) instruction
- Completion of Write Status Register (WRSR) instruction
- Completion of Page Program (PP) instruction
- Completion of Quad Page Program (4PP) instruction
- Completion of Sector Erase (SE) instruction
- Completion of Block Erase 32KB (BE32K) instruction
- Completion of Block Erase (BE) instruction
- Completion of Chip Erase (CE) instruction
- Pgm/Ers Suspend
9-3. Read Identification (RDID)
The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Macronix
Manufacturer ID and Device ID are listed as "Table 9. ID Definitions" ID Definitions.
The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code→24-bits ID data out
on SO→ to end RDID operation can drive CS# to high at any time during data out.
While Program/Erase operation is in progress, it will not decode the RDID instruction, therefore there's no effect on
the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby
stage.
9-4. Read Status Register (RDSR)
The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even
in program/erase/write status register condition). It is recommended to check the Write in Progress (WIP) bit before
sending a new instruction when a program, erase, or write status register operation is in progress.
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MX25U6435E
The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register data
out on SO.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when
during SPI mode. (Please refer to "Figure 28. Read Status Register (RDSR) Sequence (Command 05) (SPI Mode)"
and "Figure 29. Read Status Register (RDSR) Sequence (Command 05) (QPI Mode)")
For user to check if Program/Erase operation is finished or not, RDSR instruction flow are shown as follows:
Figure 5. Program/ Erase flow with read array data
start
WREN command
RDSR command*
No
WEL=1?
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
No
WIP=0?
Yes
RDSR command
Read WEL=0, BP[3:0], QE,
and SRWD data
Read array data
(same address of PGM/ERS)
No
Verify OK?
Yes
Program/erase successfully
Program/erase fail
Yes
Program/erase
another block?
* Issue RDSR to check BP[3:0].
* If WPSEL = 1, issue RDBLOCK to check the block status.
No
Program/erase completed
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MX25U6435E
Figure 6. Program/ Erase flow without read array data (read P_FAIL/E_FAIL flag)
start
WREN command
RDSR command*
No
WEL=1?
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
No
WIP=0?
Yes
RDSR command
Read WEL=0, BP[3:0], QE,
and SRWD data
RDSCUR command
P_FAIL/E_FAIL =1 ?
Yes
No
Program/erase successfully
Program/erase fail
Yes
Program/erase
another block?
* Issue RDSR to check BP[3:0].
* If WPSEL = 1, issue RDBLOCK to check the block status.
No
Program/erase completed
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Figure 7. WRSR flow
start
WREN command
RDSR command
No
WEL=1?
Yes
WRSR command
Write status register data
RDSR command
No
WIP=0?
Yes
RDSR command
Read WEL=0, BP[3:0], QE,
and SRWD data
No
Verify OK?
Yes
WRSR successfully
WRSR fail
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The definitions of the status register bits are as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write
status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status
register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status
register cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable
latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/
erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the
device will not accept program/erase/write status register instruction. The program/erase command will be ignored
if it is applied to a protected memory area. To ensure both WIP bit & WEL bit are both set to 0 and available for next
program/erase/operations, WIP bit needs to be confirm to be 0 before polling WEL bit. After WIP bit confirmed, WEL
bit needs to be confirm to be 0.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area (as
defined in "Table 2. Protected Area Sizes") of the device to against the program/erase instruction without hardware
protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR)
instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector
Erase (SE), Block Erase 32KB (BE32K), Block Erase (BE) and Chip Erase (CE) instructions (only if Block Protect bits
(BP3:BP0) set to 0, the CE instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default. Which is un-
protected.
QE bit. The Quad Enable (QE) bit, non-volatile bit, performs SPI Quad modes when it is reset to "0" (factory default)
to enable WP# or is set to "1" to enable Quad SIO2 and SIO3. QE bit is only valid for SPI mode. When operate in SPI
mode, and quad IO read is desired (for command EBh/E7h, or quad IO program, 38h). WRSR command has to be
set the through Status Register bit 6, the QE bit. Then the SPI Quad I/O commands (EBh/E7h/38h) will be accepted
by flash. If QE bit is not set, SPI Quad I/O commands (EBh/E7h/38h) will be invalid commands, the device will not
respond to them. Once QE bit is set, all SPI commands are valid. 1I/O commands and 2 I/O commands can be issued
no matter QE bit is "0" or "1". When in QPI mode, QE bit will not affect the operation of QPI mode at all. Therefore
either "0" or "1" value of QE bit does not affect the QPI mode operation.
SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection
(WP#/SIO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and
WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is
no longer accepted for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only. The
SRWD bit defaults to be "0".
Table 6. Status Register
bit7
bit6
bit5
BP3
(level of
protected
block)
bit4
BP2
(level of
protected
block)
bit3
BP1
(level of
protected
block)
bit2
BP0
(level of
protected
block)
bit1
bit0
SRWD (status
register write
protect)
QE
(Quad
Enable)
WEL
(write enable
latch)
WIP
(write in
progress bit)
1=Quad
Enable
0=not Quad
Enable
1=write
enable
0=not write 0=not in write
enable
1=write
operation
1=status
register write
disable
(note 1)
(note 1)
(note 1)
(note 1)
operation
Non-volatile Non-volatile Non-volatile Non-volatile Non-volatile Non-volatile
bit bit bit bit bit bit
volatile bit
volatile bit
Note 1: See the "Table 2. Protected Area Sizes".
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9-5. Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction,
the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in
advance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to define the
protected area of memory (as shown in "Table 2. Protected Area Sizes"). The WRSR also can set or reset the Quad
enable (QE) bit and set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#/
SIO2) pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of the status register. The WRSR instruction cannot
be executed once the Hardware Protected Mode (HPM) is entered.
The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register
data on SI→CS# goes high. (Please refer to "Figure 30. Write Status Register (WRSR) Sequence (Command 01) (SPI
Mode)" and "Figure 31. Write Status Register (WRSR) Sequence (Command 01) (QPI Mode)")
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1
during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL)
bit is reset.
Table 7. Protection Modes
Mode
Status register condition
WP# and SRWD bit status
Memory
Status register can be written
in (WEL bit is set to "1") and
the SRWD, BP0-BP3
Software protection
WP#=1 and SRWD bit=0, or
WP#=0 and SRWD bit=0, or
WP#=1 and SRWD=1
The protected area
cannot
be program or erase.
mode (SPM)
bits can be changed
The SRWD, BP0-BP3 of
status register bits cannot be
changed
The protected area
cannot
be program or erase.
Hardware protection
WP#=0, SRWD bit=1
mode (HPM)
Note:
1. As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in "Table 2.
Protected Area Sizes".
As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM).
Software Protected Mode (SPM):
-
-
When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can
change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1,
BP0, is at software protected mode (SPM).
When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values
of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software
protected mode (SPM)
Note:
If SRWD bit=1 but WP#/SIO2 is low, it is impossible to write the Status Register even if the WEL bit has previously
been set. It is rejected to write the Status Register and not be executed.
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Hardware Protected Mode (HPM):
-
When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware
protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2,
BP1, BP0 and hardware protected mode by the WP#/SIO2 to against data modification.
Note:
To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered.
If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be entered; only
can use software protected mode via BP3, BP2, BP1, BP0.
If the system enter QPI or set QE=1, the feature of HPM will be disabled.
9-6. Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on
the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address
is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can
be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been
reached.
The sequence of issuing READ instruction is: CS# goes low→sending READ instruction code→ 3-byte address
on SI→ data out on SO→to end READ operation can use CS# to high at any time during data out. (Please refer to
"Figure 32. Read Data Bytes (READ) Sequence (Command 03) (SPI Mode only) (33MHz)")
9-7. Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at
any location. The address is automatically increased to the next higher address after each byte data is shifted out,
so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when
the highest address has been reached.
Read on SPI Mode The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ
instruction code→ 3-byte address on SI→1-dummy byte (default) address on SI→ data out on SO→ to end FAST_
READ operation can use CS# to high at any time during data out. (Please refer to "Figure 33. Read at Higher Speed
(FAST_READ) Sequence (Command 0B) (SPI Mode) (104MHz)")
Read on QPI Mode The sequence of issuing FAST_READ instruction in QPI mode is: CS# goes low→ sending
FAST_READ instruction, 2 cycles→ 24-bit address interleave on SIO3, SIO2, SIO1 & SIO0→4 dummy cycles→data
out interleave on SIO3, SIO2, SIO1 & SIO0→ to end QPI FAST_READ operation can use CS# to high at any time
during data out. (Please refer to "Figure 34. Read at Higher Speed (FAST_READ) Sequence (Command 0B) (QPI
Mode) (84MHz)")
In the performance-enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0]=A5h,5Ah,F0h or 0Fh can
make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0];
likewise P[7:0]=FFh,00h,AAh or 55h and afterwards CS# is raised and then lowered, the system then will escape
from performance enhance mode and return to normal operation.
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
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9-8. 2 x I/O Read Mode (2READ)
The 2READ instruction enable double throughput of Serial Flash in read mode. The address is latched on rising
edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a
maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the
next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ
instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ
instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing 2READ instruction is: CS# goes low
sending 2READ instruction
24-bit address
→
→
interleave on SIO1 & SIO0 4 dummy cycles on SIO1 & SIO0 data out interleave on SIO1 & SIO0 to end
→
→
→
2READ operation can use CS# to high at any time during data out (Please refer to "Figure 35. 2 x I/O Read Mode
Sequence (Command BB) (SPI Mode only) (84MHz)").
While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact on
the Program/Erase/Write Status Register current cycle.
9-9. 4 x I/O Read Mode (4READ)
The 4READ instruction enable quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status
Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCLK,
and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency
fQ. The first address byte can be at any location. The address is automatically increased to the next higher address
after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address
counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following
address/dummy/data out will perform as 4-bit instead of previous 1-bit.
4 x I/O Read on SPI Mode (4READ) The sequence of issuing 4READ instruction is: CS# goes low sending
→
4READ instruction
24-bit address interleave on SIO3, SIO2, SIO1 & SIO0 2+4 dummy cycles data out
→ →
→
interleave on SIO3, SIO2, SIO1 & SIO0 to end 4READ operation can use CS# to high at any time during data out.
→
W4READ instruction (E7) is also available is SPI mode for 4 I/O read. The sequence is similar to 4READ, but with
only 4 dummy cycles. The clock rate runs at 84MHz.
4 x I/O Read on QPI Mode (4READ) The 4READ instruction also support on QPI command mode. The sequence of
issuing 4READ instruction QPI mode is: CS# goes low sending 4READ instruction 24-bit address interleave on
→
→
SIO3, SIO2, SIO1 & SIO0 2+4 dummy cycles data out interleave on SIO3, SIO2, SIO1 & SIO0 to end 4READ
→
→
→
operation can use CS# to high at any time during data out (Please refer to "Figure 36. 4 x I/O Read Mode Sequence
(Command EB) (SPI Mode) (104MHz)").
Another sequence of issuing 4 READ instruction especially useful in random access is : CS# goes low sending
→
4 READ instruction 3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 performance enhance toggling
→
→
bit P[7:0] 4 dummy cycles data out still CS# goes high
CS# goes low (reduce 4 Read instruction) 24-bit
→
→
→
→
random access address (Please refer to "Figure 37. 4 x I/O Read enhance performance Mode Sequence (Command
EB) (SPI Mode) (104MHz)" and "Figure 38. 4 x I/O Read enhance performance Mode Sequence (Command EB) (QPI
Mode) (104MHz)").
In the performance-enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh
can make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0];
likewise P[7:0]=FFh,00h,AAh or 55h and afterwards CS# is raised and then lowered, the system then will escape
from performance enhance mode and return to normal operation.
While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact on
the Program/Erase/Write Status Register current cycle.
P/N: PM1561
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27
MX25U6435E
9-10. Burst Read
This device supports Burst Read in both SPI and QPI mode.
To set the Burst length, following command operation is required
Issuing command: “C0h” in the first Byte (8-clocks), following 4 clocks defining wrap around enable with “0h” and
disable with“1h”.
Next 4 clocks are to define wrap around depth. Definition as following table:
Table 8. Wrap Around Definition Table
Data
1xh
1xh
1xh
1xh
Wrap Around
Wrap Depth
Data
00h
01h
02h
03h
Wrap Around
Wrap Depth
8-byte
No
No
No
No
X
X
X
X
Yes
Yes
Yes
Yes
16-byte
32-byte
64-byte
The wrap around unit is defined within the 256Byte page, with random initial address. It’s defined as “wrap-around
mode disable” for the default state of the device. To exit wrap around, it is required to issue another “C0” command
in which data=‘1xh”. Otherwise, wrap around status will be retained until power down or reset command. To change
wrap around depth, it is requried to issue another “C0” command in which data=“0xh”. QPI “0Bh” “EBh” and SPI “EBh”
“E7h” support wrap around feature after wrap around enable. Burst read is supported in both SPI and QPI mode. (The
device ID default without Burst Read)
Figure 8. SPI Mode
CS#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCLK
SIO
1
1
0
0
0
0
0
0
H
H
H
H
L
L
L
L
Figure 9. QPI Mode
CS#
0
1
2
3
SCLK
C1
C0
H0
L0
SIO[3:0]
MSB LSB
Note: MSB=Most Significant Bit
LSB=Least Significant Bit
P/N: PM1561
REV. 1.5, NOV. 07, 2013
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MX25U6435E
9-11. Performance Enhance Mode
The device could waive the command cycle bits if the two cycle bits after address cycle toggles. (Please refer to
"Figure 37. 4 x I/O Read enhance performance Mode Sequence (Command EB) (SPI Mode) (104MHz)" and "Figure
38. 4 x I/O Read enhance performance Mode Sequence (Command EB) (QPI Mode) (104MHz)").
Performance enhance mode is supported in both SPI and QPI mode.
In QPI mode, “EBh” “0Bh” and SPI “EBh” “E7h” commands support enhance mode. The performance enhance
mode is not supported in dual I/O mode.
After entering enhance mode, following CSB go high, the device will stay in the read mode and treat CSB go low of
the first clock as address instead of command cycle.
To exit enhance mode, a new fast read command whose first two dummy cycles is not toggle then exit. Or issue
”FFh” command to exit enhance mode.
9-12. Performance Enhance Mode Reset (FFh)
To conduct the Performance Enhance Mode Reset operation in SPI mode, FFh command code, 8 clocks, should
be issued in 1I/O sequence. In QPI Mode, FFFFFFFFh command code, 8 clocks, in 4I/O should be issued.
(Please refer to "Figure 61. Performance Enhance Mode Reset for Fast Read Quad I/O (SPI Mode)", "Figure 62.
Performance Enhance Mode Reset for Fast Read Quad I/O (QPI Mode)")
If the system controller is being Reset during operation, the flash device will return to the standard SPI operation.
Upon Reset of main chip, SPI instruction would be issued from the system. Instructions like Read ID (9Fh) or Fast
Read (0Bh) would be issued.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
9-13. Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for
any 4K-byte sector. A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit
before sending the Sector Erase (SE). Any address of the sector (see "Table 4. Memory Organization (64Mb)" )
is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the least
significant bit of the address been latched-in); otherwise, the instruction will be rejected and not executed.
Address bits [Am-A12] (Am is the most significant address) select the sector address.
The sequence of issuing SE instruction is: CS# goes low→ sending SE instruction code→ 3-byte address on SI→
CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode. (Please refer to "Figure 42. Sector Erase (SE) Sequence (Command 20) (SPI Mode)",
"Figure 43. Sector Erase (SE) Sequence (Command 20) (QPI Mode)")
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets during the tSE
timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
sector is protected by BP3, BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the sector.
P/N: PM1561
REV. 1.5, NOV. 07, 2013
29
MX25U6435E
9-14. Block Erase (BE32K)
The Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1". The instruction is used for
32K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable Latch
(WEL) bit before sending the Block Erase (BE32K). Any address of the block (see "Table 4. Memory Organization
(64Mb)") is a valid address for Block Erase (BE32K) instruction. The CS# must go high exactly at the byte boundary (the
least significant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE32K instruction is: CS# goes low→ sending BE32K instruction code→ 3-byte address
on SI→CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode. (Please refer to "Figure 44. Block Erase 32KB (BE32K) Sequence (Command 52) (SPI
Mode)"and "Figure 45. Block Erase 32KB (BE32K) Sequence (Command 52) (QPI Mode)")
The self-timed Block Erase Cycle time (tBE32K) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during the tBE32K
timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
block is protected by BP3, BP2, BP1, BP0 bits, the Block Erase (BE32K) instruction will not be executed on the
block.
9-15. Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used
for 64K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable
Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (Please refer to "Table 4. Memory
Organization (64Mb)") is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte
boundary (the least significant bit of address byte been latched-in); otherwise, the instruction will be rejected and not
executed.
The sequence of issuing BE instruction is: CS# goes low→ sending BE instruction code→ 3-byte address on SI→
CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode. (Please refer to "Figure 46. Block Erase (BE) Sequence (Command D8) (SPI Mode)" and
"Figure 47. Block Erase (BE) Sequence (Command D8) (QPI Mode)")
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during the tBE
timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
block is protected by BP3, BP2, BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the block.
9-16. Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN)
instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS#
must go high exactly at the byte boundary, otherwise the instruction will be rejected and not executed.
The sequence of issuing CE instruction is: CS# goes low→sending CE instruction code→CS# goes high.
P/N: PM1561
REV. 1.5, NOV. 07, 2013
30
MX25U6435E
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode. (Please refer to "Figure 48. Chip Erase (CE) Sequence (Command 60 or C7) (SPI Mode)",
"Figure 49. Chip Erase (CE) Sequence (Command 60 or C7) (QPI Mode)")
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Chip Erase cycle is in progress. The WIP sets during the tCE
timing, and clears when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
chip is protected by BP3, BP2, BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only
executed when BP3, BP2, BP1, BP0 all set to "0".
9-17. Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction
must be executed to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device
programs only the last 256 data bytes sent to the device. The last address byte (the 8 least significant address
bits, A7-A0) should be set to 0 for 256 bytes page program. If A7-A0 are not all zero, transmitted data that exceed
page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently selected
page. If the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the request page
and previous data will be disregarded. If the data bytes sent to the device has not exceeded 256, the data will be
programmed at the request address of the page. There will be no effort on the other data bytes of the same page.
The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→ at
least 1-byte on data on SI→ CS# goes high. (Please refer to "Figure 39. Page Program (PP) Sequence (Command
02) (SPI Mode)" and "Figure 40. Page Program (PP) Sequence (Command 02) (QPI Mode)")
The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte
boundary( the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be
executed.
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Page Program cycle is in progress. The WIP sets during the tPP
timing, and clears when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
page is protected by BP3, BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
9-18. 4 x I/O Page Program (4PP)
The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN)
instruction must be executed to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to
"1" before sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1,
SIO2, and SIO3 as address and data input, which can improve programmer performance and the effectiveness of
application of lower clock less than 33MHz. For system with faster clock, the Quad page program cannot provide
more performance, because the required internal page program time is far more than the time data flows in.
Therefore, we suggest that while executing this command (especially during sending data), user can slow the clock
speed down to 33MHz below. The other function descriptions are as same as standard page program.
The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on
SIO[3:0]→ at least 1-byte on data on SIO[3:0]→CS# goes high.
P/N: PM1561
REV. 1.5, NOV. 07, 2013
31
MX25U6435E
9-19. Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device to minimum power consumption (the current is
reduced from standby to deep power-down). The Deep Power-down mode requires the Deep Power-down (DP)
instruction to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase
instruction are ignored.
The sequence of issuing DP instruction is: CS# goes low→sending DP instruction code→CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode. (Please refer to "Figure 50. Deep Power-down (DP) Sequence (Command B9) (SPI Mode)"
and "Figure 51. Deep Power-down (DP) Sequence (Command B9) (QPI Mode)")
Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP)
and Read Electronic Signature (RES) instruction and softreset command. (those instructions allow the ID being
reading out). When Power-down, or software reset command the deep power-down mode automatically stops, and
when power-up, the device automatically is in standby mode. For DP instruction the CS# must go high exactly at the
byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed.
As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode.
9-20. Release from Deep Power-down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is completed by driving Chip Select (CS#) High. When Chip
Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the
Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in
the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip
Select (CS#) must remain High for at least tRES2(max), as specified in "Table 15. AC Characteristics". Once in the
Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. The
RDP instruction is only for releasing from Deep Power Down Mode.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as "Table 9. ID
Definitions" on next page. This is not the same as RDID instruction. It is not recommended to use for new design.
For new design, please use RDID instruction.
The sequence is shown as "Figure 52. RDP and Read Electronic Signature (RES) Sequence (Command AB) (SPI
Mode)", "Figure 53. Release from Deep Power-down (RDP) Sequence (Command AB) (SPI Mode)" and "Figure 54.
Release from Deep Power-down (RDP) Sequence (Command AB) (QPI Mode)". Even in Deep power-down mode,
the RDP and RES are also allowed to be executed, only except the device is in progress of program/erase/write
cycle; there's no effect on the current program/erase/write cycle in progress.
SPI (8 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if
continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in Deep
Power-down mode, the device transition to standby mode is immediate. If the device was previously in Deep Power-
down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least tRES2(max).
Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction.
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MX25U6435E
9-21. Read Electronic Manufacturer ID & Device ID (REMS)
The REMS instruction is an alternative to the Release from Power-down/Device ID instruction that provides both the
JEDEC assigned manufacturer ID and the specific device ID.
The REMS instruction is very similar to the Release from Power-down/Device ID instruction. The instruction is
initiated by driving the CS# pin low and shift the instruction code "90h" followed by two dummy bytes and one bytes
address (A7~A0). After which, the Manufacturer ID for Macronix (C2h) and the Device ID are shifted out on the
falling edge of SCLK with most significant bit (MSB) first as shown in "Figure 55. Read Electronic Manufacturer &
Device ID (REMS) Sequence (Command 90) (SPI Mode only)". The Device ID values are listed in "Table 9. ID
Definitions". If the one-byte address is initially set to 01h, then the device ID will be read first and then followed by
the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other.
The instruction is completed by driving CS# high.
9-22. QPI ID Read (QPIID)
User can execute this QPIID Read instruction to identify the Device ID and Manufacturer ID. The sequence of
issue QPIID instruction is CS# goes low→sending QPI ID instruction→→Data out on SO→CS# goes high. Most
significant bit (MSB) first.
After the command cycle, the device will immediately output data on the falling edge of SCLK. The manufacturer ID,
memory type, and device ID data byte will be output continuously, until the CS# goes high.
Table 9. ID Definitions
Command Type
MX25U6435E
manufacturer
memory
density
37
memory type
ID
C2
RDID (JEDEC ID)
25
electronic ID
37
RES
manufacturer
device ID
37
ID
C2
REMS
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MX25U6435E
9-23. Enter Secured OTP (ENSO)
The ENSO instruction is for entering the additional 4K-bit secured OTP mode. While the device is in 4K-bit secured
OTP mode, main array access is not available. The additional 4K-bit secured OTP is independent from main array,
and may be used to store unique serial number for system identifier. After entering the Secured OTP mode, follow
standard read or program procedure to read out the data or update data. The Secured OTP data cannot be updated
again once it is lock-down.
The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP
mode→ CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
Please note that WRSR/WRSCUR commands are not acceptable during the access of secure OTP region, once
security OTP is lock down, only read related commands are valid.
9-24. Exit Secured OTP (EXSO)
The EXSO instruction is for exiting the additional 4K-bit secured OTP mode.
The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP
mode→ CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
9-25. Read Security Register (RDSCUR)
The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read
at any time (even in program/erase/write status register/write security register condition) and continuously.
The sequence of issuing RDSCUR instruction is : CS# goes low→sending RDSCUR instruction→Security Register
data out on SO→ CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode. Please see "Figure 56. Read Security Register (RDSCUR) Sequence (Command 2B) (SPI
Mode)" & "Figure 57. Read Security Register (RDSCUR) Sequence (Command 2B) (QPI Mode)".
The definition of the Security Register bits is as below:
Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory or not. When it is
"0", it indicates non-factory lock; "1" indicates factory-lock.
Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for
customer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 4K-bit Secured
OTP area cannot be updated any more.
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MX25U6435E
Table 10. Security Register Definition
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ESB
(Erase
PSB
(Program
LDSO
(indicate if
Secured OTP
indicator bit
WPSEL
E_FAIL
P_FAIL
Reserved
Suspend bit) Suspend bit) lock-down)
0=normal
Program
succeed
1=indicate
Program
failed
0 = not lock-
0=normal
Erase
succeed
1=indicate
Erase failed
(default=0)
0=Erase
is not
suspended suspended
1= Erase 1= Program
suspended suspended
0=Program
0=normal
WP mode
1=individual
mode
down
1 = lock-down
(cannot
program/
erase
0 = non-
factory
lock
1 = factory
lock
is not
-
(default=0)
(default=0)
(default=0)
(default=0)
OTP)
Non-volatile
bit
Non-volatile
bit (OTP)
Non-volatile
bit (OTP)
Volatile bit
Volatile bit
Volatile bit
Volatile bit
Volatile bit
(OTP)
9-26. Write Security Register (WRSCUR)
The WRSCUR instruction is for setting the values of Security Register Bits. The WREN (Write Enable) instruction is
required before issuing WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO bit)
for customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area
cannot be updated any more. The LDSO bit is an OTP bit. Once the LDSO bit is set, the value of LDSO bit can not
be altered any more.
The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode. Please see "Figure 58. Write Security Register (WRSCUR) Sequence (Command 2F) (SPI
Mode)" & "Figure 59. Write Security Register (WRSCUR) Sequence (Command 2F) (QPI Mode)".
The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
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9-27. Write Protection Selection (WPSEL)
There are two write protection methods, (1) BP protection mode (2) individual block protection mode. If WPSEL=0,
flash is under BP protection mode . If WPSEL=1, flash is under individual block protection mode. The default value
of WPSEL is “0”. WPSEL command can be used to set WPSEL=1. Please note that WPSEL is an OTP bit. Once
WPSEL is set to 1, there is no chance to recovery WPSEL back to “0”. If the flash is put on BP mode, the
individual block protection mode is disabled. Contrarily, if flash is on the individual block protection mode, the BP
mode is disabled.
Every time after the system is powered-on, the Security Register bit 7 is checked. If WPSEL=1, all the
blocks and sectors will be write protected by default. User may only unlock the blocks or sectors via SBULK
and GBULK instructions. Program or erase functions can only be operated after the Unlock instruction is executed.
BP protection mode, WPSEL=0:
ARRAY is protected by BP3~BP0 and BP3~BP0 bits are protected by “SRWD=1 and WP#=0”, where SRWD is bit 7
of status register that can be set by WRSR command.
Individual block protection mode, WPSEL=1:
Blocks are individually protected by their own SRAM lock bits which are set to “1” after power up. SBULK and SBLK
command can set SRAM lock bit to “0” and “1”. When the system accepts and executes WPSEL instruction, bit
7 in the security register will be set. It will activate SBLK, SBULK, RDBLOCK, GBLK, GBULK etc instructions to
conduct block lock protection and replace the original Software Protect Mode (SPM) use (BP3~BP0) indicated block
methods. Under the individual block protection mode (WPSEL=1), hardware protection is performed by driving
WP#=0. Once WP#=0 all array blocks/sectors are protected regardless of the contents of SRAM lock bits.
The sequence of issuing WPSEL instruction is: CS# goes low → sending WPSEL instruction to enter the individual
block protect mode → CS# goes high.
WPSEL instruction function flow is as follows:
Figure 10. BP and SRWD if WPSEL=0
WPB pin
BP3 BP2 BP1 BP0
SRWD
64KB
64KB
64KB
(1) BP3~BP0 is used to define the protection group region.
(The protected area size see "Table 2. Protected Area
Sizes")
(2) “SRWD=1 and WPB=0” is used to protect BP3~BP0. In this
case, SRWD and BP3~BP0 of status register bits can not
be changed by WRSR
.
.
.
64KB
P/N: PM1561
REV. 1.5, NOV. 07, 2013
36
MX25U6435E
Figure 11. The individual block lock mode is effective after setting WPSEL=1
4KB
4KB
SRAM
SRAM
• Power-Up: All SRAM bits=1 (all blocks are default protected).
All array cannot be programmed/erased
TOP 4KBx16
Sectors
• SBLK/SBULK(36h/39h):
- SBLK(36h): Set SRAM bit=1 (protect) : array can not be
programmed/erased
4KB
SRAM
SRAM
- SBULK(39h): Set SRAM bit=0 (unprotect): array can be
programmed/erased
64KB
- All top 4KBx16 sectors and bottom 4KBx16 sectors
and other 64KB uniform blocks can be protected and
unprotected SRAM bits individually by SBLK/SBULK
command set.
SRAM
Uniform
64KB blocks
• GBLK/GBULK(7Eh/98h):
- GBLK(7Eh): Set all SRAM bits=1,whole chip are protected
and cannot be programmed/erased.
- GBULK(98h): Set all SRAM bits=0,whole chip are
unprotected and can be programmed/erased.
- All sectors and blocks SRAM bits of whole chip can be
protected and unprotected at one time by GBLK/GBULK
command set.
64KB
4KB
SRAM
SRAM
Bottom
4KBx16
Sectors
• RDBLOCK(3Ch):
- use RDBLOCK mode to check the SRAM bits status after
SBULK /SBLK/GBULK/GBLK command set.
4KB
SBULK / SBLK / GBULK / GBLK / RDBLOCK
P/N: PM1561
REV. 1.5, NOV. 07, 2013
37
MX25U6435E
Figure 12. WPSEL Flow
start
WREN command
RDSCUR(2Bh) command
WPSEL=1?
Yes
No
WPSEL disable,
block protected by BP[3:0]
WPSEL(68h) command
RDSR command
WIP=0?
No
Yes
RDSCUR(2Bh) command
No
WPSEL=1?
Yes
WPSEL set successfully
WPSEL set fail
WPSEL enable.
Block protected by individual lock
(SBLK, SBULK, … etc).
P/N: PM1561
REV. 1.5, NOV. 07, 2013
38
MX25U6435E
9-28. Single Block Lock/Unlock Protection (SBLK/SBULK)
These instructions are only effective after WPSEL was executed. The SBLK instruction is for write protection a
specified block (or sector) of memory, using AMAX-A16 or (AMAX-A12) address bits to assign a 64Kbyte block (or 4K
bytes sector) to be protected as read only. The SBULK instruction will cancel the block (or sector) write protection
state. This feature allows user to stop protecting the entire block (or sector) through the chip unprotect command
(GBULK).
The WREN (Write Enable) instruction is required before issuing SBLK/SBULK instruction.
The sequence of issuing SBLK/SBULK instruction is: CS# goes low → send SBLK/SBULK (36h/39h)
instruction→send 3 address bytes assign one block (or sector) to be protected on SI pin → CS# goes high. The CS#
must go high exactly at the byte boundary, otherwise the instruction will be rejected and not be executed.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
SBLK/SBULK instruction function flow is as follows:
Figure 13. Block Lock Flow
Start
RDSCUR(2Bh) command
No
WPSEL=1?
WPSEL command
Yes
WREN command
SBLK command
( 36h + 24bit address )
RDSR command
No
WIP=0?
Yes
RDBLOCK command
( 3Ch + 24bit address )
No
Data = FFh ?
Yes
Block lock successfully
Block lock fail
Yes
Lock another block?
No
Block lock completed
P/N: PM1561
REV. 1.5, NOV. 07, 2013
39
MX25U6435E
Figure 14. Block Unlock Flow
start
RDSCUR(2Bh) command
No
WPSEL=1?
Yes
WPSEL command
WREN command
SBULK command
( 39h + 24bit address )
RDSR command
No
WIP=0?
Yes
RDBLOCK command to verify
( 3Ch + 24bit address )
Yes
Data = FF ?
No
Block unlock successfully
Block unlock fail
Yes
Unlock another block?
Unlock block completed?
P/N: PM1561
REV. 1.5, NOV. 07, 2013
40
MX25U6435E
9-29. Read Block Lock Status (RDBLOCK)
This instruction is only effective after WPSEL was executed. The RDBLOCK instruction is for reading the status
of protection lock of a specified block (or sector), using AMAX-A16 (or AMAX-A12) address bits to assign a 64K bytes
block (4K bytes sector) and read protection lock status bit which the first byte of Read-out cycle. The status bit is "1"
to indicate that this block has be protected, that user can read only but cannot write/program /erase this block. The
status bit is "0" to indicate that this block hasn't be protected, and user can read and write this block.
The sequence of issuing RDBLOCK instruction is: CS# goes low → send RDBLOCK (3Ch) instruction → send 3
address bytes to assign one block on SI pin → read block's protection lock status bit on SO pin → CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
9-30. Gang Block Lock/Unlock (GBLK/GBULK)
These instructions are only effective after WPSEL was executed. The GBLK/GBULK instruction is for enable/disable
the lock protection block of the whole chip.
The WREN (Write Enable) instruction is required before issuing GBLK/GBULK instruction.
The sequence of issuing GBLK/GBULK instruction is: CS# goes low → send GBLK/GBULK (7Eh/98h) instruction
→CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
The CS# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed.
9-31. Program/Erase Suspend/Resume
The device allow the interruption of Sector-Erase, Block-Erase or Page-Program operations and conduct other
operations. Details as follows.
To enter the suspend/resume mode: issuing B0h for suspend; 30h for resume (SPI/QPI all acceptable)
Read security register bit2 (PSB) and bit3 (ESB) (please refer to "Table 10. Security Register Definition") to check
suspend ready information.
For "Suspend to Read", "Resume to Read", "Resume to Suspend" timing specification please note "Figure 66.
Suspend to Read Latency", "Figure 67. Resume to Read Latency" and "Figure 68. Resume to Suspend Latency".
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
P/N: PM1561
REV. 1.5, NOV. 07, 2013
41
MX25U6435E
9-32. Erase Suspend
Erase suspend allow the interruption of all erase operations.
After erase suspend, WEL bit will be clear, only read related, resume and reset command can be accepted
unconditionally. (including: 03h, 0Bh, BBh, EBh, E7h, 9Fh, AFh, 90h, 05h, 2Bh, B1h, C1h, 5Ah, 3Ch, 30h, 66h, 99h,
C0h, 35h, F5h, 00h, ABh)
For erase suspend to program operation, the programming command (38, 02) can be accepted under conditions as
follows:
The bank is divided into 16 banks in this device, each bank's density is 4Mb. While conducting erase suspend in
one bank, the programming operation that follows can only be conducted in one of the other banks and cannot be
conducted in the bank executing the suspend operation. The boundaries of the banks are illustrated as below table.
BANK (4M bit)
Address Range
780000h-7FFFFFh
700000h-77FFFFh
680000h-6FFFFFh
600000h-67FFFFh
580000h-5FFFFFh
500000h-57FFFFh
480000h-4FFFFFh
400000h-47FFFFh
BANK (4M bit)
Address Range
380000h-3FFFFFh
300000h-37FFFFh
280000h-2FFFFFh
200000h-27FFFFh
180000h-1FFFFFh
100000h-17FFFFh
080000h-0FFFFFh
000000h-07FFFFh
15
14
13
12
11
10
9
7
6
5
4
3
2
1
0
8
After erase suspend command has been issued, latency time is needed before issue another command. For
"Suspend to Read", "Resume to Read", "Resume to Suspend" timing specification please note "Figure 66. Suspend
to Read Latency", "Figure 67. Resume to Read Latency" and "Figure 68. Resume to Suspend Latency".
Erase Suspend Bit (ESB) indicates the status of Erase Suspend operation. Users may use ESB to identify the
state of flash memory. After the flash memory is suspended by Erase Suspend command, ESB is set to "1". ESB is
cleared to "0" after erase operation resumes.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
When ESB bit is issued, the Write Enable Latch (WEL) bit will be reset.
See "Figure 66. Suspend to Read Latency" for Suspend to Read latency.
9-33. Program Suspend
Program suspend allows the interruption of all program operations.
After program suspend, WEL bit will be cleared, only read related, resume and reset command can be accepted.
(including: 03h, 0Bh, BBh, EBh, E7h, 9Fh, AFh, 90h, 05h, 2Bh, B1h, C1h, 5Ah, 3Ch, 30h, 66h, 99h, C0h, 35h, F5h,
00h, ABh)
After program suspend command has been issued, latency time is needed before issue another command.
For "Suspend to Read", "Resume to Read", "Resume to Suspend" timing specification please note "Figure 66.
Suspend to Read Latency", "Figure 67. Resume to Read Latency" and "Figure 68. Resume to Suspend Latency".
Program Suspend Bit (PSB) indicates the status of Program Suspend operation. Users may use PSB to identify the
state of flash memory. After the flash memory is suspended by Program Suspend command, PSB is set to "1". PSB
is cleared to "0" after program operation resumes.
P/N: PM1561
REV. 1.5, NOV. 07, 2013
42
MX25U6435E
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
9-34. Write-Resume
The Write operation is being resumed when Write-Resume instruction issued. ESB or PSB (suspend status bit) in
Status register will be changed back to “0”
The operation of Write-Resume is as follows: CS# drives low → send write resume command cycle (30H) → drive
CS# high. By polling Busy Bit in status register, the internal write operation status could be checked to be completed
or not. The user may also wait the time lag of TSE, TBE, TPP for Sector-erase, Block-erase or Page-programming.
WREN (command "06" is not required to issue before resume. Resume to another suspend operation requires
latency time. Please refer to "Figure 68. Resume to Suspend Latency".
Please note that, if "performance enhance mode" is executed during suspend operation, the device can not be
resume. To restart the write command, disable the "performance enhance mode" is required. After the "performance
enhance mode" is disable, the write-resume command is effective.
9-35. No Operation (NOP)
The "No Operation" command is only able to terminate the Reset Enable (RSTEN) command and will not affect any
other command.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
9-36. Software Reset (Reset-Enable (RSTEN) and Reset (RST))
The Software Reset operation combines two instructions: Reset-Enable (RSTEN) command and Reset (RST)
command. It returns the device to a standby mode. All the volatile bits and settings will be cleared then, which
makes the device return to the default status as power on.
To execute Reset command (RST), the Reset-Enable (RSTEN) command must be executed first to perform the
Reset operation. If there is any other command to interrupt after the Reset-Enable command, the Reset-Enable will
be invalid.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode. Please refer to "Figure 63. Reset Sequence (SPI mode)" and "Figure 64. Reset Sequence (QPI
mode)".
If the Reset command is executed during program or erase operation, the operation will be disabled, the data under
processing could be damaged or lost.
The reset time is different depending on the last operation. Longer latency time is required to recover from a
program operation than from other operations.
9-37. Reset Quad I/O (RSTQIO)
To reset the QPI mode, the RSTQIO (F5H) command is required. After the RSTQIO command is issued, the device
returns from QPI mode (4 I/O interface in command cycles) to SPI mode (1 I/O interface in command cycles).
Note:
For EQIO and RSTQIO commands, CS# high width has to follow "write spec" tSHSL for next instruction.
P/N: PM1561
REV. 1.5, NOV. 07, 2013
43
MX25U6435E
9-38. Read SFDP Mode (RDSFDP)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional
and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables
can be interrogated by host system software to enable adjustments needed to accommodate divergent features
from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on
CFI.
The sequence of issuing RDSFDP instruction is CS# goes low→send RDSFDP instruction (5Ah)→send 3 address
bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP operation can use CS#
to high at any time during data out.
SFDP is a JEDEC Standard, JESD216.
Figure 15. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
SCLK
Command
5Ah
24 BIT ADDRESS
SI
23 22 21
3
2
1
0
High-Z
SO
CS#
47
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
SCLK
Dummy Cycle
7
6
5
4
3
2
0
1
SI
DATA OUT 2
DATA OUT 1
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
SO
MSB
MSB
MSB
P/N: PM1561
REV. 1.5, NOV. 07, 2013
44
MX25U6435E
Table 11. Signature and Parameter Identification Data Values
Description Comment
Add (h) DW Add Data (h/b)
Data
(h)
(Byte)
(Bit)
(Note1)
00h
07:00
53h
53h
46h
44h
50h
00h
01h
01h
02h
03h
04h
05h
15:08
23:16
31:24
07:00
15:08
46h
44h
50h
00h
01h
SFDP Signature
Fixed: 50444653h
SFDP Minor Revision Number
SFDP Major Revision Number
Start from 00h
Start from 01h
This number is 0-based. Therefore,
0 indicates 1 parameter header.
Number of Parameter Headers
06h
23:16
01h
01h
Unused
07h
08h
09h
0Ah
0Bh
31:24
07:00
15:08
23:16
31:24
FFh
00h
00h
01h
09h
FFh
00h
00h
01h
09h
00h: it indicates a JEDEC specified
header.
ID number (JEDEC)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length
(in double word)
Start from 00h
Start from 01h
How many DWORDs in the
Parameter table
0Ch
0Dh
0Eh
07:00
15:08
23:16
30h
00h
00h
30h
00h
00h
First address of JEDEC Flash
Parameter table
Parameter Table Pointer (PTP)
Unused
0Fh
10h
11h
12h
13h
31:24
07:00
15:08
23:16
31:24
FFh
C2h
00h
01h
04h
FFh
C2h
00h
01h
04h
ID number
(Macronix manufacturer ID)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
it indicates Macronix manufacturer
ID
Start from 00h
Start from 01h
Parameter Table Length
(in double word)
How many DWORDs in the
Parameter table
14h
15h
16h
07:00
15:08
23:16
60h
00h
00h
60h
00h
00h
First address of Macronix Flash
Parameter table
Parameter Table Pointer (PTP)
Unused
17h
31:24
FFh
FFh
P/N: PM1561
REV. 1.5, NOV. 07, 2013
45
MX25U6435E
Table 12. Parameter Table (0): JEDEC Flash Parameter Tables
Add (h) DW Add Data (h/b)
Data
(h)
Description
Comment
(Byte)
(Bit)
(Note1)
00: Reserved, 01: 4KB erase,
10: Reserved,
11: not support 4KB erase
Block/Sector Erase sizes
Write Granularity
01:00
01b
0: 1Byte, 1: 64Byte or larger
02
03
1b
0b
Write Enable Instruction Required 0: not required
for Writing to Volatile Status
1: required 00h to be written to the
Registers
status register
30h
E5h
0: use 50h opcode,
1: use 06h opcode
Write Enable Opcode Select for
Writing to Volatile Status Registers
Note: If target flash status register is
nonvolatile, then bits 3 and 4 must
be set to 00b.
04
0b
Contains 111b and can never be
changed
Unused
07:05
111b
4KB Erase Opcode
31h
32h
33h
15:08
16
20h
0b
20h
B0h
FFh
(1-1-2) Fast Read (Note2)
0=not support 1=support
Address Bytes Number used in
addressing flash array
00: 3Byte only, 01: 3 or 4Byte,
10: 4Byte only, 11: Reserved
18:17
19
00b
0b
Double Transfer Rate (DTR)
Clocking
0=not support 1=support
(1-2-2) Fast Read
(1-4-4) Fast Read
(1-1-4) Fast Read
Unused
0=not support 1=support
0=not support 1=support
0=not support 1=support
20
21
1b
1b
22
0b
23
1b
Unused
31:24
FFh
Flash Memory Density
37h:34h 31:00
03FF FFFFh
(1-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
04:00
38h
0 0100b
states (Note3)
Clocks) not support
44h
EBh
00h
FFh
(1-4-4) Fast Read Number of
Mode Bits (Note4)
000b: Mode Bits not support
07:05
010b
EBh
(1-4-4) Fast Read Opcode
39h
3Ah
3Bh
15:08
20:16
(1-1-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
0 0000b
states
Clocks) not support
(1-1-4) Fast Read Number of
Mode Bits
000b: Mode Bits not support
23:21
31:24
000b
FFh
(1-1-4) Fast Read Opcode
P/N: PM1561
REV. 1.5, NOV. 07, 2013
46
MX25U6435E
Add (h) DW Add Data (h/b)
Data
(h)
Description
Comment
(Byte)
(Bit)
(Note1)
(1-1-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy
04:00
0 0000b
states
Clocks) not support
3Ch
00h
FFh
04h
BBh
(1-1-2) Fast Read Number of
Mode Bits
000b: Mode Bits not support
07:05
15:08
20:16
000b
FFh
(1-1-2) Fast Read Opcode
3Dh
3Eh
3Fh
(1-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy
0 0100b
states
Clocks) not support
(1-2-2) Fast Read Number of
Mode Bits
000b: Mode Bits not support
23:21
000b
(1-2-2) Fast Read Opcode
(2-2-2) Fast Read
Unused
31:24
00
BBh
0b
0=not support 1=support
0=not support 1=support
03:01
04
111b
1b
40h
FEh
(4-4-4) Fast Read
Unused
07:05
111b
FFh
FFh
Unused
43h:41h 31:08
45h:44h 15:00
FFh
FFh
Unused
(2-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy
20:16
46h
0 0000b
000b
states
Clocks) not support
00h
(2-2-2) Fast Read Number of
Mode Bits
000b: Mode Bits not support
23:21
(2-2-2) Fast Read Opcode
Unused
47h
31:24
FFh
FFh
FFh
FFh
49h:48h 15:00
(4-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
20:16
4Ah
0 0100b
states
Clocks) not support
44h
(4-4-4) Fast Read Number of
Mode Bits
000b: Mode Bits not support
23:21
010b
EBh
0Ch
20h
0Fh
52h
10h
D8h
00h
FFh
(4-4-4) Fast Read Opcode
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
53h
31:24
07:00
15:08
23:16
31:24
07:00
15:08
23:16
31:24
EBh
0Ch
20h
0Fh
52h
10h
D8h
00h
FFh
Sector/block size = 2^N bytes (Note5)
0x00b: this sector type doesn't exist
Sector Type 1 Size
Sector Type 1 erase Opcode
Sector Type 2 Size
Sector/block size = 2^N bytes
0x00b: this sector type doesn't exist
Sector Type 2 erase Opcode
Sector Type 3 Size
Sector/block size = 2^N bytes
0x00b: this sector type doesn't exist
Sector Type 3 erase Opcode
Sector Type 4 Size
Sector/block size = 2^N bytes
0x00b: this sector type doesn't exist
Sector Type 4 erase Opcode
P/N: PM1561
REV. 1.5, NOV. 07, 2013
47
MX25U6435E
Table 13. Parameter Table (1): Macronix Flash Parameter Tables
Add (h) DW Add Data (h/b)
Data
(h)
Description
Comment
2000h=2.000V
2700h=2.700V
3600h=3.600V
(Byte)
(Bit)
(Note1)
07:00
15:08
00h
20h
00h
20h
Vcc Supply Maximum Voltage
61h:60h
1650h=1.650V
2250h=2.250V
2350h=2.350V
2700h=2.700V
23:16
31:24
50h
16h
50h
16h
Vcc Supply Minimum Voltage
63h:62h
H/W Reset# pin
0=not support 1=support
00
0b
H/W Hold# pin
0=not support 1=support
0=not support 1=support
0=not support 1=support
01
02
03
0b
1b
1b
Deep Power Down Mode
S/W Reset
Reset Enable (66h) should be issued
before Reset Opcode
1001 1001b
(99h)
65h:64h
F99Ch
S/W Reset Opcode
11:04
Program Suspend/Resume
Erase Suspend/Resume
Unused
0=not support 1=support
0=not support 1=support
12
13
1b
1b
14
1b
Wrap-Around Read mode
Wrap-Around Read mode Opcode
0=not support 1=support
15
1b
66h
67h
23:16
C0h
C0h
64h
08h:support 8B wrap-around read
16h:8B&16B
32h:8B&16B&32B
Wrap-Around Read data length
31:24
64h
64h:8B&16B&32B&64B
Individual block lock
0=not support 1=support
0=Volatile 1=Nonvolatile
00
01
1b
0b
Individual block lock bit
(Volatile/Nonvolatile)
0011 0110b
(36h)
Individual block lock Opcode
09:02
10
Individual block lock Volatile
protect bit default protect status
0=protect 1=unprotect
0b
C8D9h
6Bh:68h
Secured OTP
Read Lock
Permanent Lock
Unused
0=not support 1=support
0=not support 1=support
0=not support 1=support
11
12
1b
0b
13
0b
15:14
31:16
11b
FFh
FFh
Unused
FFh
FFh
Unused
6Fh:6Ch 31:00
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Note 1: h/b is hexadecimal or binary.
Note 2: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x),
address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1), (2-2-2),
and (4-4-4)
Note 3: Wait States is required dummy clock cycles after the address bits or optional mode bits.
Note 4: Mode Bits is optional control bits that follow the address bits. These bits are driven by the system controller
if they are specified. (eg,read performance enhance toggling bits)
Note 5: 4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h
Note 6: All unused and undefined area data is blank FFh.
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10. POWER-ON STATE
The device is at the following states when power-up:
- Standby mode (please note it is not deep power-down mode)
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage until the VCC reaches the following levels:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change
during power up state. When VCC is lower than VWI (POR threshold voltage value), the internal logic is reset and
the flash device has no response to any command.
For further protection on the device, after VCC reaching the VWI level, a tPUW time delay is required before the
device is fully accessible for commands like write enable (WREN), page program (PP), quad page program (4PP),
sector erase (SE), block erase 32KB (BE32K), block erase (BE), chip erase (CE), WRSCUR and write status
register (WRSR). If the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The
write, erase, and program command should be sent after the below time delay:
- tPUW after VCC reached VWI level
- tVSL after VCC reached VCC minimum level
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL, even time of
tPUW has not passed.
Please refer to the figure of "Figure 70. Power-up Timing".
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is
recommended. (generally around 0.1uF)
- At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response
to any command. The data corruption might occur during this stage if a write, program, erase cycle is in progress.
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11. ELECTRICAL SPECIFICATIONS
10-1. Absolute Maximum Ratings
Rating
Value
Ambient Operating Temperature
Storage Temperature
Applied Input Voltage
Applied Output Voltage
VCC to Ground Potential
Industrial grade
-40°C to 85°C
-65°C to 150°C
-0.5V to VCC+0.5V
-0.5V to VCC+0.5V
-0.5V to +2.5V
NOTICE:
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device. This is stress rating only and functional operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended period may affect reliability.
2. Specifications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot to VCC+1.0V or -1.0V for period up to 20ns.
Figure 17. Maximum Positive Overshoot Waveform
Figure 16. Maximum Negative Overshoot Waveform
20ns
0V
VCC+1.0V
-1.0V
2.0V
20ns
11-1. Capacitance
TA = 25°C, f = 1.0 MHz
Symbol Parameter
Min.
Typ.
Max.
10
Unit
pF
Conditions
VIN = 0V
CIN
Input Capacitance
COUT Output Capacitance
25
pF
VOUT = 0V
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Figure 18. Input Test Waveforms and Measurement Level
Input timing reference level
0.8VCC
Output timing reference level
0.7VCC
AC
Measurement
Level
0.5VCC
0.3VCC
0.2VCC
Note: Input pulse rise and fall time are <5ns
Figure 19. Output Loading
25K ohm
DEVICE UNDER
TEST
+1.8V
CL
25K ohm
CL=30pF Including jig capacitance
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MX25U6435E
Table 14. DC Characteristics
Temperature = -40 C to 85 C, VCC = 1.65V ~ 2.0V
°
°
Symbol Parameter
Notes
Min.
Typ.
Max.
Units Test Conditions
VCC = VCC Max,
uA
ILI
Input Load Current
1
±2
VIN = VCC or GND
VCC = VCC Max,
uA
ILO
Output Leakage Current
1
1
±2
80
15
VOUT = VCC or GND
VIN = VCC or GND,
CS# = VCC
ISB1 VCC Standby Current
25
2
uA
Deep Power-down
Current
VIN = VCC or GND,
CS# = VCC
ISB2
uA
f=104MHz, (4 x I/O read)
mA SCLK=0.1VCC/0.9VCC,
SO=Open
20
15
10
f=84MHz,
mA SCLK=0.1VCC/0.9VCC,
SO=Open
ICC1 VCC Read
1
1
f=33MHz,
mA SCLK=0.1VCC/0.9VCC,
SO=Open
7
VCC Program Current
Program in Progress,
CS# = VCC
ICC2
(PP)
20
10
25
15
mA
VCC Write Status
ICC3
Program status register in
mA
Register (WRSR) Current
progress, CS#=VCC
VCC Sector/Block (32K,
ICC4 64K) Erase Current
(SE/BE/BE32K)
Erase in Progress,
CS#=VCC
1
1
20
20
25
mA
VCC Chip Erase Current
Erase in Progress,
CS#=VCC
ICC5
(CE)
25
mA
VIL
VIH
VOL
Input Low Voltage
Input High Voltage
Output Low Voltage
-0.5
0.2VCC
VCC+0.4
0.2
V
V
0.8VCC
V
V
IOL = 100uA
IOH = -100uA
VOH Output High Voltage
VCC-0.2
Notes :
1. Typical values at VCC = 1.8V, T = 25 C. These currents are valid for all product versions (package and speeds).
°
2. Typical value is calculated by simulation.
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Table 15. AC Characteristics
Temperature = -40 C to 85 C, VCC = 1.65V ~ 2.0V
°
°
Symbol Alt. Parameter
Min.
Typ.
Max.
Unit
Clock Frequency for the following instructions:
fSCLK
fC FAST_READ, RDSFDP, PP, 4PP, SE, BE, CE, DP, RES, RDP, D.C.
WREN, WRDI, RDID, RDSR, WRSR
104
MHz
fRSCLK
fTSCLK
fR Clock Frequency for READ instructions
fT Clock Frequency for 2READ instructions
fQ Clock Frequency for 4READ instructions (5)
33
84
MHz
MHz
84/104 MHz
Others (fSCLK)
Normal Read (fRSCLK)
Others (fSCLK)
4.5
13
4.5
13
0.1
0.1
4
ns
ns
ns
tCH(1)(2) tCLH Clock High Time
tCL(1)(2) tCLL Clock Low Time
Normal Read (fRSCLK)
ns
tCLCH(2)
tCHCL(2)
Clock Rise Time (3) (peak to peak)
Clock Fall Time (3) (peak to peak)
tSLCH(2) tCSS CS# Active Setup Time (relative to SCLK)
tCHSL(2) CS# Not Active Hold Time (relative to SCLK)
V/ns
V/ns
ns
4
ns
tDVCH tDSU Data In Setup Time
2
ns
tCHDX(2) tDH Data In Hold Time
3
ns
tCHSH
tSHCH
CS# Active Hold Time (relative to SCLK)
CS# Not Active Setup Time (relative to SCLK)
5
5
ns
ns
Read
Write/Erase/Program
12
30
ns
ns
tSHSL(3) tCSH CS# Deselect Time
tSHQZ(2) tDIS Output Disable Time
8
8
6
ns
ns
ns
ns
ns
ns
us
us
us
us
us
ms
ms
us
ms
ms
ms
ms
s
Loading: 30pF
Loading: 15pF
Clock Low to Output Valid
tCLQV
tV
Loading: 30pF/15pF
tHO Output Hold Time
Write Protect Setup Time
Write Protect Hold Time
tCLQX
tWHSL
tSHWL
tDP(2)
tRES1(2)
tRES2(2)
tRCR
tRCP
tRCE
tW
1
20
100
CS# High to Deep Power-down Mode
CS# High to Standby Mode without Electronic Signature Read
CS# High to Standby Mode with Electronic Signature Read
Recovery Time from Read
Recovery Time from Program
Recovery Time from Erase
10
10
10
20
20
12
40
30
3
200
1000
2000
80
Write Status Register Cycle Time
Byte-Program
tBP
10
1.2
45
250
500
36
tPP
Page Program Cycle Time
tSE
Sector Erase Cycle Time
tBE32
tBE
tCE
Block Erase (32KB) Cycle Time
Block Erase (64KB) Cycle Time
Chip Erase Cycle Time
Notes:
1. tCH + tCL must be greater than or equal to 1/ Frequency.
2. Value guaranteed by characterization, not 100% tested in production.
3. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
4. Test condition is shown as "Figure 18. Input Test Waveforms and Measurement Level" and "Figure 19. Output
Loading"
5. When dummy cycle=4 (In both QPI & SPI mode), clock rate=84MHz; when dummy cycle=6 (In both QPI & SPI
mode), clock rate=104MHz.
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12. Timing Analysis
Figure 20. Serial Input Timing
tSHSL
tSHCH
tCHCL
CS#
tCHSL
tSLCH
tCHSH
SCLK
tDVCH
tCHDX
tCLCH
MSB
LSB
SI
High-Z
SO
Figure 21. Output Timing
CS#
tCH
SCLK
tCLQV
tCLQV
tCL
tSHQZ
tCLQX
SO
tCLQX
LSB
ADDR.LSB IN
SI
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Figure 22. WP# Setup Timing and Hold Timing during WRSR when SRWD=1
WP#
CS#
tSHWL
tWHSL
0
1
2
3
4
5
6
7
8
9
10 11 12
13 14
15
SCLK
01h
SI
High-Z
SO
Figure 23. Write Enable (WREN) Sequence (Command 06) (SPI Mode)
CS#
0
1
2
3
4
5
6
7
Mode 3
Mode 0
SCLK
Command
06h
SI
High-Z
SO
Figure 24. Write Enable (WREN) Sequence (Command 06) (QPI Mode)
CS#
0
1
Mode 3
Mode 0
SCLK
Command
SIO[3:0]
06h
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Figure 25. Write Disable (WRDI) Sequence (Command 04) (SPI Mode)
CS#
Mode 3
Mode 0
0
1
2
3
4
5
6
7
SCLK
Command
04h
SI
High-Z
SO
Figure 26. Write Disable (WRDI) Sequence (Command 04) (QPI Mode)
CS#
0
1
Mode 3
Mode 0
SCLK
Command
SIO[3:0]
04h
Figure 27. Read Identification (RDID) Sequence (Command 9F) (SPI mode only)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
28 29 30 31
Mode 3
Mode 0
SCLK
SI
Command
9Fh
Manufacturer Identification
Device Identification
High-Z
SO
7
6
5
3
2
1
0
15 14 13
MSB
3
2
1
0
MSB
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Figure 28. Read Status Register (RDSR) Sequence (Command 05) (SPI Mode)
CS#
SCLK
SI
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Mode 3
Mode 0
command
05h
Status Register Out
Status Register Out
High-Z
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
Figure 29. Read Status Register (RDSR) Sequence (Command 05) (QPI Mode)
CS#
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
N
SCLK
SIO[3:0]
05h
H0 L0 H0 L0 H0 L0
H0 L0
MSB
LSB
Status Byte Status Byte Status Byte
Status Byte
Figure 30. Write Status Register (WRSR) Sequence (Command 01) (SPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Mode 3
Mode 0
SCLK
command
01h
Status
Register In
SI
7
6
5
4
3
2
0
1
MSB
High-Z
SO
Note : Also supported in QPI mode with command and subsequent input/output in Quad I/O mode.
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Figure 31. Write Status Register (WRSR) Sequence (Command 01) (QPI Mode)
CS#
Mode 3
Mode 0
SCLK
4
5
0
1
C4, C0
C5, C1
SIO0
SIO1
2
3
C6, C2
C7, C3
6
7
SIO2
SIO3
Status
Register IN
Command
Figure 32. Read Data Bytes (READ) Sequence (Command 03) (SPI Mode only) (33MHz)
CS#
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
command
03h
24-Bit Address
23 22 21
MSB
3
2
1
0
SI
Data Out 1
Data Out 2
High-Z
2
7
6
5
4
3
1
7
0
SO
MSB
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Figure 33. Read at Higher Speed (FAST_READ) Sequence (Command 0B) (SPI Mode) (104MHz)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
Mode 3
Mode 0
SCLK
Command
0Bh
24-Bit Address
SI
23 22 21
3
2
1
0
High-Z
SO
CS#
47
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
SCLK
Configurable
Dummy Cycle
7
6
5
4
3
2
0
1
SI
DATA OUT 2
DATA OUT 1
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
SO
MSB
MSB
MSB
Figure 34. Read at Higher Speed (FAST_READ) Sequence (Command 0B) (QPI Mode) (84MHz)
CS#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Mode 3
Mode 0
SCLK
Command
0Bh
SIO(3:0)
X
X
H0 L0 H1 L1
MSB LSB MSB LSB
Data Out 1 Data Out 2
A5 A4 A3 A2 A1 A0
24-Bit Address
X
X
Data In
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Figure 35. 2 x I/O Read Mode Sequence (Command BB) (SPI Mode only) (84MHz)
CS#
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11
18 19 20 21 22 23 24 25 26 27
SCLK
4 dummy
cycle
8 Bit Instruction
12-Bit Address
Data Output
data
address
bit22, bit20, bit18...bit0
BBh
SI/SIO0
bit6, bit4, bit2...bit0, bit6, bit4....
High Impedance
address
bit23, bit21, bit19...bit1
data
SO/SIO1
bit7, bit5, bit3...bit1, bit7, bit5....
Figure 36. 4 x I/O Read Mode Sequence (Command EB) (SPI Mode) (104MHz)
CS#
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
n
SCLK
4 dummy
cycles
8 Bit Instruction
6 Address cycles
Data Output
Performance
enhance
indicator (Note)
data
address
EBh
P4 P0
P5 P1
P6 P2
P7 P3
SI/SIO0
bit4, bit0, bit4....
bit20, bit16..bit0
High Impedance
High Impedance
High Impedance
address
bit21, bit17..bit1
data
bit5 bit1, bit5....
SO/SIO1
WP#/SIO2
NC/SIO3
address
bit22, bit18..bit2
data
bit6 bit2, bit6....
address
bit23, bit19..bit3
data
bit7 bit3, bit7....
Note:
1. Also supported in QPI mode with command and subsequent input/output in Quad I/O mode and runs at 104MHz.
2. Hi-impedance is inhibited for the two clock cycles.
3. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited.
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Figure 37. 4 x I/O Read enhance performance Mode Sequence (Command EB) (SPI Mode) (104MHz)
CS#
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
n
SCLK
4 dummy
cycles
8 Bit Instruction
6 Address cycles
Data Output
Performance
enhance
indicator (Note)
data
address
P4 P0
P5 P1
P6 P2
P7 P3
EBh
SI/SIO0
bit4, bit0, bit4....
bit20, bit16..bit0
High Impedance
High Impedance
High Impedance
address
bit21, bit17..bit1
data
bit5 bit1, bit5....
SO/SIO1
WP#/SIO2
NC/SIO3
address
bit22, bit18..bit2
data
bit6 bit2, bit6....
address
bit23, bit19..bit3
data
bit7 bit3, bit7....
CS#
n+1
...........
n+7......n+9 ........... n+13
...........
SCLK
4 dummy
cycles
6 Address cycles
Data Output
Performance
enhance
indicator (Note)
data
address
P4 P0
P5 P1
P6 P2
P7 P3
SI/SIO0
bit4, bit0, bit4....
bit20, bit16..bit0
address
bit21, bit17..bit1
data
bit5 bit1, bit5....
SO/SIO1
WP#/SIO2
NC/SIO3
address
bit22, bit18..bit2
data
bit6 bit2, bit6....
address
bit23, bit19..bit3
data
bit7 bit3, bit7....
Note: Performance enhance mode, if P7≠P3 & P6≠P2 & P5≠P1 & P4≠P0 (Toggling), ex: A5, 5A, 0F, if not using
performance enhance recommend to keep 1 or 0 in performance enhance indicator.
Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF
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Figure 38. 4 x I/O Read enhance performance Mode Sequence (Command EB) (QPI Mode) (104MHz)
CS#
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
SCLK
EBh
SIO[3:0]
X
X
X
X
H0 L0 H1 L1
MSB LSB MSB LSB
A5 A4 A3 A2 A1 A0
P(7:4)P(3:0)
Data In
4 dummy
cycles
Data Out
performance
enhance
indicator
CS#
SCLK
n+1 .............
Mode 0
SIO[3:0]
X
X
X
X
H0 L0 H1 L1
MSB LSB MSB LSB
A5 A4 A3 A2 A1 A0
P(7:4)P(3:0)
6 Address cycles
4 dummy
cycles
Data Out
performance
enhance
indicator
Figure 39. Page Program (PP) Sequence (Command 02) (SPI Mode)
CS#
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
02h
24-Bit Address
Data Byte 1
23 22 21
MSB
3
2
1
0
7
6
5
4
3
2
0
1
SI
MSB
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
Data Byte 2
Data Byte 3
Data Byte 256
7
6
5
4
3
2
0
7
6
5
4
3
2
0
7
6
5
4
3
2
0
1
1
1
SI
MSB
MSB
MSB
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Figure 40. Page Program (PP) Sequence (Command 02) (QPI Mode)
CS#
Mode 3
Mode 0
0
1
2
SCLK
24-Bit Address
Command
02h
H255 L255
SIO[3:0]
H0 L0 H1 L1 H2 L2 H3 L3
Data Byte Data Byte Data Byte Data Byte
A5 A4 A3 A2 A1 A0
......
Data Byte
256
Data In
1
2
3
4
Figure 41. 4 x I/O Page Program (4PP) Sequence (Command 38) (SPI Mode only)
CS#
10 11 12 13 14 15 16 17 18 19 20 21
Data Data Data Data
0
1
2
3
4
5
6
7
8
9
Mode 3
Mode 0
SCLK
Command
38h
6 Address cycle
Byte 1 Byte 2 Byte 3 Byte 4
16 12
8
9
4
0
20
4
0
4
0
4
0
4
0
SI/SIO0
21 17 13
5
6
7
1
2
3
SO/SIO1
WP#/SIO2
NC/SIO3
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
22 18 14 10
23 19 15 11
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Figure 42. Sector Erase (SE) Sequence (Command 20) (SPI Mode)
CS#
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
20h
24-Bit Address
SI
23 22
MSB
2
1
0
Figure 43. Sector Erase (SE) Sequence (Command 20) (QPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
SCLK
Mode 0
24-Bit Address
Command
SIO[3:0]
20h A5 A4 A3 A2 A1 A0
MSB LSB
Figure 44. Block Erase 32KB (BE32K) Sequence (Command 52) (SPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
Mode 3
Mode 0
SCLK
Command
52h
24-Bit Address
SI
23 22
MSB
2
0
1
Figure 45. Block Erase 32KB (BE32K) Sequence (Command 52) (QPI Mode)
CS#
Mode 3
Mode 0
0
1
2
3
4
5
6
7
SCLK
24-Bit Address
Command
SIO[3:0]
52h A5 A4 A3 A2 A1 A0
MSB
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MX25U6435E
Figure 46. Block Erase (BE) Sequence (Command D8) (SPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
Mode 3
Mode 0
SCLK
24-Bit Address
Command
D8h
SI
23 22
MSB
2
0
1
Figure 47. Block Erase (BE) Sequence (Command D8) (QPI Mode)
CS#
Mode 3
Mode 0
0
1
2
3
4
5
6
7
SCLK
24-Bit Address
Command
SIO[3:0]
D8h A5 A4 A3 A2 A1 A0
MSB
Figure 48. Chip Erase (CE) Sequence (Command 60 or C7) (SPI Mode)
CS#
Mode 3
Mode 0
0
1
2
3
4
5
6
7
SCLK
SI
Command
60h or C7h
Figure 49. Chip Erase (CE) Sequence (Command 60 or C7) (QPI Mode)
CS#
0
1
Mode 3
Mode 0
SCLK
Command
60h or C7h
SIO[3:0]
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MX25U6435E
Figure 50. Deep Power-down (DP) Sequence (Command B9) (SPI Mode)
CS#
t
DP
0
1
2
3
4
5
6
7
Mode 3
Mode 0
SCLK
SI
Command
B9h
Stand-by Mode
Deep Power-down Mode
Figure 51. Deep Power-down (DP) Sequence (Command B9) (QPI Mode)
CS#
t
DP
Mode 3
Mode 0
0
1
SCLK
Command
SIO[3:0]
B9h
Stand-by Mode
Deep Power-down Mode
Figure 52. RDP and Read Electronic Signature (RES) Sequence (Command AB) (SPI Mode)
CS#
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38
SCLK
Command
ABh
t
3 Dummy Bytes
RES2
SI
23 22 21
MSB
3
2
1
0
Electronic Signature Out
High-Z
7
6
5
4
3
2
0
1
SO
MSB
Deep Power-down Mode
Stand-by Mode
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MX25U6435E
Figure 53. Release from Deep Power-down (RDP) Sequence (Command AB) (SPI Mode)
CS#
t
RES1
0
1
2
3
4
5
6
7
Mode 3
Mode 0
SCLK
Command
ABh
SI
High-Z
SO
Deep Power-down Mode
Stand-by Mode
Figure 54. Release from Deep Power-down (RDP) Sequence (Command AB) (QPI Mode)
CS#
t
RES1
Mode 3
Mode 0
0
1
SCLK
Command
SIO[3:0]
ABh
Deep Power-down Mode
Stand-by Mode
P/N: PM1561
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MX25U6435E
Figure 55. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90) (SPI Mode only)
CS#
0
1
2
3
4
5
6
7
8
9 10
Mode 3
Mode 0
SCLK
Command
90h
2 Dummy Bytes
SI
15 14 13
3
2
1
0
High-Z
SO
CS#
47
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
SCLK
ADD (1)
7
6
5
4
3
2
0
1
SI
Manufacturer ID
Device ID
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
SO
MSB
MSB
MSB
Notes:
(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first.
(2) Instruction is either 90(hex).
P/N: PM1561
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MX25U6435E
Figure 56. Read Security Register (RDSCUR) Sequence (Command 2B) (SPI Mode)
CS#
SCLK
SI
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Mode 3
Mode 0
command
2B
Security Register Out
Security Register Out
High-Z
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
Figure 57. Read Security Register (RDSCUR) Sequence (Command 2B) (QPI Mode)
CS#
0
1
2
3
4
5
6
7
8
N
Mode 3
Mode 0
SCLK
SIO[3:0]
2B
H0 L0 H0 L0 H0 L0
H0 L0
MSB
LSB
Status Byte Status Byte Status Byte
Status Byte
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MX25U6435E
Figure 58. Write Security Register (WRSCUR) Sequence (Command 2F) (SPI Mode)
CS#
0
1
2
3
4
5
6
7
Mode 3
Mode 0
SCLK
Command
2F
SI
Figure 59. Write Security Register (WRSCUR) Sequence (Command 2F) (QPI Mode)
CS#
0
1
Mode 3
Mode 0
SCLK
Command
SIO[3:0]
2F
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MX25U6435E
Figure 60. Word Read Quad I/O (W4READ) Sequence (Command E7) (SPI Mode only, 84MHz)
CS#
Mode 3
０
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Mode ０
Instruction (E7h)
IO Switches from Input to Output
4
0
4
5
6
0
1
2
4
5
6
0
1
2
4
5
6
0
1
2
4
5
6
0
1
2
4
5
6
0
1
2
4
5
6
IO0
IO1
IO2
5
6
1
2
7
3
7
3
7
3
7
3
7
3
7
3
7
IO3
A23-16 A15-8 A7-0
Dummy
Byte 1 Byte 2 Byte 3
Figure 61. Performance Enhance Mode Reset for Fast Read Quad I/O (SPI Mode)
Mode Bit Reset
for Quad I/O
CS#
Mode 3
Mode 3
Mode ０
０
1
2
3
4
5
6
7
SCLK
Mode ０
FFh
SIO0
SIO1
SIO2
Don’t Care
Don’t Care
Don’t Care
SIO3
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MX25U6435E
Figure 62. Performance Enhance Mode Reset for Fast Read Quad I/O (QPI Mode)
Mode Bit Reset
for Quad I/O
CS#
Mode 3
Mode 3
０
1
2
3
4
5
6
7
SCLK
Mode ０
Mode ０
FFFFFFFFh
SIO[3:0]
Figure 63. Reset Sequence (SPI mode)
CS#
Mode 3
Mode 3
Mode 0
SCLK
Mode 0
Command
Command
99h
66h
SIO0
Figure 64. Reset Sequence (QPI mode)
tSHSL
CS#
Mode 3
MODE 3
MODE 0
Mode 3
Mode 0
SCLK
Mode 0
Command
Command
SIO[3:0]
66h
99h
Figure 65. Enable Quad I/O Sequence
CS#
0
1
Mode 3
2
3
4
5
6
7
SCLK
Mode 0
35h
SIO0
SIO[3:1]
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MX25U6435E
Figure 66. Suspend to Read Latency
Program latency : 20us
Erase latency: 20us
Suspend Command
Read Command
CS#
[B0]
Figure 67. Resume to Read Latency
TSE/TBE/TPP
Resume Command
Read Command
CS#
[30]
Figure 68. Resume to Suspend Latency
1ms
Suspend
Command
[B0]
Resume Command
CS#
[30]
Figure 69. Software Reset Recovery
Stand-by Mode
66
99
CS#
tRCR
tRCP
tRCE
Mode
tRCR: 20us (Recovery Time from Read)
tRCP: 20us (Recovery Time from Program)
tRCE: 12ms (Recovery Time from Erase)
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MX25U6435E
Figure 70. Power-up Timing
V
CC
V
(max)
CC
Program, Erase and Write Commands are Ignored
Chip Selection is Not Allowed
V
(min)
CC
tVSL
Read Command is
Device is fully
accessible
Reset State
of the
Flash
allowed
V
WI
tPUW
time
Note: VCC (max.) is 2.0V and VCC (min.) is 1.65V.
Table 16. Power-Up Timing and VWI Threshold
Symbol
tVSL(1)
tPUW(1)
VWI(1)
Parameter
Min.
300
1
Max.
Unit
us
ms
V
VCC(min) to CS# low (VCC Rise Time)
Time delay to Write instruction
Command Inhibit Voltage
10
1.4
1.0
Note: 1. These parameters are characterized only.
12-1. Initial Delivery State
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status
Register contains 00h (all Status Register bits are 0).
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MX25U6435E
13. OPERATING CONDITIONS
At Device Power-Up and Power-Down
AC timing illustrated in "Figure 71. AC Timing at Device Power-Up" and "Figure 72. Power-Down Sequence" are
for the supply voltages and the control signals at device power-up and power-down. If the timing in the figures is
ignored, the device will not operate correctly.
During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be
selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.
Figure 71. AC Timing at Device Power-Up
VCC(min)
VCC
GND
tVR
tSHSL
CS#
tSHCH
tSLCH
tCHSL
tCHSH
SCLK
tDVCH
tCHCL
tCHDX
tCLCH
MSB IN
LSB IN
SI
High Impedance
SO
Symbol
tVR
Parameter
VCC Rise Time
Notes
Min.
20
Max.
500000
Unit
us/V
1
Notes :
1. Sampled, not 100% tested.
2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to
"Table 15. AC Characteristics".
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MX25U6435E
Figure 72. Power-Down Sequence
During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.
VCC
CS#
SCLK
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MX25U6435E
14. ERASE AND PROGRAMMING PERFORMANCE
Parameter
Min.
Typ. (1)
Max. (2)
40
Unit
ms
Write Status Register Cycle Time
Sector Erase Cycle Time (4KB)
Block Erase Cycle Time (32KB)
Block Erase Cycle Time (64KB)
Chip Erase Cycle Time
45
250
200
1000
2000
80
ms
ms
500
ms
36
s
Byte Program Time (via page program command)
Page Program Time
10
30
us
1.2
3
ms
Erase/Program Cycle
100,000
cycles
Note:
1. Typical program and erase time assumes the following conditions: 25 C, 1.8V, and checkerboard pattern.
°
2. Under worst conditions of 85 C and 1.65V.
°
3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming
command.
4. The maximum chip programming time is evaluated under the worst conditions of 0C, VCC=1.8V, and 100K cycle
with 90% confidence level.
15. DATA RETENTION
PARAMETER
Condition
Min.
Max.
UNIT
Data retention
55˚C
20
years
16. LATCH-UP CHARACTERISTICS
Min.
Max.
Input Voltage with respect to GND on all power pins, SI, CS#
Input Voltage with respect to GND on SO
Current
-1.0V
-1.0V
2 VCCmax
VCC + 1.0V
+100mA
-100mA
Includes all pins except VCC. Test conditions: VCC = 1.8V, one pin at a time.
P/N: PM1561
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MX25U6435E
17. ORDERING INFORMATION
Part No.
Clock (MHz)
104
Temperature
Package
8-WSON
(6x5mm)
Remark
MX25U6435EZNI-10G
-40 C~85 C
°
°
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MX25U6435E
18. PART NAME DESCRIPTION
MX 25 U 6435E ZN
I
10 G
OPTION:
G: RoHS Compliant and Halogen-free
SPEED:
10: 104MHz
TEMPERATURE RANGE:
I: Industrial (-40°C to 85°C)
PACKAGE:
ZN: 8-WSON
DENSITY & MODE:
6435E: 64Mb
TYPE:
U: 1.8V
DEVICE:
25: Serial Flash
P/N: PM1561
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19. PACKAGE INFORMATION
P/N: PM1561
REV. 1.5, NOV. 07, 2013
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20. REVISION HISTORY
Revision No. Description
Page
P69
P47
P6
Date
JAN/19/2010
0.01
1. Modified ordering information
2. Deleted tREHZ
3. Changed title from "Advanced Information" to "Preliminary"
1. Modified Clock rate
1.0
P6,9,17,18,27, APR/26/2010
P46,47,53~56,
P63,70,71
2. Modified Sector Erase Cycle Time from 300ms(max.)
P6,47,69
to 200ms(max.)
3. Modified Block Erase Cycle Time (32KB) from 250~300ms(typ.) P6,47,69
to 250ms(typ.)
4. Modified Byte Program Time from 8~15us(typ.) to 8us(typ.)
5. Modified Chip Erase Cycle Time from 32s(typ.) to 36s(typ.)
6. Modified Page Program Time from 1.4ms(typ.)/5ms(max.) to
1.2ms(typ.)/3ms(max.)
P47,69
P6,47,69
P47,69
7. Modified Standby current from 40uA(typ.) to 30uA(typ.)
8. Modified Table 9. DC CHARACTERISTICS
9. Modified Figure 40. AC Timing at Device Power-Up
10. Added Figure 41. Power-Down Sequence
11. Changed the naming "CFI mode" as "SFDP mode"
12. Removed "Preliminary"
P6,46
P46
P67
P68
P15,39
P6
1.1
1.2
1. Removed SFDP sequence description & content table
1. Removed the QPI support in RES command
2. Modified tCH/tCL(4PP and Normal Read) from 15ns to 4.5ns
3. Modified CIN/COUT (max.) from 6pF/8pF to 10pF/25pF
4. Modified Write Protection Selection (WPSEL) description
5. Modified tSLCH, tCHSL & tCHDX
P15,19,39
P18,31,60
P47
P44
P35,36
P47
JUL/06/2010
SEP/29/2011
6. Added RDSCUR & WRSCUR waveforms
7. Revised Ordering Information table
P63,64
P72
1.3
1. Added Read SFDP (RDSFDP) Mode
P7,14,17,
FEB/10/2012
P43~48, 53
MAY/03/2013
1.4
1. Modified Data Retention value
P6,78
P54
P73
P6,53,54
P6,78
P51
2. Modified tCH, tCL, tSHSL, tCLQX in AC Characteristics Table
3. Correct Symbol in Reset Sequence (QPI mode) Figure
1. Updated parameters for DC/AC Characteristics
2. Updated Erase and Programming Performance
3. Modified VCC to Ground Potential
1.5
NOV/07/2013
P/N: PM1561
REV. 1.5, NOV. 07, 2013
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MX25U6435E
Except for customized products which has been expressly identified in the applicable agreement, Macronix's
products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or
household applications only, and not for use in any applications which may, directly or indirectly, cause death,
personal injury, or severe property damages. In the event Macronix products are used in contradicted to their
target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its
actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or
distributors shall be released from any and all liability arisen therefrom.
Copyright© Macronix International Co., Ltd. 2009~2013. All rights reserved, including the trademarks and
tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit,
NBiit, Macronix NBit, eLiteFlash, HybridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC,
Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich Audio, Rich Book, Rich TV, and FitCAM. The names
and brands of third party referred thereto (if any) are for identification purposes only.
For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
83
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