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MX27C4111PC-12 [Macronix]

4M-BIT [512K x8/256K x16] CMOS EPROM WITH PAGE MODE; 4M- BIT [ 512K ×8 / 256K X16 ] CMOS EPROM配页模式
MX27C4111PC-12
型号： MX27C4111PC-12
厂家： MACRONIX INTERNATIONAL    MACRONIX INTERNATIONAL
描述：

4M-BIT [512K x8/256K x16] CMOS EPROM WITH PAGE MODE
4M- BIT [ 512K ×8 / 256K X16 ] CMOS EPROM配页模式

可编程只读存储器 电动程控只读存储器
文件： 总15页 (文件大小：499K)
中文：  中文翻译
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PRELIMINARY  
MX27C4111  
4M-BIT [512K x8/256K x16] CMOS EPROM  
WITH PAGE MODE  
FEATURES  
• Completely TTL compatible  
• Operating current: 60mA  
• Standby current: 100uA  
• With Page Mode function, 8-word/16-byte page  
• 512K x 8 or 256K x 16 organization  
• +12.5V programming voltage  
• Package type:  
- 40 pin plastic DIP  
- 40 pin SOP  
• Fast access time: 90/100/120/150 ns  
• Page mode access time 50/60/75 ns  
• Totally static operation  
GENERAL DESCRIPTION  
The MX27C4111 is a 4M-bit, One Time Programmable  
Read Only Memory with page mode. It is organized as  
512K x 8 or 256K x 16, operates from a single + 5 volt  
supply, has a static standby mode, and features fast  
single address location programming. All programming  
signals are TTL levels, requiring a single pulse. For  
programmingoutsidefromthesystem,existingEPROM  
programmers may be used. The MX27C4111 supports  
aintelligentfastprogrammingalgorithmwhichcanresult  
in programming time of less than two minutes.  
MX27C4111 provides Page Read Access Mode which  
can greatly reduce the read access time. Normal read  
access time and Page Mode read access time is as fast  
as 90/50ns. It is designed to be compatible with all  
microprocessors and similar applications in which high  
perofmrance, large bit storage and simple interfacing  
are important design considerations.  
This EPROM is packaged in industry standard 40 pin  
dual-in-line packages and 40 pin SOP packages.  
PIN CONFIGURATIONS  
PDIP/SOP  
BLOCK DIAGRAM  
CE  
Q0~Q14  
CONTROL  
LOGIC  
OUTPUT  
OE  
A17  
A7  
1
2
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
A8  
A9  
Q15/A-1  
BUFFERS  
BYTE/VPP  
A6  
3
A10  
A11  
A12  
A13  
A14  
A15  
A16  
BYTE/VPP  
GND  
Q15/A-1  
Q7  
Q14  
Q6  
Q13  
Q5  
Q12  
Q4  
VCC  
A5  
4
A4  
5
A3  
6
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Y-DECODER  
X-DECODER  
Y-SELECT  
A2  
7
A1  
8
A0  
9
CE  
GND  
OE  
Q0  
Q8  
Q1  
Q9  
Q2  
Q10  
Q3  
Q11  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
A0~A17  
4M BIT  
CELL  
ADDRESS  
INPUTS  
MAXTRIX  
VCC  
GND  
P/N: PM0239  
REV. 2.6, AUG. 20, 2001  
1
MX27C4111  
PIN DESCRIPTION  
SYMBOL PIN NAME  
A0~A17  
Q0~Q14  
CE  
Address Input  
Data Input/Output  
Chip Enable Input  
Output Enable Input  
OE  
BYTE/VPP Word/Byte Selection/Program Supply  
Voltage  
Q15/A-1  
Q15(Word mode)/LSB addr. (Byte  
mode)  
VCC  
GND  
Power Supply Pin (+5V)  
Ground Pin  
TRUTH TABLE OF BYTE FUNCTION  
BYTE MODE(BYTE = GND)  
CE  
H
OE  
X
Q15/A-1  
MODE  
Q0-Q7  
High Z  
High Z  
DOUT  
SUPPLY CURRENT  
Standby(ICC2)  
X
Non selected  
Non selected  
Selected  
L
H
X
Operating(ICC1)  
Operating(ICC1)  
L
L
A-1 input  
WORD MODE(BYTE = VCC)  
CE  
H
OE  
X
Q15/A-1  
High Z  
High Z  
DOUT  
MODE  
Q0-Q14  
High Z  
High Z  
DOUT  
SUPPLY CURRENT  
Standby(ICC2)  
Non selected  
Non selected  
Selected  
L
H
Operating(ICC1)  
Operating(ICC1)  
L
L
NOTE : X = H or L  
P/N: PM0239  
REV. 2.6, AUG. 20, 2001  
2
MX27C4111  
AUTO IDENTIFY MODE  
FUNCTIONAL DESCRIPTION  
Theautoidentifymodeallowsthereadingoutofabinary  
code from an EPROM that will identify its manufacturer  
and device type. This mode is intended for use by  
programming equipment for the purpose of  
automatically matching the device to be programmed  
with its corresponding programming algorithm. This  
mode is functional in the 25°C ± 5°C ambient  
temperature range that is required when programming  
the MX27C4111.  
THE PROGRAMMING OF THE MX27C4111  
When theMX27C4111 isdelivered, or it iserased, the  
chip hasall4Mbitsinthe"ONE"orHIGHstate."ZEROs"  
are loaded into the MX27C4111 through the procedure  
of programming.  
Forprogramming,thedatatobeprogrammedisapplied  
with 16 bits in parallel to the data pins.  
To activate this mode, the programming equipment  
mustforce12.0±0.5VonaddresslineA9ofthedevice.  
Two identifier bytes may then be sequenced from the  
device outputs by toggling address line A0 from VIL to  
VIH. All other address lines must be held at VIL during  
auto identify mode.  
VCC must be applied simultaneously or before VPP,  
and removed simultaneously or after VPP. When  
programming an MXIC EPROM, a 0.1uF capacitor is  
required across VPP and ground to suppress spurious  
voltage transients which may damage the device.  
Byte 0 ( A0 = VIL) represents the manufacturer code,  
andbyte1(A0=VIH),thedeviceidentifiercode. Forthe  
MX27C4111, these two identifier bytes are given in the  
Mode Select Table. All identifiers for manufacturer and  
device codes will possess odd parity, with the MSB  
(Q15) defined as the parity bit.  
FAST PROGRAMMING  
Thedeviceissetupinthefastprogrammingmodewhen  
the programming voltage VPP = 12.75V is applied, with  
VCC = 6.25 V and OE = VIH (Algorithm is shown in  
Figure 1). The programming is achieved by applying a  
single TTL low level 100us pulse to the CE input after  
addresses and data line are stable. If the data is not  
verified, an additional pulse is applied for a maximum of  
25 pulses. This process is repeated while sequencing  
through each address of the device. When the  
programmingmodeiscompleted,thedatainalladdress  
is verified at VCC = VPP = 5V ± 10%.  
READ MODE  
The MX27C4111 provides page mode with 8 words/16  
bytes per page. In order to get the benefit of fast page  
read, the user should keep chip enable(CE) low and  
toggle address A0~A2 in word mode or A-1~A2 in byte  
mode. Page Read access time(tPA) is equal to the  
delay from address stable to data output. It is twice as  
fast as normal tACC and is highly recommended.  
PROGRAM INHIBIT MODE  
Programming of multiple MX27C4111's in parallel with  
different data is also easily accomplished by using the  
Program Inhibit Mode. Except for CE and OE, all like  
inputs of the parallel MX27C4111 may be common. A  
TTL low-level program pulse applied to an MX27C4111  
CE input with VPP = 12.5 ± 0.5 V will program the  
MX27C4111. A high-level CE input inhibits the other  
MX27C4111s from being programmed.  
WORD-WIDE MODE  
With BYTE/VPP at VCC ± 0.2V outputs Q0-7 present  
data Q0-7 and outputs Q8-15 present data Q8-15, after  
CE and OE are appropriately enabled.  
BYTE-WIDE MODE  
PROGRAM VERIFY MODE  
With BYTE/VPP at GND ± 0.2V, outputs Q8-15 are tri-  
stated. IfQ15/A-1=VIH, outputsQ0-7presentdatabits  
Q8-15. If Q15/A-1 = VIL, outputs Q0-7 present data bits  
Q0-7.  
Verification should be performed on the programmed  
bits to determine that they were correctly programmed.  
TheverificationshouldbeperformedwithOEatVIL, CE  
at VIH, and VPP at its programming voltage.  
P/N: PM0239  
REV. 2.6, AUG. 20, 2001  
3
MX27C4111  
STANDBY MODE  
connected to the READ line from the system control  
bus. This assures that all deselected memory devices  
areintheirlow-powerstandbymodeandthattheoutput  
pins are only active when data is desired from a  
particular memory device.  
The MX27C4111 has a CMOS standby mode which  
reduces the maximum VCC current to 100 uA. It is  
placed in CMOS standby when CE is at VCC ± 0.3 V.  
The MX27C4111 also has a TTL-standby mode which  
reduces the maximum VCC current to 1.5 mA. It is  
placed in TTL-standby when CE is at VIH. When in  
standby mode, the outputs are in a high-impedance  
state, independent of the OE input.  
SYSTEM CONSIDERATIONS  
During the switch between active and standby  
conditions, transientcurrentpeaksareproducedonthe  
rising and falling edges of Chip Enable. The magnitude  
of these transient current peaks is dependent on the  
outputcapacitanceloadingofthedevice. Ataminimum,  
a0.1uFceramiccapacitor(highfrequency,lowinherent  
inductance) should be used on each device between  
Vcc and GND to minimize transient effects. In addition,  
to overcome the voltage drop caused by the inductive  
effects of the printed circuit board traces on EPROM  
arrays, a 4.7 uF bulk electrolytic capacitor should be  
used between VCC and GND for each eight devices.  
The location of the capacitor should be close to where  
the power supply is connected to the array.  
TWO-LINE OUTPUT CONTROL FUNCTION  
To accommodate multiple memory connections, a two-  
line control function is provided to allow for:  
1. Low memory power dissipation,  
2. Assurance that output bus contention will not  
occur.  
It is recommended that CE be decoded and used as the  
primary device-selecting function, while OE be made a  
common connection to all devices in the array and  
MODE SELECT TABLE  
BYTE/  
MODE  
CE  
OE  
VIL  
VIL  
VIL  
VIH  
X
A9  
X
A0  
X
Q15/A-1  
Q15 Out  
VIH  
VPP(5)  
VCC  
GND  
GND  
X
Q8-14  
Q0-7  
Read (Word)  
VIL  
VIL  
VIL  
VIL  
VIH  
VIL  
VIH  
VIH  
VIL  
VIL  
Q8-14 Out  
High Z  
High Z  
High Z  
High Z  
Q8-14 In  
Q8-14 Out  
High Z  
00H  
Q0-7 Out  
Q8-15 Out  
Q0-7 Out  
High Z  
High Z  
Q0-7 In  
Q0-7 Out  
High Z  
C2H  
Read (Upper Byte)  
Read (Lower Byte)  
Output Disable  
Standby  
X
X
X
X
VIL  
X
X
High Z  
High Z  
Q15 In  
Q5 Out  
High Z  
0B  
X
X
X
Program  
VIH  
VIL  
VIH  
VIL  
VIL  
X
X
VPP  
VPP  
VPP  
VCC  
VCC  
Program Verify  
Program Inhibit  
Manufacturer Code(3)  
Device Code(3)  
X
X
X
X
VH  
VH  
VIL  
VIH  
1B  
38H  
00H  
NOTES:  
1.VH = 12.0V ± 0.5V  
5.BYTE/VPP is intended for operation under DC  
Voltage conditions only.  
2.X = Either VIH or VIL  
3.A1 - A8, A10 - A17 = VIL (For auto select)  
6.Manufacture code = 00C2H  
Device code = B800H  
4.See DC Programming Characteristics for VPP  
voltages.  
P/N: PM0239  
REV. 2.6, AUG. 20, 2001  
4
MX27C4111  
FIGURE 1. FAST PROGRAMMING FLOW CHART  
START  
ADDRESS = FIRST LOCATION  
VCC = 6.25V  
VPP = 12.75V  
X = 0  
PROGRAM ONE 50us PULSE  
INCREMENT X  
INTERACTIVE  
SECTION  
YES  
X = 25?  
NO  
FAIL  
VERIFY BYTE  
?
PASS  
NO  
LAST ADDRESS  
INCREMENT ADDRESS  
FAIL  
YES  
VCC = VPP = 5.25V  
VERIFY SECTION  
FAIL  
DEVICE FAILED  
VERIFY ALL BYTES  
?
PASS  
DEVICE PASSED  
P/N: PM0239  
REV. 2.6, AUG. 20, 2001  
5
MX27C4111  
SWITCHING TEST CIRCUITS  
1.8K ohm  
DEVICE  
UNDER  
TEST  
+5V  
DIODES = IN3064  
OR EQUIVALENT  
CL  
6.2K ohm  
CL = 100 pF including jig capacitance  
SWITCHING TEST WAVEFORMS  
2.0V  
0.8V  
2.0V  
0.8V  
TEST POINTS  
AC driving levels  
OUTPUT  
INPUT  
AC TESTING: AC driving levels are 2.4V/0.4V.  
Input pulse rise and fall times are < 20ns.  
NOTICE:  
ABSOLUTE MAXIMUM RATINGS  
Stresses greater than those listed under ABSOLUTE  
MAXIMUM RATINGS may cause permanent damage to the  
device. This is a stress rating only and functional operation  
of the device at these or any other conditions above those  
indicated in the operational sections of this specification is not  
implied. Exposure to absolute maximum rating conditions for  
extended period may affect reliability.  
RATING  
VALUE  
0oC to 70oC  
-65oC to 125oC  
Ambient Operating Temperature  
Storage Temperature  
Applied Input Voltage  
Applied Output Voltage  
VCC to Ground Potential  
A9 & VPP  
-0.5V to 7.0V  
-0.5V to VCC + 0.5V  
-0.5V to 7.0V  
NOTICE:  
-0.5V to 13.5V  
Specifications contained within the following tables are sub-  
ject to change.  
P/N: PM0239  
REV. 2.6, AUG. 20, 2001  
6
MX27C4111  
DC/AC Operating Condition for Read Operation  
-90  
MX27C4111  
-10  
-12  
-15  
Operating Temperature Commercial  
Vcc POwer Supply  
0°C to 70°C 0°C to 70°C  
0°C to 70°C  
5V ± 10%  
0°C to 70°C  
5V ± 10%  
5V ± 5%  
5V ± 10%  
DC CHARACTERISTICS  
SYMBOL PARAMETER  
MIN.  
MAX.  
UNIT  
V
CONDITIONS  
VOH  
VOL  
VIH  
Output High Voltage  
Output Low Voltage  
2.4  
IOH = -0.4mA  
IOL = 2.1mA  
0.4  
VCC + 0.5  
0.8  
V
Input High Voltage  
2.0  
-0.3  
-10  
-10  
V
VIL  
Input Low Voltage  
V
ILI  
Input Leakage Current  
Output Leakage Current  
VCC Power-Down Current  
VCC Standby Current  
VCC Active Current  
10  
uA  
uA  
uA  
mA  
mA  
uA  
VIN = 0 to 5.5V  
ILO  
10  
VOUT = 0 to 5.5V  
CE = VCC ± 0.3V  
ICC3  
ICC2  
ICC1  
IPP  
100  
1.5  
CE = VIH  
60  
CE = VIL, f=5MHz, Iout = 0mA  
CE = OE = VIL, VPP = 5.5V  
VPP Supply Current Read  
10  
CAPACITANCE TA = 25oC, f = 1.0 MHz (Sampled only)  
SYMBOL  
CIN  
PARAMETER  
TYP.  
8
MAX.  
12  
UNIT  
CONDITIONS  
VIN = 0V  
Input Capacitance  
Output Capacitance  
VPP Capacitance  
pF  
pF  
pF  
COUT  
CVPP  
8
12  
VOUT = 0V  
VPP = 0V  
18  
25  
AC CHARACTERISTICS  
27C4111-90 27C4111-10  
MIN. MAX. MIN. MAX.  
27C4111-12 27C4111-15  
Symbol PARAMETER  
MIN. MAX. MIN. MAX. UNIT CONDITIONS  
tACC  
tCE  
tPA  
Address to Output Delay  
90  
90  
50  
45  
30  
100  
100  
50  
120  
120  
60  
150 ns  
150 ns  
CE = OE = VIL  
OE = VIL  
Chip Enable to Output Delay  
Page Address to Output Delay  
Output Enable to Output Delay  
OE High to Output Float,  
or CE High to Output Float  
Output Hold from Address,  
75  
65  
50  
ns  
ns  
ns  
CE = OE =VIL  
CE = VIL  
tOE  
tDF  
45  
50  
0
0
0
0
30  
0
0
35  
0
0
tOH  
0
ns  
CE or OE which ever occurred first  
BYTE Access Time  
tBHA  
tOHB  
tBHZ  
tBLZ  
90  
70  
100  
70  
120  
70  
150 ns  
ns  
BYTE Output Hold Time  
BYTE Output Delay Time  
BYTE Output Set Time  
0
0
0
0
70  
ns  
ns  
10  
10  
10  
10  
P/N: PM0239  
REV. 2.6, AUG. 20, 2001  
7
MX27C4111  
DC PROGRAMMING CHARACTERISTICS TA = 25oC ± 5oC  
SYMBOL PARAMETER  
MIN.  
MAX.  
UNIT  
V
CONDITIONS  
IOH = -0.40mA  
IOL = 2.1mA  
VOH  
VOL  
VIH  
Output High Voltage  
2.4  
Output Low Voltage  
0.4  
VCC + 0.5  
0.8  
V
Input High Voltage  
2.0  
-0.3  
-10  
V
VIL  
Input Low Voltage  
V
ILI  
Input Leakage Current  
10  
uA  
V
VIN = 0 to 5.5V  
VH  
A9 Auto Select Voltage  
11.5  
12.5  
50  
ICC3  
IPP2  
VCC1  
VPP1  
VCC Supply Current (Program & Verify)  
VPP Supply Current(Program)  
Fast Programming Supply Voltage  
Fast Programming Voltage  
mA  
mA  
V
30  
CE = VIL, OE = VIH  
6.00  
12.5  
6.50  
13.0  
V
AC PROGRAMMING CHARACTERISTICS TA = 25oC ± 5oC  
SYMBOL  
tAS  
PARAMETER  
MIN.  
2.0  
2.0  
2.0  
0
MAX.  
UNIT  
CONDITIONS  
Address Setup Time  
OE Setup Time  
us  
us  
us  
us  
us  
ns  
us  
us  
us  
ns  
tOES  
tDS  
Data Setup Time  
tAH  
Address Hold Time  
Data Hold Time  
tDH  
2.0  
0
tDFP  
tVPS  
tPW  
Chip Enable to Output Float Delay  
BYTE/VPP Setup Time  
CE initial Program Pulse Width  
VCC Setup Time  
130  
105  
150  
2.0  
95  
tVCS  
tOE  
2.0  
Data valid from OE  
P/N: PM0239  
REV. 2.6, AUG. 20, 2001  
8
MX27C4111  
WAVEFORMS  
NORMAL READ CYCLE(WORD MODE)  
ADDRESS  
INPUTS  
DATA ADDRESS  
tACC  
CE  
OE  
tCE  
tDF  
DATA  
OUT  
VALID DATA  
tOE  
tOH  
PAGE MODE READ CYCLE  
A4-A18  
VALID ADDRESS  
A0~A2 (Word mode)  
A-1~A2 (Byte mode)  
tACC  
CE  
tPA  
tPA  
tPA  
OE  
tDF  
tOH  
tOE  
DATA OUT  
P/N: PM0239  
REV. 2.6, AUG. 20, 2001  
9
MX27C4111  
WAVEFORMS  
NORMAL READ CYCLE(BYTE MODE)  
HIGH-Z  
HIGH-Z  
A-1  
tACC  
tOH  
BYTE/VPP  
Q0-Q7  
VALID DATA  
VALID DATA  
tBHA  
tOHB  
VALID DATA  
Q15-Q8  
tBHZ  
tBLZ  
FAST PROGRAMMING ALGORITHM WAVEFORMS  
PROGRAM  
VERIFY  
VIH  
Addresses  
VALID ADDRESS  
VIL  
tAH  
tAS  
DATA OUT VALID  
DATA SET  
DATA  
tDFP  
tDS  
tDH  
VPP1  
VCC  
BYTE/VPP  
tVPS  
tVCS  
VCC1  
VCC  
VCC  
CE  
VIH  
VIL  
tOE  
tOES  
tPW  
VIH  
VIL  
OE  
P/N: PM0239  
REV. 2.6, AUG. 20, 2001  
10  
MX27C4111  
ORDERING INFORMATION  
PLASTIC PACKAGE  
PART NO.  
ACCESS TIME  
OPERATING CURRENT  
STANDBY CURRENT PACKAGE  
(ns)  
90  
MAX.(mA)  
MAX.(uA)  
100  
MX27C4111MC-90  
MX27C4111MC-10  
MX27C4111MC-12  
MX27C4111MC-15  
MX27C4111PC-90  
MX27C4111PC-10  
MX27C4111PC-12  
MX27C4111PC-15  
60  
60  
60  
60  
60  
60  
60  
60  
40 Pin SOP(ROM pin out)  
40 Pin SOP(ROM pin out)  
40 Pin SOP(ROM pin out)  
40 Pin SOP(ROM pin out)  
40 Pin PDIP(ROM pin out)  
40 Pin PDIP(ROM pin out)  
40 Pin PDIP(ROM pin out)  
40 Pin PDIP(ROM pin out)  
100  
120  
150  
90  
100  
100  
100  
100  
100  
120  
150  
100  
100  
100  
P/N: PM0239  
REV. 2.6, AUG. 20, 2001  
11  
MX27C4111  
PACKAGE INFORMATION  
40-PIN PLASTIC DIP(600 mil)  
P/N: PM0239  
REV. 2.6, AUG. 20, 2001  
12  
MX27C4111  
40-PIN PLASTIC SOP  
P/N: PM0239  
REV. 2.6, AUG. 20, 2001  
13  
MX27C4111  
REVISION HISTORY  
Revision No. Description  
Page  
Date  
2.0  
1) Eliminate Interactive Programming Mode  
6/14/1997  
2) 40-CDIP package quartz lens, change to square shape.  
IPP 100uA --> 10uA  
2.1  
2.2  
2.3  
2.4  
2.5  
2.6  
8/07/1997  
1/31/1998  
4/07/1998  
5/06/1998  
Add 100ns speed grade.  
Add 90ns speed grade.  
90ns speed grade VCC=5V±10% --> VCC=5V±5%  
Cancel ceramic DIP package type  
P1,3,12,13 MAR/02/2000  
Cancel "Ultraviolet Erasable" wording in General Description  
To modify Package Information  
P1  
AUG/20/2001  
P12~13  
P/N: PM0239  
REV. 2.6, AUG. 20, 2001  
14  
MX27C4111  
MACRONIX INTERNATIONAL CO., LTD.  
HEADQUARTERS:  
TEL:+886-3-578-6688  
FAX:+886-3-563-2888  
EUROPE OFFICE:  
TEL:+32-2-456-8020  
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FAX:+81-44-246-9105  
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FAX:+65-348-8096  
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http : //www.macronix.com  
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.  
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