MX28F1000PQC-12C4_技术文档

MX28F1000P

1M-BIT [128K x 8] CMOS FLASH MEMORY

FEATURES

• 131,072 bytes by 8-bit organization

• Fast access time: 70ns(Vcc:5V±5%; CL:35pF)

90/120ns(Vcc:5V±10%; CL:100pF)

• Low power consumption

– Seven 16-KB blocks

• Auto Erase (chip & block) and Auto Program

– DATA polling

– Toggle bit

– 50mA maximum active current

– 100uA maximum standby current

• Programming and erasing voltage 12V ± 5%

• Command register architecture

– Byte Programming (15us typical)

– Auto chip erase 5 seconds typical

(including preprogramming time)

– Block Erase

• 10,000 minimum erase/program cycles

• Latch-up protected to 100mA from -1 to VCC+1V

• Advanced CMOS Flash memory technology

• Compatible with JEDEC-standard byte-wide 32-pin

EPROM pinouts

• Package type:

– 32-pin plastic DIP

– 32-pin PLCC

• Optimized high density blocked architecture

– Four 4-KB blocks

– 32-pin TSOP (Type 1)

GENERAL DESCRIPTION

MX28F1000P uses a 12.0V ± 5% VPP supply to

perform the Auto Program/Erase algorithms.

The MX28F1000P is a 1-mega bit Flash memory or-

ganized as 128K bytes of 8 bits each. MXIC's Flash

memories offer the most cost-effective and reliable

read/write non-volatile random access memory. The

MX28F1000P is packaged in 32-pin PDIP, PLCC

and TSOP. It is designed to be reprogrammed and

erased in-system or in-standard EPROM program-

mers.

The highest degree of latch-up protection is

achieved with MXIC's proprietary non-epi process.

Latch-up protection is proved for stresses up to 100

milliamps on address and data pin from -1V to VCC

+ 1V.

The standard MX28F1000P offers access times as

fast as 70 ns, allowing operation of high-speed

microprocessors without wait states. To eliminate

bus contention, the MX28F1000P has separate chip

enable (CE) and output enable (OE ) controls.

MXIC's Flash memories augment EPROM function-

ality with in-circuit electrical erasure and

programming. The MX28F1000P uses a command

register to manage this functionality, while

maintaining a standard 32-pin pinout. The

command register allows for 100% TTL level control

inputs and fixed power supply levels during erase

and programming, while maintaining maximum

EPROM compatibility.

MXIC Flash technology reliably stores memory con-

tents even after 10,000 erase and program cycles.

The MXIC cell is designed to optimize the erase and

programming mechanisms. In addition, the combi-

nation of advanced tunnel oxide processing and low

internal electric fields for erase and programming

operations produces reliable cycling.

The

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MX28F1000P

MX28F1000P Block Address and Block Structure

A16 A15 A14 A13 A12

A [ 1 6 : 0 ]

1 F F F F

1 F 0 0 0

1

4k

1 E F F F

1 E 0 0 0

4k

1

0

1

0

1 D F F F

1 D 0 0 0

1 C F F F

1 C 0 0 0

1 B F F F

16k

1

0

1

0

X

1 8 0 0 0

1 7 F F F

1 4 0 0 0

1 3 F F F

1 0 0 0 0

0 F F F F

16k

0

1

0

1

0

1

X

0 C 0 0 0

0 B F F F

0 8 0 0 0

0 7 F F F

0 4 0 0 0

0 3 F F F

0

X

0 0 0 0 0

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MX28F1000P

PIN CONFIGURATIONS

32 PDIP

TSOP (TYPE 1)

VCC

WE

NC

A14

A13

A8

VPP

A16

A15

A12

A7

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

1

A11

A9

1

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

OE

A10

CE

Q7

Q6

Q5

Q4

Q3

GND

Q2

Q1

Q0

A0

2

A8

3

A13

A14

NC

4

5

6

A6

6

WE

VCC

VPP

A16

A15

A12

A7

7

A9

A5

7

8

MX28F1000P

A11

OE

A10

CE

Q7

A4

8

9

A3

9

10

11

12

13

14

15

16

A2

10

11

12

13

14

15

16

A1

A0

Q6

Q0

A6

A1

Q5

Q1

A5

A2

Q4

Q2

A4

A3

Q3

GND

(NORMAL TYPE)

32 PLCC

OE

A10

CE

Q7

Q6

Q5

Q4

Q3

GND

Q2

Q1

Q0

A0

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

1

2

A11

A9

3

A8

4

A13

A14

NC

WE

VCC

VPP

A16

A15

A12

A7

4

1

32

30

29

5

9

A7

A6

A5

A4

A3

A2

A1

A0

Q0

A14

A13

A8

5

6

7

8

MX28F1000P

A9

9

10

11

12

13

14

15

16

MX28F1000P

25

A11

OE

A10

CE

Q7

A1

A6

A2

A5

13

14

A3

A4

21

17

20

(REVERSE TYPE)

PIN DESCRIPTION:

SYMBOL

A0~A16

Q0~Q7

CE

PIN NAME

Address Input

Data Input/Output

Chip Enable Input

Output Enable Input

Write enable Pin

OE

WE

VPP

Program Supply Voltage

Power Supply Pin (+5V)

Ground Pin

VCC

GND

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MX28F1000P

BLOCK DIAGRAM

CE

OE

WE

CONTROL

INPUT

PROGRAM/ERASE

HIGH VOLTAGE

MODE

LOGIC

STATE

MX28F1000P

FLASH

REGISTER

ADDRESS

LATCH

ARRAY

SOURCE

HV

A0-A16

AND

COMMAND

DATA

DECODER

BUFFER

Y-PASS GATE

PGM

DATA

HV

SENSE

AMPLIFIER

COMMAND

DATA LATCH

PROGRAM

DATA LATCH

I/O BUFFER

Q0-Q7

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MX28F1000P

AUTOMATIC PROGRAMMING

AUTOMATIC ERASE ALGORITHM

The MX28F1000P is byte programmable using the

Automatic Programming algorithm. The Automatic

Programming algorithm does not require the system to

time out or verify the data programmed. The typical

room temperature chip programming time of the

MX28F1000P is less than 5 seconds.

MXIC's Automatic Erase algorithm requires the user to

only write an erase set-up command and erase com-

mand. The device will automatically pre-program and

verify the entire array. Then the device automatically

times the erase pulse width, provides the erase verify,

and counts the number of sequences. A status bit

similar to DATA polling and a status bit toggling

between consecutive read cycles, provide feedback to

the user as to the status of the erase operation.

AUTOMATIC CHIP ERASE

Commands are written to the command register using

standard microprocessor write timings. Register con-

tents serve as inputs to an internal state-machine

which controls the erase and programming circuitry.

During write cycles, the command register internally

latches address and data needed for the programming

and erase operations. For system design simplifica-

tion, the MX28F1000P is designed to support either

WE or CE controlled writes. During a system write

cycle, addresses are latched on the falling edge of WE

or CE whichever occurs last. Data is latched on the

rising edge of WE or CE whichever occur first. To

simplify the following discussion, the WE pin is used as

the write cycle control pin throughout the rest of this

text. All setup and hold times are with respect to the

WE signal.

The device may be erased using the Automatic Erase

algorithm. The Automatic Erase algorithm automati-

cally programs the entire array prior to electrical erase.

The timing and verification of electrical erase are

controlled internal to the device.

AUTOMATIC BLOCK ERASE

The MX28F1000P is block(s) erasable using MXIC's

Auto Block Erase algorithm. Block erase modes allow

blocks of the array to be erased in one erase cycle.

The Automatic Block Erase algorithm automatically

programs the specified block(s) prior to electrical

erase. The timing and verification of electrical erase

are controlled internal to the device.

MXIC's Flash technology combines years of EPROM

experience to produce the highest levels of quality, relia-

bility, and cost effectiveness. The MX28F1000P electri-

cally erases all bits simultaneously using Fowler-Nord-

heim tunneling. The bytes are programmed one byte at

a time using the EPROM programming mechanism of hot

electron injection.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm requires

the user to only write a program set-up command and

a program command (program data and address). The

device automatically times the programming pulse

width, provides the program verify, and counts the

number of sequences. A status bit similar to DATA

polling and a status bit toggling between consecutive

read cycles, provide feedback to the user as to the

status of the programming operation.

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MX28F1000P

TABLE 1. COMMAND DEFINITIONS

COMMAND

BUS

FIRST BUS CYCLE

SECOND BUS CYCLE

CYCLES

OPERATION ADDRESS DATA

Read Memory

1

2

Write

X

00H

90H

30H

Read Identified codes

Read

Write

IA

X

ID

Setup auto erase/

auto erase (chip)

2

30H

Setup auto erase/

auto erase (block)

2

Write

X

20H

Write

EA

D0H

Setup auto program/

program

2

Write

X

40H

20H

60H

Write

PA

X

PD

Setup Erase/

Erase (chip)

20H

60H

Setup Erase/

Erase (block)

EA

Erase verify

Reset

2

Write

EVA

X

A0H

FFH

Read

Write

X

EVD

FFH

Note:

IA = Identifier address

EA = Block of memory location to be erased

PA = Address of memory location to be pro-

grammed

ID

= Data read from location IA during device iden-

tification

PD = Data to be programmed at location PA

EVA = Address of memory location to be read during

erase verify.

EVD = Data read from location EVA during erase

verify.

Auto modes have the build-in enchanced features.

Please use the auto erase mode whenever it is.

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MX28F1000P

COMMAND DEFINITIONS

When low voltage is applied to the VPP pin, the con-

tents of the command register default to 00H, enabling

read-only operation.

Placing high voltage on the VPP pin enables read/write

operations. Device operations are selected by writing

specific data patterns into the command register. Ta-

ble 1 defines these MX28F1000P register commands.

Table 2 defines the bus operations of MX28F1000P.

TABLE 2. MX28F1000P BUS OPERATIONS

OPERATION

READ-ONLY

VPP(1)

VPPL

VPPH

A0

X

A9

CE

VIL

VIH

VIL

VIH

VIL

OE

VIL

VIH

X

WE

VIH

X

DQ0-DQ7

Data Out

Read

A9

Output Disable

Standby

X

Tri-State

X

Tri-State

Read Silicon ID (Mfr)(2)

Read Silicon ID (Device)(2)

Read

VIL

VIH

A0

X

VID(3)

A9

VIL

X

VIH

X

Data = C2H

Data = 1AH

Data Out(4)

Tri-State

READ/WRITE

Standby(5)

X

Write

A0

A9

VIH

VIL

Data In(6)

NOTES:

1. VPPL may be grounded, a no-connect with a resistor tied

to ground, or < VCC + 2.0V. VPPH is the programming

voltage specified for the device. When VPP = VPPL,

memory contents can be read but not written or erased.

2. Manufacturer and device codes may also be accessed

via a command register write sequence. Refer to Table

1. All other addresses are don't care.

3. VID is the Silicon-ID-Read high voltage.(11.5V to 13v)

4. Read operations with VPP = VPPH may access array

data or Silicon ID codes.

5. With VPP at high voltage, the standby current equals ICC

+ IPP (standby).

6. Refer to Table 1 for valid Data-In during a write operation.

7. X can be VIL or VIH.

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MX28F1000P

device returns to the Read mode. The system is not

required to provide any control or timing during these

operations.

READ COMMAND

While VPP is high, for erase and programming, mem-

ory contents can also be accessed via the read com-

mand. The read operation is initiated by writing 00H

into the command register. Microprocessor read

cycles retrieve array data. The device remains en-

abled for reads until the command register contents

are altered.

When using the Automatic Chip Erase algorithm, note

that the erase automatically terminates when

adequate erase margin has been achieved for the

memory array(no erase verify command is required).

The margin voltages are internally generated in the

same manner as when the standard erase verify

command is used.

The default contents of the register upon VPP power-

up is 00H. This default value ensures that no spurious

alteration of memory contents occurs during the VPP

power transition. Where the VPP supply is hard-wired

to the MX28F1000P, the device powers up and

remains enabled for reads until the command register

contents are changed.

The Automatic set-up erase command is a command-

only operation that stages the device for automatic

electrical erasure of all bytes in the array. Automatic

set-up erase is performed by writing 30H to the

command register.

To command automatic chip erase, the command 30H

must be written again to the command register. The

automatic chip erase begins on the rising edge of the

WE and terminates when the data on DQ7 is "1" and

the data on DQ6 stops toggling for two consecutive

read cycles, at which time the device returns to the

Read mode.

SILICON-ID-READ COMMAND

Flash-memories are intended for use in applications

where the local CPU alters memory contents. As such,

manufacturer- and device-codes must be accessible

while the device resides in the target system. PROM

programmers typically access signature codes by rais-

ing A9 to a high voltage. However, multiplexing high

voltage onto address lines is not a desired system-

design practice.

SET-UP AUTOMATIC BLOCK ERASE/ERASE

COMMANDS

The MX28F1000P contains a Silicon-ID-Read

operation to supplement traditional PROM-

programming methodology. The operation is initiated

by writing 90H into the command register. Following

the command write, a read cycle from address 0000H

retrieves the manufacturer code of C2H. A read cycle

from address 0001H returns the device code of 1AH.

The automatic block erase does not require the device

to be entirely pre-programmed prior to executing the

Automatic set-up block erase command and

Automatic block erase command. Upon executing the

Automatic block erase command, the device automati-

cally will program and verify the block(s) memory for an

all-zero data pattern. The system is not required to

provide any controls or timing during these operations.

SET-UP AUTOMATIC CHIP ERASE/ERASE

COMMANDS

When the block(s) is automatically verified to contain

an all-zero pattern, a self-timed block erase and verify

begin. The erase and verify operations are complete

when the data on DQ7 is "1" and the data on DQ6 stops

toggling for two consecutive read cycles, at which time

the device returns to the Read mode. The system is

not required to provide any control or timing during

these operations.

The automatic chip erase does not require the device

to be entirely pre-programmed prior to excuting the

Automatic set-up erase command and Automatic chip

erase command. Upon executing the Automatic chip

erase command, the device automatically will program

and verify the entire memory for an all-zero data

pattern. When the device is automatically verified to

contain an all-zero pattern, a self-timed chip erase and

verify begin. The erase and verify operations are

complete when the data on DQ7 is "1" at which time the

When using the Automatic Block Erase algorithm, note

that the erase automatically terminates when adequate

erase margin has been achieved for the memory array

(no erase verify command is required). The margin

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MX28F1000P

voltages are internally generated in the same manner

as when the standard erase verify command is used.

SET-UP CHIP ERASE/ERASE COMMANDS

Set-up Chip Erase is a command-only operation that

stages the device for electrical erasure of all bytes in

the array. The set-up erase operation is performed by

writing 20H to the command register.

The Automatic set-up block erase command is a com-

mand only operation that stages the device for auto-

matic electrical erasure of selected blocks in the array.

Automatic set-up block erase is performed by writing

20H to the command register.

To commence chip erasure, the erase command (20H)

must again be written to the register. The erase

operation begins with the rising edge of the WE pulse.

To enter automatic block erase, the user must write

the command D0H to the command register. Block

addresses are loaded into internal register on the 2nd

falling edge of WE. Each successive block load cycles,

started by the falling edge of WE, must begin within

30ms from the rising edge of the preceding WE.

Otherwise, the loading period ends and internal auto

block erase cycle starts. When the data on DQ7 is "1"

and the data on DQ6 stops toggling for two

consecutive read cycles, at which time auto erase

ends and the device returns to the Read mode.

This two-step sequence of set-up followed by execu-

tion ensures that memory contents are not accidentally

erased. Also, chip-erasure can only occur when high

voltage is applied to the VPP pin. In the absence of this

high voltage, memory contents are protected against

erasure.

Refer to page 2 for detailed block address.

SET-UP BLOCK ERASE/ERASE COMMANDS

Set-up Block Erase is a command-only operation that

stages the device for electrical erasure of all selected

block(s) in the array. The set-up erase operation is

performed by writing 60H to the command register.

SET-UP AUTOMATIC PROGRAM/PROGRAM

COMMANDS

To enter block-erasure, the block erase command 60H

must be written again to the command register. The

block erase mode allows 1 to 8 blocks of the array to be

erased in one internal erase cycle. Internally, there are

8 registers (flags) addressed by A14 to A16. First block

address is loaded into internal registers on the 2-nd

falling of WE. Each successive block load cycles,

started by the falling edge of WE, must begin within

30ms from the rising edge of the preceding WE. Other-

wise, the loading period ends and internal block erase

cycle starts. When the data on DQ7 is "1" at which time

auto erase ends and the device returns to the Read

mode.

The Automatic Set-up Program is a command-only

operation that stages the device for automatic pro-

gramming. Automatic Set-up Program is performed by

writing 40H to the command register.

Once the Automatic Set-up Program operation is per-

formed, the next WE pulse causes a transition to an

active programming operation. Addresses are

internally latched on the falling edge of the WE pulse.

Data is internally latched on the rising edge of the WE

pulse. The rising edge of WE also begins the

programming operation. The system is not required to

provide further controls or timings. The device will

automatically provide an adequate internally

generated program pulse and verify margin. The

automatic programming operation is completed when

the data read on DQ6 stops toggling for two

consecutive read cycles and the data on DQ7 and

DQ6 are equivalent to data written to these two bits, at

which time the device returns to the Read mode (no

program verify command is required).

ERASE-VERIFY COMMAND

After each erase operation, all bytes must be verified.

The erase verify operation is initiated by writing A0H

into the command register. The address for the byte to

be verified must be supplied as it is latched on the

falling edge of the WE pulse.

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MX28F1000P

DATA POLLING-DQ7

The MX28F1000P applies an internally generated

margin voltage to the addressed byte. Reading FFH

from the addressed byte indicates that all bits in the

byte are erased.

The MX28F1000P also features Data Polling as a

method to indicate to the host system that the

Automatic Program or Erase algorithms are either in

progress or completed.

The erase-verify command must be written to the

command register prior to each byte verification to

latch its address. The process continues for each byte

in the array until a byte does not return FFH data, or the

last address is accessed.

While the Automatic Programming algorithm is in op-

eration, an attempt to read the device will produce the

complement data of the data last written to DQ7. Upon

completion of the Automatic Program algorithm an

attempt to read the device will produce the true data

last written to DQ7. The Data Polling feature is valid

after the rising edge of the second WE pulse of the two

write pulse sequences.

In the case where the data read is not FFH, another

erase operation is performed. (Refer to Set-up Erase/

Erase). Verification then resumes from the address of

the last-verified byte. Once all bytes in the array have

been verified, the erase step is complete. The device

can be programmed. At this point, the verify operation

is terminated by writing a valid command (e.g.

Program Set-up) to the command register. The High

Reliability Erase algorithm, illustrates how commands

and bus operations are combined to perform electrical

erasure of the MX28F1000P.

While the Automatic Erase algorithm is in operation,

DQ7 will read "0" until the erase operation is com-

pleted. Upon completion of the erase operation, the

data on DQ7 will read "1". The Data Polling feature is

valid after the rising edge of the second WE pulse of

two write pulse sequences.

The Data Polling feature is active during Automatic

Program/Erase algorithms.

RESET COMMAND

A reset command is provided as a means to safely

abort the erase- or program-command sequences.

Following either set-up command (erase or program)

with two consecutive writes of FFH will safely abort the

operation. Memory contents will not be altered.

Should program-fail or erase-fail happen, two

consecutive writes of FFH will reset the device to abort

the operation. A valid command must then be written

to place the device in the desired state.

POWER-UP SEQUENCE

The MX28F1000P powers up in the Read only mode. In

addition, the memory contents may only be altered after

successfulcompletionofatwo-stepcommandsequence.

Power up sequence is not required.

SYSTEM CONSIDERATIONS

WRITE OPERATON STATUS

TOGGLE BIT-DQ6

During the switch between active and standby condi-

tions, transient current peaks are produced on the

rising and falling edges of Chip Enable. The magnitude

of these transient current peaks is dependent on the

output capacitance loading of the device. At a

minimum, a 0.1uF ceramic capacitor (high frequency,

low inherent inductance) should be used on each

device between VCC and GND, and between VPP and

GND to minimize transient effects. In addition, to

overcome the voltage drop caused by the inductive

effects of the printed circuit board traces on FLASH

memory arrays, a 4.7uF bulk electrolytic capacitor

should be used between VCC and GND for each eight

devices. The location of the capacitor should be close

to where the power supply is connected to the array.

The MX28F1000P features a "Toggle Bit" as a method

to indicate to the host sytem that the Auto Program/

Erase algorithms are either in progress or completed.

While the Automatic Program or Erase algorithm is in

progress, successive attempts to read data from the

device will result in DQ6 toggling between one and

zero. Once the Automatic Program or Erase algorithm

is completed, DQ6 will stop toggling and valid data will

be read. The toggle bit is valid after the rising edge of

the second WE pulse of the two write pulse

sequences.

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MX28F1000P

NOTICE:

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed under ABSOLUTE MAXI-

MUM RATINGS may cause permanent damage to the de-

vice. This is stress rating only and functional operational

sections of this specification is not implied. Exposure to ab-

solute maximum rating conditions for extended period may

affect reliability.

RATING

VALUE

Ambient Operating Temperature -40^oC to 85^oC

Storage Temperature

Applied Input Voltage

Applied Output Voltage

VCC to Ground Potential

A9 & VPP

-65^oC to 125^oC

-0.5V to 7.0V

-0.5V to 13.5V

NOTICE:

Specifications contained within the following tables are sub-

ject to change.

CAPACITANCE TA = 25^oC, f = 1.0 MHz

SYMBOL

CIN

PARAMETER

MIN.

TYP

MAX.

14

UNIT

pF

CONDITIONS

VIN = 0V

Input Capacitance

Output Capacitance

COUT

16

pF

VOUT = 0V

READ OPERATION

DC CHARACTERISTICS

SYMBOL

PARAMETER

MIN.

TYP

MAX.

UNIT

CONDITIONS

ILI

Input Leakage Current

Output Leakage Current

VPP Current

10

uA

VIN = GND to VCC

ILO

10

uA

mA

uA

VOUT = GND to VCC

VPP = 5.5V

IPP1

ISB1

ISB2

ICC1

ICC2

VIL

1

100

1

Standby VCC current

CE = VIH

100

CE = VCC + 0.3V

IOUT = 0mA, f=1MHz

IOUT = 0mA, f=11MHz

Operating VCC current

30(NOTE4) mA

50

mA

V

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

-0.3(NOTE 1)

2.4

0.8

VIH

VCC + 0.3

0.45

V

VOL

VOH

V

IOL = 2.1mA

IOH = -400uA

2.4

V

NOTES:

3. Test condition:

1. VIL min. = -1.0V for pulse width < 50 ns.

VIL min. = -2.0V for pulse width < 20 ns.

TA =-40°C to 85°C, Vcc = 5V±10%, Vpp = GND to Vcc, CL

= 100pF(for MX28F1000P-90/12)

2. VIH max. = VCC + 1.5V for pulse width < 20 ns

TA = -40°C to 85°C, Vcc = 5V±10%, Vpp = GND to Vcc, CL

= 35pF(for MX28F1000P-70)

If VIH is over the specified maximum value, read operation

cannot be guaranteed.

4.ICC1=35mA for TA=-40°C to 85°C

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MX28F1000P

AC CHARACTERISTICS

28F1000P-70

28F1000P-90 28F1000P-12

SYMBOL PARAMETER

MIN. MAX.

MIN.

MAX. UNIT CONDITIONS

tACC

tCE

tOE

tDF

Address to Output Delay

70

30

90

35

120

50

ns

CE=OE=VIL

OE=VIL

CE to Output Delay

OE to Output Delay

CE=VIL

OE High to Output Float (Note1)

Address to Output hold

0

15

0

20

0

30

CE=VIL

tOH

CE=OE=VIL

TEST CONDITIONS:

NOTE:

•

Input pulse levels: 0.45V/2.4V

1. tDF is defined as the time at which the output achieves the

open circuit condition and data is no longer driven.

Input rise and fall times: < 10ns

Reference levels for measuring timing: 0.8V, 2.0V

28F1000P-70:Vcc = 5V ± 5%, CL: 1TTL gate +

35pF(including scope and jig)

•

28F1000P-70:Vcc = 5V ± 5%, CL: 1TTL gate +

35pF(including scope and jig)

•

Vpp = GND to Vcc

READ TIMING WAVEFORMS

ADDRESS

WE

CE

ACTIVE MODE

STANDBY MODE

tCE

OE

tDF

tOE

tACC

tOH

DATA OUT

DATA OUT VALID

REV. 1.6, JAN. 19, 1999

P/N: PM0340

12

MX28F1000P

COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION

DC CHARACTERISTICS

SYMBOL

PARAMETER

MIN.

TYP

MAX.

10

UNIT

uA

CONDITIONS

VIN=GND to VCC

VOUT=GND to VCC

CE=VIH

ILI

Input Leakage Current

Output Leakage Current

Standby VCC current

ILO

10

uA

ISB1

1

mA

uA

ISB2

1

100

30

CE=VCC ± 0.3V

IOUT=0mA, f=1MHz

IOUT=0mA, F=11MHz

In Programming

In Erase

ICC1 (Read)

ICC2

Operating VCC Current

mA

uA

50

ICC3 (Program)

ICC4 (Erase)

ICC5 (Program Verify)

ICC6 (Erase Verify)

IPP1 (Read)

IPP2 (Program)

IPP3 (Erase)

IPP4 (Program Verify)

IPP5 (Erase Verify)

VIL

50

In Program Verify

In Erase Verify

VPP=12.6V

50

VPP Current

100

50

mA

V

In Programming

In Erase

50

In Program Verify

In Erase Verify

50

Input Voltage

-0.3 (Note 5)

2.4

0.8

VIH

VCC+0.3V

(Note 6)

0.45

V

VOL

VOH

Output Voltage

V

IOL=2.1mA

2.4

IOH=-400uA

NOTES:

1. VCC must be applied before VPP and removed after VPP.

2. VPP must not exceed 14V including overshoot.

3. An influence may be had upon device reliability if the device

is installed or removed while VPP=12V.

5. VIL min. = -0.6V for pulse width < 20ns.

6. If VIH is over the specified maximum value, programming

operation cannot be guranteed.

7.AllcurrentsareinRMSunlessotherwisenoted.(Sampled,not

100% tested.)

4. Do not alter VPP either VIL to 12V or 12V to VIL when

CE=VIL.

8. For 28F1000P-70, Vcc = 5V ±5%, CL = 35pF; for 28F1000P-

90/12, Vcc = 5V ± 10%, CL = 100pF.

REV. 1.6, JAN. 19, 1999

P/N: PM0340

13

MX28F1000P

AC CHARACTERISTICS TA = -40^oC to 85^oC, VCC = 5V ± 10%, VPP =12V ± 5%

28F1000-70

28F1000P-90

28F1000P-12

SYMBOL PARAMETER

MIN. MAX.

MIN.

100

90

MAX.

MIN.

100

120

50

MAX. UNIT CONTIONS

tVPS

tOES

tCWC

tCEP

tCEPH1

tCEPH2

tAS

VPP setup time

100

70

40

20

100

0

ns

us

ns

s

OE setup time

Command programming cycle

WE programming pulse width

WE programming pluse width High

Address setup time

45

20

100

0

100

0

tAH

Address hold time

40

0

45

50

tAH1

tDS

Address hold time for DATA POLLING

Data setup time

0

40

10

45

50

tDH

Data hold time

10

tCESP

tCES

tCESC

tCESV

tVPH

tDF

CE setup time before DATA polling/toggle bit 100

100

0

100

0

CE setup time

0

CE setup time before command write

CE setup time before verify

VPP hold time

100

6

100

6

100

6

100

Output disable time (Note 3)

DATA polling/toggle bit access time

Total erase time in auto chip erase

Total erase time in auto block erase

Total programming time in auto verify

Block address load cycle

Block address load time

15

70

20

90

30

tDPA

tAETC

tAETB

tAVT

tBALC

tBAL

120

5(TYP.)

5TYP.)

15

5(TYP.)

s

300

30

15

0.3

200

0

300

30

15

0.3

200

0

300

30

us

ns

0.3

200

0

tCH

CE Hold Time

tCS

CE setup to WE going low

0

NOTES:

1. CE and OE must be fixed high during VPP transition from 5V

to 12V or from 12V to 5V.

2. Refer to read operation when VPP=VCC about read opera-

tion while VPP 12V.

3. tDFdefinedasthetimeatwhichtheoutputachievestheopen

circuit condition and data is no longer driven.

REV. 1.6, JAN. 19, 1999

P/N: PM0340

14

MX28F1000P

SWITCHING TEST CIRCUITS

1.8K ohm

+5V

DEVICE

UNDER

TEST

DIODES = IN3064

OR EQUIVALENT

CL

6.2K ohm

CL = 100 pF including jig capacitance(35pF for 70 ns parts)

SWITCHING TEST WAVEFORMS

2.4 V

2.0V

0.8V

2.0V

0.8V

TEST POINTS

0.45 V

OUTPUT

INPUT

AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0".

Input pulse rise and fall times are <20ns.

REV. 1.6, JAN. 19, 1999

P/N: PM0340

15

MX28F1000P

AUTOMATIC PROGRAMMING TIMING WAVEFORM

One byte data is programmed. Verify in fast algorithm

and additional programming by external control are not

required because these operations are excuted auto-

matically by internal control circuit. Programming

completion can be verified by DATA polling and toggle bit

checking after automatic verify starts. Device outputs

DATAduringprogrammingandDATAafterprogramming

onQ7. Q0 toQ5(Q6isfortogglebit;seetogglebit, DATA

polling, timing waveform) are in high impedance.

Setup auto program/

Auto program & DATA polling

program command

Vcc 5V

12V

Vpp

tVPH

0V

tVPS

Address

valid

A0 ~ A16

tAS

WE

tAH1

tAVT

tCWC

CE

tCESC

tCEPH1

tCES

tCEP tCESP

tCEP

tOES

OE

Q7

tDS

tDH

tDS

tDH

tDF

DATA

tDPA

Command in

Data in

DATA

DATA polling

Command in

Data in

Q0~Q5

DATA

Command #40H

REV. 1.6, JAN. 19, 1999

P/N: PM0340

16

MX28F1000P

AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART

START

Apply VppH

Write Set up auto program Command (40H)

Write Auto program Command(A/D)

NO

Toggle Bit Checking

DQ6 not Toggled

YES

NO

Verify Byte Ok

YES

Reset

NO

Last Byte

YES

Auto Program Failed

Auto Program Completed

REV. 1.6, JAN. 19, 1999

P/N: PM0340

17

MX28F1000P

AUTOMATIC CHIP ERASE TIMING WAVEFORM

All data in chip are erased. External erase verify is not

requiredbecausedatais erasedautomaticallybyinternal

control circuit. Erasure completion can be verified by

DATA polling and toggle bit checking after automatic

erase starts. Device outputs 0 during erasure and 1 after

erasure on Q7. Q0 to Q5 (Q6 is for toggle bit; see toggle

bit, DATA polling, timing waveform) are in high imped-

ance.

Setup auto chip erase/

erase command

Auto chip erase & DATA polling

Vcc 5V

12V

Vpp

tVPH

tVPS

0V

A0 ~ A16

WE

CE

tAETC

tCWC

tCEP

tCES

tCEP tCESP

tCESC

tDF

tCEPH1

tDH

tOES

OE

Q7

tDS

tDH

tDPA

Command in

DATA polling

Command in

Q0~Q5

Command #30H

REV. 1.6, JAN. 19, 1999

P/N: PM0340

18

MX28F1000P

AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART

START

Apply VppH

Write Set up auto chip Erase Command (30H)

Write Auto chip Erase Command(30H)

Toggle Bit Checking

DQ6 not Toggled

No

YES

DATA Polling

DQ7 = 1

Reset

YES

Auto Chip Erase Completed

Auto Chip Erase Failed

REV. 1.6, JAN. 19, 1999

P/N: PM0340

19

MX28F1000P

AUTOMATIC BLOCK ERASE TIMING WAVEFORM

Block data indicated by A12 to A16 are erased. External

erase verify is not required because data are erased

automatically by internal control circuit. Erasure comple-

tion can be verified by DATA polling and toggle bit

checking after automatic erase starts. Device outputs 0

during erasure and 1 after erasure on Q7. Q0 to Q5 (Q6

is for toggle bit; see toggle bit, DATA polling, timing

waveform) are in high impedance.

Auto block erase & DATA polling

Setup auto block erase/erase command

Vcc 5V

12V

Vpp

tVPH

0V

tVPS

A0 ~ A11

Block

A12 ~ A16

CE

address 0 address 1

address #

tAH1

tCH

tCS

tAS

tCWC

tAH

tCESC

tAETB

tBAL

tBALC

WE

tCEPH1

tOES tCEP

tCEP tCEPH2

OE

Q7

tDF

tDS tDH tDS tDH

tDPA

Command in Command in

DATA polling

Command in Command in

Q0~Q5

Command #20H Command #D0H

*Refer to page 2 for detailed block address.

REV. 1.6, JAN. 19, 1999

P/N: PM0340

20

MX28F1000P

AUTOMATIC BLOCK ERASE ALGORITHM FLOWCHART

START

Apply VppH

Write Set up auto block Erase Command (20H)

Write Auto block Erase Command(D0H)

to Load Block Address

Load Block Address

Last Block

to Erase

NO

YES

Wait 200us

Toggle Bit Checking

DQ6 not Toggled

NO

YES

NO

DATA Polling

DQ7 = 1

Reset

YES

Auto Block Erase Completed

Auto Block Erase Failed

REV. 1.6, JAN. 19, 1999

P/N: PM0340

21

MX28F1000P

COMPATIBLE CHIP ERASE TIMING WAVEFORM

All data in chip are erased. Control verification and

additionalerasureexternallyaccordingtocompatiblechip

erase flowchart.

Setup chip erase/

Chip erase

Erase Verify

erase command

Vcc 5V

12V

Vpp

tVPH

0V

tVPS

Verify

A0 ~ A16

WE

Address

tAH

tAS

tCESV

tET

tCWC

CE

tCESC

tCES

tCEP

tDS

tOES tCEP

tCEP

tCEPH1

OE

Q7

tVA

tDS tDH

tDH

tDF

Command in

Data valid

Command in

Data valid

Q0~Q6

Command #20H Command #20H

Command #A0H

REV. 1.6, JAN. 19, 1999

P/N: PM0340

22

MX28F1000P

COMPATIBLE BLOCK ERASE

x 8 block) without any voltage stress to the device nor

deterioration in reliability of data.

This device can be applied to the compatible block erase

algorithmshowninthefollowingflowchart. Thisalgorithm

allows to obtain faster erase time by the block (16K byte

COMPATIBLE BLOCK ERASE FLOWCHART

START

For selected block(s),

All bits PGM"0"

N = 0

BLOCK ERASE FLOW

N = N+1

FAIL

NO

N = 1024?

ERSVFY FLOW

YES

ALL BITS VERIFIED

BLOCK ERASE FAIL

APPLY

VPP = VCC

END

BLOCK ERASE

COMPLETE

BLOCK ERASE FLOW

START

Apply

VPP = VPPH

WRITE SETUP BLOCK ERASE COMMAND

( 60H )

WRITE BLOCK ERASE COMMAND

( LOAD FIRST SECTOR ADDRESS , 60H )

LOAD OTHER SECTORS' ADDRESS

IF NECESSARY

( LOAD OTHER SECTOR ADDRESS )

WAIT

10 ms

END

REV. 1.6, JAN. 19, 1999

P/N: PM0340

23

MX28F1000P

ERASE VERIFY FLOW

START

APPLY

VPP = VPPH

ADDRESS =

FIRST ADDRESS OF ERASED BLOCKS

OR LAST VERIFY FAILED ADDRESS

WRITE ERASE VERIFY COMMAND

( A0H )

WAIT 6 us

NO

ERSVFY

FFH ?

INCREMENT ADDRESS

YES

NO

LAST ADDRESS ?

YES

GO TO ERASE FLOW

AGAIN OR ABORT

ERASE VERIFY

COMPLETE

REV. 1.6, JAN. 19, 1999

P/N: PM0340

24

MX28F1000P

COMPATIBLE BLOCK ERASE TIMING WAVEFORM

Indicated block data (16 Kbyte) are erased. Control

verificationandadditionalerasureexternallyaccordingto

compatible block erase flowchart.

Setup block erase/erase command

Block erase

Erase Verify

Vcc 5V

12V

Vpp

0V

tVPH

tVPS

Verify

address

A0 ~ A13

Block

Verify

address

Block

address #

A14 ~ A16

WE

address 0 address 1

tAS tAH

tAS

tAH

tCWC

tBALC

tBAL

tCESV

tET

CE

OE

tCEPH1

tCEP

tCESC

tDF

tCEP

tDS

tOES tCEP

tCEPH2

tCES

tVA

tDS tDH tDS tDH

Command in Command in

tDH

Command in

Q7

Data valid

Command in Command in

Command in

Q0~Q6

Command #60H Command #60H

Command #A0H

REV. 1.6, JAN. 19, 1999

P/N: PM0340

25

MX28F1000P

VPP HIGH READ TIMING WAVEFORM

Vcc 5V

12V

Vpp

tVPS

tVPH

0V

A0 - A16

Address valid

tCWC

WE

tACC

tCESC

CE

tOES

tCEP

tCEPH1

tDH

tCE

OE

tDF

tDS

tOE

tOH

Q0-Q7

Data out valid

Command in

00H

VPP LOW ID CODE READ TIMING WAVEFORM

VID

VIH

A9

VIL

A0

A1 - A8

A10-A16

tACC

VIH

WE

CE

tCE

OE

tDF

tOE

tOH

Manufacturer code

C2H

Device code

1AH

Q0 - Q7

REV. 1.6, JAN. 19, 1999

P/N: PM0340

26

MX28F1000P

VPP HIGH ID CODE READ TIMING WAVEFORM

Vcc 5V

12V

Vpp

tVPS

tVPH

0V

A0

Address Valid 0 or 1

A1 - A16

tCWC

WE

tACC

tCESC

tOES

CE

tOES

tCEP

tDS

tCEPH2

tDH

tCE

OE

tDF

tOE

tOH

Q0-Q7

Data out valid

Command in

90H

C2H or 1AH

RESET TIMING WAVEFORM

Vcc 5V

12V

Vpp

tVPS

0V

A0 - A16

tCWC

WE

CE

tOES

tCEP

tDS

tCEPH1

tDH

OE

tDS

tDH

Command in

FFH

Q0-Q7

Command in

FFH

REV. 1.6, JAN. 19, 1999

P/N: PM0340

27

MX28F1000P

TOGGLE BIT, DATA POLLING TIMING WAVEFORM

Toggle bit appears in Q6, when program/erase is

opperating. DATA polling appears in Q7 during pro-

gramming or erase.

HIGH

WE

Vpp 12V

CE

OE

TOGGLE BIT

HIGH-Z

Q6

DATA

DURING P/E

DATA POLLING

DATA

HIGH-Z

Q7

DURING P

DATA

PROGRAM/ERASE COMPLETE

Q7

DURING E

DATA POLLING

HIGH-Z

Q0~Q5

DATA

ERASE AND PROGRAMMING PERFORMANCE

LIMITS

TYP.

1.5

PARAMETER

MIN.

MAX.

20

UNITS

sec

Chip/Sector Erase Time

Chip Programming Time

Erase/Program Cycles

Byte Program Time

2

13.8

sec

10,000

cycles

us

15

642

REV. 1.6, JAN. 19, 1999

P/N: PM0340

28

MX28F1000P

ORDERING INFORMATION PLASTIC PACKAGE

PART NO.

ACCESS TIME

OPERATING

STANDBY

CURRENT

MAX.(uA)

100

PACKAGE

ERASE/PROGRAM

CYCLE

CURRENT

(ns)

70

MAX.(mA)

MIN.(time)

10,000

MX28F1000PPC-70C4

MX28F1000PPC-90C4

MX28F1000PPC-12C4

MX28F1000PQC-70C4

MX28F1000PQC-90C4

MX28F1000PQC-12C4

MX28F1000PTC-70C4

50

32 Pin DIP

90

100

32 Pin DIP

10,000

120

70

100

32 Pin DIP

10,000

100

32 Pin PLCC

32 Pin TSOP

(Normal Type)

32 Pin TSOP

(Normal Type)

32 Pin TSOP

(Normal Type)

32 Pin TSOP

(Reverse Type)

32 Pin TSOP

(Reverse Type)

32 Pin TSOP

(Reverse Type)

32 Pin DIP

10,000

90

100

10,000

120

70

100

10,000

100

10,000

MX28F1000PTC-90C4

MX28F1000PTC-12C4

MX28F1000PRC-70C4

MX28F1000PRC-90C4

MX28F1000PRC-12C4

90

50

100

10,000

120

70

90

120

MX28F1000PPI-70

MX28F1000PPI-90

MX28F1000PPI-12

MX28F1000PQI-70

MX28F1000PQI-90

MX28F1000PQI-12

MX28F1000PTI-70

70

50

100

10,000

90

32 Pin DIP

120

70

32 Pin DIP

32 Pin PLCC

32 Pin TSOP

(Normal Type)

32 Pin TSOP

(Normal Type)

32 Pin TSOP

(Normal Type)

32 Pin TSOP

(Reverse Type)

32 Pin TSOP

(Reverse Type)

32 Pin TSOP

(Reverse Type)

90

120

70

MX28F1000PTI-90

MX28F1000PTI-12

MX28F1000PRI-70

MX28F1000PRI-90

MX28F1000PRI-12

90

50

100

10,000

120

70

90

120

REV. 1.6, JAN. 19, 1999

P/N: PM0340

29

MX28F1000P

PACKAGE INFORMATION

32-PIN PLASTIC DIP

ITEM

A

MILLIMETERS INCHES

42.13 max.

1.90 [REF]

2.54 [TP]

.46 [Typ.]

38.07

1.660 max.

.075 [REF]

.100 [TP]

32

17

B

C

D

E

.050 [Typ.]

1.500

F

1.27 [Typ.]

3.30 ± .25

.51 [REF]

3.94 ± .25

5.33 max.

15.22 ± .25

13.97 ± .25

.25 [Typ.]

.050 [Typ.]

.130 ± .010

.020 [REF]

1.55 ± .010

.210 max.

.600 ± .101

.550 ± .010

.010 [Typ.]

16

1

G

H

I

A

K

L

J

I

J

K

H

G

L

M

F

C

0~15¡

D

M

NOTE: Each lead certerline is located within

.25mm[.01 inch] of its true position [TP] at a

maximum at maximum material condition.

B

E

32-PIN PLASTIC LEADED CHIP CARRIER (PLCC)

A

ITEM

MILLIMETERS INCHES

B

1

A

B

C

D

E

F

G

H

I

12.44 ± .13

11.50 ± .13

14.04 ± .13

14.98 ± .13

1.93

.490 ± .005

.453 ± .005

.553 ± .005

.590 ± .005

.076

4

32

30

5

29

3.30 ± .25

2.03 ± .13

.51 ± .13

1.27 [Typ.]

.71 [REF]

.46 [REF]

10.40/12.94

(W) (L)

.89R

.130 ± .010

.080 ± .005

.020 ± .005

.050 [Typ.]

.028 [REF]

.018 [REF]

.410/.510

(W) (L)

9

25

C

D

J

13

21

K

L

14

20

17

M

N

.035R

E

.25[Typ.]

.010[Typ.]

F

N

G

H

NOTE: Each lead certerline is located within

.25mm[.01 inch] of its true position [TP] at a

maximum at maximum material condition.

M

I

J

K

L

REV. 1.6, JAN. 19, 1999

P/N: PM0340

30

MX28F1000P

32-PIN PLASTIC TSOP

ITEM

A

MILLIMETERS INCHES

20.0 ± .20

18.40 ± .10

8.20 max.

0.15 [Typ.]

.80 [Typ.]

.20 ± .10

.30 ± .10

.50 [Typ.]

.45 max.

0 ~ .20

.078 ± .006

.724 ± .004

.323 max.

.006 [Typ.]

.031 [Typ.]

.008 ± .004

.012 ± .004

.020 [Typ.]

.018 max.

0 ~ .008

A

B

C

D

E

C

F

G

H

I

O

N

M

J

K

1.00 ± .10

1.27 max.

.50

.039 ± .004

.050 max.

.020

L

M

N

K

L

D

0 ~5°

.500

J

E

I

F

H

G

NOTE: Each lead certerline is located within

.25mm[.01 inch] of its true position [TP] at a

maximum at maximum material condition.

REV. 1.6, JAN. 19, 1999

P/N: PM0340

31

MX28F1000P

Note. Revision History

Revision # Description

Page

Date

1.4

Fast access time 150ns and 1,000 times erase cycles removed.

Tsop pin configuration diagram rotated 180°.

The flow chart of block erase corrected.

1.5

1.6

Fast access time 70ns added.

Dec/26/1996

JAN/19/1999

1)Absolute max. ratings:TA=-40°C to 85°C

2)DC Characteristics:ICC1=35mA for TA=-40°C to 85°C

3)AC Characteristics:TA=-40°C to 85°C

4)Order Informance:Add Industrial Grade

5)Erase & Programming Performance:New in Creased table

P11

P14

P29

REV. 1.6, JAN. 19, 1999

P/N: PM0340

32

MX28F1000P

MACRONIX INTERNATIONAL CO., LTD.

HEADQUARTERS:

TEL:+886-3-578-8888

FAX:+886-3-578-8887

EUROPE OFFICE:

TEL:+32-2-456-8020

FAX:+32-2-456-8021

JAPAN OFFICE:

TEL:+81-44-246-9100

FAX:+81-44-246-9105

SINGAPORE OFFICE:

TEL:+65-747-2309

FAX:+65-748-4090

TAIPEI OFFICE:

TEL:+886-3-509-3300

FAX:+886-3-509-2200

MACRONIX AMERICA, INC.

TEL:+1-408-453-8088

FAX:+1-408-453-8488

CHICAGO OFFICE:

TEL:+1-847-963-1900

FAX:+1-847-963-1909

http : //www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice.

33


型号：	MX28F1000PQC-12C4
厂家：	MACRONIX INTERNATIONAL
描述：	1M-BIT [128K x 8] CMOS FLASH MEMORY 1M - BIT [ 128K ×8 ] CMOS FLASH MEMORY 闪存存储内存集成电路
文件：	总33页 (文件大小：126K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MX28F1000PQC-12C4 [Macronix]

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SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E