首页 |元器件品牌

MX28F128J3TBC-15C3 [Macronix]

Flash, 8MX16, 150ns, PDSO48, 12 X 20 MM, PLASTIC, TSOP1-48;
MX28F128J3TBC-15C3
型号： MX28F128J3TBC-15C3
厂家： MACRONIX INTERNATIONAL    MACRONIX INTERNATIONAL
描述：

Flash, 8MX16, 150ns, PDSO48, 12 X 20 MM, PLASTIC, TSOP1-48

光电二极管 内存集成电路
文件： 总56页 (文件大小：1608K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
ADVANCED INFORMATION  
MX28F320J3/640J3/128J3  
32M/64M/128M[x8/x16] SINGLE3VPAGEMODEFLASHMEMORY  
FEATURES  
• 2.7V to 3.6V operation voltage  
• Block Structure  
Software Feature  
• Support Common Flash Interface (CFI)  
- 32 x 128Kbyte Erase Blocks (32M)  
- 64 x 128Kbyte Erase Blocks (64M)  
- 128 x 128Kbyte Erase Blocks (128M)  
• Fast random / page mode access time  
- 120/25 ns Read Access Time (32M)  
- 120/25 ns Read Access Time (64M)  
- 150/25 ns Read Access Time (128M)  
• 128-bit Protection Register  
- Flash device parameters stored on the device and  
provide the host system to access.  
• Automation Suspend Options  
- Block Erase Suspend to Read  
- Block Erase Suspend to Program  
- Program Suspend to Read  
Hardware Feature(Not for 48-TSOP/48-RTSOP)  
• A0 pin  
- 64-bit Unique Device Identifier  
- 64-bit User Programmable OTP Cells  
• 32-Byte Write Buffer  
- Select low byte address when device is in byte mode.  
Not used in word mode.  
- 6 us/byte Effective Programming Time  
• Enhanced Data Protection Features Absolute Protec-  
tion with VPEN = GND  
• STS pin  
- Indicates the status of the internal state machine.  
• VPEN pin  
- Flexible Block Locking  
- For Erase /Program/ Block Lock enable.  
• VCCQ Pin  
- Block Erase/Program Lockout during PowerTransi-  
tions  
-The output buffer power supply, control the device 's  
output voltage.  
Performance  
• Low power dissipation  
Packaging  
- typical 15mA active current for page mode read  
- 80uA/(max.) standby current  
- Deep power-down current: 5uA  
• High Performance  
- 48-LeadTSOP (for MX28F128J3)  
- 48-Lead RTSOP (for MX28F128J3)  
- 56-LeadTSOP  
- 48-ball Flip Chip CSP (for MX28F320J3/640J3)  
- 64-ball CSP  
- Block erase time: 2s typ.  
- Byte programming time: 210us typ.  
- Block programming time: 0.8s typ. (using Write to  
Buffer Command)  
Technology  
- MX28F128J3 using Nbit (0.25u) FlashTechnology  
- MX28F320J3/640J3 using Nbit (0.35u) FlashTech-  
nology  
• Program/Erase Endurance cycles:  
five grades-- "C1" stands for 10 cycles  
"C2" stands for 100 cycles  
"C3" stands for 1,000 cycles  
"C4" stands for 10,000 cycles  
"C5" stands for 100,000 cycles  
(please refer to Ordering Information of page 47)  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
1
MX28F320J3/640J3/128J3  
GENERAL DESCRIPTION  
The MXIC's MX28F320J3/640J3/128J3 series Flash use  
the most advance 2 bits/cell Nbit technology, double the  
storage capacity of memory cell.The device provide the  
high density Flash memory solution with reliable perfor-  
mance and most cost-effective.  
enable (CE0, CE1, CE2) and output enable (OE) con-  
trols.The device augment EPROM functionality with in-  
circuit electrical erasure and programming. The device  
uses a command register to manage this functionality.  
The MXIC's Nbit technology reliably stores memory con-  
tents even after the specific erase and program cycles.  
The MXIC cell is designed to optimize the erase and  
program mechanisms by utilizing the dielectric's charac-  
ter to trap or release charges from ONO layer.  
The device organized as by 8 bits or by 16 bits of output  
bus.The device is packaged in 48-LeadTSOP, 48-Lead  
RTSOP, 56-Lead TSOP, 48-ball Flip Chip CSP and 64-  
ball CSP. It is designed to be reprogrammed and erased  
in system or in standard EPROM programmers.  
The device uses a 2.7V to 3.6V VCC supply to perform  
the High Reliability Erase and auto Program/Erase algo-  
rithms.  
The device offers fast access time and allowing opera-  
tion of high-speed microprocessors without wait states.  
To eliminate bus contention, the device has separate chip  
The highest degree of latch-up protection is achieved  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
2
MX28F320J3/640J3/128J3  
PIN CONFIGURATION  
48-TSOP (12mm x 20mm) (for MX28F128J3 word mode only)  
WE  
A17  
A16  
A15  
A14  
A13  
A12  
A11  
A10  
A9  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
GND  
GND  
Q15  
Q7  
2
3
4
5
Q14  
Q6  
6
7
Q13  
Q5  
8
9
Q12  
Q4  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
A20  
A22  
A21  
A19  
A18  
A8  
VCC  
VCC  
A23  
Q11  
Q3  
MX28F128J3 (x16 only)  
Normal Type  
Q10  
Q2  
A7  
A6  
Q9  
A5  
Q1  
A4  
Q8  
A3  
Q0  
A2  
OE  
A1  
GND  
RESET(*)  
CE0  
(* RESET pin : high enable)  
48-RTSOP (12mm x 20mm) (for MX28F128J3 word mode only)  
GND  
GND  
Q15  
Q7  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1
2
WE  
A17  
A16  
A15  
A14  
A13  
A12  
A11  
A10  
A9  
3
4
Q14  
Q6  
5
6
Q13  
Q5  
7
8
Q12  
Q4  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
VCC  
VCC  
A23  
Q11  
Q3  
A20  
A22  
A21  
A19  
A18  
A8  
MX28F128J3 (x16 only)  
Reverse Type  
Q10  
Q2  
A7  
Q9  
A6  
Q1  
A5  
Q8  
A4  
Q0  
A3  
OE  
A2  
GND  
RESET(*)  
A1  
CE0  
(* RESET pin : high enable)  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
3
MX28F320J3/640J3/128J3  
56 TSOP (14mm x 20mm)  
A22  
1
2
3
4
5
6
7
8
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
NC  
WE  
OE  
STS  
Q15  
Q7  
Q14  
Q6  
GND  
Q13  
Q5  
Q12  
Q4  
VCCQ  
GND  
Q11  
Q3  
Q10  
Q2  
CE1  
A21  
A20  
A19  
A18  
A17  
A16  
VCC  
A15  
A14  
A13  
A12  
CE0  
VPEN  
RESET  
A11  
A10  
A9  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
A8  
VCC  
Q9  
Q1  
Q8  
Q0  
GND  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
BYTE  
A23  
CE2  
Notes:  
1. A22 exists on 64M, 128M densities. On 32M densities this pin is a no connect (NC).  
2. A23 exists on 128M densities. On 32M and 64M densities this pin is a no connect (NC).  
48 Flip Chip CSP (for MX28F320J3/640J3)  
1
2
3
4
5
6
7
8
A5  
A14  
A12  
A9  
VPEN  
VCC  
A20  
A8  
A
B
C
D
E
F
A15  
A16  
A11  
A13  
WE  
RESET  
A22  
A19  
A21  
A18  
A7  
A6  
A4  
A3  
A2  
A10  
13 mm  
A17  
Q14  
Q15  
Q7  
Q5  
Q6  
Q11  
Q12  
Q4  
Q2  
Q3  
Q8  
Q9  
CEO  
Q0  
A1  
VCCQ  
GND  
GND  
Q13  
VCC  
Q10  
Q1  
OE  
8mm  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
4
MX28F320J3/640J3/128J3  
64 Ball CSP (10x13x1.2mm, 1.0mm-ball pitch)  
1
2
3
4
5
6
7
8
A22  
A
B
C
D
E
F
A1  
A6  
A8  
VPEN  
A13  
VCC  
A18  
A2  
A3  
GND  
A7  
A9  
CE0  
A12  
A14  
A15  
DU  
DU  
A19  
A20  
CE1  
A21  
A10  
A4  
A5  
Q1  
Q0  
A11  
Q9  
RESET  
Q3  
DU  
Q4  
DU  
DU  
A16  
Q15  
A17  
STS  
13 mm  
Q8  
BYTE  
Q10  
Q2  
Q11  
Q12  
Q5  
DU  
DU  
Q14  
Q7  
OE  
WE  
NC  
G
H
A23  
CE2  
A0  
VCCQ  
GND  
Q6  
DU  
VCC  
Q13  
GND  
10mm  
Notes:  
1. Address A22 is only valid on 64M and 128M densities. Otherwise, it is a no connect (NC).  
2. Address A23 is only valid on 128M densities. Otherwise, it is a no connect (NC).  
3. Don't Use (DU) pins refer to pins that should not be connected.  
PIN DESCRIPTION  
SYMBOL  
STS  
PIN NAME  
SYMBOL  
A0  
PIN NAME  
STATUS Pin  
Byte Select Address  
Address Input (32M:A0~A21,  
64M:A0~A22, 128M:A0~A23)  
Data Inputs/Outputs  
BYTE  
VPEN  
Byte Mode Enable  
ERASE/PROGRAM/BLOCK Lock  
Enable  
A1~A23  
Q0~Q15  
VCCQ  
VCC  
GND  
NC  
Output Buffer Power Supply  
Device Power Supply  
Device Ground  
CE0, CE1, CE2 Chip Enable Input  
WE  
Write Enable Input  
OE  
Output Enable Input  
Pin Not Connected Internally  
Don't Use  
RESET  
Reset/Deep Power Down mode  
(low enable for 56-TSOP & 64-CSP)  
Reset/Deep Power Down mode  
(high enable for 48-TSOP &  
48-RTSOP)  
DU  
RESET  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
5
MX28F320J3/640J3/128J3  
BLOCK DIAGRAM  
CE0  
CE1  
CE2  
OE  
WE  
WRITE  
CONTROL  
INPUT  
PROGRAM/ERASE  
HIGH VOLTAGE  
STATE  
MACHINE  
(WSM)  
LOGIC  
RESET(*)  
STATE  
REGISTER  
ADDRESS  
LATCH  
FLASH  
ARRAY  
ARRAY  
A0-A23  
SOURCE  
HV  
AND  
COMMAND  
DATA  
BUFFER  
Y-PASS GATE  
DECODER  
PGM  
DATA  
HV  
SENSE  
AMPLIFIER  
COMMAND  
DATA LATCH  
PROGRAM  
DATA LATCH  
I/O BUFFER  
Q0-Q15  
* : RESET pin for 56-TSOP & 64-CSP; RESET pin for 48-TSOP & 48-RTSOP.  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
6
MX28F320J3/640J3/128J3  
Figure 1. Block Architecture  
Flash memory reads erases and writes in-system via the local CPU. All bus cycles to or from the flash memory  
conform to standard microprocessor bus cycles.  
A[23-0]: 128Mbit  
A[22-0]: 64Mbit  
A[21-0]: 32Mbit  
A[23-1]: 128Mbit  
A[22-1]: 64Mbit  
A[21-1]: 32Mbit  
7FFFFF  
7F0000  
FFFFFF  
FE0000  
127  
127  
128-Kbyte Block  
64-Kword Block  
.
.
.
.
.
.
7FFFFF  
7E0000  
3FFFFF  
3F0000  
63  
63  
128-Kbyte Block  
64-Kword Block  
.
.
.
.
.
.
3FFFFF  
3E0000  
1FFFFF  
1F0000  
128-Kbyte Block  
31  
31  
64-Kword Block  
.
.
.
.
.
.
03FFFF  
01FFFF  
128-Kbyte Block  
128-Kbyte Block  
1
0
1
0
64-Kword Block  
64-Kword Block  
020000  
01FFFF  
010000  
00FFFF  
000000  
000000  
Byte Mode (x8)  
Word Mode (x16)  
Table 1. Chip Enable Truth Table  
CE2  
VIL  
VIL  
VIL  
VIL  
VIH  
VIH  
VIH  
VIH  
CE1  
VIL  
VIL  
VIH  
VIH  
VIL  
VIL  
VIH  
VIH  
CE0  
VIL  
VIH  
VIL  
VIH  
VIL  
VIH  
VIL  
VIH  
DEVICE  
Enabled  
Disabled  
Disabled  
Disabled  
Enabled  
Enabled  
Enabled  
Disabled  
NOTE: For Single-chip applications, CE2 and CE1 can  
be strapped to GND.  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
7
MX28F320J3/640J3/128J3  
Table 2. Bus Operations  
Command  
Sequence  
Read  
Array  
Output Standby RESET Read ID Read  
Read  
Read  
Write  
Disable  
Mode/  
Deep  
Query Status  
Status  
(WSM off) (WSM on)  
Power  
Down  
Mode  
Notes  
4,5,6  
VIH  
6,10,11  
VIH  
RESET (12)  
VIH  
VIH  
VIL  
(12)  
VIH  
VIH  
VIH  
VIH  
Enabled  
VIL  
VIH  
X
CE0,CE1,CE2(1) Enabled Enabled Disabled X  
Enabled Enabled Enabled  
Enabled  
VIH  
OE (2)  
WE (2)  
Address  
VPEN  
Q (3)  
VIL  
VIH  
X
VIH  
VIH  
X
X
X
X
X
X
X
X
X
VIL  
VIH  
See  
VIL  
VIH  
See  
VIL  
VIH  
X
VIL  
X
Figure 2 Table 6  
X
X
X
X
X
X
VPENH  
Data out High Z High Z  
High Z Note 8  
Note 9 Data out Q7=Data out Data in  
Q15-8=High Z  
Q6-0=High Z  
STS  
High Z  
(7)  
X
X
High Z High Z  
High Z  
(7)  
X
(default mode)  
(7)  
(7)  
NOTES:  
1. See Table 1 on page 7 for valid CE configurations.  
2. OE and WE should never be enabled simultaneously.  
3. DQ refers to Q0-Q7 if BYTE is low and Q0-Q15 if BYTE is high.  
4. Refer to DC Characteristics.When VPEN < VPENLK , memory contents can be read, but not altered.  
5. X can be VIL or VIH for control and address pins, and VPENLK or VPENH for VPEN . See DC Characteristics for  
VPENLK and VPENH voltages.  
6. In default mode, STS is VOL when the WSM is executing internal block erase, program, or lock-bit configuration  
algorithms. It is VOH when the WSM is not busy, in block erase suspend mode (with programming inactive),  
program suspend mode, or reset/deep power-down mode.  
7. High Z will be VOH with an external pull-up resistor.  
8. See Section , "Read Identifier Codes" for read identifier code data.  
9. See Section , "Read Query Mode Command" for read query data.  
10.Command writes involving block erase, program, or lock-bit configuration are reliably executed when VPEN=  
VPENH and VCC is within specification.  
11.Refer to Table 3 on page 10 for valid DIN during a write operation.  
12.RESET mode of 48-TSOP & 48-RTSOP types is high enabled to entering deep power down mode.  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
8
MX28F320J3/640J3/128J3  
FUNCTION  
OUTPUT DISABLE  
The device includes on-chip program/erase control cir-  
cuitry. The Write State Machine (WSM) controls block  
erase and byte/word/page program operations. Opera-  
tional modes are selected by the commands written to  
the Command User Interface (CUI).The Status Register  
indicates the status of the WSM and when the WSM  
successfully completes the desired program or block  
erase operation.  
When OE is atVIH, output from the devices is disabled.  
Data input/output are in a high-impedance(High-Z) state.  
STANDBY  
When CE0, CE1 and CE2 disable the device (see table1)  
and place it in standby mode.The power consumption of  
this device is reduced. Data input/output are in a high-  
impedance(High-Z) state. If the memory is deselected  
during block erase, program or lock-bit configuration, the  
internal control circuits remain active and the device con-  
sume normal active power until the operation completes.  
A Deep Powerdown mode is enabled when the RESET  
pin of 56-TSOP & 64-CSP types is at GND or RESET  
pin of 48-TSOP & 48-RTSOP is atVIH, minimizing power  
consumption.  
READ  
DEEP POWER-DOWN  
The device has three read modes, which accesses to  
the memory array, the Device Identifier or the Status  
Register independent of the VPEN voltage. The appro-  
priate read command are required to be written to the  
CUI. Upon initial device powerup or after exit from deep  
powerdown, the device automatically resets to read ar-  
ray mode. In the read array mode, low level input to CE0,  
CE1, CE2 and OE, high level input toWE and RESET or  
low level input to RESET, and address signals to the  
address inputs (A23-A0) output the data of the addressed  
location to the data input/output (Q15~Q0).  
When RESET pin of 56-TSOP & 64-CSP types is atVIL  
or RESET pin of 48-TSOP & 48-RTSOP types is atVIH,  
the device is in the deep power-down mode and its power  
consumption is substantially low around 5uA. During read  
modes, the memory is deselected and the data input/  
output are in a high-impedance(High-Z) state.To return  
from deep power down mode requires RESET pin of 56-  
TSOP & 64-CSP types at VIH or RESET pin of 48-  
RTSOP & 48-RTSOP types at VIL. After return from  
powerdown, the CUI is reset to Read Array , and the  
Status Register is set to value 80H.  
When reading information in read array mode, the de-  
vice defaults to asynchronous page mode. In this state,  
data is internally read and stored in a high-speed page  
buffer.A2:0 addresses data in the page buffer.The page  
size is 4 words or 8 bytes. Asynchronous word/byte mode  
is supported with no additional commands required.  
During block erase program or lock-bit configuration  
modes, RESET pin of 56-TSOP & 64-CSP types at VIL  
or RESET pin of 48-TSOP & 48-RTSOP types at VIH  
will abort either operation.Memory array data of the block  
being altered become invalid.  
In default mode, STS transitions low and remains low  
for a maximum time of tPLPH+tPHRH until the reset  
operation is complete. Memory contents being altered  
are no longer valid; the data may be partially corrupted  
after a program or partially altered after an erase or lock-  
bit configuration.Time tPHWL is required after RESET  
goes to logic-high (VIH) or RESET goes to VIL before  
another command can be written.  
WRITE  
Writes to the CUI enables reading of memory array data,  
device identifiers and reading and clearing of the Status  
Register and when VPEN=VPENH block erasure pro-  
gram and lock-bit configuration.The CUI is written when  
the device is enable, WE is active and OE is at high  
level. Address and data are latched on the earlier rising  
edge ofWE and CE.Standard micro-processor write tim-  
ings are used.  
READ QUERY  
The read query operation outputs block status informa-  
tion, CFI (Common Flash Interface) ID string, system  
interface information, device geometry information and  
MXIC extended query information.  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
9
MX28F320J3/640J3/128J3  
COMMAND DEFINITIONS  
Device operations are selected by writing specific address and data sequences into the CUI.Table 3 defines the valid  
register command sequences.  
When VPEN<VPENLK only read operations from the status register, query, indentifier code or blocks are enabled.  
WhenVPEN=VPENH enables block erase program and lock-bit configuration operations.  
Table 3. Command Definitions  
Command  
Sequence  
Read  
Array  
Read Read  
Read  
Clear  
Write to Word/byte Sector  
ID  
Query Status  
Status  
Buffer  
Program Erase  
Register Register  
Notes  
5
6
7,8,9  
10,11  
9,10  
Bus Write Cycles Req'd  
1
> 2  
> 2  
2
1
> 2  
2
2
First Bus  
Operation(2)  
Write  
X
Write Write  
Write  
X
Write  
X
Write  
BA  
Write  
X
Write  
BA  
Write Cycles Address(3)  
Data(4,5)  
X
X
FFH  
90H  
98H  
70H  
Read  
X
50H  
E8H  
Write  
BA  
40H/10H  
Write  
PA  
20H  
Write  
BA  
Second Bus Operation(2)  
Read Query Address(3)  
Data(4,5)  
Read Read  
IA  
ID  
QA  
QD  
SRD  
N
PD  
D0H  
Command  
Sequence  
Sector  
Erase,  
Program  
Suspend  
10,12  
Sector  
Configur-  
ation  
Set Sector Clear  
Protection  
Program  
Erase,  
Program  
Resume  
10  
Lock-Bit  
Sector  
Lock-Bit  
Notes  
13  
Bus Write Cycles Req'd  
1
1
2
2
2
2
First Bus  
Operation(2) Write  
Write  
X
Write  
X
Write  
X
Write  
X
Write  
X
Write Cycle Address(3)  
Data(4,5)  
X
B0H  
D0H  
B8H  
Write  
X
60H  
Write  
BA  
60H  
Write  
X
C0H  
Write  
PA  
Second Bus Operation(2)  
Write Cycle Address(3)  
Data(4,5)  
CC  
01H  
D0H  
PD  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
10  
MX28F320J3/640J3/128J3  
NOTES:  
1. Bus operations are defined inTable 2.  
2. X = Any valid address within the device.  
BA = Address within the block.  
IA = Identifier Code Address: see Figure 2 and Table 14.  
QA = Query database Address.  
PA = Address of memory location to be programmed.  
RCD = Data to be written to the read configuration register.This data is presented to the device on A 16-1 ;all other  
address inputs are ignored.  
3. ID = Data read from Identifier Codes.  
QD = Data read from Query database.  
SRD = Data read from status register. See Table 15 for a description of the status register bits.  
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.  
CC = Configuration Code.  
4. The upper byte of the data bus (Q8-Q15) during command writes is a "Don't Care" in x16 operation.  
5. Following the Read Identifier Codes command, read operations access manufacturer, device and block lock  
codes. See Section 4.3 for read identifier code data.  
6. If the WSM is running, only Q7 is valid; Q15-Q8 and Q6-Q0 float, which places them in a high impedance state.  
7. After the Write to Buffer command is issued check the XSR to make sure a buffer is available for writing.  
8. The number of bytes/words to be written to the Write Buffer = N + 1, where N = byte/word count argument.  
Count ranges on this device for byte mode are N = 00H to N = 1FH and for word mode are N = 0000H to N =000FH.  
The third and consecutive bus cycles, as determined by N, are for writing data into the Write Buffer.  
The Confirm command (D0H) is expected after exactly N + 1 write cycles; any other command at that point in the  
sequence aborts the write to buffer operation. Please see Figure 4. "Write to Buffer Flowchart" for additional  
information.  
9. The write to buffer or erase operation does not begin until a Confirm command (D0h) is issued.  
10.Attempts to issue a block erase or program to a locked block.  
11.Either 40H or 10H are recognized by the WSM as the byte/word program setup.  
12.Program suspends can be issued after either theWrite-to-Buffer orWord-/Byte-Program operation is initiated.  
13.The clear block lock-bits operation simultaneously clears all block lock-bits.  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
11  
MX28F320J3/640J3/128J3  
Figure 2. Device Identifier Code Memory Map  
A[23-1]:128 Mbit  
A[22-1]:64 Mbit  
A[21-1]:32 Mbit  
Word  
Address  
7FFFFF  
Block 127  
Reserved for Future  
Implementation  
7F0003  
7F0002  
Block 127 Lock Configuration  
Reserved for Future  
Implementation  
7F0000  
7EFFFF  
(Block 64 through 126)  
3FFFFF  
Block 63  
Reserved for Future  
Implementation  
3F0003  
3F0002  
Block 63 Lock Configuration  
Reserved for Future  
Implementation  
3F0000  
3EFFFF  
(Block 32 through 62)  
Block 31  
Reserved for Future  
Implementation  
1F0003  
1F0002  
Block 31 Lock Configuration  
Reserved for Future  
Implementation  
1F0000  
1EFFFF  
(Block 2 through 30)  
01FFFF  
Block 1  
Reserved for Future  
Implementation  
010003  
010002  
Block 1 Lock Configuration  
Reserved for Future  
Implementation  
010000  
00FFFF  
Block 0  
Reserved for Future  
Implementation  
000004  
000003  
000002  
000001  
Block 0 Lock Configuration  
Device Code  
Manufacturer Code  
000000  
NOTE:A0 is not used in either x8 or x16 mode when obtaining these identifier codes.Data is always given on the low  
byte in x16 mode (upper byte contains 00h).  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
12  
MX28F320J3/640J3/128J3  
Read Array Command  
The device is in Read Array mode on initial device power  
up and after exit from deep power down, or by writing  
FFH to the Command User Interface.The read configu-  
ration register defaults to asynchronous read page mode.  
The device remains enabled for reads until another com-  
mand is written.The Read Array command functions in-  
dependently of theVPEN voltage.  
Read Query Mode Command  
This section defines the data structure or "Database"  
returned by the Common Flash Interface (CFI) Query  
command. System software should parse this structure  
to gain critical information such as block size, density,  
x8/x16, and electrical specifications. Once this informa-  
tion has been obtained, the software will know which  
command sets to use to enable flash writes, block  
erases, and otherwise control the flash component.  
Query Structure Output  
The Query Database allows system software to gain in-  
formation for controlling the flash component.This sec-  
tion describes the device CFI-compliant interface that  
allows the host system to access Query data.  
Query data are always presented on the lowest-order  
data outputs (DQ 0-7) only.The numerical offset value is  
the address relative to the maximum bus width supported  
by the device. On this family of devices, the Query table  
device starting address is a 10h, which is a word ad-  
dress for x16 devices.  
For a word-wide (x16) device, the first two bytes of the  
Query structure, "Q" and "R" in ASCII, appear on the  
low byte at word addresses 10h and 11h.This CFI-com-  
pliant device outputs 00H data on upper bytes.Thus, the  
device outputs ASCII "Q" in the low byte (DQ 0-7 ) and  
00h in the high byte (DQ 8-15 ).  
At Query addresses containing two or more bytes of in-  
formation, the least significant data byte is presented at  
the lower address, and the most significant data byte is  
presented at the higher address.  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
13  
MX28F320J3/640J3/128J3  
In all of the following tables, addresses and data are represented in hexadecimal notation, so the "h" suffix has been  
dropped.In addition, since the upper byte of word-wide devices is always "00h",” the leading "00" has been dropped  
from the table notation and only the lower byte value is shown. Any x16 device outputs can be assumed to have 00h  
on the upper byte in this mode.  
Table 4. Summary of Query Structure Output as a Function of Device and Mode  
Device  
Query start location in  
maximum device bus  
width addresses  
Query data with maximum  
device bus width addressing  
Query data with byte  
addressing  
Type/Mode  
Hex  
Offset  
10:  
Hex  
Code  
0051  
0052  
0059  
ASCII  
Value  
"Q"  
Hex  
Hex  
Code  
51  
ASCII  
Offset  
20:  
Value  
"Q"  
x16 device  
x16 mode  
10h  
11:  
"R"  
21:  
00  
"Null"  
"R"  
12:  
"Y"  
22:  
52  
x16 device  
x8 mode  
20:  
51  
"Q"  
N/A (1)  
N/A (1)  
21:  
51  
"Q"  
22:  
52  
"R"  
NOTE:  
1. The system must drive the lowest order addresses to access all the device's array data when the device is  
configured in x8 mode.Therefore, word addressing, where these lower addresses are not toggled by the system, is  
"Not Applicable" for x8-configured devices.  
Table 5. Example of Query Structure Output of a x16- and x8-Capable Device  
Word Addressing  
Hex Code  
Byte Addressing  
Hex Code  
Offset  
A15-A0  
0010h  
0011h  
0012h  
0013h  
0014h  
0015h  
0016h  
0017h  
0018h  
...  
Value  
Offset  
A7-A0  
20h  
21h  
22h  
23h  
24h  
25h  
26h  
27h  
28h  
...  
Value  
D15 - D0  
D7 - D0  
0051  
0052  
0059  
P_IDLO  
P_IDHI  
PLO  
"Q"  
"R"  
51  
51  
"Q"  
"Q"  
"Y"  
52  
"R"  
PrVendor  
ID#  
52  
"R"  
59  
"Y"  
PrVendor  
TblAdr  
AltVendor  
ID#  
59  
"Y"  
PHI  
P_IDLO  
P_IDLO  
P_IDHI  
...  
PrVendor  
ID#  
A_IDLO  
A_IDHI  
...  
ID#  
...  
...  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
14  
MX28F320J3/640J3/128J3  
Query Structure Overview  
The Query command causes the flash component to display the Common Flash Interface (CFI) Query structure or  
"database". The structure sub-sections and address locations are summarized below.  
Table 6. Query Structure (1)  
Offset  
00h  
Sub-Section  
Name Description  
Manufacturer Code  
01h  
Device Code  
(BA+2)h (2)  
04-0Fh  
10h  
Block Status Register  
Reserved  
Block-Specific Information  
Reserved forVendor-Specific Information  
Reserved forVendor-Specific Information  
Command Set ID andVendor Data Offset  
Flash Device Layout  
CFI Query Identification String  
System Interface Information  
Device Geometry Definition  
Primary MXIC-Specific Extended  
QueryTable  
1Bh  
27h  
P (3)  
Vendor-Defined Additional Information Specific to the  
PrimaryVendor Algorithm  
NOTES:  
1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a  
function of device bus width and mode.  
2. BA = Block Address beginning location (i.e., 02000h is block 2s beginning location when the block size is 128  
Kbyte).  
3. Offset 15 defines "P" which points to the Primary Intel-Specific Extended Query Table.  
Block Status Register  
The block status register indicates whether an erase operation completed successfully or whether a given block is  
locked or can be accessed for flash program/erase operations.  
Table 7. Block Status Register  
Offset  
Length  
Description  
Address  
Value  
(BA+2)h (1)  
1
Block Lock Status Register  
BSR.0 Block Lock Status  
0 = Unlocked  
BA+2:  
--00 or --01  
BA+2:  
BA+2:  
(bit 0): 0 or 1  
(bit 1-7): 0  
1 = Locked  
BSR 1-7: Reserved for Future Use  
NOTE:  
1. BA =The beginning location of a Block Address (i.e., 008000h is block 1s (64-KB block) beginning location in word  
mode).  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
15  
MX28F320J3/640J3/128J3  
CFI Query Identification String  
The CFI Query Identification String provides verification that the component supports the Common Flash Interface  
specification. It also indicates the specification version and supported vendor-specified command set(s).  
Table 8. CFI Identification  
Offset  
Length  
Description  
Add.  
Hex  
Code  
--51  
--52  
--59  
--01  
--00  
--31  
--00  
--00  
--00  
--00  
--00  
Value  
10h  
3
Query-unique ASCII string "QRY"  
10  
11:  
12:  
13:  
14:  
15:  
16:  
17:  
18:  
19:  
1A:  
"Q"  
"R"  
"Y"  
13h  
15h  
17h  
19h  
2
2
2
2
Primary vendor command set and control interface ID code.  
16-bit ID code for vendor-specified algorithms  
Extended QueryTable primary algorithm address  
Alternate vendor command set and control interface ID code.  
0000h means no second vendor-specified algorithm exists  
Secondary algorithm Extended QueryTable address.  
0000h means none exists  
System Interface Information  
The following device information can optimize system interface software.  
Table 9. System Interface Information  
Offset  
Length  
Description  
Add.  
1B:  
1C:  
1D:  
1E:  
Hex  
Value  
2.7 V  
3.6 V  
0.0V  
0.0V  
Code  
1Bh  
1
VCC logic supply minimum program/erase voltage  
bits 0-3 BCD 100 mV  
--27  
--36  
--00  
--00  
bits 4-7 BCD volts  
1Ch  
1Dh  
1Eh  
1
1
1
VCC logic supply maximum program/erase voltage  
bits 0-3 BCD 100 mV  
bits 4-7 BCD volts  
VPP [programming] supply minimum program/erase voltage  
bits 0-3 BCD 100 mV  
bits 4-7 HEX volts  
VPP [programming] supply maximum program/erase voltage  
bits 0-3 BCD 100 mV  
bits 4-7 HEX volts  
1Fh  
20h  
21h  
22h  
23h  
24h  
25h  
26h  
1
1
1
1
1
1
1
1
"n" such that typical single word program time-out = 2us  
"n" such that typical max. buffer write time-out = 2us  
"n" such that typical block erase time-out = 2ms  
"n" such that typical full chip erase time-out = 2ms  
1F:  
20:  
21:  
22:  
--07  
--07  
--0A  
--00  
--04  
--04  
--04  
--00  
128us  
128us  
1s  
NA  
"n" such that maximum word program time-out = 2 times typical 23:  
2ms  
2ms  
16s  
"n" such that maximum buffer write time-out = 2 times typical  
"n" such that maximum block erase time-out = 2 times typical  
"n" such that maximum chip erase time-out = 2 times typical  
24:  
25:  
26:  
NA  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
16  
MX28F320J3/640J3/128J3  
Device Geometry Definition  
This field provides critical details of the flash device geometry.  
Table 10. Device Geometry Definition  
Offset Length  
Description  
Code See Table  
Below  
27h  
28h  
1
2
"n" such that device size = 2n in number of bytes  
Flash device interface: x8 async(28:00,29:00),  
27:  
28:  
29:  
2A:  
2B:  
--02 x8/x16  
x16 async(28:01,29:00), x8/x16 async(28:02,29:00)  
"n" such that maximum number of bytes in write buffer = 2n  
--00  
--05  
--00  
2Ah  
2
32  
1
Number of erase block regions within device:  
1. x = 0 means no erase blocking; the device erases in "bulk"  
2. x specifies the number of device or partition regions with one or  
more contiguous same-size erase blocks  
2Ch  
2Dh  
1
4
2C:  
--01  
3. Symmetrically blocked partitions have one blocking region  
4. Partition size = (total blocks) x (individual block size)  
Erase Block Region 1 Information  
2D:  
2E:  
2F:  
30:  
bits 0-15 = y, y+1 = number of identical-size erase blocks  
bits 16-31 = z, region erase block(s) size are z x 256 bytes  
Device Geometry Definition  
Address  
27:  
32M  
--16  
--02  
--00  
--05  
--00  
--01  
--1F  
--00  
--00  
--02  
64M  
--17  
--02  
--00  
--05  
--00  
--01  
--3F  
--00  
--00  
--02  
128M  
--18  
--02  
--00  
--05  
--00  
--01  
--7F  
--00  
--00  
--02  
28:  
29:  
2A:  
2B:  
2C:  
2D:  
2E:  
2F:  
30:  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
17  
MX28F320J3/640J3/128J3  
Primary-Vendor Specific Extended Query Table  
Certain flash features and commands are optional.The PrimaryVendor-Specific Extended Query table specifies this  
and other similar information.  
Table 11. Primary Vendor-Specific Extended Query  
Offset(1) Length Description  
Add.  
Hex  
Code  
--50  
--52  
--49  
--31  
--31  
--0A  
--00  
--00  
--00  
Value  
P=31h  
(P+0)h  
(P+1)h  
(P+2)h  
(P+3)h  
(P+4)h  
(P+5)h  
(P+6)h  
(P+7)h  
(P+8)h  
(Optional Flash Features and Commands)  
3
Primary extended query table  
Unique ASCII string "PRI"  
31:  
32:  
33:  
34:  
35:  
36:  
37:  
38:  
39:  
"P"  
"R"  
"I"  
1
1
Major version number, ASCII  
"1"  
"1"  
Minor version number, ASCII  
Optional feature and command support (1=yes, 0=no)  
bits 9-31 are reserved; undefined bits are "0". If bit 31 is  
"1" then another 31 bit field of optional features follows at  
the end of the bit-30 field.  
bit 0 Chip erase supported  
bit 0 = 0  
No  
Yes  
Yes  
Yes(1)  
No  
4
bit 1 Suspend erase supported  
bit 1 = 1  
bit 2 = 1  
bit 2 Suspend program supported  
bit 3 Legacy lock/unlock supported  
bit 4 Queued erase supported  
bit 3 = 1(1)  
bit 4 = 0  
bit 5 = 0  
bit 6 = 1  
bit 7 = 1  
bit 8 = 0  
bit 5 Instant Individual block locking supported  
bit 6 Protection bits supported  
No  
Yes  
Yes  
No  
bit 7 Page-mode read supported  
bit 8 Synchronous read supported  
(P+9)h  
1
Supported functions after suspend:read Array, Status,Query  
Other supported operations are:  
3A:  
--01  
bit 0 = 1  
bits 1-7 reserved; undefined bits are "0"  
bit 0 Program supported after erase suspend  
Block status register mask  
Yes  
(P+A)h  
(P+B)h  
3B:  
3C:  
--01  
--00  
2
1
1
bits 2-15 are Reserved; undefined bits are "0"  
bit 0 Block Lock-Bit Status register active  
bit 1 Block Lock-Down Bit Status active  
VCC logic supply highest performance program/erase voltage  
bits 0-3 BCD value in 100 mV  
bit 0 = 1  
bit 1 = 0  
Yes  
No  
(P+C)h  
(P+D)h  
3D:  
3E:  
--33  
--00  
3.3V  
0.0V  
bits 4-7 BCD value in volts  
VPP optimum program/erase supply voltage  
bits 0-3 BCD value in 100 mV  
bits 4-7 HEX value in volts  
NOTE:  
1.Future devices may not support the described "Legacy Lock/Unlock" function.Thus bit 3 would have a value of "0".  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
18  
MX28F320J3/640J3/128J3  
Table 12. Protection Register Information  
Offset(1) Length Description  
Add. Hex  
Code  
Value  
P=31h  
(Optional Flash Features and Commands)  
(P+E)h  
1
Number of Protection register fields in JEDEC ID space.  
"00h," indicates that 256 protection bytes are available  
Protection Field 1: Protection Description  
3F:  
--01  
01  
This field describes user-available OneTime Programmable  
(OTP) protection register bytes.Some are pre-programmed  
with device-unique serial numbers. Others are user-programmable.  
Bits 0-15 point to the protection register lock  
(P+F)h  
(P+10)h  
(P+11)h  
(P+12)h  
40:  
--00  
00h  
byte, the section's first byte. The following bytes are factory  
pre-programmed and user-programmable.  
bits 0-7 = Lock/bytes JEDEC-plane physical low address  
bits 8-15 = Lock/bytes JEDEC-plane physical high address  
bits 16-23 = "n" such that 2 n = factory pre-programmed bytes  
bits 24-31 = "n" such that 2 n = user-programmable bytes  
NOTE:  
1.The variable P is a pointer which is defined at CFI offset 15h.  
Table 13. Page Read Information  
Offset(1) Length Description  
Add.  
Hex  
Value  
P=31h  
(Optional Flash Features and Commands)  
Code  
Page Mode Read capability  
bits 0-7 = "n" such that 2n HEX value represents the number  
of read-page bytes. See offset 28h for device word width to  
determine page-mode data output width. 00h indicates no  
read page buffer.  
(P+13)h  
1
1
44:  
--03  
8 byte  
0
(P+14)h  
(P+15)h  
Number of synchronous mode read configuration fields that  
follow. 00h indicates no burst capability.  
Reserved for future use  
45:  
46:  
--00  
NOTE:  
1.The variable P is a pointer which is defined at CFI offset 15h.  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
19  
MX28F320J3/640J3/128J3  
DEVICE OPERATION  
SILICON ID READ  
The Silicon ID Read mode allows the reading out of a  
binary code from the device and will identify its manu-  
facturer and type. This mode is intended for use by  
programming equipment for the purpose of automatically  
matching the device to be programmed with its corre-  
sponding programming algorithm. This mode is func-  
tional over the entire temperature range of the device.  
During the "Silicon ID Read" Mode, manufacturer's code  
(MXIC=C2H) can be read out by setting A0=VIL and  
device identifier can be read out by setting A0=VIH.  
To terminate the operation, it is necessary to write the  
read command. The "Silicon ID Read" command func-  
tions independently of theVPEN voltage.This command  
is valid only when the WSM is off or the device is sus-  
pended.  
To activate this mode, the two cycle "Silicon ID Read"  
command is requested. (The command sequence is il-  
lustrated inTable 14.  
Table 14. MX28F320J3/640J3/128J3 Silicon ID Codes and Verify Sector Protect Code  
Type  
Address (1) Code (HEX) Q7 Q6  
Q5 Q4 Q3 Q2 Q1 Q0  
Manufacture Code  
00000  
C2H  
1
0
0
0
1
1
1
1
0
1
1
1
0
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
0
32M  
64M  
128M  
00001  
(00) 72H  
(00) 73H  
(00) 74H  
Device Code  
00001  
00001  
Block Lock Configuration  
- Block is Unlocked  
- Block is Locked  
X0002 (2)  
DQ0=0  
DQ0=1  
DQ1-7  
- Reserved for Future Use  
* Outputs C2H at protected sector address, 00H at unprotected sector address.  
** Only the top and the bottom sectors have protect-bit feature. Sector address = (A20, A19, A18,A17,A16) =  
00000B or 11111B  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
20  
MX28F320J3/640J3/128J3  
Table 15. Status Register Definitions  
High Z  
Symbol When Status  
Busy?  
Definition  
Notes  
"1"  
"0"  
Busy  
Block Erase Suspended Block Erase in  
Progress/Completed  
ERASE AND CLEAR LOCK-BITS Error in Block Erasure or Successful Block  
SR.7  
SR.6  
No  
WRITE STATE MACHINE STATUS Ready  
ERASE SUSPEND STATUS  
1
Yes  
SR.5  
Yes  
2
3
STATUS  
Clear Lock-Bits  
Erase or Clear  
Lock-Bits  
SR.4  
SR.3  
Yes  
Yes  
PROGRAM AND SET LOCK-BIT  
STATUS  
Error in Setting Lock-Bit Successful Set Block  
Lock Bit  
PROGRAMMINGVOLTAGE  
STATUS  
Low ProgrammingVoltage ProgrammingVoltage  
Detected, Operation  
Aborted  
OK  
SR.2  
SR.1  
Yes  
Yes  
Yes  
PROGRAM SUSPEND STATUS  
DEVICE PROTECT STATUS  
RESERVED  
Program suspended  
Program in progress/  
completed  
Block Lock-Bit Detected, Unlock  
Operation Abort  
4
5
SR.0  
Notes  
1. Check STS or SR.7 to determine block erase, program, or lock-bit configuration completion. SR.6-SR.0 are not  
driven while SR.7 = 0  
2. If both SR.5 and SR.4 are "1" after a block erase or lock-bit configuration attempt, an improper command se-  
quence was entered.  
3. SR.3 does not provide a continuous programming voltage level indication.TheWSM interrogates and indicates the  
programming voltage level only after Block Erase, Program, Set Block Lock-Bit, or Clear Block Lock-Bits com-  
mand sequences.  
4. SR.1 does not provide a continuous indication of block lock-bit values.The WSM interrogates the block lock-bits  
only after Block Erase, Program, or Lock-Bit configuration command sequences. It informs the system, depend-  
ing on the attempted operation, if the block lock-bit is set. Read the block lock configuration codes using the Read  
Identifier Codes command to determine block lock-bit status.  
5. SR.0 is reserved for future use and should be masked when polling the status register.  
Table 16 . Extended Status Register Definitions  
High Z  
Symbol When Status  
Busy?  
Definition  
Notes  
"1"  
Write buffer available  
"0"  
XSR.7 No  
XSR.6- Yes  
XSR.0  
WRITE BUFFER STATUS  
RESERVED  
Write buffer not available  
1
2
Notes:  
1. After a Buffer-Write command, XSR.7 = 1 indicates that a Write Buffer is available.  
2. XSR.6-XSR.0 are reserved for future use and should be masked when polling the status register.  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
21  
MX28F320J3/640J3/128J3  
the Q7 bit to a "1". In default mode, STS will also transi-  
tion to VOH.  
READ STATUS REGISTER COMMAND  
The Status Register is read after writing the Read Status  
Register command of 70H to the Command User Inter-  
face. Also, after starting the internal operation the de-  
vice is set to the Read Status Register mode automati-  
cally.  
At this time, A read array/program command sequence  
can also be issued during erase suspend to read or pro-  
gram data in other blocks. During a program operation  
with block erase suspended, status register bit SR.7 will  
return to "0" and STS output (in default mode) will transi-  
tion to VOL The WSM will continue to run, idling in the  
SUSPEND state, regardless of the state of all input con-  
trol pins.  
The contents of Status Register are latched on the later  
falling edge of OE or the first edge of CE0, CE1, CE2  
that enables the device OE must be toggle toVIH or the  
device must be disable before further reads to update  
the status register latch.The Read Status Register com-  
mand functions independently of theVPEN voltage.  
The only other valid commands while block erase is sus-  
pended are Read Query, Read Status Register, Clear  
Status Register, Configure, and Block Erase Resume.  
After a Block Erase Resume command is written to the  
flash memory, the WSM will continue the block erase  
process. Status register bits SR.6 and SR.7 will auto-  
matically clear and STS (in default mode) will return to  
VOL. VPEN must remain at VPENH (the same VPEN  
level used for block erase) while block erase is suspended.  
Block erase cannot resume until program operations ini-  
tiated during block erase suspend have completed.  
CLEAR STATUS REGISTER COMMAND  
The Erase Status, Program Status, Block Status bits  
and protect status are set to "1" by the Write State Ma-  
chine and can only be reset by the Clear Status Register  
command of 50H. These bits indicates various failure  
conditions.  
BLOCK ERASE COMMAND  
WRITE TO BUFFER COMMAND  
Automated block erase is initiated by writing the Block  
Erase command of 20H followed by the Confirm com-  
mand of D0H. An address within the block to be erased  
is required (erase changes all block data to FFH).  
To program the device, a Write to Buffer command is  
issue first. A variable number of bytes, up to the buffer  
size, can be loaded into the buffer and written to the  
flash device. First, the Write to Buffer Setup command  
is issued along with the Block Address (see Figure ,  
Write to Buffer Flowchart ” on page ). After the com-  
mand is issued, the extended Status Register (XSR) can  
be read when CE is VIL. XSR.7 indicates if the Write  
Buffer is available.  
Block preconditioning, erase, and verify are handled in-  
ternally by the WSM (invisible to the system). The CPU  
can detect block erase completion by analyzing the out-  
put of the STS pin or status register bit SR.7.Toggle OE,  
CE0 , CE1 , or CE2 to update the status register. The  
CUI remains in read status register mode until a new  
command is issued.Also, reliable block erasure can only  
occur when VCC is valid and VPEN = VPENH .  
If the buffer is available, the number of words/bytes to  
be program is written to the device. Next, the start ad-  
dress is given along with the write buffer data. Subse-  
quent writes provide additional device addresses and  
data, depending on the count. After the last buffer data  
is given, a Write Confirm command must be issued.The  
WSM beginning copy the buffer data to the flash array.  
BLOCK ERASE SUSPEND COMMAND  
This command only has meaning while the WSM is ex-  
ecuting Block erase operation, and therefore will only be  
responded to during Block erase operation. After this com-  
mand has been executed, the WSM suspend the erase  
operations, and then return to Read Status Register  
mode. The WSM will set the Q6 bit to a "1". Once the  
WSM has reached the Suspend state, the WSM will set  
If an error occurs while writing, the device will stop writ-  
ing, and status register bit SR.4 will be set to a "1" to  
indicate a program failure.The internal WSM verify only  
detects errors for "1" that do not successfully program  
to "0" . If a program error is detected, the status register  
should be cleared. Any time SR.4 and/or SR.5 is set, the  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
22  
MX28F320J3/640J3/128J3  
device will not accept any more Write to Buffer com-  
mands.Reliable buffered writes can only occur whenVCC  
is valid and VPEN = VPENH. Also, successful program-  
ming requires that the corresponding block lock-bit be  
reset.  
BYTE/WORD PROGRAM COMMANDS  
Byte/Word program is executed by a two-command se-  
quence.The Byte/Word Program Setup command of 40H  
is written to the Command Interface, followed by a sec-  
ond write specifying the address and data to be written.  
The WSM controls the program pulse application and  
verify operation.The CPU can detect the completion of  
the program event by analyzing the STS pin or status  
register bit SR.7.  
If a byte/word program is attempted while VPEN_V  
PENLK, status register bits SR.4 and SR.3 will be set to  
"1". Successful byte/word programs require that the cor-  
responding block lock-bit be cleared. If a byte/ word pro-  
gram is attempted when the corresponding block lock-  
bit is set, SR.1 and SR.4 will be set to "1".  
SUSPEND/RESUME COMMAND  
Writing the Suspend command of B0H during block erase  
operation interrupts the block erase operation and allows  
read out from another block of memory.Writing the Sus-  
pend command of B0H during program operation inter-  
rupts the program operation and allows read out from  
another block of memory.The Block address is required  
when writing the Suspend/Resume Command.The de-  
vice continues to output Status Register data when read,  
after the Suspend command is written to it. Polling the  
WSM Status and Suspend Status bits will determine when  
the erase operation or program operation has been sus-  
pended.When SR.7 = 1, SR.2 should also be set to "1",  
indicating that the device is in the program suspend mode.  
STS in level RY/BY mode will also transition to VOH.  
At this time, writing of the Read Array command to the  
CUI enables reading data from blocks other than that  
which is suspended.The only other valid commands while  
programming is suspended are Read Query, Read Sta-  
tus Register, Clear Status Register, Configure, and Pro-  
gram Resume. When the Resume command of D0H is  
written to the CUI, theWSM will continue with the erase  
or program processes. Status register bits SR.2 and SR.7  
will automatically clear and STS in RY/BY mode will re-  
turn toVOL.  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
23  
MX28F320J3/640J3/128J3  
Read Configuration  
The device will support both asynchronous page mode and standard word/byte reads. No configuration is required.  
Status register and identifier only support standard word/byte single read operations.  
Table 17. Read Configuration Register Definition  
RM  
R
15  
R
7
R
14  
R
6
R
13  
R
5
R
R
11  
R
3
R
10  
R
2
R
9
16(A16)  
12  
R
8
R
R
1
4
Notes  
RCR.16 = READ MODE (RM)  
Read mode configuration effects reads from the flash  
array.  
0 = StandardWord/Byte Reads Enabled (Default)  
1 = Page-Mode Reads Enabled  
Status register, query, and identifier reads support  
standard word/byte read cycles.  
These bits are reserved for future use. Set these  
bits to "0".  
RCR.15-1= RESERVED FOR FUTURE  
ENHANCEMENTS (R)  
Configuration Command  
The Status (STS) pin can be configured to different states using the Configuration command. Once the STS pin has  
been configured, it remains in that configuration until another configuration command is issued or RP is asserted low.  
Initially, the STS pin defaults to RY/BY operation where RY/BY low indicates that the state machine is busy. RY/BY  
high indicates that the state machine is ready for a new operation or suspended. Table 19, "Configuration Coding  
Definitions" on page 28 displays the possible STS configurations.  
To reconfigure the Status (STS) pin to other modes, the Configuration command is given followed by the desired  
configuration code.The three alternate configurations are all pulse mode for use as a system interrupt as described  
below. For these configurations, bit 0 controls Erase Complete interrupt pulse, and bit 1 controls Program Complete  
interrupt pulse. Supplying the 00h configuration code with the Configuration command resets the STS pin to the  
default RY/BY level mode. The possible configurations and their usage are described in Table 19, "Configuration  
Coding Definitions" on page 28. The Configuration command may only be given when the device is not busy or  
suspended. Check SR.7 for device status. An invalid configuration code will result in both status register bits SR.4  
and SR.5 being set to "1".” When configured in one of the pulse modes, the STS pin pulses low with a typical pulse  
width of 250 ns.  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
24  
MX28F320J3/640J3/128J3  
Table 18. Configuration Coding Definitions  
Reserved  
bits7-2  
Pulse on  
Program  
Complete (1)  
bit 1  
Pulse on  
Erase  
Compete (1)  
bit 0  
Q7 - Q2 are reserved for future use.  
Q7 - Q2 = Reserved  
default (Q1-Q 0 = 00) RY/BY, level mode  
- used to control HOLD to a memory controller to  
prevent accessing a flash memory subsystem while  
any flash device's WSM is busy.  
Q1 - Q0 = STS Pin Configuration Codes  
00 = default, level mode RY/BY  
(device ready) indication  
01 = pulse on Erase complete  
configuration 01 ER INT, pulse mode  
10 = pulse on Program complete  
- used to generate a system interrupt pulse when any  
flash device in an array has completed a Block Erase.  
Helpful for reformatting blocks after file system free  
space reclamation or "cleanup"  
11 = pulse on Erase or Program Complete  
Configuration Codes 01b, 10b, and 11b are all pulse  
mode such that the STS pin pulses low then high when  
the operation indicated by the given configuration is  
completed.  
configuration 10 PR INT, pulse mode  
-used to generate a system interrupt pulse when any  
flash device in an array has complete a Program op-  
eration. Provides highest performance for servicing  
continuous buffer write operations.  
Configuration Command Sequences for STS pin  
configuration (masking bits Q7- Q 2 to 00h) are as  
follows:  
Default RY/BY level mode: B8h, 00h  
ER INT (Erase Interrupt): B8h, 01h  
Pulse-on-Erase Complete  
PR INT (Program Interrupt): B8h, 02h  
Pulse-on-Program Complete  
ER/PR INT (Erase or Program Interrupt): B8h, 03h  
Pulse-on-Erase or Program Complete  
configuration 11 ER/PR INT, pulse mode  
-used to generate system interrupts to trigger servic-  
ing of flash arrays when either erase or program opera-  
tions are completed when a common interrupt service  
routine is desired.  
NOTE: 1.When the device is configured in one of the pulse modes, the STS pin pulses low with a typical pulse  
width of 250 ns.  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
25  
MX28F320J3/640J3/128J3  
tion.To return to read array mode, write the Read Array  
command (FFH).  
Set Block Lock-Bit Commands  
This device provided the block lock-bits, to lock and  
unlock the individual block.To set the block lock-bit, the  
two cycle Set Block Lock-Bit command is requested.  
This command is invalid while theWSM is running or the  
device is suspended.Writing the set block lock-bit com-  
mand of 60H followed by confirm command and an ap-  
propriate block address. After the command is written,  
the device automatically outputs status register data when  
read.The CPU can detect the completion of the set lock-  
bit event by analyzing the STS pin output or status reg-  
ister bit SR.7. Also, reliable operations occur only when  
VCC and VPEN are valid. With VPEN _VPENLK , lock-  
bit contents are protected against alteration.  
Programming the Protection Register  
The protection register bits are programmed using the  
two-cycle Protection Program command.The 64-bit num-  
ber is programmed 16 bits at a time for word-wide parts  
and eight bits at a time for byte-wide parts. First write  
the Protection Program Setup command, C0H.The next  
write to the device will latch in address and data and  
program the specified location.  
Any attempt to address Protection Program commands  
outside the defined protection register address space will  
result in a status register error. Attempting to program a  
locked protection register segment will result in a status  
register error.  
Clear Block Lock-Bits Command  
All set block lock-bits can clear by the Clear Block Lock-  
Bits command.This command is invalid while the WSM  
is running or the device is suspended.To Clear the block  
lock-bits, two cycle command is requested .The device  
automatically outputs status register data when read.The  
CPU can detect completion of the clear block lock-bits  
event by analyzing the STS pin output or status register  
bit SR.7. If a clear block lock-bits operation is aborted  
due to V PEN or V CC transitioning out of valid range,  
block lock-bit values are left in an undetermined state. A  
repeat of clear block lock-bits is required to initialize block  
lock-bit contents to known values.  
Locking the Protection Register  
The user-programmable segment of the protection regis-  
ter is lockable by programming Bit 1 of the PR-LOCK  
location to 0. Bit 0 of this location is programmed to 0 at  
the Intel factory to protect the unique device number. Bit  
1 is set using the Protection Program command to pro-  
gram "FFFD" to the PR-LOCK location. After these bits  
have been programmed, no further changes can be made  
to the values stored in the protection register. Protection  
Program commands to a locked section will result in a  
status register error. Protection register lockout state is  
not reversible.  
Protection Register Program Command  
The device offer a 128-bit protection register to increase  
the security of a system design.The 128-bits protection  
register are divided into two 64-bit segments. One is pro-  
grammed in the factory with a unique 64-bit number,  
which is unchangeable. The other one is left blank for  
customer designers to program as desired. Once the  
customer segment is programmed, it can be locked to  
prevent reprogramming.  
Reading the Protection Register  
The protection register is read in the identification read  
mode.The device is switched to this mode by writing the  
Read Identifier command 90H. Once in this mode, read  
cycles from addresses retrieve the specified informa-  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
26  
MX28F320J3/640J3/128J3  
Figure 3. Protection Register Memory Map  
A[23 -1]: 128 Mbit  
Word  
Address  
A[22 -1]: 64 Mbit  
A[21 -1]: 32 Mbit  
88H  
4 Words  
User Programmed  
85H  
84H  
4 Words  
Factory Programmed  
81H  
80H  
1 Word Lock  
NOTE: A 0 is not used in x16 mode when accessing the protection register map (See Table 20 for x16 addressing).  
For x8 mode A 0 is used (See Table 21 for x8 addressing).  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
27  
MX28F320J3/640J3/128J3  
Table 20. Word-Wide Protection Register Addressing  
Word  
Use  
A8  
1
A7  
0
A6  
0
A5  
0
A4  
0
A3  
0
A2  
0
A1  
LOCK  
Both  
0
0
1
2
3
4
5
6
7
Factory  
Factory  
Factory  
Factory  
User  
1
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
1
0
1
0
0
0
0
1
0
User  
1
0
0
0
0
1
1
User  
1
0
0
0
0
1
1
User  
1
0
0
0
1
0
0
NOTE: 1. All address lines not specified in the above table must be 0 when accessing the Protection Register,  
i.e., A23-A9 = 0.  
Table 21. Byte-Wide Protection Register Addressing  
Word  
Use  
A8  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A7  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A6  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A5  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A4  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
A3  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
A2  
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
A1  
LOCK  
Both  
0
LOCK  
Both  
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Factory  
Factory  
Factory  
Factory  
Factory  
Factory  
Factory  
Factory  
User  
User  
User  
User  
User  
User  
User  
User  
NOTE: 1. All address lines not specified in the above table must be 0 when accessing the Protection Register,  
i.e., A23-A9 = 0.  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
28  
MX28F320J3/640J3/128J3  
Figure 4. Write to Buffer Flowchart  
Start  
Set Time-Out  
NO  
Write E8H to Block Address  
Read Extended Status Register  
YES  
NO  
Write to Buffer  
Time-Out ?  
XSR.7=1 ?  
YES  
Write Word or Byte  
Count to Block Address  
Write Buffer Data,  
Start Address  
YES  
X = 0  
Check  
X=N ?  
Abort Write to  
Buffer Command?  
YES  
Write to Another  
Block Address  
NO  
Write to Buffer  
Failed  
YES  
Write Next Buffer Data,  
Device Address  
X = X+1  
Program Buffer to Flash  
Confirm D0H  
Another Write  
to Buffer ?  
Issue Read  
Status Command  
NO  
Read Status Register  
NO  
SR.7=1?  
YES  
Full Status Check if Desired  
Programming Complete  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
29  
MX28F320J3/640J3/128J3  
Figure 5. Program Suspend/Resume Flowchart  
Start  
Write B0H  
Read Status Register  
NO  
SR.7=1 ?  
YES  
NO  
SR.2=1 ?  
YES  
Programming Completed  
Write FFH  
Read Array Data  
NO  
Done Reading  
YES  
Write D0H  
Write FFH  
Programming Resumed  
Read Array Data  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
30  
MX28F320J3/640J3/128J3  
Figure 6. Byte/Word Programming Flowchart  
Bus  
Command  
Comments  
Operation  
Write  
Setup Byte/  
Data=40H  
Start  
Word Program Addr=Location to Be  
Programmed  
Write 40H,  
Address  
Write  
Byte/Word  
Program  
Data=Data to Be  
Programmed  
Addr=Location to Be  
Programmed  
Write Data  
and Address  
Read  
Status Register Data  
(Note 1)  
Standby  
Read  
Status Register  
Check SR.7  
1=WSM Ready  
0=WSM Busy  
0
SR.7=  
1.Toggling OE (low to high to low) updates the status  
register.This can be done in place of issuing the Read  
Status Register command. Repeat for subsequent pro-  
gramming operations.  
SR full status check can be done after each program  
operation, or after a sequence of programming opera-  
tions.  
1
Full Status Check if Desired  
Byte/Word Program Complete  
Write FFH after the last program operation to place  
device in read array mode.  
FULL STATUS CHECK PROCEDURE  
Bus  
Command Comments  
Operation  
Standby  
Read Status Register  
Data (See Above)  
Check SR.3  
1=Programming toVoltage  
Error Detect  
1
VPP Range Error  
SR.3=  
Standby  
Check SR.1  
1=Device Protect Detect  
RP=VIH, Block Lock-Bit is  
Set Only required for  
systems  
0
1
1
SR.1=  
0
Device Protect Error  
Standby  
Check SR.4  
1=Programming Error  
Toggling OE (low to high to low) updates the status  
register.This can be done in place of issuing the Read  
Status Register command. Repeat for subsequent pro-  
gramming operations.  
Programming Error  
SR.4=  
0
SR.4, SR.3, and SR.1 are only cleared by the Clear  
Status Register Command in cases where multiple lo-  
cation are programmed before full status is checked.  
If an error is detected, clear the status register before  
attempting retry or other error recovery.  
Byte/Word Program Successful  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
31  
MX28F320J3/640J3/128J3  
Figure 7. Block Erase Flowchart  
Start  
Write 20H to Block Address  
Write Confirm D0H to Block Address  
Read  
Status Register  
NO  
NO  
SR.7=1 ?  
YES  
Write B0H?  
YES  
Full Status Check  
If Desired  
Suspend Loop  
Write D0H  
YES  
Erase Flash  
Block(s) Completed  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
32  
MX28F320J3/640J3/128J3  
Figure 8. Block Erase Suspend/Resume Flowchart  
Bus  
Command  
Comments  
Start  
Operation  
Write  
Erase  
Data=B0H  
Suspend  
Addr=X  
Write B0H  
Read  
Status Register Data  
Addr=X  
Read  
Status Register  
Standby  
Check SR.7  
1=WSM Ready  
0=WSM Busy  
Check SR.6  
0
SR.7=  
Standby  
Write  
1=Block Erase Suspend  
0=Block Erase Completed  
Data=D0H  
1
0
Erase  
SR.6=  
1
Erase Completed  
Resume  
Addr=X  
Read  
Program  
Read or Program?  
No  
Read Array  
Program  
Loop  
Data  
Done ?  
Yes  
Write D0H  
Write FFH  
Block Erase Resumed  
Read Array Data  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
33  
MX28F320J3/640J3/128J3  
Figure 9. Set Block Lock-Bit Flowchart  
Start  
Write 60H, Block Address  
Write 01H, Block Address  
Read  
Status Register  
NO  
SR.7=1 ?  
YES  
Full Status Check  
If Desired  
Set Lock-Bit Completed  
FULL STATUS CHECK PROCEDURE  
Read Status Register  
Data (See Above)  
NO  
Voltage Range Error  
Command Sequence Error  
Set Lock-Bit Error  
SR.3=0 ?  
YES  
YES  
SR.4,5=1 ?  
NO  
NO  
SR.4=0 ?  
YES  
Set Lock-Bit Successful  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
34  
MX28F320J3/640J3/128J3  
Figure 10. Clear Lock-Bit Flowchart  
Start  
Write 60H  
Write D0H  
Read  
Status Register  
NO  
SR.7=1 ?  
YES  
Full Status Check  
If Desired  
Set Lock-Bit Completed  
FULL STATUS CHECK PROCEDURE  
Read Status Register  
Data (See Above)  
NO  
Voltage Range Error  
Command Sequence Error  
Clear Block Lock-Bits Error  
SR.3=0 ?  
YES  
YES  
SR.4,5=1 ?  
NO  
NO  
SR.5=0 ?  
YES  
Clear Block Lock-Bit Successful  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
35  
MX28F320J3/640J3/128J3  
Figure 11. Protection Register Programming Flowchart  
Start  
Write C0H (Protection Reg.  
Program Setup)  
Write Protect. Register  
Address/Data  
Read  
Status Register  
NO  
SR.7=1 ?  
YES  
Full Status Check  
If Desired  
Program Completed  
FULL STATUS CHECK PROCEDURE  
Read Status Register  
Data (See Above)  
1,1  
VPEN Range Error  
SR.3, SR.4=  
0,1  
Protection Register  
Programming Error  
SR.1, SR.4=  
1,1  
Attempted Program to Locked  
Register-Aborted  
SR.1, SR.4=  
YES  
Program Successful  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
36  
MX28F320J3/640J3/128J3  
OPERATING RATINGS  
ABSOLUTE MAXIMUM RATINGS  
StorageTemperature  
Commercial (C) Devices  
Plastic Packages . . . . . . . . . . . . . ..... -65oC to +150oC  
Ambient Temperature (TA ). . . . . . . . . . . . 0°C to +70°C  
VCC Supply Voltages  
AmbientTemperature  
with Power Applied. . . . . . . . . . . . . .... -65oC to +125oC  
Voltage with Respect to Ground  
VCC for full voltage range. . . . . . . . . . . +2.7 V to 3.6 V  
Operating ranges define those limits between which the  
functionality of the device is guaranteed.  
VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V  
A9, OE, and  
RESET or RESET(Note 2) .........-0.5V to +12.5 V  
All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V  
Output Short Circuit Current (Note 3) . . . . . . 200 mA  
Notes:  
1. Minimum DC voltage on input or I/O pins is -0.5 V.  
During voltage transitions, input or I/O pins may over-  
shoot VSS to -2.0 V for periods of up to 20 ns. See  
Figure 6. Maximum DC voltage on input or I/O pins is  
VCC +0.5 V. During voltage transitions, input or I/O  
pins may overshoot to VCC +2.0 V for periods up to  
20 ns. See Figure 7.  
2. Minimum DC input voltage on pins A9, OE, and RE-  
SET or RESET is -0.5 V. During voltage transitions,  
A9, OE, and RESET or RESET may overshoot VSS  
to -2.0 V for periods of up to 20 ns. See Figure 6.  
Maximum DC input voltage on pin A9 is +12.5V which  
may overshoot to 14.0 V for periods up to 20 ns.  
3.No more than one output may be shorted to ground at  
a time. Duration of the short circuit should not be  
greater than one second.  
Stresses above those listed under "Absolute Maximum  
Rat-ings" may cause permanent damage to the device.  
This is a stress rating only; functional operation of the  
device at these or any other conditions above those in-  
dicated in the operational sections of this data sheet is  
not implied. Exposure of the device to absolute maxi-  
mum rating conditions for extended periods may affect  
device reliability.  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
37  
MX28F320J3/640J3/128J3  
DC Characteristics  
Symbol Parameter  
Notes  
Typ  
Max  
Unit  
Test Conditions  
ILI  
Input andV PEN Load Current  
1
±1  
uA  
VCC =VCC Max;VCCQ =VCCQ Max  
VIN = VCCQ or GND  
ILO  
Output Leakage Current  
VCC Standby Current  
1
±10  
uA  
VCC =VCC Max;VCCQ =VCCQ Max  
VIN = VCCQ or GND  
CMOS Inputs, VCC = VCC Max,  
Device is disabled (see table 2)  
RESET=VCCQ±0.2V or RESET=VIL  
TTL Inputs, VCC=VCC max,  
Device is disable (see table 2),  
RESET=VIH or RESET=VIL  
RESET=GND±0.2V, or RESET=VIH  
IOUT(STS)=0mA  
ICC1  
ICC2  
ICC3  
1,2,3  
25  
80  
2
uA  
0.71  
mA  
VCC Power-Down Current  
2
5
uA  
CMOS Inputs, VCC=VCC Max,  
VCCQ=VCCQ Max  
15  
20  
mA  
Device is enabled (see Table 2)  
f=5MHz, IOUT=0mA  
VCC Page Mode Read Current  
1,3  
1,3  
CMOS Inputs, VCC=VCC Max,  
VCCQ=VCCQ Max  
24  
40  
29  
50  
mA  
mA  
Device is enabled (see Table 2)  
f=33MHz, IOUT=0mA  
CMOS Inputs, VCC=VCC Max,  
VCCQ=VCCQ Max  
ICC4  
VCCWord Mode Read Current  
Device is enabled (see Table 2)  
f=5MHz, IOUT=0MA  
ICC5  
ICC6  
ICC7  
VCC Program or Set Lock-Bit  
Current  
1,4  
1,4  
35  
40  
35  
40  
60  
70  
70  
80  
10  
mA  
mA  
mA  
mA  
mA  
CMOS Inputs, VPEN=VCC  
TTL Inputs, VPEN=VCC  
VCC Block Erase or Clear  
Block Lock-Bits Current  
CMOS Inputs, VPEN=VCC  
TTL Inputs, VPEN=VCC  
VCC Program Suspend or Block 1,5  
Erase Suspend Current  
Device is disabled (see Table 2)  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
38  
MX28F320J3/640J3/128J3  
DC Characteristics, Continued  
Symbol Parameter  
Notes  
Min  
-0.5  
2.0  
Max  
0.8  
Unit  
V
Test Conditions  
VIL  
Input LowVoltage  
Input HighVoltage  
4
4
VIH  
VCCQ+0.5  
0.4  
V
V
VCCQ=VCCQ2/3 Min  
IOL=2mA  
VOL  
Output LowVoltage  
2,4  
0.2  
V
V
V
V
V
V
VCCQ=VCCQ2/3 Min  
IOL=100uA  
0.85 x  
VCCQ  
VCCQ=VCCQ Min  
IOH=-2.5mA  
VOH  
Output HighVoltage  
2,4  
VCCQ-0.2  
VCCQ=VCCQ Min  
IOH=-100uA  
VPENLK VPEN Lockout during Program, 4,6,7  
Erase and Lock-Bit Operations  
2.2  
3.6  
VPENH VPEN during Block Erase,  
Program, or Lock-Bit Operations  
6,7  
2.7  
2.2  
VLKO  
VCC LockoutVoltage  
8
NOTES:  
1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and  
speeds).  
2. Includes STS.  
3. CMOS inputs are either VCC ±0.2 V or GND ±0.2 V.TTL inputs are either VIL or VIH .  
4. Sampled, not 100% tested.  
5. ICCWS and ICCES are specified with the device de-selected. If the device is read or written while in erase suspend  
mode, the device's current draw is I CCR or I CCW .  
6.Block erases, programming, and lock-bit configurations are inhibited whenV PEN ˆV PENLK , and not guaranteed  
in the range betweenVPENLK (max) andVPENH (min), and aboveVPENH (max).  
7.Typically, VPEN is connected to VCC (2.7 V - 3.6 V).  
8.Block erases, programming, and lock-bit configurations are inhibited whenVCC <VLKO , and not guaranteed in the  
range betweenVLKO (min) andVCC (min), and aboveVCC (max).  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
39  
MX28F320J3/640J3/128J3  
Figure 12. Transient Input/Output Reference Waveform for VCCQ=3.0V-3.6V or VCCQ=2.7V-3.6 V  
VCCQ  
VCCQ/2 Output  
TEST POINTS  
Input VCCQ/2  
0.0  
Note:AC test inputs are driven at VCCQ for a Logic "1" and 0.0V for a Logic "0".  
Input timing being, and output timing ends, at VCCQ/2V (50% of VCCQ).  
Input rise and fall times (10% tp 90%)<5ns.  
Figure 13. Transient Equivalent Testing Load Circuit  
1.3V  
1N914  
RL=3.3K ohm  
Device  
Out  
Under Test  
CL  
NOTE: CL Includes Jig Capacitance  
Test Configuration  
C L (pF)  
30  
VCCQ = VCC = 3.0 V-3.6 V  
VCCQ = VCC = 2.7 V-3.6 V  
30  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
40  
MX28F320J3/640J3/128J3  
AC Characteristics --Read-Only Operations (1,2)  
Versions  
VCC  
VCCQ  
Notes  
3.0V-3.6V(3)  
3.0V-3.6V(3)  
2.7V-3.6V(3)  
2.7V-3.6V(3)  
(All units in ns unless otherwise noted)  
Sym  
Parameter  
Min  
120  
120  
150  
Max  
Min  
120  
120  
150  
Max  
tAVAV  
Read/Write CycleTime  
32M  
64M  
128M  
32M  
64M  
128M  
32M  
64M  
128M  
7
tAVQV  
tELQV  
Address to Output Delay  
CEX to Output Delay  
120  
120  
150  
120  
120  
150  
50  
120  
120  
150  
120  
120  
150  
50  
2
2, 7  
2
tGLQV  
tPHQV  
OE to Non-Array Output Delay  
RESET High to Output Delay  
2, 4  
32M  
64M  
180  
180  
210  
180  
180  
210  
128M  
8
5
5
5
5
5
tELQX  
tGLQX  
tEHQZ  
tGHQZ  
tOH  
CEX to Output in Low Z  
0
0
0
0
OE to Output in Low Z  
CEX High to Output in High Z  
OE High to Output in High Z  
Output Hold from Address, CEX, or OE  
Change, Whichever Occurs First  
35  
15  
35  
15  
0
0
0
0
tELFL/tELFH CEX Low to BYTE High or Low  
tFLQV/tFHQV BYTE to Output Delay  
5
10  
10  
1000  
1000  
1000  
1000  
tFLQZ  
tEHEL  
tAPA  
BYTE to Output in High Z  
CEx High to CEx Low  
5
5
Page Address Access Time  
OE to Array Output Delay  
5, 6  
4
25  
25  
30  
30  
tGLQV  
NOTES:CEX low is defined as the first edge of CE0 , CE1 , or CE2 that enables the device. CEX high is defined at  
the first edge of CE0, CE1, or CE2 that disables the device (see Table 2).  
1. See AC Input/Output Reference Waveforms for the maximum allowable input slew rate.  
2. OE may be delayed up to t ELQV -t GLQV after the first edge of CE0, CE1, or CE2 that enables the device (see  
Table 2) without impact on t ELQV .  
3. See Figures 14-16,Transient Input/Output ReferenceWaveform forVCCQ = 3.0V - 3.6V orVCCQ = 2.7V-3.6V, and  
Transient Equivalent Testing Load Circuit for testing characteristics.  
4.When reading the flash array a faster tGLQV (R16) applies. Non-array reads refer to status register reads, query  
reads, or device identifier reads.  
5. Sampled, not 100% tested.  
6. For devices configured to standard word/byte read mode, R15 (tAPA) will equal R2 (tAVQV).  
7. The performance of 64Mb depends on 120ns speed grade or 150ns speed grades.  
8. tPHQV is RESET low to output delay for 48-TSOP & 48-RTSOP package types.  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
41  
MX28F320J3/640J3/128J3  
Figure 14. AC Waveform for Both Page-Mode and Standard Word/Byte Read Operations (for 56-  
TSOP & 64-CSP)  
VIH  
Address  
(A23-A3)  
VIL  
tAVAV  
VIH  
VIL  
Address  
(A2-A0)  
Valid Address  
Valid Address Valid Address  
Valid Address  
tEHEL  
Disable  
VIH  
VIL  
CEx[E]  
Enable  
tEHQZ  
tAVQV  
VIH  
VIL  
OE [G]  
tGHQZ  
tELQV  
VIH  
VIL  
WE [W]  
tGLQV  
tOH  
tAPA  
tPHQV  
tELQX  
VOH  
VOL  
DATA[D/Q]  
Q0- Q15  
High Z  
High Z  
Valid  
Valid  
Valid  
Valid  
Output  
Output Output Output  
tGLQX  
VIH  
VIL  
VCC  
RESET[P]  
BYTE [F]  
VIH  
VIL  
tFLQV/tFHQV  
tELFL/tELFH  
tFLQZ  
VIH  
VIL  
NOTE:  
1. CEX low is defined as the first edge of CE0 , CE1 , or CE2 that enables the device. CEX high is defined at the first  
edge of CE0, CE1, or CE2 that disables the device (see Table 2).  
2. For standard word/byte read operations, tAPA will equal tAVQV.  
3. When reading the flash array a faster tGLQV applies. Non-array reads refer to status register reads, query reads,  
or device identifier reads.  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
42  
MX28F320J3/640J3/128J3  
Figure 15. AC Waveform for Both Page-Mode and Standard Word Read Operations (for 48-TSOP  
& 48-RTSOP)  
VIH  
Address  
(A23-A3)  
VIL  
tAVAV  
VIH  
VIL  
Address  
(A2-A0)  
Valid Address  
Valid Address Valid Address  
Valid Address  
tEHEL  
Disable  
VIH  
VIL  
CEx[E]  
Enable  
tEHQZ  
tAVQV  
VIH  
VIL  
OE [G]  
tGHQZ  
tELQV  
VIH  
VIL  
WE [W]  
tGLQV  
tOH  
tAPA  
tPHQV  
tELQX  
VOH  
VOL  
DATA[D/Q]  
Q0- Q15  
High Z  
High Z  
Valid  
Valid  
Valid  
Valid  
Output  
Output Output Output  
tGLQX  
VIH  
VIL  
VCC  
VIH  
VIL  
RESET[P]  
(Note 4)  
NOTE:  
1. CEX low is defined as the first edge of CE0 , CE1 , or CE2 that enables the device. CEX high is defined at the first  
edge of CE0, CE1, or CE2 that disables the device (see Table 2).  
2. For standard word/byte read operations, tAPA will equal tAVQV.  
3. When reading the flash array a faster tGLQV applies. Non-array reads refer to status register reads, query reads,  
or device identifier reads.  
4. For 48-TSOP & 48-RTSOP the RESET pin is high enable.  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
43  
MX28F320J3/640J3/128J3  
AC Characteristics--Write Operations (1,2)  
Versions  
Valid for All  
Speeds  
Unit  
Symbol  
Parameter  
Notes  
Min  
2
Max  
tPHWL (tPHEL )  
tELWL (tWLEL )  
tWP  
RESET High Recovery to WE(CEX) Going Low  
CEX (WE) Low toWE(CEX) Going Low  
Write PulseWidth  
3,10  
4
us  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
us  
sec  
us  
us  
0
4
70  
50  
55  
0
tDVWH (tDVEH )  
tAVWH (tAVEH )  
tWHEH (tEHWH)  
tWHDX (tEHDX)  
tWHAX (tEHAX)  
tWPH  
Data Setup to WE(CEX) Going High  
Address Setup to WE(CEX) Going High  
CEX (WE) Hold fromWE(CEX) High  
Data Hold fromWE(CEX) High  
5
5
0
Address Hold fromWE(CEX) High  
Write PulseWidth High  
0
6
3
30  
0
tVPWH (tVPEH)  
tWHGL (tEHGL)  
tWHRL (tEHRL)  
tQVVL  
VPEN Setup to WE(CEX) Going High  
Write Recovery before Read  
7
35  
WE(CEX) High to STS Going Low  
VPEN Hold from Valid SRD, STS Going High  
8
500  
3,8,9  
4,9  
4
0
tWHQV5 (tEHQV5) Set Lock-Bit Time  
64  
0.5  
25  
26  
75/85  
0.70  
tWHQV6 (tEHQV6) Clear Block Lock-Bits Time  
tWHRH1 (tEHRH1) Program Suspend LatencyTime to Read  
9
75/90  
35/40  
tWHRH (tEHRH)  
Erase Suspend LatencyTime to Read  
9
NOTES:  
CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first  
edge of CE0, CE1, or CE2 that disables the device (see Table 2).  
1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as  
during read-only operations. Refer to AC Characteristics-Read-Only Operations.  
2. A write operation can be initiated and terminated with either CE X or WE.  
3. Sampled, not 100% tested.  
4. Write pulse width (tWP) is defined from CEX orWE going low (whichever goes low last) to CEX orWE going high  
(whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH.  
5. Refer to Table 4 for valid A IN and D IN for block erase, program, or lock-bit configuration.  
6. Write pulse width high (t WPH) is defined from CEX or WE going high (whichever goes high first) to CEX or WE  
going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL .  
7. For array access, tAVQV is required in addition to tWHGL for any accesses after a write.  
8. STS timings are based on STS configured in its RY/BY default mode.  
9. VPEN should be held at VPENH until determination of block erase, program, or lock-bit configuration success  
(SR.1/3/4/5=0).  
10.For 48-TSOP & 48-RTSOP, the RESET pin is high enable.  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
44  
MX28F320J3/640J3/128J3  
Figure 16. AC Waveform for Write Operations (for 56-TSOP & 64-CSP)  
A
B
C
D
E
F
VIH  
VIL  
Address  
(A)  
AIN  
AIN  
tAVWH  
(tAVEH)  
tWHAX  
(tEHAX)  
Disable  
VIH  
VIL  
CEx,(WE)[E(W)]  
Enable  
tWHGL  
(tEHGL)  
tWHEH  
(tEHWH)  
tPHWL  
(tPHEL)  
VIH  
VIL  
OE  
tELWL  
(tWLEL)  
tWPH  
tWHQZ/tWHRH  
Disable  
VIH  
VIL  
WE,(CEx)[W(E)]  
Enable  
tWP  
tOVWH  
(tDVEH)  
tWHDX  
(tEHDX)  
VIH  
VIL  
Valid  
SRD  
DATA[D/Q]  
STS[R]  
DIN  
DIN  
DIN  
tWHRL  
(tEHRL)  
VOH  
VOL  
VIH  
VIL  
RESET [P]  
tVPWH  
(tVPEH)  
tQVVL  
VPENH  
VPENLK  
VIL  
VPEN[V]  
NOTES:  
1. CEX low is defined as the first edge of CE0 , CE1 , or CE2 that enables the device. CEX high is defined at the first  
edge of CE0, CE1, or CE2 that disables the device (see Table 2).  
STS is shown in its default mode (RY/BY).  
a.VCC power-up and standby.  
b.Write block erase, write buffer, or program setup.  
c.Write block erase or write buffer confirm, or valid address and data.  
d. Automated erase delay.  
e. Read status register or query data.  
f.Write Read Array command.  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
45  
MX28F320J3/640J3/128J3  
Figure 17. AC Waveform for Write Operations (for 48-TSOP & 48-RSOP)  
A
B
C
D
E
F
VIH  
VIL  
Address  
(A)  
AIN  
AIN  
tAVWH  
(tAVEH)  
tWHAX  
(tEHAX)  
Disable  
VIH  
VIL  
CEx,(WE)[E(W)]  
Enable  
tWHGL  
(tEHGL)  
tWHEH  
(tEHWH)  
tPHWL  
(tPHEL)  
VIH  
VIL  
OE  
tELWL  
(tWLEL)  
tWPH  
tWHQZ/tWHRH  
Disable  
VIH  
VIL  
WE,(CEx)[W(E)]  
Enable  
tWP  
tOVWH  
(tDVEH)  
tWHDX  
(tEHDX)  
VIH  
VIL  
Valid  
SRD  
DATA[D/Q]  
DIN  
DIN  
DIN  
VIH  
VIL  
RESET [P]  
(Note 2)  
NOTES:  
1. CEX low is defined as the first edge of CE0 , CE1 , or CE2 that enables the device. CEX high is defined at the first  
edge of CE0, CE1, or CE2 that disables the device (see Table 2).  
STS is shown in its default mode (RY/BY).  
a.VCC power-up and standby.  
b.Write block erase, write buffer, or program setup.  
c.Write block erase or write buffer confirm, or valid address and data.  
d. Automated erase delay.  
e. Read status register or query data.  
f.Write Read Array command.  
2. For 48-TSOP & 48-RTSOP, the RESET pin is high enable.  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
46  
MX28F320J3/640J3/128J3  
Figure 18. AC Waveform for Reset Operation (for 56-TSOP & 64-CSP)  
VIH  
VIL  
STS (R)  
tPHRH  
VIH  
VIL  
RESET (P)  
tPLPH  
NOTE:  
1. STS is shown in its default mode (RY/BY).  
Figure 19. AC Waveform for Reset Operation (for 48-TSOP & 48-RTSOP)  
VIH  
RESET (P)  
VIL  
(Note 2)  
tPLPH  
NOTE:  
1. STS is shown in its default mode (RY/BY).  
2. For 48-TSOP & 48-RTSOP, the RESET pin is high enable.  
Reset Specifications (1)  
Sym  
Parameter  
Notes  
Min  
Max Unit  
tPLPH  
RESET Pulse Low Time  
2
35  
us  
(If RESET is tied to VCC , this specification is not applicable)  
(for 48-TSOP & 48-RSTOP, the tPLPH indicates the RESET  
Pulse HighTime)  
tPHRH  
RESET High to Reset during Block Erase, Program, or  
Lock-Bit Configuration  
3
2
us  
NOTES:  
1. These specifications are valid for all product versions (packages and speeds).  
2. If RESET is asserted while a block erase, program, or lock-bit configuration operation is not executing then the  
minimum required RESET Pulse LowTime is 100ns.  
3. A reset time, tPHQV, is required from the latter of STS (in RY/BY mode) or RESET going high until outputs are  
valid.  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
47  
MX28F320J3/640J3/128J3  
ERASE AND PROGRAMMING PERFORMANCE(1)  
LIMITS  
TYP.(2)  
2.0  
PARAMETER  
MIN.  
MAX.  
15.0  
654  
UNITS  
sec  
Block Erase Time  
Write Buffer Byte Program Time  
(Time to Program 32 bytes/16 words)  
Byte Program Time (Using Word/Byte Program Command)  
Block Program Time (Using Write to Buffer Command)  
Block Erase/Program Cycles  
218  
us  
210  
0.8  
630  
2.4  
us  
sec  
C1  
C2  
C3  
C4  
10  
Cycles  
100  
1,000  
10,000  
Note: 1.Not 100% Tested, Excludes external system level over head.  
2.Typical values measured at 25°C,3.3V. Additionally programming typically assume checkerboard pattern.  
LATCH-UP CHARACTERISTICS  
MIN.  
-1.0V  
MAX.  
13.5V  
Input Voltage with respect to GND on all pins except I/O pins  
Input Voltage with respect to GND on all I/O pins  
Current  
-1.0V  
Vcc + 1.0V  
+100mA  
-100mA  
Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.  
CAPACITANCE TA=0°C to 70°C, VCC=2.7V~3.6V  
Parameter Symbol  
Parameter Description  
Input Capacitance  
Test Set  
VIN=0  
TYP  
MAX  
8
UNIT  
pF  
CIN  
6
8
COUT  
Output Capacitance  
VOUT=0  
12  
pF  
Notes:  
1. Sampled, not 100% tested.  
2.Test conditions TA=25°C, f=1.0MHz  
DATA RETENTION  
Parameter  
Test Conditions  
Min  
10  
Unit  
Minimum Pattern Data Retention Time  
150  
125  
Years  
Years  
20  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
48  
MX28F320J3/640J3/128J3  
ORDERING INFORMATION  
PLASTIC PACKAGE  
Part NO.  
Access Time  
(ns)  
Packagetype  
Cycles  
MX28F128J3TBC-15C1  
MX28F128J3RBC-15C1  
MX28F128J3TC-15C3  
MX28F128J3TBC-15C3  
MX28F128J3RBC-15C3  
MX28F128J3XCC-15C3  
MX28F128J3TC-15C4  
MX28F128J3TBC-15C4  
MX28F128J3RBC-15C4  
MX28F128J3XCC-15C1  
MX28F128J3XCC-15C4  
MX28F640J3TC-12C3  
MX28F640J3IAC-12C3  
MX28F640J3XCC-12C3  
MX28F640J3TC-15C4  
MX28F640J3IAC-15C4  
MX28F640J3XCC-15C4  
MX28F320J3TC-12C3  
MX28F320J3IAC-12C3  
MX28F320J3XCC-12C3  
MX28F320J3TC-12C4  
MX28F320J3IAC-12C4  
MX28F320J3XCC-12C4  
150/25  
150/25  
150/25  
150/25  
150/25  
150/25  
150/25  
150/25  
150/25  
150/25  
150/25  
120/25  
120/25  
120/25  
150/25  
150/25  
150/25  
120/25  
120/25  
120/25  
120/25  
120/25  
120/25  
48-TSOP  
48-RTSOP  
56-TSOP  
48-TSOP  
48-RTSOP  
64-CSP  
10  
10  
1,000  
1,000  
1,000  
1,000  
10,000  
10,000  
10,000  
10  
56-TSOP  
48-TSOP  
48-RTSOP  
64-CSP  
64-CSP  
10,000  
1,000  
1,000  
1,000  
10,000  
10,000  
10,000  
1,000  
1,000  
1,000  
10,000  
10,000  
10,000  
56-TSOP  
48-FCCSP  
64-CSP  
56-TSOP  
48-FCCSP  
64-CSP  
56-TSOP  
48-FCCSP  
64-CSP  
56-TSOP  
48-FCCSP  
64-CSP  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
49  
MX28F320J3/640J3/128J3  
PACKAGE INFORMATION  
48-Ball Flip Chip CSP  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
50  
MX28F320J3/640J3/128J3  
56 TSOP  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
51  
MX28F320J3/640J3/128J3  
64 CSP  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
52  
MX28F320J3/640J3/128J3  
48 TSOP  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
53  
MX28F320J3/640J3/128J3  
48 TSOP (Reverse )  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
54  
MX28F320J3/640J3/128J3  
REVISION HISTORY  
Revision No. Description  
Page  
Date  
0.1  
1. To add 32M/128M information  
All  
JAN/17/2002  
2. To modify the CSP package size from 13x10mm to 10x13mm P3  
0.2  
1. Add 48-TSOP  
P1  
APR/04/2002  
2. Technology name is changed from MXVAND to Nbit  
3. 48-ball CSP name is added "Flip Chip" wording  
4. 64-ball CSP naming is changed  
P1  
P1  
P1,4  
5. Mis-tying : removing verify sector  
5-1 Protection code from Table 14  
P8,19  
P30  
P31  
P1,3,47  
P1,9,11,38  
P38  
P1,3,46,47  
P43  
P45  
P1,41,47  
P3,5,6,8,9,20, JUN/07/2002  
P37,38,41~47  
5-2 Correct Program Suspend/Resume flowchart  
5-3 Correct Block Erase Suspend/Resume flowchart  
1. Added 48-RTSOP  
0.3  
0.4  
MAY/28/2002  
2. Added deep power-down spec:5uA(max.)  
3. Changed standby current from 120uA(max.) to 80uA(max.)  
4. Added "Cx" on part number to distinguish different program  
5. Changed spec of tPHWL(tPHEL) from 1us to 2us  
6. Changed spec of tPHRH from 100ns to 2us  
7. Changed speed spec of 32Mb from 110ns-->120ns  
Deep power down mode is entering by RESET pin at VIH of  
48-TSOP & 48-RTSOP types. 64-CSP & 56-TSOP is still kept  
RESET=VIL for entering deep power down mode.  
Removed reset command  
P10,11  
P/N:PM0858  
REV. 0.4, JUN. 07, 2002  
55  
MX28F320J3/640J3/128J3  
MACRONIX INTERNATIONAL CO., LTD.  
HEADQUARTERS:  
TEL:+886-3-578-6688  
FAX:+886-3-563-2888  
EUROPE OFFICE:  
TEL:+32-2-456-8020  
FAX:+32-2-456-8021  
JAPAN OFFICE:  
TEL:+81-44-246-9100  
FAX:+81-44-246-9105  
SINGAPORE OFFICE:  
TEL:+65-348-8385  
FAX:+65-348-8096  
TAIPEI OFFICE:  
TEL:+886-2-2509-3300  
FAX:+886-2-2509-2200  
MACRONIX AMERICA, INC.  
TEL:+1-408-453-8088  
FAX:+1-408-453-8488  
CHICAGO OFFICE:  
TEL:+1-847-963-1900  
FAX:+1-847-963-1909  
http : //www.macronix.com  
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.  

相关型号：

SI9130DB

 5- and 3.3-V Step-Down Synchronous Converters

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135LG-T1

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135LG-T1-E3

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135_11

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9136_11

 Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130CG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130LG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130_11

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137LG

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9122E

 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明