MX28F128J3TC-15 [Macronix]

Flash, 8MX16, PDSO56, 14 X 20 MM, PLASTIC, TSOP-56;


型号：	MX28F128J3TC-15
厂家：	MACRONIX INTERNATIONAL
描述：	Flash, 8MX16, PDSO56, 14 X 20 MM, PLASTIC, TSOP-56 光电二极管内存集成电路
文件：	总6页 (文件大小：36K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BRIEF

MX28F128J3

128M[x8/x16] SINGLE3VPAGEMODEFLASHMEMORY

FEATURES

• 2.7V to 3.6V operation voltage

• Block Structure

Software Feature

• Support Common Flash Interface (CFI)

- Flash device parameters stored on the device and

provide the host system to access.

• Automation Suspend Options

- Block Erase Suspend to Read

- Block Erase Suspend to Program

- Program Suspend to Read

- 128 x 128Kbyte Erase Blocks

• Fast random / page mode access time

- 150/25 ns Read Access Time

• 128-bit Protection Register

- 64-bit Unique Device Identifier

- 64-bit User Programmable OTP Cells

• 32-Byte Write Buffer

- 6 us/byte Effective Programming Time

Hardware Feature(Not for 48-TSOP/48-RTSOP)

• Enhanced Data Protection Features Absolute Protec-

tion with VPEN = GND

• A0 pin

- Select low byte address when device is in byte mode.

- Flexible Block Locking

Not used in word mode.

• STS pin

- Block Erase/Program Lockout during PowerTransi-

tions

- Indicates the status of the internal state machine.

• VPEN pin

Performance

- For Erase /Program/ Block Lock enable.

• VCCQ Pin

• Low power dissipation

- typical 15mA active current for page mode read

- 80uA/(max.) standby current

- Deep power-down current: 5uA

• High Performance

-The output buffer power supply, control the device 's

output voltage.

Packaging

- Block erase time: 2s typ.

- 48-LeadTSOP

- 48-Lead RTSOP

- 56-LeadTSOP

- 64-ball CSP

- Byte programming time: 210us typ.

- Block programming time: 0.8s typ. (using Write to

Buffer Command)

• Program/Erase Endurance cycles: 10,000 cycles

Technology

- MX28F128J3 using Nbit (0.25u) FlashTechnology

OCT/30/2002

MX28F128J3

GENERAL DESCRIPTION

The MXIC's MX28F128J3 series Flash use the most ad-

vance 2 bits/cell Nbit technology, double the storage ca-

pacity of memory cell.The device provide the high den-

sity Flash memory solution with reliable performance and

most cost-effective.

enable (CE0, CE1, CE2) and output enable (OE) con-

trols.The device augment EPROM functionality with in-

circuit electrical erasure and programming. The device

uses a command register to manage this functionality.

The MXIC's Nbit technology reliably stores memory con-

tents even after the specific erase and program cycles.

The MXIC cell is designed to optimize the erase and

program mechanisms by utilizing the dielectric's charac-

ter to trap or release charges from ONO layer.

The device organized as by 8 bits or by 16 bits of output

bus.The device is packaged in 48-LeadTSOP, 48-Lead

RTSOP, 56-Lead TSOP, and 64-ball CSP. It is designed

to be reprogrammed and erased in system or in standard

EPROM programmers.

The device uses a 2.7V to 3.6V VCC supply to perform

the High Reliability Erase and auto Program/Erase algo-

rithms.

The device offers fast access time and allowing opera-

tion of high-speed microprocessors without wait states.

To eliminate bus contention, the device has separate chip

The highest degree of latch-up protection is achieved

PIN CONFIGURATION

48-TSOP (12mm x 20mm) (for MX28F128J3 word mode only)

A17

A16

A15

A14

A13

A12

A11

A10

GND

Q15

Q14

Q13

Q12

A20

A22

A21

A19

A18

VCC

A23

Q11

MX28F128J3 (x16 only)

Normal Type

Q10

GND

RESET(*)

CE0

(* RESET pin : high enable)

OCT/30/2002

MX28F128J3

48-RTSOP (12mm x 20mm) (for MX28F128J3 word mode only)

GND

Q15

A17

A16

A15

A14

A13

A12

A11

A10

Q14

Q13

Q12

VCC

A23

Q11

A20

A22

A21

A19

A18

MX28F128J3 (x16 only)

Reverse Type

Q10

GND

RESET(*)

CE0

(* RESET pin : high enable)

56 TSOP (14mm x 20mm)

A22

CE1

A21

A20

A19

A18

A17

A16

VCC

A15

A14

A13

A12

CE0

VPEN

RESET

A11

A10

STS

Q15

Q14

GND

Q13

Q12

VCCQ

GND

Q11

Q10

VCC

GND

BYTE

A23

CE2

OCT/30/2002

MX28F128J3

64 Ball CSP (10x13x1.2mm, 1.0mm-ball pitch)

A22

VPEN

A13

VCC

A18

GND

CE0

A12

A14

A15

A19

A20

CE1

A21

A10

A11

RESET

A16

Q15

A17

13 mm

STS

BYTE

Q10

Q11

Q12

Q14

A23

CE2

VCCQ

GND

VCC

Q13

GND

10mm

Notes:

1. Don't Use (DU) pins refer to pins that should not be connected.

PIN DESCRIPTION

SYMBOL

STS

PIN NAME

SYMBOL

PIN NAME

STATUS Pin

Byte Select Address

Address Input

BYTE

VPEN

Byte Mode Enable

ERASE/PROGRAM/BLOCK Lock

Enable

A1~A23

Q0~Q15

Data Inputs/Outputs

CE0, CE1, CE2 Chip Enable Input

VCCQ

VCC

GND

Output Buffer Power Supply

Device Power Supply

Device Ground

Write Enable Input

Output Enable Input

RESET

Reset/Deep Power Down mode

(low enable for 56-TSOP & 64-CSP)

Reset/Deep Power Down mode

(high enable for 48-TSOP &

48-RTSOP)

Pin Not Connected Internally

Don't Use

RESET

OCT/30/2002

MX28F128J3

ORDERING INFORMATION

PLASTIC PACKAGE

Part NO.

Access Time

(ns)

Packagetype

MX28F128J3TBC-15

MX28F128J3RBC-15

MX28F128J3TC-15

MX28F128J3XCC-15

150/25

48-TSOP

48-RTSOP

56-TSOP

64-CSP

150/25

OCT/30/2002

MX28F128J3

MACRONIX INTERNATIONAL CO., LTD.

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FAX:+65-348-8096

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MACRONIX AMERICA, INC.

TEL:+1-408-453-8088

FAX:+1-408-453-8488

CHICAGO OFFICE:

TEL:+1-847-963-1900

FAX:+1-847-963-1909

http : //www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.

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