MX28F160C3BBXAI-70G [Macronix]
Flash, 1MX16, 70ns, PBGA48;
| 型号： | MX28F160C3BBXAI-70G |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | Flash, 1MX16, 70ns, PBGA48 内存集成电路 |
| 文件： | 总42页 (文件大小：413K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MX28F160C3BT/B
16M-BIT[1Mx16]CMOSSINGLEVOLTAGE
3VONLYFLASHMEMORY
FEATURES
• Bit Organization: 1,048,576 x 16
• Singlepowersupplyoperation
-VCC=VCCQ=2.7~3.6Vforread,eraseandprogram
operation
- Word write suspend to read
- Sector erase suspend to word write
- Sector erase suspend to read register report
• Automatic sector erase, word write and sector lock/
unlockconfiguration
- VPP=12V for fast production programming
-Operatingtemperature:-40°C~85°C
• Fast access time : 70/90ns
• Status Reply
- Detection of program and erase operation comple-
tion.
• Lowpowerconsumption
- 9mA typical active read current, f=5MHz
- 18mA typical program current (VPP=1.65~3.6V)
- 21mA typical erase current (VPP=1.65~3.6V)
- 7uA typical standby current under power saving
mode
- Command User Interface (CUI)
- Status Register (SR)
• Data Protection Performance
-Includebootsectorsandparameterandmainsectors
to be locked/unlocked
• Sectorarchitecture
• 100,000minimumerase/programcycles
• Common Flash Interface (CFI)
• 128-bitProtectionRegister
-Sectorstructure:4Kwordx2(bootsectors),4Kword
x6(parametersectors), 32Kwordx31(mainsectors)
- Top/Bottom Boot
- 64-bit Unique Device Identifier
-64-bitUser-Programmable
• Auto Erase and Auto Program
- Automatically program and verify data at specified
address
• Latch-up protected to 100mA from -1V to VCC+1V
• Package type:
- Auto sector erase at specified sector
• Automatic Suspend Enhance
- 48-pin TSOP (12mm x 20mm)
- 48-ball CSP (8mm x 6mm)
fast as 70ns, allowing operation of high-speed micropro-
cessors without wait states.
GENERAL DESCRIPTION
The MX28F160C3BT/B is a 16-mega bit Flash memory
organized as 1M words of 16 bits. The 1M word of data
is arranged in eight 4Kword boot and parameter sectors,
and thirty-one 32K word main sectors which are indi-
vidually erasable. MXIC's Flash memories offer the most
cost-effective and reliable read/write non-volatile random
access memory. The MX28F160C3BT/B is packaged in
48-pin TSOP and 48-ball CSP. It is designed to be re-
programmed and erased in system or in standard
EPROM programmers.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX28F160C3BT/B uses a command register to man-
age this functionality. The command register allows for
100% TTL level control inputs and fixed power supply
levels during erase and programming, while maintaining
maximum EPROM compatibility.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
The standard MX28F160C3BT/B offers access time as
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MX28F160C3BT/B
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cy-
cling. The MX28F160C3BT/B uses a 2.7V~3.6V VCC
supply to perform the High Reliability Erase and auto
Program/Erase algorithms.
typical ICCS current is 7uA (CMOS) at 3.0V VCC.
As CE# and RESET# are at VCC, ICC CMOS standby
mode is enabled. When RESET# is at GND, the reset
mode is enabled which minimize power consumption and
provide data write protection.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
A reset time (tPHQV) is required from RESET# switch-
ing high until outputs are valid. Similarly, the device has
a wake time (tPHEL) from RESET#-high until writes to
the CUI are recognized.With RESET# at GND, theWSM
is reset and the status register is cleared.
The dedicated VPP pin gives complete data protection
when VPP< VPPLK.
A Command User Interface (CUI) serves as the inter-
face between the system processor and internal opera-
tion of the device. A valid command sequence written to
the CUI initiates device automation. An internal Write
State Machine (WSM) automatically executes the algo-
rithms and timings necessary for erase, word write and
sector lock/unlock configuration operations.
A sector erase operation erases one of the device's 32K-
word sectors typically within 1.0s, 4K-word sectors typi-
cally within 0.5s independent of other sectors. Each sec-
tor can be independently erased minimum 100,000 times.
Sector erase suspend mode allows system software to
suspend sector erase to read or write data from any other
sector.
Writing memory data is performed in word increments of
the device's 32K-word sectors typically within 0.8s and
4K-word sectors typically within 0.1s.Word program sus-
pend mode enables the system to read data or execute
code from any other memory array location.
MX28F160C3BT/B features with individual sectors lock-
ing by using a combination of bits thirty-nine sector lock-
bits and WP#, to lock and unlock sectors.
The status register indicates when the WSM's sector
erase, word program or lock configuration operation is
done.
The access time is 70/90/110ns (tELQV) over the oper-
ating temperature range (-40°C to +85°C) andVCC sup-
ply voltage range of 2.7V~3.6V.
MX28F160C3BT/B's power saving mode feature sub-
stantially reduces active current when the device is in
static mode (addresses not switching).In this mode, the
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MX28F160C3BT/B
BLOCK DIAGRAM
DQ0-DQ15
Output
Buffer
Input
Buffer
I/O
VCC
Logic
Identifier
Register
CE#
WE#
Command
User
Interface
OE#
Status
RESET#
WP#
Register
Data
Comparator
Write
State
Machine
Y
VPP
Program/Erase
Voltage Switch
Input
Buffer
Y-Gating
A0~A19
Decoder
VCC
GND
32K-Word
Main Sector
x31
Address
Latch
X
Decoder
Address
Counter
.......
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MX28F160C3BT/B
PIN CONFIGURATIONS
48 TSOP (Standard Type) (12mm x 20mm)
A15
A14
A13
A12
A11
A10
A9
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
VCCQ
GND
Q15
Q7
2
3
4
5
6
Q14
Q6
7
A8
8
Q13
Q5
NC
9
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Q12
Q4
WE#
RESET#
VPP
WP#
A19
A18
A17
A7
MX28F160C3BT/B
VCC
Q11
Q3
Q10
Q2
Q9
Q1
A6
Q8
A5
Q0
A4
OE#
GND
CE#
A0
A3
A2
A1
48 Ball CSP (8mm x 6mm) Top View, Ball Down for MX28F160C3BT/BXA
(Ball Pitch=0.75mm, Ball Width=0.35mm)
A1
A2
A3
A8
A4
A5
A6
A7
A7
A8
A4
A13
A11
VPP
WP#
A19
B1
B2
B3
B4
B5
B6
B7
A5
B8
A2
A14
A10
WE#
RESET#
A18
A17
C1
C2
C3
A9
C4
C5
C6
A6
C7
A3
C8
A1
A15
A12
NC
NC
6.0 mm
D1
D2
D3
D4
D5
D6
D7
D8
A0
A16
DQ14
DQ5
DQ11
DQ2
DQ8
CE#
E1
E2
E3
E4
E5
E6
E7
E8
VCCQ
DQ15
DQ6
DQ12
DQ3
DQ9
DQ0
GND
F1
F2
F3
F4
F5
F6
F7
F8
GND
DQ7
DQ13
DQ4
VCC
DQ10
DQ1
OE#
8.0 mm
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MX28F160C3BT/B
Table 1. Pin Description
Symbol
Type
Description and Function
A0-A19
input
Address inputs for memory address. Data pin float to high-impedance when the chip is
deselected or outputs are disable. Addresses are internally latched during a write or
erase cycle.
DQ0-DQ15 input/output Data inputs/outputs: Inputs array data on the second CE# and WE# cycle during a
program command.Data is internally latched.Outputs array and configuration data.The
data pin float to tri-state when the chip is de-selected.
CE#
input
Chip Enable : Activates the device's control logic, input buffers, and sense amplifiers.
CE# high de-selects the memory device and reduce power consumption to standby
level. CE# is active low.
RESET#
input
Reset/Deep Power Down:when RESET#=VIL, the device is in reset/deep power down
mode, which drives the outputs to High Z, resets the WSM and minimizes current level.
When RESET#=VIH, the device is normal operation. When RESET# transitions from
VIL to VIH, the device defaults to the read array mode.
WE#
VPP
input
Write Enable: to control write to CUI and array sector. WE#=VIL becomes active. The
data and addresses are latched on the rising edge of the second WE# pulse.
input/supply Program/Erase Power Supply:(1.65V~3.6V or 11.4V~12.6V)
Lower VPP<VPPLK, to protect any contents against Program and Erase Command.
Set VPP=VCC for in-system Read, Program and Erase Operation.
Raise VPP to 12V±5% for faster program and erase in a production environment.
OE#
WP#
input
input
Output enable: gates the device's outputs during a real cycle.
Write Protect: When WP# is VIL, the sectors marked Lock Down can't be unlocked
through software. When WP# is VIH, the lock down mechanism is disable and sectors
previously locked down are now locked and can be unlocked and locked through soft-
ware.AfterWP# goes low, any sectors previously marked lock down revert to that state.
Device power supply: (2.7V~3.6V).
VCC
supply
input
VCCQ
GND
I/O Power Supply: supplies for input/output buffers. (VCCQ must be tied to VCC)
Ground voltage: all the GND pin shall not be connected.
supply
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MX28F160C3BT/B
SECTOR STRUCTURE (TOP)
Sector
Sector Size
4KWord
Address Range (h)
FF000 ~ FFFFF
FE000 ~ FEFFF
FD000 ~ FDFFF
FC000 ~ FCFFF
FB000 ~ FBFFF
FA000 ~ FAFFF
F9000 ~ F9FFF
F8000 ~ F8FFF
F0000 ~ F7FFF
E8000 ~ EFFFF
E0000 ~ E7FFF
D8000 ~ DFFFF
D0000 ~ D7FFF
C8000 ~ CFFFF
C0000 ~ C7FFF
B8000 ~ BFFFF
B0000 ~ B7FFF
A8000 ~ AFFFF
A0000 ~ A7FFF
98000 ~ 9FFFF
90000 ~ 97FFF
88000 ~ 8FFFF
80000 ~ 87FFF
78000 ~ 7FFFF
70000 ~ 77FFF
68000 ~ 6FFFF
60000 ~ 67FFF
58000 ~ 5FFFF
50000 ~ 57FFF
48000 ~ 4FFFF
40000 ~ 47FFF
38000 ~ 3FFFF
30000 ~ 37FFF
28000 ~ 2FFFF
20000 ~ 27FFF
18000 ~ 1FFFF
10000 ~ 17FFF
08000 ~ 0FFFF
00000 ~ 07FFF
Boot Sector 0
Boot Sector 1
4KWord
Parameter Sector 0
Parameter Sector 1
Parameter Sector 2
Parameter Sector 3
Parameter Sector 4
Parameter Sector 5
Main Sector 0
Main Sector 1
Main Sector 2
Main Sector 3
Main Sector 4
Main Sector 5
Main Sector 6
Main Sector 7
Main Sector 8
Main Sector 9
Main Sector 10
Main Sector 11
Main Sector 12
Main Sector 13
Main Sector 14
Main Sector 15
Main Sector 16
Main Sector 17
Main Sector 18
Main Sector 19
Main Sector 20
Main Sector 21
Main Sector 22
Main Sector 23
Main Sector 24
Main Sector 25
Main Sector 26
Main Sector 27
Main Sector 28
Main Sector 29
Main Sector 30
4K Word
4K Word
4KWord
4K Word
4K Word
4K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32KWord
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MX28F160C3BT/B
SECTOR STRUCTURE (BOTTOM)
Sector
Sector Size
Address Range (h)
00000 ~ 00FFF
01000 ~ 01FFF
02000 ~ 02FFF
03000 ~ 03FFF
04000 ~ 04FFF
05000 ~ 05FFF
06000 ~ 06FFF
07000 ~ 07FFF
08000 ~ 0FFFF
10000 ~ 17FFF
18000 ~ 1FFFF
20000 ~ 27FFF
28000 ~ 2FFFF
30000 ~ 37FFF
38000 ~ 3FFFF
40000 ~ 47FFF
48000 ~ 4FFFF
50000 ~ 57FFF
58000 ~ 5FFFF
60000 ~ 67FFF
68000 ~ 6FFFF
70000 ~ 77FFF
78000 ~ 7FFFF
80000 ~ 87FFF
88000 ~ 8FFFF
90000 ~ 97FFF
98000 ~ 9FFFF
A0000 ~ A7FFF
A8000 ~ AFFFF
B0000 ~ B7FFF
B8000 ~ BFFFF
C0000 ~ C7FFF
C8000 ~ CFFFF
D0000 ~ D7FFF
D8000 ~ DFFFF
E0000 ~ E7FFF
E8000 ~ EFFFF
F0000 ~ F7FFF
F8000 ~ FFFFF
Boot Sector 0
4K Word
4K Word
Boot Sector 1
Parameter Sector 0
Parameter Sector 1
Parameter Sector 2
Parameter Sector 3
Parameter Sector 4
Parameter Sector 5
Main Sector 0
Main Sector 1
Main Sector 2
Main Sector 3
Main Sector 4
Main Sector 5
Main Sector 6
Main Sector 7
Main Sector 8
Main Sector 9
Main Sector 10
Main Sector 11
Main Sector 12
Main Sector 13
Main Sector 14
Main Sector 15
Main Sector 16
Main Sector 17
Main Sector 18
Main Sector 19
Main Sector 20
Main Sector 21
Main Sector 22
Main Sector 23
Main Sector 24
Main Sector 25
Main Sector 26
Main Sector 27
Main Sector 28
Main Sector 29
Main Sector 30
4K Word
4K Word
4K Word
4K Word
4K Word
4K Word
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
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MX28F160C3BT/B
2 PRINCIPLES OF OPERATION
3 BUS OPERATION
The product includes an on-chip WSM to manage sec-
tor erase, word write and lock-bit configuration functions.
The local CPU reads and writes flash memory in-sys-
tem. All bus cycles to or from the flash memory conform
to standard microprocessor bus cycles.
After initial device power-up or return from reset mode
(see section on Bus Operations), the device defaults to
read array mode. Manipulation of external memory con-
trol pins allow array read, standby and output disable
operations.
3.1 Read
Information can be read from any sector, configuration
codes or status register independent of the VPP volt-
age. RESET# can be at VIH.
Status register and identifier codes can be accessed
through the CUI independent of the VPP voltage. All
functions associated with altering memory contents -
sector erase, word write, sector lock/unlock, status and
identifier codes - are accessed via the CUI and verified
through the status register.
The first task is to write the appropriate read mode com-
mand (Read Array, Read Configuration, Read Query or
Read Status Register) to the CUI. Upon initial device
power-up or after exit from reset, the device automati-
cally resets to read array mode. In order to read data,
control pins set for CE#, OE#, WE#, RESET# and WP#
must be driven to active. CE# and OE# must be active
to obtain data at the outputs.CE# is the device selection
control.OE# is the data output (DQ0-DQ15) control and
active drives the selected memory data onto the I/O bus,
WE# must beVIH, RESET# must beVIH, WP# must be
at VIL or VIH.
Commands are written using standard microprocessor
write timings. The CUI contents serve as input to the
WSM, which controls the sector erase, word write and
sector lock/unlock.The internal algorithms are regulated
by theWSM, including pulse repetition, internal verifica-
tion and margining of data. Addresses and data are in-
ternally latched during write cycles. Address is latched
at falling edge of CE# and data latched at rising edge of
WE#.Writing the appropriate command outputs array data,
accesses the identifier codes or outputs status register
data.
3.2 Output Disable
With OE# at a logic-high level (VIH), the device outputs
are disabled. Output pins (DQ0-DQ15) are placed in a
high-impedance state.
Interface software that initiates and polls progress of
sector erase, word write and sector lock/unlock can be
stored in any sector.This code is copied to and executed
from system RAM during flash memory updates. After
successful completion, reads are again possible via the
Read Array command. Sector erase suspend allows
system software to suspend a sector erase to read/write
data from/to sectors other than that which is suspend.
Word write suspend allows system software to suspend
a word write to read data from any other flash memory
array location.
3.3 Standby
CE# at a logic-high level (VIH) places the device in
standby mode which substantially reduces device power
consumption. DQ0~DQ15 outputs are placed in a high-
impedance state independent of OE#.If deselected dur-
ing sector erase, word write or sector lock/unlock, the
device continues functioning, and consuming active
power until the operation completes.
With the mechanism of sector lock, memory contents
cannot be altered due to noise or unwanted operation.
When RESET#=VIH andVCC<VLKO (lockout voltage),
any data write alteration can be failure. During read op-
eration, if writeVPP voltage is belowVPPLK, then hard-
ware level data protection is achieved. With CUI's two-
step command sequence sector erase, word write or
sector lock/unlock, software level data protection is
achieved also.
3.4 Reset
As RESET#=VIL, it initiates the reset mode.The device
enters reset/deep power down mode.However, the data
stored in the memory has to be sustained at least 100ns
in the read mode before the device becomes deselected
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MX28F160C3BT/B
and output high impedance state.
mands require the command and address within the de-
vice or sector within the device (Sector Lock) to be
locked. The Clear Sector Lock-Bits command requires
the command and address within the device.
In read modes, RESET#-low deselects the memory,
places output drivers in a high-impedance state and turns
off all internal circuits. RESET# must be held low for a
minimum of 100ns.Time tPHQV is required after return
from reset mode until initial memory access outputs are
valid. After this wake-up interval tPHEL or tPHWL, nor-
mal operation is restored.The CUI is reset to read array
mode and status register is set to 80H. Sector lock bit is
set at lock status.
The CUI does not occupy an addressable memory loca-
tion. It is written when WE# and CE# are active (which-
ever goes high first). The address and data needed to
execute a command are latched on the rising edge of
WE# or CE#.Standard microprocessor write timings are
used.
During sector erase, word write or sector lock/unlock
modes, RESET#-low will abort the operation.Memory con-
tents being altered are no longer valid; the data may be
partially erased or written.
In addition, CUI will go into either array read mode or
erase/write interrupted mode.When power is up and the
device reset subsequently, it is necessary to read sta-
tus register in order to assure the status of the device.
Recognizing status register (SR.7~0) will assure if the
device goes back to normal reset and enters array read
mode.
3.5 Read Configuration Codes
The read configuration codes operation outputs the manu-
facturer code, device code, sector lock configuration
codes, and the protection register. Using the manufac-
turer and device codes, the system CPU can automati-
cally match the device with its proper algorithms. The
sector lock codes identify locked and unlocked sectors.
3.6 Write
Writing commands to the CUI enable reading of device
data and identifier codes. They also control inspection
and clearing of the status register.WhenVCC=2.7V-3.6V
and VPP within VPP1 or VPP2 range, the CUI addition-
ally controls sector erase, word write and sector lock/
unlock.
The Sector Erase command requires appropriate com-
mand data and an address within the sector to be erased.
The Full Chip Erase command requires appropriate com-
mand data and an address within the device.The Word
Write command requires the command and address of
the location to be written. Set Sector lock/unlock com-
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MX28F160C3BT/B
4 COMMAND DEFINITIONS
The flash memory has four read modes:read array, read
configuration, read status, read query, and two write
modes: program, erase. These read modes are acces-
sible independent of the VPP voltage. But write modes
are disable duringVPP<VPPLK.PlacingVPP onVPP1/
2 enables successful sector erase, word write and sec-
tor lock/unlock.
Device operations are selected by writing specific com-
mands into the CUI.Table 3 defines these commands.
Table 2. Bus Operation
Mode
Notes
RESET#
VIH
CE#
VIL
VIL
VIH
X
OE#
VIL
VIH
X
WE#
VIH
VIH
X
DQ0~DQ15
DOUT
High Z
High Z
High Z
DIN
Read
1,2
Output Disable
Standby
Reset
2
VIH
2
2
VIH
VIL
X
X
Write
2,3,4,5
VIH
VIL
VIH
VIL
Notes:
1. Refer to DC Characteristics for VPPLK, VPP1, VPP2 voltage.
2. X can be VIL or VIH for pin and addresses.
3. RESET# at GND±0.2 to ensure the lowest power consumption.
4. Refer to Table 3 for valid DIN during a write operation.
5. To program or erase the lockable sectors holds WP# at VIH.
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MX28F160C3BT/B
Table 3. Command Definition (1)
Command
Bus
Notes
First Bus Cycle
Second Bus Cycle
Cycles
Operation Address
Data Operation Address Data
Required
(1)
(2)
X
X
X
X
X
X
X
X
(3)
FFH
(1)
(2)
(3)
Read Array
1
> 2
2
Write
Write
Write
Write
Write
Write
Write
Write
Read Configuration
Read Query
2,4
2,7
3
90H
Read
Read
Read
IA
QA
X
ID
98H
QD
Read Status Register
Clear Status Register
Sector Erase/Confirm
Word Write
2
70H
SRD
1
3
50H
2
20H
Write
Write
SA
D0H
WD
2
2,5
40H/10H
B0H
WA
Program/Erase Suspend
1
Program/Erase Resume
1
Write
X
D0H
Sector Lock
2
2
2
2
Write
Write
Write
Write
X
X
X
X
60H
60H
60H
C0H
Write
Write
Write
Write
SA
SA
SA
PA
01H
D0H
2FH
PD
Sector Unlock
6
Lock-Down Sector
Protection Program
Notes:
1. Bus operation are defined in Table 2 and referred to AC Timing Waveform.
2. X=Any address within device.
IA=ID-Code Address (refer toTable 4).
ID=Data read from identifier code.
SA=Sector Address within the sector being erased.
WA=Address of memory location to be written.
WD=Data to be written at location WA.
PA=Program Address, PD=Program Data
QA=Query Address, QD=Query Data.
3. Data is latched from the rising edge of WE# or CE# (whichever goes high first)
SRD=Data read from status register, see Table 6 for description of the status register bits.
4. Following the Read Configuration codes command, read operation access manufacturer, device codes, sector
lock/unlock codes, see chapter 4.2.
5. Either 40H or 10H command is recognized by the WSM as word write setup.
6. The sector unlock operation simultaneously clear all sector lock.
7. Read Query Command is read for CFI query information.
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MX28F160C3BT/B
4.1 Read Array Command
4.3 Read Status Register Command
Upon initial device power-up and after exit from reset
mode, the device defaults to read array mode. This op-
eration is also initiated by writing the Read Array com-
mand. The device remains enabled for reads until an-
other command is written. Once the internal WSM has
started a sector erase, word write or sector lock con-
figuration the device will not recognize the Read Array
command until the WSM completes its operation unless
the WSM is suspended via a Sector Erase Suspend or
Word Write Suspend command. If RESET#=VIL device
is in read Read Array command mode, this read opera-
tion no longer requires VPP. The Read Array command
functions independently of theVPP voltage and RESET#
can be VIH.
CUI writes read status command (70H).The status reg-
ister may be read to determine when a sector erase,
word write or lock-bit configuration is complete and
whether the operation completed successfully. (refer to
table 6) It may be read at any time by writing the Read
Status Register command. After writing this command,
all subsequent read operations output data from the sta-
tus register until another valid command is written.The
status register contents are latched on the falling edge
of CE# or OE#, whichever occurs last.CE# or OE# must
toggle to VIH before further reads to update the status
register latch.The Read Status Register command func-
tions independently of theVPP voltage.RESET# can be
VIH.
4.2 Read Configuration Codes Command
4.4 Clear Status Register Command
The configuration code operation is initiated by writing
the Read Configuration Codes command (90H). To re-
turn to read array mode, write the Read Array Command
(FFH). Following the command write, read cycles from
addresses shown in Table 4 retrieve the manufacturer,
device, sector lock configuration codes and the protec-
tion register(see Table 4 for configuration code values).
To terminate the operation, write another valid command.
Like the Read Array command, the Read Configuration
Codes command functions independently of the VPP
voltage and RESET# can be VIH. Following the Read
Configuration Codes command, the information is shown:
Status register bits SR.5, SR.4, SR.3 or SR.1 are set to
"1"s by the WSM and can only be reset by the Clear
Status Register command (50H). These bits indicate
various failure conditions (seeTable 6).By allowing sys-
tem software to reset these bits, several operations (such
as cumulatively erasing multiple sectors or writing sev-
eral words in sequence) may be performed.The status
register may be polled to determine if an error occurred
during the sequence.
To clear the status register, the Clear Status Register
command (50H) is written on CUI. It functions indepen-
dently of the appliedVPPVoltage. RESET# can beVIH.
This command is not functional during sector erase or
word write suspend modes.
Table 4: ID Code
Code
Address
(A19-A0)
00000H
Data
(DQ15-DQ0)
00C2H
88C2/88C3H
LocK
Manufacturer Code
Device Code(Top/Bottom) 00001H
Sector Lock Configuration XX002H
- Sector is unlocked
DQ0=0
DQ0=1
DQ1=1
PR-LK
- Sector is locked
- Sector is locked-down
Protection Register Lock 80
Protection Register
81-88
PR
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should be checked. If word write error is detected, the
status register should be cleared.The internalWSM verify
only detects errors for "1"s that do not successfully write
to "0"s. The CUI remains in read status register mode
until it receives another command.
4.5 Sector Erase Command
Erase is executed one sector at a time and initiated by a
two-cycle command. A sector erase setup is first writ-
ten (20H), followed by a sector erase confirm (D0H).This
command sequence requires appropriate sequencing and
an address within the sector to be erased. Sector pre-
conditioning, erase, and verify are handled internally by
the WSM. After the two-cycle sector erase sequence is
written, the device automatically outputs status register
data when read (see Figure 8).The CPU can detect sec-
tor erase completion by analyzing the output data of the
status register bit SR.7.
Reliable word writes can only occur when
VCC=2.7V~3.6V andVPP=VPP1/2. IfVPP is not within
acceptable limits, the WSM doesn't execut the program
command.If word write is attempted whileVPP<VPPLK,
status register bits SR.3 and SR.4 will be set to "1".
Successful word write requires for boot sector that WP#
is VIH the corresponding sector lock-bit be cleared. In
parameter and main sectors case, it must be cleared
the corresponding sector lock-bit. If word write is at-
tempted when the excepting above sector being clocked
conditions, SR.1 and SR.4 will be set to "1". Word write
is not functional.
When the sector erase is complete, status register bit
SR.5 should be checked. If a sector erase error is de-
tected, the status register should be cleared before sys-
tem software attempts corrective actions. The CUI re-
mains in read status register mode until a new com-
mand is issued.
4.7 Sector Erase Suspend Command
This two-step command sequence of set-up followed by
execution ensures that sector contents are not acciden-
tally erased. An invalid sector Erase command sequence
will result in both status register bits SR.4 and SR.5
being set to "1". Also, reliable sector erasure can only
occur when 2.7V~3.6V andVPP=VPP1/2.In the absence
of this high voltage, sector contents are protected against
erasure.If sector erase is attempted whileVPP<VPPLK
SR.3 and SR.5 will be set to "1". To successfully erase
the boot sector, the corresponding sector lock-bit must
be clear first. In parameter and sectors case, it must be
cleared the corresponding sector lock-bit. If sector erase
is attempted when the excepting above sector being
locked conditions, SR.1 and SR.5 will be set to "1". Sec-
tor erase is not functional.
The Sector Erase Suspend command (50H) allows sec-
tor-erase interruption to read or word write data in an-
other sector of memory. Once the sector erase process
starts, writing the Sector Erase Suspend command re-
quests that theWSM suspend the sector erase sequence
at a predetermined point in the algorithm. The device
outputs status register data when read after the Sector
Erase Suspend command is written. Polling status reg-
ister bits SR.7 and SR.6 can determine when the sector
erase operation has been suspended (both will be set to
"1"). Specification tWHRH2/tEHRH2 defines the sector
erase suspend latency.
When Sector Erase Suspend command is written to the
CUI, if sector erase was finished, the device would be
placed read array mode. Therefore, after Sector Erase
Suspend command is written to the CUI, Read Status
Register command (70H) has to be written to CUI, then
status register bit SR.6 should be checked if/when the
device is in suspend mode.
4.6 Word Write Command
Word write is executed by a two-cycle command se-
quence.Word write setup (standard 40H or alternate 10H)
is written, followed by a second write that specifies the
address and data.TheWSM then takes over, controlling
the word write and write verify algorithms internally. Af-
ter the word write sequence is written, the device auto-
matically outputs status register data when read (see
Figure 6). The CPU can detect the completion of the
word write event by analyzing the status register bit SR.7.
At this point, a Read Array command can be written to
read data from sectors other than that which is sus-
pended.AWordWrite commands sequence can also be
issued during erase suspend to program data in other
sectors. Using the Word Write Suspend command (see
Section 4.9), a word write operation can also be sus-
pended. During a word write operation with sector erase
suspended, status register bit SR.7 will return to "0".
When word write is complete, status register bit SR.4
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MX28F160C3BT/B
However, SR.6 will remain "1" to indicate sector erase
suspend status.
is suspended are Read Status Register Read Configura-
tion, Read Query and Word Write Resume. After Word
Write Resume command is written to the flash memory,
the WSM will continue the Word write process. Status
register bits SR.2 and SR.7 will automatically be cleared.
After the Word Write Resume command is written, the
device automatically outputs status register data when
read (see Figure 7).VPP must remain at VPP1/2 while
in word write suspend mode.RESET# must also remain
at VIH (the same RESET# level used for word write).
The only other valid commands while sector erase is
suspended are Read Status Register, Read Configura-
tion, Read Query, Program Setup, Program Resume,
Sector Lock, Sector Unlock, Sector Lock-Down and sec-
tor erase Resume. After a Sector Erase Resume com-
mand is written to the flash memory, the WSM will con-
tinue the sector erase process. Status register bits SR.6
and SR.7 will automatically be cleared. After the Erase
Resume command is written, the device automatically
outputs status register data when read (see Figure 9).
VPP must remain at VPP1/2 while sector erase is sus-
pended. RESET# must also remain at VIH (the same
RESET# level used for sector erase). Sector cannot re-
sume until word write operations initiated during sector
erase suspend has completed.
If the time between writing theWordWrite Resume com-
mand and writing the Word Write Suspend command is
short and both commands are written repeatedly, a longer
time is required than standard word write until the comple-
tion of the operation.
If the time between writing the Sector Erase Resume
command and writing the Sector Erase Suspend com-
mand is shorter than 15ms and both commands are writ-
ten repeatedly, a longer time is required than standard
sector erase until the completion of the operation.
4.8 Word Write Suspend Command
The Word Write Suspend command allows word write
interruption to read data in other flash memory locations.
Once the word write process starts, writing the Word
Write Suspend command requests that the WSM sus-
pend theWord write sequence at a predetermined point
in the algorithm. The device continues to output status
register data when read after the Word Write Suspend
command is written.Polling status register bits SR.7 and
SR.2 can determine when the word write operation has
been suspended (both will be set to "1"). Specification
tWHRH1/tEHRH1 defines the word write suspend latency.
WhenWordWrite Suspend command write to the CUI, if
word write was finished, the device places read array
mode. Therefore, after Word Write Suspend command
write to the CUI, Read Status Register command (70H)
has to be written to CUI, then status register bit SR.2
should be checked for if/when the device is in suspend
mode.
At this point, a Read Array command can be written to
read data from locations other than that which is sus-
pended.The only other valid commands while word write
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4.9 Sector Lock/Unlock /Lockdown Command
4.9.1 Sector Locked State
4.9.4 Read Sector Lock Status
The lock status of every sector can be read through
Read Configuration mode.To enter this mode, first com-
mand write 90H to the device.The subsequent reads at
sector address +00002 will output the lock status of this
sector.The lock status can be read from the lowest two
output pins DQ0 and DQ1. DQ0, DQ0 indicates the sec-
tor lock/unlock status and set by the lock command and
cleared by the unlock command. When entering lock-
down, the lock status is automatically set. DQ1 indi-
cates lock-down status and is set by the lock-down com-
mand. It cannot be further cleared by software, only by
device reset or power-down.
The default status of all sectors upon power-up or reset
is locked. Any attempt on program or erase operations
will result in an error on bit SR.1 of a locked sector. The
status of a locked sector can be changed to unlocked or
lock-down using software commands. An unlocked sec-
tor can be locked by writing the sector lock command
sequence, 60H followed by 01H.
4.9.2 Sector Unlocked State
An unlocked sector can be programmed or erased. All
unlocked sector return to the locked state when the de-
vice is either reset or powered down. The status of an
unlocked sector can be changed to locked or locked-
down using software commands. A locked sector can
be unlocked by writing unlock command sequence, 60H
followed by D0H.
Sector Lock Configuration Table
Lock Status
Data
Sector is unlocked
Sector is locked
Sector is locked-down
DQ0=0
DQ0=1
DQ1=1
4.9.3 Sector Locked-Down State
Sectors which are locked-down are protected from pro-
gram and erase operation; however, the protection sta-
tus of these sectors cannot be changed using software
commands alone. Any sector locked or unlocked can be
locked-down by writing the lock-down command se-
quence, 60H followed by 2FH.When the device is reset
or powered down, the locked-down sectors will revert to
the locked state.
The status of WP# will determine the function of sector
lock-down and is summarized is followed:
WP#
Sector Lock-down Description
WP#=0 - sectors are protected from program, erase,
and lock status changes
WP#=1 - the sector lock-down function is disabled
- an individual lock-down sector can be un-
locked and relocked via software command.
Once WP# goes low, sectors that previously
locked-down returns to lock-down state
regardless of any changes whenWP# was
high.
In addition, sector lock-down is cleared only when the
device is reset or powered down.
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MX28F160C3BT/B
sector is being placed in erase suspend, the locking sta-
tus bits will be changed immediately, but when the erase
is resumed, the erase operation will complete.
4.9.5 Sector Locking while Erase Suspend
The sector lock status can be performed during an erase
suspend by using standard locking command sequences
to unlock, lock, or lock-down a sector.
Locking operation cannot be performed during a program
suspend.
In order to change sector locking during an erase opera-
tion, the write erase suspend command (B0H) is placed
first; then check the status register until it is shown that
the actual erase operation has been suspended. Subse-
quent writing the desired lock command sequence to a
sector and the lock status will be changed. When com-
pleting any desired lock, read or program operation, re-
sume the erase operation with the Erase Resume Com-
mand (D0H).
4.9.6 Status Register Error Checking
The operation of locking system for this device can be
used the term "state (X,Y,Z)" to specify locking status,
where X=value of WP#, Y=bit DQ1 of the sector lock
status register, and Z=bit DQ0 of the sector lock status
register. DQ0 indicates if a sector is locked (1) or un-
locked (0). DQ1 indicates if a sector has been locked-
down(1) or not (0).
If a sector is locked or locked-down during the same
Table 5. Sector Locking State Transitions
Current State
Erase/Prog.
Operation if
Lock Command Input Result (Next State)
(X,Y, Z)=
(X,Y, Z)=
WP# DQ1 DQ0
Name
Unlocked
Enable ?
Yes
No
Lock
(001)
Unlock
Unchanged
(000)
Lock-Down
(011)
0
0
0
1
1
1
1
0
0
1
0
0
1
1
0
1
1
0
1
0
1
Locked (default)
Locked-Down
Unlocked
Unchanged
Unchanged
(101)
(011)
No
Unchanged
Unchanged
(100)
Unchanged
(111)
Yes
No
Locked
Unchanged
(111)
(111)
Lock-Down Disabled
Lock-Down Disabled
Yes
No
Unchanged
(110)
(111)
Unchanged
Unchanged
Note:
At power-up or device reset, all sectors default to locked state (001) (if WP#=0).
HoldingWP#=0 is the recommended default.
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Table 6. Status Register Definition
WSMS
7
SESS
6
ES
5
PS
4
VPPS
3
PSS
2
SLS
1
R
0
NOTES:
Check WSM bit first to determine word program or sec-
tor Erase completion, before checking Program or Erase
Status bits.
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
When Sector Erase Suspend is issued, WSM halts ex-
ecution and sets bothWSMS and SESS bits to "1".SESS
bit remains set to "1" until an Sector Erase Resume
command is issued.
SR.6 = SECTOR ERASE SUSPEND STATUS (SESS)
1 = Sector ERASE Suspended
0 = Sector Erase in Progress/Completed
SR.5 = ERASE STATUS (ES)
1 = Error in Programming
0 = Successful Sector Erase or Clear Sector Lock-
Bits
When this bit (SR.5) is set to "1", it means WSM is
unable to verify successful sector erasure.
When this bit is set to "1", WSM has attempted but failed
to program a word.
SR.4 = PROGRAM STATUS (PS)
1 = Error in Programming
0 = Successful Programming
The WSM interrogatesVPP level only after the Program
or Erase command sequences have been entered and
informs the system if VPP has not been switched on.
SR.3 bit is not guaranteed to report accurate feedback
between VPPLK and VPP1 min.
SR.3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
When program suspend is issued, WSM halts the ex-
ecution and sets both WSMS and PSS bits to "1". SR.2
remains set to "1" until a Program Resume command is
issued.
SR.2 = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/Completed
If a program or erase operation is attempted to one of
the locked sectors, this bit is set by the WSM. The op-
eration specified is aborted and the device is returned to
read status mode.
SR.1 = SECTOR LOCK STATUS (SLS)
1 =Program/Erase attempted an a locked sector;
operation aborted
0 = No operation to locked sectors
SR. 0 is reserved for future use and should be masked
out when polling the status register.
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS
(R)
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MX28F160C3BT/B
read cycles from addresses shown in Table 7 will re-
trieve the specified information. To return to read array
mode, write the Read Array Command (FFH).
5. 128-Bit Protection Register
The 128 bits of protection register are divided into two
64-bit segments. One of the segments is programmed
at MXIC side with unique 64-bit number; where changes
are forbidden. The other segment is left empty for cus-
tomer to program. Once the customer segment is pro-
grammed, it can be locked to prevent further reprogram-
ming.
Two-cycle Protection Program Command is used to pro-
gram protection register bits. The 64-bit number is pro-
grammed 16 bits at a time. First, write C0H Protection
Program Setup command. The next write to the device
will latch in address and data and program the specified
location.The allowable address are also shown inTable
7. Refer to Figure 11 for the Protection Register Pro-
gramming Flowchart.
5.1 Protection Register Read & Programming
Any attempt to address Protection Program command
onto undefined protection register address space will
result in a Status Register error (SR.4 set to "1"). In
addition, attempting to program to a previously locked
protection register segment will result in a status regis-
ter error (SR.4=1, SR.1=1).
The protection register is read in the configuration read
mode, which follows the stated Command Bus Defini-
tions.
The device is switched to this read mode by writing the
Read Configuration command (90H). Once in this mode,
Table 7. Word-Wide Protection Register Addressing
Word
Lock
User
Both
A7
1
A6
0
A5
0
A4
0
A3
0
A2
0
A1
0
A0
0
0
1
2
3
4
5
6
7
Factory
Factory
Factory
Factory
Customer
Customer
Customer
Customer
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
Notes: 1. Set address bit A19-A15=1 for TOP Boot device.
2. Set address bit A19-A15=0 for Bottom Boot device.
3.The address not specified in above are don't care.
Table 8. Protection Register Memory Map
5.2 Protection Register Locking
The user-programmable segment of the protection reg-
ister is lockable by programming Bit 1 of the PR-Lock
location to 0. Bit 0 of this location is programmed to 0 at
MXIC to protect the unique device number. This bit is
set using the protection program command to program
"FFFD" to PR-LOCK location. After these bits have been
programmed, no further changes can be made to the
value stored in the protection register. Protection Pro-
gram command to a locked section will result in a status
register error (Program Error bit SR.4 and Lock Error bit
SR.1 will be set to 1). Protection register lockout state is
not reversible.
Protection Register Purpose
Bit Address
88H~85H
4 words User Program
Register
84H~81H
4 words Factory Program
Register
80H(Bit0 & Bit1)
Protection Register Lock
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These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and ex-
tended exposure beyond the "Operation Conditions" may
affect device reliability.
6 ELECTRICAL SPECIFICATIONS
6.1 ABSOLUTE MAXIMUM RATINGS
OperatingTemperature
During Read, Sector Erase, Word
1. Minimum DC voltage is -0.5V on input/output pins.
During transitions, this level may undershoot to -2.0V
for periods <20ns. Maximum DC voltage on input/out-
put pins to VCC+0.5V which during transition; may
overshoot to VCC+2.0V for periods <20ns.
2. Maximum DC voltage on VPP may overshoot to
+14.0V for periods <20ns.
3. Output shorted for no more than one second.No more
than one output shorted at a time.
Write . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
Storage Temperature . . . . . . . . . . . . . .-65oC to +125oC
Voltage on Any Pin (except VCC and
VPP) with respect to GND . . . . . . . . .-0.5 V to +3.7V(1)
VPP Supply Voltage (for Sector Erase and Word Write)
with respect to GND . . . . . . . . . .-0.5V to +13.5V(1,2,4)
VCC andVCCQ SupplyVoltage
with respect to GND. . . . . . . . . . . . . . . . .-0.2V to +3.6V(1)
Output Short Circuit Voltage . . . . . . . . . . . . .100mA(3)
4. VPP voltage is normally 1.65V~3.6V. Connection to
supply of 11.4V~12.6V can only be done for 1000
cycles on the main sectors and 2500 cycles on the
parameter sectors during program/erase. VPP may
be connected to 12V for a total of 80 hours maximum.
WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
6.2 Operating Conditions (Temperature andVCC Operating Conditions)
Symbol
TA
Parameter
Min.
-40
Max.
+85
3.6
Unit
oC
V
Notes
OperatingTemperature
VCC SupplyVoltage
I/O Supply Voltage
SupplyVoltage
VCC1
VCCQ
VPP1
VPP2
Cycling
2.7
1
2.7
3.6
V
1
1.65
11.4
100,000
3.6
V
1
SupplyVoltage
12.6
V
1,2
2
Sector Erase Cycling
NOTE:
1. VCC and VCCQ must share the same supply when they are in the VCC1 range.
2. Applying VPP=11.4~12.6V during a program/erase can only be done for a maximum of 1000 cycles on the main
sectors and 2500 cycles on the parameter sectors.VPP may be connected to 12V for a total of 80 hours maximum.
6.2.1 Capacitance (1) (TA=+25oC, f=1MHz)
Symbol
CIN
Parameter
Typ.
6
Max.
8
Unit
pF
Test Condition
VIN=0.0V
Input Capacitance
Output Capacitance
COUT
10
12
pF
VOUT=0.0V
NOTE:
1.Sampled, not 100% tested.
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MX28F160C3BT/B
6.2.2 AC Input/Output Test Conditions
VCCQ
VCCQ/2 Output
TEST POINTS
Input VCCQ/2
0.0
Note:AC test inputs are driven at VCCQ/2 for a Logic "1" and 0.0V for a Logic "0".
Figure 1.Transient Input/Output ReferenceWaveform
Figure 2. SWITCHINGTEST CIRCUITS
TEST SPECIFICATIONS
Test Condition
Output Load
70 90 110 Unit
1 TTL gate
DEVICE UNDER
TEST
2.7K ohm
3.3V
Output Load Capacitance, CL 30 100 100 pF
(including jig capacitance)
Input Rise and Fall Times
Input Pulse Levels
5
ns
V
0.0-3.0
1.5
CL
6.2K ohm
DIODES=IN3064
OR EQUIVALENT
Input timing measurement
reference levels
V
Output timing measurement
reference levels
1.5
V
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MX28F160C3BT/B
6.2.3 AC Characteristic -- Read Only Operation (1)
-70
-90
Min.
Sym.
Parameter
Notes
Min.
Max.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVAV
tAVQV
tELQV
tGLQV
tPHQV
tELQX
tGLQX
tEHQZ
tGHQZ
tOH
Read CycleTime
70
90
Address to Output Delay
CE# to Output Delay
OE# to Output Delay
RESET# to Output Delay
CE# to Output in Low Z
OE# to Output in Low Z
CE# to Output in High Z
OE# to Output in High Z
Output Hold from Address,
CE#, or OE# Change,
Whichever Occurs First
70
70
90
90
2
2
20
30
150
150
3
3
3
3
3
0
0
0
0
20
20
20
20
0
0
Notes:
1. See AC Waveform:Read Operations at Figure 3.
2. OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV.
3. Sampled, but not 100% tested.
4. See test Configuration.
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MX28F160C3BT/B
Figure 3. READ-ONLY OPERATION AC WAVEFORM
Device and
Address Selection
Data
Valid
Standby
VIH
VIL
Addresses(A)
CE# (E)
Address Stable
tAVAV
VIH
VIL
tEHQZ
tGHQZ
VIH
VIL
OE# (G)
WE# (W)
VIH
VIL
tGLQV
tGLQX
tOH
tELQV
tELQX
VOH
VOL
DATA
(D/Q)
High Z
High Z
Valid Output
tAVQV
VIH
tPHQV
RESET# (P)
VIL
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MX28F160C3BT/B
6.2.5 AC Characteristic -- Write Operation
-70
Min.
150
0
-90
Min.
150
0
Sym.
Parameter
Note
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPHWL/tPHEL
tELWL/tWLEL
tWLWH/tELEH
tDVWH/tDVEH
tAVWH/tAVEH
RESET# High Recovery to WE#(CE#) Going Low
CE#(WE#) Setup toWE#(CE#) Going Low
WE#(CE#) PulseWidth
4
2
2
45
40
50
0
60
50
60
0
Data Setup toWE#(CE#) Going High
Address Setup to WE#(CE#) Going High
tWHEH/tEHWH CE#(WE#) HoldTime fromWE#(CE#) High
tWHDX/tEHDX
tWHAX/tEHAX
tWHWL/tEHEL
tVPWH/tVPEH
tQVVL
Data HoldTime fromWE#(CE#) High
Address HoldTime from WE#(CE#) High
WE#(CE#) Pulse Width High
2
2
4
3
3
3
3
3
0
0
0
0
25
200
0
30
200
0
VPP Setup to WE#(CE#) Going High
VPP Hold from Valid SRD
tBHWH/tBHEH
tQVBL
WP# Setup toWE#(CE#)Going High
WP# Hold fromValid SRD
0
0
0
0
tWHGL
WE# High to OE# Going Low
30
30
Notes:
1. Write timing characteristics during erase suspend are the same as during write-only operations.
2. Refer to Table 5 for valid AIN or DIN.
3. Sampled, not 100% tested.
4. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# orWE# going high
(whichever goes high first).Hence, tWP=tWLWH=tELEH=tWLEH=tELWH.Similarly, Write pulse width high (tWPH)
is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low
first). Hence, tWPH=tWHWL=tEHEL=tWHEL=tEHWL.
5. SeeTest Configuration.
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MX28F160C3BT/B
Figure 4. WRITE AND ERASE OPERATION AC WAVEFORM
A
B
C
D
E
F
VIH
VIL
Address (A)
AIN
AIN
tAVWH
(tAVEH)
tWHAX
(tEHAX)
(Note 1)
VIH
VIL
CE#(WE#)[E(W)]
OE#(G)
tELWL
(tWLEL)
tWHEH
(tEHWH)
VIH
VIL
tWHWL
(tEHEL)
tWHGL
(Note 1)
Disable
WE#,(CE#)[W(E)]
Enable
VIH
VIL
tELEH
(tWLWH)
tDVWH
(tEVEH)
tWHDX
(tEHDX)
VIH
VIL
High Z
Valid
SRD
DATA[D/Q]
RESET#[P]
DIN
DIN
DIN
tPHWL
(tPHEL)
VOH
VOL
tQVBL
tQVVL
tBHWH
(tBHEH)
VIH
VIL
WP#
tVPWH
(tVPEH)
VPPH2
VPPH1
VPP[V]
VPPLK
VIL
Notes:
1. CE# must be toggled low when reading Status Register Data. WE# must be inactive (high) when reading Status
Register Data.
A.VCC Power-Up and Standby.
B.Write Program or Erase Setup Command.
C.Write Valid Address and Data (for Program) or Erase Confirm Command.
D.Automated Program or Erase Delay.
E.Read Status Register Data (SRD): reflects completed program/erase operation.
F.Write Read Array Command.
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MX28F160C3BT/B
6.2.5 Erase and Program Timing (1)
Vpp
Note
2,3
1.65V-3.6V
11.4V-12.6V
Symbol
Parameter
Typ(1)
Max
Typ(1)
Max
Unit
tBWPB
4-KW Parameter Sector
Word ProgramTime
32-KW Main Sector
Word ProgramTime
Word ProgramTime
0.10
0.8
12
0.30
0.03
0.24
8
0.12
s
tBWMB
2,3
2,3
2,3
2,3
3
2.4
200
4
1
185
4.0
5
s
us
s
tWHQV1/
tEHQV1
tWHQV2/
tEHQV2
tWHQV3/
tEHQV3
tWHRH1/
tEHRH1
tWHRH2/
tEHRH2
4-KW Parameter Sector
Erase Time
0.5
1
0.4
0.6
15
32-KW Main Sector
Erase Time
5
s
Program Suspend Latency
15
20
20
20
20
us
us
Erase Suspend Latency
3
15
15
Notes:
1. Typical values measured at TA=+25° C and nominal voltage.
2. Excludes external system-level overhead.
3. Sampled, but not 100% tested.
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MX28F160C3BT/B
Figure 5. RESET WAVEFORM
VIH
VIL
RESET# (P)
tPHQV
tPHWL
tPHEL
tPLPH
tPLRH
(A) Reset during Read Mode
tPHQV
tPHWL
tPHEL
Abort
Complete
VIH
RESET# (P)
VIL
tPLPH
(B) Reset during Program or Sector Erase, tPLPH < tPLRH
Abort
Deep
Power-
Down
tPHQV
tPHWL
tPHEL
Complete
tPLRH
VIH
VIL
RESET# (P)
tPLPH
(C) Reset Program or Sector Erase, tPLPH > tPLRH
AC Characteristic -- Under Reset Operation
Sym.
Parameter
VCC=2.7V~3.6V
Unit Notes
Min.
Max.
tPLPH RESET# Low to Reset during Read
100
ns
1,3
(If RESET# is tied to VCC, this specification is not applicable)
tPLRH1 RESET# Low to Reset during Sector Erase
tPLRH2 RESET# Low to Reset during Program
22
12
us
us
1,4
1,4
Notes:
1. See Section 3.4 for a full description of these conditions.
2. If tPLPH is < 100ns the device may still reset but this is not guaranteed.
3. If RESET# is asserted while a sector erase or word program operation is not executing, the reset will complete
within 100ns.
4. Sampled, but not 100% tested.
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MX28F160C3BT/B
6.2.6 DC Characteristics
VCC
2.7V-3.6V
2.7V-3.6V
Sym.
ILI
Parameter
VCCQ
Unit
uA
Test Conditions
Note Typ.
Max.
Input Load Current
1,2
± 1
VCC=VCC Max. ;VCCQ=VCCQ Max.
VIN=VCCQ or GND
ILO
Output Leakage
Current
1,2
1
0.2
7
± 10
uA
VCC=VCC Max. ;VCCQ=VCCQ Max.
VIN=VCCQ or GND
ICCS
VCC Standby Current
15
uA
VCC=VCC Max. ; CE#=RESET#=VCCQ
or during Program/Erase Suspend
WP#=VCCQ or GND
ICCD
ICCR
VCC Power-Down
Current
1,2
7
9
15
18
5
uA
mA
uA
VCC=VCC Max ; VCCQ=VCCQ Max
VIN=VCCQ or GND
RESET#=GND±0.2V
VCC Read Current
1,2,3
VCC=VCC Max ;VCCQ=VCCQ Max
OE#=VIH, CE#=VIL, f=5MHz,
IOUT=0mA, Inputs=VIL or VIH
RESET#=GND±0.2V
IPPD
IPPR
VPP Deep Power-
Down Current
1
0.2
VPP < VCC
VPP Read Current
1,4
1,4
1,4
1,4
2
±15
200
55
uA
uA
VPP < VCC
50
18
10
21
16
7
VPP > VCC
ICCW+ VCC+VPP Program
IPPW Current
ICCE+ VCC+VPP Erase
IPPE Current
ICCES VCC Program
or or Erase Suspend
ICCWS Current
mA
mA
mA
mA
uA
VPP=VPP1, Program in Progress
VPP=VPP2(12V), Program in Progress
VPP=VPP1, Erase in Progress
VPP=VPP2(12V), Erase in Progress
CE#=VCC,
30
45
45
15
Program or Erase Suspend in Progress
VIL
Input LowVoltage
-0.4
VCC*0.22V
V
V
V
VIH
VOL
Input HighVoltage
Output LowVoltage
2.0 VCCQ+0.3V
-0.1
0.1
VCC=VCC Min,VCC=VCCQ Min
IOL=100uA
VOH
Output HighVoltage
VCCQ
-0.1V
V
VCC=VCC Min,VCC=VCCQ Min
IOH=-100uA
VPPLK VPP Lock-OutVoltage
6
6
6
1.0
3.6
V
V
V
V
CompleteWrite Protection
VPP1
VPP2
VLKO
VPP during Program/
Erase Operations
VCC Prog/Erase
LockVoltage
1.65
11.4
1.5
12.6
VLKO2 VCCQ Prog/Erase
LockVoltage
1.2
V
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MX28F160C3BT/B
Notes:
1. All currents are in RMS unless otherwise noted.Typical values at nominal VCC, TA=+25°C.
2. The test conditions VCC Max, VCCQ Max, VCC Min, and VCCQ Min refer to the maximum or minimum VCC or
VCCQ voltage listed at the top of each column.
3. Power Savings (Mode) reduces ICCR to approximately standby levels in static operation (CMOS inputs).
4. Sampled, but not 100% tested.
5. ICCES and ICCWS are specified with device de-selected. If device is read while in erase suspend, current draw is
sum of ICCES and ICCR. If the device is read while in program suspend, current draw is the sum of ICCWS and
ICCR.
6. Erase and Program are inhibited whenVPP<VPPLK.
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MX28F160C3BT/B
Figure 6. Automated Word Programming Flowchart
Bus
Command Comments
Start
Operation
Write
Program
Setup
Data=40H
Write 40H
Write
Read
Program
Data=Data to Program
Addr=Location to Program
Status Register DataToggle
CE# or OE# to Update
Status Register Data
Check SR.7
Program Address/Data
Read Status Register
Standby
1=WSM Ready
0=WSM Busy
No
SR.7=1 ?
Repeat for subsequent programming operations.
SR full status check can be done after each program
or after a sequence of program operations.
Write FFH after the last program operation to reset
device to read array mode.
Yes
Full Status
Check if Desired
Program Ccomplete
Bus
Command
Comments
FULL STATUS CHECK PROCEDURE
Operation
Standby
Read Status Register
Data(See Above)
Check SR.3
1=VPP Low Detect
Check SR.4
Standby
Standby
1=VPP Program Error
Check SR.1
1
VPP Range Error
Programming Error
SR.3=
1=Attempted Program to
Locked Sector-Program
Aborted
0
1
1
SR.4=
0
SR.3 MUST be cleared, if set during a program at-
tempt, before further attempts are allowed by theWrite
State Machine.
SR.4, SR.3, and SR.1 are only cleared by the Clear
Status Register Command, in cases where multiple
bytes are programmed before full status is checked.
If an error is detected, clear the status register before
attempting retry or other error recovery.
Attempted Program to
Locked Sector- Aborted
SR.1=
0
Program Successful
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MX28F160C3BT/B
Figure 7. Program Suspend/Resume Flowchart
Start
Bus
Command Comments
Operation
Write
Program
Suspend
Data=B0H
Addr=X
Write B0H
Write 70H
Write
Read
Read Status Data=70H
Addr=X
Status Register DataToggle
Read
Status Register
CE# or OE# to Update
Status Register Data
Addr=X
0
Standby
Stanby
Check SR.7
SR.7=
1=WSM Ready
0=WSM Busy
1
Check SR.2
0
1=Program Suspended
0=Program Completed
SR.2=
Program Completed
1
Write
Read
Read Array Data=FFH
Addr=X
Write FFH
Read array data from
sector other than the one
being programmed.
Data=D0H
Read Array Data
Done Reading
Write
Program
Resume
Addr=X
No
Yes
Write D0H
Write FFH
Program Write Resumed
Read Array Data
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MX28F160C3BT/B
Figure 8. Automated Sector Erase Flowchart
Bus
Command Comments
Start
Operation
Write
Erase Setup Data=20H
Write 20H
Addr=Within Sector to Be
Erased
Write
Erase
Data=D0H
Write D0H and
Sector Address
Confirm
Addr=Within Sector to Be
Erased
Read
Status Register
Suspend
Erase Loop
Read
Status Register DataToggle
CE# or OE# to Update
Status Register Data
Check SR.7
No
Yes
0
SR.7=
Suspend Erase
Standby
1=WSM Ready
0=WSM Busy
1
Repeat for subsequent sector erasures.
Full status check can be done after each sector erase
or after a sequence of sector erasures.
Write FFH after the last write operation to reset device
to read array mode.
Full Status Check if Desired
Sector Erase Complete
FULL STATUS CHECK PROCEDURE
Bus
Command
Comments
Operation
Standby
Read Status Register
Data(See Above)
Check SR.3
1=VPP Low Detect
Check SR.4, 5
Both 1=Command
Sequence Error
Check SR.5
Standby
1
VPP Range Error
SR.3=
0
Standby
Standby
1=Sector Erase Error
Check SR.1
1
SR.4,5=
Command Sequence Error
1=Attempted Erase of
Locked Sector- Erase
Aborted
0
1
SR.5=
Sector Erase Error
SR.1 and SR.3 MUST be cleared, if set during an erase
attempt, before further attempts are allowed by the
Write State Machine.
0
SR.1,3,4,5 are only cleared by the Clear Status Reg-
ister Command, in cases where multiple bytes are
erased before full status is checked.
Attempted Erase of Locked
Sector - Aborted
1
SR.1=
0
If an error is detected, clear the status register before
attempting retry or other error recovery.
Sector Erase Successful
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MX28F160C3BT/B
Figure 9. Erase Suspend/Resume Flowchart
Bus
Command Comments
Start
Operation
Write
Erase
Data=B0H
Addr=X
Write B0H
Write 70H
Suspend
Write
Read
Read Status Data=70H
Addr=X
Status Register DataToggle
Read
Status Register
CE# or OE# to Update
Status Register Data
Addr=X
0
Standby
Stanby
Check SR.7
SR.7=
1=WSM Ready
0=WSM Busy
1
Check SR.6
0
1=Erase Suspended
0=Erase Completed
SR.6=
Erase Completed
Write
Read
Read Array Data=FFH
1
Addr=X
Write FFH
Read array data from
sector other than the one
being erased.
Data=D0H
Read Array Data
Done Reading
Write
Erase
Resume
Addr=X
No
Yes
Write D0H
Write FFH
Erase Write Resumed
Read Array Data
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MX28F160C3BT/B
Figure 10. Locking Operations Flowchart
Bus
Command
Comments
Operation
Write
Start
Config. Setup Data=60H
Addr=X
Write 60H
(Configuration Setup)
Write
Lock, unlock Data=01H (Sector Lock)
or Lockdown
D0H(Sector Unlock)
2FH(Sector Lockdown)
Addr=Within sector to lock
Write
01H, D0H, or 2FH
Write
Read Status Data=70H
(Optional) Register
Read
(Optional)
Stanby
Addr=X
Status Register Register
Addr=X
Check Status Register
80H=no error
Write 70H
(Read Status Register)
Lock Command
Read Status Register
Sequence Error
(Optional)
30H=Lock Command
Sequence Error
Data=90H
1,1
SR.4, SR.5=
Write
Read
(Optional) Configuration Addr=X
0,0
Read
Sector Lock Sector Lock Status Data
Write 90H
(Read Configuration)
(Optional)
Status
Addr=Second addr of
sector
Stanby
Confirm Locking Change
on DQ1, DQ0 (See Sector
Locking State Table for
valid combinations.)
Read Sector Lock Status
No
Locking Change
Confirmed ?
Yes
Locking Change
Complete
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MX28F160C3BT/B
Figure 11. Protection Register Programming Flowchart
Bus
Command Comments
Start
Operation
Write
Protection
Program
Setup
Data=C0H
Write C0H
(Protection Reg. Program Setup)
Write
Read
Protection
Program
Data=Data to Program
Addr=Location to Program
Status Register DataToggle
CE# or OE# to Update
Status Register Data
Check SR.7
Write Protect. Register
Address/Data
Read Status Register
Standby
1=WSM Ready
No
SR.7=1 ?
Yes
0=WSM Busy
Protection Program operations can only be addressed
within the protection register address space. Addresses
outside the defined space will return an error.
Repeat for subsequent programming operations.
SR Full Status Check can be done after each program
or after a sequence of program operations.
Write FFH after the last operation to reset device to
read array mode.
Full Status
Check if Desired
Program Ccomplete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data(See Above)
Bus
Command
Comments
Operation
Standby
SR.1, SR.3, SR.4
0
0
1
0
1 VPP Low
1 Prot. Reg.
Prog. Error
1 Register
Locked:
1,1
VPP Range Error
SR.3, SR.4=
Standby
Stanby
1
0
Protection Register
programming Error
0,1
SR.1, SR.4=
Aborted
SR.3 MUST be cleared, if set during a program at-
tempt, before further attempts are allowed by theWrite
State Machine.
Attempted Program to
Locked Register Aborted
1,1
SR.1,3,4 are only cleared by the Clear Status Regis-
ter Command, in cases of multiple protection register
program operations before full status is checked.
If an error is detected, clear the status register before
attempting retry or other error recovery.
SR.1, SR.4=
Program Successful
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MX28F160C3BT/B
7 VPP Program and Erase Voltage
MX28F160C3BT/B product provides in-system program-
ming and erase in the 1.65V~3.6V of VPP range. In ad-
dition,VPP pin on 12V provides fast production program-
ming.
7.1 VPP Fast manufacturing Programming
WhenVPP is between 1.65V and 3.6V, all program and
erase current is drawn through the VCC pin. If VPP is
driven by a logic signal, VIH=1.65V. That is, VPP must
remain above 1.65V to perform in-system flash update/
modifications. When VPP is connected to a 12V power
supply, the device draws program and erase current di-
rectly from the VPP pin.
7.2 Protection Under VPP<VPPLK
VPP can off additional hardware write protection. The
VPP programming voltage can be kept low for the abso-
lute hardware protection of all sector in the flash device.
As VPP is below VPPLK, any program or erase opera-
tion will result in a error, prompting the corresponding
status register bit (SR.3) to be set.
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MX28F160C3BT/B
The single cycle Query command is valid only when the
device is in the Read mode, including Erase Suspend,
Program Suspend, Standby mode, and Read ID mode;
however, it is ignored otherwise.
8. QUERY COMMAND AND COMMON FLASH
INTERFACE (CFI) MODE
MX28F160C3BT/B is capable of operating in the CFI
mode. This mode allows the host system to determine
the manufacturer of the device such as operating pa-
rameters and configuration.Two commands are required
in CFI mode. Query command of CFI mode is placed
first, then the Reset command exits CFI mode. These
are described inTable 3.
The Reset command exits from the CFI mode to the
Read mode, or Erase Suspend mode, Program Suspend
or read ID mode. The command is valid only when the
device is in the CFI mode.
Table 9-1. CFI mode: Identification Data Values
(All values in these tables are in hexadecimal)
Description
Addressh
Datah
0051
0052
0059
0003
0000
0035
0000
0000
0000
0000
0000
Query-unique ASCII string "QRY"
10
11
12
13
14
15
16
17
18
19
1A
Primary vendor command set and control interface ID code
Address for primary algorithm extended query table
Alternate vendor command set and control interface ID code (none)
Address for secondary algorithm extended query table (none)
Table 9-2. CFI Mode: System Interface Data Values
Description
Addressh
Datah
0027
0036
00B4
00C6
0005
0000
000A
0000
0004
0000
0003
0000
VCC supply, minimum (2.7V)
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
VCC supply, maximum (3.6V)
VPP supply, minimum (11.4V)
VPP supply, maximum (12.6V)
Typical timeout for single word write (2N us)
Typical timeout for maximum size buffer write (2N us)
Typical timeout for individual sector erase (2N ms)
Typical timeout for full chip erase (2N ms) (not supported)
Maximum timeout for single word write times (2N X Typ)
Maximum timeout for maximum size buffer write times (2N X Typ)
Maximum timeout for individual sector erase times (2N X Typ)
Maximum timeout for full chip erase times (not supported)
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MX28F160C3BT/B
Table 9-3. CFI Mode: Device Geometry Data Values
Description
Device size (2n bytes)
Addressh
Datah
0015
0001
0000
0000
0000
0002
27
28
29
2A
2B
2C
Flash device interface code (asynchronous x16)
Maximum number of bytes in write buffer=2n (not supported)
Number of erase sector regions within device (one or more continuous
same-size erase sectors at one sector region)
T B
1E 07
00 00
00 20
01 00
T B
Erase Sector Region 1 information
2D
2E
2F
30
[2E,2D] = number of same-size sectors in region 1-1
[30, 2F] = region erase sector size in multiples of 256-bytes
Erase Sector Region 2 information
31
32
33
34
07 1E
00 00
20 00
00 01
[32,31] = number of same-size sectors in region 2-1
[34,33] = region erase sector size in multiples of 256-bytes
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MX28F160C3BT/B
Table 9-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values
Description
Addressh
Datah
0050
0052
0049
0031
0030
66
Query-unique ASCII string "PRI"
35
36
37
38
39
3A
3B
3C
3D
Major version number, ASCII
Minor version number, ASCII
OptionalFeature&CommandSupport
bit 0 Chip Erase Supported (1=yes, 0=no)
bit 1 Suspend Erase Supported (1=yes, 0=no)
bit 2 Suspend Program Supported (1=yes, 0=no)
bit 3 Lock/Unlock Supported (1=yes, 0=no)
bit 4 Queued Erase Supported (1=yes, 0=no)
bit 5 Instant individual sector locking supported (1=yes, 0=no)
bit 6 Protection bits supported (1=yes, 0=no)
bit 7 Page mode read supported (1=yes, 0=no)
bit 8 Synchronous read support (1=yes, 0=no)
bits 9-31 revered for future use; undefined bits are "0"
Supported functions after suspend
00
00
00
3E
01
bit 0 Program supported after erase suspend (1=yes, 0=no)
bit 1-7 Reserved for other supported options; undefined bits are "0"
Sector Lock Status
3F
40
03
00
Define which bits in the sector status Register section of the Query are
implemented.
bit 0 sector Lock Status Register Lock/Unlock bit (bit 0) active; (1=yes, 0=no)
bit 1 sector Lock Status Register Lock-Down bit (bit 1) active; (1=yes, 0=no)
Bits 2-15 reserved for future use. Undefined bits are "0".
VCC Logic Supply Optimum Program/Erase Voltage (highest performance)
bits 7-4 BCD value in volts
41
42
33
bits 3-0 BCD value in 100mV
VPP Supply Optimum Program/Erase Voltage
bits 7-4 HEX value in volts
C0
bits 3-0 BCD value in 100mV
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MX28F160C3BT/B
ORDER INFORMATION
PART NO.
ACCESS TIME
OPERATING
STANDBY
PACKAGE
(ns)
70
70
90
90
70
70
90
90
70
70
90
90
70
70
90
90
70
70
90
90
70
70
90
90
70
70
90
90
70
70
90
90
Read Current MAX.(mA) Current MAX.(uA)
MX28F160C3BTTC-70
MX28F160C3BBTC-70
MX28F160C3BTTC-90
MX28F160C3BBTC-90
MX28F160C3BTTI-70
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
48 Pin TSOP
48 Pin TSOP
48 Pin TSOP
48 Pin TSOP
48 Pin TSOP
48 Pin TSOP
48 Pin TSOP
48 Pin TSOP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Pin TSOP
48 Pin TSOP
48 Pin TSOP
48 Pin TSOP
48 Pin TSOP
48 Pin TSOP
48 Pin TSOP
48 Pin TSOP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
MX28F160C3BBTI-70
MX28F160C3BTTI-90
MX28F160C3BBTI-90
MX28F160C3BTXAC-70
MX28F160C3BBXAC-70
MX28F160C3BTXAC-90
MX28F160C3BBXAC-90
MX28F160C3BTXAI-70
MX28F160C3BBXAI-70
MX28F160C3BTXAI-90
MX28F160C3BBXAI-90
MX28F160C3BTTC-70G
MX28F160C3BBTC-70G
MX28F160C3BTTC-90G
MX28F160C3BBTC-90G
MX28F160C3BTTI-70G
MX28F160C3BBTI-70G
MX28F160C3BTTI-90G
MX28F160C3BBTI-90G
MX28F160C3BTXAC-70G
MX28F160C3BBXAC-70G
MX28F160C3BTXAC-90G
MX28F160C3BBXAC-90G
MX28F160C3BTXAI-70G
MX28F160C3BBXAI-70G
MX28F160C3BTXAI-90G
MX28F160C3BBXAI-90G
REV. 1.0, MAR. 18, 2004
P/N:PM1085
39
MX28F160C3BT/B
PACKAGE INFORMATION
REV. 1.0, MAR. 18, 2004
P/N:PM1085
40
MX28F160C3BT/B
REV. 1.0, MAR. 18, 2004
P/N:PM1085
41
MX28F160C3BT/B
MACRONIX INTERNATIONALCO., LTD.
HEADQUARTERS:
TEL:+886-3-578-6688
FAX:+886-3-563-2888
EUROPE OFFICE:
TEL:+32-2-456-8020
FAX:+32-2-456-8021
JAPAN OFFICE:
TEL:+81-44-246-9100
FAX:+81-44-246-9105
SINGAPORE OFFICE:
TEL:+65-348-8385
FAX:+65-348-8096
TAIPEI OFFICE:
TEL:+886-2-2509-3300
FAX:+886-2-2509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-453-8088
FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900
FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
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