MX29F001TRC-90_技术文档

INDEX

NEW ADVANCED INFORMATION

MX2 9 F0 0 1 T/ B

1 M-BIT [1 2 8 K x 8 ]CMOS FLASH MEMORY

FEATURES

• Status Reply

• 131072x8 only organization

– Data polling & Toggle bit for detection of program

and erase cycle completion.

• Fast access time: 70/90/120ns

• Low power consumption

• Chip protect/unprotect for 5V only system or 5V/12V

system

– 30mA maximum active current

– 1µA typical standby current

• 100,000 minimum erase/program cycles

• Latch-up protected to 100mA from -1 to VCC+1V

• Command register architecture

– Byte Programming (7µs typical)

– Block Erase (8K-Byte x1, 4K-Byte x 2, 8K Bytex2,

32K-Bytex1, and 64K-Byte x1)

• Boot Code Sector Architecture

– T = Top Boot Sector

– B = Bottom Boot Sector

• Low VCC write inhibit≤ 3.2V

• Package type:

• Auto Erase (chip & block) and Auto Program

– Automatically erase any combination of sectors

with Erase Suspend capability.

– 32-pin PLCC

– 32-pin TSOP

– Automatically programs and verifies data at speci

fied address

– 32-pin PDIP

• Erase Suspend/Erase Resume

• Boot Code Sector Architecture

– T=Top Boot Sector

– B=Bottom Boot Sector

– Suspends an erase operation to read data from,

or program data to, a sector that is not being

erased, then resumes the erase operation.

GENERAL DESCRIPTION

The MX29F001T/B is a 1-mega bit Flash memory

organized as 128K bytes of 8 bits only MXIC's Flash

memories offer the most cost-effective and reliable

read/write non-volatile random access memory. The

MX29F001T/B is packaged in 32-pin PLCC, TSOP,

PDIP. It is designed to be reprogrammed and

erased in-system or in-standard EPROM program-

mers.

compatibility.

MXIC Flash technology reliably stores memory con-

tents even after 100,000 erase and program cycles.

The MXIC cell is designed to optimize the erase and

programming mechanisms. In addition, the combi-

nation of advanced tunnel oxide processing and low

internal electric fields for erase and programming

operations produces reliable cycling.

The

The standard MX29F001T/B offers access time as

fast as 70ns, allowing operation of high-speed

microprocessors without wait states. To eliminate

bus contention, the MX29F001T/B has separate chip

enable (CE) and output enable (OE ) controls.

MX29F001T/B uses a 5.0V ± 10% VCC supply to

perform the High Reliability Erase and auto

Program/Erase algorithms.

The highest degree of latch-up protection is

achieved with MXIC's proprietary non-epi process.

Latch-up protection is proved for stresses up to 100

milliamps on address and data pin from -1V to VCC

+ 1V.

MXIC's Flash memories augment EPROM function-

ality with in-circuit electrical erasure and

programming. The MX29F001T/B uses a command

register to manage this functionality. The command

register allows for 100% TTL level control inputs and

fixed power supply levels during erase and

programming, while maintaining maximum EPROM

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MX2 9 F0 0 1 T/ B

PIN CONFIGURATIONS

32 PDIP

PIN DESCRIPTION:

32PLCC

SYMBOL

A0~A16

Q0~Q7

CE

PIN NAME

VCC

WE

NC

A14

A13

A8

NC

A16

A15

A12

A7

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

1

Address Input

2

4

1

32

30

29

5

9

A7

A6

A5

A4

A3

A2

A1

A0

Q0

A14

A13

A8

3

Data Input/Output

Chip Enable Input

Write Enable Input

Output Enable Input

Power Supply Pin (+5V)

Ground Pin

4

5

A6

6

A9

A5

7

WE

A11

OE

A10

CE

Q7

A4

8

MX29F001T/B

25

A11

OE

A10

CE

Q7

A3

9

OE

A2

10

11

12

13

14

15

16

A1

VCC

A0

Q6

Q0

13

14

21

GND

Q5

Q1

17

20

Q4

Q2

Q3

GND

TSOP (TYPE 1)

BLOCK STRUCTURE

A11

A9

1

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

OE

2

A10

CE

Q7

Q6

Q5

Q4

Q3

GND

Q2

Q1

Q0

A0

A8

3

A 1 6 ~ A 0

1 F F F F H

A13

A14

NC

WE

VCC

NC

A16

A15

A12

A7

4

5

8

K - B Y T E

6

7

1 D F F F H

8

MX29F001T/B

4

9

1 C F F F H

1 B F F F H

10

11

12

13

14

15

16

4

8

K - B Y T E

A6

A1

1 9 F F F H

1 7 F F F H

A5

A2

A4

A3

3 2 K - B Y T E

6 4 K - B Y T E

0 F F F F H

0 0 0 0 0 H

(NORMAL TYPE)

OE

A10

CE

Q7

Q6

Q5

Q4

Q3

GND

Q2

Q1

Q0

A0

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

1

A11

A9

MX29F001T Sector Architecture

2

3

A8

4

A13

A14

NC

WE

VCC

NC

A16

A15

A12

A7

A 1 6 ~ A 0

1 F F F F H

5

6

7

6 4 K - B Y T E

3 2 K - B Y T E

8

MX29F001T/B

9

0 F F F F H

10

11

12

13

14

15

16

0 7 F F F H

0 5 F F F H

8

4

K - B Y T E

A1

A6

A2

A5

0 3 F F F H

0 2 F F F H

A3

A4

4

8

K - B Y T E

(REVERSE TYPE)

0 1 F F F H

0 0 0 0 0 H

MX29F001B Sector Architecture

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MX2 9 F0 0 1 T/ B

BLOCK DIAGRAM

WRITE

STATE

CONTROL

INPUT

PROGRAM/ERASE

HIGH VOLTAGE

CE

OE

WE

MACHINE

(WSM)

LOGIC

STATE

MX29F001T/B

REGISTER

ADDRESS

LATCH

AND

FLASH

ARRAY

SOURCE

HV

A0-A16

COMMAND

DATA

BUFFER

Y-PASS GATE

DECODER

PGM

DATA

HV

SENSE

AMPLIFIER

COMMAND

DATA LATCH

PROGRAM

DATA LATCH

Q0-Q7

I/O BUFFER

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MX2 9 F0 0 1 T/ B

AUTOMATIC PROGRAMMING

AUTOMATIC ERASE ALGORITHM

The MX29F001T/B is byte programmable using the

Automatic Programming algorithm. The Automatic

Programming algorithm does not require the system to

time out or verify the data programmed. The typical

chip programming time of the MX29F001T/B at room

temperature is less than 2 seconds.

MXIC's Automatic Erase algorithm requires the user to

write commands to the command register using stand-

ard microprocessor write timings. The device will

automatically pre-program and verify the entire array.

Then the device automatically times the erase pulse

width, provides the erase verification, and counts the

number of sequences. A status bit toggling between

consecutive read cycles provides feedback to the user

as to the status of the programming operation.

AUTOMATIC CHIP ERASE

Register contents serve as inputs to an internal state-

machine which controls the erase and programming

circuitry. During write cycles, the command register

internally latches addresses and data needed for the

programming and erase operations. During a system

write cycle, addresses are latched on the falling edge,

and data are latched on the rising edge of WE .

The entire chip is bulk erased using 10 ms erase

pulses according to MXIC's Automatic Chip Erase

algorithm. Typical erasure at room temperature is

accomplished in less than two second. The Automatic

Erase algorithm automatically programs the entire

array prior to electrical erase. The timing and

verification of electrical erase are internally controlled

within the device.

MXIC's Flash technology combines years of EPROM

experience to produce the highest levels of quality, relia-

bility, and cost effectiveness. The MX29F001T/B electri-

cally erases all bits simultaneously using Fowler-Nord-

heim tunneling. The bytes are programmed by using the

EPROM programming mechanism of hot electron

injection.

AUTOMATIC BLOCK ERASE

The MX29F001T/B is block(s) erasable using MXIC's

Auto Block Erase algorithm. Block erase modes allow

blocks of the array to be erased in one erase cycle.

The Automatic Block Erase algorithm automatically

programs the specified block(s) prior to electrical

erase. The timing and verification of electrical erase

are internally con trolled by the device.

Duringaprogramcycle, thestate-machinewillcontrolthe

program sequences and command register will not re-

spond to any command set. During a Sector Erase cycle,

thecommandregisterwillonlyrespondtoEraseSuspend

command. After Erase Suspend is completed, the device

stays in read mode. After the state machine has com-

pleted its task, it will allow the command register to

respond to its full command set.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm requires

the user to only write program set-up commands

(include 2 unlock write cycle and A0H) and a program

command (program data and address). The device

automatically times the programming pulse width,

provides the program verification, and counts the

number of sequences. A status bit similar to DATA

polling and a status bit toggling between consecutive

read cycles, provides feedback to the user as to the

status of the programming operation.

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MX2 9 F0 0 1 T/ B

TABLE1. SOFTWARE COMMAND DEFINITIONS

First Bus

Cycle

Second Bus

Cycle

Third Bus

Cycle

Fourth Bus

Cycle

Fifth Bus

Cycle

Sixth Bus

Cycle

Command

Bus

Cycle Addr Data

XXXH F0H

Addr Data

Addr Data Addr Data

Reset/Read

1

Reset/Read

4

555H AAH 2AAH 55H

555H F0H

555H 90H

RA

ADI DDI

SA 00H

x02 01H

PA PD

555H AAH 2AAH

555H AAH 2AAH 55H SA 30H

RD

Read Silicon ID

Chip Protect Verify

4

Porgram

4

6

1

6

555H AAH 2AAH 55H

XXXH B0H

555H A0H

555H 80H

Chip Erase

55H 555H 10H

Sector Erase

Sector Erase Suspend

Sector Erase Resume

Unlock for sector

protect/unprotect

Note:

XXXH 30H

555H AAH 2AAH 55H

555H 80H

555H AAH

2AAH 55H 555H 20H

1. ADI = Address of Device identifier;A1=0, A0 =0 for manufacture code, A1=0, A0 =1 for device code.(Refer to

Table 3)

DDI = Data of Device identifier : C2H for manufacture code, 18H/19H for device code.

X = X can be VIL or VIH

RA=Address of memory location to be read.

RD=Data to be read at location RA.

2.PA = Address of memory location to be programmed.

PD = Data to be programmed at location PA.

SA = Address to the sector to be erased.

3.The system should generate the following address patterns: 555H or 2AAH to Address A0~A10.

Address bit A11~A16=X=Don't care for all address commands except for Program Address (PA) and Sector

Address (SA). Write Sequence may be initiated with A11~A16 in either state.

4.For chip protect verify operation : If read out data is 01H, it means the chip has been protected. If read out data is

00H, it means the chip is still not being protected.

COMMAND DEFINITIONS

Device operations are selected by writing specific ad-

dress and data sequences into the command register.

Writing incorrect address and data values or writing

them in the improper sequence will reset the device to

the read mode. Table 1 defines the valid register com-

mand sequences. Note that the Erase Suspend (B0H)

and Erase Resume (30H) commands are valid only

while the Sector Erase operation is in progress. Either

of the two reset command sequences will reset the

device(when applicable).

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MX2 9 F0 0 1 T/ B

TABLE 2. MX29F001T/B BUS OPERATION

Pins

CE

OE

WE

H

A0

L

A1

L

A6

X

A9

Q0 ~ Q7

C2H

Mode

Read Silicon ID

Manfacturer Code(1)

Read Silicon ID

Device Code(1)

Read

L

V_ID(2)

L

H

L

X

V_ID(2)

18H/19H

L

H

L

X

H

X

H

L

A0

X

A1

X

A6

X

A9

X

D_OUT

HIGH Z

D_IN(3)

X

Standby

Output Disable

Write

H

X

H

A0

X

A1

X

A6

L

A9

Chip Protect with 12V

system(6)

V_ID(2)

L

V_ID(2)

Chip Unprotect with 12V

system(6)

L

X

V_ID(2)

L

H

L

X

H

X

H

X

H

X

L

V_ID(2)

H

X

Code(5)

X

Verify Chip Protect

with 12V system

L

H

L

Chip Protect without 12V

system (6)

Chip Unprotect without 12V

system (6)

L

H

X

H

X

Verify Chip Protect/Unprotect

without 12V system (7)

Reset

H

X

H

Code(5)

HIGH Z

X

NOTES:

1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1.

2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.

3. Refer to Table 1 for valid Data-In during a write operation.

4. X can be VIL or VIH.

5. Code=00H means unprotected.

Code=01H means protected.

6. Refer to chip protect/unprotect algorithm and waveform.

Must issue "unlock for chip protect/unprotect" command before "chip protect/unprotect without 12V system" command.

7. The "verify chip protect/unprotect without 12V sysytem" is only following "Chip protect/unprotect without 12V system"

command.

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MX2 9 F0 0 1 T/ B

READ/RESET COMMAND

SET-UP AUTOMATIC CHIP ERASE COM-

MANDS

The read or reset operation is initiated by writing the

read/reset command sequence into the command

register. Microprocessor read cycles retrieve array

data. The device remains enabled for reads until the

command register contents are altered.

Chip erase is a six-bus cycle operation. There are two

"unlock" write cycles. These are followed by writing

the "set-up" command 80H. Two more "unlock" write

cycles are then followed by the chip erase command

10H.

If program-fail or erase-fail happen, the write of F0H

will reset the device to abort the operation. A valid

command must then be written to place the device in

the desired state.

The Automatic Chip Erase does not require the device

to be entirely pre-programmed prior to executing the

Automatic Chip Erase. Upon executing the Automatic

Chip Erase, the device will automatically program and

verify the entire memory for an all-zero data pattern.

When the device is automatically verified to contain an

all-zero pattern, a self-timed chip erase and

verification begin. The erase and verification

operations are completed when the data on Q7 is "1"

at which time the device returns to the Read mode.

The system does not require to provide any control or

timing during these operations.

SILICON-ID-READ COMMAND

Flash memories are intended for use in applications

where the local CPU alters memory contents. As such,

manufacturer and device codes must be accessible

while the device resides in the target system. PROM

programmers typically access siganature codes by

raising A9 to a high voltage. However, multiplexing

high voltage onto address lines is not generally desired

system design practice.

When using the Automatic Chip Erase algorithm, note

that the erase automatically terminates when

adequate erase margin has been achieved for the

memory array(no erase verify command is required).

The MX29F001T/B contains a Silicon-ID-Read opera-

tion to supplement traditional PROM programming

methodology. The operation is initiated by writing the

read silicon ID command sequence into the command

register. Following the command write, a read cycle

with A1=VIL,A0=VIL retrieves the manufacturer code

of C2H. A read cycle with A1=VIL, A0=VIH returns the

device code of 18H for MX29F001T,19H for

MX29F001B.

If the Erase operation was unsuccessful, the data on

Q5 is "1"(see Table 4), indicating an erase operation

exceed internal timing limit.

The automatic erase begins on the rising edge of the

last WE pulse in the command sequence and

terminates when the data on Q7 is "1" and the data on

Q6 stops toggling for two consecutive read cycles, at

which time the device returns to the Read mode.

TABLE 3. EXPANDED SILICON ID CODE

Pins A0 A1 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Code(Hex)

Manufacture code

Device code

VIL VIL

VIH VIL

1

0

1

0

1

0

1

0

1

0

C2H

18H

for MX29F001T

Device code

VIH VIL

0

1

0

1

0

1

19H

for MX29F001B

Chip Protection Verification

X

VIH

0

1

0

01H (Protected)

00H (Unprotected)

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MX2 9 F0 0 1 T/ B

BLOCK ERASE COMMANDS

ERASE SUSPEND

The Automatic Block Erase does not require the

device to be entirely pre-programmed prior to

executing the Automatic Set-up Block Erase

command and Automatic Block Erase command.

Upon executing the Automatic Block Erase command,

the device will automatically program and verify the

block(s) memory for an all-zero data pattern. The

system does not require to provide any control or

timing during these operations.

This command only has meaning while the state ma-

chine is executing Automatic Block Erase operation,

and therefore will only be responded during Automatic

Block Erase operation. Writing the Erase Suspend

command during the Block Erase time-out immediately

terminates the time-out immediately terminates the

time-out period and suspends the erase operation.

After this command has been executed, the command

register will initiate erase suspend mode. The state

machine will return to read mode automatically after

suspend is ready. At this time, state machine only

allows the command register to respond to the Read

Memory Array, Erase Resume and Program com-

mands.

When the block(s) is automatically verified to contain

an all-zero pattern, a self-timed block erase and

verification begin. The erase and verification

operations are complete when the data on Q7 is "1"

and the data on Q6 stops toggling for two consecutive

read cycles, at which time the device returns to the

Read mode. The system does not require to provide

any control or timing during these operations.

The system can determine the status of the program

operation using the Q7 or Q6 status bits, just as in the

standard program operation. After an erase-suspend

program operation is complete, the system can once

again read array data within non-suspended blocks.

When using the Automatic Block Erase algorithm,

note that the erase automatically terminates when

adequate erase margin has been achieved for the

memory array (no erase verification command is

required). Sector erase is a six-bus cycle operation.

There are two "unlock" write cycles. These are

followed by writing the set-up command 80H. Two

more "unlock" write cycles are then followed by the

sector erase command 30H. The sector address is

latched on the falling edge of WE, while the

command(data) is latched on the rising edge of WE.

Block addresses selected are loaded into internal

register on the sixth falling edge of WE. Each succes-

sive block load cycle started by the falling edge of WE

must begin within 80µs from the rising edge of the

preceding WE. Otherwise, the loading period ends

and internal auto block erase cycle starts. (Monitor Q3

to determine if the sector erase timer window is still

open, see section Q3, Sector Erase Timer.) Any

command other than Block Erase (30H) or Erase

Suspend (B0H) during the time-out period resets the

derice to read mode.

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INDEX

MX2 9 F0 0 1 T/ B

Table 4. Write Operation Status

Status

Q7

Q6

Q5

0

Q3

0

Byte Program in Auto Program Algorithm

Q7 Toggle

Auto Erase Algorithm

0

1

Toggle

1

0

1

Erase Suspend Read

0

In Progress

(Erase Suspended Sector)

Erase Suspend Read

Erase Suspended Mode

Data Data Data Data

(Non-Erase Suspended Sector)

Erase Suspend Program

(Non-Erase Suspended Sector)

Q7 Toggle

(Note1)

0

Byte Program in Auto Program Algorithm

Program/Erase in Auto Erase Algorithm

Q7 Toggle

1

0

1

0

Exceeded

0

Toggle

Time Limits Erase Suspended Mode

Erase Suspend Program

Q7 Toggle

(Non-Erase Suspended Sector)

Note:

1. Performing successive read operations from any address will cause Q6 to toggle.

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MX2 9 F0 0 1 T/ B

ERASE RESUME

read. The toggle bit is valid after the rising edge of the

sixth WE pulse of the six write pulse sequences for chip/

sector erase.

This command will cause the command register to clear

the suspend state and return back to Sector Erase mode

but only if an Erase Suspend command was previously

issued. EraseResumewillnothaveanyeffectinallother

conditions.Another Erase Suspend command can be

written after the chip has resumed erasing.

TheToggleBitfeatureisactiveduringAutomaticProgram/

Erase algorithms or sector erase time-out.(see section

Q3 Sector Erase Timer)

DATA POLLING-Q7

SET-UP AUTOMATIC PROGRAM COMMANDS

TheMX29F001T/BalsofeaturesDataPollingasamethod

to indicate to the host system that the Automatic Program

or Erase algorithms are either in progress or completed.

To initiate Automatic Program mode, A three-cycle

command sequence is required. There are two "un-

lock" write cycles. These are followed by writing the

Automatic Program command A0H.

WhiletheAutomaticProgrammingalgorithmisinoperation,

anattempttoreadthedevicewillproducethecomplement

data of the data last written to Q7. Upon completion of the

Automatic Program Algorithm an attempt to read the

device will produce the true data last written to Q7. The

Data Polling feature is valid after the rising edge of the

fourth WE pulse of the four write pulse sequences for

automatic program.

Once the Automatic Program command is initiated,

the next WE pulse causes a transition to an active

programming operation. Addresses are latched on the

falling edge, and data are internally latched on the

rising edge of the WE pulse. The rising edge of WE

also begins the programming operation. The system

does not require to provide further controls or timings.

The device will automatically provide an adequate

internally generated program pulse and verify margin.

While the Automatic Erase algorithm is in operation, Q7

will read "0" until the erase operation is competed. Upon

completionoftheeraseoperation,thedataonQ7willread

"1". The Data Polling feature is valid after the rising edge

of the sixth WE pulse of six write pulse sequences for

automatic chip/sector erase.

If the program opetation was unsuccessful, the data

on Q5 is "1"(see Table 4), indicating the program

operation exceed internal timing limit. The automatic

programming operation is completed when the data

read on Q6 stops toggling for two consecutive read

cycles and the data on Q7 and Q6 are equivalent to

data written to these two bits, at which time the device

returns to the Read mode(no program verify command

is required).

The Data Polling feature is active during Automatic

Program/Erase algorithm or sector erase time-out.(see

section Q3 Sector Erase Timer)

WRITE OPERATION STATUS

TOGGLE BIT-Q6

The MX29F001T/B features a "Toggle Bit" as a method

to indicate to the host system that the Auto Program/

Erase algorithms are either in progress or complete.

While the Automatic Program or Erase algorithm is in

progress, successive attempts to read data from the

device will result in Q6 toggling between one and zero.

Once the Automatic Program or Erase algorithm is

completed, Q6 will stop toggling and valid data will be

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INDEX

MX2 9 F0 0 1 T/ B

Q5

Q3

Sector Erase Timer

Exceeded Timing Limits

Q5willindicateiftheprogramorerasetimehasexceeded

the specified limits(internal pulse count). Under these

conditions Q5 will produce a "1". This time-out condition

indicates that the program or erase cycle was not

successfully completed. Data Polling and Toggle Bit are

the only operating functions of the device under this

condition.

After the completion of the initial sector erase command

sequence th sector erase time-out will begin. Q3 will

remain low until the time-out is complete. Data Polling

and Toggle Bit are valid after the initial sector erase

command sequence.

If Data Polling or the Toggle Bit indicates the device has

been written with a valid erase command, Q3 may be

used to determine if the sector erase timer window is still

open. If Q3 is high ("1") the internally controlled erase

cyclehasbegun;attemptstowritesubsequentcommands

to the device will be ignored until the erase operation is

completed as indicated by Data Polling or Toggle Bit. If

Q3 is low ("0"), the device will accept additional sector

erase commands. To insure the command has been

accepted, thesystemsoftwareshouldcheckthestatusof

Q3 prior to and following each subsequent sector erase

command. If Q3 were high on the second status check,

the command may not have been accepted.

If this time-out condition occurs during sector erase

operation, it is specifies that a particular sector is bad and

it may not be reused. However, other sectors are still

functional and may be used for the program or erase

operation. Thedevicemustberesettouseothersectors.

Write the Reset command sequence to the device, and

then execute program or erase command sequence.

This allows the system to continue to use the other active

sectors in the device.

If this time-out condition occures during the chip erase

operation, it specifies that the entire chip is bad or

combination of sectors are bad.

DATA PROTECTION

If this time-out condition occurs during the byte

programming operation, it specifies that the entire sector

containing that byte is bad and this sector maynot be

reused, (other sectors are still functional and can be

reused).

TheMX29F001T/B isdesignedtoofferprotectionagainst

accidental erasure or programming caused by spurious

systemlevelsignalsthatmayexistduringpowertransition.

Duringpowerupthedeviceautomaticallyresetsthestate

machine in the Read mode. In addition, with its control

register architecture, alteration of the memory contents

only occurs after successful completion of specific

command sequences. The device also incorporates

several features to prevent inadvertent write cycles

resulting from VCC power-up and power-down transition

or system noise.

The time-out condition may also appear if a user tries to

program a non blank location without erasing. In this

case the device locks out and never completes the

AutomaticAlgorithmoperation. Hence,thesystemnever

reads a valid data on Q7 bit and Q6 never stops toggling.

Once the Device has exceeded timing limits, the Q5 bit

will indicate a "1". Please note that this is not a device

failure condition since the device was incorrectly used.

P/N: PM0515

REV. 1.7, SEP 14, 1998

11

INDEX

MX2 9 F0 0 1 T/ B

WRITE PULSE "GLITCH" PROTECTION

CHIP UNPROTECT WITH 12V SYSTEM

Noisepulsesoflessthan5ns(typical)onCEorWEwillnot

initiate a write cycle.

The MX29F001T/B also features the chip unprotect

mode, so that all sectors are unprotected after chip

unprotect completion to incorporate any changes in the

code.

LOGICAL INHIBIT

To activate this mode, the programming equipment must

force VID on control pin OE and address pin A9. The CE

pins must be set at VIL. Pins A6 must be set to VIH.(see

Table 2) Refer to chip unprotect algorithm and waveform

for the chip unprotect algorithm. The unprotection

mechanism begins on the falling edge of the WE pulse

and is terminated with the rising edge of the same.

Writing is inhibited by holding any one of OE = VIL, CE =

VIHorWE=VIH. ToinitiateawritecycleCEandWEmust

be a logical zero while OE is a logical one.

POWER SUPPLY DECOUPLING

In order to reduce power switching effect, each device

should have a 0.1µF ceramic capacitor connected

between its VCC and GND. (Using a 10uF bulk capacitor

connected for high current condition is available if

necessary.)

It is also possible to determine if the chip is unprotected

in the system by writing the Read Silicon ID command.

Performing a read operation with A1=VIH, it will produce

00H at data outputs (Q0-Q7) for an unprotected sector. It

is noted that all sectors are unprotected after the chip

unprotect algorithm is completed.

CHIP PROTECTION WITH 12V SYSTEM

The MX29F001T/B features hardware sector protection.

Thisfeaturewilldisablebothprogramanderaseoperations

for these sectors protected. To activate this mode, the

programming equipment must force VID on address pin

A9 and control pin OE, (suggest VID = 12V) A6 = VIL and

CE = VIL.(see Table 2) Programming of the protection

circuitry begins on the falling edge of the WE pulse and is

terminated with the rising edge of the same. Please refer

to chip protect algorithm and waveform.

CHIP PROTECTION WITHOUT 12V SYSTEM

TheMX29F001T/Balsofeatureahardwarechipprotection

method in a system without 12V power suppply. The

programmingequipmentdonotneedtosupply12voltsto

protect all sectors. The details are shown in chip protect

algorithm and waveform.

CHIP UNPROTECT WITHOUT 12V SYSTEM

To verify programming of the protection circuitry, the

programming equipment must force VID on address pin

A9 ( with CE and OE at VIL and WE at VIH. When A1=1,

it will produce a logical "1" code at device output Q0 for a

protected sector. Otherwise the device will produce 00H

for the unprotected sector. In this mode, the

address,except for A1, are don't care. Address locations

with A1 = VIL are reserved to read manufacturer and

device codes.(Read Silicon ID)

The MX29F001T/B also feature a hardware chip

unprotection method in a system without 12V power

supply. The programming equipment do not need to

supply 12 volts to unprotect all sectors. The details are

shown in chip unprotect algorithm and waveform.

POWER-UP SEQUENCE

It is also possible to determine if the chip is protected in

the system by writing a Read Silicon ID command.

Performing a read operation with A1=VIH, it will produce

a logical "1" at Q0 for the protected sector.

The MX29F001T/B powers up in the Read only mode. In

addition, the memory contents may only be altered after

successful completion of the predefined command

sequences.

P/N: PM0515

REV. 1.7, SEP 14, 1998

12

INDEX

MX2 9 F0 0 1 T/ B

ABSOLUTE MAXIMUM RATINGS

NOTICE:

Stresses greater than those listed under ABSOLUTE MAXI-

MUM RATINGS may cause permanent damage to the de-

vice. This is a stress rating only and functional operational

sections of this specification is not implied. Exposure to ab-

solute maximum rating conditions for extended period may

affect reliability.

RATING

VALUE

Ambient Operating Temperature 0^oC to 70^oC

Storage Temperature

Applied Input Voltage

Applied Output Voltage

VCC to Ground Potential

A9&OE

-65^oC to 125^oC

-0.5V to 7.0V

-0.5V to 13.5V

NOTICE:

Specifications contained within the following tables are sub-

ject to change.

CAPACITANCE TA = 25^oC, f = 1.0 MHz

SYMBOL

CIN

PARAMETER

MIN.

TYP

MAX.

8

UNIT

pF

CONDITIONS

VIN = 0V

Input Capacitance

Output Capacitance

COUT

12

pF

VOUT = 0V

READ OPERATION

DC CHARACTERISTICS TA = 0^oC TO 70^oC, VCC = 5V ± 10%

SYMBOL

PARAMETER

MIN.

TYP

MAX.

UNIT

CONDITIONS

ILI

Input Leakage Current

1

µA

VIN = GND to VCC

ILO

Output Leakage Current

Standby VCC current

10

µA

mA

µA

mA

V

VOUT = GND to VCC

CE = VIH

ISB1

ISB2

ICC1

ICC2

VIL

1

5

CE = VCC + 0.3V

IOUT = 0mA, f=1MHz

IOUT = 0mA, f=10MHz

Operating VCC current

30

50

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

-0.3(NOTE 1)

2.0

0.8

VIH

VCC + 0.3

0.45

V

VOL

VOH

V

IOL = 2.1mA

2.4

V

IOH = -400µA

NOTES:

1. VIL min. = -1.0V for pulse width ≤ 50 ns.

VIL min. = -2.0V for pulse width ≤ 20 ns.

2. VIH max. = VCC + 1.5V for pulse width ≤ 20 ns

If VIH is over the specified maximum value, read operation

cannot be guaranteed.

P/N: PM0515

REV. 1.7, SEP 14, 1998

13

INDEX

MX2 9 F0 0 1 T/ B

AC CHARACTERISTICS TA = 0^oC to 70^oC, VCC = 5V ± 10%

29F001T/B-70 29F001T/B-90 29F001T/B-12

SYMBOL PARAMETER

MIN.

MAX.

70

MIN. MAX.

MIN. MAX. UNIT CONDITIONS

tACC

tCE

tOE

tDF

Address to Output Delay

90

40

120

50

ns

CE=OE=VIL

OE=VIL

CE to Output Delay

70

OE to Output Delay

40

CE=VIL

OE High to Output Float (Note1)

Address to Output hold

0

20

0

30

0

30

CE=VIL

tOH

CE=OE=VIL

TEST CONDITIONS:

NOTE:

•

Input pulse levels: 0.45V/2.4V

1. tDF is defined as the time at which the output achieves the

open circuit condition and data is no longer driven.

Input rise and fall times: ≤ 10ns

Output load: 1 TTL gate + 100pF (Including scope and jig)

Reference levels for measuring timing: 0.8V, 2.0V

READ TIMING WAVEFORMS

VIH

ADD Valid

A0~16

VIL

tCE

VIH

CE

VIL

VIH

WE

tDF

VIL

tOE

VIH

OE

tACC

VIL

tOH

HIGH Z

VOH

VOL

DATA

Q0~7

DATA Valid

P/N: PM0515

REV. 1.7, SEP 14, 1998

14

INDEX

MX2 9 F0 0 1 T/ B

COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION

DC CHARACTERISTICS TA = 0^oC to 70^oC, VCC = 5V ± 10%

SYMBOL

PARAMETER

MIN.

TYP

MAX.

UNIT CONDITIONS

ICC1 (Read)

ICC2

Operating VCC Current

30

mA

IOUT=0mA, f=1MHz

50

IOUT=0mA, F=10MHz

In Programming

In Erase

ICC3 (Program)

50

ICC4 (Erase)

ICCES

50

VCC Erase Suspend Current

2

CE=VIH, Erase Suspended

NOTES:

1. VIL min. = -0.6V for pulse width ≤ 20ns.

2. If VIH is over the specified maximum value, programming

operation cannot be guranteed.

3. ICCES is specified with the device de-selected. If the device

is read during erase suspend mode, current draw is the sum

of ICCES and ICC1 or ICC2.

4. All current are in RMS unless otherwise noted.

P/N: PM0515

REV. 1.7, SEP 14, 1998

15

INDEX

MX2 9 F0 0 1 T/ B

AC CHARACTERISTICS TA = 0^oC to 70^oC, VCC = 5V ± 10%

29F001T/B-70 29F001T/B-90 29F001T/B-12

SYMBOL PARAMETER

MIN.

50

70

35

20

0

MAX. MIN.

MAX. UNIT CONDITIONS

tOES

tCWC

tCEP

tCEPH1

tCEPH2

tAS

OE setup time

50

ns

s

Command programming cycle

WE programming pulse width

WE programming pluse width High

Address setup time

90

120

45

50

20

0

tAH

Address hold time

45

30

0

45

50

tDS

Data setup time

45

50

tDH

Data hold time

0

tCESC

tDF

CE setup time before command write

Output disable time (Note 1)

Total erase time in auto chip erase

Total erase time in auto block erase

Total programming time in auto verify

Block address load time

0

30

40

tAETC

tAETB

tAVT

tBAL

2(TYP.)

1(TYP.)

s

7

µs

ns

µs

ms

80

0

80

0

80

0

tCH

CE Hold Time

tCS

CE setup to WE going low

Voltge Transition Time

0

tVLHT

tOESP

tWPP

tWPP2

4

OE Setup Time to WE Active

Write pulse width for chip protect

Write pulse width for chip unprotect

4

10

12

10

12

10

12

NOTES:

1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.

P/N: PM0515

REV. 1.7, SEP 14, 1998

16

INDEX

MX2 9 F0 0 1 T/ B

SWITCHING TEST CIRCUITS

DEVICE UNDER

1.8K ohm

+5V

TEST

CL

6.2K ohm

DIODES=IN3064

OR EQUIVALENT

CL=100pF Including jig capacitance

SWITCHING TEST WAVEFORMS

2.4V

2.0V

0.8V

2.0V

0.8V

TEST POINTS

0.45V

OUTPUT

INPUT

AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0".

Input pulse rise and fall times are < 20ns.

COMMAND WRITE TIMING WAVEFORM

VCC

5V

VIH

VIL

ADD

A0~16

ADD Valid

tAH

tAS

VIH

VIL

WE

tOES

tCEPH1

tCEP

tCWC

VIH

VIL

CE

OE

tCS

tCH

tDH

VIH

VIL

tDS

VIH

VIL

DATA

Q0-7

DIN

P/N: PM0515

REV. 1.7, SEP 14, 1998

17

INDEX

MX2 9 F0 0 1 T/ B

AUTOMATIC PROGRAMMING TIMING WAVEFORM

One byte data is programmed. Verification in fast algo-

rithm and additional programming by external control are

not required because these operations are executed

automatically by internal control circuit. Programming

completion can be verified by DATA polling and toggle bit

checking after automatic verify starts. Device outputs

DATAduringprogrammingandDATAafterprogramming

on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling,

timing waveform)

AUTOMATIC PROGRAMMING TIMING WAVEFORM

Vcc 5V

A11~A16

ADD Valid

2AAH

555H

ADD Valid

A0~A10

WE

555H

tAS

tCWC

tCEPH1

tAH

tCESC

tAVT

CE

OE

tCEP

tDS tDH

tDF

DATA

Q0~Q2

Command In

Data In

DATA polling

,Q4(Note 1)

DATA

Command In

Q7

Command #A0H

Command #AAH

Command #55H

tOE

(Q0~Q7)

Notes:

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit

P/N: PM0515

REV. 1.7, SEP 14, 1998

18

INDEX

MX2 9 F0 0 1 T/ B

AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data A0H Address 555H

Write Program Data/Address

NO

Toggle Bit Checking

Q6 not Toggled

YES

NO

Invalid

Verify Byte Ok

Command

YES

NO

Q5 = 1

Reset

Auto Program Completed

YES

Auto Program Exceed

Timing Limit

P/N: PM0515

REV. 1.7, SEP 14, 1998

19

INDEX

MX2 9 F0 0 1 T/ B

TOGGLE BIT ALGORITHM

START

Read Q7~Q0

(Note 1)

NO

Toggle Bit Q6

=Toggle?

YES

NO

Q5=1?

YES

(Note 1,2)

Read Q7~Q0 Twice

Toggle Bit Q6=

Toggle?

YES

Program/Erase Operation Not

Program/Erase Operation Complete

Complete, Write Reset Command

Notes:

1.Read togglr bit Q6 twice to determine whether or not it is toggle. See text.

2.Recheck toggle bit Q6 because it may stop toggling as Q5 changes to "1". See text.

P/N: PM0515

REV. 1.7, SEP 14, 1998

20


型号：	MX29F001TRC-90
厂家：	MACRONIX INTERNATIONAL
描述：	Flash, 128KX8, 90ns, PDSO32, REVERSE, TSOP1-32 光电二极管存储闪存
文件：	总20页 (文件大小：121K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MX29F001TRC-90 [Macronix]

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