MX29F004TRC-90_技术文档

INDEX

ADVANCED INFORMATION

MX29F004T/B

4M-BIT [512KX8] CMOS FLASH MEMORY

FEATURES

• 524,288 x 8 only

• Erase suspend/Erase Resume

- Suspends an erase operation to read data from,

or program data to, another sector that is not being

erased, then resumes the erase.

• Status Reply

- Data polling & Toggle bit for detection of program

and erase cycle completion.

• Chip protect/unprotect for 5V only system or 5V/

12V system.

• 100,000 minimum erase/program cycles

• Latch-up protected to 100mA from -1V to VCC+1V

• Low VCC write inhibit≤3.2V

• Package type:

- 32-pin PLCC, TSOP or PDIP

• Single power supply operation

- 5.0V only operation for read, erase and program

operation

• Fast access time: 70/90/120ns

• Low power consumption

- 30mA maximum active current

- 1uA typical standby current

• Command register architecture

- Byte Programming (7us typical)

- Block Erase

(Block structure:16KB/8KB/8KB/32KB and 64KBx7)

• Auto Erase (chip & block) and Auto Program

- Automatically erase any combination of sectors

with Erase Suspend capability.

- Automatically program and verify data at specified

address

• Compatibility with JEDEC standard

- Pinout and software compatible with single-power

supply Flash

GENERAL DESCRIPTION

The MX29F004T/B is a 4-mega bit Flash memory

organized as 512K bytes of 8 bits. MXIC's Flash

memoriesofferthemostcost-effectiveandreliableread/

write non-volatile random access memory. The

MX29F004T/B is packaged in 32-pin PLCC, TSOP,

PDIP. Itisdesignedtobereprogrammedanderasedin-

system or in-standard EPROM programmers.

during erase and programming, while maintaining

maximum EPROM compatibility.

MXIC Flash technology reliably stores memory

contents even after 100,000 erase and program

cycles. The MXIC cell is designed to optimize the

erase and programming mechanisms. In addition,

the combination of advanced tunnel oxide

processing and low internal electric fields for erase

and programming operations produces reliable

cycling. The MX29F004T/B uses a 5.0V±10% VCC

supply to perform the High Reliability Erase and

auto Program/Erase algorithms.

ThestandardMX29F004T/Boffersaccesstimesasfast

as 70ns, allowing operation of high-speed

microprocessors without wait states. To eliminate bus

contention,theMX29F004T/Bhasseparatechipenable

(CE) and output enable (OE ) controls.

MXIC's Flash memories augment EPROM functionality

with in-circuit electrical erasure and programming. The

MX29F004T/Busesacommandregistertomanagethis

functionality. The command register allows for 100%

TTL level control inputs and fixed power supply levels

The highest degree of latch-up protection is

achieved with MXIC's proprietary non-epi process.

Latch-up protection is proved for stresses up to

100 milliamps on address and data pin from -1V to

VCC + 1V.

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INDEX

MX29F004T/B

PIN CONFIGURATIONS

32 PDIP

32 PLCC

VCC

WE

A17

A14

A13

A8

A18

A16

A15

A12

A7

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

1

2

3

4

1

32

30

29

4

5

9

A7

A6

A5

A4

A3

A2

A1

A0

Q0

A14

A13

A8

5

A6

6

A9

A5

7

A11

OE

A10

CE

A4

8

A9

A3

9

MX29F004T/B

25

A11

OE

A10

CE

Q7

A2

10

11

12

13

14

15

16

A1

Q7

A0

Q6

Q0

Q5

Q1

13

14

21

Q4

Q2

17

20

Q3

GND

32 TSOP (Standard Type) (12mm x 20mm)

32 TSOP (Reverse Type) (12mm x 20mm)

1

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

A11

A9

1

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

OE

A10

CE

Q7

Q6

Q5

Q4

Q3

GND

Q2

Q1

Q0

A0

OE

A11

A9

2

A10

3

A8

3

CE

A8

4

A13

A14

A17

WE

VCC

A18

A16

A15

A12

A7

4

Q7

A13

A14

A17

WE

5

Q6

6

Q5

7

Q4

8

Q3

VCC

A18

A16

A15

A12

A7

MX29F004T/B

9

GND

10

11

12

13

14

15

16

Q2

11

Q1

12

Q0

13

A0

14

A1

15

A2

16

A3

A6

A1

A6

A5

A2

A5

A4

A3

A4

PIN DESCRIPTION

SYMBOL

A0~A18

Q0~Q7

CE

PIN NAME

Address Input

Data Input/Output

Chip Enable Input

Write Enable Input

Output Enable Input

Ground Pin

WE

OE

GND

VCC

+5.0V single power supply

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INDEX

MX29F004T/B

BLOCK STRUCTURE

MX29F004T TOP BOOT SECTOR ADDRESS TABLE

Sector Size

Address Range (in hexadecimal)

(x8) Address Range

00000h-0FFFFh

Sector

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

A18

0

A17

0

A16

0

A15

X

0

A14

X

A13

X

(Kbytes)

64

32

8

0

1

X

10000h-1FFFFh

0

1

0

X

20000h-2FFFFh

0

1

X

30000h-3FFFFh

1

0

X

40000h-4FFFFh

1

0

1

X

50000h-5FFFFh

1

0

X

60000h-6FFFFh

1

X

70000h-77FFFh

1

0

78000h-79FFFh

1

0

1

8

7A000h-7BFFFh

7C000h-7FFFFh

1

X

16

MX29F004B BOTTEM BOOT SECTOR ADDRESS TABLE

Sector Size

Address Range (in hexadecimal)

(x8) Address Range

00000h-03FFFh

Sector

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

A18

0

A17

0

A16

0

A15

0

A14

0

A13

X

(Kbytes)

16

8

0

1

0

04000h-05FFFh

0

1

8

06000h-07FFFh

0

1

X

32

64

08000h-0FFFFh

0

1

X

10000h-1FFFFh

0

1

0

X

20000h-2FFFFh

0

1

X

30000h-3FFFFh

1

0

X

40000h-4FFFFh

1

0

1

X

50000h-5FFFFh

1

0

X

60000h-6FFFFh

1

X

70000h-7FFFFh

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INDEX

MX29F004T/B

BLOCK DIAGRAM

WRITE

STATE

CONTROL

INPUT

PROGRAM/ERASE

HIGH VOLTAGE

CE

OE

WE

MACHINE

(WSM)

LOGIC

STATE

MX29F004T/B

FLASH

ADDRESS

LATCH

REGISTER

ARRAY

A0-A18

AND

SOURCE

HV

BUFFER

Y-PASS GATE

COMMAND

DATA

DECODER

PGM

SENSE

DATA

HV

AMPLIFIER

COMMAND

DATA LATCH

PROGRAM

DATA LATCH

Q0-Q7

I/O BUFFER

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INDEX

MX29F004T/B

AUTOMATIC PROGRAMMING

AUTOMATIC ERASE ALGORITHM

The MX29F004T/B is byte programmable using the

Automatic Programming algorithm. The Automatic

Programming algorithm makes the external system do

not need to have time out sequence or to verify the data

programmed. The typical room temperature chip

programming time of the MX29F004T/B is less than 4

seconds.

MXIC's Automatic Erase algorithm requires the user to

writecommandstothecommandregisterusingstandard

microprocessor write timings. The device will

automatically pre-program and verification the entire

array. Then the device automatically times the erase

pulse width, provides the erase verify, and counts the

number of sequences. A status bit toggling between

consecutive read cycles, provides feedback to the user

as to the status of the programming operation.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 10 ms erase pulses

according to MXIC's Automatic Chip Erase algorithm.

Typicalerasureatroomtemperatureisaccomplishedin

less than 4 second. The Automatic Erase algorithm

automaticallyprogramstheentirearraypriortoelectrical

erase. Thetimingandverificationofelectricaleraseare

controlled internally within the device.

Register contents serve as inputs to an internal state-

machine which controls the erase and programming

circuitry. During write cycles, the command register

internally latches address and data needed for the

programming and erase operations. During a system

write cycle, addresses are latched on the falling edge,

and data are latched on the rising edge of WE .

AUTOMATIC BLOCK ERASE

MXIC's Flash technology combines years of EPROM

experience to produce the highest levels of quality,

reliability, and cost effectiveness. The MX29F004T/B

electrically erases all bits simultaneously using Fowler-

Nordheim tunneling. The bytes are programmed by

using the EPROM programming mechanism of hot

electron injection.

The MX29F004T/B is block(s) erasable using MXIC's

Auto Block Erase algorithm. Block erase modes

allow blocks of the array to be erased in one erase

cycle. The Automatic Block Erase algorithm

automatically programs the specified block(s) prior to

electrical erase. The timing and verification of

electrical erase are controlled internally within the

device.

During a program cycle, the state-machine will control

the program sequences and command register will not

respond to any command set. During a Sector Erase

cycle, the command register will only respond to Erase

Suspendcommand.AfterEraseSuspendiscompleted,

the device stays in read mode. After the state machine

hascompleteditstask,itwillallowthecommandregister

to respond to its full command set.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm requires the

user to only write program set-up commands (include 2

unlock write cycle and A0H) and a program command

(program data and address). The device automatically

timestheprogrammingpulsewidth,providestheprogram

verification, and counts the number of sequences. A

statusbitsimilartoDATApollingandastatusbittoggling

between consecutive read cycles, provides feedback to

the user as to the status of the programming operation.

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INDEX

MX29F004T/B

TABLE1. SOFTWARE COMMAND DEFINITIONS

First Bus

Cycle

Second Bus Third Bus

Cycle Cycle

Fourth Bus Fifth Bus

Cycle Cycle

Sixth Bus

Cycle

Command

Bus

Cycle Addr

XXXH F0H

RA RD

555H AAH 2AAH 55H 555H 90H

Data Addr Data Addr Data Addr Data Addr Data Addr Data

Reset

1

Read

1

Read Silicon ID

Porgram

4

6

1

6

ADI DDI

PA PD

555H AAH 2AAH 55H 555H A0H

555H AAH 2AAH 55H 555H 80H

XXXH B0H

Chip Erase

555H AAH 2AAH 55H

555H 10H

SA 30H

Sector Erase

Sector Erase Suspend

Sector Erase Resume

Unlock for sector

protect/unprotect

XXXH 30H

555H AAH 2AAH 55H 555H 80H

555H AAH 2AAH 55H

555H 20H

Note:

1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacture code,A1=0, A0 =1 for device code.

(Refer to table 3)

DDI = Data of Device identifier : C2H for manufacture code, 45H/46H for device code.

X = X can be VIL or VIH

RA=Address of memory location to be read.

RD=Data to be read at location RA.

2. PA = Address of memory location to be programmed.

PD = Data to be programmed at location PA.

SA = Address to the sector to be erased.

3. The system should generate the following address patterns: 555H or 2AAH to Address A10~A0.

Address bit A11~A18=X=Don't care for all address commands except for Program Address (PA) and Sector

Address (SA). Write Sequence may be initiated with A11~A18 in either state.

COMMAND DEFINITIONS

Deviceoperationsareselectedbywritingspecificaddress

anddatasequencesintothecommandregister. Writing

incorrect address and data values or writing them in the

improper sequence will reset the device to the read

mode. Table 1 defines the valid register command

sequences. Note that the Erase Suspend (B0H) and

EraseResume(30H)commandsarevalidonlywhilethe

Sector Erase operation is in progress. Either of the two

reset command sequences will reset the device(when

applicable).

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INDEX

MX29F004T/B

TABLE 2. MX29F004T/B BUS OPERATION

Mode

Pins

CE

L

OE

L

WE

H

A0

L

A1

L

A6

X

A9

Q0 ~ Q7

C2H

Read Silicon ID

Manfacturer Code(1)

Read Silicon ID

Device Code(1)

Read

V_ID(2)

L

H

L

X

V_ID(2)

45H/46H

L

H

L

H

X

H

L

A0

X

A1

X

A6

X

A9

X

D_OUT

Standby

X

HIGH Z

D_IN(3)

X

Output Disable

Write

H

X

H

A0

X

A1

X

A6

L

A9

V_ID(2)

Chip Protect with 12V

system(6)

V_ID(2)

L

Chip Unprotect with 12V

system(6)

L

X

V_ID(2)

L

X

H

X

H

X

H

X

L

V_ID(2)

H

X

Verify Chip Protect

with 12V system

Chip Protect without 12V

system (6)

L

H

L

Code(5)

X

H

L

Chip Unprotect without 12V

system (6)

L

H

X

H

X

Verify Chip Protect/Unprotect

without 12V system (7)

Reset

H

X

H

Code(5)

HIGH Z

X

NOTES:

1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1.

2. VID is the Silicon-ID-Read high voltage, 11.5V to 13V.

3. Refer to Table 1 for valid Data-In during a write operation.

4. X can be VIL or VIH.

5. Code=00H means unprotected.

Code=01H means protected.

6. Refer to chip protect/unprotect algorithm and waveform.

Must issue "unlock for chip protect/unprotect" command before "chip protect/unprotect without 12V system" command.

7. The "verify chip protect/unprotect without 12V sysytem" is only following "Chip protect/unprotect without 12V system"

command.

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INDEX

MX29F004T/B

READ/RESET COMMAND

SET-UP AUTOMATIC CHIP/BLOCK ERASE

The read or reset operation is initiated by writing the

read/reset command sequence into the command

register. Microprocessor read cycles retrieve array

data. The device remains enabled for reads until the

command register contents are altered.

Chip erase is a six-bus cycle operation. There are two

"unlock" write cycles. These are followed by writing the

"set-up"command80H. Twomore "unlock"writecycles

are then followed by the chip erase command 10H.

The Automatic Chip Erase does not require the device

to be entirely pre-programmed prior to executing the

Automatic Chip Erase. Upon executing the Automatic

Chip Erase, the device automatically will program and

verify the entire memory for an all-zero data pattern.

When the device is automatically verified to contain an

all-zeropattern,aself-timedchiperaseandverifybegin.

Theeraseandverifyoperationsarecompletedwhenthe

data on Q7 is "1" at which time the device returns to the

Read mode. The system is not required to provide any

control or timing during these operations.

If program-fail or erase-fail happen, the write of F0H will

resetthedevicetoaborttheoperation. Avalidcommand

must then be written to place the device in the desired

state.

SILICON-ID-READ COMMAND

Flash memories are intended for use in applications

where the local CPU alters memory contents. As such,

manufacturer and device codes must be accessible

while the device resides in the target system. PROM

programmerstypicallyaccesssignaturecodesbyraising

A9toahighvoltage. However,multiplexinghighvoltage

onto address lines is not generally desired system

design practice.

When using the Automatic Chip Erase algorithm, note

that the erase automatically terminates when adequate

erasemarginhasbeenachievedforthememoryarray(no

erase verification command is required).

TheMX29F004T/BcontainsaSilicon-ID-Readoperation

to supplement traditional PROM programming

methodology. The operation is initiated by writing the

read silicon ID command sequence into the command

register. Followingthecommandwrite,areadcyclewith

A1=VIL,A0=VILretrievesthemanufacturercodeofC2H.

A read cycle with A1=VIL, A0=VIH returns the device

code of 45H/46H for MX29F004T/B.

IftheEraseoperationwasunsuccessful, thedataonQ5

is "1"(see Table 4), indicating an Erase Failure.

Theautomaticerasebeginsontherisingedgeofthelast

WE pulse in the command sequence and terminates

when the data on Q7 is "1" and the data on Q6 stops

toggling for two consecutive read cycles, at which time

the device returns to the Read mode.

TABLE 3. EXPANDED SILICON ID CODE

Pins

A0

A1

Q7

1

Q6

1

Q5

0

Q4

0

Q3

0

Q2

0

Q1

1

Q0

0

Code(Hex)Code

Manufacture code

VIL

C2H

45H

46H

01H

00H

Device code for MX29F004T VIH VIL

Device code for MX29F004B VIH VIL

0

1

0

1

0

1

0

1

0

1

0

Protected Chip

X

VIH

0

1

Unprotected Chip

0

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INDEX

MX29F004T/B

BLOCK ERASE COMMANDS

The Automatic Block Erase does not require the

device to be entirely pre-programmed prior to

executing the Automatic Set-up Block Erase

command and Automatic Block Erase command.

Upon executing the Automatic Block Erase

command, the device automatically will program and

verify the block(s) memory for an all-zero data

pattern. The system is not required to provide any

controls or timing during these operations.

When using the Automatic Block Erase algorithm,

note that the erase automatically terminates when

adequate erase margin has been achieved for the

memory array (no erase verifIcation command is

required). Sector erase is a six-bus cycle operation.

There are two "unlock" write cycles. These are

followed by writing the set-up command 80H. Two

more "unlock" write cycles are then followed by the

sector erase command 30H. The sector address is

latched on the falling edge of WE, while the

command(data) is latched on the rising edge of WE.

Block addresses selected are loaded into internal

register on the sixth falling edge of WE. Each succes-

sive block load cycle started by the falling edge of WE

must begin within 80µs from the rising edge of the

preceding WE. Otherwise, the loading period ends

and internal auto block erase cycle starts. (Monitor

Q3 to determine if the sector erase timer window is

still open, see section Q3, Sector Erase Timer.) Any

command other than Block Erase(30H) or Erase

Suspend(B0H) during the time-out period resets the

device to read mode.

When the block(s) is automatically verified to contain

an all-zero pattern, a self-timed block erase and verify

begin. The erase and verify operations are complete

when the data on Q7 is "1" and the data on Q6 stops

toggling for two consecutive read cycles, at which

time the device returns to the Read mode. The

system is not required to provide any control or timing

during these operations.

Table 4. Write Operation Status

Status

Q7

Q6

Q5

0

Q3

0

Q2

1

Byte Program in Auto Program Algorithm

Auto Erase Algorithm

Q7 Toggle

0

1

Toggle

1

0

1

Toggle

(Note1)

Data

Erase Suspend Read

0

In Progress

(Erase Suspended Sector)

Erase Suspend Read

Erase Suspended Mode

Data Data Data Data

(Non-Erase Suspended Sector)

Erase Suspend Program

Q7 Toggle

(Note2)

0

1

(Note3)

1

(Non-Erase Suspended Sector)

Byte Program in Auto Program Algorithm

Program/Erase in Auto Erase Algorithm

Q7 Toggle

1

0

1

Exceeded

0

Toggle

N/A

Time Limits Erase Suspended Mode

Erase Suspend Program

Q7 Toggle

(Non-Erase Suspended Sector)

Notes:

1.Performing successive read operations from the erase-suspended sector will cause Q2 to toggle.

2.Performing successive read operations from any address will cause Q6 to toggle.

3.Reading the byte address being programmed while in the erase-suspend program mode will indicate logic "1" at the Q2 bit.

However, successive reads from the erase-suspended sector will cause Q2 to toggle.

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INDEX

MX29F004T/B

If the program opetation was unsuccessful, the data on

Q5 is "1"(see Table 4), indicating a program failure. The

automatic programming operation is completed when

the data read on Q6 stops toggling for two consecutive

read cycles and the data on Q7 and Q6 are equivalent

todatawrittentothesetwobits, atwhichtimethedevice

returns to the Read mode(no program verify command

is required).

ERASE SUSPEND

Thiscommandonlyhasmeaningwhilethestatemachine

is executing Automatic Block Erase operation, and

thereforewillonlyberespondedduringAutomaticBlock

Erase operation. However, When the Erase Suspend

commandiswrittenduringthesectorerasetime-out,the

device immediately terminates the time-out period and

suspends the erase operation. After this command has

been executed, the command register will initiate erase

suspend mode. The state machine will return to read

mode automatically after suspend is ready. At this time,

state machine only allows the command register to

respondtotheReadMemoryArray, EraseResumeand

program commands.

DATA POLLING-Q7

The MX29F004T/B also features Data Polling as a

methodtoindicatetothehostsystemthattheAutomatic

Program or Erase algorithms are either in progress or

completed.

While the Automatic Programming algorithm is in

operation, anattempttoreadthedevicewillproducethe

complement data of the data last written to Q7. Upon

completion of the Automatic Program Algorithm an

attempt to read the device will produce the true data last

written to Q7. The Data Polling feature is valid after the

risingedgeofthefourth WEpulseofthefourwritepulse

sequences for automatic program.

The system can determine the status of the program

operation using the Q7 or Q6 status bits, just as in the

standard program operation. After an erase-suspend

program operation is complete, the system can once

again read array data within non-suspended blocks.

ERASE RESUME

This command will cause the command register to clear

thesuspendstateandreturnbacktoSectorErasemode

but only if an Erase Suspend command was previously

issued. Erase Resume will not have any effect in all

otherconditions.AnotherEraseSuspendcommandcan

be written after the chip has resumed erasing.

While the Automatic Erase algorithm is in operation, Q7

willread"0"untiltheeraseoperationiscompeted. Upon

completion of the erase operation, the data on Q7 will

read"1". TheDataPollingfeatureisvalidaftertherising

edge of the sixth WE pulse of six write pulse sequences

for automatic chip/sector erase.

SET-UP AUTOMATIC PROGRAM

COMMANDS

The Data Polling feature is active during Automatic

Program/Erase algorithm or sector erase time-out.(see

section Q3 Sector Erase Timer)

To initiate Automatic Program mode, A three-cycle

commandsequenceisrequired. Therearetwo"unlock"

writecycles. ThesearefollowedbywritingtheAutomatic

Program command A0H.

Once the Automatic Program command is initiated, the

next WE pulse causes a transition to an active

programming operation. Addresses are latched on the

fallingedge,and dataareinternally latchedon therising

edgeoftheWEpulse. TherisingedgeofWEalsobegins

the programming operation. The system is not required

to provide further controls or timings. The device will

automatically provide an adequate internally generated

program pulse and verify margin.

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INDEX

MX29F004T/B

Q2 toggles when the system reads at addresses within

thosesectorsthathavebeenselectedforerasure. (The

system may use either OE or CE to control the read

cycles.) ButQ2cannotdistinguishwhetherthesectoris

actively erasing or is erase-suspended. Q6, by

comparison, indicates whether the device is actively

erasing, or is in Erase Suspend, but cannot distinguish

which sectors are selected for erasure. Thus, both

statusbitsarerequiredforsectorsandmodeinformation.

Refer to Table 4 to compare outputs for Q2 and Q6.

Q6:Toggle BIT I

Toggle Bit I on Q6 indicates whether an Automatic

Program or Erase algorithm is in progress or complete,

or whether the device has entered the Erase Suspend

mode. Toggle Bit I may be read at any address, and is

valid after the rising edge of the final WE pulse in the

command sequence(prior to the program or erase

operation), and during the sector time-out.

During an Automatic Program or Erase algorithm

operation,successivereadcyclestoanyaddresscause

Q6 to toggle. The system may use either OE or CE to

controlthereadcycles.Whentheoperationiscomplete,

Q6 stops toggling.

Reading Toggle Bits Q6/ Q2

Whenever the system initially begins reading toggle bit

status, it must read Q7-Q0 at least twice in a row to

determinewhetheratogglebitistoggling. Typically, the

system would note and store the value of the toggle bit

after the first read. After the second read, the system

would compare the new value of the toggle bit with the

first. If the toggle bit is not toggling, the device has

completedtheprogramoreraseoperation. Thesystem

can read array data on Q7-Q0 on the following read

cycle.

After an erase command sequence is written, if the chip

has been protected, Q6 toggles and returns to reading

array data.

The system can use Q6 and Q2 together to determine

whetherasectorisactivelyerasingoriserasesuspended.

Whenthedeviceisactivelyerasing(thatis,theAutomatic

Erase algorithm is in progress), Q6 toggling. When the

device enters the Erase Suspend mode, Q6 stops

toggling. However, the system must also use Q2 to

determinewhichsectorsareerasingorerase-suspended.

Alternatively, the system can use Q7.

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the system

alsoshould notewhetherthevalueofQ5ishigh(seethe

sectiononQ5). Ifitis,thesystemshouldthendetermine

again whether the toggle bit is toggling, since the toggle

bit may have stopped toggling just as Q5 went high. If

the toggle bit is no longer toggling, the device has

successfuly completed the program or erase operation.

If it is still toggling, the device did not complete the

operation successfully, and the system must write the

reset command to return to reading array data.

If a program address falls within a protected sector, Q6

togglesforapproximately2usaftertheprogramcommand

sequence is written, then returns to reading array data.

Q6 also toggles during the erase-suspend-program

mode, and stops toggling once the Automatic Program

algorithm is complete.

Theremainingscenarioisthatsysteminitiallydetermines

that the toggle bit is toggling and Q5 has not gone high.

The system may continue to monitor the toggle bit and

Q5 through successive read cycles, determining the

status as described in the previous paragraph.

Alternatively, it may choose to perform other system

tasks. Inthiscase,thesystemmuststartatthebeginning

of the algorithm when it returns to determine the status

of the operation.

Table 4 shows the outputs for Toggle Bit I on Q6.

Q2:Toggle Bit II

The "Toggle Bit II" on Q2, when used with Q6, indicates

whether a particular sector is actively eraseing (that is,

the Automatic Erase alorithm is in process), or whether

thatsectoriserase-suspended. ToggleBitIisvalidafter

the rising edge of the final WE pulse in the command

sequence.

P/N:PM0554

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11

INDEX

MX29F004T/B

with its control register architecture, alteration of the

memorycontentsonlyoccursaftersuccessfulcompletion

of specific command sequences. The device also

incorporates several features to prevent inadvertent

write cycles resulting from VCC power-up and power-

down transition or system noise.

Q5

Exceeded Timing Limits

Q5willindicateiftheprogramorerasetimehasexceeded

the specified limits(internal pulse count). Under these

conditionsQ5willproducea"1". Thistime-outcondition

indicates that the program or erase cycle was not

successfullycompleted. DataPollingandToggleBitare

the only operating functions of the device under this

condition.

Q3

Sector Erase Timer

After the completion of the initial sector erase command

sequence, the sector erase time-out will begin. Q3 will

remain low until the time-out is complete. Data Polling

and Toggle Bit are valid after the initial sector erase

command sequence.

If this time-out condition occurs during sector erase

operation, it specifies that a particular sector is bad and

it may not be reused. However, other sectors are still

functional and may be used for the program or erase

operation. The device must be reset to use other

sectors. Write the Reset command sequence to the

device, and then execute program or erase command

sequence. Thisallowsthesystemtocontinuetousethe

other active sectors in the device.

If Data Polling or the Toggle Bit indicates the device has

been written with a valid erase command, Q3 may be

usedtodetermineifthesectorerasetimerwindowisstill

open. If Q3 is high ("1") the internally controlled erase

cycle has begun; attempts to write subsequent

commands to the device will be ignored until the erase

operation is completed as indicated by Data Polling or

Toggle Bit. If Q3 is low ("0"), the device will accept

additional sector erase commands. To insure the

command has been accepted, the system software

shouldcheckthestatusofQ3priortoandfollowingeach

subsequent sector erase command. If Q3 were high on

the second status check, the command may not have

been accepted.

If this time-out condition occurs during the chip erase

operation, it specifies that the entire chip is bad or

combination of sectors are bad.

If this time-out condition occurs during the byte

programmingoperation,itspecifiesthattheentiresector

containing that byte is bad and this sector maynot be

reused, (other sectors are still functional and can be

reused).

The time-out condition may also appear if a user tries to

program a non blank location without erasing. In this

case the device locks out and never completes the

Automatic Algorithm operation. Hence, the system

never reads a valid data on Q7 bit and Q6 never stops

toggling. Once the Device has exceeded timing limits,

the Q5 bit will indicate a "1". Please note that this is not

adevicefailureconditionsincethedevicewasincorrectly

used.

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5ns(typical) on CE or WE will

not initiate a write cycle.

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE = VIL, CE

= VIH or WE = VIH. To initiate a write cycle CE and WE

must be a logical zero while OE is a logical one.

DATA PROTECTION

POWER SUPPLY DECOUPLING

TheMX29F004T/Bisdesignedtoofferprotectionagainst

accidental erasure or programming caused by spurious

system level signals that may exist during power

transition. During power up the device automatically

resets the state machine in the Read mode. In addition,

In order to reduce power switching effect, each device

should have a 0.1uF ceramic capacitor connected

between its VCC and GND.

P/N:PM0554

REV. 0.4, AUG. 01, 1998

12

INDEX

MX29F004T/B

It is also possible to determine if the chip is unprotected

in the system by writing the Read Silicon ID command.

PerformingareadoperationwithA1=VIH,itwillproduce

00H at data outputs(Q0-Q7) for an unprotected sector.

It is noted that all sectors are unprotected after the chip

unprotect algorithm is completed.

CHIP PROTECTION WITH 12V SYSTEM

TheMX29F004T/Bfeatureshardwaresectorprotection.

This feature will disable both program and erase

operations for these sectors protected. To activate this

mode, the programming equipment must force VID on

address pin A9 and control pin OE, (suggest VID = 12V)

A6 = VIL and CE = VIL.(see Table 2) Programming of

the protection circuitry begins on the falling edge of the

WE pulse and is terminated on the rising edge. Please

refer to chip protect algorithm and waveform.

POWER-UP SEQUENCE

TheMX29F004T/BpowersupintheReadonlymode. In

addition, thememorycontentsmayonlybealteredafter

successful completion of the predefined command

sequences.

To verify programming of the protection circuitry, the

programming equipment must force VID on address pin

A9(withCEandOEatVILandWEatVIH). WhenA1=1,

it will produce a logical "1" code at device output Q0 for

a protected sector. Otherwise the device will produce

00H for the unprotected sector. In this mode, the

addresses, except for A1, are don't care. Address

locationswithA1=VILarereservedtoreadmanufacturer

and device codes.(Read Silicon ID)

CHIP PROTECTION WITHOUT 12V SYSTEM

The MX29F004T/B also feature a hardware chip

protectionmethodinasystemwithout12Vpowersuppply.

The programming equipment do not need to supply 12

volts to protect all sectors. The details are shown in chip

protect algorithm and waveform.

It is also possible to determine if chip is protected in the

system by writing a Read Silicon ID command.

PerformingareadoperationwithA1=VIH,itwillproduce

a logical "1" at Q0 for the protected sector.

CHIP UNPROTECT WITHOUT 12V SYSTEM

The MX29F004T/B also feature a hardware chip

unprotection method in a system without 12V power

supply. The programming equipment do not need to

supply 12 volts to unprotect all sectors. The details are

shown in chip unprotect algorithm and waveform.

CHIP UNPROTECT WITH 12V SYSTEM

The MX29F004T/B also features the chip unprotect

mode, so that all sectors are unprotected after chip

unprotect is completed to incorporate any changes in

the code.

To activate this mode, the programming equipment

must force VID on control pin OE and address pin A9.

The CE pins must be set at VIL. Pins A6 must be set to

VIH.(seeTable2) Refertochipunprotect algorithmand

waveform for the chip unprotect algorithm. The

unprotection mechanism begins on the falling edge of

the WE pulse and is terminated on the rising edge.

P/N:PM0554

REV. 0.4, AUG. 01, 1998

13

INDEX

MX29F004T/B

CAPACITANCE (TA = 25^oC, f = 1.0 MHz)

SYMBOL

CIN

PARAMETER

MIN.

TYP

MAX.

8

UNIT

pF

CONDITIONS

VIN = 0V

Input Capacitance

Output Capacitance

COUT

12

pF

VOUT = 0V

READ OPERATION

DC CHARACTERISTICS (TA = 0^°C TO 70^°C, VCC = 5V±10%)

SYMBOL PARAMETER

MIN.

TYP

MAX.

1

UNIT

µA

CONDITIONS

ILI

Input Leakage Current

VIN = GND to VCC

VOUT = GND to VCC

CE = VIH

ILO

Output Leakage Current

Standby VCC current

10

1

µA

ISB1

ISB2

ICC1

ICC2

VIL

mA

µA

1

5

CE = VCC + 0.3V

IOUT = 0mA, f=1MH

IOUT = 0mA, f=10MHz

Operating VCC current

30

50

V

mA

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

-0.3(NOTE 1) 0.8

2.0

VIH

VCC + 0.3

0.45

V

VOL

VOH

IOL = 2.1mA

IOH = -400uA

2.4

NOTES:

1. VIL min. = -1.0V for pulse width ≤ 50 ns.

VIL min. = -2.0V for pulse width ≤ 20 ns.

2. VIH max. = VCC + 1.5V for pulse width ≤ 20 ns

IfVIHisoverthespecifiedmaximumvalue, readoperation

cannot be guaranteed.

AC CHARACTERISTICS (TA = 0^oC to 70^oC, VCC = 5V±10%)

29F004T/B-70 29F004T/B-90 29F004T/B-12

SYMBOL PARAMETER

MIN.

MAX.

70

MIN. MAX.

UNIT CONDITIONS

tACC

tCE

tOE

tDF

Address to Output Delay

90

40

120

50

ns

CE=OE=VIL

OE=VIL

CE to Output Delay

70

OE to Output Delay

40

CE=VIL

OE High to Output Float (Note1)

Address to Output hold

0

20

0

30

0

30

CE=VIL

tOH

CE=OE=VIL

TEST CONDITIONS:

NOTE:

•

Input pulse levels: 0.45V/2.4V

1. tDF is defined as the time at which the output achieves the

open circuit condition and data is no longer driven.

Input rise and fall times: ≤ 10ns

Output load: 1 TTL gate + 100pF (Including scope and jig)

Reference levels for measuring timing: 0.8V, 2.0V

P/N:PM0554

REV. 0.4, AUG. 01, 1998

14

INDEX

MX29F004T/B

NOTICE:

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed under ABSOLUTE

MAXIMUM RATINGS may cause permanent damage to

the device. This is a stress rating only and functional

operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for

extended period may affect reliability.

RATING

VALUE

Ambient Operating Temperature 0^oC to 70^oC

Storage Temperature

Applied Input Voltage

Applied Output Voltage

VCC to Ground Potential

A9 & OE

-65^oC to 125^oC

-0.5V to 7.0V

-0.5V to 13.5V

NOTICE:

Specifications contained within the following tables are

subject to change.

READ TIMING WAVEFORMS

VIH

ADD Valid

Addresses

VIL

tCE

VIH

CE

VIL

VIH

WE

tDF

VIL

tOE

VIH

OE

tACC

VIL

tOH

HIGH Z

VOH

VOL

Outputs

DATA Valid

COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION

DC CHARACTERISTICS (TA = 0^oC to 70^oC, VCC = 5V±10%)

SYMBOL

ICC1 (Read)

ICC2

PARAMETER

MIN.

TYP

MAX.

30

UNIT

mA

CONDITIONS

Operating VCC Current

IOUT=0mA, f=1MHz

IOUT=0mA, F=10MHz

In Programming

50

ICC3 (Program)

ICC4 (Erase)

ICCES

50

In Erase

VCC Erase Suspend Current

2

CE=VIH, Erase Suspended

NOTES:

1. VIL min. = -0.6V for pulse width ≤ 20ns.

3. ICCES is specified with the device de-selected. If the

device is read during erase suspend mode, current draw is

the sum of ICCES and ICC1 or ICC2.

2. If VIH is over the specified maximum value, programming

operation cannot be guranteed.

4. All current are in RMS unless otherwise noted.

P/N:PM0554

REV. 0.4, AUG. 01, 1998

15

INDEX

MX29F004T/B

AC CHARACTERISTICS TA = 0^oC to 70^oC, VCC = 5V ± 10%

29F004T/B-70 29F004T/B-90 29F004T/B-12

SYMBOL PARAMETER

MIN. MAX.

MIN. MAX. UNIT CONDITIONS

tOES

tCWC

tCEP

tCEPH1

tCEPH2

tAS

OE setup time

50

120

50

20

0

ns

s

Command programming cycle

WE programming pulse width

WE programming pluse width High

Address setup time

70

90

35

45

20

0

tAH

Address hold time

45

50

0

tDS

Data setup time

30

45

tDH

Data hold time

0

tCES

tCESC

tDF

CE setup time

0

CE setup time before command write

Output disable time (Note 1)

Verify access time

0

30

40

tVA

70

4(TYP.)

1(TYP.)

7

90

4(TYP.)

1(TYP.)

7

120

tAETC

tAETB

tAVT

tET

Total erase time in auto chip erase

Total erase time in auto block erase

Total programming time in auto verify

Standby time in erase

4(TYP.)

1(TYP.)

s

7

µs

ms

µs

ns

µs

ms

10

0.3

80

0

tBALC

tBAL

Block address load cycle

Block address load time

CE Hold Time

0.3

80

0

30

0.3

80

0

30

tCH

tCS

CE setup to WE going low

Voltge Transition Time

0

tVLHT

tOESP

tWPP1

tWPP2

4

OE Setup Time to WE Active

Write pulse width for sector protect

4

10

12

10

12

Write pulse width for sector unprotect 12

NOTES:

1. tDF defined as the time at which the output achieves the

open circuit condition and data is no longer driven.

P/N:PM0554

REV. 0.4, AUG. 01, 1998

16

INDEX

MX29F004T/B

SWITCHING TEST CIRCUITS

DEVICE UNDER

TEST

1.8K ohm

+5V

CL

6.2K ohm

DIODES=IN3064

OR EQUIVALENT

CL=100pF Including jig capacitance

SWITCHING TEST WAVEFORMS

2.4V

2.0V

0.8V

2.0V

TEST POINTS

0.8V

0.45V

INPUT

OUTPUT

AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0".

Input pulse rise and fall times are <20ns.

COMMAND WRITE TIMING WAVEFORM

VCC

5V

VIH

VIL

Addresses

ADD Valid

tAH

tAS

VIH

VIL

WE

CE

tOES

tCEPH1

tCEP

tCWC

VIH

VIL

tCS

tCH

tDH

VIH

VIL

OE

tDS

VIH

VIL

Data

DIN

P/N:PM0554

REV. 0.4, AUG. 01, 1998

17

INDEX

MX29F004T/B

AUTOMATIC PROGRAMMING TIMING WAVEFORM

bit checking after automatic verification starts. Device

outputs DATA during programming and DATA after

programming on Q7.(Q6 is for toggle bit; see toggle bit,

DATA polling, timing waveform)

One byte data is programmed. Verify in fast algorithm

and additional programming by external control are not

required because these operations are executed

automatically by internal control circuit. Programming

completion can be verified by DATA polling and toggle

AUTOMATIC PROGRAMMING TIMING WAVEFORM

Vcc 5V

A11~A18

ADD Valid

2AAH

555H

ADD Valid

tAVT

A0~A10

WE

555H

tAS

tCWC

tCEPH1

tAH

tCESC

CE

OE

tCEP

tDS tDH

tDF

Q0,Q1,

DATA

Command In

Data In

DATA polling

Q4(Note 1)

DATA

Command In

Q7

Command #A0H

Command #55H

Command #AAH

(Q0~Q7)

tOE

Notes:

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

P/N:PM0554

REV. 0.4, AUG. 01, 1998

18

INDEX

MX29F004T/B

AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data A0H Address 555H

Write Program Data/Address

NO

Toggle Bit Checking

Q6 not Toggled

YES

NO

Invalid

Verify Byte Ok

Command

YES

NO

Q5 = 1

Auto Program Completed

YES

Reset

Auto Program Exceed

Timing Limit

P/N:PM0554

REV. 0.4, AUG. 01, 1998

19

INDEX

MX29F004T/B

AUTOMATIC CHIP ERASE TIMING WAVEFORM

All data in chip are erased. External erase verification is

not required because data is erased automatically by

internal control circuit. Erasure completion can be

verified by DATA polling and toggle bit checking after

automaticerasestarts. Deviceoutputs0duringerasure

and1aftererasureonQ7.(Q6isfortogglebit;seetoggle

bit, DATA polling, timing waveform)

AUTOMATIC CHIP ERASE TIMING WAVEFORM

Vcc 5V

A11~A18

2AAH

555H

2AAH

555H

A0~A10

WE

555H

tAS

tCWC

tAH

tCEPH1

tCESC

tAETC

CE

OE

tCEP

tDF

tDS tDH

Q0,Q1,

Command In

Q4(Note 1)

DATA polling

tDPA

Command In

Q7

Command #80H

Command #AAH

Command #55H

Command #10H

Command #AAH

Command #55H

(Q0~Q7)

Notes:

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

P/N:PM0554

REV. 0.4, AUG. 01, 1998

20

INDEX

MX29F004T/B

AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 80H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 10H Address 555H

NO

Toggle Bit Checking

Q6 not Toggled

YES

NO

Invalid

DATA Polling

Q7 = 1

Command

YES

NO

Q5 = 1

Auto Chip Erase Completed

Reset

Auto Chip Erase Exceed

Timing Limit

P/N:PM0554

REV. 0.4, AUG. 01, 1998

21

INDEX

MX29F004T/B

AUTOMATIC BLOCK ERASE TIMING WAVEFORM

checking after automatic erase starts. Device outputs 0

during erasure and 1 after erasure on Q7.(Q6 is for

togglebit;seetogglebit,DATApolling,timingwaveform)

BlockdataindicatedbyA16toA18areerased. External

erase verify is not required because data are erased

automatically by internal control circuit. Erasure com-

pletion can be verified by DATA polling and toggle bit

AUTOMATIC BLOCK ERASE TIMING WAVEFORM

Vcc 5V

Block

A16~A18

Address 0

Address 1

Address N

2AAH

555H

2AAH

A0~A10

WE

555H

tAS

tCWC

tAH

tBAL

tCESC

tCEPH1

tCEPH2

tAETB

CE

OE

tCEP

tDF

tDS tDH

Command In

Q0,Q1,

Command In

Q4(Note 1)

DATA polling

tDPA

Command In

Q7

Command #30H

Command #80H

Command #AAH

Command #55H

Command #30H

Command #AAH

(Q0~Q7)

Command #55H

Notes:

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

P/N:PM0554

REV. 0.4, AUG. 01, 1998

22

INDEX

MX29F004T/B

AUTOMATIC BLOCK ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 80H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 30H Sector Address

NO

Toggle Bit Checking

Invalid Command

Q6 Toggled ?

YES

Load Other Sector Addrss If Necessary

(Load Other Sector Address)

NO

Last Block

to Erase

YES

NO

Time-out Bit

Checking Q3=1 ?

YES

Toggle Bit Checking

Q6 not Toggled

YES

Q5 = 1

DATA Polling

Q7 = 1

Reset

Auto Block Erase Completed

Auto Block Erase Exceed

Timing Limit

P/N:PM0554

REV. 0.4, AUG. 01, 1998

23

INDEX

MX29F004T/B

ERASE SUSPEND/ERASE RESUME FLOWCHART

START

Write Data B0H

NO

Toggle Bit checking Q6

not toggled

YES

Read Array or

Program

Reading or

NO

Programming End

YES

Write Data 30H

Continue Erase

Another

NO

Erase Suspend ?

YES

P/N:PM0554

REV. 0.4, AUG. 01, 1998

24

INDEX

MX29F004T/B

TIMING WAVEFORM FOR CHIP PROTECTION FOR SYSTEM WITH 12V

A1

A6

12V

5V

A9

tVLHT

Verify

12V

5V

OE

tVLHT

tWPP 1

WE

CE

tOESP

Data

01H

tOE

TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITH 12V

A1

12V

5V

A9

tVLHT

A6

Verify

12V

5V

OE

tVLHT

tWPP 2

WE

tOESP

CE

Data

00H

tOE

P/N:PM0554

REV. 0.4, AUG. 01, 1998

25

INDEX

MX29F004T/B

SECTOR PROTECTION ALGORITHM FOR SYSTEM WITH 12V

START

PLSCNT=1

OE=VID,A9=VID,CE=VIL

A6=VIL

Activate WE Pulse

Time Out 10us

Set WE=VIH, CE=OE=VIL

A9 should remain VID

Read Data with A1=1

No

Data=01H?

Yes

PLSCENT=32?

Yes

Remove VID from A9

Write Reset Command

Device Failed

Chip Protection

Complete

P/N:PM0554

REV. 0.4, AUG. 01, 1998

26

INDEX

MX29F004T/B

CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITH 12V

START

PLSCNT=1

Set OE=A9=VID

CE=VIL, A6=1

Activate WE Pulse

Time Out 12ms

Increment

PLSCENT

Set OE=CE=VIL

A9=VID, A1=1

Read Data from Device

No

Data=00H?

Yes

PLSCENT=1000?

Yes

Remove VID from A9

Write reset Command

Device Failed

Chip Unprotect

Complete

P/N:PM0554

REV. 0.4, AUG. 01, 1998

27

INDEX

MX29F004T/B

TIMING WAVEFORM FOR CHIP PROTECTION FOR SYSTEM WITHOUT 12V

A1

A6

5V

A9

Q6 Toggle bit polling

Verify

OE

tCEP

WE

CE

*See following Note

Don't

Care

Data

01H

tOE

Note: Must issue "unlock for chip protect/unprotect" command

before sector protection for a system without 12V provided.

TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITHOUT 12V

A1

5V

A9

A6

Q6 Toggle bit polling

Verify

5V

OE

tCEP

WE

*See following Note

CE

Don't

Care

Data

00H

tOE

Note: Must issue "unlock for chip protect/unprotect" command

before chip unprotection for a system without 12V provided.

P/N:PM0554

REV. 0.4, AUG. 01, 1998

28

INDEX

MX29F004T/B

SECTOR PROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V

START

PLSCNT=1

Write "unlock for chip protect/unprotect"

Command(Table1)

OE=VIH, A9=VIH

CE=VIL, A6=VIL

Activate WE Pulse to start

Data don't care

No

Toggle bit checking

Q6 not Toggled

Yes

Increment PLSCNT

Set CE=OE=VIL

A9=VIH

Read Data from chip,

A1=1

No

Data=01H?

PLSCENT=32?

Yes

Write Reset Command

Device Failed

Chip Protection

Complete

P/N:PM0554

REV. 0.4, AUG. 01, 1998

29

INDEX

MX29F004T/B

CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V

START

PLSCNT=1

Write "unlock for chip protect/unprotect"

Command (Table 1)

Set OE=A9=VIH

CE=VIL, A6=1

Active WE Pulse to start

Data don't care

Increment

PLSCENT

No

Toggle bit checking

Q6 not Toggled

Yes

Set OE==CE=VIL,

A9=VIH, A1=1

No

Read Data from Device

No

PLSCENT=1000?

Data=00H?

Yes

Device Failed

Write Reset Command

Chip Unprotect

Complete

P/N:PM0554

REV. 0.4, AUG. 01, 1998

30

INDEX

MX29F004T/B

ID CODE READ TIMING WAVEFORM

VCC

5V

VID

ADD

A9

VIH

VIL

VIH

VIL

ADD

A0

tACC

VIH

VIL

A1

ADD

A2-A8

VIH

A10-A17 VIL

CE

VIH

VIL

VIH

VIL

tCE

WE

OE

tOE

VIH

VIL

tDF

tOH

VIH

VIL

DATA

Q0-Q7

DATA OUT

C2H

DATA OUT

58H/59H

P/N:PM0554

REV. 0.4, AUG. 01, 1998

31

INDEX

MX29F004T/B

ORDERING INFORMATION

PLASTIC PACKAGE

(Top Boot Sector as an example, For Bottom Boot Sector ones, MX29F004TXX will be changed to MX29F004Bxx)

PART NO.

ACCESS

OPERATING CURRENT

STANDBY CURRENT PACKAGE

TIME (ns) MAX.(mA)

MAX.(µA)

MX29F004TQC-70

MX29F004TQC-90

MX29F004TQC-12

MX29F004TTC-70

70

50

100

32 Pin PLCC

32 Pin TSOP

(Normal Type)

32 Pin TSOP

(Normal Type)

32 Pin TSOP

(Normal Type)

32 Pin TSOP

(Reverse Type)

32 Pin TSOP

(Reverse Type)

32 Pin TSOP

(Reverse Type)

32 Pin PDIP

90

120

70

MX29F004TTC-90

MX29F004TTC-12

MX29F004TRC-70

MX29F004TRC-90

MX29F004TRC-12

90

50

100

120

70

90

120

MX29F004TPC-70

MX29F004TPC-90

MX29F004TPC-120

70

50

100

90

32 Pin PDIP

120

32 Pin PDIP

P/N:PM0554

REV. 0.4, AUG. 01, 1998

32

INDEX

MX29F004T/B

MACRONIX INTERNATIONAL CO., LTD.

HEADQUARTERS:

TEL:+886-3-578-8888

FAX:+886-3-578-8887

EUROPE OFFICE:

TEL:+32-2-456-8020

FAX:+32-2-456-8021

JAPAN OFFICE:

TEL:+81-44-246-9100

FAX:+81-44-246-9105

SINGAPORE OFFICE:

TEL:+65-747-2309

FAX:+65-748-4090

TAIPEI OFFICE:

TEL:+886-3-509-3300

FAX:+886-3-509-2200

MACRONIX AMERICA, INC.

TEL:+1-408-453-8088

FAX:+1-408-453-8488

CHICAGO OFFICE:

TEL:+1-847-963-1900

FAX:+1-847-963-1909

http : //www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice.

33


型号：	MX29F004TRC-90
厂家：	MACRONIX INTERNATIONAL
描述：	Flash, 512KX8, 90ns, PDSO32, 12 X 20 MM, PLASTIC, REVERSE, TSOP-32 光电二极管
文件：	总33页 (文件大小：226K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MX29F004TRC-90 [Macronix]

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MX29F004TTC-12

MX29F004TTC-12G

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MX29F004TTC-55G

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MX29F004TTC-90

MX29F004TTC-90G

MX29F004TTI-12

MX29F004TTI-55

MX29F004TTI-70

MX29F004TTI-90