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MX29LV002CBQI-70G [Macronix]

2M-BIT [256K x 8] CMOS SINGLE VOLTAGE 3V ONLY FLASH MEMORY; 2M- BIT [ 256K ×8 ] CMOS单电压3V仅限于Flash存储器
MX29LV002CBQI-70G
型号： MX29LV002CBQI-70G
厂家： MACRONIX INTERNATIONAL    MACRONIX INTERNATIONAL
描述：

2M-BIT [256K x 8] CMOS SINGLE VOLTAGE 3V ONLY FLASH MEMORY
2M- BIT [ 256K ×8 ] CMOS单电压3V仅限于Flash存储器

闪存 存储 内存集成电路
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中文：  中文翻译
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MX29LV002C/002NC T/B  
2M-BIT [256K x 8] CMOS SINGLE VOLTAGE  
3V ONLY FLASH MEMORY  
FEATURES  
• Extended single - supply voltage range 2.7V to 3.6V  
• 262,411 x 8  
• Singlepowersupplyoperation  
- 3.0V only operation for read, erase and program  
operation  
• Ready/Busy# pin (RY/BY#)  
-Providesahardwaremethodofdetectingprogramor  
eraseoperationcompletion.  
• Sectorprotection  
- Hardware method to disable any combination of  
sectors from program or erase operations  
-Temporarysectorunprotectallowscodechangesin  
previously locked sectors  
• Fast access time: 70/90ns  
• Lowpowerconsumption  
- 20mA maximum active current  
- 0.2uA typical standby current  
• CFI (Common Flash Interface) compliant  
- Flash device parameters stored on the device and  
provide the host system to access  
• 100,000minimumerase/programcycles  
• Latch-up protected to 100mA from -1V to VCC+1V  
• Boot Sector Architecture  
• Commandregisterarchitecture  
- Byte Programming (9us typical)  
- Sector Erase (Sector structure 16K-Byte x 1,  
8K-Byte x 2, 32K-Byte x1, and 64K-Byte x3)  
• Auto Erase (chip & sector) and Auto Program  
-Automaticallyeraseanycombinationofsectorswith  
Erase Suspend capability.  
- T = Top Boot Sector  
- B = Bottom Boot Sector  
- Automatically program and verify data at specified  
address  
• Erasesuspend/EraseResume  
- Suspends sector erase operation to read data from,  
orprogramdatato,any sectorthatisnotbeingerased,  
then resumes the erase.  
• HardwareRESET#pin(onlyfor29LV002C)  
- Resets internal state machine to read mode  
• Package type:  
- 32-pin TSOP (type 1)  
-32-pinPLCC  
• 20 years data retention  
• Status Reply  
- Data# Polling & Toggle bit for detection of program  
anderaseoperationcompletion.  
GENERAL DESCRIPTION  
The MX29LV002C T/B is a 2-mega bit Flash memory  
organized as 256K bytes of 8 bits. MXIC's Flash memo-  
ries offer the most cost-effective and reliable read/write  
non-volatile random access memory. The MX29LV002C  
T/B is packaged in 32-pin TSOP and 32-pin PLCC. It is  
designed to be reprogrammed and erased in system or  
in standard EPROM programmers.  
TTL level control inputs and fixed power supply levels  
during erase and programming, while maintaining maxi-  
mum EPROM compatibility.  
MXIC Flash technology reliably stores memory contents  
even after 100,000 erase and program cycles. The MXIC  
cell is designed to optimize the erase and programming  
mechanisms. In addition, the combination of advanced  
tunnel oxide processing and low internal electric fields  
for erase and program operations produces reliable cy-  
cling. The MX29LV002C T/B uses a 2.7V~3.6V VCC  
supply to perform the High Reliability Erase and auto  
Program/Erase algorithms.  
The standard MX29LV002C T/B offers access time as  
fast as 70ns, allowing operation of high-speed micropro-  
cessors without wait states. To eliminate bus conten-  
tion, the MX29LV002C T/B has separate chip enable  
(CE#) and output enable (OE#) controls.  
MXIC's Flash memories augment EPROM functionality  
with in-circuit electrical erasure and programming. The  
MX29LV002CT/B uses a command register to manage  
this functionality. The command register allows for 100%  
The highest degree of latch-up protection is achieved  
with MXIC's proprietary non-epi process. Latch-up pro-  
tection is proved for stresses up to 100 milliamps on  
address and data pin from -1V to VCC + 1V.  
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MX29LV002C/002NC T/B  
PIN CONFIGURATIONS  
32 TSOP (TYPE 1)  
NC on MX29LV002NC  
32 PLCC  
A11  
A9  
1
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
OE#  
A10  
CE#  
Q7  
2
A8  
3
4
1
32  
30  
29  
A13  
A14  
A17  
WE#  
VCC  
RESET#  
A16  
A15  
A12  
A7  
4
5
9
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
Q0  
A14  
A13  
A8  
5
Q6  
6
Q5  
7
Q4  
MX29LV002C/002NC T/B  
8
Q3  
A9  
MX29LV002C/  
002NC T/B  
9
GND  
Q2  
25  
A11  
OE#  
A10  
CE#  
Q7  
10  
11  
12  
13  
14  
15  
16  
Q1  
Q0  
A0  
A6  
A1  
13  
14  
21  
A5  
A2  
17  
20  
A4  
A3  
NC on MX29LV002NC  
PIN DESCRIPTION  
SYMBOL PIN NAME  
A0~A17  
Q0~Q7  
CE#  
Address Input  
DataInput/Output  
Chip Enable Input  
Write Enable Input  
WE#  
RESET#  
HardwareResetPin/SectorProtect  
Unlock  
OE#  
VCC  
GND  
Output Enable Input  
Power Supply Pin (+3V)  
GroundPin  
SECTOR STRUCTURE  
A 1 7 ~ A 0  
3 F F F F H  
A 1 7 ~ A 0  
3 F F F F H  
1 6 K - B Y T E  
( B O O T S E C T O R )  
6 4 K - B Y T E  
6 4 K - B Y T E  
2 F F F F H  
1 F F F F H  
0 F F F F H  
0 7 F F F H  
0 5 F F F H  
0 3 F F F H  
0 0 0 0 0 H  
3 B F F F H  
3 9 F F F H  
8
8
K - B Y T E  
K - B Y T E  
6 4 K - B Y T E  
3 2 K - B Y T E  
3 7 F F F H  
2 F F F F H  
1 F F F F H  
3 2 K - B Y T E  
6 4 K - B Y T E  
6 4 K - B Y T E  
6 4 K - B Y T E  
8
8
K - B Y T E  
K - B Y T E  
1 6 K - B Y T E  
( B O O T S E C T O R )  
0 F F F F H  
0 0 0 0 0 H  
MX29LV002CT Sector Architecture  
MX29LV002CB Sector Architecture  
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MX29LV002C/002NC T/B  
BLOCK DIAGRAM  
WRITE  
WE#  
OE#  
CONTROL  
PROGRAM/ERASE  
HIGH VOLTAGE  
STATE  
MACHINE  
(WSM)  
INPUT  
LOGIC  
WP#  
RESET#  
STATE  
REGISTER  
FLASH  
ARRAY  
ADDRESS  
LATCH  
ARRAY  
A0~A17  
AND  
SOURCE  
HV  
BUFFER  
Y-PASS GATE  
COMMAND  
DATA  
DECODER  
PGM  
DATA  
HV  
SENSE  
AMPLIFIER  
COMMAND  
DATA LATCH  
PROGRAM  
DATA LATCH  
I/O BUFFER  
Q0-Q7  
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MX29LV002C/002NC T/B  
AUTOMATIC ERASE ALGORITHM  
AUTOMATIC PROGRAMMING  
MXIC's Automatic Erase algorithm requires the user to  
write commands to the command register using stan-  
dard microprocessor write timings. The device will auto-  
matically pre-program and verify the entire array. Then  
the device automatically times the erase pulse width,  
provides the erase verification, and counts the number  
of sequences. A status bit toggling between consecu-  
tive read cycles provides feedback to the user as to the  
status of the erasing operation.  
The MX29LV002C T/B is byte programmable using the  
Automatic Programming algorithm. The Automatic Pro-  
gramming algorithm makes the external system do not  
need to have time out sequence nor to verify the data  
programmed. The typical chip programming time at room  
temperature of the MX29LV002C T/B is less than 10  
seconds.  
AUTOMATIC CHIP ERASE  
Register contents serve as inputs to an internal state-  
machine which controls the erase and programming cir-  
cuitry. During write cycles, the command register inter-  
nally latches address and data needed for the program-  
ming and erase operations. During a system write cycle,  
addresses are latched on the falling edge, and data are  
latched on the rising edge of WE# or CE#, whichever  
happens first.  
The entire chip is bulk erased using 10 ms erase pulses  
according to MXIC's Automatic Chip Erase algorithm.  
Typical erasure at room temperature is accomplished in  
less than 4 second. The Automatic Erase algorithm au-  
tomatically programs the entire array prior to electrical  
erase. The timing and verification of electrical erase are  
controlled internally within the device.  
MXIC's Flash technology combines years of EPROM  
experience to produce the highest levels of quality, reli-  
ability, and cost effectiveness. The MX29LV002C T/B  
electrically erases all bits simultaneously using Fowler-  
Nordheim tunneling. The bytes are programmed by us-  
ing the EPROM programming mechanism of hot elec-  
tron injection.  
AUTOMATIC SECTOR ERASE  
The MX29LV002CT/B is sector(s) erasable using MXIC's  
Auto Sector Erase algorithm. The Automatic Sector  
Erase algorithm automatically programs the specified  
sector(s) prior to electrical erase. The timing and verifi-  
cation of electrical erase are controlled internally within  
the device. An erase operation can erase one sector,  
multiple sectors, or the entire device.  
During a program cycle, the state-machine will control  
the program sequences and command register will not  
respond to any command set. During a Sector Erase  
cycle, the command register will only respond to Erase  
Suspend command. After Erase Suspend is completed,  
the device stays in read mode. After the state machine  
has completed its task, it will allow the command regis-  
ter to respond to its full command set.  
AUTOMATIC PROGRAMMING ALGORITHM  
MXIC's Automatic Programming algorithm requires the  
user to only write program set-up commands (including  
2 unlock write cycle and A0H) and a program command  
(program data and address). The device automatically  
times the programming pulse width, provides the pro-  
gram verification, and counts the number of sequences.  
The device provides an unlock bypass mode with faster  
programming. Only two write cycles are needed to pro-  
gram a byte, instead of four. A status bit similar to Data#  
Polling and a status bit toggling between consecutive  
read cycles, provide feedback to the user as to the sta-  
tus of the programming operation. Refer to write opera-  
tion status, table7, for more information on these status  
bits.  
AUTOMATIC SELECT  
The automatic select mode provides manufacturer and  
device identification, and sector protection verification,  
through identifier codes output on Q7~Q0.This mode is  
mainly adapted for programming equipment on the de-  
vice to be programmed with its programming algorithm.  
When programming by high voltage method, automatic  
select mode requires VID (11.5V to 12.5V) on address  
pin A9 and other address pin A6, A1 as referring toTable  
3. In addition, to access the automatic select codes in-  
system, the host can issue the automatic select com-  
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MX29LV002C/002NC T/B  
mand through the command register without requiringVID,  
as shown in table4.  
To verify whether or not sector being protected, the sec-  
tor address must appear on the appropriate highest or-  
der address bit (see Table 1 and Table 2). The rest of  
address bits, as shown in table3, are don't care. Once  
all necessary bits have been set as required, the pro-  
gramming equipment may read the corresponding iden-  
tifier code on Q7~Q0.  
TABLE 3. MX29LV002C T/B AUTOSELECT MODE OPERATION  
A17 A12  
A8  
|
A5  
|
Description  
CE# OE# WE# RESET#  
|
|
A9  
A6  
A1 A0  
Q7~Q0  
(note) A13 A10  
A7  
X
A2  
X
Manufacture Code  
Device ID  
L
L
L
L
H
H
H
H
X
X
X
X
VID  
VID  
L
L
L
L
L
C2H  
59H  
Read  
Silicon  
ID  
X
X
H
(Top Boot Block)  
Device ID  
L
L
L
L
H
H
H
H
X
X
X
VID  
VID  
X
X
L
L
X
X
L
H
L
5AH  
01H  
(Bottom Boot Block)  
Sector Protection Verification  
SA  
H
(protected)  
00H  
(unprotected)  
NOTE: SA=Sector Address, X=Don't Care, L=Logic Low, H=Logic High.  
RESET# pin for 32-TSOP only.  
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MX29LV002C/002NC T/B  
TABLE 4. MX29LV002C T/B COMMAND DEFINITIONS  
First Bus  
Bus Cycle  
Second Bus Third Bus  
Fourth Bus  
Cycle  
Fifth Bus  
Cycle  
Sixth Bus  
Cycle  
Command  
Cycle  
Cycle  
Cycle Addr Data Addr  
XXXH F0H  
RA RD  
555H AAH 2AAH 55H 555H 90H ADI  
Data Addr  
Data Addr Data Addr  
Data Addr Data  
Reset  
1
Read  
1
Read Silicon ID  
Sector Protect  
Verify  
4
4
DDI  
555H AAH 2AAH 55H 555H 90H (SA) 00H  
x02H 01H  
Program  
4
6
6
1
1
555H AAH 2AAH 55H 555H A0H PA  
PD  
Chip Erase  
555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H  
555H 10H  
SA 30H  
Sector Erase  
Sector Erase Suspend  
Sector Erase Resume  
555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H  
XXXH B0H  
XXXH 30H  
Notes:  
1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacturer code,A1=0, A0 = 1 for device code. A2-A17=do  
not care.  
(Refer to table 3)  
DDI = Data of Device identifier : C2H for manufacture code, 59H/5AH (Top/Bottom) for device code.  
X = X can be VIL or VIH  
RA=Address of memory location to be read.  
RD=Data to be read at location RA.  
2. PA = Address of memory location to be programmed.  
PD = Data to be programmed at location PA.  
SA = Address of the sector to be erased.  
3. The system should generate the following address patterns: 555H or 2AAH to Address A11~A0.  
Address bit A12~A18=X=Don't care for all address commands except for Program Address (PA) and Sector  
Address (SA). Write Sequence may be initiated with A12~A18 in either state.  
4. For Sector ProtectVerify operation:If read out data is 01H, it means the sector has been protected. If read out data  
is 00H, it means the sector is still not being protected.  
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MX29LV002C/002NC T/B  
COMMAND DEFINITIONS  
read mode. Table 4 defines the valid register command  
sequences. Note that the Erase Suspend (B0H) and  
Erase Resume (30H) commands are valid only while the  
Sector Erase operation is in progress.  
Device operations are selected by writing specific ad-  
dress and data sequences into the command register.  
Writing incorrect address and data values or writing them  
in the improper sequence will reset the device to the  
TABLE 5. MX29LV002C T/B BUS OPERATION  
RE-  
ADDRESS  
DESCRIPTION  
CE# OE# WE# SET# A17 A12 A9 A8 A6 A5 A1 A0  
Q0~Q7  
(8)  
H
H
L
A13 A10  
A7  
AIN  
AIN  
X
A2  
Read  
Write  
Reset  
L
L
L
H
X
H
L
Dout  
DIN(3)  
High Z  
X
X
Temporary sector unlock  
Output Disable  
Standby  
X
X
H
X
X
H
X
VID  
H
AIN  
X
DIN  
L
VCC±  
0.3V  
L
High Z  
High Z  
VCC±  
0.3V  
VID  
VID  
H
X
Sector Protect  
H
H
L
L
L
SA  
X
X
X
X
X
X
X
X
X
L
H
L
X
X
X
H
H
H
L
L
L
DIN  
DIN  
Chip Unprotect  
L
Sector ProtectionVerify  
L
H
SA  
VID  
CODE(5)  
Notes:  
1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer toTable 4.  
2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.  
3. Refer to Table 4 for valid Data-In during a write operation.  
4. X can be VIL or VIH.  
5. Code=00H means unprotected.  
Code=01H means protected.  
6. A18~A13=Sector address for sector protect.  
7. The sector protect and chip unprotect functions may also be implemented via programming equipment.  
8. RESET# pin for 32-TSOP package type only.  
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MX29LV002C/002NC T/B  
REQUIREMENTS FOR READING ARRAY  
STANDBY MODE  
DATA  
When using both pins of CE# and RESET#, the device  
enter CMOS Standby with both pins held at Vcc± 0.3V.  
The RESET# pin is provided only for 40-pinTSOP pack-  
age type. If CE# and RESET# are held at VIH, but not  
within the range of VCC ± 0.3V, the device will still be in  
the standby mode, but the standby current will be larger.  
During Auto Algorithm operation, Vcc active current  
(Icc2) is required even CE# = "H" until the operation is  
completed. The device can be read with standard ac-  
cess time (tCE) from either of these standby modes,  
before it is ready to read data.  
To read array data from the outputs, the system must  
drive the CE# and OE# pins to VIL. CE# is the power  
control and selects the device. OE# is the output control  
and gates array data to the output pins.WE# should remain  
at VIH.  
The internal state machine is set for reading array data  
upon device power-up, or after a hardware reset. This  
ensures that no spurious alteration of the memory content  
occurs during the power transition. No command is  
necessary in this mode to obtain array data. Standard  
microprocessor read cycles that assert valid address on  
the device address inputs produce valid data on the device  
data outputs.The device remains enabled for read access  
until the command register contents are altered.  
OUTPUT DISABLE  
With the OE# input at a logic high level (VIH), output  
from the devices are disabled.This will cause the output  
pins to be in a high impedance state.  
WRITE COMMANDS/COMMAND SEQUENCES  
RESET# OPERATION (for 32-TSOP package type)  
To program data to the device or erase sectors of memory  
, the system must drive WE# and CE# to VIL, and OE#  
to VIH.  
The RESET# pin provides a hardware method of resetting  
the device to reading array data.When the RESET# pin  
is driven low for at least a period of tRP, the device  
immediately terminates any operation in progress,  
tristates all output pins, and ignores all read/write  
commands for the duration of the RESET# pulse. The  
device also resets the internal state machine to reading  
array data.The operation that was interrupted should be  
reinitiated once the device is ready to accept another  
command sequence, to ensure data integrity  
An erase operation can erase one sector, multiple sectors  
, or the entire device.Table indicates the address space  
that each sector occupies. A "sector address" consists  
of the address bits required to uniquely select a sector.  
The "Writing specific address and data commands or  
sequences into the command register initiates device  
operations. Table 1 defines the valid register command  
sequences.Writing incorrect address and data values or  
writing them in the improper sequence resets the device  
to reading array data. Section has details on erasing a  
sector or the entire chip, or suspending/resuming the erase  
operation.  
Current is reduced for the duration of the RESET# pulse.  
When RESET# is held at VSS±0.3V, the device draws  
CMOS standby current (ICC4).If RESET# is held atVIL  
but not within VSS±0.3V, the standby current will be  
greater.  
After the system writes the autoselect command  
sequence, the device enters the autoselect mode. The  
system can then read autoselect codes from the internal  
register (which is separate from the memory array) on  
Q7-Q0. Standard read cycle timings apply in this mode.  
Refer to the Autoselect Mode and Autoselect Command  
Sequence section for more information.  
The RESET# pin may be tied to system reset circuitry.  
A system reset would that also reset the Flash memory,  
enabling the system to read the boot-up firm-ware from  
the Flash memory.  
If RESET# is asserted during a program or erase  
operation, the RY/BY# pin remains a "0" (busy) until the  
internal reset operation is complete, which requires a time  
of tREADY (during Embedded Algorithms).The system  
can thus monitor RY/BY# to determine whether the reset  
ICC2 in the DC Characteristics table represents the active  
current specification for the write mode. The "AC  
Characteristics" section contains timing specification table  
and timing diagrams for write operations.  
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MX29LV002C/002NC T/B  
operation is complete. If RESET# is asserted when a  
sector erase command 30H.  
program or erase operation is completed within a time of  
tREADY (not during Embedded Algorithms).The system  
can read data tRH after the RESET# pin returns toVIH.  
The Automatic Chip Erase does not require the device to  
be entirely pre-programmed prior to executing the Auto-  
matic Chip Erase. Upon executing the Automatic Chip  
Erase, the device will automatically program and verify  
the entire memory for an all-zero data pattern. When the  
device is automatically verified to contain an all-zero pat-  
tern, a self-timed chip erase and verify begin. The erase  
and verify operations are completed when the data on  
Q7 is "1" at which time the device returns to the Read  
mode. The system is not required to provide any control  
or timing during these operations.  
Refer to the AC Characteristics tables for RESET#  
parameters and to Figure 24 for the timing diagram.  
READ/RESET COMMAND  
The read or reset operation is initiated by writing the read/  
reset command sequence into the command register.  
Microprocessor read cycles retrieve array data. The de-  
vice remains enabled for reads until the command regis-  
ter contents are altered.  
When using the Automatic Chip Erase algorithm, note  
that the erase automatically terminates when adequate  
erase margin has been achieved for the memory array(no  
erase verification command is required).  
If program-fail or erase-fail happen, the write of F0H will  
reset the device to abort the operation. A valid com-  
mand must then be written to place the device in the  
desired state.  
If the Erase operation was unsuccessful, the data on Q5  
is "1"(see Table 7), indicating the erase operation ex-  
ceed internal timing limit.  
The automatic erase begins on the rising edge of the last  
WE# or CE# pulse, whichever happens first in the com-  
mand sequence and terminates when the data on Q7 is  
"1" and the data on Q6 stops toggling for two consecu-  
tive read cycles, at which time the device returns to the  
Read mode.  
SILICON-ID READ COMMAND  
Flash memories are intended for use in applications where  
the local CPU alters memory contents. As such, manu-  
facturer and device codes must be accessible while the  
device resides in the target system. PROM program-  
mers typically access signature codes by raising A9 to  
a high voltage (VID). However, multiplexing high voltage  
onto address lines is not generally desired system de-  
sign practice.  
The MX29LV002C T/B contains a Silicon-ID-Read op-  
eration to supple traditional PROM programming meth-  
odology. The operation is initiated by writing the read  
silicon ID command sequence into the command regis-  
ter. Following the command write, a read cycle with  
A1=VIL, A0=VIL retrieves the manufacturer code of C2H.  
A read cycle with A1=VIL, A0=VIH returns the device  
code of 59H for MX29LV002CT, 5AH for MX29LV002CB.  
SET-UP AUTOMATIC CHIP/SECTOR ERASE  
COMMANDS  
Chip erase is a six-bus cycle operation. There are two  
"unlock" write cycles. These are followed by writing the  
"set-up" command 80H. Two more "unlock" write cycles  
are then followed by the chip erase command 10H or  
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MX29LV002C/002NC T/B  
TABLE 6. EXPANDED SILICON ID CODE  
Pins  
A0  
A1  
Q7 Q6  
Q5  
0
Q4  
0
Q3  
0
Q2  
0
Q1  
1
Q0  
0
Code(Hex)  
C2H  
Manufacture code  
Device code  
VIL VIL  
VIH VIL  
1
1
1
0
1
1
1
0
0
1
59H  
for MX29LV002CT  
Device code  
VIH VIL  
1
0
1
1
1
0
1
0
5AH  
for MX29LV002CB  
Sector Protection  
Verification  
X
X
VIH  
VIH  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
01H (Protected)  
00H (Unprotected)  
READING ARRAY DATA  
RESET COMMAND  
The device is automatically set to reading array data  
after device power-up.No commands are required to re-  
trieve data.The device is also ready to read array data  
after completing an Automatic Program or Automatic  
Erase algorithm.  
Writing the reset command to the device resets the de-  
vice to reading array data.Address bits are don't care for  
this command.  
The reset command may be written between the se-  
quence cycles in an erase command sequence before  
erasing begins. This resets the device to reading array  
data.Once erasure begins, however, the device ignores  
reset commands until the operation is complete.  
After the device accepts an Erase Suspend command,  
the device enters the Erase Suspend mode. The sys-  
tem can read array data using the standard read tim-  
ings, except that if it reads at an address within erase-  
suspended sectors, the device outputs status data. Af-  
ter completing a programming operation in the Erase  
Suspend mode, the system may once again read array  
data with the same exception. See "Erase Suspend/  
Erase Resume Commands" for more infor-mation on this  
mode.  
The reset command may be written between the se-  
quence cycles in a program command sequence be-fore  
programming begins. This resets the device to reading  
array data (also applies to programming in Erase Sus-  
pend mode). Once programming begins, however, the  
device ignores reset commands until the operation is  
complete.  
The system must issue the reset command to re-en-  
able the device for reading array data if Q5 goes high, or  
while in the autoselect mode.See the "Reset Command"  
section, next.  
The reset command may be written between the se-  
quence cycles in an SILICON ID READ command se-  
quence.Once in the SILICON ID READ mode, the reset  
command must be written to return to reading array data  
(also applies to SILICON ID READ during Erase Sus-  
pend).  
If Q5 goes high during a program or erase operation, writ-  
ing the reset command returns the device to reading ar-  
ray data (also applies during Erase Suspend).  
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SECTOR ERASE COMMANDS  
The Automatic Sector Erase does not require the de-  
vice to be entirely pre-programmed prior to executing  
the Automatic Sector Erase Set-up command and Au-  
tomatic Sector Erase command. Upon executing the  
Automatic Sector Erase command, the device will auto-  
matically program and verify the sector(s) memory for  
an all-zero data pattern. The system is not required to  
provide any control or timing during these operations.  
(no erase verification command is required). Sector erase  
is a six-bus cycle operation. There are two "unlock" write  
cycles. These are followed by writing the set-up com-  
mand 80H. Two more "unlock" write cycles are then fol-  
lowed by the sector erase command 30H. The sector  
address is latched on the falling edge of WE# or CE#,  
whichever happens later, while the command (data) is  
latched on the rising edge of WE# or CE#, whichever  
happens first. Sector addresses selected are loaded  
into internal register on the sixth falling edge of WE# or  
CE#, whichever happens later. Each successive sector  
load cycle started by the falling edge of WE# or CE#,  
whichever happens later must begin within 50us from  
the rising edge of the preceding WE# or CE#, whichever  
happens first. Otherwise, the loading period ends and  
internal auto sector erase cycle starts. (Monitor Q3 to  
determine if the sector erase timer window is still open,  
see section Q3, Sector EraseTimer.) Any command other  
than Sector Erase(30H) or Erase Suspend(B0H) during  
the time-out period resets the device to read mode.  
When the sector(s) is automatically verified to contain  
an all-zero pattern, a self-timed sector erase and verify  
begin. The erase and verify operations are complete  
when the data on Q7 is "1" and the data on Q6 stops  
toggling for two consecutive read cycles, at which time  
the device returns to the Read mode. The system is not  
required to provide any control or timing during these  
operations.  
When using the Automatic sector Erase algorithm, note  
that the erase automatically terminates when adequate  
erase margin has been achieved for the memory array  
Table 7. Write Operation Status  
Status  
Q7  
Q6  
Q5  
Q3  
Q2 RY/BY#  
(Note1)  
(Note2)  
Byte Program in Auto Program Algorithm  
Auto Erase Algorithm  
Q7# Toggle  
0
N/A  
1
No  
0
Toggle  
0
1
Toggle  
0
0
Toggle  
0
1
Erase Suspend Read  
(Erase Suspended Sector)  
No  
Toggle  
N/A Toggle  
In Progress  
Erase Suspended Mode  
Erase Suspend Read  
Data  
Data Data Data Data  
1
0
0
(Non-Erase Suspended Sector)  
Erase Suspend Program  
Q7# Toggle  
Q7# Toggle  
0
1
N/A N/A  
Byte Program in Auto Program Algorithm  
N/A  
1
No  
Toggle  
Exceeded  
Time Limits Auto Erase Algorithm  
0
Toggle  
1
1
Toggle  
0
0
Erase Suspend Program  
Q7# Toggle  
N/A N/A  
Note:  
1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further details.  
2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.  
See "Q5:Exceeded Timing Limits " for more information.  
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ing edge, and data are internally latched on the rising  
edge of the WE# or CE#, whichever happens first. The  
ERASE SUSPEND  
This command only has meaning while the state ma-  
chine is executing Automatic Sector Erase operation,  
and therefore will only be responded during Automatic  
Sector Erase operation. When the Erase Suspend com-  
mand is written during a sector erase operation, the de-  
vice requires a maximum of 20us to suspend the erase  
operations.However, When the Erase Suspend command  
is written during the sector erase time-out, the device  
immediately terminates the time-out period and suspends  
the erase operation. After this command has been ex-  
ecuted, the command register will initiate erase suspend  
mode. The state machine will return to read mode auto-  
matically after suspend is ready. At this time, state ma-  
chine only allows the command register to respond to  
the Read Memory Array, Erase Resume and program  
commands.  
rising edge of WE# or CE#, whichever happens first,  
also begins the programming operation. The system is  
not required to provide further controls or timings. The  
device will automatically provide an adequate internally  
generated program pulse and verify margin.  
The device provides Q2, Q3, Q5, Q6, Q7, and RY/BY#  
to determine the status of a write operation. If the pro-  
gram operation was unsuccessful, the data on Q5 is  
"1"(seeTable 7), indicating the program operation exceed  
internal timing limit.The automatic programming opera-  
tion is completed when the data read on Q6 stops tog-  
gling for two consecutive read cycles and the data on Q7  
and Q6 are equivalent to data written to these two bits,  
at which time the device returns to the Read mode(no  
program verify command is required).  
The system can determine the status of the program  
operation using the Q7 or Q6 status bits, just as in the  
standard program operation. After an erase-suspend pro-  
gram operation is complete, the system can once again  
read array data within non-suspended sectors.  
BYTE PROGRAM COMMAND SEQUENCE  
The device programs one byte of data for each program  
operation. The command sequence requires four bus  
cycles, and is initiated by writing two unlock write cycles,  
followed by the program set-up command. The program  
address and data are written next, which in turn initiate  
the Embedded Program algorithm. The system is not  
required to provide further controls or timings. The device  
automatically generates the program pulses and verifies  
the programmed cell margin. Table 1 shows the address  
and data requirements for the byte program command  
sequence.  
ERASE RESUME  
This command will cause the command register to clear  
the suspend state and return back to Sector Erase mode  
but only if an Erase Suspend command was previously  
issued. Erase Resume will not have any effect in all  
other conditions. Another Erase Suspend command can  
be written after the chip has resumed erasing.However,  
a 10ms time delay must be required after the erase re-  
sume command, if the system implements an endless  
erase suspend/resume loop, or the number of erase sus-  
pend/resume is exceeded 1024 times.The erase times  
will be expended if the erase behavior always be sus-  
pended. (Please refer to MXIC Flash Application Note  
for details.)  
When the Embedded Program algorithm is complete,  
the device then returns to reading array data and  
addresses are no longer latched. The system can  
determine the status of the program operation by using  
Q7, Q6, or RY/BY#. See "Write Operation Status" for  
information on these status bits.  
Any commands written to the device during the Em-  
bedded Program Algorithm are ignored. Note that a  
hardware reset immediately terminates the programming  
operation. The Byte Program command sequence should  
be reinitiated once the device has reset to reading array  
data, to ensure data integrity.  
AUTOMATIC PROGRAM COMMANDS  
To initiate Automatic Program mode, A three-cycle com-  
mand sequence is required. There are two "unlock" write  
cycles. These are followed by writing the Automatic Pro-  
gram command A0H.  
Programming is allowed in any sequence and across  
sector boundaries. A bit cannot be programmed from a  
"0" back to a "1". Attempting to do so may halt the  
operation and set Q5 to "1", or cause the Data# Polling  
algorithm to indicate the operation was successful.  
However, a succeeding read will show that the data is  
Once the Automatic Program command is initiated, the  
next WE# pulse causes a transition to an active pro-  
gramming operation. Addresses are latched on the fall-  
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MX29LV002C/002NC T/B  
still "0". Only erase operations can convert a "0" to a  
"1".  
unprotected sectors, and ignores the selected sectors  
that are protected.  
When the system detects Q7 has changed from the  
complement to true data, it can read valid data at Q7-Q0  
on the following read cycles. This is because Q7 may  
change asynchronously with Q0-Q6 while Output En-  
able (OE#) is asserted low.  
WRITE OPERATION STATUS  
The device provides several bits to determine the sta-  
tus of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/  
BY#. Table 10 and the following subsections describe  
the functions of these bits. Q7, RY/BY#, and DQ6 each  
offer a method for determining whether a program or erase  
operation is complete or in progress. These three bits  
are discussed first. Please note that RY/BY# pin is pro-  
vided for 40-pin TSOP package type only.  
RY/BY#:Ready/Busy# (for 32-pin TSOP package  
only)  
The RY/BY# is a dedicated, open-drain output pin that  
indicates whether an Automatic Erase/Program algorithm  
is in progress or complete. The RY/BY# status is valid  
after the rising edge of the final WE# or CE#, whichever  
happens first, in the command sequence.Since RY/BY#  
is an open-drain output, several RY/BY# pins can be tied  
together in parallel with a pull-up resistor to Vcc.  
Q7: Data# Polling  
The Data# Polling bit, Q7, indicates to the host sys-tem  
whether an Automatic Algorithm is in progress or com-  
pleted, or whether the device is in Erase Suspend.Data#  
Polling is valid after the rising edge of the finalWE# pulse  
in the program or erase command sequence.  
If the output is low (Busy), the device is actively erasing  
or programming. (This includes programming in the Erase  
Suspend mode.) If the output is high (Ready), the de-  
vice is ready to read array data (including during the  
Erase Suspend mode), or is in the standby mode.  
During the Automatic Program algorithm, the device out-  
puts on Q7 the complement of the datum programmed  
to Q7.This Q7 status also applies to programming dur-  
ing Erase Suspend.When the Automatic Program algo-  
rithm is complete, the device outputs the datum pro-  
grammed to Q7.The system must provide the program  
address to read valid status information on Q7. If a pro-  
gram address falls within a protected sector, Data# Poll-  
ing on Q7 is active for approximately 1 us, then the de-  
vice returns to reading array data.  
Table 7 shows the outputs for RY/BY# during write op-  
eration.  
Q6:Toggle BIT I  
Toggle Bit I on Q6 indicates whether an Automatic Pro-  
gram or Erase algorithm is in progress or complete, or  
whether the device has entered the Erase Suspend mode.  
Toggle Bit I may be read at any address, and is valid  
after the rising edge of the final WE# or CE#, whichever  
happens first, in the command sequence (prior to the  
program or erase operation), and during the sector time-  
out.  
During the Automatic Erase algorithm, Data# Polling pro-  
duces a "0" on Q7. When the Automatic Erase algo-  
rithm is complete, or if the device enters the Erase Sus-  
pend mode, Data# Polling produces a "1" on Q7.This is  
analogous to the complement/true datum out-put de-  
scribed for the Automatic Program algorithm: the erase  
function changes all the bits in a sector to "1" prior to  
this, the device outputs the "complement," or "0". The  
system must provide an address within any of the sec-  
tors selected for erasure to read valid status information  
on Q7.  
During an Automatic Program or Erase algorithm opera-  
tion, successive read cycles to any address cause Q6  
to toggle. The system may use either OE# or CE# to  
control the read cycles.When the operation is complete,  
Q6 stops toggling.  
After an erase command sequence is written, if all sec-  
tors selected for erasing are protected, Data# Polling on  
Q7 is active for approximately 100 us, then the device  
returns to reading array data. If not all selected sectors  
are protected, the Automatic Erase algorithm erases the  
After an erase command sequence is written, if all sec-  
tors selected for erasing are protected, Q6 toggles and  
returns to reading array data. If not all selected sectors  
are protected, the Automatic Erase algorithm erases the  
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MX29LV002C/002NC T/B  
unprotected sectors, and ignores the selected sectors  
that are protected.  
after the first read. After the second read, the system  
would compare the new value of the toggle bit with the  
first. If the toggle bit is not toggling, the device has  
completed the program or erase operation. The system  
can read array data on Q7-Q0 on the following read cycle.  
The system can use Q6 and Q2 together to determine  
whether a sector is actively erasing or is erase sus-  
pended.When the device is actively erasing (that is, the  
Automatic Erase algorithm is in progress), Q6 toggling.  
When the device enters the Erase Suspend mode, Q6  
stops toggling. However, the system must also use Q2  
to determine which sectors are erasing or erase-sus-  
pended. Alternatively, the system can use Q7.  
However, if after the initial two read cycles, the system  
determines that the toggle bit is still toggling, the sys-  
tem also should note whether the value of Q5 is high  
(see the section on Q5). If it is, the system should then  
determine again whether the toggle bit is toggling, since  
the toggle bit may have stopped toggling just as Q5 went  
high. If the toggle bit is no longer toggling, the device  
has successfully completed the program or erase op-  
eration. If it is still toggling, the device did not complete  
the operation successfully, and the system must write  
the reset command to return to reading array data.  
If a program address falls within a protected sector, Q6  
toggles for approximately 2 us after the program com-  
mand sequence is written, then returns to reading array  
data.  
Q6 also toggles during the erase-suspend-program mode,  
and stops toggling once the Automatic Program algo-  
rithm is complete.  
The remaining scenario is that system initially determines  
that the toggle bit is toggling and Q5 has not gone high.  
The system may continue to monitor the toggle bit and  
Q5 through successive read cycles, determining the sta-  
tus as described in the previous paragraph. Alterna-  
tively, it may choose to perform other system tasks. In  
this case, the system must start at the beginning of the  
algorithm when it returns to determine the status of the  
operation.  
Table 7 shows the outputs for Toggle Bit I on Q6.  
Q2:Toggle Bit II  
The "Toggle Bit II" on Q2, when used with Q6, indicates  
whether a particular sector is actively erasing (that is,  
the Automatic Erase algorithm is in process), or whether  
that sector is erase-suspended. Toggle Bit II is valid  
after the rising edge of the final WE# or CE#, whichever  
happens first, in the command sequence.  
Q5  
ExceededTiming Limits  
Q5 will indicate if the program or erase time has ex-  
ceeded the specified limits (internal pulse count). Under  
these conditions Q5 will produce a "1". This time-out  
condition indicates that the program or erase cycle was  
not successfully completed. Data# Polling and Toggle  
Bit are the only operating functions of the device under  
this condition.  
Q2 toggles when the system reads at addresses within  
those sectors that have been selected for erasure. (The  
system may use either OE# or CE# to control the read  
cycles.) But Q2 cannot distinguish whether the sector  
is actively erasing or is erase-suspended. Q6, by com-  
parison, indicates whether the device is actively eras-  
ing, or is in Erase Suspend, but cannot distinguish which  
sectors are selected for erasure. Thus, both status bits  
are required for sectors and mode information. Refer to  
Table 7 to compare outputs for Q2 and Q6.  
If this time-out condition occurs during sector erase op-  
eration, it specifies that a particular sector is bad and it  
may not be reused. However, other sectors are still func-  
tional and may be used for the program or erase opera-  
tion. The device must be reset to use other sectors.  
Write the Reset command sequence to the device, and  
then execute program or erase command sequence. This  
allows the system to continue to use the other active  
sectors in the device.  
Reading Toggle Bits Q6/ Q2  
Whenever the system initially begins reading toggle bit  
status, it must read Q7-Q0 at least twice in a row to  
determine whether a toggle bit is toggling. Typically, the  
system would note and store the value of the toggle bit  
If this time-out condition occurs during the chip erase  
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MX29LV002C/002NC T/B  
operation, it specifies that the entire chip is bad or com-  
bination of sectors are bad.  
cycles resulting fromVCC power-up and power-down tran-  
sition or system noise.  
If this time-out condition occurs during the byte program-  
ming operation, it specifies that the entire sector con-  
taining that byte is bad and this sector maynot be re-  
used, (other sectors are still functional and can be re-  
used).  
WRITE PULSE "GLITCH" PROTECTION  
Noise pulses of less than 5ns(typical) on CE# or WE#  
will not initiate a write cycle.  
The time-out condition will not appear if a user tries to  
program a non blank location without erasing. Please  
note that this is not a device failure condition since the  
device was incorrectly used.  
LOGICAL INHIBIT  
Writing is inhibited by holding any one of OE# = VIL,  
CE# = VIH or WE# = VIH. To initiate a write cycle CE#  
and WE# must be a logical zero while OE# is a logical  
one.  
Q3  
Sector Erase Timer  
POWER SUPPLY DECOUPLING  
After the completion of the initial sector erase command  
sequence, the sector erase time-out will begin. Q3 will  
remain low until the time-out is complete. Data# Polling  
andToggle Bit are valid after the initial sector erase com-  
mand sequence.  
In order to reduce power switching effect, each device  
should have a 0.1uF ceramic capacitor connected be-  
tween itsVCC and GND.  
If Data# Polling or theToggle Bit indicates the device has  
been written with a valid erase command, Q3 may be  
used to determine if the sector erase timer window is  
still open. If Q3 is high ("1") the internally controlled  
erase cycle has begun; attempts to write subsequent  
commands to the device will be ignored until the erase  
operation is completed as indicated by Data# Polling or  
Toggle Bit. If Q3 is low ("0"), the device will accept  
additional sector erase commands. To insure the com-  
mand has been accepted, the system software should  
check the status of Q3 prior to and following each sub-  
sequent sector erase command. If Q3 were high on the  
second status check, the command may not have been  
accepted.  
POWER-UP SEQUENCE  
The MX29LV002CT/B powers up in the Read only mode.  
In addition, the memory contents may only be altered  
after successful completion of the predefined command  
sequences.  
TEMPORARY SECTOR UNPROTECT  
This feature allows temporary unprotection of previously  
protected sector to change data in-system.TheTempo-  
rary Sector Unprotect mode is activated by setting the  
RESET# pin toVID(11.5V-12.5V). During this mode, for-  
merly protected sectors can be programmed or erased  
as un-protected sector. Once VID is remove from the  
RESET# pin, all the previously protected sectors are pro-  
tected again.  
DATA PROTECTION  
The MX29LV002C T/B is designed to offer protection  
against accidental erasure or programming caused by  
spurious system level signals that may exist during power  
transition. During power up the device automatically re-  
sets the state machine in the Read mode. In addition,  
with its control register architecture, alteration of the  
memory contents only occurs after successful comple-  
tion of specific command sequences. The device also  
incorporates several features to prevent inadvertent write  
SECTOR PROTECTION  
The MX29LV002CT/B features hardware sector protec-  
tion. This feature will disable both program and erase  
operations for these sectors protected. To activate this  
mode, the programming equipment must force VID on  
address pin A9 and OE# (suggestVID = 12V). Program-  
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ming of the protection circuitry begins on the falling edge  
of the WE# pulse and is terminated on the rising edge.  
Please refer to sector protect algorithm and waveform.  
To verify programming of the protection circuitry, the pro-  
gramming equipment must forceVID on address pin A9  
( with CE# and OE# at VIL and WE# at VIH). When  
A1=VIH, A0=VIL, A6=VIL, it will produce a logical "1"  
code at device output Q0 for a protected sector. Other-  
wise the device will produce 00H for the unprotected sec-  
tor. In this mode, the addresses, except for A1, are don't  
care. Address locations with A1 = VIL are reserved to  
read manufacturer and device codes.(Read Silicon ID)  
It is also possible to determine if the sector is protected  
in the system by writing a Read Silicon ID command.  
Performing a read operation with A1=VIH, it will produce  
a logical "1" at Q0 for the protected sector.  
CHIP UNPROTECT  
The MX29LV002C T/B also features the chip unprotect  
mode, so that all sectors are unprotected after chip  
unprotectiscompletedtoincorporateanychangesinthe  
code. It is recommended to protect all sectors before  
activating chip unprotect mode.  
Toactivatethismode,theprogrammingequipmentmust  
force VID on control pin OE# and address pin A9. The  
CE# pins must be set at VIL. Pins A6 must be set to  
VIH.(seeTable2) Refertochipunprotect algorithmand  
waveform for the chip unprotect algorithm. The  
unprotectionmechanismbeginsonthefallingedgeofthe  
WE# pulse and is terminated on the rising edge.  
It is also possible to determine if the chip is unprotected  
in the system by writing the Read Silicon ID command.  
PerformingareadoperationwithA1=VIH,itwillproduce  
00H at data outputs(Q0-Q7) for an unprotected sector.  
It is noted that all sectors are unprotected after the chip  
unprotect algorithm is completed.  
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OPERATING RATINGS  
ABSOLUTE MAXIMUM RATINGS  
StorageTemperature  
Commercial (C) Devices  
Plastic Packages . . . . . . . . . . . . . ..... -65oC to +150oC  
Ambient Temperature (TA ). . . . . . . . . . . . 0° C to +70°C  
Industrial (I) Devices  
AmbientTemperature  
with Power Applied. . . . . . . . . . . . . .... -65oC to +125oC  
Voltage with Respect to Ground  
Ambient Temperature (TA ). . . . . . . . . . -40° C to +85°C  
VCC Supply Voltages  
VCC for full voltage range. . . . . . . . . . . +2.7 V to 3.6 V  
VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V  
A9, OE#, and  
Operating ranges define those limits between which the  
functionality of the device is guaranteed.  
RESET# (Note 2) . . . . . . . . . . . ....-0.5 V to +12.5 V  
All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V  
Output Short Circuit Current (Note 3) . . . . . . 200 mA  
Notes:  
1. Minimum DC voltage on input or I/O pins is -0.5 V.  
During voltage transitions, input or I/O pins may over-  
shoot VSS to -2.0 V for periods of up to 20 ns. Maxi-  
mum DC voltage on input or I/O pins is VCC +0.5 V.  
During voltage transitions, input or I/O pins may over-  
shoot to VCC +2.0 V for periods up to 20 ns.  
2.Minimum DC input voltage on pins A9, OE#, and RE-  
SET# is -0.5 V. During voltage transitions, A9, OE#,  
and RESET# may overshootVSS to -2.0V for periods  
of up to 20 ns.Maximum DC input voltage on pin A9 is  
+12.5V which may overshoot to 14.0V for periods up  
to 20 ns.The RESET# pin is provided for 40-pinTSOP  
package type.  
3.No more than one output may be shorted to ground at  
a time.Duration of the short circuit should not be greater  
than one second.  
Stresses above those listed under "Absolute Maximum  
Ratings" may cause permanent damage to the device.  
This is a stress rating only; functional operation of the  
device at these or any other conditions above those indi-  
cated in the operational sections of this data sheet is not  
implied. Exposure of the device to absolute maximum  
rating conditions for extended periods may affect device  
reliability.  
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Table 8. CAPACITANCE TA = 25oC, f = 1.0 MHz  
SYMBOL PARAMETER  
MIN.  
TYP  
MAX.  
8
UNIT  
pF  
CONDITIONS  
VIN = 0V  
CIN1  
CIN2  
COUT  
Input Capacitance  
Control Pin Capacitance  
Output Capacitance  
12  
pF  
VIN = 0V  
12  
pF  
VOUT = 0V  
Table 9. DC CHARACTERISTICS TA = -40oC to 85oC, VCC = 2.7V to 3.6V  
Symbol PARAMETER  
MIN.  
TYP  
MAX.  
± 1  
35  
± 1  
12  
4
UNIT  
uA  
CONDITIONS  
ILI  
Input Leakage Current  
VIN = VSS to VCC  
ILIT  
ILO  
ICC1  
A9 Input Leakage Current  
Output Leakage Current  
VCC Active Read Current  
uA  
VCC=VCC max; A9=12.5V  
VOUT = VSS to VCC, VCC=VCC max  
CE#=VIL, OE#=VIH @5MHz  
@1MHz  
uA  
7
2
mA  
mA  
mA  
uA  
ICC2  
ICC3  
VCC Active write Current  
VCC Standby Current  
15  
0.2  
30  
5
CE#=VIL, OE#=VIH  
CE#; RESET#=VCC ± 0.3V  
(RESET# pin for 40-TSOP)  
RESET#=VSS ± 0.3V  
ICC4  
VCC Standby Current  
During Reset  
0.2  
0.2  
5
uA  
(RESET# pin for 40-TSOP)  
VIH=VCC ± 0.3V; VIL=VSS ± 0.3V  
ICC5  
VIL  
Automatic sleep mode  
Input Low Voltage(Note 1)  
Input High Voltage  
Voltage for Automatic  
Select and Temporary  
Chip Unprotect  
5
uA  
V
-0.5  
0.8  
VIH  
VID  
0.7xVCC  
VCC+ 0.3  
V
11.5  
12.5  
0.45  
V
V
VCC=3.3V  
VOL  
Output Low Voltage  
Output High Voltage(TTL)  
Output High Voltage  
(CMOS)  
IOL = 4.0mA, VCC= VCC min  
IOH = -2mA, VCC=VCC min  
IOH = -100uA, VCC min  
VOH1  
VOH2  
0.85xVCC  
VCC-0.4  
NOTES:  
1. VIL min. = -1.0V for pulse width is equal to or less than 50 ns.  
VIL min. = -2.0V for pulse width is equal to or less than 20 ns.  
2. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns  
If VIH is over the specified maximum value, read operation cannot be guaranteed.  
3. Automatic sleep mode enable the low power mode when addresses remain stable for tACC +30ns.  
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AC CHARACTERISTICS  
TA = -40oC to 85oC, VCC = 2.7V~3.6V  
Table 10. READ OPERATIONS  
29LV002CT/B-70  
29LV002CT/B-90  
SYMBOL PARAMETER  
MIN.  
MAX.  
70  
MIN.  
MAX.  
90  
UNIT CONDITIONS  
tRC  
tACC  
tCE  
Read Cycle Time (Note 1)  
Address to Output Delay  
CE# to Output Delay  
ns  
70  
90  
ns  
ns  
ns  
ns  
ns  
ns  
CE#=OE#=VIL  
OE#=VIL  
70  
90  
tOE  
OE# to Output Delay  
30  
35  
CE#=VIL  
tDF  
OE# High to Output Float (Note1)  
Output Enable Read  
0
25  
0
30  
CE#=VIL  
tOEH  
0
0
Hold Time  
Toggle and  
10  
10  
Data# Polling  
tOH  
Address to Output hold  
0
0
ns  
CE#=OE#=VIL  
NOTE:  
1. Not 100% tested.  
TEST CONDITIONS:  
• Input pulse levels: 0V/3.0V.  
2. tDF is defined as the time at which the output achieves  
the open circuit condition and data is no longer driven.  
• Input rise and fall times is equal to or less than 5ns.  
• Outputload:1TTLgate+100pF(Includingscopeand  
jig),for29LV002CT/B-90.1TTL gate+30pF(Including  
scope and jig) for 29LV002CT/B-70.  
• Reference levels for measuring timing: 1.5V.  
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MX29LV002C/002NC T/B  
Figure 1. SWITCHING TEST CIRCUITS  
DEVICE UNDER  
TEST  
2.7K ohm  
+3.3V  
CL  
6.2K ohm  
DIODES=IN3064  
OR EQUIVALENT  
CL=100pF Including jig capacitance  
CL=30pF for MX29LV004T/B-70  
Figure 2. SWITCHING TEST WAVEFORMS  
3.0V  
1.5V  
TEST POINTS  
1.5V  
0V  
INPUT  
OUTPUT  
AC TESTING: Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0".  
Input pulse rise and fall times are < 5ns.  
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Figure 3. READ TIMING WAVEFORMS  
tRC  
VIH  
VIL  
ADD Valid  
Addresses  
tACC  
tCE  
VIH  
VIL  
CE#  
VIH  
VIL  
WE#  
tOE  
tDF  
tOEH  
VIH  
VIL  
OE#  
Outputs  
RESET#  
tACC  
tOH  
HIGH Z  
HIGH Z  
VOH  
VOL  
DATA Valid  
VIH  
VIL  
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AC CHARACTERISTICS  
TA = -40oC to 85oC, VCC = 2.7V~3.6V  
Table 11. Erase/Program Operations  
29LV002CT/B-70  
29LV002CT/B-90  
SYMBOL PARAMETER  
MIN.  
70  
0
MAX.  
MIN.  
90  
0
MAX.  
UNIT  
ns  
tWC  
tAS  
Write Cycle Time (Note 1)  
Address Setup Time  
Address Hold Time  
ns  
tAH  
45  
35  
0
45  
45  
0
ns  
tDS  
Data Setup Time  
ns  
tDH  
Data Hold Time  
ns  
tOES  
tGHWL  
Output Enable Setup Time  
Read Recovery Time Before Write  
(OE# High to WE# Low)  
CE# Setup Time  
0
0
ns  
0
0
ns  
tCS  
0
0
ns  
ns  
ns  
ns  
us  
tCH  
CE# Hold Time  
0
0
tWP  
tWPH  
Write Pulse Width  
35  
35  
Write Pulse Width High  
30  
30  
tWHWH1 ProgrammingOperation(Note2)  
(Byte/Wordprogramtime)  
9(Typ.)  
9(Typ.)  
tWHWH2 Sector Erase Operation (Note 2)  
0.7(Typ.)  
0.7(Typ.)  
sec  
us  
tVCS  
tRB  
VCC Setup Time (Note 1)  
50  
0
50  
0
Recovery Time from RY/BY#  
Program/Erase Vaild to RY/BY# Delay  
Write Pulse Width for Sector Protect  
(A9, OE#Control)  
ns  
tBUSY  
tWPP1  
90  
90  
ns  
100ns  
10us  
(Typ.)  
12ms  
(Typ.)  
50  
100ns  
100ns  
10us  
(Typ.)  
12ms  
(Typ.)  
50  
tWPP2  
Write Pulse Width for Sector Unprotect  
(A9, OE#Control)  
100nss  
tBAL  
Sector Address Load Time  
us  
NOTES:  
1. Not 100% tested.  
2. See the "Erase and Programming Performance" section for more information.  
3. RY/BY# pin is provided for 32-TSOP.  
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AC CHARACTERISTICS  
TA = -40oC to 85oC,VCC = 2.7V~3.6V  
Table 12. Alternate CE# Controlled Erase/Program Operations  
29LV002CT/B-70  
29LV002CT/B-90  
SYMBOL PARAMETER  
MIN.  
MAX.  
MIN.  
MAX.  
UNIT  
ns  
tWC  
tAS  
Write CycleTime (Note 1)  
70  
90  
Address SetupTime  
Address HoldTime  
Data SetupTime  
0
0
ns  
tAH  
45  
45  
ns  
tDS  
35  
45  
ns  
tDH  
Data HoldTime  
0
0
ns  
tOES  
tGHEL  
tWS  
tWH  
tCP  
Output Enable SetupTime  
Read RecoveryTime BeforeWrite  
WE# SetupTime  
0
0
ns  
0
0
ns  
0
0
ns  
WE# HoldTime  
0
0
ns  
CE# PulseWidth  
35  
35  
ns  
tCPH  
CE# Pulse Width High  
30  
30  
ns  
tWHWH1 Programming Operation(note2)  
tWHWH2 Sector Erase Operation (note2)  
9(Typ.)  
0.7(Typ.)  
9(Typ.)  
0.7(Typ.)  
us  
sec  
NOTE:  
1. Not 100% tested.  
2. See the "Erase and Programming Performance" section for more information.  
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Figure 4. COMMAND WRITE TIMING WAVEFORM  
VCC  
3V  
VIH  
VIL  
Addresses  
ADD Valid  
tAH  
tAS  
VIH  
VIL  
WE#  
CE#  
tOES  
tWPH  
tWP  
tCWC  
VIH  
VIL  
tCS  
tCH  
tDH  
VIH  
VIL  
OE#  
Data  
tDS  
VIH  
VIL  
DIN  
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AUTOMATIC PROGRAMMING TIMING WAVEFORM  
after automatic programming starts. Device outputs  
DATA# during programming and DATA after programming  
on Q7.(Q6 is for toggle bit; see toggle bit, Data# Polling,  
timing waveform)  
One byte data is programmed. Verify in fast algorithm  
and additional verification by external control are not re-  
quired because these operations are executed automati-  
cally by internal control circuit. Programming completion  
can be verified by Data# Polling and toggle bit checking  
Figure 5. AUTOMATIC PROGRAMMING TIMING WAVEFORM  
Program Command Sequence(last two cycle)  
Read Status Data (last two cycle)  
tWC  
tAS  
PA  
PA  
555h  
PA  
Address  
CE#  
tAH  
tCH  
tGHWL  
OE#  
WE#  
tWHWH1  
tWP  
tCS  
tWPH  
tDS tDH  
Status  
A0h  
PD  
DOUT  
Data  
tBUSY  
tRB  
RY/BY#  
tVCS  
VCC  
NOTES:  
1.PA=Program Address, PD=Program Data, DOUT is the true data the program address  
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Figure 6. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART  
START  
Write Data AAH Address 555H  
Write Data 55H Address 2AAH  
Write Data A0H Address 555H  
Write Program Data/Address  
Data Poll  
Increment  
Address  
from system  
No  
No  
Verify Word Ok ?  
YES  
Last Address ?  
YES  
Auto Program Completed  
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Figure 7. CE# CONTROLLED PROGRAM TIMING WAVEFORM  
PA for program  
555 for program  
2AA for erase  
SA for sector erase  
555 for chip erase  
Data# Polling  
Address  
PA  
tWC  
tWH  
tAS  
tAH  
WE#  
OE#  
tGHEL  
tCP  
tWHWH1 or 2  
CE#  
Data  
tWS  
tDS  
tCPH  
tBUSY  
tDH  
DOUT  
Q7  
PD for program  
30 for sector erase  
10 for chip erase  
A0 for program  
55 for erase  
tRH  
RESET#  
RY/BY#  
NOTES:  
1.PA=Program Address, PD=Program Data, DOUT=Data Out, Q7=complement of data written to device.  
2.Figure indicates the last two bus cycles of the command sequence.  
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AUTOMATIC CHIP ERASE TIMING WAVEFORM  
All data in chip are erased. External erase verification is  
not required because data is verified automatically by  
internal control circuit. Erasure completion can be veri-  
fied by Data# Polling and toggle bit checking after auto-  
matic erase starts. Device outputs 0 during erasure  
and 1 after erasure on Q7.(Q6 is for toggle bit;see toggle  
bit, Data# Polling, timing waveform)  
Figure 8. AUTOMATIC CHIP ERASE TIMING WAVEFORM  
Erase Command Sequence(last two cycle)  
Read Status Data  
VA  
tWC  
tAS  
VA  
2AAh  
555h  
Address  
CE#  
tAH  
tCH  
tGHWL  
OE#  
WE#  
tWHWH2  
tWP  
tCS  
tWPH  
tDS tDH  
In  
Progress  
55h  
10h  
Complete  
Data  
tBUSY  
tRB  
RY/BY#  
tVCS  
VCC  
NOTES:  
SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").  
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Figure 9. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART  
START  
Write Data AAH Address 555H  
Write Data 55H Address 2AAH  
Write Data 80H Address 555H  
Write Data AAH Address 555H  
Write Data 55H Address 2AAH  
Write Data 10H Address 555H  
Data Pall from System  
NO  
Data=FFh ?  
YES  
Auto Chip Erase Completed  
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AUTOMATIC SECTOR ERASE TIMING WAVEFORM  
Sector indicated by A12 to A17 are erased. External  
erase verify is not required because data are verified  
automatically by internal control circuit. Erasure comple-  
tion can be verified by Data# Polling and toggle bit check-  
ing after automatic erase starts. Device outputs 0 dur-  
ing erasure and 1 after erasure on Q7.(Q6 is for toggle  
bit; see toggle bit, Data# Polling, timing waveform)  
Figure 10. AUTOMATIC SECTOR ERASE TIMING WAVEFORM  
Erase Command Sequence(last two cycle)  
Read Status Data  
VA  
tWC  
tAS  
Sector  
Sector  
Sector  
VA  
2AAh  
Address  
CE#  
Address 0  
Address 1  
Address n  
tAH  
tCH  
tGHWL  
OE#  
WE#  
tWHWH2  
tBAL  
tWP  
tCS  
tWPH  
tDS tDH  
In  
Progress  
55h  
30h  
30h  
30h  
Complete  
Data  
tBUSY  
tRB  
RY/BY#  
tVCS  
VCC  
NOTES:  
SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").  
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Figure 11. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART  
START  
Write Data AAH Address 555H  
Write Data 55H Address 2AAH  
Write Data 80H Address 555H  
Write Data AAH Address 555H  
Write Data 55H Address 2AAH  
Write Data 30H Sector Address  
NO  
Last Sector  
to Erase  
YES  
Data Poll from System  
NO  
Data=FFh  
YES  
Auto Sector Erase Completed  
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Figure 12. ERASE SUSPEND/ERASE RESUME FLOWCHART  
START  
Write Data B0H  
ERASE SUSPEND  
NO  
Toggle Bit checking Q6  
not toggled  
YES  
Read Array or  
Program  
Reading or  
NO  
Programming End  
YES  
Write Data 30H  
Delay 10ms (note)  
Continue Erase  
ERASE RESUME  
Another  
NO  
Erase Suspend ?  
YES  
Note: If the system implements an endless erase suspend/resume loop, or the number of erase suspend/resume is  
exceeded 1024 times, then the 10ms time delay must be put into consideration.  
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Figure 13. IN-SYSTEM SECTOR PROTECT/UNPROTECT TIMING WAVEFORM (RESET# Control)  
VID  
VIH  
RESET#  
SA, A6  
A1, A0  
Valid*  
Valid*  
Valid*  
Sector Protect or Sector Unprotect  
Verify  
40h  
Status  
Data  
60h  
60h  
Sector Protect =150us  
Sector Unprotect =15ms  
1us  
CE#  
WE#  
OE#  
Note: When sector protect, A6=0, A1=1, A0=0. When sector unprotect, A6=1, A1=1, A0=0.  
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Figure 14. IN-SYSTEM SECTOR PROTECTION ALGORITHM WITH RESET#=VID  
START  
PLSCNT=1  
RESET#=VID  
Wait 1us  
No  
Temporary Sector  
Unprotect Mode  
First Write  
Cycle=60H  
Yes  
Set up sector address  
Write 60H to sector address  
with A6=0, A1=1, A0=0  
Wait 150us  
Verify sector protect :  
write 40H with A6=0,  
A1=1, A0=0  
Increment PLSCNT  
Reset PLSCNT=1  
Read from sector address  
No  
No  
PLSCNT=25?  
Data=01H ?  
Yes  
Yes  
Device failed  
Yes  
Protect another  
sector?  
No  
Remove VID from RESET#  
Write reset command  
Sector protect complete  
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Figure 15. SECTOR PROTECT TIMING WAVEFORM (A9, OE# Control)  
A1  
A6  
12V  
3V  
A9  
tVLHT  
tVLHT  
Verify  
12V  
3V  
OE#  
tVLHT  
tWPP 1  
WE#  
CE#  
tOESP  
Data  
01H  
F0H  
tOE  
Sector Address  
A18-A12  
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Figure 16. SECTOR PROTECTION ALGORITHM (A9, OE# Control)  
START  
Set Up Sector Addr  
PLSCNT=1  
OE#=VID, A9=VID, CE#=VIL  
A6=VIL  
Activate WE# Pulse  
Time Out 150us  
Set WE#=VIH, CE#=OE#=VIL  
A9 should remain VID  
Read from Sector  
Addr=SA, A1=1  
No  
No  
Data=01H?  
PLSCNT=32?  
Yes  
Device Failed  
Yes  
Protect Another  
Sector?  
Remove VID from A9  
Write Reset Command  
Sector Protection  
Complete  
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Figure 17. IN-SYSTEM SECTOR UNPROTECTION ALGORITHM WITH RESET#=VID  
START  
PLSCNT=1  
RESET#=VID  
Wait 1us  
No  
No  
Temporary Sector  
Unprotect Mode  
First Write  
Cycle=60H ?  
Yes  
All sector  
Protect all sectors  
protected?  
Yes  
Set up first sector address  
Chip unprotect :  
write 60H with  
A6=1, A1=1, A0=0  
Wait 50ms  
Verify chip unprotect  
write 40H to sector address  
with A6=1, A1=1, A0=0  
Increment PLSCNT  
Read from sector address  
with A6=1, A1=1, A0=0  
No  
No  
Set up next sector address  
PLSCNT=1000?  
Data=00H ?  
Yes  
Yes  
Device failed  
Yes  
Last sector  
verified?  
No  
Remove VID from RESET#  
Write reset command  
Chip unprotect complete  
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Figure 18. TIMING WAVEFORM FOR CHIP UNPROTECTION (A9, OE# Control)  
A1  
12V  
3V  
A9  
A6  
tVLHT  
Verify  
12V  
3V  
OE#  
tVLHT  
tVLHT  
tWPP 2  
WE#  
CE#  
tOESP  
Data  
00H  
F0H  
tOE  
A18-A12  
Sector Address  
Notes: tWPP1 (Write pulse width for sector protect)=100ns min, 10us(typ.).  
tWPP2 (Write pulse width for sector unprotect)=100ns min, 12ms(typ).  
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Figure 19. CHIP UNPROTECTION ALGORITHM (A9, OE# Control)  
START  
Protect All Sectors  
PLSCNT=1  
Set OE#=A9=VID  
CE#=VIL, A6=1  
Activate WE# Pulse  
Time Out 50ms  
Increment  
PLSCNT  
Set OE#=CE#=VIL  
A9=VID,A1=1  
Set Up First Sector Addr  
Read Data from Device  
No  
No  
Data=00H?  
Yes  
PLSCNT=1000?  
Increment  
Sector Addr  
Yes  
Device Failed  
No  
All sectors have  
been verified?  
Yes  
Remove VID from A9  
Write Reset Command  
Chip Unprotect  
Complete  
* It is recommended before unprotect whole chip, all sectors should be protected in advance.  
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WRITE OPERATION STATUS  
Figure 20. DATA# POLLING ALGORITHM  
Start  
Read Q7~Q0  
Add.=VA(1)  
Yes  
Q7 = Data ?  
No  
No  
Q5 = 1 ?  
Yes  
Read Q7~Q0  
Add.=VA  
Yes  
Q7 = Data ?  
(2)  
No  
FAIL  
Pass  
NOTE : 1.VA=Valid address for programming  
2.Q7 should be re-checked even Q5="1" because Q7 may change  
simultaneously with Q5.  
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Figure 21. TOGGLE BIT ALGORITHM  
Start  
Read Q7-Q0  
Read Q7-Q0  
(Note 1)  
NO  
Toggle Bit Q6 =  
Toggle ?  
YES  
NO  
Q5= 1?  
YES  
Read Q7~Q0 Twice  
(Note 1,2)  
NO  
Toggle bit Q6=  
Toggle?  
YES  
Program/Erase Operation  
Not Complete,Write  
Reset Command  
Program/Erase  
operation Complete  
Note:1.Read toggle bit twice to determine whether or not it is toggling.  
2. Recheck toggle bit because it may stop toggling as Q5 change to "1".  
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MX29LV002C/002NC T/B  
Figure 22. DATA# POLLING TIMINGS (DURING AUTOMATIC ALGORITHMS)  
tRC  
VA  
VA  
VA  
Address  
CE#  
tACC  
tCE  
tCH  
tOE  
OE#  
WE#  
tOEH  
tDF  
tOH  
High Z  
High Z  
Complement  
Status Data  
Complement  
Status Data  
True  
True  
Valid Data  
Valid Data  
Q7  
Q0-Q6  
tBUSY  
RY/BY#  
NOTES:  
1. VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data read cycle.  
2. CE# must be toggled when DATA# polling.  
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MX29LV002C/002NC T/B  
Figure 23. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)  
tRC  
VA  
VA  
tACC  
tCE  
VA  
VA  
Address  
CE#  
tCH  
tOE  
OE#  
tDF  
tOEH  
WE#  
tOH  
High Z  
Valid Status  
(second read)  
Valid Status  
(first raed)  
Valid Data  
Valid Data  
Q6/Q2  
(stops toggling)  
tBUSY  
RY/BY#  
NOTES:  
1. VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle,  
and array data read cycle.  
2. CE# must be toggled when toggle bit toggling.  
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MX29LV002C/002NC T/B  
Table 13. AC CHARACTERISTICS (for 32-pin TSOP package type)  
Parameter Std Description  
Test Setup All Speed Options Unit  
tREADY1  
RESET# PIN Low (During Automatic Algorithms)  
MAX  
20  
us  
to Read or Write (See Note)  
tREADY2  
RESET# PIN Low (NOT During Automatic  
Algorithms) to Read or Write (See Note)  
RESET# Pulse Width (During Automatic Algorithms)  
RESET# HighTime Before Read (See Note)  
RY/BY# Recovery Time(to CE#, OE# go low)  
MAX  
500  
ns  
tRP  
tRH  
tRB  
MIN  
MIN  
MIN  
500  
50  
0
ns  
ns  
ns  
Note:Not 100% tested  
Figure 24. RESET# TIMING WAVEFORM (for 32-pin TSOP package type)  
RY/BY#  
CE#, OE#  
tRH  
RESET#  
tRP  
tReady2  
Reset Timing NOT during Automatic Algorithms  
tReady1  
RY/BY#  
tRB  
CE#, OE#  
RESET#  
tRP  
Reset Timing during Automatic Algorithms  
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MX29LV002C/002NC T/B  
Table 14. TEMPORARY SECTOR UNPROTECT  
Parameter Std. Description  
Test Setup All Speed Options Unit  
tVIDR  
tRSP  
VID Rise and Fall Time (See Note)  
RESET# SetupTime forTemporary Sector Unprotect  
Min  
Min  
500  
4
ns  
us  
Note:  
Not 100% tested  
Figure 25. TEMPORARY SECTOR UNPROTECT TIMING DIAGRAM  
12V  
RESET#  
0 or Vcc  
0 or Vcc  
Program or Erase Command Sequence  
tVIDR  
tVIDR  
CE#  
WE#  
tRSP  
RY/BY#  
Figure 26. Q6 vs Q2 for Erase and Erase Suspend Operations  
Enter Embedded  
Erasing  
Erase  
Enter Erase  
Erase  
Suspend  
Suspend Program  
Resume  
Erase  
Erase  
Erase Suspend  
Read  
Erase  
Erase  
Complete  
WE#  
Q6  
Suspend  
Program  
Q2  
NOTES:  
The system can use OE# or CE# to toggle Q2/Q6, Q2 toggles only when read at an address within an erase-suspended  
P/N:PM1204  
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MX29LV002C/002NC T/B  
Figure 27. TEMPORARY SECTOR UNPROTECT ALGORITHM  
Start  
RESET# = VID (Note 1)  
Perform Erase or Program Operation  
Operation Completed  
RESET# = VIH  
Temporary Sector Unprotect Completed(Note 2)  
Note : 1. All protected sectors are temporary unprotected.  
VID=11.5V~12.5V  
2. All previously protected sectors are protected again.  
P/N:PM1204  
REV. 1.0, JUN. 30, 2005  
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MX29LV002C/002NC T/B  
Figure 28. ID CODE READ TIMING WAVEFORM  
VCC  
3V  
VID  
VIH  
VIL  
ADD  
A9  
VIH  
VIL  
ADD  
A0  
tACC  
tACC  
VIH  
VIL  
A1  
ADD  
A2-A8  
VIH  
A10-A18 VIL  
CE#  
VIH  
VIL  
VIH  
VIL  
tCE  
WE#  
OE#  
tOE  
VIH  
VIL  
tDF  
tOH  
tOH  
VIH  
VIL  
DATA  
Q0-Q7  
DATA OUT  
C2H  
DATA OUT  
B5H/B6H  
P/N:PM1204  
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MX29LV002C/002NC T/B  
RECOMMENDED OPERATING CONDITIONS  
At Device Power-Up  
AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up.  
If the timing in the figure is ignored, the device may not operate correctly.  
VCC(min)  
VCC  
GND  
tVR  
tACC  
tR or tF  
tR or tF  
VIH  
VIL  
Valid  
ADDRESS  
CE#  
Address  
tF  
tCE  
tR  
VIH  
VIL  
VIH  
VIL  
WE#  
tF  
tOE  
tR  
VIH  
VIL  
OE#  
VIH  
VIL  
WP#/ACC  
DATA  
VOH  
VOL  
High Z  
Valid  
Ouput  
Figure A. ACTiming at Device Power-Up  
Notes  
Symbol  
Parameter  
Min.  
Max.  
Unit  
us/V  
us/V  
us/V  
tVR  
tR  
VCC RiseTime  
1
20  
500000  
20  
Inptut Signal Rise Time  
Inptut Signal Fall Time  
1,2  
1,2  
tF  
20  
Notes :  
1. Sampled, not 100% tested.  
2. This specification is applied for not only the device power-up but also the normal operations.  
P/N:PM1204  
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MX29LV002C/002NC T/B  
Table 15. ERASE AND PROGRAMMING PERFORMANCE(1)  
LIMITS  
PARAMETER  
MIN.  
TYP.(2)  
MAX.(3)  
15  
UNIT  
sec  
Sector Erase Time  
Chip Erase Time  
0.7  
4
32  
sec  
Byte Programming Time  
Chip Programming Time  
Erase/Program Cycles  
9
300  
us  
4.5  
13.5  
sec  
100,000  
Cycles  
Note: 1.Not 100% Tested, Excludes external system level over head.  
2.Typical values measured at 25° C, 3V.  
3.Maximum values measured at 25° C, 2.7V.  
Table 16. LATCH-UP CHARACTERISTICS  
MIN.  
-1.0V  
MAX.  
Input Voltage with respect to GND on all pins except I/O pins  
Input Voltage with respect to GND on all I/O pins  
Current  
12.5V  
Vcc + 1.0V  
+100mA  
-1.0V  
-100mA  
Includes all pins except Vcc. Test conditions: Vcc = 3.0V, one pin at a time.  
Table 17. DATA RETENTION  
Parameter Description  
Test Conditions  
150°C  
Min  
10  
Unit  
Years  
Years  
Data Retention Time  
125°C  
20  
P/N:PM1204  
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MX29LV002C/002NC T/B  
described inTable 18.  
QUERY COMMAND AND COMMON FLASH  
The single cycle Query command is valid only when the  
device is in the Read mode, including Erase Suspend,  
Standby mode, and Read ID mode;however, it is ignored  
otherwise.  
INTERFACE (CFI) MODE ( for MX29LV002CT/  
CB)  
MX29LV002CT/CB is capable of operating in the CFI  
mode. This mode all the host system to determine the  
manufacturer of the device such as operating param-  
eters and configuration.Two commands are required in  
CFI mode. Query command of CFI mode is placed first,  
then the Reset command exits CFI mode. These are  
The Reset command exits from the CFI mode to the  
Read mode, or Erase Suspend mode, or read ID mode.  
The command is valid only when the device is in the CFI  
mode.  
TABLE 18-1. CFI mode: Identification Data Values  
(All values in these tables are in hexadecimal)  
Description  
Address  
20  
Data  
0051  
0052  
0059  
0002  
0000  
0040  
0000  
0000  
0000  
0000  
0000  
Query-unique ASCII string "QRY"  
22  
24  
Primary vendor command set and control interface ID code  
Address for primary algorithm extended query table  
26  
28  
2A  
2C  
2E  
30  
Alternate vendor command set and control interface ID code (none)  
Address for secondary algorithm extended query table (none)  
32  
34  
TABLE 18-2. CFI Mode: System Interface Data Values  
(All values in these tables are in hexadecimal)  
Description  
Address  
36  
Data  
0027  
0036  
0000  
0000  
0004  
0000  
000A  
0000  
0005  
0000  
0004  
0000  
VCC supply, minimum (2.7V)  
VCC supply, maximum (3.6V)  
38  
VPP supply, minimum (none)  
3A  
3C  
3E  
40  
VPP supply, maximum (none)  
Typical timeout for single word/byte write (2N us)  
Typical timeout for Minimum size buffer write (2N us)  
Typical timeout for individual block erase (2N ms)  
Typical timeout for full chip erase (2N ms)  
Maximum timeout for single word/byte write times (2N X Typ)  
Maximum timeout for buffer write times (2N X Typ)  
Maximum timeout for individual block erase times (2N X Typ)  
Maximum timeout for full chip erase times (not supported)  
42  
44  
46  
48  
4A  
4C  
P/N:PM1204  
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MX29LV002C/002NC T/B  
TABLE 18-3. CFI Mode: Device Geometry Data Values  
(All values in these tables are in hexadecimal)  
Description  
Address  
4E  
50  
Data  
0012  
0000  
0000  
0000  
0000  
0004  
0000  
0000  
0040  
0000  
0001  
0000  
0020  
0000  
0000  
0000  
0080  
0000  
0002  
0000  
0000  
0001  
Device size (2N bytes)  
Flash device interface code (refer to the CFI publication 100)  
52  
54  
56  
58  
5A  
5C  
5E  
60  
62  
64  
66  
68  
6A  
6C  
6E  
70  
72  
74  
76  
78  
Maximum number of bytes in multi-byte write (not supported)  
Number of erase block regions  
Erase block region 1 information (refer to the CFI publication 100)  
Erase block region 2 information  
Erase block region 3 information  
Erase block region 4 information  
TABLE 18-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values  
(All values in these tables are in hexadecimal)  
Description  
Address  
80  
Data  
0050  
0052  
0049  
0031  
0030  
0000  
0002  
0001  
0001  
0004  
0000  
0000  
0000  
Query-unique ASCII string "PRI"  
82  
84  
Major version number, ASCII  
86  
Minor version number, ASCII  
88  
Address sensitive unlock (0=required, 1= not required)  
Erase suspend (2= to read and write)  
Sector protect (N= # of sectors/group)  
Temporarysectorunprotected(1=supported)  
Sectorprotect/unprotectedscheme  
SimultaneousR/Woperation(0=notsupported)  
Burst mode type (0=not supported)  
Page mode type (0=not supported)  
8A  
8C  
8E  
90  
92  
94  
96  
98  
P/N:PM1204  
REV. 1.0, JUN. 30, 2005  
51  
MX29LV002C/002NC T/B  
ORDERING INFORMATION  
PART NO.  
AccessTime Operating Current Standby Current  
PACKAGE  
Remark  
(ns)  
70  
70  
90  
90  
70  
70  
90  
90  
70  
70  
70  
70  
70  
70  
70  
70  
70  
90  
70  
90  
70  
90  
70  
90  
70  
90  
70  
90  
70  
90  
70  
90  
MAX. (mA)  
30  
MAX. (uA)  
MX29LV002CTTC-70  
MX29LV002CBTC-70  
MX29LV002CTTC-90  
MX29LV002CBTC-90  
MX29LV002CTTI-70  
MX29LV002CBTI-70  
MX29LV002CTTI-90  
MX29LV002CBTI-90  
MX29LV002CTQC-70  
MX29LV002CBQC-70  
MX29LV002CTQC-90  
MX29LV002CBQC-90  
MX29LV002CTQI-70  
MX29LV002CBQI-70  
MX29LV002CTQI-90  
MX29LV002CBQI-90  
MX29LV002CTTC-70G  
MX29LV002CTTC-90G  
MX29LV002CBTC-70G  
MX29LV002CBTC-90G  
MX29LV002CTTI-70G  
MX29LV002CTTI-90G  
MX29LV002CBTI-70G  
MX29LV002CBTI-90G  
MX29LV002CTQC-70G  
MX29LV002CTQC-90G  
MX29LV002CBQC-70G  
MX29LV002CBQC-90G  
MX29LV002CTQI-70G  
MX29LV002CTQI-90G  
MX29LV002CBQI-70G  
MX29LV002CBQI-90G  
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
32 Pin TSOP  
32 Pin TSOP  
32 Pin TSOP  
32 Pin TSOP  
32 Pin TSOP  
32 Pin TSOP  
32 Pin TSOP  
32 Pin TSOP  
32 Pin PLCC  
32 Pin PLCC  
32 Pin PLCC  
32 Pin PLCC  
32 Pin PLCC  
32 Pin PLCC  
32 Pin PLCC  
32 Pin PLCC  
32 Pin TSOP  
32 Pin TSOP  
32 Pin TSOP  
32 Pin TSOP  
32 Pin TSOP  
32 Pin TSOP  
32 Pin TSOP  
32 Pin TSOP  
32 Pin PLCC  
32 Pin PLCC  
32 Pin PLCC  
32 Pin PLCC  
32 Pin PLCC  
32 Pin PLCC  
32 Pin PLCC  
32 Pin PLCC  
30  
30  
30  
30  
30  
30  
30  
30  
30  
30  
30  
30  
30  
30  
30  
30  
PB free  
PB free  
PB free  
PB free  
PB free  
PB free  
PB free  
PB free  
PB free  
PB free  
PB free  
PB free  
PB free  
PB free  
PB free  
PB free  
30  
30  
30  
30  
30  
30  
30  
30  
30  
30  
30  
30  
30  
30  
30  
P/N:PM1204  
REV. 1.0, JUN. 30, 2005  
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MX29LV002C/002NC T/B  
PART NO.  
AccessTime Operating Current Standby Current  
PACKAGE  
Remark  
(ns)  
70  
70  
90  
90  
70  
70  
90  
90  
70  
70  
70  
70  
70  
70  
70  
70  
70  
90  
70  
90  
70  
90  
70  
90  
70  
90  
70  
90  
70  
90  
70  
90  
MAX. (mA)  
30  
MAX. (uA)  
MX29LV002NCTTC-70  
MX29LV002NCBTC-70  
MX29LV002NCTTC-90  
MX29LV002NCBTC-90  
MX29LV002NCTTI-70  
MX29LV002NCBTI-70  
MX29LV002NCTTI-90  
MX29LV002NCBTI-90  
MX29LV002NCTQC-70  
MX29LV002NCBQC-70  
MX29LV002NCTQC-90  
MX29LV002NCBQC-90  
MX29LV002NCTQI-70  
MX29LV002NCBQI-70  
MX29LV002NCTQI-90  
MX29LV002NCBQI-90  
MX29LV002NCTTC-70G  
MX29LV002NCTTC-90G  
MX29LV002NCBTC-70G  
MX29LV002NCBTC-90G  
MX29LV002NCTTI-70G  
MX29LV002NCTTI-90G  
MX29LV002NCBTI-70G  
MX29LV002NCBTI-90G  
MX29LV002NCTQC-70G  
MX29LV002NCTQC-90G  
MX29LV002NCBQC-70G  
MX29LV002NCBQC-90G  
MX29LV002NCTQI-70G  
MX29LV002NCTQI-90G  
MX29LV002NCBQI-70G  
MX29LV002NCBQI-90G  
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
32 Pin TSOP  
32 Pin TSOP  
32 Pin TSOP  
32 Pin TSOP  
32 Pin TSOP  
32 Pin TSOP  
32 Pin TSOP  
32 Pin TSOP  
32 Pin PLCC  
32 Pin PLCC  
32 Pin PLCC  
32 Pin PLCC  
32 Pin PLCC  
32 Pin PLCC  
32 Pin PLCC  
32 Pin PLCC  
32 Pin TSOP  
32 Pin TSOP  
32 Pin TSOP  
32 Pin TSOP  
32 Pin TSOP  
32 Pin TSOP  
32 Pin TSOP  
32 Pin TSOP  
32 Pin PLCC  
32 Pin PLCC  
32 Pin PLCC  
32 Pin PLCC  
32 Pin PLCC  
32 Pin PLCC  
32 Pin PLCC  
32 Pin PLCC  
30  
30  
30  
30  
30  
30  
30  
30  
30  
30  
30  
30  
30  
30  
30  
30  
PB free  
PB free  
PB free  
PB free  
PB free  
PB free  
PB free  
PB free  
PB free  
PB free  
PB free  
PB free  
PB free  
PB free  
PB free  
PB free  
30  
30  
30  
30  
30  
30  
30  
30  
30  
30  
30  
30  
30  
30  
30  
P/N:PM1204  
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53  
MX29LV002C/002NC T/B  
PART NAME DESCRIPTION  
MX 29 LV 002/002N C T T C 70 G  
OPTION:  
G: Lead-free package  
R: Restricted VCC (3.0V~3.6V)  
Q: Restricted VCC (3.0V~3.6V) with Lead-free package  
SPEED:  
70: 70ns  
90: 90ns  
TEMPERATURE RANGE:  
C: Commercial (0˚C to 70˚C)  
I: Industrial (-40˚C to 85˚C)  
PACKAGE:  
Q: PLCC  
T: TSOP  
BOOT BLOCK TYPE:  
T: Top Boot  
B: Bottom Boot  
REVISION:  
C
DENSITY & MODE:  
002: 2M, x8 Boot Block  
002N: 2M, x8 Boot Block, RESET PIN DISABLE  
TYPE:  
L, LV: 3V  
DEVICE:  
29:Flash  
P/N:PM1204  
REV. 1.0, JUN. 30, 2005  
54  
MX29LV002C/002NC T/B  
PACKAGE INFORMATION  
P/N:PM1204  
REV. 1.0, JUN. 30, 2005  
55  
MX29LV002C/002NC T/B  
P/N:PM1204  
REV. 1.0, JUN. 30, 2005  
56  
MX29LV002C/002NC T/B  
REVISION HISTORY  
Revision No. Description  
Page  
P1  
Date  
JUN/30/2005  
1.0  
1. Removed "Preliminary"  
2. Added "Recommended Operating Conditions"  
P48  
P/N:PM1204  
REV. 1.0, JUN. 30, 2005  
57  
MX29LV002C/002NC T/B  
MACRONIX INTERNATIONALCO., LTD.  
Headquarters:  
TEL:+886-3-578-6688  
FAX:+886-3-563-2888  
Europe Office :  
TEL:+32-2-456-8020  
FAX:+32-2-456-8021  
Hong Kong Office :  
TEL:+86-755-834-335-79  
FAX:+86-755-834-380-78  
Japan Office :  
Kawasaki Office :  
TEL:+81-44-246-9100  
FAX:+81-44-246-9105  
Osaka Office :  
TEL:+81-6-4807-5460  
FAX:+81-6-4807-5461  
Singapore Office :  
TEL:+65-6346-5505  
FAX:+65-6348-8096  
Taipei Office :  
TEL:+886-2-2509-3300  
FAX:+886-2-2509-2200  
MACRONIX AMERICA, INC.  
TEL:+1-408-262-8887  
FAX:+1-408-262-8810  
http : //www.macronix.com  
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.  

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