MX29LV017BTI-90 [Macronix]
16M-BIT [2Mx8] CMOS SINGLE VOLTAGE 3V ONLY FLASH MEMORY; 16M - BIT [ 2Mx8 ] CMOS单电压3V仅限于Flash存储器
| 型号： | MX29LV017BTI-90 |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | 16M-BIT [2Mx8] CMOS SINGLE VOLTAGE 3V ONLY FLASH MEMORY |
| 文件： | 总55页 (文件大小：340K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MX29LV017B
16M-BIT[2Mx8]CMOSSINGLEVOLTAGE
3VONLYFLASHMEMORY
FEATURES
• Status Reply
• Extended single - supply voltage range 2.7V to 3.6V
• 2,097,152 x 8
- Data# Polling & Toggle bit for detection of program
anderaseoperationcompletion.
• Singlepowersupplyoperation
• Ready/Busy# pin (RY/BY#)
- 3.0V only operation for read, erase and program
operation
-Providesahardwaremethodofdetectingprogramor
eraseoperationcompletion.
• Fast access time: 70/90ns
• Sectorprotection
• Fully compatible with MX29LV017A decice
• Lowpowerconsumption
- Hardware method to disable any combination of
sectors from program or erase operations
-Temporarysectorunprotectallowscodechangesin
previously locked sectors.
- 30mA maximum active current
- 0.2uA typical standby current
• Commandregisterarchitecture
- Byte Programming (9us typical)
- Sector Erase (Sector structure 64K-Byte x32)
• Auto Erase (chip & sector) and Auto Program
-Automaticallyeraseanycombinationofsectorswith
Erase Suspend capability.
• CFI (Common Flash Interface) compliant
- Flash device parameters stored on the device and
provide the host system to access
• 100,000minimumerase/programcycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Low VCC write inhibit is equal to or less than 1.4V
• Package type:
- Automatically program and verify data at specified
address
- 40-pin TSOP
• Erasesuspend/EraseResume
- Suspends sector erase operation to read data from,
orprogramdatato,any sectorthatisnotbeingerased,
then resumes the erase.
• Compatibility with JEDEC standard
- Pinout and software compatible with single-power
supply Flash
GENERAL DESCRIPTION
The MX29LV017B is a 16-mega bit Flash memory orga-
nized as 2M bytes of 8 bits. MXIC's Flash memories
offer the most cost-effective and reliable read/write non-
volatile random access memory. The MX29LV017B is
packaged in 40-pin TSOP. It is designed to be repro-
grammed and erased in system or in standard EPROM
programmers.
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining maxi-
mum EPROM compatibility.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cy-
cling. The MX29LV017B uses a 2.7V~3.6VVCC supply
to perform the High Reliability Erase and auto Program/
Erase algorithms.
The standard MX29LV017B offers access time as fast
as 70ns, allowing operation of high-speed microproces-
sors without wait states. To eliminate bus contention,
the MX29LV017B has separate chip enable (CE#) and
output enable (OE#) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29LV017B uses a command register to manage this
functionality. The command register allows for 100%
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamperes on
address and data pin from -1V to VCC + 1V.
P/N:PM1086
REV. 1.1, DEC. 07, 2004
1
MX29LV017B
PIN CONFIGURATIONS
PIN DESCRIPTION
40 TSOP (Standard Type) (10mm x 20mm)
SYMBOL PIN NAME
A0~A20 Address Input
A16
A15
A14
A13
A12
A11
A9
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A17
GND
A20
A19
A10
Q7
2
Q0~Q7
CE#
Data Input/Output
Chip Enable Input
Write Enable Input
3
4
5
6
WE#
7
Q6
A8
8
Q5
RESET# Hardware Reset Pin/Sector Protect Unlock
OE# Output Enable Input
RY/BY# Ready/Busy Output
WE#
RESET#
NC
9
Q4
10
11
12
13
14
15
16
17
18
19
20
VCC
VCC
NC
MX29LV017B
RY/BY#
A18
A7
Q3
VCC
GND
Power Supply Pin (2.7V~3.6V)
Ground Pin
Q2
A6
Q1
A5
Q0
A4
OE#
GND
CE#
A0
A3
A2
A1
P/N:PM1086
REV. 1.1, DEC. 07, 2004
2
MX29LV017B
BLOCK STRUCTURE
Table 1: MX29LV017B SECTOR ARCHITECTURE
Sector
SA0
A20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A19
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A18
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A17
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A16
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Address Range (in hexadecimal)
000000-00FFFF
010000-01FFFF
020000-02FFFF
030000-03FFFF
040000-04FFFF
050000-05FFFF
060000-06FFFF
070000-07FFFF
080000-08FFFF
090000-09FFFF
0A0000-0AFFFF
0B0000-0BFFFF
0C0000-0CFFFF
0D0000-0DFFFF
0E0000-0EFFFF
0F0000-0FFFFF
100000-10FFFF
110000-11FFFF
120000-12FFFF
130000-13FFFF
140000-14FFFF
150000-15FFFF
160000-16FFFF
170000-17FFFF
180000-18FFFF
190000-19FFFF
1A0000-1AFFFF
1B0000-1BFFFF
1C0000-1CFFFF
1D0000-1DFFFF
1E0000-1EFFFF
1F0000-1FFFFF
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
P/N:PM1086
REV. 1.1, DEC. 07, 2004
3
MX29LV017B
BLOCK DIAGRAM
WRITE
STATE
CE#
OE#
WE#
CONTROL
INPUT
PROGRAM/ERASE
HIGH VOLTAGE
MACHINE
(WSM)
LOGIC
RESET#
STATE
REGISTER
ADDRESS
LATCH
FLASH
ARRAY
ARRAY
A0-A20
SOURCE
HV
AND
COMMAND
DATA
BUFFER
Y-PASS GATE
DECODER
PGM
DATA
HV
SENSE
AMPLIFIER
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
I/O BUFFER
Q0-Q7
P/N:PM1086
REV. 1.1, DEC. 07, 2004
4
MX29LV017B
dard microprocessor write timings. The device will auto-
matically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number
of sequences. A status bit toggling between consecu-
tive read cycles provides feedback to the user as to the
status of the erasing operation.
AUTOMATIC PROGRAMMING
The MX29LV017B is byte programmable using the Au-
tomatic Programming algorithm. The Automatic Pro-
gramming algorithm makes the external system do not
need to have time out sequence nor to verify the data
programmed. The typical chip programming time at room
temperature of the MX29LV017B is less than 18 sec-
onds.
Register contents serve as inputs to an internal state-
machine which controls the erase and programming cir-
cuitry. During write cycles, the command register inter-
nally latches address and data needed for the program-
ming and erase operations. During a system write cycle,
addresses are latched on the falling edge, and data are
latched on the rising edge of WE# or CE#, whichever
happens first.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm requires the
user to only write program set-up commands (including
2 unlock write cycle and A0H) and a program command
(program data and address). The device automatically
times the programming pulse width, provides the pro-
gram verification, and counts the number of sequences.
A status bit similar to Data# Polling and a status bit
toggling between consecutive read cycles, provide feed-
back to the user as to the status of the programming
operation. Refer to write operation status, Table 7, for
more information on these status bits.
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, reli-
ability, and cost effectiveness. The MX29LV017B elec-
trically erases all bits simultaneously using Fowler-
Nordheim tunneling. The bytes are programmed by us-
ing the EPROM programming mechanism of hot elec-
tron injection.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command regis-
ter to respond to its full command set.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at room temperature is accomplished in
less than 25 second. The Automatic Erase algorithm
automatically programs the entire array prior to electri-
cal erase. The timing and verification of electrical erase
are controlled internally within the device.
AUTOMATIC SELECT
AUTOMATIC SECTOR ERASE
The automatic select mode provides manufacturer and
device identification, and sector protection verification,
through identifier codes output on Q7~Q0.This mode is
mainly adapted for programming equipment on the de-
vice to be programmed with its programming algorithm.
When programming by high voltage method, automatic
select mode requires VID (11.5V to 12.5V) on address
pin A9. Other address pin A6, A1 and A0 as referring to
Table 2.In addition, to access the automatic select codes
in-system, the host can issue the automatic select com-
mand through the command register without requiring
VID, as shown in Table 4.
The MX29LV017B is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. The Automatic Sector
Erase algorithm automatically programs the specified
sector(s) prior to electrical erase. The timing and verifi-
cation of electrical erase are controlled internally within
the device. An erase operation can erase one sector,
multiple sectors, or the entire device.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stan-
To verify whether or not sector being protected, the sec-
tor address must appear on the appropriate highest or-
P/N:PM1086
REV. 1.1, DEC. 07, 2004
5
MX29LV017B
der address bit (seeTable 1).The rest of address bits, as
shown inTable 2, are don't care.Once all necessary bits
have been set as required, the programming equipment
may read the corresponding identifier code on Q7~Q0.
TABLE 2. MX29LV017B AUTOMATIC SELECT MODE BUS OPERATION (A9=VID)
A20 A15 A9 A8 A6 A5 A1 A0
Description
CE# OE# WE# RE-
|
|
|
A7
X
|
A2
X
Q7~Q0
C2H
SET# A16 A10
Read Silicon ID
Manufacturer Code
Read Silicon ID
(Device Code)
L
L
L
L
H
H
H
H
X
X
X
X
VID
VID
L
L
L
L
L
X
X
X
X
H
C8H
01H
Sector Protection
Verification
L
L
H
H
SA
X
VID
L
H
L
(protected)
00H
(unprotected)
Note : SA=Sector Address, X=Don't Care, L=Logic Low, H=Logic High
P/N:PM1086
REV. 1.1, DEC. 07, 2004
6
MX29LV017B
The single cycle Query command is valid only when the
device is in the Read mode, including Erase Suspend,
Standby mode, and Automatic Select mode; however, it
is ignored otherwise.
QUERY COMMAND AND COMMON FLASH
INTERFACE(CFI) MODE
MX29LV017B is capable of operating in the CFI mode.
This mode all the host system to determine the manu-
facturer of the device such as operating parameters and
configuration.Two commands are required in CFI mode.
Query command of CFI mode is placed first, then the
Reset command exits CFI mode. These are described
in Table 3.
The Reset command exits from the CFI mode to the
Read mode, or Erase Suspend mode, or Automatic Se-
lect mode. The command is valid only when the device
is in the CFI mode.
Table 3-1. CFI mode: Identification Data Values
(All values in these tables are in hexadecimal)
Description
Address
10
Data
51
52
59
02
00
40
00
00
00
00
00
Query-unique ASCII string "QRY"
11
12
Primary vendor command set and control interface ID code
Address for primary algorithm extended query table
13
14
15
16
Alternate vendor command set and control interface ID code (none)
Address for secondary algorithm extended query table (none)
17
18
19
1A
Table 3-2. CFI Mode: System Interface Data Values
(All values in these tables are in hexadecimal)
Description
Address
1B
1C
1D
1E
1F
Data
27
36
00
00
04
00
0A
00
05
00
04
00
VCC supply, minimum (2.7V)
VCC supply, maximum (3.6V)
VPP supply, minimum (none)
VPP supply, maximum (none)
Typical timeout for single word/byte write (2N us)
Typical timeout for Minimum size buffer write (2N us) (not supported)
Typical timeout for individual sector erase (2N ms)
Typical timeout for full chip erase (2N ms)
Maximum timeout for single word/byte write times (2N X Typ)
Maximum timeout for buffer write times (2N X Typ)
Maximum timeout for individual sector erase times (2N X Typ)
Maximum timeout for full chip erase times (not supported)
20
21
22
23
24
25
26
P/N:PM1086
REV. 1.1, DEC. 07, 2004
7
MX29LV017B
Table 3-3. CFI Mode: Device Geometry Data Values
(All values in these tables are in hexadecimal)
Description
Device size (2N bytes)
Address
27
Data
15
00
00
00
00
01
1F
00
00
01
00
00
00
00
00
00
00
00
00
00
00
00
Flash device interface code (asynchronous x 8)
28
29
Maximum number of bytes in multi-byte write (not supported)
2A
2B
2C
2D
2E
2F
30
Number of erase sector regions
Erase sector region 1 information (refer to the CFI publication 100)
Erase sector region 2 information
Erase sector region 3 information
Erase sector region 4 information
31
32
33
34
35
36
37
38
39
3A
3B
3C
Table 3-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values
(All values in these tables are in hexadecimal)
Description
Address
40
Data
50
52
49
31
30
01
02
01
01
04
00
00
00
Query-unique ASCII string "PRI"
41
42
Major version number, ASCII
43
Minor version number, ASCII
44
Address sensitive unlock (0=required, 1= not required)
Erase suspend (2= to read and write)
Sector protect (N= # of sectors/group)
Temporarysectorunprotect(1=supported)
Sector protect/chip unprotect scheme
SimultaneousR/Woperation(0=notsupported)
Burst mode type (0=not supported)
Page mode type (0=not supported)
45
46
47
48
49
4A
4B
4C
P/N:PM1086
REV. 1.1, DEC. 07, 2004
8
MX29LV017B
in the improper sequence will reset the device to the
read mode. Table 4 defines the valid register command
sequences. Note that the Erase Suspend (B0H) and
Erase Resume (30H) commands are valid only while the
Sector Erase operation is in progress.
COMMAND DEFINITIONS
Device operations are selected by writing specific ad-
dress and data sequences into the command register.
Writing incorrect address and data values or writing them
TABLE 4. MX29LV017B COMMAND DEFINITIONS
First Bus
Bus Cycle
Cycle Addr Data Addr
Second Bus Third Bus
Fourth Bus
Cycle
Fifth Bus
Cycle
Sixth Bus
Cycle
Command
Cycle
Cycle
Data Addr
Data Addr Data Addr
Data Addr Data
Reset
1
1
4
4
XXXH F0H
RA RD
XXXH AAH XXXH 55H XXXH 90H ADI
Read
Read Silicon ID
Sector Protect
Verify
DDI
XXXH AAH XXXH 55H XXXH 90H (SA) 00H
x02H 01H
Byte Program
Chip Erase
4
6
6
1
1
1
XXXH AAH XXXH 55H XXXH A0H PA
PD
XXXH AAH XXXH 55H XXXH 80H XXXH AAH XXXH 55H
XXXH 10H
SA 30H
Sector Erase
Sector Erase Suspend
Sector Erase Resume
CFI Query
XXXH AAH XXXH 55H XXXH 80H XXXH AAH XXXH 55H
XXXH B0H
XXXH 30H
XXXH 98
Notes:
1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacturer code,A1=0, A0 = 1 for device code. A2-A20=do
not care.
(Refer to table 2)
DDI = Data of Device identifier : C2H for manufacture code, C8H for device code.
X = X can be VIL or VIH
RA=Address of memory location to be read. RD=Data to be read at location RA.
2. PA = Address of memory location to be programmed.
PD = Data to be programmed at location PA.
SA = Address of the sector to be erased.
3. For Sector ProtectVerify operation:If read out data is 01H, it means the sector has been protected. If read out data
is 00H, it means the sector is still not being protected.
4. Any number of CFI data read cycles are permitted.
5. The reset command is required to return to the read mode when the device is in the automatic select mode or if Q5
goes high.
P/N:PM1086
REV. 1.1, DEC. 07, 2004
9
MX29LV017B
TABLE 5. MX29LV017B BUS OPERATION
ADDRESS
DESCRIPTION
CE# OE# WE# RESET# A20 A15 A9 A8 A6 A5 A1 A0 Q0~Q7
A16 A10
A7
AIN
AIN
X
A2
Read
L
L
L
H
X
X
H
H
L
H
Dout
DIN(3)
High Z
DIN
Write
H
Reset
X
X
L
X
X
H
X
L
L
VID
Temporary sector unlock
Output Disable
Standby
AIN
X
H
High Z
High Z
DIN
VCC±0.3V X
VCC±0.3V
VID
X
Sector Protect
Chip Unprotect
Sector Protection Verify
L
L
L
H
H
L
SA
X
X
X
X
X
X
X
L
H
L
X
X
X
H
H
H
L
L
L
VID
X
DIN
H
H
SA
VID
X
L CODE(5)
Notes :
1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 4.
2. VID is the high voltage, 11.5V to 12.5V.
3. Refer to Table 4 for valid Data-In during a write operation.
4. X can be VIL or VIH.
5. Code=00H means unprotected.
Code=01H means protected.
6. A20~A16=Sector address for sector protect.
7. The sector protect and chip unprotect functions may also be implemented via programming equipment.
P/N:PM1086
REV. 1.1, DEC. 07, 2004
10
MX29LV017B
Characteristics" section contains timing specification
table and timing diagrams for write operations.
REQUIREMENTS FOR READING ARRAY
DATA
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control
and gates array data to the output pins.WE# should remain
at VIH.
STANDBY MODE
When using both pins of CE# and RESET#, the device
enter CMOS Standby with both pins held atVCC± 0.3V.
If CE# and RESET# are held at VIH, but not within the
range ofVCC ±0.3V, the device will still be in the standby
mode, but the standby current will be larger.During Auto
Algorithm operation, VCC active current (ICC2) is re-
quired even CE# = "H" until the operation is completed.
The device can be read with standard access time (tCE)
from either of these standby modes, before it is ready to
read data.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content
occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid address on
the device address inputs produce valid data on the device
data outputs.The device remains enabled for read access
until the command register contents are altered.
OUTPUT DISABLE
With the OE# input at a logic high level (VIH), output
from the devices are disabled.This will cause the output
pins to be in a high impedance state.
WRITE COMMANDS/COMMAND SEQUENCES
To program data to the device or erase sectors of memory
, the system must drive WE# and CE# to VIL, and OE#
to VIH.
RESET# OPERATION
An erase operation can erase one sector, multiple sectors
, or the entire device.Table indicates the address space
that each sector occupies. A "sector address" consists
of the address bits required to uniquely select a sector.
The Writing specific address and data commands or
sequences into the command register initiates device
operations. Table 1 defines the valid register command
sequences.Writing incorrect address and data values or
writing them in the improper sequence resets the device
to reading array data. Section has details on erasing a
sector or the entire chip, or suspending/resuming the erase
operation.
The RESET# pin provides a hardware method of resetting
the device to reading array data.When the RESET# pin
is driven low for at least a period of tRP, the device
immediately terminates any operation in progress,
tristates all output pins, and ignores all read/write
commands for the duration of the RESET# pulse. The
device also resets the internal state machine to reading
array data.The operation that was interrupted should be
re-initiated once the device is ready to accept another
command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse.
When RESET# is held at GND±0.3V, the device draws
CMOS standby current (ICC4).If RESET# is held atVIL
but not within GND±0.3V, the standby current will be
greater.
After the system writes the "read silicon-ID" and "sector
protect verify" command sequence, the device enters
the "read silicon-ID" and "sector protect verify" mode.
The system can then read "read silicon-ID" and "sector
protect verify" codes from the internal register (which is
separate from the memory array) on Q7-Q0. Standard
read cycle timings apply in this mode. Refer to the "read
silicon-ID" and "sector protect verify" Mode and "read
silicon-ID" and "sector protect verify" Command
Sequence section for more information.
The RESET# pin may be tied to system reset circuitry.
A system reset would that also reset the Flash memory,
enabling the system to read the boot-up firmware from
the Flash memory.
If RESET# is asserted during a program or erase
operation, the RY/BY# pin remains a "0" (busy) until the
internal reset operation is complete, which requires a
ICC2 in the DC Characteristics table represents the active
current specification for the write mode. The "AC
P/N:PM1086
REV. 1.1, DEC. 07, 2004
11
MX29LV017B
time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is completed within a
time of tREADY (not during Embedded Algorithms).The
system can read data tRH after the RESET# pin returns
to VIH.
AUTOMATIC CHIP ERASE COMMANDS
Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command 80H. Two more "unlock" write cy-
cles are then followed by the chip erase command 10H.
The device does not require the system to entirely pre-
program prior to executing the Automatic Chip Erase.
Upon executing the Automatic Chip Erase, the device
will automatically program and verify the entire memory
for an all-zero data pattern. When the device is auto-
matically verified to contain an all-zero pattern, a self-
timed chip erase and verify begin. The erase and verify
operations are completed when the data on Q7 is "1" at
which time the device returns to the Read mode. The
system is not required to provide any control or timing
during these operations.
Refer to the AC Characteristics tables for RESET#
parameters and to Figure 22 for the timing diagram.
READ/RESET COMMAND
The read or reset operation is initiated by writing the
read/reset command sequence into the command reg-
ister. Microprocessor read cycles retrieve array data.
The device remains enabled for reads until the command
register contents are altered.
When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array
(no erase verification command is required).
If program-fail or erase-fail happen, the write of F0H will
reset the device to abort the operation. A valid com-
mand must then be written to place the device in the
desired state.
If the Erase operation was unsuccessful, the data on
Q5 is "1"(see Table 7), indicating the erase operation
exceed internal timing limit.
SILICON-ID READ COMMAND
The automatic erase begins on the rising edge of the
last WE# or CE# pulse, whichever happens first in the
command sequence and terminates when either the data
on Q7 is "1" at which time the device returns to the
Read mode or the data on Q6 stops toggling for two
consecutive read cycles at which time the device re-
turns to the Read mode.
Flash memories are intended for use in applications where
the local CPU alters memory contents. As such, manu-
facturer and device codes must be accessible while the
device resides in the target system. PROM program-
mers typically access signature codes by raising A9 to
a high voltage (VID). However, multiplexing high volt-
age onto address lines is not generally desired system
design practice.
The MX29LV017B contains a Silicon-ID-Read operation
to supple traditional PROM programming methodology.
The operation is initiated by writing the read silicon ID
command sequence into the command register. Fol-
lowing the command write, a read cycle with A1=VIL,
A0=VIL retrieves the manufacturer code of C2H. A read
cycle with A1=VIL, A0=VIH returns the device code of
C8H for MX29LV017B.
The system must write the reset command to exit the
"Silicon-ID Read Command".
P/N:PM1086
REV. 1.1, DEC. 07, 2004
12
MX29LV017B
TABLE 6. SILICON ID CODE
Pins
A0
A1
Q7
1
Q6
1
Q5
0
Q4
0
Q3
0
Q2
0
Q1
1
Q0
0
Code(Hex)
C2H
Manufacturer code
Device code
Sector Protection
Verification
VIL VIL
VIH VIL
VIL VIH
VIL VIH
1
1
0
0
1
0
0
0
C8H
0
0
0
0
0
0
0
1
01H (Protected)
00H(Unprotected)
0
0
0
0
0
0
0
0
READING ARRAY DATA
RESET COMMAND
The device is automatically set to reading array data
after device power-up.No commands are required to re-
trieve data.The device is also ready to read array data
after completing an Automatic Program or Automatic
Erase algorithm.
Writing the reset command to the device resets the de-
vice to reading array data.Address bits are don't care for
this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data.Once erasure begins, however, the device ignores
reset commands until the operation is complete.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The sys-
tem can read array data using the standard read tim-
ings, except that if it reads at an address within erase-
suspended sectors, the device outputs status data. Af-
ter completing a programming operation in the Erase
Suspend mode, the system may once again read array
data with the same exception.See Erase Suspend/Erase
Resume Commands” for more information on this mode.
The system must issue the reset command to re-en-
able the device for reading array data if Q5 goes high, or
while in the "read silicon-ID" and "sector protect verify"
mode. See the "Reset Command" section, next.
The reset command may be written between the se-
quence cycles in a program command sequence be-fore
programming begins. This resets the device to reading
array data (also applies to programming in Erase Sus-
pend mode). Once programming begins, however, the
device ignores reset commands until the operation is
complete.
The reset command may be written between the se-
quence cycles in an Automatic Select command se-
quence. Once in the Automatic Select mode, the reset
command must be written to return to reading array data
(also applies to Automatic Select during Erase Suspend).
If Q5 goes high during a program or erase operation, writ-
ing the reset command returns the device to read-ing
array data (also applies during Erase Suspend).
P/N:PM1086
REV. 1.1, DEC. 07, 2004
13
MX29LV017B
mand is issued during the sector erase operation, the
device requires a maximum 20us to suspend the sector
erase operation.However, when the Erase Suspend com-
mand is written during the sector erase time-out, the
device immediately terminates the time-out period and
suspends the erase operation. After this command has
been executed, the command register will initiate erase
suspend mode. The state machine will return to read
mode automatically after suspend is ready. At this time,
state machine only allows the command register to re-
spond to Erase Resume, program data to , or read data
from any sector not selected for erasure.
SECTOR ERASE COMMANDS
The device does not require the system to entirely pre-
program prior to executing the Automatic Sector Erase
Set-up command and Automatic Sector Erase com-
mand. Upon executing the Automatic Sector Erase com-
mand, the device will automatically program and verify
the sector(s) memory for an all-zero data pattern. The
system is not required to provide any control or timing
during these operations.
When the sector(s) is automatically verified to contain
an all-zero pattern, a self-timed sector erase and verify
begin. The erase and verify operations are complete
when either the data on Q7 is "1" at which time the de-
vice returns to the Read mode or the data on Q6 stops
toggling for two consecutive read cycles at which time
the device returns to the Read mode. The system is not
required to provide any control or timing during these
operations.
The system can determine the status of the program
operation using the Q7 or Q6 status bits, just as in the
standard program operation. After an erase-suspend pro-
gram operation is complete, the system can once again
read array data within non-suspended sectors.
ERASE RESUME
When using the Automatic Sector Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array
(no erase verification command is required). Sector
erase is a six-bus cycle operation. There are two "un-
lock" write cycles. These are followed by writing the
set-up command 80H. Two more "unlock" write cycles
are then followed by the sector erase command 30H.
The sector address is latched on the falling edge of WE#
or CE#, whichever happens later, while the command
(data) is latched on the rising edge of WE# or CE#, which-
ever happens first. Sector addresses selected are
loaded into internal register on the sixth falling edge of
WE# or CE#, whichever happens later. Each succes-
sive sector load cycle started by the falling edge of WE#
or CE#, whichever happens later must begin within 50us
from the rising edge of the preceding WE# or CE#, which-
ever happens first. Otherwise, the loading period ends
and internal auto sector erase cycle starts. (Monitor Q3
to determine if the sector erase timer window is still open,
see section Q3, Sector EraseTimer.) Any command other
than Sector Erase(30H) or Erase Suspend(B0H) during
the time-out period resets the device to read mode.
This command will cause the command register to clear
the suspend state and return back to Sector Erase mode
but only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
other conditions. Another Erase Suspend command can
be written after the device has resumed erasing.
BYTE PROGRAM COMMAND SEQUENCE
The device programs one byte of data for each program
operation. The command sequence requires four bus
cycles, and is initiated by writing two unlock write cycles,
followed by the program set-up command. The program
address and data are written next, which in turn initiate
the Embedded Program algorithm. The system is not
required to provide further controls or timings. The device
automatically generates the program pulses and verifies
the programmed cell margin. Table 4 shows the address
and data requirements for the byte program command
sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and
addresses are no longer latched. The system can
determine the status of the program operation by using
Q7, Q6, or RY/BY#. See "Write Operation Status" for
information on these status bits.
ERASE SUSPEND
This command only has meaning while the state ma-
chine is executing Automatic Sector Erase operation,
and therefore will only be responded during Automatic
Sector Erase operation. When the Erase Suspend Com-
Any commands written to the device during the Em-
P/N:PM1086
REV. 1.1, DEC. 07, 2004
14
MX29LV017B
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the programming
operation. The Byte Program command sequence should
be re-initiated once the device has reset to reading array
data, to ensure data integrity.
this, the device outputs the "complement," or "0". The
system must provide an address within any of the sec-
tors selected for erasure to read valid status information
on Q7.
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Data# Polling on
Q7 is active for approximately 100 us, then the device
returns to reading array data. If not all selected sectors
are protected, the Automatic Erase algorithm erases the
unprotected sectors, and ignores the selected sectors
that are protected.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed from a
"0" back to a "1". Attempting to do so may halt the
operation and set Q5 to "1", or cause the Data# Polling
algorithm to indicate the operation was successful.
However, a succeeding read will show that the data is
still "0". Only erase operations can convert a "0" to a
"1".
When the system detects Q7 has changed from the
complement to true data, it can read valid data at Q7-Q0
on the following read cycles. This is because Q7 may
change asynchronously with Q0-Q6 while Output En-
able (OE#) is asserted low.
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/
BY#.Table 7 and the following subsections describe the
functions of these bits.Q7, RY/BY#, and Q6 each offer a
method for determining whether a program or erase op-
eration is complete or in progress. These three bits are
discussed first.
RY/BY#:Ready/Busy
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Automatic Erase/Program algorithm
is in progress or complete. The RY/BY# status is valid
after the rising edge of the final WE# or CE#, whichever
happens first, in the command sequence.Since RY/BY#
is an open-drain output, several RY/BY# pins can be tied
together in parallel with a pull-up resistor toVCC.
Q7: Data# Polling
The Data# Polling bit, Q7, indicates to the host system
whether an Automatic Algorithm is in progress or com-
pleted, or whether the device is in Erase Suspend.Data#
Polling is valid after the rising edge of the finalWE# pulse
in the program or erase command sequence.
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the Erase
Suspend mode.) If the output is high (Ready), the de-
vice is ready to read array data (including during the
Erase Suspend mode), or is in the standby mode.
During the Automatic Program algorithm, the device out-
puts on Q7 the complement of the datum programmed
to Q7.This Q7 status also applies to programming dur-
ing Erase Suspend.When the Automatic Program algo-
rithm is complete, the device outputs the datum pro-
grammed to Q7.The system must provide the program
address to read valid status information on Q7. If a pro-
gram address falls within a protected sector, Data# Poll-
ing on Q7 is active for approximately 1 us, then the de-
vice returns to reading array data.
Table 7 shows the outputs for RY/BY# during write op-
eration.
Q6:Toggle BIT I
Toggle Bit I on Q6 indicates whether an Automatic Pro-
gram or Erase algorithm is in progress or complete, or
whether the device has entered the Erase Suspend mode.
Toggle Bit I may be read at any address, and is valid
after the rising edge of the final WE# or CE#, whichever
happens first, in the command sequence (prior to the
program or erase operation), and during the sector time-
out.
During the Automatic Erase algorithm, Data# Polling pro-
duces a "0" on Q7. When the Automatic Erase algo-
rithm is complete, or if the device enters the Erase Sus-
pend mode, Data# Polling produces a "1" on Q7.This is
analogous to the complement/true datum out-put de-
scribed for the Automatic Program algorithm: the erase
function changes all the bits in a sector to "1" prior to
P/N:PM1086
REV. 1.1, DEC. 07, 2004
15
MX29LV017B
During an Automatic Program or Erase algorithm opera-
tion, successive read cycles to any address cause Q6
to toggle. The system may use either OE# or CE# to
control the read cycles.When the operation is complete,
Q6 stops toggling.
are required for sectors and mode information. Refer to
Table 7 to compare outputs for Q2 and Q6.
Reading Toggle Bits Q6/ Q2
Whenever the system initially begins reading toggle bit
status, it must read Q7-Q0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system
can read array data on Q7-Q0 on the following read cycle.
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Q6 toggles for
approximately 100us and returns to reading array data.
If not all selected sectors are protected, the Automatic
Erase algorithm erases the unprotected sectors, and
ignores the selected sectors that are protected.
The system can use Q6 and Q2 together to determine
whether a sector is actively erasing or is erase sus-
pended.When the device is actively erasing (that is, the
Automatic Erase algorithm is in progress), Q6 toggling.
When the device enters the Erase Suspend mode, Q6
stops toggling. However, the system must also use Q2
to determine which sectors are erasing or erase-sus-
pended. Alternatively, the system can use Q7.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of Q5 is high
(see the section on Q5). If it is, the system should then
determine again whether the toggle bit is toggling, since
the toggle bit may have stopped toggling just as Q5 went
high. If the toggle bit is no longer toggling, the device
has successfully completed the program or erase op-
eration. If it is still toggling, the device did not complete
the operation successfully, and the system must write
the reset command to return to reading array data.
If a program address falls within a protected sector, Q6
toggles for approximately 2 us after the program com-
mand sequence is written, then returns to reading array
data.
Q6 also toggles during the erase-suspend-program mode,
and stops toggling once the Automatic Program algo-
rithm is complete.
The remaining scenario is that system initially determines
that the toggle bit is toggling and Q5 has not gone high.
The system may continue to monitor the toggle bit and
Q5 through successive read cycles, determining the sta-
tus as described in the previous paragraph. Alterna-
tively, it may choose to perform other system tasks. In
this case, the system must start at the beginning of the
algorithm when it returns to determine the status of the
operation.
Table 7 shows the outputs for Toggle Bit I on Q6.
Q2:Toggle Bit II
The "Toggle Bit II" on Q2, when used with Q6, indicates
whether a particular sector is actively erasing (that is,
the Automatic Erase algorithm is in process), or whether
that sector is erase-suspended. Toggle Bit II is valid
after the rising edge of the final WE# or CE#, whichever
happens first, in the command sequence.
Q5
ExceededTiming Limits
Q5 will indicate if the program or erase time has ex-
ceeded the specified limits (internal pulse count). Under
these conditions Q5 will produce a "1". This time-out
condition indicates that the program or erase cycle was
not successfully completed. Data# Polling and Toggle
Bit are the only operating functions of the device under
this condition.
Q2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
system may use either OE# or CE# to control the read
cycles.) But Q2 cannot distinguish whether the sector
is actively erasing or is erase-suspended. Q6, by com-
parison, indicates whether the device is actively eras-
ing, or is in Erase Suspend, but cannot distinguish which
sectors are selected for erasure. Thus, both status bits
If this time-out condition occurs during sector erase op-
P/N:PM1086
REV. 1.1, DEC. 07, 2004
16
MX29LV017B
eration, it specifies that a particular sector is bad and it
may not be reused. However, other sectors are still func-
tional and may be used for the program or erase opera-
tion. The device must be reset to use other sectors.
Write the Reset command sequence to the device, and
then execute program or erase command sequence. This
allows the system to continue to use the other active
sectors in the device.
If this time-out condition occurs during the byte program-
ming operation, it specifies that the entire sector con-
taining that byte is bad and this sector may not be re-
used, (other sectors are still functional and can be re-
used).
The time-out condition will not appear if a user tries to
program a non blank location without erasing. Please
note that this is not a device failure condition since the
device was incorrectly used.
If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad or com-
bination of sectors are bad.
Table 7. WRITE OPERATION STATUS
Status
Q7
Q6
Q5
Q3
Q2 RY/BY#
(Note1)
(Note 2)
Byte Program in Auto Program Algorithm
Auto Erase Algorithm
Q7# Toggle
0
N/A
1
No
0
Toggle
0
1
Toggle
0
0
Toggle
0
1
Erase Suspend Read
(Erase Suspended Sector)
No
Toggle
N/A Toggle
In Progress
Erase Suspended Mode
Erase Suspend Read
Data
Data Data Data Data
1
0
0
(Non-Erase Suspended Sector)
Erase Suspend Program
Q7# Toggle
Q7# Toggle
0
1
N/A N/A
Byte Program in Auto Program Algorithm
N/A
1
No
Toggle
Exceeded
Time Limits Auto Erase Algorithm
0
Toggle
1
1
Toggle
0
0
Erase Suspend Program
Q7# Toggle
N/A N/A
Notes:
1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.
See "Q5:Exceeded Timing Limits " for more information.
P/N:PM1086
REV. 1.1, DEC. 07, 2004
17
MX29LV017B
Q3
POWER SUPPLY DECOUPLING
Sector Erase Timer
In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected be-
tween itsVCC and GND.
After the completion of the initial sector erase command
sequence, the sector erase time-out will begin. Q3 will
remain low until the time-out is complete. Data# Polling
andToggle Bit are valid after the initial sector erase com-
mand sequence.
POWER-UP SEQUENCE
The MX29LV017B powers up in the Read only mode. In
addition, the memory contents may only be altered after
successful completion of the predefined command se-
quences.
If Data# Polling or theToggle Bit indicates the device has
been written with a valid erase command, Q3 may be
used to determine if the sector erase timer window is
still open. If Q3 is high ("1") the internally controlled
erase cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data# Polling or
Toggle Bit. If Q3 is low ("0"), the device will accept
additional sector erase commands. To insure the com-
mand has been accepted, the system software should
check the status of Q3 prior to and following each sub-
sequent sector erase command. If Q3 were high on the
second status check, the command may not have been
accepted.
TEMPORARY SECTOR UNPROTECT
This feature allows temporary unprotection of previously
protected sector to change data in-system.TheTempo-
rary Sector Unprotect mode is activated by setting the
RESET# pin toVID(11.5V-12.5V). During this mode, for-
merly protected sectors can be programmed or erased
as un-protected sector. Once VID is remove from the
RESET# pin, all the previously protected sectors are pro-
tected again.
DATA PROTECTION
SECTOR PROTECTION
The MX29LV017B is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power transi-
tion. During power up the device automatically resets
the state machine in the Read mode. In addition, with
its control register architecture, alteration of the memory
contents only occurs after successful completion of spe-
cific command sequences. The device also incorpo-
rates several features to prevent inadvertent write cycles
resulting fromVCC power-up and power-down transition
or system noise.
The MX29LV017B features hardware sector protection.
This feature will disable both program and erase opera-
tions for these sectors protected. To activate this mode,
the programming equipment must forceVID on address
pin A9 and OE# (suggest VID = 12V). Programming of
the protection circuitry begins on the falling edge of the
WE# pulse and is terminated on the rising edge.Please
refer to sector protect algorithm and waveform.
To verify programming of the protection circuitry, the pro-
gramming equipment must forceVID on address pin A9
( with CE# and OE# at VIL and WE# at VIH). When
A1=VIH, A0=VIL, A6=VIL, it will produce a logical "1"
code at device output Q0 for a protected sector. Other-
wise the device will produce 00H for the unprotected sec-
tor. In this mode, the addresses, except for A6, A1, A0,
are don't care. Address locations with A6=A1=VIL are
reserved to read manufacturer and device codes.(Read
Silicon ID)
WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 5ns(typical) on CE# or WE#
will not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE# = VIL,
CE# = VIH or WE# = VIH. To initiate a write cycle, CE#
and WE# must be a logical zero while OE# is a logical
one.
It is also possible to determine if the sector is protected
in the system by writing a Automatic Select command.
Performing a read operation with A1=VIH, it will produce
P/N:PM1086
REV. 1.1, DEC. 07, 2004
18
MX29LV017B
a logical "1" at Q0 for the protected sector.
The system must write the reset command to exit the
Automatic Select mode.
CHIP UNPROTECT
TheMX29LV017Balsofeaturesthechipunprotectmode,
sothatallsectorsareunprotectedafterchipunprotectis
completed to incorporate any changes in the code. It is
recommended to protect all sectors before activating
chip unprotect mode.
Toactivatethismode,theprogrammingequipmentmust
force VID on control pin OE# and address pin A9. The
CE# pinsmustbesetatVIL. PinsA6mustbesettoVIH.
Refer to chip unprotect algorithm and waveform for the
chip unprotect algorithm. The unprotection mechanism
begins on the falling edge of the WE# pulse and is
terminated on the rising edge.
It is also possible to determine if the chip is unprotected
inthesystembywritingtheAutomaticSelectcommand.
PerformingareadoperationwithA1=VIH,itwillproduce
00H at data outputs(Q0-Q7) for an unprotected sector.
It is noted that all sectors are unprotected after the chip
unprotect algorithm is completed.
P/N:PM1086
REV. 1.1, DEC. 07, 2004
19
MX29LV017B
OPERATING RATINGS
ABSOLUTE MAXIMUM RATINGS
StorageTemperature
Commercial (C) Devices
Plastic Packages . . . . . . . . . . . . . ..... -65oC to +150oC
Ambient Temperature (TA ). . . . . . . . . . . . 0°C to +70°C
Industrial (I) Devices
AmbientTemperature
with Power Applied. . . . . . . . . . . . . .... -65oC to +125oC
Voltage with Respect to Ground
Ambient Temperature (TA ). . . . . . . . . . -40°C to +85° C
VCC Supply Voltages
VCC for regulated voltage range . . . . . +3.0 V to 3.6 V
VCC for full voltage range. . . . . . . . . . . +2.7 V to 3.6 V
VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V
A9, OE#, and
RESET# (Note 2) . . . . . . . . . . . ....-0.5 V to +12.5 V
All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Operating ranges define those limits between which the
functionality of the device is guaranteed.
Notes:
1. Minimum DC voltage on input or I/O pins is -0.5 V.
During voltage transitions, input or I/O pins may over-
shoot GND to -2.0 V for periods of up to 20 ns. Maxi-
mum DC voltage on input or I/O pins is VCC +0.5 V.
During voltage transitions, input or I/O pins may over-
shoot to VCC +2.0 V for periods up to 20 ns.
2.Minimum DC input voltage on pins A9, OE#, and RE-
SET# is -0.5 V. During voltage transitions, A9, OE#,
and RESET# may overshoot GND to -2.0V for periods
of up to 20 ns. Maximum DC input voltage on pin A9
is +12.5 V which may overshoot to 14.0 V for periods
up to 20 ns.
3.No more than one output may be shorted to ground at
a time. Duration of the short circuit should not be
greater than one second.
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device at these or any other conditions above those in-
dicated in the operational sections of this data sheet is
not implied. Exposure of the device to absolute maxi-
mum rating conditions for extended periods may affect
device reliability.
P/N:PM1086
REV. 1.1, DEC. 07, 2004
20
MX29LV017B
CAPACITANCE TA = 25oC, f = 1.0 MHz
SYMBOL PARAMETER
MIN.
TYP
6
MAX.
7.5
9
UNIT
CONDITIONS
VIN = 0V
CIN1
CIN2
COUT
Input Capacitance
pF
pF
pF
Control Pin Capacitance
Output Capacitance
7.5
8.5
VIN = 0V
12
VOUT = 0V
READ OPERATION
Table 8. DC CHARACTERISTICS TA = -40oC TO 85oC, VCC = 2.7V~3.6V
Symbol PARAMETER
MIN.
TYP
MAX.
± 1
35
± 1
16
4
UNIT
uA
CONDITIONS
ILI
Input Leakage Current
VIN = GND to VCC, VCC= VCC max
VCC=VCC max; A9=12.5V
ILIT
ILO
ICC1
A9 Input Leakage Current
Output Leakage Current
VCC Active Read Current
uA
uA
VOUT = GND to VCC, VCC=VCC max
9
mA
mA
mA
uA
CE#=VIL,
OE#=VIH
@5MHz
@1MHz
2
ICC2
ICC3
ICC4
VCC Active write Current
VCC Standby Current
VCC Standby Current
During Reset (See Conditions)
Automotive sleep mode
Input Low Voltage(Note 1)
Input High Voltage
20
0.2
0.2
30
15
15
CE#=VIL, OE#=VIH, WE#=VIL
CE#; RESET#=VCC ± 0.3V
RESET#=GND ± 0.3V
uA
ICC5
VIL
0.2
15
0.8
uA
V
VIH=VCC ± 0.3V; VIL=GND ± 0.3V
-0.5
VIH
VID
0.7xVCC
VCC+ 0.3
V
Voltage for Automotive
Select and Temporary
Sector Unprotect
11.5
12.5
0.45
V
VCC=3.3V
VOL
Output Low Voltage
V
V
V
V
IOL = 4.0mA, VCC= VCC min
IOH = -2mA, VCC=VCC min
IOH = -100uA, VCC=VCC min
VOH1
VOH2
VLKO
Output High Voltage
0.85xVCC
VCC-0.4
1.4
Output High Voltage
Low VCC Lock-out Voltage
2.1
Notes :
1. VIL min. = -1.0V for pulse width is equal to or less than 50 ns.
VIL min. = -2.0V for pulse width is equal to or less than 20 ns.
2. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns
If VIH is over the specified maximum value, read operation cannot be guaranteed.
3. Automatic sleep mode enable the low power mode when addresses remain stable for tACC +30ns.
P/N:PM1086
REV. 1.1, DEC. 07, 2004
21
MX29LV017B
AC CHARACTERISTICS
TA = -40oC to 85oC, VCC = 2.7V~3.6V
Table 9. READ OPERATIONS
29LV017B-70
29LV017B-90
Symbol PARAMETER
MIN.
MAX. MIN.
MAX.
UNIT Conditions
tRC
Read CycleTime (Note 1)
Address to Output Delay
CE# to Output Delay
70
90
90
90
35
ns
tACC
tCE
70
70
30
25
ns
ns
ns
ns
ns
ns
ns
CE#=OE#=VIL
OE#=VIL
tOE
tDF
OE# to Output Delay
CE#=VIL
OE# High to Output Float (Note 2)
Output Enable Read
0
0
30
CE#=VIL
tOEH
0
0
HoldTime
Toggle and Data# Polling
10
0
10
0
tOH
Address to Output hold
CE#=OE#=VIL
Notes :
1. Not 100% tested.
2. tDF is defined as the time at which the output achieves
the open circuit condition and data is no longer driven.
TEST CONDITIONS:
• Input pulse levels: 0V/3.0V.
• Input rise and fall times is equal to or less than 5ns.
• Outputload:1TTLgate+100pF(Includingscopeand
jig), for 29LV017B-90. 1 TTL gate + 30pF (Including
scope and jig) for 29LV017B-70
• Reference levels for measuring timing: 1.5V.
P/N:PM1086
REV. 1.1, DEC. 07, 2004
22
MX29LV017B
SWITCHING TEST CIRCUITS
DEVICE UNDER
TEST
2.7K ohm
+3.3V
CL
6.2K ohm
DIODES=IN3064
OR EQUIVALENT
CL=100pF Including jig capacitance (MX29LV017B-90)
CL=30pF Including jig capacitance (MX29LV017B-70)
SWITCHING TEST WAVEFORMS
3.0V
TEST POINTS
0V
INPUT
OUTPUT
AC TESTING: Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0".
Input pulse rise and fall times are < 5ns.
P/N:PM1086
REV. 1.1, DEC. 07, 2004
23
MX29LV017B
Figure 1. READ TIMING WAVEFORMS
tRC
VIH
ADD Valid
Addresses
VIL
tACC
tCE
VIH
CE#
VIL
VIH
WE#
VIL
tOE
tDF
tOEH
VIH
OE#
VIL
tACC
tOH
HIGH Z
HIGH Z
VOH
VOL
Outputs
DATA Valid
VIH
VIL
RESET#
P/N:PM1086
REV. 1.1, DEC. 07, 2004
24
MX29LV017B
AC CHARACTERISTICS
TA = -40oC to 85oC, VCC = 2.7V~3.6V
Table 10. Erase/Program Operations
29LV017B-70
29LV017B-90
SYMBOL
tWC
PARAMETER
MIN.
70
0
MAX.
MIN.
90
0
MAX.
UNIT
ns
Write Cycle Time (Note 1)
Address Setup Time
tAS
ns
tAH
Address Hold Time
45
35
0
45
45
0
ns
tDS
Data Setup Time
ns
tDH
Data Hold Time
ns
tOES
tGHWL
Output Enable Setup Time
Read Recovery Time Before Write
(OE# High to WE# Low)
CE# Setup Time
0
0
ns
0
0
ns
tCS
0
0
ns
ns
ns
ns
us
tCH
CE# Hold Time
0
0
tWP
Write Pulse Width
35
35
tWPH
tWHWH1
Write Pulse Width High
ProgrammingOperation(Note2)
(Byte program time)
30
30
9(typ.)
9(typ.)
tWHWH2
tVCS
Sector Erase Operation (Note 2)
VCC Setup Time (Note 1)
Recovery Time from RY/BY#
Sector Erase Valid to RY/BY# Delay
Chip Erase Valid to RY/BY# Delay
Program Valid to RY/BY# Delay
Write pulse width for sector
protect (A9, OE# Control)
Write pulse width for sector
unprotect (A9, OE# Control)
0.7(typ.)
0.7(typ.)
sec
us
ns
ns
ns
ns
50
0
50
0
tRB
tBUSY
90
90
90
90
90
90
tWPP1
tWPP2
100ns
100ns
10us(typ.) 100ns
10us(typ.)
12ms(typ.) 100ns
12ms(typ.)
Notes :
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
P/N:PM1086
REV. 1.1, DEC. 07, 2004
25
MX29LV017B
AC CHARACTERISTICS
TA = -40oC to 85oC, VCC = 2.7V~3.6V
Table 11. Alternate CE# Controlled Erase/Program Operations
29LV017B-70
29LV017B-90
SYMBOL
tWC
PARAMETER
MIN.
MAX.
MIN.
MAX.
UNIT
ns
Write Cycle Time (Note 1)
Address SetupTime
Address HoldTime
70
90
tAS
0
0
ns
tAH
45
45
ns
tDS
Data SetupTime
35
45
ns
tDH
Data HoldTime
0
0
ns
tOES
tGHEL
tWS
Output Enable SetupTime
Read RecoveryTime Before Write
WE# SetupTime
0
0
ns
0
0
ns
0
0
ns
tWH
WE# HoldTime
0
0
ns
tCP
CE# PulseWidth
35
35
ns
tCPH
tWHWH1
tWHWH2
CE# Pulse Width High
Programming Operation(Note 2)
Sector Erase Operation (Note 2)
30
30
ns
9(Typ.)
0.7(Typ.)
9(Typ.)
0.7(Typ.)
us
sec
Notes :
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
P/N:PM1086
REV. 1.1, DEC. 07, 2004
26
MX29LV017B
Figure 2. COMMAND WRITE TIMING WAVEFORM
VCC
3V
VIH
Addresses
ADD Valid
VIL
tAH
tAS
VIH
VIL
WE#
CE#
tOES
tWPH
tWP
tCWC
VIH
VIL
tCS
tCH
tDH
VIH
VIL
OE#
Data
tDS
VIH
VIL
DIN
P/N:PM1086
REV. 1.1, DEC. 07, 2004
27
MX29LV017B
AUTOMATIC PROGRAMMING TIMING WAVEFORM
ing after automatic programming starts. Device outputs
DATA# during programming and DATA# after programming
on Q7.(Q6 is for toggle bit; see toggle bit, Data# Polling,
timing waveform)
One byte data is programmed. Verify in fast algorithm
and additional verification by external control are not re-
quired because these operations are executed automati-
cally by internal control circuit. Programming comple-
tion can be verified by Data# Polling or toggle bit check-
Figure 3. AUTOMATIC PROGRAMMING TIMING WAVEFORM
Program Command Sequence(last two cycle)
Read Status Data (last two cycle)
tWC
tAS
PA
PA
XXXh
PA
Address
CE#
tAH
tCH
tGHWL
OE#
WE#
tWHWH1
tWP
tCS
tWPH
tDS tDH
Status
A0h
PD
DOUT
Data
tBUSY
tRB
RY/BY#
tVCS
VCC
Note :
1.PA=Program Address, PD=Program Data, DOUT is the true data the program address
P/N:PM1086
REV. 1.1, DEC. 07, 2004
28
MX29LV017B
Figure 4. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART
START
Write Data AAH
Write Data 55H
Write Data A0H
Write Program Data/Address
Data Poll
Increment
Address
from system
No
No
Verify Data OK ?
YES
Last Address ?
YES
Auto Program Completed
P/N:PM1086
REV. 1.1, DEC. 07, 2004
29
MX29LV017B
Figure 5. CE# CONTROLLED WRITE TIMING WAVEFORM
PA for program
XXX for program
XXX for erase
SA for sector erase
XXX for chip erase
Data# Polling
Address
PA
tWC
tWH
tAS
tAH
WE#
OE#
tGHEL
tCP
tWHWH1 or 2
CE#
Data
tWS
tDS
tCPH
tBUSY
tDH
DOUT
Q7
PD for program
30 for sector erase
10 for chip erase
A0 for program
55 for erase
tRH
RESET#
RY/BY#
Notes :
1. PA=Program Address, PD=Program Data, DOUT=Data Out, Q7=complement of data written to device.
2. Figure indicates the last two bus cycles of the command sequence.
P/N:PM1086
REV. 1.1, DEC. 07, 2004
30
MX29LV017B
AUTOMATIC CHIP ERASE TIMING WAVEFORM
All data in chip are erased. External erase verification is
not required because data is verified automatically by
internal control circuit. Erasure completion can be veri-
fied by Data# Polling or toggle bit checking after auto-
matic erase starts. Device outputs 0 during erasure
and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle
bit, Data# Polling, timing waveform)
Figure 6. AUTOMATIC CHIP ERASE TIMING WAVEFORM
Erase Command Sequence(last two cycle)
Read Status Data
VA
tWC
tAS
VA
XXXh
XXXh
Address
CE#
tAH
tCH
tGHWL
OE#
WE#
tWHWH2
tWP
tCS
tWPH
tDS tDH
In
Progress
55h
10h
Complete
Data
tBUSY
tRB
RY/BY#
tVCS
VCC
Note :
VA=Valid Address for reading status data(see "Write Operation Status").
P/N:PM1086
REV. 1.1, DEC. 07, 2004
31
MX29LV017B
Figure 7. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address XXXH
Write Data 55H Address XXXH
Write Data 80H Address XXXH
Write Data AAH Address XXXH
Write Data 55H Address XXXH
Write Data 10H Address XXXH
Data Poll from System
NO
Data=FFh ?
YES
Auto Chip Erase Completed
P/N:PM1086
REV. 1.1, DEC. 07, 2004
32
MX29LV017B
AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Sector indicated by A16 to A20 are erased. External
erase verify is not required because data are verified
automatically by internal control circuit. Erasure comple-
tion can be verified by Data# Polling or toggle bit check-
ing after automatic erase starts. Device outputs 0 dur-
ing erasure and 1 after erasure on Q7.(Q6 is for toggle
bit; see toggle bit, Data# Polling, timing waveform)
Figure 8. AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Erase Command Sequence(last two cycle)
Read Status Data
tWC
tAS
VA
VA
XXXh
SA
Address
CE#
tAH
tCH
tGHWL
OE#
WE#
tWHWH2
tWP
tCS
tWPH
tDS tDH
In
Progress
55h
30h
Complete
Data
tBUSY
tRB
RY/BY#
tVCS
VCC
Note :
SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").
P/N:PM1086
REV. 1.1, DEC. 07, 2004
33
MX29LV017B
Figure 9. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address XXXH
Write Data 55H Address XXXH
Write Data 80H Address XXXH
Write Data AAH Address XXXH
Write Data 55H Address XXXH
Write Data 30H Sector Address
NO
Last Sector
to Erase
YES
Data Poll from System
NO
Data=FFh
YES
Auto Sector Erase Completed
P/N:PM1086
REV. 1.1, DEC. 07, 2004
34
MX29LV017B
Figure 10. ERASE SUSPEND/ERASE RESUME FLOWCHART
START
Write Data B0H
ERASE SUSPEND
NO
Toggle Bit checking Q6
not toggled
YES
Read Array or
Program
Reading or
NO
Programming End
YES
Write Data 30H
Continue Erase
ERASE RESUME
Another
NO
Erase Suspend ?
YES
P/N:PM1086
REV. 1.1, DEC. 07, 2004
35
MX29LV017B
Figure 11. IN-SYSTEM SECTOR PROTECT/CHIP UNPROTECTTIMINGWAVEFORM (RESET# Con-
trol)
VID
VIH
RESET#
SA, A6
A1, A0
Valid*
Valid*
Valid*
Sector Protect or Chip Unprotect
Verify
40h
Status
Data
60h
60h
Sector Protect =150us
Sector Unprotect =15ms
1us
CE#
WE#
OE#
Note: When sector protect, A6=0, A1=1, A0=0. When sector unprotect, A6=1, A1=1, A0=0.
P/N:PM1086
REV. 1.1, DEC. 07, 2004
36
MX29LV017B
Figure 12. SECTOR PROTECT TIMING WAVEFORM (A9, OE# Control)
A1
A6
12V
3V
A9
tVLHT
tVLHT
Verify
12V
3V
OE#
tVLHT
tWPP 1
WE#
CE#
tOESP
Data
01H
F0H
tOE
Sector Address
A20-A12
Notes : tVLHT (Voltage transition time)=4us min.
tWPP1 (Write pulse width for sector protect)=100ns min.
tOESP (OE# setup time to WE# active)=4us min.
P/N:PM1086
REV. 1.1, DEC. 07, 2004
37
MX29LV017B
Figure 13. SECTOR PROTECTION ALGORITHM (A9, OE# Control)
START
Set Up Sector Addr
PLSCNT=1
OE#=VID, A9=VID, CE#=VIL
A6=VIL
Activate WE# Pulse
Time Out 150us
Set WE#=VIH, CE#=OE#=VIL
A9 should remain VID
Read from Sector
No
Addr=SA, A6=VIL, A1=VIH, A0=VIL
No
Data=01H?
PLSCNT=32?
Yes
Device Failed
Yes
Protect Another
Sector?
Remove VID from A9
Write Reset Command
Sector Protection
Complete
P/N:PM1086
REV. 1.1, DEC. 07, 2004
38
MX29LV017B
Figure 14. IN-SYSTEM SECTOR PROTECTION ALGORITHM WITH RESET#=VID
START
PLSCNT=1
RESET#=VID
Wait 1us
No
Temporary Sector
Unprotect Mode
First Write
Cycle=60H
Yes
Set up sector address
Write 60H to sector address
with A6=0, A1=1, A0=0
Wait 150us
Verify sector protect :
write 40H to sector address
with A6=0, A1=1, A0=0
Increment PLSCNT
Reset PLSCNT=1
Read from sector address
with A6=0, A1=1, A0=0
No
No
PLSCNT=25?
Data=01H ?
Yes
Yes
Device failed
Yes
Protect another
sector?
No
Remove VID from RESET#
Write reset command
Sector protect complete
P/N:PM1086
REV. 1.1, DEC. 07, 2004
39
MX29LV017B
Figure 15. IN-SYSTEM CHIP UNPROTECTION ALGORITHM WITH RESET#=VID
START
PLSCNT=1
RESET#=VID
Wait 1us
No
No
Temporary Sector
Unprotect Mode
First Write
Cycle=60H ?
Yes
All sector
Protect all sectors
protected?
Yes
Set up first sector address
Chip unprotect :
write 60H with
A6=1, A1=1, A0=0
Wait 15ms
Verify sector unprotect
write 40H to sector address
with A6=1, A1=1, A0=0
Increment PLSCNT
Read from sector address
with A6=1, A1=1, A0=0
No
No
Set up next sector address
PLSCNT=1000?
Data=00H ?
Yes
Yes
Device failed
Yes
Last sector
verified?
No
Remove VID from RESET#
Write reset command
Chip unprotect complete
P/N:PM1086
REV. 1.1, DEC. 07, 2004
40
MX29LV017B
Figure 16. TIMING WAVEFORM FOR CHIP UNPROTECTION (A9, OE# Control)
A1
12V
VCC 3V
A9
A6
tVLHT
Verify
12V
VCC 3V
OE#
tVLHT
tVLHT
tWPP 2
WE#
CE#
tOESP
Data
00H
F0H
tOE
A20-A16
Sector Address
Notes : tVLHT (Voltage transition time)=4us min.
tWPP2 (Write pulse width for chip unprotect)=100ns min.
tOESP (OE# setup time to WE# active)=4us min.
P/N:PM1086
REV. 1.1, DEC. 07, 2004
41
MX29LV017B
Figure 17. CHIP UNPROTECTION ALGORITHM (A9, OE# Control)
START
Protect All Sectors
PLSCNT=1
Set OE#=A9=VID
CE#=VIL,A6=1
Activate WE# Pulse
Time Out 15ms
Increment
PLSCNT
Set OE#=CE#=VIL
A9=VID,A1=1,A6=A0=0
Set Up First Sector Addr
Read Data from Device
No
No
Data=00H?
Yes
PLSCNT=1000?
Increment
Sector Addr
Yes
Device Failed
No
All sectors have
been verified?
Yes
Remove VID from A9
Write Reset Command
Chip Unprotect
Complete
* It is recommended before unprotect whole chip, all sectors should be protected in advance.
P/N:PM1086
REV. 1.1, DEC. 07, 2004
42
MX29LV017B
WRITE OPERATION STATUS
Figure 18. DATA# POLLING ALGORITHM
Start
Read Q7~Q0
Add.=VA(1)
Yes
Q7 = Data ?
No
No
Q5 = 1 ?
Yes
Read Q7~Q0
Add.=VA
Yes
Q7 = Data ?
(2)
No
FAIL
Pass
Notes : 1. VA=Valid address for programming
2. Q7 should be re-checked even Q5="1" because Q7 may change
simultaneously with Q5.
P/N:PM1086
REV. 1.1, DEC. 07, 2004
43
MX29LV017B
Figure 19. TOGGLE BIT ALGORITHM
Start
Read Q7-Q0
Read Q7-Q0
(Note 1)
NO
Toggle Bit Q6 =
Toggle ?
YES
NO
Q5= 1?
YES
Read Q7~Q0 Twice
(Note 1, 2)
NO
Toggle bit Q6=
Toggle?
YES
Program/Erase Operation
Not Complete,Write
Reset Command
Program/Erase
operation Complete
Notes : 1. Read toggle bit twice to determine whether or not it is toggling.
2. Recheck toggle bit because it may stop toggling as Q5 change to "1".
P/N:PM1086
REV. 1.1, DEC. 07, 2004
44
MX29LV017B
Figure 20. Data# Polling Timings (During Automatic Algorithms)
tRC
VA
tACC
tCE
VA
VA
Address
CE#
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
Complement
Status Data
Complement
Status Data
True
True
Valid Data
Valid Data
Q7
High Z
Q0-Q6
tBUSY
RY/BY#
Note :
VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data read cycle.
P/N:PM1086
REV. 1.1, DEC. 07, 2004
45
MX29LV017B
Figure 21. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)
tRC
VA
VA
VA
VA
Address
CE#
tACC
tCE
tCH
tOE
OE#
tDF
tOEH
WE#
tOH
High Z
Valid Status
(second read)
Valid Status
(first read)
Valid Data
Valid Data
Q6/Q2
(stops toggling)
tBUSY
RY/BY#
Note :
VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle, and
array data read cycle.
P/N:PM1086
REV. 1.1, DEC. 07, 2004
46
MX29LV017B
Table 12. AC CHARACTERISTICS
Parameter Std Description
Test Setup All Speed Options Unit
tREADY1
RESET# PIN Low (During Automatic Algorithms)
MAX
20
us
to Read or Write (See Note)
tREADY2
RESET# PIN Low (NOT During Automatic
Algorithms) to Read or Write (See Note)
RESET# Pulse Width (During Automatic Algorithms)
RESET# HighTime Before Read(See Note)
RY/BY# Recovery Time(to CE#, OE# go low)
MAX
500
ns
tRP
tRH
tRB
MIN
MIN
MIN
500
50
0
ns
ns
ns
Note : Not 100% tested
Figure 22. RESET# TIMING WAVEFORM
RY/BY#
CE#, OE#
tRH
RESET#
tRP
tReady2
Reset Timing NOT during Automatic Algorithms
tReady1
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Reset Timing during Automatic Algorithms
P/N:PM1086
REV. 1.1, DEC. 07, 2004
47
MX29LV017B
Table 13. TEMPORARY SECTOR UNPROTECT
Parameter Std. Description
Test Setup All Speed Options Unit
tVIDR
tRSP
VID Rise and Fall Time (See Note)
Min
Min
500
4
ns
us
RESET# SetupTime forTemporary Sector Unprotect
Note : Not 100% tested
Figure 23. TEMPORARY SECTOR UNPROTECT TIMING DIAGRAM
12V
RESET#
0 or VCC
0 or VCC
Program or Erase Command Sequence
tVIDR
tVIDR
CE#
WE#
tRSP
RY/BY#
Figure 24. Q6 vs Q2 for Erase and Erase Suspend Operations
Enter Embedded
Erasing
Erase
Enter Erase
Erase
Suspend
Suspend Program
Resume
Erase
Erase
Erase Suspend
Read
Erase
Erase
WE#
Q6
Suspend
Program
Complete
Q2
Note :
The system can use OE# or CE# to toggle Q2/Q6, Q2 toggles only when read at an address within an erase-suspended
P/N:PM1086
REV. 1.1, DEC. 07, 2004
48
MX29LV017B
Figure 25. TEMPORARY SECTOR UNPROTECT ALGORITHM
Start
RESET# = VID (Note 1)
Perform Erase or Program Operation
Operation Completed
RESET# = VIH
Temporary Sector Unprotect Completed (Note 2)
Notes : 1. All protected sectors are temporary unprotected.
VID=11.5V~12.5V
2. All previously protected sectors are protected again.
P/N:PM1086
REV. 1.1, DEC. 07, 2004
49
MX29LV017B
Figure 26. ID CODE READ TIMING WAVEFORM
VCC
3V
VID
ADD
A9
VIH
VIL
VIH
VIL
ADD
A0
tACC
tACC
VIH
VIL
A1
ADD
A2-A8
VIH
A10-A20 VIL
CE#
VIH
VIL
VIH
VIL
tCE
WE#
OE#
tOE
VIH
VIL
tDF
tOH
tOH
VIH
VIL
DATA
Q0-Q7
DATA OUT
C2H
DATA OUT
C8H
P/N:PM1086
REV. 1.1, DEC. 07, 2004
50
MX29LV017B
ERASE AND PROGRAMMING PERFORMANCE (1)
LIMITS
PARAMETER
MIN.
TYP.(2)
0.7
MAX.(3)
UNITS
sec
Sector Erase Time
Chip Erase Time
15
22.5
9
sec
Byte Programming Time
Chip Programming Time
Erase/Program Cycles
300
54
us
18
sec
100,000
Cycles
Notes : 1. Not 100% Tested, Excludes external system level over head.
2.Typical values measured at 25° C, 3V.
3. Maximum values measured at 85° C, 2.7V, 100,000 cycles.
LATCH-UP CHARACTERISTICS
MIN.
-1.0V
MAX.
Input Voltage with respect to GND on all pins except I/O pins
Input Voltage with respect to GND on all I/O pins
VCC Current
12.5V
VCC + 1.0V
+100mA
-1.0V
-100mA
Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.
P/N:PM1086
REV. 1.1, DEC. 07, 2004
51
MX29LV017B
ORDERING INFORMATION
PART NO.
ACCESS
OPERATING
STANDBY
PACKAGE
Remark
TIME(ns) Current MAX.(mA) Current MAX.(uA)
MX29LV017BTC-70
MX29LV017BTC-90
MX29LV017BTI-70
MX29LV017BTI-90
MX29LV017BTC-70G
MX29LV017BTC-90G
MX29LV017BTI-70G
MX29LV017BTI-90G
70
90
70
90
70
90
70
90
30
30
30
30
30
30
30
30
15
15
15
15
15
15
15
15
40 Pin TSOP
(NormalType)
40 Pin TSOP
(NormalType)
40 Pin TSOP
(NormalType)
40 Pin TSOP
(NormalType)
40 Pin TSOP
(NormalType)
40 Pin TSOP
(NormalType)
40 Pin TSOP
(NormalType)
40 Pin TSOP
(NormalType)
Pb-free
Pb-free
Pb-free
Pb-free
P/N:PM1086
REV. 1.1, DEC. 07, 2004
52
MX29LV017B
PACKAGE INFORMATION
P/N:PM1086
REV. 1.1, DEC. 07, 2004
53
MX29LV017B
REVISION HISTORY
Revision No. Description
Page
P52
P1,2,52
Date
DEC/07/2004
1.1
1. Added Pb-free package information
2. Removed 48-CSP information
P/N:PM1086
REV. 1.1, DEC. 07, 2004
54
MX29LV017B
MACRONIX INTERNATIONALCO., LTD.
Headquarters:
TEL:+886-3-578-6688
FAX:+886-3-563-2888
Europe Office :
TEL:+32-2-456-8020
FAX:+32-2-456-8021
Hong Kong Office :
TEL:+86-755-834-335-79
FAX:+86-755-834-380-78
Japan Office :
Kawasaki Office :
TEL:+81-44-246-9100
FAX:+81-44-246-9105
Osaka Office :
TEL:+81-6-4807-5460
FAX:+81-6-4807-5461
Singapore Office :
TEL:+65-6346-5505
FAX:+65-6348-8096
Taipei Office :
TEL:+886-2-2509-3300
FAX:+886-2-2509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-262-8887
FAX:+1-408-262-8810
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明