MX29LV160BXBI-70R_技术文档

MX29LV160T/B & MX29LV160AT/AB

16M-BIT[2Mx8/1Mx16]CMOSSINGLEVOLTAGE

3VONLYFLASHMEMORY

FEATURES

• Ready/Busy pin (RY/BY)

• Extended single - supply voltage range 2.7V to 3.6V

• 2,097,152 x 8/1,048,576 x 16 switchable

• Singlepowersupplyoperation

- 3.0V only operation for read, erase and program

operation

• Fast access time: 70/90ns

-Providesahardwaremethodofdetectingprogramor

eraseoperationcompletion.

• Sectorprotection

- Hardware method to disable any combination of

sectors from program or erase operations

-Temporarysectorunprotectallowscodechangesin

previously locked sectors.

• Lowpowerconsumption

- 20mA maximum active current

• CFI (Common Flash Interface) compliant (for

MX29LV160AT/BT)

- 0.2uA typical standby current

• Commandregisterarchitecture

- Flash device parameters stored on the device and

provide the host system to access

• 100,000minimumerase/programcycles

• Latch-up protected to 100mA from -1V to VCC+1V

• Boot Sector Architecture

- T = Top Boot Sector

- B = Bottom Boot Sector

• Low VCC write inhibit is equal to or less than 2.3V

• Package type:

- Byte/word Programming (9us/11us typical)

- Sector Erase (Sector structure 16K-Bytex1,

8K-Bytex2, 32K-Bytex1, and 64K-Byte x31)

• Auto Erase (chip & sector) and Auto Program

-Automaticallyeraseanycombinationofsectorswith

Erase Suspend capability.

- Automatically program and verify data at specified

address

• Erasesuspend/EraseResume

- 44-pin SOP

- 48-pin TSOP

-48-ballCSP(8x13mm:forMX29LV160T/B;6x8mm:

forMX29LV160AT/BT)

- Suspends sector erase operation to read data from,

orprogramdatato,any sectorthatisnotbeingerased,

then resumes the erase.

• Status Reply

• Compatibility with JEDEC standard

- Pinout and software compatible with single-power

supply Flash

-Datapolling&Togglebitfordetectionofprogramand

eraseoperationcompletion.

power supply levels during erase and programming, while

maintaining maximum EPROM compatibility.

GENERAL DESCRIPTION

The MX29LV160T/B & MX29LV160AT/AB is a 16-mega

bit Flash memory organized as 2M bytes of 8 bits or 1M

words of 16 bits. MXIC's Flash memories offer the most

cost-effective and reliable read/write non-volatile random

access memory. The MX29LV160T/B & MX29LV160AT/

AB is packaged in 44-pin SOP, 48-pinTSOP and 48-ball

CSP. It is designed to be reprogrammed and erased in

system or in standard EPROM programmers.

MXIC Flash technology reliably stores memory contents

even after 100,000 erase and program cycles. The MXIC

cell is designed to optimize the erase and programming

mechanisms. In addition, the combination of advanced

tunnel oxide processing and low internal electric fields

for erase and program operations produces reliable cy-

cling. The MX29LV160T/B & MX29LV160AT/AB uses a

2.7V~3.6V VCC supply to perform the High Reliability

Erase and auto Program/Erase algorithms.

The standard MX29LV160T/B & MX29LV160AT/AB of-

fers access time as fast as 70ns, allowing operation of

high-speed microprocessors without wait states. To elimi-

nate bus contention, the MX29LV160T/B &

MX29LV160AT/AB has separate chip enable (CE) and

output enable (OE) controls.

The highest degree of latch-up protection is achieved

with MXIC's proprietary non-epi process. Latch-up pro-

tection is proved for stresses up to 100 milliamps on

address and data pin from -1V to VCC + 1V.

Part Name

MX29LV160T/B

Difference

1) Without CFI compliant

2)CSP dimension:8x13mm

MXIC's Flash memories augment EPROM functionality

with in-circuit electrical erasure and programming. The

MX29LV160T/B & MX29LV160AT/AB uses a command

register to manage this functionality. The command reg-

ister allows for 100% TTL level control inputs and fixed

MX29LV160AT/AB 1) With CFI compliant

2)CSP dimension:6x8mm

P/N:PM0866

REV. 3.3, MAR. 08, 2002

1

MX29LV160T/B & MX29LV160AT/AB

PIN CONFIGURATIONS

PIN DESCRIPTION

SYMBOL PIN NAME

44 SOP(500 mil)

44

WE

A19

A8

RESET

A0~A19 Address Input

2

3

4

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

A18

A17

A7

Q0~Q14 Data Input/Output

A9

5

A10

A11

A12

A13

A14

A15

A16

BYTE

GND

Q15/A-1

Q7

Q14

Q6

Q13

Q5

Q12

Q4

VCC

A6

Q15/A-1 Q15(Word mode)/LSB addr(Byte mode)

6

A5

7

A4

CE

Chip Enable Input

8

A3

9

A2

WE

Write Enable Input

10

11

12

13

14

15

16

17

18

19

20

21

22

A1

A0

BYTE

RESET

OE

Word/Byte Selection input

Hardware Reset Pin/Sector Protect Unlock

Output Enable Input

CE

GND

OE

Q0

Q8

Q1

Q9

Q2

Q10

Q3

Q11

RY/BY

VCC

GND

Ready/Busy Output

Power Supply Pin (2.7V~3.6V)

Ground Pin

48 TSOP (Standard Type) (12mm x 20mm)

A15

A14

A13

A12

A11

A10

A9

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

BYTE

GND

Q15/A-1

Q7

2

3

4

5

6

Q14

Q6

7

A8

8

Q13

Q5

A19

NC

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

Q12

Q4

WE

RESET

NC

MX29LV160T/B, MX29LV160AT/AB

VCC

Q11

Q3

NC

RY/BY

A18

A17

A7

Q10

Q2

Q9

Q1

A6

Q8

A5

Q0

A4

OE

A3

GND

CE

A2

A1

A0

48-Ball CSP (Ball Pitch=0.8mm) Top View, Balls Facing Down (8x13mm for MX29LV160T/B; 6x8mm for

MX29LV160AT/AB)

A

B

C

D

E

F

G

H

6

5

4

3

2

1

A13

A9

WE

A12

A8

A14

A10

A15

A11

A19

NC

A5

A16

Q7

Q5

Q2

Q0

A0

BYTE

Q14

Q12

Q10

Q8

Q15/A-1 GND

Q13

VCC

Q11

Q9

Q6

RESET NC

Q4

RY/BY NC

A18

A6

Q3

A7

A3

A17

A4

Q1

A2

A1

CE

OE

GND

P/N:PM0866

REV. 3.3, MAR. 08, 2002

2

MX29LV160T/B & MX29LV160AT/AB

BLOCK STRUCTURE

Table 1: MX29LV160AT SECTOR ARCHITECTURE

Sector

Sector Size

Address range

Sector Address

Byte Mode Word Mode Byte Mode(x8) Word Mode(x16) A19 A18 A17 A16 A15 A14 A13 A12

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

64Kbytes 32Kwords 000000-00FFFF 00000-07FFF

64Kbytes 32Kwords 010000-01FFFF 08000-0FFFF

64Kbytes 32Kwords 020000-02FFFF 10000-17FFF

64Kbytes 32Kwords 030000-03FFFF 18000-1FFFF

64Kbytes 32Kwords 040000-04FFFF 20000-27FFF

64Kbytes 32Kwords 050000-05FFFF 28000-2FFFF

64Kbytes 32Kwords 060000-06FFFF 30000-37FFF

64Kbytes 32Kwords 070000-07FFFF 38000-3FFFF

64Kbytes 32Kwords 080000-08FFFF 40000-47FFF

64Kbytes 32Kwords 090000-09FFFF 48000-4FFFF

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

X

0

X

0

SA10 64Kbytes 32Kwords 0A0000-0AFFFF 50000-57FFF

SA11 64Kbytes 32Kwords 0B0000-0BFFFF 58000-5FFFF

SA12 64Kbytes 32Kwords 0C0000-0CFFFF 60000-67FFF

SA13 64Kbytes 32Kwords 0D0000-0DFFFF 68000-6FFFF

SA14 64Kbytes 32Kwords 0E0000-0EFFFF 70000-77FFF

SA15 64Kbytes 32Kwords 0F0000-0FFFFF 78000-7FFFF

SA16 64Kbytes 32Kwords 100000-10FFFF 80000-87FFF

SA17 64Kbytes 32Kwords 110000-11FFFF 88000-8FFFF

SA18 64Kbytes 32Kwords 120000-12FFFF 90000-97FFF

SA19 64Kbytes 32Kwords 130000-13FFFF 98000-9FFFF

SA20 64Kbytes 32Kwords 140000-14FFFF A0000-A7FFF

SA21 64Kbytes 32Kwords 150000-15FFFF A8000-AFFFF

SA22 64Kbytes 32Kwords 160000-16FFFF B0000-B7FFF

SA23 64Kbytes 32Kwords 170000-17FFFF B8000-BFFFF

SA24 64Kbytes 32Kwords 180000-18FFFF C0000-C7FFF

SA25 64Kbytes 32Kwords 190000-19FFFF C8000-CFFFF

SA26 64Kbytes 32Kwords 1A0000-1AFFFF D0000-D7FFF

SA27 64Kbytes 32Kwords 1B0000-1BFFFF D8000-DFFFF

SA28 64Kbytes 32Kwords 1C0000-1CFFFF E0000-E7FFF

SA29 64Kbytes 32Kwords 1D0000-1DFFFF E8000-EFFFF

SA30 64Kbytes 32Kwords 1E0000-1EFFFF F0000-F7FFF

SA31 32Kbytes 16Kwords 1F0000-1F7FFF F8000-FBFFF

SA32

SA33

8Kbytes

4Kwords 1F8000-1F9FFF FC000-ECFFF

4Kwords 1FA000-1FBFFF FD000-FDFFF

8Kwords 1FC000-1FFFFF FE000-FFFFF

1

0

1

SA34 16Kbytes

1

X

Note: Byte mode: address range A19:A-1, word mode:address range A19:A0.

P/N:PM0866

REV. 3.3, MAR. 08, 2002

3

MX29LV160T/B & MX29LV160AT/AB

Table 2: MX29LV160AB SECTOR ARCHITECTURE

Sector

Sector Size

Address range

Sector Address

Byte Mode Word Mode Byte Mode (x8) Word Mode (x16) A19 A18 A17 A16 A15 A14 A13 A12

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

16Kbytes

8Kbytes

8Kwords 000000-003FFF 00000-01FFF

4Kwords 004000-005FFF 02000-02FFF

4Kwords 006000-007FFF 03000-03FFF

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

1

32Kbytes 16Kwords 008000-00FFFF 04000-07FFF

64Kbytes 32Kwords 010000-01FFFF 08000-0FFFF

64Kbytes 32Kwords 020000-02FFFF 10000-17FFF

64Kbytes 32Kwords 030000-03FFFF 18000-1FFFF

64Kbytes 32Kwords 040000-04FFFF 20000-27FFF

64Kbytes 32Kwords 050000-05FFFF 28000-2FFFF

64Kbytes 32Kwords 060000-06FFFF 30000-37FFF

1

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

SA10 64Kbytes 32Kwords 070000-07FFFF 38000-3FFFF

SA11 64Kbytes 32Kwords 080000-08FFFF 40000-47FFF

SA12 64Kbytes 32Kwords 090000-09FFFF 48000-4FFFF

SA13 64Kbytes 32Kwords 0A0000-0AFFFF 50000-57FFF

SA14 64Kbytes 32Kwords 0B0000-0BFFFF 58000-5FFFF

SA15 64Kbytes 32Kwords 0C0000-0CFFFF 60000-67FFF

SA16 64Kbytes 32Kwords 0D0000-0DFFFF 68000-6FFFF

SA17 64Kbytes 32Kwords 0E0000-0EFFFF 70000-77FFF

SA18 64Kbytes 32Kwords 0F0000-0FFFFF 78000-7FFFF

SA19 64Kbytes 32Kwords 100000-10FFFF 80000-87FFF

SA20 64Kbytes 32Kwords 110000-11FFFF 88000-8FFFF

SA21 64Kbytes 32Kwords 120000-12FFFF 90000-97FFF

SA22 64Kbytes 32Kwords 130000-13FFFF 98000-9FFFF

SA23 64Kbytes 32Kwords 140000-14FFFF A0000-A7FFF

SA24 64Kbytes 32Kwords 150000-15FFFF A8000-AFFFF

SA25 64Kbytes 32Kwords 160000-16FFFF B0000-B7FFF

SA26 64Kbytes 32Kwords 170000-17FFFF B8000-BFFFF

SA27 64Kbytes 32Kwords 180000-18FFFF C0000-C7FFF

SA28 64Kbytes 32Kwords 190000-19FFFF C8000-CFFFF

SA29 64Kbytes 32Kwords 1A0000-1AFFFF D0000-D7FFF

SA30 64Kbytes 32Kwords 1B0000-1BFFFF D8000-DFFFF

SA31 64Kbytes 32Kwords 1C0000-1CFFFF E0000-E7FFF

SA32 64Kbytes 32Kwords 1D0000-1DFFFF E8000-EFFFF

SA33 64Kbytes 32Kwords 1E0000-1EFFFF F0000-FFFFF

SA34 64Kbytes 32Kwords 1F0000-1FFFFF F8000-FFFFF

Note: Byte mode:address range A19:A-1, word mode:address range A19:A0.

P/N:PM0866

REV. 3.3, MAR. 08, 2002

4

MX29LV160T/B & MX29LV160AT/AB

BLOCK DIAGRAM

WRITE

CE

OE

WE

CONTROL

INPUT

PROGRAM/ERASE

HIGH VOLTAGE

STATE

MACHINE

(WSM)

LOGIC

RESET

STATE

REGISTER

ADDRESS

LATCH

FLASH

ARRAY

A0-A19

SOURCE

HV

AND

COMMAND

DATA

BUFFER

Y-PASS GATE

DECODER

PGM

DATA

HV

SENSE

AMPLIFIER

COMMAND

DATA LATCH

PROGRAM

DATA LATCH

I/O BUFFER

Q0-Q15/A-1

P/N:PM0866

REV. 3.3, MAR. 08, 2002

5

MX29LV160T/B & MX29LV160AT/AB

AUTOMATIC ERASE ALGORITHM

AUTOMATIC PROGRAMMING

MXIC's Automatic Erase algorithm requires the user to

write commands to the command register using stan-

dard microprocessor write timings. The device will auto-

matically pre-program and verify the entire array. Then

the device automatically times the erase pulse width,

provides the erase verification, and counts the number

of sequences. A status bit toggling between consecu-

tive read cycles provides feedback to the user as to the

status of the erasing operation.

The MX29LV160T/B & MX29LV160AT/AB is byte pro-

grammable using the Automatic Programming algorithm.

The Automatic Programming algorithm makes the ex-

ternal system do not need to have time out sequence

nor to verify the data programmed. The typical chip pro-

gramming time at room temperature of the MX29LV160T/

B & MX29LV160AT/AB is less than 10 seconds.

AUTOMATIC PROGRAMMING ALGORITHM

Register contents serve as inputs to an internal state-

machine which controls the erase and programming cir-

cuitry. During write cycles, the command register inter-

nally latches address and data needed for the program-

ming and erase operations. During a system write cycle,

addresses are latched on the falling edge, and data are

latched on the rising edge of WE or CE, whichever hap-

pens first.

MXIC's Automatic Programming algorithm requires the

user to only write program set-up commands (including

2 unlock write cycle and A0H) and a program command

(program data and address). The device automatically

times the programming pulse width, provides the pro-

gram verification, and counts the number of sequences.

The device provides an unlock bypass mode with faster

programming. Only two write cycles are needed to pro-

gram a word or byte, instead of four. A status bit similar

to DATA polling and a status bit toggling between con-

secutive read cycles, provide feedback to the user as

to the status of the programming operation. Refer to write

operation status, table 7, for more information on these

status bits.

MXIC's Flash technology combines years of EPROM

experience to produce the highest levels of quality, reli-

ability, and cost effectiveness. The MX29LV160T/B &

MX29LV160AT/AB electrically erases all bits simulta-

neously using Fowler-Nordheim tunneling. The bytes are

programmed by using the EPROM programming mecha-

nism of hot electron injection.

During a program cycle, the state-machine will control

the program sequences and command register will not

respond to any command set. During a Sector Erase

cycle, the command register will only respond to Erase

Suspend command. After Erase Suspend is completed,

the device stays in read mode. After the state machine

has completed its task, it will allow the command regis-

ter to respond to its full command set.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 10 ms erase pulses

according to MXIC's Automatic Chip Erase algorithm.

Typical erasure at room temperature is accomplished in

less than 25 second. The Automatic Erase algorithm

automatically programs the entire array prior to electri-

cal erase. The timing and verification of electrical erase

are controlled internally within the device.

AUTOMATIC SELECT

AUTOMATIC SECTOR ERASE

The auto select mode provides manufacturer and de-

vice identification, and sector protection verification,

through identifier codes output on Q7~Q0.This mode is

mainly adapted for programming equipment on the de-

vice to be programmed with its programming algorithm.

When programming by high voltage method, automatic

select mode requires VID (11.5V to 12.5V) on address

pin A9 and other address pin A6, A1 and A0 as referring

to Table 3. In addition, to access the automatic select

codes in-system, the host can issue the automatic se-

The MX29LV160T/B & MX29LV160AT/AB is sector(s)

erasable using MXIC's Auto Sector Erase algorithm.The

Automatic Sector Erase algorithm automatically pro-

grams the specified sector(s) prior to electrical erase.

The timing and verification of electrical erase are con-

trolled internally within the device. An erase operation

can erase one sector, multiple sectors, or the entire de-

vice.

P/N:PM0866

REV. 3.3, MAR. 08, 2002

6

MX29LV160T/B & MX29LV160AT/AB

lect command through the command register without

requiring VID, as shown in table 4.

To verify whether or not sector being protected, the sec-

tor address must appear on the appropriate highest or-

der address bit (see Table 1 and Table 2). The rest of

address bits, as shown in table 3, are don't care. Once

all necessary bits have been set as required, the pro-

gramming equipment may read the corresponding iden-

tifier code on Q7~Q0.

TABLE 3. MX29LV160T/B & MX29LV160AT/AB AUTO SELECT MODE BUS OPERATION (A9=VID)

A19

|

A11

|

A9

A8

|

A6

A5

|

A1

A0

Description

Mode

CE

OE

WE RESET

Q15~Q0

A12

X

A10

X

A7

X

A2

X

Read Silicon ID

Manufacture Code

Read Silicon ID

(Top Boot Block)

Device ID

L

H

VID

L

C2H

Word

Byte

Word

Byte

L

H

X

VID

X

L

X

L

H

22C4H

XXC4H

2249H

(Bottom Boot Block)

XX49H

XX01H

(protected)

Sector Protection

Verification

L

H

SA

X

VID

X

L

X

H

L

XX00H

(unprotected)

NOTE: SA=Sector Address, X=Don't Care, L=Logic Low, H=Logic High

P/N:PM0866

REV. 3.3, MAR. 08, 2002

7

MX29LV160T/B & MX29LV160AT/AB

described inTable 6.

QUERY COMMAND AND COMMON FLASH

The single cycle Query command is valid only when the

device is in the Read mode, including Erase Suspend,

Standby mode, and Read ID mode; however, it is ig-

nored otherwise.

INTERFACE (CFI) MODE ( for MX29LV160AT/

AB)

MX29LV160AT/AB is capable of operating in the CFI

mode. This mode all the host system to determine the

manufacturer of the device such as operating param-

eters and configuration.Two commands are required in

CFI mode. Query command of CFI mode is placed first,

then the Reset command exits CFI mode. These are

The Reset command exits from the CFI mode to the

Read mode, or Erase Suspend mode, or read ID mode.

The command is valid only when the device is in the

CFI mode.

Table 4-1. CFI mode: Identification Data Values

(All values in these tables are in hexadecimal)

Description

Address

Data

(ByteMode)

(WordMode)

Query-unique ASCII string "QRY"

20

22

24

26

28

2A

2C

2E

30

32

34

10

11

12

13

14

15

16

17

18

19

1A

0051

0052

0059

0002

0000

0040

0000

Primary vendor command set and control interface ID code

Address for primary algorithm extended query table

Alternate vendor command set and control interface ID code (none)

Address for secondary algorithm extended query table (none)

Table 4-2. CFI Mode: System Interface Data Values

(All values in these tables are in hexadecimal)

Description

Address

Data

(ByteMode)

(WordMode)

VCC supply, minimum (2.7V)

36

38

3A

3C

3E

40

42

44

46

48

4A

4C

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

0027

0036

0000

0004

0000

000A

0000

0005

0000

0004

0000

VCC supply, maximum (3.6V)

VPP supply, minimum (none)

VPP supply, maximum (none)

Typical timeout for single word/byte write (2^Nus)

Typical timeout for Minimum size buffer write (2^Nus)

Typical timeout for individual block erase (2^Nms)

Typical timeout for full chip erase (2^Nms)

Maximum timeout for single word/byte write times (2^NX Typ)

Maximum timeout for buffer write times (2^NX Typ)

Maximum timeout for individual block erase times (2^NX Typ)

Maximum timeout for full chip erase times (not supported)

P/N:PM0866

REV. 3.3, MAR. 08, 2002

8

MX29LV160T/B & MX29LV160AT/AB

Table 4-3. CFI Mode: Device Geometry Data Values

(All values in these tables are in hexadecimal)

Description

Address

Data

(ByteMode)

(WordMode)

Device size (2^Nbytes)

4E

50

52

54

56

58

5A

5C

5E

60

62

64

66

68

6A

6C

6E

70

72

74

76

78

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

0015

0002

0000

0004

0000

0040

0000

0001

0000

0020

0000

0080

0000

001E

0000

0001

Flash device interface code (refer to the CFI publication 100)

Maximum number of bytes in multi-byte write (not supported)

Number of erase block regions

Erase block region 1 information (refer to the CFI publication 100)

Erase block region 2 information

Erase block region 3 information

Erase block region 4 information

Table 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values

(All values in these tables are in hexadecimal)

Description

Address

Data

(ByteMode)

(WordMode)

Query-unique ASCII string "PRI"

80

82

84

86

88

8A

8C

8E

90

92

94

96

98

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

0050

0052

0049

0031

0030

0000

0002

0001

0004

0000

Major version number, ASCII

Minor version number, ASCII

Address sensitive unlock (0=required, 1= not required)

Erase suspend (2= to read and write)

Sector protect (N= # of sectors/group)

Temporarysectorunprotect(1=supported)

Sector protect/unprotect scheme

SimultaneousR/Woperation(0=notsupported)

Burst mode type (0=not supported)

Page mode type (0=not supported)

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REV. 3.3, MAR. 08, 2002

9

MX29LV160T/B & MX29LV160AT/AB

in the improper sequence will reset the device to the

read mode. Table 5 defines the valid register command

sequences. Note that the Erase Suspend (B0H) and

Erase Resume (30H) commands are valid only while the

Sector Erase operation is in progress.

COMMAND DEFINITIONS

Device operations are selected by writing specific ad-

dress and data sequences into the command register.

Writing incorrect address and data values or writing them

TABLE 5. MX29LV160T/B & MX29LV160AT/AB COMMAND DEFINITIONS

First Bus

Bus Cycle

Second Bus Third Bus

Fourth Bus

Cycle

Fifth Bus

Cycle

Sixth Bus

Cycle

Command

Cycle

Cycle Addr Data Addr

Data Addr

Data Addr Data Addr

Data Addr Data

Reset

1

4

XXXH F0H

RA RD

Read

Read Silicon ID Word

Byte

555H AAH 2AAH 55H 555H 90H ADI

AAAH AAH 555H 55H AAAH 90H ADI

DDI

Sector Protect

Verify

Word

555H AAH 2AAH 55H 555H 90H (SA) XX00H

x02H XX01H

Byte

4

AAAH AAH 555H 55H AAAH 90H (SA) 00H

x04H 01H

Program

Word

Byte

Word

Byte

Word

Byte

4

6

1

555H AAH 2AAH 55H 555H A0H PA

AAAH AAH 555H 55H AAAH A0H PA

PD

Chip Erase

Sector Erase

555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H

555H 10H

AAAH 10H

AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H

555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H

SA

30H

AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H

Sector Erase Suspend

Sector Erase Resume

XXXH B0H

XXXH 30H

555H 98

AAAH

CFI Query (for

Word

29LV160AT/AB) Byte

Note:

1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacturer code,A1=0, A0 = 1 for device code. A2-A18=do not care.

(Refer to table 3)

DDI = Data of Device identifier : C2H for manufacture code, C4H/49H (x8) and 22C4H/2249H (x16) for device code.

X = X can be VIL or VIH

RA=Address of memory location to be read. RD=Data to be read at location RA.

2.PA = Address of memory location to be programmed. PD = Data to be programmed at location PA.

SA = Address of the sector to be erased.

3.The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 in word mode/AAAH or

555H to Address A10~A-1 in byte mode.

Address bit A11~A19=X=Don't care for all address commands except for Program Address (PA) and Sector

Address (SA). Write Sequence may be initiated with A11~A19 in either state.

4. For Sector Protect Verify operation: If read out data is 01H, it means the sector has been protected. If read out data is 00H,

it means the sector is still not being protected.

5. Any number of CFI data read cycles are permitted.

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TABLE 6. MX29LV160T/B & MX29LV160AT/AB BUS OPERATION

ADDRESS

OE WE RESET A19 A10 A9 A8 A6 A5 A1 A0

Q8~Q15

DESCRIPTION

CE

Q0~Q7

BYTE

=VIL

A11

A7

A2

=VIH

Read

L

H

AIN

Dout

=High Z

DQ15=A-1

Write

L

H

X

H

X

L

X

H

X

H

L

AIN

X

DIN(3)

High Z

DIN

High Z

DIN

Reset

X

High Z

Temporary sector unlock

Output Disable

Standby

VID

H

AIN

X

L

High Z

Vcc±

0.3V

L

Vcc±

0.3V

VID

H

X

Sector Protect

H

L

SA

X

L

H

L

X

H

L

DIN

X

Chip Unprotect

L

Sector Protection Verify

L

H

SA

VID

CODE(5)

NOTES:

1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 4.

2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.

3. Refer to Table 4 for valid Data-In during a write operation.

4. X can be VIL or VIH.

5. Code=00H/XX00H means unprotected.

Code=01H/XX01H means protected.

6. A19~A12=Sector address for sector protect.

7.The sector protect and chip unprotect functions may also be implemented via programming equipment.

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MX29LV160T/B & MX29LV160AT/AB

separate from the memory array) on Q7-Q0. Standard

read cycle timings apply in this mode. Refer to the "read

silicon-ID" and "sector protect verify" Mode and "read

silicon-ID" and "sector protect verify" Command

Sequence section for more information.

REQUIREMENTS FOR READING ARRAY

DATA

To read array data from the outputs, the system must

drive the CE and OE pins toVIL. CE is the power control

and selects the device. OE is the output control and gates

array data to the output pins. WE should remain at VIH.

ICC2 in the DC Characteristics table represents the

active current specification for the write mode.The "AC

Characteristics" section contains timing specification

table and timing diagrams for write operations.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory content

occurs during the power transition. No command is

necessary in this mode to obtain array data. Standard

microprocessor read cycles that assert valid address on

the device address inputs produce valid data on the device

data outputs.The device remains enabled for read access

until the command register contents are altered.

STANDBY MODE

When using both pins of CE and RESET, the device

enter CMOS Standby with both pins held at Vcc±0.3V.

IF CE and RESET are held at VIH, but not within the

range ofVCC ± 0.3V, the device will still be in the standby

mode, but the standby current will be larger.During Auto

Algorithm operation,Vcc active current (Icc2) is required

even CE = "H" until the operation is completed.The de-

vice can be read with standard access time (tCE) from

either of these standby modes, before it is ready to read

data.

WRITE COMMANDS/COMMAND

SEQUENCES

To program data to the device or erase sectors of memory

, the system must drive WE and CE to VIL, and OE to

VIH.

The device features an Unlock Bypass mode to facilitate

faster programming. Once the device enters the Unlock

Bypass mode, only two write cycles are required to

program a byte, instead of four. The "byte Program

Command Sequence" section has details on

programming data to the device using both standard and

Unlock Bypass command sequences.

OUTPUT DISABLE

With the OE input at a logic high level (VIH), output from

the devices are disabled.This will cause the output pins

to be in a high impedance state.

RESET OPERATION

An erase operation can erase one sector, multiple sectors

, or the entire device.Table indicates the address space

that each sector occupies. A "sector address" consists

of the address bits required to uniquely select a sector.

The "Writing specific address and data commands or

sequences into the command register initiates device

operations. Table 1 defines the valid register command

sequences.Writing incorrect address and data values or

writing them in the improper sequence resets the device

to reading array data. Section has details on erasing a

sector or the entire chip, or suspending/resuming the erase

operation.

The RESET pin provides a hardware method of resetting

the device to reading array data.When the RESET pin is

driven low for at least a period of tRP, the device

immediately terminates any operation in progress,

tristates all output pins, and ignores all read/write

commands for the duration of the RESET pulse. The

device also resets the internal state machine to reading

array data.The operation that was interrupted should be

reinitiated once the device is ready to accept another

command sequence, to ensure data integrity

Current is reduced for the duration of the RESET pulse.

When RESET is held at VSS±0.3V, the device draws

CMOS standby current (ICC4). If RESET is held at VIL

but not within VSS±0.3V, the standby current will be

greater.

After the system writes the "read silicon-ID" and "sector

protect verify" command sequence, the device enters

the "read silicon-ID" and "sector protect verify" mode.

The system can then read "read silicon-ID" and "sector

protect verify" codes from the internal register (which is

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MX29LV160T/B & MX29LV160AT/AB

The RESET pin may be tied to system reset circuitry. A

returns the device code of C4H/22C4H for MX29LV160AT,

49H/2249H for MX29LV160AB.

system reset would that also reset the Flash memory,

enabling the system to read the boot-up firmware from

the Flash memory.

The system must write the reset command to exit the

"Silicon-ID Read Command" code.

If RESET is asserted during a program or erase

operation, the RY/BY pin remains a "0" (busy) until the

internal reset operation is complete, which requires a

time of tREADY (during Embedded Algorithms). The

system can thus monitor RY/BY to determine whether

the reset operation is complete. If RESET is asserted

when a program or erase operation is completed within a

time of tREADY (not during Embedded Algorithms).The

system can read data tRH after the RESET pin returns

to VIH.

SET-UP AUTOMATIC CHIP/SECTOR ERASE

COMMANDS

Chip erase is a six-bus cycle operation. There are two

"unlock" write cycles. These are followed by writing the

"set-up" command 80H. Two more "unlock" write cy-

cles are then followed by the chip erase command 10H

or sector erase command 30H.

Refer to the AC Characteristics tables for RESET

parameters and to Figure 22 for the timing diagram.

The Automatic Chip Erase does not require the device

to be entirely pre-programmed prior to executing the Au-

tomatic Chip Erase. Upon executing the Automatic Chip

Erase, the device will automatically program and verify

the entire memory for an all-zero data pattern. When the

device is automatically verified to contain an all-zero

pattern, a self-timed chip erase and verify begin. The

erase and verify operations are completed when the data

on Q7 is "1" at which time the device returns to the

Read mode. The system is not required to provide any

control or timing during these operations.

READ/RESET COMMAND

The read or reset operation is initiated by writing the

read/reset command sequence into the command reg-

ister. Microprocessor read cycles retrieve array data.

The device remains enabled for reads until the command

register contents are altered.

If program-fail or erase-fail happen, the write of F0H will

reset the device to abort the operation. A valid com-

mand must then be written to place the device in the

desired state.

When using the Automatic Chip Erase algorithm, note

that the erase automatically terminates when adequate

erase margin has been achieved for the memory array

(no erase verification command is required).

If the Erase operation was unsuccessful, the data on

Q5 is "1" (see Table 8), indicating the erase operation

exceed internal timing limit.

SILICON-ID READ COMMAND

Flash memories are intended for use in applications where

the local CPU alters memory contents. As such, manu-

facturer and device codes must be accessible while the

device resides in the target system. PROM program-

mers typically access signature codes by raising A9 to

a high voltage (VID). However, multiplexing high volt-

age onto address lines is not generally desired system

design practice.

The automatic erase begins on the rising edge of the

last WE or CE pulse, whichever happens first in the

command sequence and terminates when either the data

on Q7 is "1" at which time the device returns to the

Read mode or the data on Q6 stops toggling for two

consecutive read cycles at which time the device re-

turns to the Read mode.

The MX29LV160T/B & MX29LV160AT/AB contains a Sili-

con-ID-Read operation to supple traditional PROM pro-

gramming methodology. The operation is initiated by

writing the read silicon ID command sequence into the

command register. Following the command write, a read

cycle with A1=VIL, A0=VIL retrieves the manufacturer

code of C2H/00C2H. A read cycle with A1=VIL, A0=VIH

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MX29LV160T/B & MX29LV160AT/AB

TABLE 7. SILICON ID CODE

Pins

A0

Word VIL

Byte VIL

A1

VIL 00H

VIL

Q15~Q8 Q7 Q6 Q5

Q4 Q3 Q2 Q1 Q0 Code(Hex)

Manufacture code

1

0

1

0

1

0

1

0

1

0

1

0

00C2H

X

C2H

Device code

Word VIH VIL 22H

Byte VIH VIL

Word VIH VIL 22H

22C4H

for MX29LV160AT

Device code

X

C4H

2249H

for MX29LV160AB

Sector Protection

Verification

Byte VIH VIL

X

49H

Word

Byte

X

VIH

01H (Protected)

00H (Unprotected)

READING ARRAY DATA

RESET COMMAND

Writing the reset command to the device resets the

device to reading array data. Address bits are don't care

for this command.

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data.The device is also ready to read array data

after completing an Automatic Program or Automatic

Erase algorithm.

The reset command may be written between the

sequence cycles in an erase command sequence before

erasing begins. This resets the device to reading array

data. Once erasure begins, however, the device ignores

reset commands until the operation is complete.

After the device accepts an Erase Suspend command,

the device enters the Erase Suspend mode. The system

can read array data using the standard read timings,

except that if it reads at an address within erase-

suspended sectors, the device outputs status data. After

completing a programming operation in the Erase

Suspend mode, the system may once again read array

data with the same exception. See erase Suspend/Erase

Resume Commands” for more information on this mode.

The system must issue the reset command to re-en-

able the device for reading array data if Q5 goes high, or

while in the "read silicon-ID" and "sector protect verify"

mode. See the "Reset Command" section, next.

The reset command may be written between the

sequence cycles in a program command sequence before

programming begins. This resets the device to reading

array data (also applies to programming in Erase

Suspend mode). Once programming begins, however,

the device ignores reset commands until the operation

is complete.

The reset command may be written between the

sequence cycles in an SILICON ID READ command

sequence. Once in the SILICON ID READ mode, the

reset command must be written to return to reading array

data (also applies to SILICON ID READ during Erase

Suspend).

If Q5 goes high during a program or erase operation,

writing the reset command returns the device to reading

array data (also applies during Erase Suspend).

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MX29LV160T/B & MX29LV160AT/AB

mand is issued during the sector erase operation, the

device requires a maximum 20us to suspend the sector

erase operation.However, when the Erase Suspend com-

mand is written during the sector erase time-out, the

device immediately terminates the time-out period and

suspends the erase operation. After this command has

been executed, the command register will initiate erase

suspend mode. The state machine will return to read

mode automatically after suspend is ready. At this time,

state machine only allows the command register to re-

spond to Erase Resume, program data to , or read data

from any sector not selected for erasure.

SECTOR ERASE COMMANDS

The Automatic Sector Erase does not require the de-

vice to be entirely pre-programmed prior to executing

the Automatic Sector Erase Set-up command and Au-

tomatic Sector Erase command. Upon executing the

Automatic Sector Erase command, the device will auto-

matically program and verify the sector(s) memory for

an all-zero data pattern. The system is not required to

provide any control or timing during these operations.

When the sector(s) is automatically verified to contain

an all-zero pattern, a self-timed sector erase and verify

begin. The erase and verify operations are complete

when either the data on Q7 is "1" at which time the de-

vice returns to the Read mode or the data on Q6 stops

toggling for two consecutive read cycles at which time

the device returns to the Read mode. The system is not

required to provide any control or timing during these

operations.

The system can determine the status of the program

operation using the Q7 or Q6 status bits, just as in the

standard program operation. After an erase-suspend pro-

gram operation is complete, the system can once again

read array data within non-suspended sectors.

ERASE RESUME

When using the Automatic sector Erase algorithm, note

that the erase automatically terminates when adequate

erase margin has been achieved for the memory array

(no erase verification command is required). Sector

erase is a six-bus cycle operation. There are two "un-

lock" write cycles. These are followed by writing the

set-up command 80H. Two more "unlock" write cycles

are then followed by the sector erase command 30H.

The sector address is latched on the falling edge of WE

or CE, whichever happens later, while the command

(data) is latched on the rising edge of WE or CE, which-

ever happens first. Sector addresses selected are

loaded into internal register on the sixth falling edge of

WE or CE, whichever happens later. Each successive

sector load cycle started by the falling edge of WE or

CE, whichever happens later must begin within 50us

from the rising edge of the preceding WE or CE, which-

ever happens first. Otherwise, the loading period ends

and internal auto sector erase cycle starts.(Monitor Q3

to determine if the sector erase timer window is still open,

see section Q3, Sector EraseTimer.) Any command other

than Sector Erase (30H) or Erase Suspend (B0H) during

the time-out period resets the device to read mode.

This command will cause the command register to clear

the suspend state and return back to Sector Erase mode

but only if an Erase Suspend command was previously

issued. Erase Resume will not have any effect in all

other conditions. Another Erase Suspend command can

be written after the chip has resumed erasing.However,

for MX29LV160T/B, a 10ms time delay must be required

after the erase resume command, if the system imple-

ments a endless erase suspend/resume loop, or the

number of erase suspend/resume is exceeded 1024

times. The erase times will be expended if the erase

behavior always be suspended. (Please refer to MXIC

Flash Application Note for details.) Please note that the

above 10ms time delay is not necessary for

MX29LV160AT/AB.

WORD/BYTE PROGRAM COMMAND SEQUENCE

The device programs one byte of data for each program

operation. The command sequence requires four bus

cycles, and is initiated by writing two unlock write cycles,

followed by the program set-up command. The program

address and data are written next, which in turn initiate

the Embedded Program algorithm. The system is not

required to provide further controls or timings.The device

automatically generates the program pulses and verifies

the programmed cell margin. Table 4 shows the address

and data requirements for the byte program command

sequence.

ERASE SUSPEND

This command only has meaning while the state ma-

chine is executing Automatic Sector Erase operation,

and therefore will only be responded during Automatic

Sector Erase operation. When the Erase Suspend Com-

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MX29LV160T/B & MX29LV160AT/AB

When the Embedded Program algorithm is complete,

During the Automatic Erase algorithm, Data Polling pro-

duces a "0" on Q7. When the Automatic Erase algo-

rithm is complete, or if the device enters the Erase Sus-

pend mode, Data Polling produces a "1" on Q7. This is

analogous to the complement/true datum output de-

scribed for the Automatic Program algorithm: the erase

function changes all the bits in a sector to "1" prior to

this, the device outputs the "complement,” or "0".” The

system must provide an address within any of the sec-

tors selected for erasure to read valid status information

on Q7.

the device then returns to reading array data and

addresses are no longer latched. The system can

determine the status of the program operation by using

Q7, Q6, or RY/BY. See "Write Operation Status" for

information on these status bits.

Any commands written to the device during the

Embedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the programming

operation.The Byte Program command sequence should

be reinitiated once the device has reset to reading array

data, to ensure data integrity.

After an erase command sequence is written, if all sec-

tors selected for erasing are protected, Data Polling on

Q7 is active for approximately 100 us, then the device

returns to reading array data. If not all selected sectors

are protected, the Automatic Erase algorithm erases the

unprotected sectors, and ignores the selected sectors

that are protected.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed from a

"0" back to a "1". Attempting to do so may halt the

operation and set Q5 to "1" ,” or cause the Data Polling

algorithm to indicate the operation was successful.

However, a succeeding read will show that the data is

still "0". Only erase operations can convert a "0" to a

"1".

When the system detects Q7 has changed from the

complement to true data, it can read valid data at Q7-Q0

on the following read cycles. This is because Q7 may

change asynchronously with Q0-Q6 while Output En-

able (OE) is asserted low.

WRITE OPERATION STATUS

The device provides several bits to determine the sta-

tus of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/

BY. Table 8 and the following subsections describe the

functions of these bits. Q7, RY/BY, and DQ6 each offer

a method for determining whether a program or erase

operation is complete or in progress. These three bits

are discussed first.

RY/BY:Ready/Busy

The RY/BY is a dedicated, open-drain output pin that

indicates whether an Automatic Erase/Program algorithm

is in progress or complete. The RY/BY status is valid

after the rising edge of the final WE or CE, whichever

happens first, in the command sequence. Since RY/BY

is an open-drain output, several RY/BY pins can be tied

together in parallel with a pull-up resistor to Vcc.

Q7: Data Polling

The Data Polling bit, Q7, indicates to the host system

whether an Automatic Algorithm is in progress or com-

pleted, or whether the device is in Erase Suspend. Data

Polling is valid after the rising edge of the finalWE pulse

in the program or erase command sequence.

If the output is low (Busy), the device is actively erasing

or programming. (This includes programming in the Erase

Suspend mode.) If the output is high (Ready), the de-

vice is ready to read array data (including during the

Erase Suspend mode), or is in the standby mode.

During the Automatic Program algorithm, the device out-

puts on Q7 the complement of the datum programmed

to Q7.This Q7 status also applies to programming dur-

ing Erase Suspend.When the Automatic Program algo-

rithm is complete, the device outputs the datum pro-

grammed to Q7.The system must provide the program

address to read valid status information on Q7. If a pro-

gram address falls within a protected sector, Data Poll-

ing on Q7 is active for approximately 1 us, then the de-

vice returns to reading array data.

Table 8 shows the outputs for RY/BY during write opera-

tion.

Q6:Toggle BIT I

Toggle Bit I on Q6 indicates whether an Automatic Pro-

gram or Erase algorithm is in progress or complete, or

whether the device has entered the Erase Suspend mode.

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MX29LV160T/B & MX29LV160AT/AB

Toggle Bit I may be read at any address, and is valid

cycles.) But Q2 cannot distinguish whether the sector

is actively erasing or is erase-suspended. Q6, by com-

parison, indicates whether the device is actively eras-

ing, or is in Erase Suspend, but cannot distinguish which

sectors are selected for erasure. Thus, both status bits

are required for sectors and mode information. Refer to

Table 7 to compare outputs for Q2 and Q6.

after the rising edge of the final WE or CE, whichever

happens first, in the command sequence (prior to the

program or erase operation), and during the sector time-

out.

During an Automatic Program or Erase algorithm opera-

tion, successive read cycles to any address cause Q6

to toggle.The system may use either OE or CE to con-

trol the read cycles.When the operation is complete, Q6

stops toggling.

Reading Toggle Bits Q6/ Q2

Whenever the system initially begins reading toggle bit

status, it must read Q7-Q0 at least twice in a row to

determine whether a toggle bit is toggling. Typically, the

system would note and store the value of the toggle bit

after the first read. After the second read, the system

would compare the new value of the toggle bit with the

first. If the toggle bit is not toggling, the device has

completed the program or erase operation. The system

can read array data on Q7-Q0 on the following read cycle.

After an erase command sequence is written, if all sec-

tors selected for erasing are protected, Q6 toggles and

returns to reading array data. If not all selected sectors

are protected, the Automatic Erase algorithm erases the

unprotected sectors, and ignores the selected sectors

that are protected.

The system can use Q6 and Q2 together to determine

whether a sector is actively erasing or is erase sus-

pended.When the device is actively erasing (that is, the

Automatic Erase algorithm is in progress), Q6 toggling.

When the device enters the Erase Suspend mode, Q6

stops toggling. However, the system must also use Q2

to determine which sectors are erasing or erase-sus-

pended. Alternatively, the system can use Q7.

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of Q5 is high

(see the section on Q5). If it is, the system should then

determine again whether the toggle bit is toggling, since

the toggle bit may have stopped toggling just as Q5 went

high. If the toggle bit is no longer toggling, the device

has successfully completed the program or erase op-

eration. If it is still toggling, the device did not complete

the operation successfully, and the system must write

the reset command to return to reading array data.

If a program address falls within a protected sector, Q6

toggles for approximately 2 us after the program com-

mand sequence is written, then returns to reading array

data.

Q6 also toggles during the erase-suspend-program mode,

and stops toggling once the Automatic Program algo-

rithm is complete.

The remaining scenario is that system initially determines

that the toggle bit is toggling and Q5 has not gone high.

The system may continue to monitor the toggle bit and

Q5 through successive read cycles, determining the sta-

tus as described in the previous paragraph. Alterna-

tively, it may choose to perform other system tasks. In

this case, the system must start at the beginning of the

algorithm when it returns to determine the status of the

operation.

Table 8 shows the outputs for Toggle Bit I on Q6.

Q2:Toggle Bit II

The "Toggle Bit II" on Q2, when used with Q6, indicates

whether a particular sector is actively erasing (that is,

the Automatic Erase algorithm is in process), or whether

that sector is erase-suspended. Toggle Bit II is valid

after the rising edge of the final WE or CE, whichever

happens first, in the command sequence.

Q5

ExceededTiming Limits

Q5 will indicate if the program or erase time has ex-

ceeded the specified limits (internal pulse count). Under

these conditions Q5 will produce a "1". This time-out

condition indicates that the program or erase cycle was

Q2 toggles when the system reads at addresses within

those sectors that have been selected for erasure. (The

system may use either OE or CE to control the read

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MX29LV160T/B & MX29LV160AT/AB

If this time-out condition occurs during the chip erase

operation, it specifies that the entire chip is bad or com-

bination of sectors are bad.

not successfully completed. Data Polling andToggle Bit

are the only operating functions of the device under this

condition.

If this time-out condition occurs during the byte program-

ming operation, it specifies that the entire sector con-

taining that byte is bad and this sector may not be re-

used, (other sectors are still functional and can be re-

used).

If this time-out condition occurs during sector erase op-

eration, it specifies that a particular sector is bad and it

may not be reused. However, other sectors are still func-

tional and may be used for the program or erase opera-

tion. The device must be reset to use other sectors.

Write the Reset command sequence to the device, and

then execute program or erase command sequence. This

allows the system to continue to use the other active

sectors in the device.

The time-out condition will not appear if a user tries to

program a non blank location without erasing. Please

note that this is not a device failure condition since the

device was incorrectly used.

Table 8. WRITE OPERATION STATUS

Status

Q7

Q6

Q5

Q3

Q2 RY/BY

(Note1)

(Note2)

Byte Program in Auto Program Algorithm

Auto Erase Algorithm

Q7

Toggle

0

N/A

1

No

0

Toggle

0

1

0

Toggle

0

1

Erase Suspend Read

(Erase Suspended Sector)

No

Toggle

N/A Toggle

In Progress

Erase Suspended Mode

Erase Suspend Read

Data

Q7

Data Data Data Data

1

0

(Non-Erase Suspended Sector)

Erase Suspend Program

Toggle

0

1

N/A N/A

Byte Program in Auto Program Algorithm

Q7

N/A

1

No

Toggle

Exceeded

Time Limits Auto Erase Algorithm

0

Toggle

1

Toggle

0

Erase Suspend Program

Q7

N/A N/A

Note:

1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further

details.

2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.

See "Q5: Exceeded Timing Limits " for more information.

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18

MX29LV160T/B & MX29LV160AT/AB

Q3

POWER SUPPLY DE COUPLING

Sector Erase Timer

In order to reduce power switching effect, each device

should have a 0.1uF ceramic capacitor connected be-

tween itsVCC and GND.

After the completion of the initial sector erase command

sequence, the sector erase time-out will begin. Q3 will

remain low until the time-out is complete. Data Polling

andToggle Bit are valid after the initial sector erase com-

mand sequence.

POWER-UP SEQUENCE

The MX29LV160T/B & MX29LV160AT/AB powers up in

the Read only mode. In addition, the memory contents

may only be altered after successful completion of the

predefined command sequences.

If Data Polling or theToggle Bit indicates the device has

been written with a valid erase command, Q3 may be

used to determine if the sector erase timer window is

still open. If Q3 is high ("1") the internally controlled

erase cycle has begun; attempts to write subsequent

commands to the device will be ignored until the erase

operation is completed as indicated by Data Polling or

Toggle Bit. If Q3 is low ("0"), the device will accept

additional sector erase commands. To insure the com-

mand has been accepted, the system software should

check the status of Q3 prior to and following each sub-

sequent sector erase command. If Q3 were high on the

second status check, the command may not have been

accepted.

TEMPORARY SECTOR UNPROTECT

This feature allows temporary unprotection of previously

protected sector to change data in-system.TheTempo-

rary Sector Unprotect mode is activated by setting the

RESET pin toVID (11.5V-12.5V). During this mode, for-

merly protected sectors can be programmed or erased

as un-protected sector. Once VID is remove from the

RESET pin. All the previously protected sectors are pro-

tected again.

DATA PROTECTION

SECTOR PROTECTION

The MX29LV160T/B & MX29LV160AT/AB is designed

to offer protection against accidental erasure or program-

ming caused by spurious system level signals that may

exist during power transition. During power up the de-

vice automatically resets the state machine in the Read

mode. In addition, with its control register architecture,

alteration of the memory contents only occurs after suc-

cessful completion of specific command sequences. The

device also incorporates several features to prevent in-

advertent write cycles resulting fromVCC power-up and

power-down transition or system noise.

The MX29LV160T/B & MX29LV160AT/AB features hard-

ware sector protection. This feature will disable both

program and erase operations for these sectors pro-

tected. To activate this mode, the programming equip-

ment must force VID on address pin A9 and OE (sug-

gest VID = 12V). Programming of the protection cir-

cuitry begins on the falling edge of the WE pulse and is

terminated on the rising edge. Please refer to sector pro-

tect algorithm and waveform.

To verify programming of the protection circuitry, the pro-

gramming equipment must forceVID on address pin A9

( with CE and OE atVIL andWE atVIH). When A1=VIH,

A0=VIL, A6=VIL, it will produce a logical "1" code at

device output Q0 for a protected sector. Otherwise the

device will produce 00H for the unprotected sector. In

this mode, the addresses, except for A1, are don't care.

Address locations with A1 = VIL are reserved to read

manufacturer and device codes. (Read Silicon ID)

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5ns (typical) on CE orWE will

not initiate a write cycle.

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE = VIL, CE

= VIH or WE = VIH. To initiate a write cycle CE and WE

must be a logical zero while OE is a logical one.

It is also possible to determine if the sector is protected

in the system by writing a Read Silicon ID command.

Performing a read operation with A1=VIH, it will produce

P/N:PM0866

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19

MX29LV160T/B & MX29LV160AT/AB

a logical "1" at Q0 for the protected sector.

The system must write the reset command to exit the

"Silicon-ID Read Command" code.

CHIP UNPROTECT

TheMX29LV160T/B&MX29LV160AT/ABalsofeatures

thechipunprotectmode,sothatallsectorsareunprotected

after chip unprotect is completed to incorporate any

changes in the code. It is recommended to protect all

sectors before activating chip unprotect mode.

Toactivatethismode,theprogrammingequipmentmust

forceVIDoncontrolpinOEandaddresspinA9. TheCE

pins must be set at VIL. Pins A6 must be set to VIH.

Refer to chip unprotect algorithm and waveform for the

chip unprotect algorithm. The unprotection mechanism

begins on the falling edge of the WE pulse and is

terminated on the rising edge.

It is also possible to determine if the chip is unprotected

in the system by writing the Read Silicon ID command.

PerformingareadoperationwithA1=VIH,itwillproduce

00H at data outputs(Q0-Q7) for an unprotected sector.

It is noted that all sectors are unprotected after the chip

unprotect algorithm is completed.

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20

MX29LV160T/B & MX29LV160AT/AB

OPERATING RATINGS

ABSOLUTE MAXIMUM RATINGS

StorageTemperature

Commercial (C) Devices

Plastic Packages . . . . . . . . . . . . . ..... -65^oC to +150^oC

Ambient Temperature (T^A). . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

AmbientTemperature

with Power Applied. . . . . . . . . . . . . .... -65^oC to +125^oC

Voltage with Respect to Ground

Ambient Temperature (T^A). . . . . . . . . . -40°C to +85°C

V^CCSupply Voltages

V^CCfor regulated voltage range . . . . . +3.0 V to 3.6 V

V^CCfor full voltage range. . . . . . . . . . . +2.7 V to 3.6 V

VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V

A9, OE, and

RESET (Note 2) . . . . . . . . . . . ....-0.5 V to +12.5 V

All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Operating ranges define those limits between which the

functionality of the device is guaranteed.

Notes:

1. Minimum DC voltage on input or I/O pins is -0.5 V.

During voltage transitions, input or I/O pins may over-

shoot VSS to -2.0 V for periods of up to 20 ns. See

Figure 6. Maximum DC voltage on input or I/O pins is

VCC +0.5 V. During voltage transitions, input or I/O

pins may overshoot to VCC +2.0 V for periods up to

20 ns.

2. Minimum DC input voltage on pins A9, OE, and

RESET is -0.5 V. During voltage transitions, A9, OE,

and RESET may overshootVSS to -2.0V for periods

of up to 20 ns. See Figure 6. Maximum DC input volt-

age on pin A9 is +12.5 V which may overshoot to

14.0 V for periods up to 20 ns.

3.No more than one output may be shorted to ground at

a time. Duration of the short circuit should not be

greater than one second.

Stresses above those listed under "Absolute Maximum

Ratings" may cause permanent damage to the device.

This is a stress rating only; functional operation of the

device at these or any other conditions above those in-

dicated in the operational sections of this data sheet is

not implied. Exposure of the device to absolute maxi-

mum rating conditions for extended periods may affect

device reliability.

P/N:PM0866

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21

MX29LV160T/B & MX29LV160AT/AB

CAPACITANCE TA = 25^oC, f = 1.0 MHz

SYMBOL

CIN1

PARAMETER

MIN.

TYP

MAX.

8

UNIT

pF

CONDITIONS

VIN = 0V

Input Capacitance

Control Pin Capacitance

Output Capacitance

CIN2

12

pF

VIN = 0V

COUT

12

pF

VOUT = 0V

READ OPERATION

Table 9. DC CHARACTERISTICS TA = -40^oC TO 85^oC, VCC = 3V±10%

MX29LV160T/B & MX29LV160AT/AB-70R, MX29LV160T/B & MX29LV160AT/AB-90R)

(VCC=3.0~3.6V for

Symbol PARAMETER

MIN.

TYP

MAX.

±1

35

±1

16

4

UNIT

uA

CONDITIONS

ILI

Input Leakage Current

VIN = VSS to VCC

ILIT

ILO

ICC1

A9 Input Leakage Current

Output Leakage Current

VCC Active Read Current

uA

VCC=VCC max; A9=12.5V

VOUT = VSS to VCC, VCC=VCC max

uA

9

2

mA

uA

CE=VIL, OE=VIH

(Byte Mode)

@5MHz

@1MHz

@5MHz

@1MHz

9

16

4

CE=VIL, OE=VIH

(Word Mode)

2

ICC2

ICC3

ICC4

VCC Active write Currect

VCC Standby Currect

During Reset (See Conditions)

Automatic sleep mode

Input Low Voltage (Note 1)

Input High Voltage

20

0.2

30

5

CE=VIL, OE=VIH

CE; RESET=VCC ±0.3V

RESET=VSS ±0.3V

5

uA

ICC5

VIL

0.2

5

uA

V

VIH=VCC ±0.3V;VIL=VSS ±0.3V

-0.5

0.8

VIH

VID

0.7xVCC

VCC+ 0.3

V

Voltage for Automatic

Select and Temporary

Sector Unprotect

11.5

12.5

0.45

V

VCC=3.3V

VOL

Output Low Voltage

Output High Voltage (TTL)

Output High Voltage

(CMOS)

IOL = 4.0mA, VCC= VCC min

IOH = -2mA, VCC=VCC min

IOH = -100uA, VCC min

VOH1

VOH2

0.85xVCC

VCC-0.4

VLKO

Low VCC Lock-out

Voltage

2.3

2.5

V

NOTES:

1.VIL min. = -1.0V for pulse width is equal to or less than 50 ns.

VIL min. = -2.0V for pulse width is equal to or less than 20 ns.

2.VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns

If VIH is over the specified maximum value, read operation cannot be guaranteed.

3.Automatic sleep mode enable the low power mode when addresses remain stable for tACC +30ns.

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22

MX29LV160T/B & MX29LV160AT/AB

AC CHARACTERISTICS

TA = -40^oC to 85^oC,VCC = 2.7V~3.6V (VCC=3.0~3.6V for MX29LV160T/

B & MX29LV160AT/AB-70R, MX29LV160T/B & MX29LV160AT/AB-90R)

Table 10. READ OPERATIONS

29LV160AT/B-70

29LV160AT/B-70R (Note3)

Symbol PARAMETER

MIN.

MAX.

70

MIN.

MAX.

70

UNIT CONDITIONS

tRC

tACC

tCE

Read Cycle Time (Note 1)

ns

Address to Output Delay

CE to Output Delay

70

ns

CE=OE=VIL

OE=VIL

70

tOE

OE to Output Delay

30

CE=VIL

tDF

OE High to Output Float (Note2)

Output Enable Read

0

25

0

25

CE=VIL

tOEH

0

Hold Time

Toggle and Data Polling 10

10

0

tOH

Address to Output hold

0

CE=OE=VIL

29LV160AT/B-90

29LV160AT/B-90R (Note3)

Symbol PARAMETER

MIN.

MAX.

90

MIN.

MAX.

90

UNIT CONDITIONS

tRC

tACC

tCE

Read Cycle Time (Note 1)

ns

Address to Output Delay

CE to Output Delay

90

ns

CE=OE=VIL

OE=VIL

90

tOE

OE to Output Delay

35

CE=VIL

tDF

OE High to Output Float (Note2)

Output Enable Read

0

30

0

30

CE=VIL

tOEH

0

Hold Time

Toggle and Data Polling 10

10

0

tOH

Address to Output hold

0

CE=OE=VIL

NOTE:

TEST CONDITIONS:

1. Not 100% tested.

• Input pulse levels: 0V/3.0V.

2. tDF is defined as the time at which the output achieves

the open circuit condition and data is no longer driven.

3. 29LV160AT/B-70R & 29LV160AT/B-90R operates at

VCC=3.0~3.6V.

• Input rise and fall times is equal to or less than 5ns.

• Outputload:1TTLgate+100pF(Includingscopeand

jig),for29LV160AT/B-90.1TTL gate+30pF(Including

scopeandjig)for29LV160AT/B-70and29LV160AT/B-

70R.

• Reference levels for measuring timing: 1.5V.

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23

MX29LV160T/B & MX29LV160AT/AB

SWITCHING TEST CIRCUITS

DEVICE UNDER

TEST

2.7K ohm

+3.3V

CL

6.2K ohm

DIODES=IN3064

OR EQUIVALENT

CL=100pF Including jig capacitance

SWITCHING TEST WAVEFORMS

3.0V

TEST POINTS

0V

INPUT

OUTPUT

AC TESTING: Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0".

Input pulse rise and fall times are < 5ns.

P/N:PM0866

REV. 3.3, MAR. 08, 2002

24

MX29LV160T/B & MX29LV160AT/AB

Figure 1. READ TIMING WAVEFORMS

tRC

VIH

VIL

ADD Valid

Addresses

tACC

tCE

VIH

VIL

CE

VIH

VIL

WE

tOE

tDF

tOEH

VIH

VIL

OE

tACC

tOH

HIGH Z

VOH

VOL

Outputs

DATA Valid

VIH

VIL

RESET

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REV. 3.3, MAR. 08, 2002

25

MX29LV160T/B & MX29LV160AT/AB

AC CHARACTERISTICS

TA = -40^oC to 85^oC,VCC = 2.7V~3.6V (VCC=3.0~3.6V for MX29LV160T/

B & MX29LV160AT/AB-70R, MX29LV160T/B & MX29LV160AT/AB-90R)

Table 11. Erase/Program Operations

29LV160AT/B-70(R) 29LV160AT/B-90(R)

SYMBOL

tWC

PARAMETER

MIN.

70

0

MAX.

MIN.

90

0

MAX.

UNIT

ns

Write Cycle Time (Note 1)

Address Setup Time

tAS

ns

tAH

Address Hold Time

45

35

0

45

0

ns

tDS

Data Setup Time

ns

tDH

Data Hold Time

ns

tOES

tGHWL

Output Enable Setup Time

Read Recovery Time Before Write

(OE High to WE Low)

0

ns

0

ns

tCS

CE Setup Time

0

ns

us

tCH

CE Hold Time

0

tWP

Write Pulse Width

35

tWPH

tWHWH1

Write Pulse Width High

ProgrammingOperation(Note2)

(Byte/Wordprogramtime)

Sector Erase Operation (Note 2)

VCC Setup Time (Note 1)

Recovery Time from RY/BY

Sector Erase Valid to RY/BY Delay

Chip Erase Valid to RY/BY Delay

Program Valid to RY/BY Delay

Write pulse width for sector

protect (A9, OE Control)

Write pulse width for sector

unprotect (A9, OE Control)

30

9/11(typ.)

tWHWH2

tVCS

0.7(typ.)

sec

us

ns

50

0

50

0

tRB

tBUSY

90

tWPP1

tWPP2

100ns

10us(typ.) 100ns

10us(typ.)

12ms(typ.) 100ns

12ms(typ.)

NOTES:

1. Not 100% tested.

2.See the "Erase and Programming Performance" section for more information.

P/N:PM0866

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26

MX29LV160T/B & MX29LV160AT/AB

AC CHARACTERISTICS

TA = -40^oC to 85^oC,VCC = 2.7V~3.6V (VCC=3.0~3.6V for MX29LV160T/

B & MX29LV160AT/AB-70R, MX29LV160T/B & MX29LV160AT/AB-90R)

Table 12. Alternate CE Controlled Erase/Program Operations

29LV160AT/B-70(R)

29LV160AT/B-90(R)

SYMBOL

tWC

PARAMETER

MIN.

MAX.

MIN.

MAX.

UNIT

ns

Write CycleTime (Note 1)

Address SetupTime

Address HoldTime

Data SetupTime

70

90

tAS

0

ns

tAH

45

ns

tDS

35

45

ns

tDH

Data HoldTime

0

ns

tOES

tGHEL

tWS

Output Enable SetupTime

Read RecoveryTime BeforeWrite

WE Setup Time

0

ns

0

ns

0

ns

tWH

WE HoldTime

0

ns

tCP

CE Pulse Width

35

ns

tCPH

tWHWH1

CE Pulse Width High

30

ns

Programming

Byte

9(Typ.)

11(Typ.)

0.7(Typ.)

9(Typ.)

11(Typ.)

0.7(Typ.)

us

Operation(note2)

Word

us

tWHWH2

Sector Erase Operation (note2)

sec

NOTE:

1. Not 100% tested.

2.See the "Erase and Programming Performance" section for more information.

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27

MX29LV160T/B & MX29LV160AT/AB

Figure 2. COMMAND WRITE TIMING WAVEFORM

VCC

3V

VIH

VIL

Addresses

ADD Valid

tAH

tAS

VIH

VIL

WE

CE

tOES

tWPH

tWP

tCWC

VIH

VIL

tCS

tCH

tDH

VIH

VIL

OE

tDS

VIH

VIL

Data

DIN

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REV. 3.3, MAR. 08, 2002

28

MX29LV160T/B & MX29LV160AT/AB

AUTOMATIC PROGRAMMING TIMING WAVEFORM

ing after automatic programming starts. Device outputs

DATA during programming and DATA after programming

on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling,

timing waveform)

One byte data is programmed. Verify in fast algorithm

and additional verification by external control are not re-

quired because these operations are executed automati-

cally by internal control circuit. Programming comple-

tion can be verified by DATA polling or toggle bit check-

Figure 3. AUTOMATIC PROGRAMMING TIMING WAVEFORM

Program Command Sequence(last two cycle)

Read Status Data (last two cycle)

tWC

tAS

PA

555h

PA

Address

tAH

CE

tCH

tGHWL

OE

tWHWH1

tWP

WE

tCS

tWPH

tDS tDH

Status

A0h

PD

DOUT

Data

tBUSY

tRB

RY/BY

tVCS

VCC

NOTES:

1.PA=Program Address, PD=Program Data, DOUT is the true data the program address

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MX29LV160T/B & MX29LV160AT/AB

Figure 4. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data A0H Address 555H

Write Program Data/Address

Data Poll

Increment

Address

from system

No

Verify Word Ok ?

YES

Last Address ?

YES

Auto Program Completed

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30

MX29LV160T/B & MX29LV160AT/AB

Figure 5. CE CONTROLLED PROGRAMTIMINGWAVEFORM

PA for program

555 for program

2AA for erase

SA for sector erase

555 for chip erase

Data Polling

Address

PA

tWC

tWH

tAS

tAH

WE

OE

tGHEL

tCP

tWHWH1 or 2

CE

tWS

tDS

tCPH

tBUSY

tDH

DOUT

DQ7

Data

PD for program

30 for sector erase

10 for chip erase

A0 for program

55 for erase

tRH

RESET

RY/BY

NOTES:

1.PA=Program Address, PD=Program Data, DOUT=Data Out, DQ7=complement of data written to device.

2.Figure indicates the last two bus cycles of the command sequence.

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31

MX29LV160T/B & MX29LV160AT/AB

AUTOMATIC CHIP ERASE TIMING WAVEFORM

All data in chip are erased. External erase verification is

not required because data is verified automatically by

internal control circuit. Erasure completion can be veri-

fied by DATA polling or toggle bit checking after auto-

matic erase starts. Device outputs 0 during erasure

and 1 after erasure on Q7. (Q6 is for toggle bit; see toggle

bit, DATA polling, timing waveform)

Figure 6. AUTOMATIC CHIP ERASE TIMING WAVEFORM

Erase Command Sequence(last two cycle)

Read Status Data

VA

tWC

tAS

VA

2AAh

555h

Address

tAH

CE

tCH

tGHWL

OE

tWHWH2

tWP

WE

tCS

tWPH

tDS tDH

In

Progress

55h

10h

Complete

Data

tBUSY

tRB

RY/BY

tVCS

VCC

NOTES:

SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").

P/N:PM0866

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MX29LV160T/B & MX29LV160AT/AB

Figure 7. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 80H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 10H Address 555H

Data Poll from System

NO

Data=FFh ?

YES

Auto Chip Erase Completed

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33

MX29LV160T/B & MX29LV160AT/AB

AUTOMATIC SECTOR ERASE TIMING WAVEFORM

Sector indicated by A12 to A19 are erased. External

erase verify is not required because data are verified

automatically by internal control circuit. Erasure comple-

tion can be verified by DATA polling or toggle bit check-

ing after automatic erase starts. Device outputs 0 dur-

ing erasure and 1 after erasure on Q7. (Q6 is for toggle

bit; see toggle bit, DATA polling, timing waveform)

Figure 8. AUTOMATIC SECTOR ERASE TIMING WAVEFORM

Erase Command Sequence(last two cycle)

Read Status Data

tWC

tAS

VA

2AAh

SA

Address

tAH

CE

tCH

tGHWL

OE

tWHWH2

tWP

WE

tCS

tWPH

tDS tDH

In

Progress

55h

30h

Complete

Data

tBUSY

tRB

RY/BY

tVCS

VCC

NOTES:

SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").

P/N:PM0866

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34

MX29LV160T/B & MX29LV160AT/AB

Figure 9. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 80H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 30H Sector Address

NO

Last Sector

to Erase

YES

Data Poll from System

NO

Data=FFh

YES

Auto Sector Erase Completed

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35

MX29LV160T/B & MX29LV160AT/AB

Figure 10. ERASE SUSPEND/ERASE RESUME FLOWCHART

START

Write Data B0H

ERASE SUSPEND

NO

Toggle Bit checking Q6

not toggled

YES

Read Array or

Program

Reading or

NO

Programming End

YES

Write Data 30H

Delay 10ms (note)

Continue Erase

ERASE RESUME

Another

NO

Erase Suspend ?

YES

Note:It's only for a certain condition of MX29LV160T/B.If the system implements an endless erase suspend/resume

loop, or the number of erase suspend/resume is exceeded 1024 times, then the 10ms time delay must be put into

consideration. Please note that the 10ms time delay is not necessary for MX29LV160AT/AB.

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36

MX29LV160T/B & MX29LV160AT/AB

Figure 11. IN-SYSTEM SECTOR PROTECT/UNPROTECT TIMING WAVEFORM (RESET Control)

VID

VIH

RESET

SA, A6

A1, A0

Valid*

Sector Protect or Sector Unprotect

Verify

40h

Status

Data

60h

Sector Protect =150us

Sector Unprotect =15ms

1us

CE

WE

OE

Note: When sector protect, A6=0, A1=1, A0=0. When sector unprotect, A6=1, A1=1, A0=0.

P/N:PM0866

REV. 3.3, MAR. 08, 2002

37

MX29LV160T/B & MX29LV160AT/AB

Figure 12. SECTOR PROTECT TIMING WAVEFORM (A9, OE Control)

A1

A6

12V

5V

A9

tVLHT

Verify

12V

5V

OE

tVLHT

tWPP 1

WE

CE

tOESP

Data

01H

F0H

tOE

A19-A12

Sector Address

P/N:PM0866

REV. 3.3, MAR. 08, 2002

38

MX29LV160T/B & MX29LV160AT/AB

Figure 13. SECTOR PROTECTION ALGORITHM (A9, OE Control)

START

Set Up Sector Addr

PLSCNT=1

OE=VID,A9=VID,CE=VIL

A6=VIL

Activate WE Pulse

Time Out 150us

Set WE=VIH, CE=OE=VIL

A9 should remain VID

.

Read from Sector

Addr=SA, A1=1

No

Data=01H?

PLSCNT=32?

Yes

Device Failed

Yes

Protect Another

Sector?

Remove VID from A9

Write Reset Command

Sector Protection

Complete

P/N:PM0866

REV. 3.3, MAR. 08, 2002

39

MX29LV160T/B & MX29LV160AT/AB

Figure 14. IN-SYSTEM SECTOR PROTECTION ALGORITHM WITH RESET=VID

START

PLSCNT=1

RESET=VID

Wait 1us

No

Temporary Sector

Unprotect Mode

First Write

Cycle=60H

Yes

Set up sector address

Write 60H to sector address

with A6=0, A1=1, A0=0

Wait 150us

Verify sector protect :

write 40H with A6=0,

A1=1, A0=0

Increment PLSCNT

Reset PLSCNT=1

Read from sector address

No

PLSCNT=25?

Data=01H ?

Yes

Device failed

Yes

Protect another

sector?

No

Remove VID from RESET

Write reset command

Sector protect complete

P/N:PM0866

REV. 3.3, MAR. 08, 2002

40

MX29LV160T/B & MX29LV160AT/AB

Figure 15. IN-SYSTEM SECTOR UNPROTECTION ALGORITHM WITH RESET=VID

START

PLSCNT=1

RESET=VID

Wait 1us

No

Temporary Sector

Unprotect Mode

First Write

Cycle=60H ?

Yes

All sector

Protect all sectors

protected?

Yes

Set up first sector address

Sector unprotect :

write 60H with

A6=1, A1=1, A0=0

Wait 50ms

Verify sector unprotect

write 40H to sector address

with A6=1, A1=1, A0=0

Increment PLSCNT

Read from sector address

with A6=1, A1=1, A0=0

No

Set up next sector address

PLSCNT=1000?

Data=00H ?

Yes

Device failed

Yes

Last sector

verified?

No

Remove VID from RESET

Write reset command

Sector unprotect complete

P/N:PM0866

REV. 3.3, MAR. 08, 2002

41

MX29LV160T/B & MX29LV160AT/AB

Figure 16. TIMING WAVEFORM FOR CHIP UNPROTECTION (A9, OE Control)

A1

12V

Vcc 3V

A9

A6

tVLHT

Verify

12V

Vcc 3V

OE

tVLHT

tWPP 2

WE

CE

tOESP

Data

00H

F0H

tOE

A19-A12

Sector Address

Notes: tVLHT (Voltage transition time)=4us min.

tWPP1 (Write pulse width for sector protect)=100ns min.

tWPP2 (Write pulse width for sector unprotect)=100ns min.

tOESP (OE setup time to WE active)=4us min.

P/N:PM0866

REV. 3.3, MAR. 08, 2002

42

MX29LV160T/B & MX29LV160AT/AB

Figure 17. CHIP UNPROTECTION ALGORITHM (A9, OE Control)

START

Protect All Sectors

PLSCNT=1

Set OE=A9=VID

CE=VIL,A6=1

Activate WE Pulse

Time Out 50ms

Increment

PLSCNT

Set OE=CE=VIL

A9=VID,A1=1

Set Up First Sector Addr

Read Data from Device

No

Data=00H?

Yes

PLSCNT=1000?

Increment

Sector Addr

Yes

Device Failed

No

All sectors have

been verified?

Yes

Remove VID from A9

Write Reset Command

Chip Unprotect

Complete

* It is recommended before unprotect whole chip, all sectors should be protected in advance.

P/N:PM0866

REV. 3.3, MAR. 08, 2002

43

MX29LV160T/B & MX29LV160AT/AB

WRITE OPERATION STATUS

Figure 18. DATA POLLING ALGORITHM

Start

Read Q7~Q0

Add.=VA(1)

Yes

Q7 = Data ?

No

Q5 = 1 ?

Yes

Read Q7~Q0

Add.=VA

Yes

Q7 = Data ?

(2)

No

FAIL

Pass

NOTE : 1.VA=Valid address for programming

2.Q7 should be re-checked even Q5="1" because Q7 may change

simultaneously with Q5.

P/N:PM0866

REV. 3.3, MAR. 08, 2002

44

MX29LV160T/B & MX29LV160AT/AB

Figure 19. TOGGLE BIT ALGORITHM

Start

Read Q7-Q0

(Note 1)

NO

Toggle Bit Q6 =

Toggle ?

YES

NO

Q5= 1?

YES

Read Q7~Q0 Twice

(Note 1,2)

NO

Toggle bit Q6=

Toggle?

YES

Program/Erase Operation

Not Complete,Write

Reset Command

Program/Erase

operation Complete

Note:1.Read toggle bit twice to determine whether or not it is toggling.

2. Recheck toggle bit because it may stop toggling as Q5 change to "1".

P/N:PM0866

REV. 3.3, MAR. 08, 2002

45

MX29LV160T/B & MX29LV160AT/AB

Figure 20. Data Polling Timings (During Automatic Algorithms)

tRC

VA

Address

CE

tACC

tCE

tCH

tOE

OE

tOEH

tDF

WE

tOH

High Z

Complement

Status Data

Complement

Status Data

True

Valid Data

DQ7

Q0-Q6

tBUSY

RY/BY

NOTES:

VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data read cycle.

P/N:PM0866

REV. 3.3, MAR. 08, 2002

46

MX29LV160T/B & MX29LV160AT/AB

Figure 21. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)

tRC

VA

tACC

tCE

VA

Address

CE

tCH

tOE

OE

tDF

tOEH

WE

tOH

High Z

Valid Status

(second read)

Valid Status

(first raed)

Valid Data

Q6/Q2

(stops toggling)

tBUSY

RY/BY

NOTES:

VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle, and

array data read cycle.

P/N:PM0866

REV. 3.3, MAR. 08, 2002

47

MX29LV160T/B & MX29LV160AT/AB

Table 13. AC CHARACTERISTICS

Parameter Std Description

Test Setup All Speed Options Unit

tREADY1

tREADY2

RESET PIN Low (During Automatic Algorithms)

MAX

20

us

to Read or Write (See Note)

RESET PIN Low (NOT During Automatic

Algorithms) to Read orWrite (See Note)

RESET Pulse Width (During Automatic Algorithms)

RESET HighTime Before Read (See Note)

RY/BY Recovery Time (to CE, OE go low)

MAX

500

ns

tRP

tRH

tRB

MIN

500

50

0

ns

Note:Not 100% tested

Figure 22. RESET TIMING WAVEFORM

RY/BY

CE, OE

tRH

RESET

tRP

tReady2

Reset Timing NOT during Automatic Algorithms

tReady1

RY/BY

tRB

CE, OE

RESET

tRP

Reset Timing during Automatic Algorithms

P/N:PM0866

REV. 3.3, MAR. 08, 2002

48

MX29LV160T/B & MX29LV160AT/AB

AC CHARACTERISTICS

WORD/BYTE CONFIGURATION (BYTE)

Parameter

Description

Speed Options

Unit

JEDEC Std

-70 (R)

-90 (R)

tELFL/tELFH CE to BYTE Switching Low or High

Max

Min

5

ns

tFLQZ

tFHQV

BYTE Switching Low to Output HIGH Z

BYTE Switching High to Output Active

25

70

30

90

Figure 23. BYTE TIMING WAVEFORM FOR READ OPERATIONS (BYTE switching from byte

mode to word mode)

CE

OE

tELFH

BYTE

DOUT

(Q0-Q7)

DOUT

(Q0-Q14)

Q0~Q14

Q15/A-1

DOUT

(Q15)

VA

tFHQV

P/N:PM0866

REV. 3.3, MAR. 08, 2002

49

MX29LV160T/B & MX29LV160AT/AB

Figure 24. BYTE TIMING WAVEFORM FOR READ OPERATIONS (BYTE switching from word

mode to byte mode)

CE

OE

tELFH

BYTE

DOUT

(Q0-Q14)

DOUT

(Q0-Q7)

Q0~Q14

Q15/A-1

DOUT

(Q15)

VA

tFLQZ

Figure 25. BYTE TIMING WAVEFORM FOR PROGRAM OPERATIONS

CE

The falling edge of the last WE signal

WE

BYTE

tAS

tAH

P/N:PM0866

REV. 3.3, MAR. 08, 2002

50

MX29LV160T/B & MX29LV160AT/AB

Table 14. TEMPORARY SECTOR UNPROTECT

Parameter Std. Description

Test Setup All Speed Options Unit

tVIDR

tRSP

VID Rise and Fall Time (See Note)

RESET SetupTime forTemporary Sector Unprotect

Min

500

4

ns

us

Note:

Not 100% tested

Figure 26. TEMPORARY SECTOR UNPROTECT TIMING DIAGRAM

12V

RESET

0 or Vcc

Program or Erase Command Sequence

tVIDR

CE

WE

tRSP

RY/BY

Figure 27. Q6 vs Q2 for Erase and Erase Suspend Operations

Enter Embedded

Erasing

Erase

Enter Erase

Erase

Suspend

Suspend Program

Resume

Erase

Erase Suspend

Read

Erase

WE

Q6

Suspend

Program

Complete

Q2

NOTES:

The system can use OE or CE to toggle Q2/Q6, Q2 toggles only when read at an address within an erase-suspended

P/N:PM0866

REV. 3.3, MAR. 08, 2002

51

MX29LV160T/B & MX29LV160AT/AB

Figure 28. TEMPORARY SECTOR UNPROTECT ALGORITHM

Start

RESET = VID (Note 1)

Perform Erase or Program Operation

Operation Completed

RESET = VIH

Temporary Sector Unprotect Completed(Note 2)

Note :

1. All protected sectors are temporary unprotected.

VID=11.5V~12.5V

2. All previously protected sectors are protected again.

P/N:PM0866

REV. 3.3, MAR. 08, 2002

52

MX29LV160T/B & MX29LV160AT/AB

Figure 29. ID CODE READ TIMING WAVEFORM

VCC

3V

VID

VIH

VIL

ADD

A9

VIH

VIL

ADD

A0

tACC

VIH

VIL

A1

ADD

A2-A8

VIH

A10-A19 VIL

CE

VIH

VIL

VIH

VIL

tCE

WE

OE

tOE

VIH

VIL

tDF

tOH

VIH

VIL

DATA

Q0-Q15

DATA OUT

C4H/49H (Byte)

C2H/00C2H

22C4H/2249H (Word)

P/N:PM0866

REV. 3.3, MAR. 08, 2002

53

MX29LV160T/B & MX29LV160AT/AB

ERASE AND PROGRAMMING PERFORMANCE (1)

LIMITS

TYP.(2)

PARAMETER

MIN.

MAX.(3)

UNITS

Sector Erase Time

0.7

25

9

15

sec

Chip Erase Time

Byte Programming Time

Word Programming Time

Chip Programming Time

300

360

54

us

11

18

12

us

Byte Mode

Word Mode

sec

36

sec

Erase/Program Cycles

100,000

Cycles

Note: 1.Not 100% Tested, Excludes external system level over head.

2.Typical values measured at 25°C, 3V.

3.Maximum values measured at 25°C, 2.7V.

LATCHUP CHARACTERISTICS

MIN.

-1.0V

MAX.

Input Voltage with respect to GND on all pins except I/O pins

Input Voltage with respect to GND on all I/O pins

Current

12.5V

Vcc + 1.0V

+100mA

-1.0V

-100mA

Includes all pins except Vcc. Test conditions: Vcc = 3.0V, one pin at a time.

P/N:PM0866

REV. 3.3, MAR. 08, 2002

54

MX29LV160T/B & MX29LV160AT/AB

ORDERING INFORMATION

PART NO.

ACCESSTIME

OPERATING CURRENT STANDBY CURRENT PACKAGE

(ns)

70

MAX.(mA)

MAX.(uA)

MX29LV160TMC-70

MX29LV160BMC-70

MX29LV160TMC-90

MX29LV160BMC-90

MX29LV160TTC-70

30

5

44 Pin SOP

70

44 Pin SOP

90

44 Pin SOP

90

44 Pin SOP

70

48 Pin TSOP

(NormalType)

48 Pin TSOP

(NormalType)

48 Pin TSOP

(NormalType)

48 Pin TSOP

(NormalType)

48 Pin TSOP

(NormalType)

48 Pin TSOP

(NormalType)

48 Pin TSOP

(NormalType)

48 Pin TSOP

(NormalType)

48 Pin TSOP

(NormalType)

48 Pin TSOP

(NormalType)

48 Pin TSOP

(NormalType)

48 Pin TSOP

(NormalType)

48 Pin TSOP

(NormalType)

48 Pin TSOP

(NormalType)

48 Pin TSOP

(NormalType)

48 Pin TSOP

(NormalType)

MX29LV160BTC-70

MX29LV160TTC-90

MX29LV160BTC-90

MX29LV160TTI-70

MX29LV160BTI-70

MX29LV160TTI-90

MX29LV160BTI-90

MX29LV160TTC-70R

MX29LV160BTC-70R

MX29LV160TTI-70R

MX29LV160BTI-70R

MX29LV160TTC-90R

MX29LV160BTC-90R

MX29LV160TTI-90R

MX29LV160BTI-90R

70

90

70

90

70

90

30

5

P/N:PM0866

REV. 3.3, MAR. 08, 2002

55

MX29LV160T/B & MX29LV160AT/AB

PART NO.

ACCESSTIME

OPERATING CURRENT STANDBY CURRENT PACKAGE

(ns)

70

90

70

90

70

90

70

90

MAX.(mA)

MAX.(uA)

MX29LV160TXBC-70

MX29LV160BXBC-70

MX29LV160TXBC-90

MX29LV160BXBC-90

MX29LV160TXBC-70R

MX29LV160BXBC-70R

MX29LV160TXBC-90R

MX29LV160BXBC-90R

MX29LV160TXBI-70

MX29LV160BXBI-70

MX29LV160TXBI-90

MX29LV160BXBI-90

MX29LV160TXBI-70R

MX29LV160BXBI-70R

MX29LV160TXBI-90R

MX29LV160BXBI-90R

30

5

48 Ball CSP

P/N:PM0866

REV. 3.3, MAR. 08, 2002

56

MX29LV160T/B & MX29LV160AT/AB

PART NO.

ACCESSTIME

OPERATING CURRENT STANDBY CURRENT PACKAGE

(ns)

70

MAX.(mA)

MAX.(uA)

MX29LV160ATMC-70

MX29LV160ABMC-70

MX29LV160ATMC-90

MX29LV160ABMC-90

MX29LV160ATTC-70

30

5

44 Pin SOP

70

44 Pin SOP

90

44 Pin SOP

90

44 Pin SOP

70

48 Pin TSOP

(NormalType)

48 Pin TSOP

(NormalType)

48 Pin TSOP

(NormalType)

48 Pin TSOP

(NormalType)

48 Pin TSOP

(NormalType)

48 Pin TSOP

(NormalType)

48 Pin TSOP

(NormalType)

48 Pin TSOP

(NormalType)

48 Pin TSOP

(NormalType)

48 Pin TSOP

(NormalType)

48 Pin TSOP

(NormalType)

48 Pin TSOP

(NormalType)

48 Pin TSOP

(NormalType)

48 Pin TSOP

(NormalType)

48 Pin TSOP

(NormalType)

48 Pin TSOP

(NormalType)

MX29LV160ABTC-70

MX29LV160ATTC-90

MX29LV160ABTC-90

MX29LV160ATTI-70

MX29LV160ABTI-70

MX29LV160ATTI-90

MX29LV160ABTI-90

MX29LV160ATTC-70R

MX29LV160ABTC-70R

MX29LV160ATTI-70R

MX29LV160ABTI-70R

MX29LV160ATTC-90R

MX29LV160ABTC-90R

MX29LV160ATTI-90R

MX29LV160ABTI-90R

70

90

70

90

70

90

30

5

P/N:PM0866

REV. 3.3, MAR. 08, 2002

57

MX29LV160T/B & MX29LV160AT/AB

PART NO.

ACCESSTIME

OPERATING CURRENT STANDBY CURRENT PACKAGE

(ns)

MAX.(mA)

MAX.(uA)

MX29LV160ATXBC-70

MX29LV160ABXBC-70

MX29LV160ATXEC-70

MX29LV160ABXEC-70

MX29LV160ATXBC-90

MX29LV160ABXBC-90

MX29LV160ATXEC-90

MX29LV160ABXEC-90

MX29LV160ATXBC-70R

MX29LV160ABXBC-70R

MX29LV160ATXBC-90R

MX29LV160ABXBC-90R

MX29LV160ATXBI-70

MX29LV160ABXBI-70

MX29LV160ATXEI-70

MX29LV160ABXEI-70

MX29LV160ATXBI-90

MX29LV160ABXBI-90

MX29LV160ATXEI-90

70

30

5

48 Ball CSP

(ball size:0.3mm)

48 Ball CSP

70

90

70

90

70

90

30

5

(ball size:0.3mm)

48 Ball CSP

(ball size:0.4mm)

48 Ball CSP

(ball size:0.4mm)

48 Ball CSP

(ball size:0.3mm)

48 Ball CSP

(ball size:0.3mm)

48 Ball CSP

(ball size:0.4mm)

48 Ball CSP

(ball size:0.4mm)

48 Ball CSP

(ball size:0.3mm)

48 Ball CSP

(ball size:0.3mm)

48 Ball CSP

(ball size:0.3mm)

48 Ball CSP

(ball size:0.3mm)

48 Ball CSP

(ball size:0.3mm)

48 Ball CSP

(ball size:0.3mm)

48 Ball CSP

(ball size:0.4mm)

48 Ball CSP

(ball size:0.4mm)

48 Ball CSP

(ball size:0.3mm)

48 Ball CSP

(ball size:0.3mm)

48 Ball CSP

(ball size:0.4mm)

P/N:PM0866

REV. 3.3, MAR. 08, 2002

58

MX29LV160T/B & MX29LV160AT/AB

PART NO.

ACCESSTIME

OPERATING CURRENT STANDBY CURRENT PACKAGE

(ns)

MAX.(mA)

MAX.(uA)

MX29LV160ABXEI-90

MX29LV160ATXBI-70R

MX29LV160ABXBI-70R

MX29LV160ATXBI-90R

MX29LV160ABXBI-90R

90

30

5

48 Ball CSP

(ball size:0.4mm)

48 Ball CSP

70

90

30

5

(ball size:0.3mm)

48 Ball CSP

(ball size:0.3mm)

48 Ball CSP

(ball size:0.3mm)

48 Ball CSP

(ball size:0.3mm)

P/N:PM0866

REV. 3.3, MAR. 08, 2002

59

MX29LV160T/B & MX29LV160AT/AB

PACKAGE INFORMATION

48-PIN PLASTIC TSOP

P/N:PM0866

REV. 3.3, MAR. 08, 2002

60

MX29LV160T/B & MX29LV160AT/AB

44-PIN PLASTIC SOP

P/N:PM0866

REV. 3.3, MAR. 08, 2002

61

MX29LV160T/B & MX29LV160AT/AB

48-Ball CSP (for MX29LV160ATXBC/ATXBI/ABXBC/ABXBI)

P/N:PM0866

REV. 3.3, MAR. 08, 2002

62

MX29LV160T/B & MX29LV160AT/AB

48-Ball CSP (for MX29LV160TXBC/TXBI/BXBC/BXBI)

P/N:PM0866

REV. 3.3, MAR. 08, 2002

63

MX29LV160T/B & MX29LV160AT/AB

48-Ball CSP (for MX29LV160ATXEC/ATXEI/ABXEC/ABXEI)

P/N:PM0866

REV. 3.3, MAR. 08, 2002

64

MX29LV160T/B & MX29LV160AT/AB

REVISION HISTORY

Revision No. Description

(MX29LV160AT/AB)

Page

Date

0.1

Mis-typing:Table 4-3 Device Gemetry Data Values

P9

NOV/15/2001

1) Device size: Data=0015h

2) Erase block region 1 information:

Data=0000h for byte address=5A, Word address=2D

Data=0040h for byte address=5E, Word address=2F

Data=0000h for byte address=60, Word address=30

Added 48-Ball CSP Package

1.Modify Ordering Information

2.Add 48-ball CSP Package Information for MX29LV160ATXEC/TXEI P60

/BXEC/BXBI)

0.2

0.3

P1,2,56,59 DEC/11/2001

P56

DEC/28/2001

(MX29LV160T/B)

1.1

Changed DQ-->Q

P2,6,7,9,21,22APR/05/2000

Modify Toggle Bit I-->II

Modify Ambient Operating Temperature 0°C to 70°C

Correct Type Error

P13

P15

P8

1.2

APR/17/2000

Modify DC Characteristics VCC=5V±10%-->VCC=3V±10%

Modify Timing Waveform for Chip Unprotection 5V-->3V

1.Add "Table 8" for Read Operation, DC Characteristics

2.Add "Table 9" for Read Operation, AC Characteristics

3.Add & Modify "Table 10" for Erase/Program Operation,

AC Characteristics

P16

P33

P19

P20

P23

1.3

1.4

MAY/08/2000

JUN/05/2000

4.Add "Table 11" for Alternate CE Controlled Erase/Program

Operations

P24

5.Modify Automatic Programming Timing Waveform, Automatic

Programming Algorithm Flowchart

P26,27

6.Add CE Controlled Programming Timing Waveform

8.Add Write Operation Status for DATA polling & Toggle Bit

Algorithm and Timing Waveform

P28

P39,40,41

9.Add Q6 vs Q2 for Erase and Erase Suspend Operation

P44

1.5

Modify Feature--10,000 minimum erase/program cycles-->100,000-- P1

Modify General Description--even after 10,000 --->100,000 erase-- P1

JUN/28/2000

1.6

1.7

Modify Erase/Program Cycles(MIN.) 10,000-->100,000

Correct content error

P47

AUG/25/2000

P13,14,19,30 SEP/14/2000

Add Title Description

Add Sector Protect Timing waveform

Add Sector Protection Algorithm

P34,37

P35

P36

1.8

Add AC Characteristics-- 29LV160T/B-70R

Add Ordering Information

P20

P50

P23,24

P8

P14

P50

P2

NOV/09/2000

1.9

2.0

Add AC Characteristics Table10 & Table11-- 29LV160T/B-70R

Delete Unlock Bypass Command Definitions

Delete Unlock Bypass Command Sequence

Add Ordering Information--48 Ball CSP

To corrected the naming of reset pin from RP to RESET

Modify Timing Waveform

NOV/16/2000

JAN/04/2001

2.1

2.2

2.3

JAN/16/2001

JAN/30/2001

P27,29,30,32 FEB/07/2001

P28

Modify Automatic Programming Algorithm Flowchart

Delete Figure 21. Toggle Bit Timings(During Embedded Algorithms) P45

Add Figure 19. Toggle Bit Algorithm

Modify Absolute Maximum Ratings

P43

P19

P/N:PM0866

REV. 3.3, MAR. 08, 2002

65

MX29LV160T/B & MX29LV160AT/AB

Rev. No. Description

Page

P24

P23,2

P40

P52~54

P24

Date

MAR/07/2001

JUL/03/2001

2.4

2.5

Change tBUSY spec. from 90ns to 90us

Correct typing error

tWPP1/tWPP2 was changed to 100ns

To modify Package Information

2.6

Separate the tBUSY spec: tBUSY:90us for sector erase

tBUSY:90ns for chip erase ; tBUSY:90ns for program

Correct typing error

JUL/05/2001

2.7

2.8

P24

All

JUL/10/2001

JUL/24/2001

Add MX29LV161T/B part number

MX29LV160T/B tBUSY=90ns at sector erase mode

MX29LV161T/B tBUSY=90us at sector erase mode

P24

2.9

1.Separate data sheet into two files:MX29LV160T/B & MX29LV161T/B All

SEP/24/2001

2.tBUSY spec was changed from 90ns min. to 90ns max.

3.Add tWPP1/tWPP2 typical spec

P24

4.Add word/byte switching spec and waveform

5.Add 90R speed grade

6.The expression of 48-ball CSP pin configuration was changed from

"Top view, ball facing up" to "Top view, ball facing down"

(The physical pin out is not changed, just a different expression.)

7.Correct mistyping

P47,48

P21,24,51

P2

- byte/word program:7us/12us-->9us/11us

P1,24

- sector size of word mode 16K words/8K words/32K words/64K words P4

--->8K words/4K words/16K words/32K words

- TA of Extended Devices was removed

- ICC4 condition: RESET=VCC±0.3V --> RESET=VSS±0.3V

- TA=0°C to 70°C -->TA=-40°C to 85°C

- Add A19~A12 into figure

P19

P20

P20,21,24

P35,41

3.0

Wording change of sector erase commands

P11,13,27,30 OCT/17/2001

P32

(MX29LV160T/B & MX29LV160AT/AB)

3.1

1.Combinded MX29LV160AT/AB & MX29LV160T/B datasheet to be

All

JAN/11/2001

together

2.The system must write "Reset" command to exit "silicon-ID read

mode" & "sector protection verification" mode

1.Add 10ms time delay for erase suspend/resume

1.Correct typing error

P12-14,19

P15,36

P1,2,7,10,11 MAR/08/2002

13,14,16,17,51

3.2

3.3

MAR/01/2002

P/N:PM0866

REV. 3.3, MAR. 08, 2002

66

MX29LV160T/B & MX29LV160AT/AB

MACRONIX INTERNATIONAL CO., LTD.

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http : //www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.


型号：	MX29LV160BXBI-70R
厂家：	MACRONIX INTERNATIONAL
描述：	Flash, 1MX16, 70ns, PBGA48, 8 X 13 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, MO-210, CSP-48 内存集成电路
文件：	总67页 (文件大小：1461K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MX29LV160BXBI-70R [Macronix]

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