MX29LV640TTI-90_技术文档

MX29LV640T/B

64M-BIT[8Mx8/4Mx16] SINGLEVOLTAGE3VONLY

FLASHMEMORY

FEATURES

GENERAL FEATURES

SOFTWARE FEATURES

• Single Power Supply Operation

• Support Common Flash Interface (CFI)

- 2.7 to 3.6 volt for read, erase, and program opera-

tions

• 8,388,608 x 8 / 4,194,304 x 16 switchable

• Sector structure

- 8KB (4KW) x 8 and 64KB(32KW) x 127

• Sector Protection/Chip Unprotect

- Provides sector group protect function to prevent

program or erase operation in the protected sector

group

- Flash device parameters stored on the device and

provide the host system to access.

• Erase Suspend/ Erase Resume

- Suspends sector erase operation to read data from

or program data to another sector which is not being

erased

• Status Reply

- Data polling & Toggle bits provide detection of pro-

gram and erase operation completion

- Provides chip unprotect function to allow code

changes

- Provides temporary sector group unprotect function

for code changes in previously protected sector groups

• Secured Silicon Sector

HARDWARE FEATURES

• Ready/Busy (RY/BY) Output

- Provides a hardware method of detecting program

and erase operation completion

• Hardware Reset (RESET) Input

- Provides a hardware method to reset the internal

state machine to read mode

- Provides a 128-word area for code or data that can

be permanently protected.

- Once this sector is protected, it is prohibited to pro-

gram or erase within the sector again.

• Latch-up protected to 250mA from -1V to Vcc + 1V

• Low Vcc write inhibit is equal to or less than 1.5V

• Compatible with JEDEC standard

- Pin-out and software compatible to single power sup-

ply Flash

• WP Pin

- Write protect (WP) function allows protection of two

outermost boot sectors, regardless of sector protect

status

PACKAGE

PERFORMANCE

• High Performance

• 48-pinTSOP

• 63-ball CSP

• 64-ball Easy BGA

- Fast access time: 90/120ns

- Fast program time:11us/word, 45s/chip (typical)

- Fast erase time: 0.9s/sector, 45s/chip (typical)

• Low Power Consumption

- Low active read current: 10mA (typical) at 5MHz

- Low standby current: 0.2uA (typ.)

• Minimum 100,000 erase/program cycle

• 20-year data retention

GENERAL DESCRIPTION

The standard MX29LV640T/B offers access time as fast

as 90ns, allowing operation of high-speed microproces-

sors without wait states. To eliminate bus contention,

the MX29LV640T/B has separate chip enable (CE) and

output enable (OE) controls.

The MX29LV640T/B is a 64-mega bit Flash memory or-

ganized as 8M bytes of 8 bits or 4M bytes of 16 bits.

MXIC's Flash memories offer the most cost-effective and

reliable read/write non-volatile random access memory.

The MX29LV640T/B is packaged in 48-pin TSOP, 63-

ball CSP and 64-ball Easy BGA. It is designed to be

reprogrammed and erased in system or in standard

EPROM programmers.

MXIC's Flash memories augment EPROM functionality

with in-circuit electrical erasure and programming. The

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REV. 1.2, NOV. 05, 2003

1

MX29LV640T/B

MX29LV640T/B uses a command register to manage this

functionality.

AUTOMATIC SECTOR ERASE

The MX29LV640T/B is sector(s) erasable using MXIC's

Auto Sector Erase algorithm. Sector erase modes allow

sectors of the array to be erased in one erase cycle. The

Automatic Sector Erase algorithm automatically pro-

grams the specified sector(s) prior to electrical erase.

The timing and verification of electrical erase are con-

trolled internally within the device.

MXIC Flash technology reliably stores memory contents

even after 100,000 erase and program cycles. The MXIC

cell is designed to optimize the erase and program

mechanisms. In addition, the combination of advanced

tunnel oxide processing and low internal electric fields

for erase and programming operations produces reliable

cycling. The MX29LV640T/B uses a 2.7V to 3.6V VCC

supply to perform the High Reliability Erase and auto

Program/Erase algorithms.

AUTOMATIC ERASE ALGORITHM

The highest degree of latch-up protection is achieved

with MXIC's proprietary non-epi process. Latch-up pro-

tection is proved for stresses up to 100 milliamperes on

address and data pin from -1V to VCC + 1V.

MXIC's Automatic Erase algorithm requires the user to

write commands to the command register using stan-

dard microprocessor write timings. The device will auto-

matically pre-program and verify the entire array. Then

the device automatically times the erase pulse width,

provides the erase verification, and counts the number

of sequences. A status bit toggling between consecu-

tive read cycles provides feedback to the user as to the

status of the programming operation.

AUTOMATIC PROGRAMMING

The MX29LV640T/B is byte/word programmable using

the Automatic Programming algorithm. The Automatic

Programming algorithm makes the external system do

not need to have time out sequence nor to verify the

data programmed. The typical chip programming time at

room temperature of the MX29LV640T/B is less than 50

seconds.

Register contents serve as inputs to an internal state-

machine which controls the erase and programming cir-

cuitry. During write cycles, the command register inter-

nally latches address and data needed for the program-

ming and erase operations. During a system write cycle,

addresses are latched on the falling edge, and data are

latched on the rising edge of WE .

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Flash technology combines years of EPROM

experience to produce the highest levels of quality, reli-

ability, and cost effectiveness.The MX29LV640T/B elec-

trically erases all bits simultaneously using Fowler-

Nordheim tunneling. The bytes are programmed by us-

ing the EPROM programming mechanism of hot elec-

tron injection.

MXIC's Automatic Programming algorithm require the user

to only write program set-up commands (including 2 un-

lock write cycle and A0H) and a program command (pro-

gram data and address). The device automatically times

the programming pulse width, provides the program veri-

fication, and counts the number of sequences. A status

bit similar to DATA polling and a status bit toggling be-

tween consecutive read cycles, provide feedback to the

user as to the status of the programming operation.

During a program cycle, the state-machine will control

the program sequences and command register will not

respond to any command set. During a Sector Erase

cycle, the command register will only respond to Erase

Suspend command. After Erase Suspend is completed,

the device stays in read mode. After the state machine

has completed its task, it will allow the command regis-

ter to respond to its full command set.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 50 ms erase pulses

according to MXIC's Automatic Chip Erase algorithm.

Typical erasure at room temperature is accomplished in

less than 115 seconds. The Automatic Erase algorithm

automatically programs the entire array prior to electrical

erase. The timing and verification of electrical erase are

controlled internally within the device.

P/N:PM0920

REV. 1.2, NOV. 05, 2003

2

MX29LV640T/B

PIN CONFIGURATION

48 TSOP

A15

A14

A13

A12

A11

A10

A9

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

BYTE

GND

Q15/A-1

Q7

2

3

4

5

6

Q14

Q6

7

A8

8

Q13

Q5

A19

A20

WE

RESET

A21

WP

RY/BY

A18

A17

A7

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

Q12

Q4

V

CC

MX29LV640T/B

Q11

Q3

Q10

Q2

Q9

Q1

A6

Q8

A5

Q0

A4

OE

GND

CE

A0

A3

A2

A1

63 Ball CSP (TopView, Ball Down)

12.0 mm

8

7

6

5

4

3

2

1

NC

NC*

NC

NC*

Q15/

A-1

A13

A9

A12

A14

A10

A15

A11

A16

Q7

BYTE

GND

Q6

A8

Q14

Q12

Q13

RESET

WE

RY/BY

A7

A21

A18

A6

A19

A20

A5

Q5

Q2

Q0

A0

VCC

Q11

Q9

Q4

Q3

11.0 mm

Q10

Q8

WP

A17

Q1

NC*

A3

A4

A2

A1

CE

OE

GND

NC*

B

NC*

M

NC*

L

A

C

D

E

F

G

H

J

K

* Ball are shorted together via the substrate but not connected to the die.

P/N:PM0920

REV. 1.2, NOV. 05, 2003

3

MX29LV640T/B

64 Ball Easy BGA (TopView, Ball Down)

A8

B8

C8

D8

E8

F8

G8

NC

H8

NC

GND

NC

A7

B7

C7

D7

E7

F7

G7

H7

A13

A12

A14

A15

A16

BYTE

Q15

GND

A6

A9

B6

A8

C6

D6

E6

Q7

F6

G6

H6

Q6

A10

A11

Q14

Q13

A5

B5

C5

D5

E5

Q5

F5

G5

H5

Q4

WE

RESET

A21

A19

Q12

VCC

10 mm

A4

B4

C4

D4

E4

Q2

F4

G4

H4

Q3

RY/BY

WP

A18

A20

Q10

Q11

A3

A7

B3

C3

A6

D3

A5

E3

Q0

F3

G3

Q9

H3

Q1

A17

Q8

A2

A3

B2

A4

C2

A2

D2

A1

E2

A0

F2

G2

OE

H2

CE

GND

A1

B1

C1

D1

E1

F1

G1

NC

H1

NC

13mm

LOGIC SYMBOL

PIN DESCRIPTION

SYMBOL PIN NAME

22

16 or 8

A0~A21

Q0~Q14

Q15/A-1

CE

Address Input

Data Inputs/Outputs

A0-A21

Q0-Q15

(A-1)

Q15(Word Mode)/LSB addr(Byte Mode)

Chip Enable Input

WE

Write Enable Input

OE

Output Enable Input

CE

OE

WE

RESET

WP

Hardware Reset Pin, Active Low

HardwareWrite Protect

Read/Busy Output

RY/BY

VCC

+3.0V single power supply

Device Ground

RY/BY

GND

RESET

WP

NC

Pin Not Connected Internally

P/N:PM0920

REV. 1.2, NOV. 05, 2003

4

MX29LV640T/B

BLOCK DIAGRAM

CE

OE

WRITE

STATE

CONTROL

INPUT

PROGRAM/ERASE

HIGH VOLTAGE

WE

MACHINE

(WSM)

WP

LOGIC

BYTE

RESET

STATE

MX29LV640T/B

FLASH

ADDRESS

LATCH

REGISTER

ARRAY

A0-A21

AND

SOURCE

HV

BUFFER

Y-PASS GATE

COMMAND

DATA

DECODER

PGM

SENSE

DATA

HV

AMPLIFIER

COMMAND

DATA LATCH

PROGRAM

DATA LATCH

Q0-Q15

I/O BUFFER

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REV. 1.2, NOV. 05, 2003

5

MX29LV640T/B

MX29LV640T SECTOR GROUP ARCHITECTURE

Sector Sector Sector Address

Sector Size

(Kbytes/Kwords)

64/32

(x8)

(x16)

Group

1

A21-A12

Address Range

SA0

0000000xxx

0000001xxx

0000010xxx

0000011xxx

0000100xxx

0000101xxx

0000110xxx

0000111xxx

0001000xxx

0001001xxx

0001010xxx

0001011xxx

0001100xxx

0001101xxx

0001110xxx

0001111xxx

0010000xxx

0010001xxx

0010010xxx

0010011xxx

0010100xxx

0010101xxx

0010110xxx

0010111xxx

0011000xxx

0011001xxx

0011010xxx

0011011xxx

0011100xxx

0011101xxx

0011110xxx

0011111xxx

0100000xxx

0100001xxx

0100010xxx

0100011xxx

0100100xxx

0100101xxx

0100110xxx

0100111xxx

000000h-00FFFFh

010000h-01FFFFh

020000h-02FFFFh

030000h-03FFFFh

040000h-04FFFFh

050000h-05FFFFh

060000h-06FFFFh

070000h-07FFFFh

080000h-08FFFFh

090000h-09FFFFh

0A0000h-0AFFFFh

0B0000h-0BFFFFh

0C0000h-0CFFFFh

0D0000h-0DFFFFh

0E0000h-0EFFFFh

0F0000h-0FFFFFh

100000h-10FFFFh

110000h-11FFFFh

120000h-12FFFFh

130000h-13FFFFh

140000h-14FFFFh

150000h-15FFFFh

160000h-16FFFFh

170000h-17FFFFh

180000h-18FFFFh

190000h-19FFFFh

1A0000h-1AFFFFh

1B0000h-1BFFFFh

1C0000h-1CFFFFh

1D0000h-1DFFFFh

1E0000h-1EFFFFh

1F0000h-1FFFFFh

200000h-20FFFFh

210000h-21FFFFh

220000h-22FFFFh

230000h-23FFFFh

240000h-24FFFFh

250000h-25FFFFh

260000h-26FFFFh

270000h-27FFFFh

000000h-07FFFh

008000h-0FFFFh

010000h-17FFFh

018000h-01FFFFh

020000h-027FFFh

028000h-02FFFFh

030000h-037FFFh

038000h-03FFFFh

040000h-047FFFh

048000h-04FFFFh

050000h-057FFFh

058000h-05FFFFh

060000h-067FFFh

068000h-06FFFFh

070000h-077FFFh

078000h-07FFFFh

080000h-087FFFh

088000h-08FFFFh

090000h-097FFFh

098000h-09FFFFh

0A0000h-0A7FFFh

0A8000h-0AFFFFh

0B0000h-0B7FFFh

0B8000h-0BFFFFh

0C0000h-0C7FFFh

0C8000h-0CFFFFh

0D0000h-0D7FFFh

0D8000h-0DFFFFh

0E0000h-0E7FFFh

0E8000h-0EFFFFh

0F0000h-0F7FFFh

0F8000h-0FFFFFh

100000h-107FFFh

108000h-10FFFFh

110000h-117FFFh

118000h-11FFFFh

120000h-127FFFh

128000h-12FFFFh

130000h-137FFFh

138000h-13FFFFh

1

SA1

1

SA2

1

SA3

2

SA4

2

SA5

2

SA6

2

SA7

3

SA8

3

SA9

3

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

3

4

5

6

7

8

9

10

P/N:PM0920

REV. 1.2, NOV. 05, 2003

6

MX29LV640T/B

Sector Sector Sector Address

Sector Size

(Kbytes/Kwords)

64/32

(x8)

(x16)

Group

11

12

13

14

15

16

17

18

19

20

A21-A12

Address Range

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

SA71

SA72

SA73

SA74

SA75

SA76

SA77

SA78

SA79

0101000xxx

0101001xxx

0101010xxx

0101011xxx

0101100xxx

0101101xxx

0101110xxx

0101111xxx

0110000xxx

0110001xxx

0110010xxx

0110011xxx

0110100xxx

0110101xxx

0110110xxx

0110111xxx

0111000xxx

0111001xxx

0111010xxx

0111011xxx

0111100xxx

0111101xxx

0111110xxx

0111111xxx

1000000xxx

1000001xxx

1000010xxx

1000011xxx

1000100xxx

1000101xxx

1000110xxx

1000111xxx

1001000xxx

1001001xxx

1001010xxx

1001011xxx

1001100xxx

1001101xxx

1001110xxx

1001111xxx

280000h-28FFFFh

290000h-29FFFFh

2A0000h-2AFFFFh

2B0000h-2BFFFFh

2C0000h-2CFFFFh

2D0000h-2DFFFFh

2E0000h-2EFFFFh

2F0000h-2FFFFFh

300000h-30FFFFh

310000h-31FFFFh

320000h-32FFFFh

330000h-33FFFFh

340000h-34FFFFh

350000h-35FFFFh

360000h-36FFFFh

370000h-37FFFFh

380000h-38FFFFh

390000h-39FFFFh

3A0000h-3AFFFFh

3B0000h-3BFFFFh

3C0000h-3CFFFFh

3D0000h-3DFFFFh

3E0000h-3EFFFFh

3F0000h-3FFFFFh

400000h-40FFFFh

410000h-41FFFFh

420000h-42FFFFh

430000h-43FFFFh

440000h-44FFFFh

450000h-45FFFFh

460000h-46FFFFh

470000h-47FFFFh

480000h-48FFFFh

490000h-49FFFFh

4A0000h-4AFFFFh

4B0000h-4BFFFFh

4C0000h-4CFFFFh

4D0000h-4DFFFFh

4E0000h-4EFFFFh

4F0000h-4FFFFFh

140000h-147FFFh

148000h-14FFFFh

150000h-157FFFh

158000h-15FFFFh

160000h-147FFFh

168000h-14FFFFh

170000h-177FFFh

178000h-17FFFFh

180000h-187FFFh

188000h-18FFFFh

190000h-197FFFh

198000h-19FFFFh

1A0000h-1A7FFFh

1A8000h-1AFFFFh

1B0000h-1B7FFFh

1B8000h-1BFFFFh

1C0000h-1C7FFFh

1C8000h-1CFFFFh

1D0000h-1D7FFFh

1D8000h-1DFFFFh

1E0000h-1E7FFFh

1E8000h-1EFFFFh

1F0000h-1F7FFFh

1F8000h-1FFFFFh

200000h-207FFFh

208000h-20FFFFh

210000h-217FFFh

218000h-21FFFFh

220000h-227FFFh

228000h-22FFFFh

230000h-237FFFh

238000h-23FFFFh

240000h-247FFFh

248000h-24FFFFh

250000h-257FFFh

258000h-25FFFFh

260000h-247FFFh

268000h-24FFFFh

270000h-277FFFh

278000h-27FFFFh

P/N:PM0920

REV. 1.2, NOV. 05, 2003

7

MX29LV640T/B

Sector Sector Sector Address

Sector Size

(Kbytes/Kwords)

64/32

(x8)

(x16)

Group

21

22

23

24

25

26

27

28

29

30

A21-A12

Address Range

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

SA95

SA96

SA97

SA98

SA99

1010000xxx

1010001xxx

1010010xxx

1010011xxx

1010100xxx

1010101xxx

1010110xxx

1010111xxx

1011000xxx

1011001xxx

1011010xxx

1011011xxx

1011100xxx

1011101xxx

1011110xxx

1011111xxx

1100000xxx

1100001xxx

1100010xxx

1100011xxx

500000h-50FFFFh

510000h-51FFFFh

520000h-52FFFFh

530000h-53FFFFh

540000h-54FFFFh

550000h-55FFFFh

560000h-56FFFFh

570000h-57FFFFh

580000h-58FFFFh

590000h-59FFFFh

5A0000h-5AFFFFh

5B0000h-5BFFFFh

5C0000h-5CFFFFh

5D0000h-5DFFFFh

5E0000h-5EFFFFh

5F0000h-5FFFFFh

600000h-60FFFFh

610000h-61FFFFh

620000h-62FFFFh

630000h-63FFFFh

640000h-64FFFFh

650000h-65FFFFh

660000h-66FFFFh

670000h-67FFFFh

680000h-68FFFFh

690000h-69FFFFh

6A0000h-6AFFFFh

6B0000h-6BFFFFh

6C0000h-6CFFFFh

6D0000h-6DFFFFh

6E0000h-6EFFFFh

6F0000h-6FFFFFh

700000h-70FFFFh

710000h-71FFFFh

720000h-72FFFFh

730000h-73FFFFh

740000h-74FFFFh

750000h-75FFFFh

760000h-76FFFFh

770000h-77FFFFh

280000h-287FFFh

288000h-28FFFFh

290000h-297FFFh

298000h-29FFFFh

2A0000h-2A7FFFh

2A8000h-2AFFFFh

2B0000h-2B7FFFh

2B8000h-2BFFFFh

2C0000h-2C7FFFh

2C8000h-2CFFFFh

2D0000h-2D7FFFh

2D8000h-2DFFFFh

2E0000h-2E7FFFh

2E8000h-2EFFFFh

2F0000h-2F7FFFh

2F8000h-2FFFFFh

300000h-307FFFh

308000h-30FFFFh

310000h-317FFFh

318000h-31FFFFh

320000h-327FFFh

328000h-32FFFFh

330000h-337FFFh

338000h-33FFFFh

340000h-347FFFh

348000h-34FFFFh

350000h-357FFFh

358000h-35FFFFh

360000h-347FFFh

368000h-34FFFFh

370000h-377FFFh

378000h-37FFFFh

380000h-387FFFh

388000h-38FFFFh

390000h-397FFFh

398000h-39FFFFh

3A0000h-3A7FFFh

3A8000h-3AFFFFh

3B0000h-3B7FFFh

3B8000h-3BFFFFh

SA100 1100100xxx

SA101 1100101xxx

SA102 1100110xxx

SA103 1100111xxx

SA104 1101000xxx

SA105 1101001xxx

SA106 1101010xxx

SA107 1101011xxx

SA108 1101100xxx

SA109 1101101xxx

SA110 1101110xxx

SA111 1101111xxx

SA112 1110000xxx

SA113 1110001xxx

SA114 1110010xxx

SA115 1110011xxx

SA116 1110100xxx

SA117 1110101xxx

SA118 1110110xxx

SA119 1110111xxx

P/N:PM0920

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8

MX29LV640T/B

Sector Sector Sector Address

Sector Size

(x8)

(x16)

Group

31

A21-A12

(Kbytes/Kwords)

Address Range

SA120 1111000xxx

SA121 1111001xxx

SA122 1111010xxx

SA123 1111011xxx

SA124 1111100xxx

SA125 1111101xxx

SA126 1111110xxx

SA127 1111111000

SA128 1111111001

SA129 1111111010

SA130 1111111011

SA131 1111111100

SA132 1111111101

SA133 1111111110

SA134 1111111111

64/32

8/4

780000h-78FFFFh

790000h-79FFFFh

7A0000h-7AFFFFh

7B0000h-7BFFFFh

7C0000h-7CFFFFh

7D0000h-7DFFFFh

7E0000h-7EFFFFh

7F0000h-7F1FFFh

7F2000h-7F3FFFh

7F4000h-7F5FFFh

7F6000h-7F7FFFh

7F8000h-7F9FFFh

7FA000h-7FBFFFh

7FC000h-7FDFFFh

7FE000h-7FFFFFh

3C0000h-3C7FFFh

3C8000h-3CFFFFh

3D0000h-3D7FFFh

3D8000h-3DFFFFh

3E0000h-3E7FFFh

3E8000h-3EFFFFh

3F0000h-3F7FFFh

3F8000h-3FFFFFh

3F9000h-3F9FFFh

3FA000h-3FAFFFh

3FB000h-3FBFFFh

3FC000h-3FCFFFh

3FD000h-3FDFFFh

3FE000h-3FEFFFh

3FF000h-3FFFFFh

31

32

33

34

8/4

35

8/4

36

8/4

37

8/4

38

8/4

39

8/4

40

8/4

Note:The address range is A21:A-1 in byte mode (BYTE=VIL) or A20:A0 in word mode (BYTE=VIH)

Top Boot Security Sector Addresses

Sector Address

A21~A12

Sector Size

(bytes/words)

256/128

(x8)

(x16)

Address Range

7FFF00h-7FFFFFh

Address Range

3FFF70h-3FFFFFh

1111111111

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9

MX29LV640T/B

MX29LV640B SECTOR GROUP ARCHITECTURE

Sector Sector Sector Address

Sector Size

(Kbytes/Kwords)

8/4

(x8)

(x16)

Group

1

A21-A12

Address Range

SA0

0000000000

0000000001

0000000010

0000000011

0000000100

0000000101

0000000110

0000000111

0000001xxx

0000010xxx

0000011xxx

0000100xxx

0000101xxx

0000110xxx

0000111xxx

0001000xxx

0001001xxx

0001010xxx

0001011xxx

0001100xxx

0001101xxx

0001110xxx

0001111xxx

0010000xxx

0010001xxx

0010010xxx

0010011xxx

0010100xxx

0010101xxx

0010110xxx

0010111xxx

0011000xxx

0011001xxx

0011010xxx

0011011xxx

0011100xxx

0011101xxx

0011110xxx

0011111xxx

000000h-001FFFh

002000h-003FFFh

004000h-005FFFh

006000h-007FFFh

008000h-009FFFh

00A000h-00BFFFh

00C000h-00DFFFh

00E000h-00FFFFh

010000h-01FFFFh

020000h-02FFFFh

030000h-03FFFFh

040000h-04FFFFh

050000h-05FFFFh

060000h-06FFFFh

070000h-07FFFFh

080000h-08FFFFh

090000h-09FFFFh

0A0000h-0AFFFFh

0B0000h-0BFFFFh

0C0000h-0CFFFFh

0D0000h-0DFFFFh

0E0000h-0EFFFFh

0F0000h-0FFFFFh

100000h-10FFFFh

110000h-11FFFFh

120000h-12FFFFh

130000h-13FFFFh

140000h-14FFFFh

150000h-15FFFFh

160000h-16FFFFh

170000h-17FFFFh

180000h-18FFFFh

190000h-19FFFFh

1A0000h-1AFFFFh

1B0000h-1BFFFFh

1C0000h-1CFFFFh

1D0000h-1DFFFFh

1E0000h-1EFFFFh

1F0000h-1FFFFFh

000000h-000FFFh

001000h-001FFFh

002000h-002FFFh

003000h-003FFFh

004000h-004FFFh

005000h-005FFFh

006000h-006FFFh

007000h-007FFFh

008000h-00FFFFh

010000h-017FFFh

018000h-01FFFFh

020000h-027FFFh

028000h-02FFFFh

030000h-037FFFh

038000h-03FFFFh

040000h-047FFFh

048000h-04FFFFh

050000h-057FFFh

058000h-05FFFFh

060000h-067FFFh

068000h-06FFFFh

070000h-077FFFh

078000h-07FFFFh

080000h-087FFFh

088000h-08FFFFh

090000h-097FFFh

098000h-09FFFFh

0A0000h-0A7FFFh

0A8000h-0AFFFFh

0B0000h-0B7FFFh

0B8000h-0BFFFFh

0C0000h-0C7FFFh

0C8000h-0CFFFFh

0D0000h-0D7FFFh

0D8000h-0DFFFFh

0E0000h-0E7FFFh

0E8000h-0EFFFFh

0F0000h-0F7FFFh

0F8000h-0FFFFFh

2

SA1

8/4

3

SA2

8/4

4

SA3

8/4

5

SA4

8/4

6

SA5

8/4

7

SA6

8/4

8

SA7

8/4

9

SA8

64/32

9

SA9

9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

10

11

12

13

14

15

16

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REV. 1.2, NOV. 05, 2003

10

MX29LV640T/B

Sector Sector Sector Address

Sector Size

(Kbytes/Kwords)

64/32

(x8)

(x16)

Group

17

18

19

20

21

22

23

24

25

26

A21-A12

Address Range

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

SA71

SA72

SA73

SA74

SA75

SA76

SA77

SA78

0100000xxx

0100001xxx

0100010xxx

0100011xxx

0100100xxx

0100101xxx

0100110xxx

0100111xxx

0101000xxx

0101001xxx

0101010xxx

0101011xxx

0101100xxx

0101101xxx

0101110xxx

0101111xxx

0110000xxx

0110001xxx

0110010xxx

0110011xxx

0110100xxx

0110101xxx

0110110xxx

0110111xxx

0111000xxx

0111001xxx

0111010xxx

0111011xxx

0111100xxx

0111101xxx

0111110xxx

0111111xxx

1000000xxx

1000001xxx

1000010xxx

1000011xxx

1000100xxx

1000101xxx

1000110xxx

1000111xxx

200000h-20FFFFh

210000h-21FFFFh

220000h-22FFFFh

230000h-23FFFFh

240000h-24FFFFh

250000h-25FFFFh

260000h-26FFFFh

270000h-27FFFFh

280000h-28FFFFh

290000h-29FFFFh

2A0000h-2AFFFFh

2B0000h-2BFFFFh

2C0000h-2CFFFFh

2D0000h-2DFFFFh

2E0000h-2EFFFFh

2F0000h-2FFFFFh

300000h-30FFFFh

310000h-31FFFFh

320000h-32FFFFh

330000h-33FFFFh

340000h-34FFFFh

350000h-35FFFFh

360000h-36FFFFh

370000h-37FFFFh

380000h-38FFFFh

390000h-39FFFFh

3A0000h-3AFFFFh

3B0000h-3BFFFFh

3C0000h-3CFFFFh

3D0000h-3DFFFFh

3E0000h-3EFFFFh

3F0000h-3FFFFFh

400000h-40FFFFh

410000h-41FFFFh

420000h-42FFFFh

430000h-43FFFFh

440000h-44FFFFh

450000h-45FFFFh

460000h-46FFFFh

470000h-47FFFFh

100000h-107FFFh

108000h-10FFFFh

110000h-117FFFh

118000h-11FFFFh

120000h-127FFFh

128000h-12FFFFh

130000h-137FFFh

138000h-13FFFFh

140000h-147FFFh

148000h-14FFFFh

150000h-157FFFh

158000h-15FFFFh

160000h-167FFFh

168000h-16FFFFh

170000h-177FFFh

178000h-17FFFFh

180000h-187FFFh

188000h-18FFFFh

190000h-197FFFh

198000h-19FFFFh

1A0000h-1A7FFFh

1A8000h-1AFFFFh

1B0000h-1B7FFFh

1B8000h-1BFFFFh

1C0000h-1C7FFFh

1C8000h-1CFFFFh

1D0000h-1D7FFFh

1D8000h-1DFFFFh

1E0000h-1E7FFFh

1E8000h-1EFFFFh

1F0000h-1F7FFFh

1F8000h-1FFFFFh

200000h-207FFFh

208000h-20FFFFh

210000h-217FFFh

218000h-21FFFFh

220000h-227FFFh

228000h-22FFFFh

230000h-237FFFh

238000h-23FFFFh

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11

MX29LV640T/B

Sector Sector Sector Address

Sector Size

(Kbytes/Kwords)

64/32

(x8)

(x16)

Group

27

28

29

30

31

32

33

34

35

36

A21-A12

Address Range

SA79

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

SA95

SA96

SA97

SA98

SA99

1001000xxx

1001001xxx

1001010xxx

1001011xxx

1001100xxx

1001101xxx

1001110xxx

1001111xxx

1010000xxx

1010001xxx

1010010xxx

1010011xxx

1010100xxx

1010101xxx

1010110xxx

1010111xxx

1011000xxx

1011001xxx

1011010xxx

1011011xxx

1011100xxx

480000h-48FFFFh

490000h-49FFFFh

4A0000h-4AFFFFh

4B0000h-4BFFFFh

4C0000h-4CFFFFh

4D0000h-4DFFFFh

4E0000h-4EFFFFh

4F0000h-4FFFFFh

500000h-50FFFFh

510000h-51FFFFh

520000h-52FFFFh

530000h-53FFFFh

540000h-54FFFFh

550000h-55FFFFh

560000h-56FFFFh

570000h-57FFFFh

580000h-58FFFFh

590000h-59FFFFh

5A0000h-5AFFFFh

5B0000h-5BFFFFh

5C0000h-5CFFFFh

5D0000h-5DFFFFh

5E0000h-5EFFFFh

5F0000h-5FFFFFh

600000h-60FFFFh

610000h-61FFFFh

620000h-62FFFFh

630000h-63FFFFh

640000h-64FFFFh

650000h-65FFFFh

660000h-66FFFFh

670000h-67FFFFh

680000h-68FFFFh

690000h-69FFFFh

6A0000h-6AFFFFh

6B0000h-6BFFFFh

6C0000h-6CFFFFh

6D0000h-6DFFFFh

6E0000h-6EFFFFh

6F0000h-6FFFFFh

240000h-247FFFh

248000h-24FFFFh

250000h-257FFFh

258000h-25FFFFh

260000h-267FFFh

268000h-26FFFFh

270000h-277FFFh

278000h-27FFFFh

280000h-287FFFh

288000h-28FFFFh

290000h-297FFFh

298000h-29FFFFh

2A0000h-2A7FFFh

2A8000h-2AFFFFh

2B0000h-2B7FFFh

2B8000h-2BFFFFh

2C0000h-2C7FFFh

2C8000h-2CFFFFh

2D0000h-2D7FFFh

2D8000h-2DFFFFh

2E0000h-2E7FFFh

2E8000h-2EFFFFh

2F0000h-2F7FFFh

2F8000h-2FFFFFh

300000h-307FFFh

308000h-30FFFFh

310000h-317FFFh

318000h-31FFFFh

320000h-327FFFh

328000h-32FFFFh

330000h-337FFFh

338000h-33FFFFh

340000h-347FFFh

348000h-34FFFFh

350000h-357FFFh

358000h-35FFFFh

360000h-367FFFh

368000h-36FFFFh

370000h-377FFFh

378000h-37FFFFh

SA100 1011101xxx

SA101 1011110xxx

SA102 1011111xxx

SA103 1100000xxx

SA104 1100001xxx

SA105 1100010xxx

SA106 1100011xxx

SA107 1100100xxx

SA108 1100101xxx

SA109 1100110xxx

SA110 1100111xxx

SA111 1101000xxx

SA112 1101001xxx

SA113 1101010xxx

SA114 1101011xxx

SA115 1101100xxx

SA116 1101101xxx

SA117 1101110xxx

SA118 1101111xxx

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12

MX29LV640T/B

Sector Sector Sector Address

Sector Size

(Kbytes/Kwords)

64/32

(x8)

(x16)

Group

37

A21-A12

Address Range

SA119 1110000xxx

SA120 1110001xxx

SA121 1110010xxx

SA122 1110011xxx

SA123 1110100xxx

SA124 1110101xxx

SA125 1110110xxx

SA126 1110111xxx

SA127 1111000xxx

SA128 1111001xxx

SA129 1111010xxx

SA130 1111011xxx

SA131 1111100xxx

SA132 1111101xxx

SA133 1111110xxx

SA134 1111111xxx

700000h-70FFFFh

710000h-71FFFFh

720000h-72FFFFh

730000h-73FFFFh

740000h-74FFFFh

750000h-75FFFFh

760000h-76FFFFh

770000h-77FFFFh

780000h-78FFFFh

790000h-79FFFFh

7A0000h-7AFFFFh

7B0000h-7BFFFFh

7C0000h-7CFFFFh

7D0000h-7DFFFFh

7E0000h-7EFFFFh

7F0000h-7FFFFFh

380000h-387FFFh

388000h-38FFFFh

390000h-397FFFh

398000h-39FFFFh

3A0000h-3A7FFFh

3A8000h-3AFFFFh

3B0000h-3B7FFFh

3B8000h-3BFFFFh

3C0000h-3C7FFFh

3C8000h-3CFFFFh

3D0000h-3D7FFFh

3D8000h-3DFFFFh

3E0000h-3E7FFFh

3E8000h-3EFFFFh

3F0000h-3F7FFFh

3F8000h-3FFFFFh

37

64/32

37

64/32

37

64/32

38

64/32

38

64/32

38

64/32

38

64/32

39

64/32

39

64/32

39

64/32

39

64/32

40

64/32

40

64/32

40

64/32

40

64/32

Note:The address range is A20:A-1 in byte mode (BYTE=VIL) or A20:A0 in word mode (BYTE=VIH)

Bottom Boot Security Sector Addresses

Sector Address

A21~A12

Sector Size

(bytes/words)

256/128

(x8)

(x16)

Address Range

000000h-0000FFh

Address Range

000000-00007Fh

0000000000

P/N:PM0920

REV. 1.2, NOV. 05, 2003

13

MX29LV640T/B

Table 1

BUS OPERATION (1)

Operation

CE

OE WE

RESET

WP

L/H

Address

Q15~Q0

D_OUT

Read

L

H

X

H

X

H

L

H

A_IN

X

Write (Program/Erase)

Standby

L

H

(Note 2)

H

D_IN

VCC±0.3V

X

H

X

L

VCC±0.3V

High-Z

Output Disable

Reset

L

X

L

H

L

L/H

X

L/H

X

Sector Group Protect

(Note 2)

V_ID

L/H

Sector Addresses, D_IN, D_OUT

A6=L, A1=H, A0=L

Chip unprotect

(Note 2)

L

H

X

L

V_ID

(Note 2)

Sector Addresses, D_IN, D_OUT

A6=H, A1=H, A0=L

Temporary Sector Group

Unprotect

X

A_IN

D_IN

Legend:

L=Logic LOW=V_IL, H=Logic High=V_IH, V_ID=12.0±0.5V, X=Don't Care, A_IN=Address IN, D_IN=Data IN, D_OUT=Data OUT

Notes:

1. The sector group protect and chip unprotect functions may also be implemented via programming equipment. See

the "Sector Group Protection and Chip Unprotect" section.

2. If WP=VIL, the two outermost boot sectors remain protected. If WP=VIH, the two outermost boot sector protec-

tion depends on whether they were last protected or unprotect using the method described in "Sector/ Sector Block

Protection and Unprotect".

3. D_INor D_OUTas required by command sequence, Data polling or sector protect algorithm (see Figure 2).

P/N:PM0920

REV. 1.2, NOV. 05, 2003

14

MX29LV640T/B

AUTOSELECT CODES (High Voltage Method)

Operation

CE OE WE A0 A1 A5 A6 A8 A9 A14 A15

Q0~Q15

to

A2

X

to

A7

X

to to

A10 A21

Manufactures Code

Read Device Code

Silicon (Top Boot Block)

L

H

L

X

V_ID

X

XXC2H

22C9H (word)

XXC9H (byte)

22CBH (word)

XXCBH (byte)

Code(1)

H

X

ID

Device Code

L

H

X

H

L

X

L

X

V_ID

X

SA

X

(Bottom Boot Block)

Sector Protect Verify

Secured Silicon Sector

Indicator Bit (Q7)

H

xx88h

(factory locked)

xx08h

(non-factory locked)

Notes:

1.code=xx00h means unprotected, or code=xx01h means protected, SA=Sector Address, X=Don't care.

P/N:PM0920

REV. 1.2, NOV. 05, 2003

15

MX29LV640T/B

REQUIREMENTS FOR READING ARRAY

DATA

STANDBY MODE

MX29LV640T/B can be set into Standby mode with two

different approaches. One is using both CE and RESET

pins and the other one is using RESET pin only.

To read array data from the outputs, the system must

drive the CE and OE pins toVIL.CE is the power control

and selects the device. OE is the output control and gates

array data to the output pins.WE should remain at VIH.

When using both pins of CE and RESET, a CMOS

Standby mode is achieved with both pins held at Vcc ±

0.3V. Under this condition, the current consumed is less

than 0.2uA (typ.). If both of the CE and RESET are held

atVIH, but not within the range ofVCC ± 0.3V, the device

will still be in the standby mode, but the standby current

will be larger. During Auto Algorithm operation, Vcc ac-

tive current (Icc2) is required even CE = "H" until the

operation is completed.The device can be read with stan-

dard access time (tCE) from either of these standby

modes.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory content

occurs during the power transition. No command is

necessary in this mode to obtain array data. Standard

microprocessor read cycles that assert valid address on

the device address inputs produce valid data on the device

data outputs.The device remains enabled for read access

until the command register contents are altered.

When using only RESET, a CMOS standby mode is

achieved with RESET input held at Vss ±0.3V, Under

this condition the current is consumed less than 1uA

(typ.). Once the RESET pin is taken high, the device is

back to active without recovery delay.

WRITE COMMANDS/COMMAND

SEQUENCES

To program data to the device or erase sectors of memory

, the system must drive WE and CE to VIL, and OE to

VIH.

In the standby mode the outputs are in the high imped-

ance state, independent of the OE input.

An erase operation can erase one sector, multiple sectors

, or the entire device.Table indicates the address space

that each sector occupies. A "sector address" consists

of the address bits required to uniquely select a sector.

The "Writing specific address and data commands or

sequences into the command register initiates device

operations. Table 1 defines the valid register command

sequences.Writing incorrect address and data values or

writing them in the improper sequence resets the device

to reading array data. Section has details on erasing a

sector or the entire chip, or suspending/resuming the erase

operation.

MX29LV640T/B is capable to provide the Automatic

Standby Mode to restrain power consumption during read-

out of data. This mode can be used effectively with an

application requested low power consumption such as

handy terminals.

To active this mode, MX29LV640T/B automatically switch

themselves to low power mode when MX29LV640T/B

addresses remain stable during access time of

tACC+30ns. It is not necessary to control CE, WE, and

OE on the mode. Under the mode, the current consumed

is typically 0.2uA (CMOS level).

After the system writes the Automatic Select command

sequence, the device enters the Automatic Select mode.

The system can then read Automatic Select codes from

the internal register (which is separate from the memory

array) on Q7-Q0. Standard read cycle timings apply in

this mode. Refer to the Automatic Select Mode and

Automatic Select Command Sequence section for more

information.

AUTOMATIC SLEEP MODE

The automatic sleep mode minimizes Flash device en-

ergy consumption.The device automatically enables this

mode when address remain stable for tACC+30ns.The

automatic sleep mode is independent of the CE, WE,

and OE control signals. Standard address access tim-

ings provide new data when addresses are changed.While

in sleep mode, output data is latched and always avail-

able to the system. ICC4 in the DC Characteristics table

represents the automatic sleep mode current specifica-

tion.

ICC2 in the DC Characteristics table represents the active

current specification for the write mode. The "AC

Characteristics" section contains timing specification

table and timing diagrams for write operations.

P/N:PM0920

REV. 1.2, NOV. 05, 2003

16

MX29LV640T/B

which are protected or unprotected at the same time.To

activate this mode, the programming equipment must

force VID on address pin A9 and control pin OE, (sug-

gest VID = 12V) A6 = VIL and CE = VIL. (see Table 2)

Programming of the protection circuitry begins on the

falling edge of the WE pulse and is terminated on the

rising edge. Please refer to sector group protect algo-

rithm and waveform.

OUTPUT DISABLE

With the OE input at a logic high level (VIH), output from

the devices are disabled.This will cause the output pins

to be in a high impedance state.

RESET OPERATION

The RESET pin provides a hardware method of resetting

the device to reading array data.When the RESET pin is

driven low for at least a period of tRP, the device

immediately terminates any operation in progress,

tristates all output pins, and ignores all read/write

commands for the duration of the RESET pulse. The

device also resets the internal state machine to reading

array data.The operation that was interrupted should be

reinitiated once the device is ready to accept another

command sequence, to ensure data integrity

MX29LV640T/B also provides another method.Which re-

quiresVID on the RESET only.This method can be imple-

mented either in-system or via programming equipment.

This method uses standard microprocessor bus cycle

timing.

To verify programming of the protection circuitry, the pro-

gramming equipment must forceVID on address pin A9

( with CE and OE at VIL and WE at VIH). When A1=1, it

will produce a logical "1" code at device output Q0 for a

protected sector. Otherwise the device will produce 00H

for the unprotected sector. In this mode, the addresses,

except for A1, are don't care. Address locations with A1

=VIL are reserved to read manufacturer and device codes.

(Read Silicon ID)

Current is reduced for the duration of the RESET pulse.

When RESET is held at VSS±0.3V, the device draws

CMOS standby current (ICC4). If RESET is held at VIL

but not within VSS±0.3V, the standby current will be

greater.

It is also possible to determine if the group is protected

in the system by writing a Read Silicon ID command.

Performing a read operation with A1=VIH, it will produce

a logical "1" at Q0 for the protected sector.

The RESET pin may be tied to system reset circuitry. A

system reset would that also reset the Flash memory,

enabling the system to read the boot-up firmware from

the Flash memory.

If RESET is asserted during a program or erase

operation, the RY/BY pin remains a "0" (busy) until the

internal reset operation is complete, which requires a time

of tREADY (during Embedded Algorithms).The system

can thus monitor RY/BY to determine whether the reset

operation is complete. If RESET is asserted when a

program or erase operation is completed within a time of

tREADY (not during Embedded Algorithms).The system

can read data tRH after the RESET pin returns to VIH.

CHIP UNPROTECT OPERATION

The MX29LV640T/B also features the chip unprotect

mode, so that all sectors are unprotected after chip

unprotect is completed to incorporate any changes in

the code. It is recommended to protect all sectors before

activating chip unprotect mode.

To activate this mode, the programming equipment must

forceVID on control pin OE and address pin A9. The CE

pins must be set at VIL. Pins A6 must be set to VIH.

(seeTable 2) Refer to chip unprotect algorithm and wave-

form for the chip unprotect algorithm. The unprotect

mechanism begins on the falling edge of the WE pulse

and is terminated on the rising edge.

Refer to the AC Characteristics tables for RESET

parameters and to Figure 14 for the timing diagram.

SECTOR GROUP PROTECT OPERATION

The MX29LV640T/B features hardware sector group pro-

tection. This feature will disable both program and erase

operations for these sector group protected. In this de-

vice, a sector group consists of four adjacent sectors

MX29LV640T/B also provides another method.Which re-

quiresVID on the RESET only.This method can be imple-

mented either in-system or via programming equipment.

This method uses standard microprocessor bus cycle

timing.

P/N:PM0920

REV. 1.2, NOV. 05, 2003

17

MX29LV640T/B

It is also possible to determine if the chip is unprotect in

the system by writing the Read Silicon ID command.

Performing a read operation with A1=VIH, it will produce

00H at data outputs (Q0-Q7) for an unprotect sector.It is

noted that all sectors are unprotected after the chip

unprotect algorithm is completed.

SILICON ID READ OPERATION

Flash memories are intended for use in applications where

the local CPU alters memory contents. As such, manu-

facturer and device codes must be accessible while the

device resides in the target system. PROM program-

mers typically access signature codes by raising A9 to

a high voltage. However, multiplexing high voltage onto

address lines is not generally desired system design prac-

tice.

WRITE PROTECT (WP)

The write protect function provides a hardware method

to protect boot sectors without using V_ID.

MX29LV640T/B provides hardware method to access the

silicon ID read operation.Which method requiresVID on

A9 pin, VIL on CE, OE, A6, and A1 pins. Which apply

VIL on A0 pin, the device will output MXIC's manufac-

ture code of C2H.Which applyVIH on A0 pin, the device

will output MX29LV640T/B device code of C9H/CBH.

If the system asserts VIL on the WP pin, the device

disables program and erase functions in the two "outer-

most" 8 Kbyte boot sectors independently of whether

those sectors were protected or unprotect using the

method described in Sector/Sector Group Protection and

Chip Unprotect". The two outermost 8 Kbyte boot sec-

tors are the two sectors containing the lowest addresses

in a bottom-boot-configured device, or the two sectors

containing the highest addresses in a top-boot-config-

ured device.

VERIFY SECTOR GROUP PROTECT STATUS

OPERATION

MX29LV640T/B provides hardware method for sector

group protect status verify. Which method requires VID

on A9 pin, VIH on WE and A1 pins, VIL on CE, OE, A6,

and A0 pins, and sector address on A16 to A21 pins.

Which the identified sector is protected, the device will

output 01H. Which the identified sector is not protect,

the device will output 00H.

If the system asserts VIH on the WP pin, the device

reverts to whether the two outermost 8K Byte boot sec-

tors were last set to be protected or unprotect. That is,

sector protection or unprotection for these two sectors

depends on whether they were last protected or unprotect

using the method described in "Sector/Sector Group Pro-

tection and Chip Unprotect".

DATA PROTECTION

Note that the WP pin must not be left floating or uncon-

nected; inconsistent behavior of the device may result.

The MX29LV640T/B is designed to offer protection

against accidental erasure or programming caused by

spurious system level signals that may exist during power

transition. During power up the device automatically re-

sets the state machine in the Read mode. In addition,

with its control register architecture, alteration of the

memory contents only occurs after successful comple-

tion of specific command sequences. The device also

incorporates several features to prevent inadvertent write

cycles resulting fromVCC power-up and power-down tran-

sition or system noise.

TEMPORARY SECTOR GROUP UNPROTECT

OPERATION

This feature allows temporary unprotect of previously

protected sector to change data in-system.TheTempo-

rary Sector Unprotect mode is activated by setting the

RESET pin toVID(11.5V-12.5V). During this mode, for-

merly protected sectors can be programmed or erased

as unprotect sector. Once VID is remove from the RE-

SET pin, all the previously protected sectors are pro-

tected again.

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18

MX29LV640T/B

SECURED SILICON SECTOR

LOW VCC WRITE INHIBIT

The MX29LV640T/B features a OTP memory region

where the system may access through a command se-

quence to create a permanent part identification as so

called Electronic Serial Number (ESN) in the device.

Once this region is programmed, any further modifica-

tion on the region is impossible.The secured silicon sector

is a 128 words in length, and uses a Secured Silicon

Sector Indicator Bit (Q7) to indicate whether or not the

Secured Silicon Sector is locked when shipped from the

factory. This bit is permanently set at the factory and

cannot be changed, which prevent duplication of a fac-

tory locked part. This ensures the security of the ESN

once the product is shipped to the field.

When VCC is less than VLKO the device does not ac-

cept any write cycles. This protects data during VCC

power-up and power-down.The command register and

all internal program/erase circuits are disabled, and the

device resets. Subsequent writes are ignored until VCC

is greater thanVLKO. The system must provide the proper

signals to the control pins to prevent unintentional write

whenVCC is greater thanVLKO.

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5ns (typical) on CE or WE will

not initiate a write cycle.

The MX29LV640T/B offers the device with Secured Sili-

con Sector either factory locked or customer lockable.

The factory-locked version is always protected when

shipped from the factory , and has the Secured Silicon

Sector Indicator Bit permanently set to a "1". The cus-

tomer-lockable version is shipped with the Secured Sili-

con Sector unprotected, allowing customers to utilize

that sector in any form they prefer. The customer-lock-

able version has the secured sector Indicator Bit perma-

nently set to a "0". Therefore, the Secured Silicon Sec-

tor Indicator Bit prevents customer, lockable device from

being used to replace devices that are factory locked.

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE =VIL, CE =

VIH or WE = VIH. To initiate a write cycle CE and WE

must be a logical zero while OE is a logical one.

POWER-UP SEQUENCE

The MX29LV640T/B powers up in the Read only mode.

In addition, the memory contents may only be altered

after successful completion of the predefined command

sequences.

The system access the Secured Silicon Sector through

a command sequence (refer to "Enter Secured Silicon/

Exit Secured Silicon Sector command Sequence). After

the system has written the Enter Secured Silicon Sector

command sequence, it may read the Secured Silicon

Sector by using the address normally occupied by the

last sector SA134 (for MX29LV640T) or first sector SA0

(for MX29LV640B). Once entry the Secured Silicon Sec-

tor the operation of boot sectors is disabled but the op-

eration of main sectors is as normally.This mode of op-

eration continues until the system issues the Exit Se-

cured Silicon Sector command sequence, or until power

is removed from the device. On power-up, or following a

hardware reset, the device reverts to sending command

to sector SA0.

POWER-UP WRITE INHIBIT

IfWE=CE=VIL and OE=VIH during power up, the device

does not accept commands on the rising edge of WE.

The internal state machine is automatically reset to the

read mode on power-up.

POWER SUPPLY DE COUPLING

In order to reduce power switching effect, each device

should have a 0.1uF ceramic capacitor connected be-

tween itsVCC and GND.

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19

MX29LV640T/B

FACTORY LOCKED:Secured Silicon Sector

Programmed and Protected At the Factory

In device with an ESN, the Secured Silicon Sector is

protected when the device is shipped from the factory.

The Secured Silicon Sector cannot be modified in any

way.A factory locked device has an 8-word random ESN

at address 3FFF70h-3FFF77h (for MX29LV640T) or

000000h-000007h (for MX29LV640B).

CUSTOMER LOCKABLE:Secured Silicon

Sector NOT Programmed or Protected At the

Factory

As an alternative to the factory-locked version, the device

may be ordered such that the customer may program

and protect the 128-word Secured Silicon Sector.

Programming and protecting the Secured Silicon Sector

must be used with caution since, once protected, there

is no procedure available for unprotected the Secured

Silicon Sector area and none of the bits in the Secured

Silicon Sector memory space can be modified in any

way.

The Secured Silicon Sector area can be protected using

one of the following procedures:

Write the three-cycle Enter Secured Silicon Sector Region

command sequence, and then follow the in-system

sector protect algorithm as shown in Figure 2, except

that RESET may be at either VIH or VID.This allows in-

system protection of the Secured Silicon Sector without

raising any device pin to a high voltage. Note that method

is only applicable to the Secured Silicon Sector.

Write the three-cycle Enter Secured Silicon Sector Region

command sequence, and then alternate method of sector

protection described in the :Sector Group Protection and

Unprotect" section.

Once the Secured Silicon Sector is programmed, locked

and verified, the system must write the Exit Secured

Silicon Sector Region command sequence to return to

reading and writing the remainder of the array.

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MX29LV640T/B

Erase Resume (30H) commands are valid only while the

Sector Erase operation is in progress. Either of the two

reset command sequences will reset the device (when

applicable).

SOFTWARE COMMAND DEFINITIONS

Device operations are selected by writing specific ad-

dress and data sequences into the command register.

Writing incorrect address and data values or writing them

in the improper sequence will reset the device to the

read mode. Table 2 defines the valid register command

sequences. Note that the Erase Suspend (B0H) and

All addresses are latched on the falling edge of WE or

CE, whichever happens later.All data are latched on ris-

ing edge of WE or CE, whichever happens first.

TABLE 2. MX29LV640T/B COMMAND DEFINITIONS

First Bus

Cycle

Second Bus Third Bus

Cycle Cycle

Fourth Bus

Cycle

Fifth Bus Sixth Bus

Cycle Cycle

Command

Bus

Cycles Addr Data Addr Data Addr Data Addr

Data Addr Data Addr Data

Read (Note 5)

1

RA

RD

Reset (Note 6)

XXX F0

Automatic Select (Note 7)

Manufacturer ID

Word

Byte

Word

Byte

4

3

4

6

1

555 AA

AAA AA

555 AA

AAA AA

555 AA

AAA AA

555 AA

AAA AA

555 AA

AAA AA

555 AA

AAA AA

555 AA

AAA AA

555 AA

AAA AA

555 AA

AAA AA

2AA 55

555 55

2AA 55

555 55

2AA 55

555 55

2AA 55

555 55

2AA 55

555 55

2AA 55

555 55

2AA 55

555 55

2AA 55

555 55

2AA 55

555 55

555 90

AAA 90

555 90

AAA 90

555 90

AAA 90

555 90

AAA 90

555 88

AAA 88

555 90

AAA 90

555 A0

AAA A0

555 80

AAA 80

555 80

AAA 80

X00

X01

X02

X03

X06

C2H

DDI

Device ID

Secured Sector Fact- Word

see

ory Protect (Note 9)

Sector Group Protect

Verify (Note 8)

Enter Secured Silicon

Sector

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

note 9

(SA)X02 xx00/

(SA)X04 xx01

Exit Secured Silicon

Sector

XXX

PA

00

Program

PD

AA

PA

Chip Erase

555

AAA

555

AAA

2AA 55 555 10

555 55 AAA 10

2AA 55 SA 30

555 55 SA 30

Sector Erase

CFI Query (Note 12)

55

98

B0

30

AA

BA

Erase Suspend (Note 10)

Erase Resume (Note 11)

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21

MX29LV640T/B

Legend:

X=Don't care

PD=Data to be programmed at location PA. Data is

latched on the rising edge of WE or CE pulse.

SA=Address of the sector to be erase or verified (in

autoselect mode).

RA=Address of the memory location to be read.

RD=Data read from location RA during read operation.

PA=Address of the memory location to be programmed.

Addresses are latched on the falling edge of the WE or

CE pulse, whichever happen later.

DDI=Data of device identifier

Address bits A21-A12 uniquely select any sector.

C2H for manufacture code

C9/CBH (Top/Bottom) for device code

Notes:

1. See Table 1 for descriptions of bus operations.

2. All values are in hexadecimal.

3. Except when reading array or automatic select data, all bus cycles are write operation.

4. Address bits are don't care for unlock and command cycles, except when PA or SA is required.

5. No unlock or command cycles required when device is in read mode.

6. The Reset command is required to return to the read mode when the device is in the automatic select mode or if

Q5 goes high.

7. The fourth cycle of the automatic select command sequence is a read cycle.

8. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. In the third

cycle of the command sequence, address bit A21=0 to verify sectors 0~63, A21=1 to verify sectors 64~134 for

Top Boot device.

9. The data is 88h for factory locked and 08h for not factory locked.

10.The system may read and program functions in non-erasing sectors, or enter the automatic select mode, when in

the erase Suspend mode.The Erase Suspend command is valid only during a sector erase operation.

11.The Erase Resume command is valid only during the Erase Suspend mode.

12.Command is valid when device is ready to read array data or when device is in automatic select mode.

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22

MX29LV640T/B

READING ARRAY DATA

SILICON ID READ COMMAND SEQUENCE

The SILICON ID READ command sequence allows the

host system to access the manufacturer and devices

codes, and determine whether or not a sector is protected.

Table 2 shows the address and data requirements.

This method is an alternative to that shown in Table 1,

which is intended for PROM programmers and requires

V^IDon address bit A9.

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data.The device is also ready to read array data

after completing an Automatic Program or Automatic

Erase algorithm.

After the device accepts an Erase Suspend command,

the device enters the Erase Suspend mode. The sys-

tem can read array data using the standard read tim-

ings, except that if it reads at an address within erase-

suspended sectors, the device outputs status data. After

completing a programming operation in the Erase

Suspend mode, the system may once again read array

data with the same exception. See Erase Suspend/Erase

Resume Commands for more information on this mode.

The system must issue the reset command to re-en-

able the device for reading array data if Q5 goes high, or

while in the automatic select mode. See the "Reset

Command" section, next.

The SILICON ID READ command sequence is initiated

by writing two unlock cycles, followed by the SILICON

ID READ command.The device then enters the SILICON

ID READ mode, and the system may read at any address

any number of times, without initiating another command

sequence. A read cycle at address XX00h retrieves the

manufacturer code. A read cycle at address XX01h

returns the device code. A read cycle containing a sector

address (SA) and the address 02h returns 01h if that

sector is protected, or 00h if it is unprotected. Refer to

Table for valid sector addresses.

The system must write the reset command to exit the

automatic select mode and return to reading array data.

RESET COMMAND

Writing the reset command to the device resets the

device to reading array data. Address bits are don't care

for this command.

Byte/Word PROGRAM COMMAND SEQUENCE

The command sequence requires four bus cycles, and

is initiated by writing two unlock write cycles, followed

by the program set-up command. The program address

and data are written next, which in turn initiate the

Embedded Program algorithm.The system is not required

to provide further controls or timings. The device

automatically generates the program pulses and verifies

the programmed cell margin. Table 1 shows the address

and data requirements for the byte program command

sequence.

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the device to reading array

data. Once erasure begins, however, the device ignores

reset commands until the operation is complete.

The reset command may be written between the se-

quence cycles in a program command sequence before

programming begins. This resets the device to reading

array data (also applies to programming in Erase Suspend

mode). Once programming begins, however, the device

ignores reset commands until the operation is complete.

When the Embedded Program algorithm is complete, the

device then returns to reading array data and addresses

are no longer latched. The system can determine the

status of the program operation by using Q7, Q6, or RY/

BY. See "Write Operation Status" for information on these

status bits.

The reset command may be written between the

sequence cycles in an SILICON ID READ command

sequence. Once in the SILICON ID READ mode, the

reset command must be written to return to reading array

data (also applies to SILICON ID READ during Erase

Suspend).

Any commands written to the device during the

Embedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the programming

operation. The Byte/Word Program command sequence

should be reinitiated once the device has reset to reading

array data, to ensure data integrity.

If Q5 goes high during a program or erase operation,

writing the reset command returns the device to reading

array data (also applies during Erase Suspend).

Programming is allowed in any sequence and across

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23

MX29LV640T/B

sector boundaries. A bit cannot be programmed from a

"0" back to a "1". Attempting to do so may halt the

operation and set Q5 to "1" ,” or cause the Data Polling

algorithm to indicate the operation was successful.

However, a succeeding read will show that the data is

still "0". Only erase operations can convert a "0" to a

"1".

The MX29LV640T/B contains a Silicon-ID-Read opera-

tion to supplement traditional PROM programming meth-

odology. The operation is initiated by writing the read

silicon ID command sequence into the command regis-

ter. Following the command write, a read cycle with

A1=VIL,A0=VIL retrieves the manufacturer code of C2H.

A read cycle with A1=VIL, A0=VIH returns the device

code of 22C9H/22CBH for MX29LV640T/B.

SETUP AUTOMATIC CHIP/SECTOR ERASE

Chip erase is a six-bus cycle operation. There are two

"unlock" write cycles. These are followed by writing the

"set-up" command 80H. Two more "unlock" write cycles

are then followed by the chip erase command 10H, or

the sector erase command 30H.

TABLE 3. SILICON ID CODE

Pins

A0 A1

Q7

1

Q6

1

Q5

0

Q4

0

Q3

0

Q2

0

Q1

1

Q0

0

Code(Hex)

C2H

Manufacturecode

VIL VIL

Device code for MX29LV640T VIH VIL

1

0

1

0

1

22C9H(word)

XXC9H(byte)

22CBH(word)

XXCBH(byte)

Device code for MX29LV640B VIH VIL

1

0

1

0

1

returns to reading array data and addresses are no longer

latched.

AUTOMATIC CHIP/SECTOR ERASE COM-

MAND

Figure 3 illustrates the algorithm for the erase operation.

See the Erase/Program Operations tables in "AC Char-

acteristics" for parameters, and to Figure 16 for timing

diagrams.

The device does not require the system to preprogram

prior to erase.The Automatic Erase algorithm automati-

cally pre-program and verifies the entire memory for an

all zero data pattern prior to electrical erase.The system

is not required to provide any controls or timings during

these operations. Table 2 shows the address and data

requirements for the chip erase command sequence.

Any commands written to the chip during the Automatic

Erase algorithm are ignored. Note that a hardware reset

during the chip erase operation immediately terminates

the operation.The Chip Erase command sequence should

be reinitiated once the device has returned to reading

array data, to ensure data integrity.

The system can determine the status of the erase op-

eration by using Q7, Q6, Q2, or RY/BY. See "Write Op-

eration Status" for information on these status bits.When

the Automatic Erase algorithm is complete, the device

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24

MX29LV640T/B

mand is issued during the sector erase operation, the

device requires a maximum 20us to suspend the sector

erase operation.However,When the Erase Suspend com-

mand is written during the sector erase time-out, the

device immediately terminates the time-out period and

suspends the erase operation. After this command has

been executed, the command register will initiate erase

suspend mode. The state machine will return to read

mode automatically after suspend is ready. At this time,

state machine only allows the command register to re-

spond to the Erase Resume, program data to, or read

data from any sector not selected for erasure.

SECTOR ERASE COMMANDS

The Automatic Sector Erase does not require the device

to be entirely pre-programmed prior to executing the

Automatic Set-up Sector Erase command and

Automatic Sector Erase command. Upon executing the

Automatic Sector Erase command, the device will

automatically program and verify the sector(s) memory

for an all-zero data pattern. The system is not required

to provide any control or timing during these operations.

When the sector(s) is automatically verified to contain

an all-zero pattern, a self-timed sector erase and verify

begin. The erase and verify operations are complete

when the data on Q7 is "1" and the data on Q6 stops

toggling for two consecutive read cycles, at which time

the device returns to the Read mode. The system is not

required to provide any control or timing during these

operations.

The system can determine the status of the program

operation using the Q7 or Q6 status bits, just as in the

standard program operation. After an erase-suspend pro-

gram operation is complete, the system can once again

read array data within non-suspended blocks.

When using the Automatic Sector Erase algorithm, note

that the erase automatically terminates when adequate

erase margin has been achieved for the memory array

(no erase verification command is required). Sector

erase is a six-bus cycle operation. There are two

"unlock" write cycles. These are followed by writing the

set-up command 80H. Two more "unlock" write cycles

are then followed by the sector erase command 30H.

The sector address is latched on the falling edge of WE

or CE, whichever happens later , while the command

(data) is latched on the rising edge of WE or CE,

whichever happens first. Sector addresses selected are

loaded into internal register on the sixth falling edge of

WE or CE, whichever happens later. Each successive

sector load cycle started by the falling edge of WE or

CE, whichever happens later must begin within 50us

from the rising edge of the preceding WE or CE,

whichever happens first. Otherwise, the loading period

ends and internal auto sector erase cycle starts.

(Monitor Q3 to determine if the sector erase timer

window is still open, see section Q3, Sector Erase

Timer.) Any command other than Sector Erase(30H) or

Erase Suspend(B0H) during the time-out period resets

the device to read mode.

ERASE RESUME

This command will cause the command register to clear

the suspend state and return back to Sector Erase mode

but only if an Erase Suspend command was previously

issued. Erase Resume will not have any effect in all

other conditions. Another Erase Suspend command can

be written after the chip has resumed erasing.

QUERY COMMAND AND COMMON FLASH

INTERFACE (CFI) MODE

MX29LV640T/B is capable of operating in the CFI mode.

This mode all the host system to determine the manu-

facturer of the device such as operating parameters and

configuration.Two commands are required in CFI mode.

Query command of CFI mode is placed first, then the

Reset command exits CFI mode.These are described in

Table 3.

The single cycle Query command is valid only when the

device is in the Read mode, including Erase Suspend,

Standby mode, and Read ID mode;however, it is ignored

otherwise.

ERASE SUSPEND

The Reset command exits from the CFI mode to the

Read mode, or Erase Suspend mode, or read ID mode.

The command is valid only when the device is in the CFI

mode.

This command only has meaning while the state ma-

chine is executing Automatic Sector Erase operation,

and therefore will only be responded during Automatic

Sector Erase operation. When the Erase Suspend com-

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MX29LV640T/B

Table 4-1. CFI mode: Identification Data Values

(All values in these tables are in hexadecimal)

Description

Addressh Addressh

Datah

(x16)

10

(x8)

20

22

24

26

28

2A

2C

2E

30

32

34

Query-unique ASCII string "QRY"

0051

0052

0059

0002

0000

0040

0000

11

12

Primary vendor command set and control interface ID code

Address for primary algorithm extended query table

13

14

15

16

Alternate vendor command set and control interface ID code (none)

Address for secondary algorithm extended query table (none)

17

18

19

1A

Table 4-2. CFI Mode: System Interface Data Values

Description

Addressh Addressh

Datah

(x16)

1B

1C

1D

1E

1F

20

(x8)

36

VCC supply, minimum (2.7V)

0027

0036

0000

0004

0000

000A

0000

0005

0000

0004

0000

VCC supply, maximum (3.6V)

38

VPP supply, minimum (none)

3A

3C

3E

40

VPP supply, maximum (none)

Typical timeout for single word/byte write (2^Nus)

Typical timeout for maximum size buffer write (2^Nus)

Typical timeout for individual block erase (2^Nms)

Typical timeout for full chip erase (2^Nms)

Maximum timeout for single word/byte write times (2^NX Typ)

Maximum timeout for maximum size buffer write times (2^NX Typ)

Maximum timeout for individual block erase times (2^NX Typ)

Maximum timeout for full chip erase times (not supported)

21

42

22

44

23

46

24

48

25

4A

4C

26

Table 4-3. CFI Mode: Device Geometry Data Values

Description

Addressh Addressh

Datah

(x16)

27

(x8)

4E

50

Device size (2ⁿbytes)

0017

0002

0000

Flash device interface code (02=asynchronous x8/x16)

28

29

52

Maximum number of bytes in multi-byte write (not supported)

2A

2B

54

56

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MX29LV640T/B

Number of erase block regions

2C

2D

58

5A

5C

5E

60

62

64

66

68

6A

6C

6E

70

72

74

76

78

0002

0007

Erase block region 1 information

[2E,2D] = # of blocks in region -1

[30, 2F] = size in multiples of 256-bytes

2E

0000

2F

0020

30

0000

31h

32h

33h

34h

35h

36h

37h

38h

39h

3Ah

3Bh

3Ch

007Eh

0000h

0001h

0000h

Erase Block Region 2 Information (refer to CFI publication 100)

Erase Block Region 3 Information (refer to CFI publication 100)

Erase Block Region 4 Information (refer to CFI publication 100)

Table 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values

Description

Addressh Addressh

Datah

(x16)

40

(x8)

80

82

84

86

88

8A

8C

8E

90

92

94

96

98

9A

Query-unique ASCII string "PRI"

0050

0052

0049

0031

0000

0002

0004

0001

0004

0000

00h

41

42

Major version number, ASCII

43

Minor version number, ASCII

44

Address sensitive unlock (0=required, 1= not required)

Erase suspend (2= to read and write)

Sector protect (N= # of sectors/group)

Temporarysectorunprotect(1=supported)

Sector protect/unprotect scheme

45

46

47

48

49

SimultaneousR/Woperation(0=notsupported)

Burst mode type (0=not supported)

4A

4B

4C

4Dh

Page mode type (0=not supported)

ACC (Acceleration) Supply Minimum

00h=NotSupported,D7-D4:Volt,D3-D0:100mV

ACC (Acceleration) Supply Maximum

00h=NotSupported,D7-D4:Volt,D3-D0:100mV

Top/Bottom Boot Sector Flag

4Eh

4Fh

9C

9E

00h

0002h/

0003h

02h=Bottom Boot Device, 03h=Top Boot Device

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MX29LV640T/B

WRITE OPERATION STATUS

The device provides several bits to determine the status

of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/BY.

Table 10 and the following subsections describe the func-

tions of these bits. Q7, RY/BY, and Q6 each offer a

method for determining whether a program or erase op-

eration is complete or in progress. These three bits are

discussed first.

Table 5. Write Operation Status

Status

Q7

Q6

Q5

Q3

Q2 RY/BY

Note1

Note2

Byte/Word Program in Auto Program Algorithm

Auto Erase Algorithm

Q7

Toggle

0

N/A

1

No

0

Toggle

0

1

0

Toggle

0

1

Erase Suspend Read

(Erase Suspended Sector)

No

Toggle

N/A Toggle

In Progress

Erase Suspended Mode

Erase Suspend Read

Data

Q7

Data Data Data Data

1

0

(Non-Erase Suspended Sector)

Erase Suspend Program

Toggle

0

1

N/A N/A

Byte/Word Program in Auto Program Algorithm

Q7

N/A

1

No

Toggle

Exceeded

Time Limits Auto Erase Algorithm

0

Toggle

1

Toggle

0

Erase Suspend Program

Q7

N/A N/A

Notes:

1. Performing successive read operations from the erase-suspended sector will cause Q2 to toggle.

2. Performing successive read operations from any address will cause Q6 to toggle.

3. Reading the byte address being programmed while in the erase-suspend program mode will indicate logic "1" at the

Q2 bit.

However, successive reads from the erase-suspended sector will cause Q2 to toggle.

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MX29LV640T/B

after the rising edge of the final WE or CE, whichever

happens first pulse in the command sequence (prior to

the program or erase operation), and during the sector

time-out.

Q7: Data Polling

The Data Polling bit, Q7, indicates to the host system

whether an Automatic Algorithm is in progress or com-

pleted, or whether the device is in Erase Suspend. Data

Polling is valid after the rising edge of the finalWE pulse

in the program or erase command sequence.

During an Automatic Program or Erase algorithm opera-

tion, successive read cycles to any address cause Q6

to toggle. The system may use either OE or CE to con-

trol the read cycles.When the operation is complete, Q6

stops toggling.

During the Automatic Program algorithm, the device out-

puts on Q7 the complement of the datum programmed

to Q7.This Q7 status also applies to programming dur-

ing Erase Suspend.When the Automatic Program algo-

rithm is complete, the device outputs the datum pro-

grammed to Q7.The system must provide the program

address to read valid status information on Q7. If a pro-

gram address falls within a protected sector, Data Poll-

ing on Q7 is active for approximately 1 us, then the de-

vice returns to reading array data.

After an erase command sequence is written, if all sec-

tors selected for erasing are protected, Q6 toggles for

100us and returns to reading array data. If not all se-

lected sectors are protected, the Automatic Erase algo-

rithm erases the unprotected sectors, and ignores the

selected sectors that are protected.

The system can use Q6 and Q2 together to determine

whether a sector is actively erasing or is erase suspended.

When the device is actively erasing (that is, the Auto-

matic Erase algorithm is in progress), Q6 toggling.When

the device enters the Erase Suspend mode, Q6 stops

toggling. However, the system must also use Q2 to de-

termine which sectors are erasing or erase-suspended.

Alternatively, the system can use Q7.

During the Automatic Erase algorithm, Data Polling pro-

duces a "0" on Q7.When the Automatic Erase algorithm

is complete, or if the device enters the Erase Suspend

mode, Data Polling produces a "1" on Q7.This is analo-

gous to the complement/true datum output described for

the Automatic Program algorithm: the erase function

changes all the bits in a sector to "1" prior to this, the

device outputs the "complement,” or "0".” The system

must provide an address within any of the sectors se-

lected for erasure to read valid status information on Q7.

If a program address falls within a protected sector, Q6

toggles for approximately 2us after the program com-

mand sequence is written, then returns to reading array

data.

After an erase command sequence is written, if all sec-

tors selected for erasing are protected, Data Polling on

Q7 is active for approximately 100 us, then the device

returns to reading array data. If not all selected sectors

are protected, the Automatic Erase algorithm erases the

unprotected sectors, and ignores the selected sectors

that are protected.

Q6 also toggles during the erase-suspend-program mode,

and stops toggling once the Automatic Program algo-

rithm is complete.

Table 4 shows the outputs for Toggle Bit I on Q6.

When the system detects Q7 has changed from the

complement to true data, it can read valid data at Q7-Q0

on the following read cycles. This is because Q7 may

change asynchronously with Q0-Q6 while Output Enable

(OE) is asserted low.

Q2:Toggle Bit II

The "Toggle Bit II" on Q2, when used with Q6, indicates

whether a particular sector is actively erasing (that is,

the Automatic Erase algorithm is in process), or whether

that sector is erase-suspended. Toggle Bit II is valid

after the rising edge of the final WE or CE, whichever

happens first pulse in the command sequence.

Q6:Toggle BIT I

Toggle Bit I on Q6 indicates whether an Automatic Pro-

gram or Erase algorithm is in progress or complete, or

whether the device has entered the Erase Suspend mode.

Toggle Bit I may be read at any address, and is valid

Q2 toggles when the system reads at addresses within

those sectors that have been selected for erasure. (The

system may use either OE or CE to control the read

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29

MX29LV640T/B

cycles.) But Q2 cannot distinguish whether the sector

is actively erasing or is erase-suspended. Q6, by com-

parison, indicates whether the device is actively eras-

ing, or is in Erase Suspend, but cannot distinguish which

sectors are selected for erasure. Thus, both status bits

are required for sectors and mode information. Refer to

Table 4 to compare outputs for Q2 and Q6.

only operating functions of the device under this condi-

tion.

If this time-out condition occurs during sector erase op-

eration, it specifies that a particular sector is bad and it

may not be reused. However, other sectors are still func-

tional and may be used for the program or erase opera-

tion. The device must be reset to use other sectors.

Write the Reset command sequence to the device, and

then execute program or erase command sequence. This

allows the system to continue to use the other active

sectors in the device.

Reading Toggle Bits Q6/ Q2

Whenever the system initially begins reading toggle bit

status, it must read Q7-Q0 at least twice in a row to

determine whether a toggle bit is toggling. Typically, the

system would note and store the value of the toggle bit

after the first read. After the second read, the system

would compare the new value of the toggle bit with the

first. If the toggle bit is not toggling, the device has

completed the program or erase operation. The system

can read array data on Q7-Q0 on the following read cycle.

If this time-out condition occurs during the chip erase

operation, it specifies that the entire chip is bad or com-

bination of sectors are bad.

If this time-out condition occurs during the byte/word pro-

gramming operation, it specifies that the entire sector

containing that byte is bad and this sector may not be

reused, (other sectors are still functional and can be re-

used).

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of Q5 is high

(see the section on Q5). If it is, the system should then

determine again whether the toggle bit is toggling, since

the toggle bit may have stopped toggling just as Q5 went

high. If the toggle bit is no longer toggling, the device

has successfully completed the program or erase opera-

tion. If it is still toggling, the device did not complete the

operation successfully, and the system must write the

reset command to return to reading array data.

The time-out condition may also appear if a user tries to

program a non blank location without erasing. In this

case the device locks out and never completes the Au-

tomatic Algorithm operation. Hence, the system never

reads a valid data on Q7 bit and Q6 never stops toggling.

Once the Device has exceeded timing limits, the Q5 bit

will indicate a "1". Please note that this is not a device

failure condition since the device was incorrectly used.

The Q5 failure condition may appear if the system tries

to program a to a "1" location that is previously pro-

grammed to "0". Only an erase operation can change a

"0" back to a "1".” Under this condition, the device halts

the operation, and when the operation has exceeded the

timing limits, Q5 produces a "1".

The remaining scenario is that system initially determines

that the toggle bit is toggling and Q5 has not gone high.

The system may continue to monitor the toggle bit and

Q5 through successive read cycles, determining the sta-

tus as described in the previous paragraph. Alternatively,

it may choose to perform other system tasks. In this

case, the system must start at the beginning of the al-

gorithm when it returns to determine the status of the

operation.

Q3:Sector Erase Timer

After the completion of the initial sector erase command

sequence, the sector erase time-out will begin. Q3 will

remain low until the time-out is complete. Data Polling

andToggle Bit are valid after the initial sector erase com-

mand sequence.

Q5:Program/Erase Timing

Q5 will indicate if the program or erase time has exceeded

the specified limits (internal pulse count). Under these

conditions Q5 will produce a "1". This time-out condition

indicates that the program or erase cycle was not suc-

cessfully completed. Data Polling andToggle Bit are the

If Data Polling or the Toggle Bit indicates the device has

been written with a valid erase command, Q3 may be

used to determine if the sector erase timer window is

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30

MX29LV640T/B

still open. If Q3 is high ("1") the internally controlled

erase cycle has begun; attempts to write subsequent

commands to the device will be ignored until the erase

operation is completed as indicated by Data Polling or

Toggle Bit. If Q3 is low ("0"), the device will accept addi-

tional sector erase commands. To insure the command

has been accepted, the system software should check

the status of Q3 prior to and following each subsequent

sector erase command. If Q3 were high on the second

status check, the command may not have been accepted.

If the time between additional erase commands from the

system can be less than 50us, the system need not to

monitor Q3.

RY/BY:READY/BUSY OUTPUT

The RY/BY is a dedicated, open-drain output pin that

indicates whether an Embedded Algorithm is in progress

or complete. The RY/BY status is valid after the rising

edge of the final WE pulse in the command sequence.

Since RY/BY is an open-drain output, several RY/BY pins

can be tied together in parallel with a pull-up resistor to

VCC .

If the output is low (Busy), the device is actively erasing

or programming. (This includes programming in the Erase

Suspend mode.) If the output is high (Ready), the device

is ready to read array data (including during the Erase

Suspend mode), or is in the standby mode.

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MX29LV640T/B

OPERATING RATINGS

ABSOLUTE MAXIMUM RATINGS

StorageTemperature

Commercial (C) Devices

Plastic Packages . . . . . . . . . . . . . ..... -65^oC to +150^oC

Ambient Temperature (T^A). . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

AmbientTemperature

with Power Applied. . . . . . . . . . . . . .... -65^oC to +125^oC

Voltage with Respect to Ground

Ambient Temperature (T^A). . . . . . . . . . -40°C to +85°C

V^CCSupply Voltages

V^CCfor full voltage range. . . . . . . . . . . +2.7 V to 3.6 V

VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V

A9, OE, and

Operating ranges define those limits between which the

functionality of the device is guaranteed.

RESET (Note 2) . . . . . . . . . . . ....-0.5 V to +12.5 V

All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is -0.5 V.

During voltage transitions, input or I/O pins may over-

shoot VSS to -2.0 V for periods of up to 20 ns. See

Figure 6. Maximum DC voltage on input or I/O pins is

VCC +0.5 V. During voltage transitions, input or I/O

pins may overshoot to VCC +2.0 V for periods up to

20 ns. See Figure 7.

2. Minimum DC input voltage on pins A9, OE, and

RESET is -0.5 V. During voltage transitions, A9, OE,

and RESET may overshoot VSS to -2.0 V for periods

of up to 20 ns. See Figure 6. Maximum DC input volt-

age on pin A9 is +12.5V which may overshoot to 14.0

V for periods up to 20 ns.

3.No more than one output may be shorted to ground at

a time. Duration of the short circuit should not be

greater than one second.

Stresses above those listed under "Absolute Maximum

Ratings" may cause permanent damage to the device.

This is a stress rating only; functional operation of the

device at these or any other conditions above those in-

dicated in the operational sections of this data sheet is

not implied. Exposure of the device to absolute maxi-

mum rating conditions for extended periods may affect

device reliability.

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MX29LV640T/B

DC CHARACTERISTICS

TA=-40°C to 85°C, VCC=2.7V~3.6V

Para-

meter Description

Test Conditions

Min

Typ

Max

Unit

I LI

Input Load Current (Note 1)

VIN = VSS to VCC ,

VCC = VCC max

±1.0

uA

I LIT A9 Input Leakage Current

I LO Output Leakage Current

VCC=VCC max; A9 = 12.5V

VOUT = VSS to VCC ,

VCC= VCC max

35

uA

±1.0

ICC1 VCC Active Read Current

(Notes 2,3)

CE= VIL, OE = VIH 5 MHz

1 MHz

9

2

16

4

mA

ICC2 VCC Active Write Current

(Notes 2,4,6)

CE= V IL , OE = V IH

26

30

ICC3 VCC Standby Current

(Note 2)

CE,RESET=VCC±0.3V

WP=VIH

0.2

15

uA

ICC4 VCC Reset Current

(Note 2)

RESET=VSS±0.3V

WP=VIH

ICC5 Automatic Sleep Mode

(Note 2,5)

VIL = V SS ±0.3 V,

VIH = VCC ±0.3 V,

WP=VIH

VIL

Input Low Voltage

-0.5

0.7xVcc

11.5

0.8

Vcc+0.3

12.5

V

VIH Input High Voltage

VID Voltage for Autoselect and

Temporary Sector Unprotect

VOL Output Low Voltage

VOH1 Output High Voltage

VOH2

VCC = 3.0 V ±10%

IOL= 4.0mA,VCC=VCC min

IOH=-2.0mA,VCC=VCC min

IOH=-100uA,VCC=VCC min

0.45

V

0.85VCC

VCC-0.4

1.5

VLKO Low VCC Lock-Out Voltage

(Note 4)

Notes:

1. On the WP pin only, the maximum input load current when WP = VIL is ±5.0uA

2. Maximum ICC specifications are tested with VCC = VCC max.

3. The ICC current listed is typically is less than 2 mA/MHz, with OE at VIH . Typical specifications are for VCC =

3.0V.

4. ICC active while Embedded Erase or Embedded Program is in progress.

5. Automatic sleep mode enables the low power mode when addresses remain stable for t ACC + 30 ns.Typical sleep

mode current is 200 nA.

6. Not 100% tested.

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MX29LV640T/B

SWITCHING TEST CIRCUITS

TEST SPECIFICATIONS

Test Condition

Output Load

90

1 TTL gate

100

120

Unit

pF

DEVICE UNDER

TEST

2.7K ohm

Output Load Capacitance, CL 30

(including jig capacitance)

Input Rise and Fall Times

Input Pulse Levels

3.3V

5

ns

V

0.0-3.0

1.5

CL

6.2K ohm

DIODES=IN3064

OR EQUIVALENT

Input timing measurement

reference levels

V

Output timing measurement

reference levels

1.5

V

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don't Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State(High Z)

SWITCHING TEST WAVEFORMS

3.0V

Measurement Level

1.5V

0.0V

INPUT

OUTPUT

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MX29LV640T/B

AC CHARACTERISTICS

Read-Only Operations

Parameter

TA=-40°C to 85°C, VCC=2.7V~3.6V

Speed Options

90 120 Unit

Std.

tRC

tACC

tCE

tOE

tDF

Description

Test Setup

Read CycleTime (Note 1)

Address to Output Delay

Min

CE, OE=VIL Max

90

35

30

120

50

ns

Chip Enable to Output Delay

Output Enable to Output Delay

Chip Enable to Output High Z (Note 1)

Output Enable to Output High Z (Note 1)

Output Hold Time From Address, CE or OE,

whichever Occurs First

OE=VIL

Max

Min

30

tDF

30

tOH

0

Read

Min

0

ns

tOEH

Output Enable HoldTime Toggle and

10

(Note 1)

Data Polling

Notes:

1. Not 100% tested.

2. See SWITCHING TEST CIRCUITS and TEST SPECIFICATIONS TABLE for test specifications.

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MX29LV640T/B

Fig 1. COMMAND WRITE OPERATION

VCC

5V

VIH

Addresses

ADD Valid

VIL

tAH

tAS

VIH

VIL

WE

tOES

tWPH

tWP

tCWC

VIH

VIL

CE

OE

tCS

tCH

tDH

VIH

VIL

tDS

VIH

VIL

Data

DIN

READ/RESET OPERATION

Fig 2. READ TIMING WAVEFORMS

tRC

VIH

ADD Valid

Addresses

VIL

tCE

VIH

CE

tRH

VIL

tRH

VIH

WE

tDF

VIL

VIH

VIL

tOEH

tOE

OE

tOH

tACC

HIGH Z

VOH

VOL

Outputs

DATA Valid

VIH

VIL

RESET

RY/BY

0V

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36

MX29LV640T/B

AC CHARACTERISTICS

Parameter

Description

Test Setup All Speed Options Unit

tREADY1

RESET PIN Low (During Automatic Algorithms)

to Read orWrite (See Note)

MAX

20

us

tREADY2

RESET PIN Low (NOT During Automatic

Algorithms) to Read orWrite (See Note)

MAX

500

ns

tRP

RESET PulseWidth (NOT During Automatic Algorithms) MIN

500

50

0

ns

us

tRH

RESET HighTime Before Read(See Note)

RY/BY Recovery Time(to CE, OE go low)

RESET Low to Standby Mode

MIN

tRB

tRPD

20

Note:Not 100% tested

Fig 3. RESET TIMING WAVEFORM

RY/BY

CE, OE

RESET

tRH

tRP

tReady2

Reset Timing NOT during Automatic Algorithms

tReady1

RY/BY

tRB

CE, OE

RESET

tRP

Reset Timing during Automatic Algorithms

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MX29LV640T/B

ERASE/PROGRAM OPERATION

Fig 4. AUTOMATIC CHIP/SECTOR ERASE TIMING WAVEFORM

Erase Command Sequence(last two cycle)

Read Status Data

tWC

tAS

VA

2AAh

SA

Address

555h for chip erase

tAH

CE

tCH

OE

tWHWH2

tWP

WE

tCS

tWPH

tDS tDH

In

Progress

55h

30h

Complete

Data

10 for Chip Erase

tBUSY

tRB

RY/BY

tVCS

VCC

NOTES:

1.SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").

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MX29LV640T/B

Fig 5. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 80H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 10H Address 555H

Data Poll

from system

YES

No

DATA = FFh ?

YES

Auto Erase Completed

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MX29LV640T/B

Fig 6. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 80H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 30H Sector Address

NO

Last Sector

to Erase ?

YES

Data Poll from System

NO

Data=FFh?

YES

Auto Sector Erase Completed

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MX29LV640T/B

Fig 7. ERASE SUSPEND/RESUME FLOWCHART

START

Write Data B0H

ERASE SUSPEND

NO

Toggle Bit checking Q6

not toggled

YES

Read Array or

Program

Reading or

NO

Programming End

YES

Write Data 30H

ERASE RESUME

Continue Erase

Another

NO

Erase Suspend ?

YES

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MX29LV640T/B

Fig 8. SECURED SILICON SECTOR PROTECTED ALGORITHMS FLOWCHART

START

Enter Secured Silicon Sector

Wait 1us

First Wait Cycle Data=60h

Second Wait Cycle Data=60h

A6=0, A1=1, A0=0

Wait 300us

No

Data = 01h ?

Yes

Device Failed

Write Reset Command

Secured Sector Protect Complete

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MX29LV640T/B

AC CHARACTERISTICS

Erase and Program Operations

Parameter

TA=-40°C to 85°C, VCC=2.7V~3.6V

Speed Options

90 120 Unit

Std.

tWC

tAS

Description

Write CycleTime (Note 1)

Address SetupTime

Min

90

45

120

ns

0

tASO

tAH

Address SetupTime to OE low during toggle bit polling

Address HoldTime

15

50

tAHT

Address HoldTime From CE or OE high during toggle

bit polling

0

tDS

Data SetupTime

Min

50

ns

tDH

Data HoldTime

0

20

0

tOEPH

tGHWL

Output Enable High during toggle bit polling

Read RecoveryTime BeforeWrite

(OE High to WE Low)

tGHEL

tCS

Read RecoveryTime BeforeWrite

CE Setup Time

Min

Typ

Min

0

ns

us

sec

us

ns

tCH

CE HoldTime

tWP

Write Pulse Width

35

50

tWPH

tWHWH1

Write PulseWidth High

30

9

Programming Operation

Byte

Word

11

1.6

50

0

tWHWH2

tVCS

Sector Erase Operation (Note 2)

VCC SetupTime (Note 1)

tRB

Write Recovery Time from RY/BY

Program/Erase Valid to RY/BY Delay

tBUSY

90

Notes:

1. Not 100% tested.

2. See the "Erase And Programming Performance" section for more information.

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MX29LV640T/B

Fig 9. AUTOMATIC PROGRAM TIMING WAVEFORMS

Program Command Sequence(last two cycle)

Read Status Data (last two cycle)

tWC

tAS

PA

XXXh

PA

Address

tAH

CE

tCH

OE

tWP

tWHWH1

WE

tCS

tWPH

tDS tDH

Status

A0h

PD

DOUT

Data

tBUSY

tRB

RY/BY

tVCS

VCC

NOTES:

1.PA=Program Address, PD=Program Data, DOUT is the true data the program address

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MX29LV640T/B

AC CHARACTERISTICS

Alternate CE Controlled Erase and Program Operations

Parameter

Speed Options

Std.

tWC

tAS

Description

90

120 Unit

Write CycleTime (Note 1)

Address SetupTime

Address HoldTime

Data SetupTime

Min

90

120

ns

0

tAH

45

50

tDS

tDH

Data HoldTime

0

tGHEL

Read RecoveryTime BeforeWrite

(OE High to WE Low)

WE Setup Time

tWS

Min

Typ

0

ns

tWH

WE HoldTime

tCP

CE Pulse Width

45

50

ns

tCPH

tWHWH1

CE Pulse Width High

Programming Operation

30

9

ns

Byte

us

Word

11

1.6

us

tWHWH2

Sector Erase Operation (Note 2)

sec

Notes:

1. Not 100% tested.

2.See the "Erase And Programming Performance" section for more information.

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MX29LV640T/B

Fig 10. CE CONTROLLED PROGRAM TIMING WAVEFORM

PA for program

555 for program

2AA for erase

SA for sector erase

555 for chip erase

Data Polling

Address

PA

tWC

tWH

tAS

tAH

WE

OE

tGHEL

tCP

tWHWH1 or 2

CE

tWS

tDS

tCPH

tBUSY

tDH

DOUT

Q7

Data

PD for program

30 for sector erase

10 for chip erase

A0 for program

55 for erase

tRH

RESET

RY/BY

NOTES:

1.PA=Program Address, PD=Program Data, DOUT=Data Out, Q7=complement of data written to device.

2.Figure indicates the last two bus cycles of the command sequence.

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MX29LV640T/B

Fig 11. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data A0H Address 555H

Write Program Data/Address

Data Poll

Increment

Address

from system

No

Verify Word Ok ?

YES

Last Address ?

YES

Auto Program Completed

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REV. 1.2, NOV. 05, 2003

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MX29LV640T/B

SECTOR GROUP PROTECT/CHIP UNPROTECT

Fig 12. Sector Group Protect / Chip Unprotect Waveform (RESET Control)

VID

VIH

RESET

SA, A6

A1, A0

Valid*

Sector Group Protect or Chip Unprotect

Verify

40h

Status

Data

60h

Sector Group Protect:150us

Chip Unprotect:15ms

1us

CE

WE

OE

Note: For sector group protect A6=0, A1=1, A0=0. For chip unprotect A6=1, A1=1, A0=0

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REV. 1.2, NOV. 05, 2003

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MX29LV640T/B

Fig 13. IN-SYSTEM SECTOR GROUP PROTECT/CHIP UNPROTECT ALGORITHMS WITH

RESET=VID

START

Protect all sectors:

PLSCNT=1

The indicated portion of

PLSCNT=1

the sector protect algorithm

must be performed

RESET=VID

for all unprotected sectors

RESET=VID

prior to issuing the first

sector unprotect address

Wait 1us

No

First Write

Temporary Sector

Unprotect Mode

Cycle=60h?

First Write

No

Temporary Sector

Unprotect Mode

Cycle=60h?

Yes

Set up sector address

No

All sectors

protected?

Sector Protect:

Write 60h to sector

address with

A6=0, A1=1, A0=0

Yes

Set up first sector address

Wait 150us

Sector Unprotect:

Write 60h to sector

address with

Verify Sector Protect:

Write 40h to sector

address with

Reset

PLSCNT=1

A6=1, A1=1, A0=0

A6=0, A1=1, A0=0

Increment PLSCNT

Wait 15 ms

Read from

sector address

with

A6=0, A1=1, A0=0

Verify Sector Unprotect:

Write 40h to sector

address with

No

Increment PLSCNT

A6=1, A1=1, A0=0

No

Data=01h?

Yes

PLSCNT=25?

Read from

sector address

with

Yes

A6=1, A1=1, A0=0

No

Device failed

Reset

Yes

Protect another

sector?

PLSCNT=1

No

PLSCNT=1000?

Data=00h?

Yes

No

Sector Protect

Algorithm

Yes

Remove VID from RESET

Device failed

No

Last sector

verified?

Write reset command

Yes

Chip Unprotect

Algorithm

Sector Protect complete

Remove VID from RESET

Write reset command

Sector Unprotect complete

P/N:PM0920

REV. 1.2, NOV. 05, 2003

49

MX29LV640T/B

AC CHARACTERISTICS

Parameter

tVLHT

Description

Test Setup

Min.

All Speed Options Unit

Voltage transition time

4

100

4

us

ns

us

tWPP1

Write pulse width for sector group protect

OE setup time to WE active

Min.

tOESP

Min.

Fig 14. SECTOR GROUP PROTECT TIMING WAVEFORM (A9, OE Control)

A1

A6

12V

3V

A9

tVLHT

Verify

12V

3V

OE

tVLHT

tWPP 1

WE

tOESP

CE

Data

01H

F0H

tOE

Sector Address

A21-A16

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REV. 1.2, NOV. 05, 2003

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MX29LV640T/B

Fig 15. SECTOR GROUP PROTECTION ALGORITHM (A9, OE Control)

START

Set Up Sector Addr

PLSCNT=1

OE=VID,A9=VID,CE=VIL

A6=VIL

Activate WE Pulse

Time Out 150us

Set WE=VIH, CE=OE=VIL

A9 should remain VID

.

Read from Sector

Addr=SA, A1=1

No

Data=01H?

PLSCNT=32?

Yes

Device Failed

Yes

Protect Another

Sector?

Remove VID from A9

Write Reset Command

Sector Protection

Complete

P/N:PM0920

REV. 1.2, NOV. 05, 2003

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MX29LV640T/B

Fig 16. CHIP UNPROTECT TIMING WAVEFORM (A9, OE Control)

A1

12V

3V

A9

A6

tVLHT

Verify

12V

3V

OE

tVLHT

tWPP 2

WE

CE

tOESP

Data

00H

F0H

tOE

P/N:PM0920

REV. 1.2, NOV. 05, 2003

52

MX29LV640T/B

Fig 17. CHIP UNPROTECT FLOWCHART (A9, OE Control)

START

Protect All Sectors

PLSCNT=1

Set OE=A9=VID

CE=VIL,A6=1

Activate WE Pulse

Time Out 15ms

Increment

PLSCNT

Set OE=CE=VIL

A9=VID,A1=1

Set Up First Sector Addr

Read Data from Device

No

Data=00H?

Increment

PLSCNT=1000?

Sector Addr

Yes

Device Failed

No

All sectors have

been verified?

Yes

Remove VID from A9

Write Reset Command

Chip Unprotect

Complete

* It is recommended before unprotect whole chip, all sectors should be protected in advance.

P/N:PM0920

REV. 1.2, NOV. 05, 2003

53

MX29LV640T/B

AC CHARACTERISTICS

Parameter Description

Test

Setup

Min

All Speed Options Unit

tVIDR

tRSP

tRRB

VID Rise and Fall Time (see Note)

500

4

ns

us

RESET SetupTime forTemporary Sector Unprotect

RESET Hold Time from RY/BY High forTemporary

Sector Group Unprotect

Min

4

Fig 18. TEMPORARY SECTOR GROUP UNPROTECT WAVEFORMS

12V

RESET

0 or 3V

VIL or VIH

tVIDR

Program or Erase Command Sequence

CE

WE

tRSP

tRRB

RY/BY

P/N:PM0920

REV. 1.2, NOV. 05, 2003

54

MX29LV640T/B

Fig 19. TEMPORARY SECTOR GROUP UNPROTECT FLOWCHART

Start

RESET = VID (Note 1)

Perform Erase or Program Operation

Operation Completed

RESET = VIH

Temporary Sector Unprotect Completed(Note 2)

Note :

1. All protected sectors are temporary unprotected.

VID=11.5V~12.5V

2. All previously protected sectors are protected again.

P/N:PM0920

REV. 1.2, NOV. 05, 2003

55

MX29LV640T/B

Fig 20. SILICON ID READ TIMING WAVEFORM

VCC

3V

VID

ADD

A9

VIH

VIL

VIH

VIL

ADD

A0

tACC

VIH

VIL

A1

VIH

VIL

ADD

CE

VIH

VIL

VIH

VIL

tCE

WE

OE

tOE

VIH

VIL

tDF

tOH

VIH

VIL

DATA

Q0-Q15

DATA OUT

00C2H

DATA OUT

22C9H for Top

22CBH for Bottom

P/N:PM0920

REV. 1.2, NOV. 05, 2003

56

MX29LV640T/B

WRITE OPERATION STATUS

Fig 21. DATA POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)

tRC

VA

Address

CE

tACC

tCE

tCH

tOE

OE

tOEH

tDF

WE

tOH

High Z

Complement

Status Data

True

Valid Data

Q7

Q0-Q6

True

tBUSY

RY/BY

NOTES:

VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data raed cycle.

P/N:PM0920

REV. 1.2, NOV. 05, 2003

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MX29LV640T/B

Fig 22. DATA POLLING ALGORITHM

Start

Read Q7~Q0

Add.=VA(1)

Yes

Q7 = Data ?

No

Q5 = 1 ?

Yes

Read Q7~Q0

Add.=VA

Yes

Q7 = Data ?

(2)

No

FAIL

Pass

Notes:

1.VA=valid address for programming.

2.Q7 should be rechecked even Q5="1" because Q7 may change simultaneously with Q5.

P/N:PM0920

REV. 1.2, NOV. 05, 2003

58

MX29LV640T/B

Fig 23. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)

tRC

VA

Address

CE

tACC

tCE

tCH

tOE

OE

tOEH

tDF

WE

tOH

tDH

Valid Status

(second read)

Valid Status

(first read)

Valid Data

Q6/Q2

Valid Status

(stops toggling)

RY/BY

NOTES:

VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle, and

array data read cycle.

P/N:PM0920

REV. 1.2, NOV. 05, 2003

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MX29LV640T/B

Fig 24. TOGGLE BIT ALGORITHM

START

Read Q7~Q0

(Note 1)

NO

Toggle Bit Q6

=Toggle?

YES

NO

Q5=1?

YES

(Note 1,2)

Read Q7~Q0 Twice

Toggle Bit Q6=

Toggle?

YES

Program/Erase Operation Not

Program/Erase Operation Complete

Complete, Write Reset Command

Note:

1. Read toggle bit twice to determine whether or not it is toggling.

2. Recheck toggle bit because it may stop toggling as Q5 changes to "1".

P/N:PM0920

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MX29LV640T/B

Fig 25. Q6 versus Q2

Enter Embedded

Erasing

Erase

Enter Erase

Erase

Suspend

Suspend Program

Resume

Erase

Erase Suspend

Read

Erase

Erase Suspend

Read

Erase

WE

Q6

Suspend

Program

Complete

Q2

NOTES:

The system can use OE or CE to toggle Q2/Q6, Q2 toggles only when read at an address within an erase-suspended

P/N:PM0920

REV. 1.2, NOV. 05, 2003

61

MX29LV640T/B

ERASE AND PROGRAMMING PERFORMANCE (1)

LIMITS

PARAMETER

MIN.

TYP.(2)

0.9

45

MAX.

15

UNITS

sec

Sector Erase Time

Chip Erase Time

65

sec

Byte Programming Time

Word Programming Time

Chip Programming Time

9

300

360

160

140

us

11

us

Byte Mode

Word Mode

50

sec

45

sec

Erase/Program Cycles

100,000

Cycles

Note: 1. Not 100% Tested, Excludes external system level over head.

2.Typical program and erase times assume the following condition= 25°C,3.0V VCC.

Additionally, programming typicals assume checkerboard pattern.

LATCH-UP CHARACTERISTICS

MIN.

MAX.

Input Voltage with respect to GND on all pins except I/O pins

Input Voltage with respect to GND on all I/O pins

Current

-1.0V

13.5V

Vcc + 1.0V

+100mA

-100mA

Includes all pins except Vcc. Test conditions: Vcc = 3.0V, one pin at a time.

TSOP PIN CAPACITANCE

Parameter Symbol

Parameter Description

Input Capacitance

Test Set

VIN=0

TYP

MAX

7.5

12

UNIT

pF

CIN

6

COUT

CIN2

Output Capacitance

Control Pin Capacitance

VOUT=0

VIN=0

8.5

7.5

pF

9

pF

Notes:

1. Sampled, not 100% tested.

2.Test conditions TA=25°C, f=1.0MHz

DATA RETENTION

Parameter

Test Conditions

Min

10

Unit

Minimum Pattern Data Retention Time

150

125

Years

20

P/N:PM0920

REV. 1.2, NOV. 05, 2003

62

MX29LV640T/B

ORDERING INFORMATION

PLASTIC PACKAGE

PART NO.

ACCESS TIME

Ball Pitch/

Ball size

PACKAGE

Remark

(ns)

MX29LV640TTC-90

MX29LV640TTC-12

MX29LV640BTC-90

MX29LV640BTC-12

MX29LV640TTI-90

MX29LV640TTI-12

MX29LV640BTI-90

MX29LV640BTI-12

90

48 Pin TSOP

(Normal Type)

48 Pin TSOP

(Normal Type)

48 Pin TSOP

(Normal Type)

48 Pin TSOP

(Normal Type)

48 Pin TSOP

(Normal Type)

48 Pin TSOP

(Normal Type)

48 Pin TSOP

(Normal Type)

48 Pin TSOP

(Normal Type)

63 Ball CSP

64 Ball CSP

120

90

120

90

120

90

120

MX29LV640TXBC-90

MX29LV640TXBC-12

MX29LV640BXBC-90

MX29LV640BXBC-12

MX29LV640TXBI-90

MX29LV640TXBI-12

MX29LV640BXBI-90

MX29LV640BXBI-12

MX29LV640TXEC-90

MX29LV640TXEC-12

MX29LV640BXEC-90

MX29LV640BXEC-12

MX29LV640TXEI-90

MX29LV640TXEI-12

MX29LV640BXEI-90

MX29LV640BXEI-12

MX29LV640TXCC-90

MX29LV640TXCC-12

MX29LV640BXCC-90

MX29LV640BXCC-12

MX29LV640TXCI-90

MX29LV640TXCI-12

MX29LV640BXCI-90

MX29LV640BXCI-12

90

120

90

0.8mm/0.3mm

0.8mm/0.4mm

1mm/0.4mm

120

90

120

90

120

90

120

90

120

90

120

90

120

90

120

90

1mm/0.4mm

120

90

1mm/0.4mm

120

90

1mm/0.4mm

120

1mm/0.4mm

P/N:PM0920

REV. 1.2, NOV. 05, 2003

63

MX29LV640T/B

PART NO.

ACCESS TIME

Ball Pitch/

Ball size

PACKAGE

Remark

PB-free

(ns)

MX29LV640TTC-90G

MX29LV640TTC-12G

MX29LV640BTC-90G

MX29LV640BTC-12G

MX29LV640TTI-90G

MX29LV640TTI-12G

MX29LV640BTI-90G

MX29LV640BTI-12G

90

48 Pin TSOP

(Normal Type)

48 Pin TSOP

(Normal Type)

48 Pin TSOP

(Normal Type)

48 Pin TSOP

(Normal Type)

48 Pin TSOP

(Normal Type)

48 Pin TSOP

(Normal Type)

48 Pin TSOP

(Normal Type)

48 Pin TSOP

(Normal Type)

120

90

120

90

120

90

120

P/N:PM0920

REV. 1.2, NOV. 05, 2003

64

MX29LV640T/B

PACKAGE INFORMATION

P/N:PM0920

REV. 1.2, NOV. 05, 2003

65

MX29LV640T/B

P/N:PM0920

REV. 1.2, NOV. 05, 2003

66

MX29LV640T/B

P/N:PM0920

REV. 1.2, NOV. 05, 2003

67

MX29LV640T/B

P/N:PM0920

REV. 1.2, NOV. 05, 2003

68

MX29LV640T/B

REVISION HISTORY

Revision No. Description

Page

P33

P63,66

P27

P64

P1

Date

JUL/22/2003

1.0

1.1

1.2

1. To modified the max. ICC current from 5uA to 15uA

2. To added 63CSP with 0.4mm ball size package information

1. To corrected CFI code in table 4-3 device geometry data values

2. To added pb-free part no. for 48-TSOP package

1. Removed "Preliminary" from title

OCT/28/2003

NOV/05/2003

P/N:PM0920

REV. 1.2, NOV. 05, 2003

69

MX29LV640T/B

MACRONIX INTERNATIONAL CO., LTD.

HEADQUARTERS:

TEL:+886-3-578-6688

FAX:+886-3-563-2888

EUROPE OFFICE:

TEL:+32-2-456-8020

FAX:+32-2-456-8021

JAPAN OFFICE:

TEL:+81-44-246-9100

FAX:+81-44-246-9105

SINGAPORE OFFICE:

TEL:+65-348-8385

FAX:+65-348-8096

TAIPEI OFFICE:

TEL:+886-2-2509-3300

FAX:+886-2-2509-2200

MACRONIX AMERICA, INC.

TEL:+1-408-453-8088

FAX:+1-408-453-8488

CHICAGO OFFICE:

TEL:+1-847-963-1900

FAX:+1-847-963-1909

http : //www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.


型号：	MX29LV640TTI-90
厂家：	MACRONIX INTERNATIONAL
描述：	64M-BIT [8M x 8/4M x 16] SINGLE VOLTAGE 3V ONLY FLASH MEMORY 64M - BIT [ 8M ×8 / 4M ×16 ]单电压3V仅限于Flash存储器闪存存储内存集成电路光电二极管
文件：	总70页 (文件大小：1166K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MX29LV640TTI-90 [Macronix]

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