MX29NS320E [Macronix]
128/64/32M-BIT [8/4/2M x16-bit] CMOS 1.8 Volt-only,;
| 型号： | MX29NS320E |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | 128/64/32M-BIT [8/4/2M x16-bit] CMOS 1.8 Volt-only, |
| 文件： | 总70页 (文件大小：707K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Datasheet
MULTIPLEXED, Burst Mode, Flash Memory
MX29NS320E/640E/128E
P/N: PM1516
REV. 1.1, APR. 26, 2011
MULTIPLEXED, Burst Mode, Flash Memory
Contents
1. FEATURES........................................................................................................................................6
2. GENERAL INFORMATION ..............................................................................................................8
2-1. Operating Speeds..................................................................................................................8
2-2. Ordering Information.............................................................................................................8
2-3. Part Name Description..........................................................................................................9
3. PIN CONFIGURATION / SYMBOL DESCRIPTION........................................................................10
3-1. Logic Symbol.......................................................................................................................10
3-2. Pin Descriptions..................................................................................................................11
4. BLOCK DIAGRAM..........................................................................................................................12
4-1. Block Structure....................................................................................................................13
Table 1-1. Sector Address Table (MX29NS320E) ................................................................................13
Table 1-2. Sector Address Table (MX29NS640E) ................................................................................14
Table 1-3. Sector Address Table (MX29NS128E) ................................................................................16
5. BUS OPERATIONS.........................................................................................................................17
Table 2. Bus Operations.......................................................................................................................17
5-1. Non-Burst (Asynchronous) Read Operation.....................................................................18
5-2. Burst (Synchronous) Read Operation ..............................................................................18
5-2-1. Continuous Burst Read..............................................................................................................18
Table 3-1. Address Latency for 10, 9 and 8 Dummy Cycles ................................................................19
Table 3-2. Address Latency for 7, 6, and 5 Dummy Cycles .................................................................19
Table 3-3. Address Latency for 4 Dummy Cycles ................................................................................19
Table 3-4. Address Latency for 3 Dummy Cycles ................................................................................19
Table 3-5. Address/8-word Boundary Crossing Latency for 10, 9 and 8 Dummy Cycles.....................19
Table 3-6. Address/128-word Boundary Crossing Latency for 7, 6, and 5 Dummy Cycles..................20
Table 3-7. Address/128-word Boundary Crossing Latency for 4 Dummy Cycles.................................20
Table 3-8. Address/128-word Boundary Crossing Latency for 3 Dummy Cycles.................................20
5-2-2. 8-, 16-Word Modes Linear Burst with Wrap Around ..................................................................20
Table 4. Burst Address Groups ............................................................................................................20
5-2-3. Reading Memory Array..............................................................................................................21
5-3. Set Configuration Register Command Sequence ............................................................21
5-3-1. Programmable Dummy Cycle....................................................................................................22
5-3-2. Configurable Dummy Cycle.......................................................................................................22
5-3-3. Burst Length Configuration........................................................................................................22
Table 5. Configurable Dummy Cycles vs. Frequency ..........................................................................23
5-3-4. Burst Wrap Around ....................................................................................................................23
5-3-5. Output Drive Strength................................................................................................................23
REV. 1.1, APR. 26, 2011
P/N: PM1585
2
MX29NS320/640/128E
5-4. Program Operation..............................................................................................................24
5-4-1. Programming Commands/Command Sequences .....................................................................25
5-4-2. Accelerated Program and Erase Operations .............................................................................25
5-4-3. Write Buffer Programming Operation.........................................................................................25
5-4-4. Write Buffer Programming Command Sequence.......................................................................26
5-4-5. Buffer Write Abort.......................................................................................................................26
Table 6. Write Buffer Command Sequence..........................................................................................26
Figure 1. Write Buffer Programming Operation....................................................................................27
Figure 2. Status Polling For Write Buffer Program...............................................................................28
5-5. Erase Operation ..................................................................................................................29
5-5-1. Sector Erase .............................................................................................................................29
5-5-2. Chip Erase ................................................................................................................................29
5-5-3. Sector Erase Command Sequence ...........................................................................................30
5-5-4. Accelerated Sector Erase ..........................................................................................................30
Figure 3. Erase Operation....................................................................................................................31
5-6. Program/Erase Operation Status ......................................................................................32
Table 7. Program Operation Status......................................................................................................32
5-7. Program/Erase Suspend/Resume......................................................................................33
5-7-1. Program Suspend......................................................................................................................33
5-7-2. Program Resume.......................................................................................................................33
5-7-3. Program Suspend/Program Resume Commands .....................................................................33
5-7-4. Erase Suspend ..........................................................................................................................34
5-7-5. Sector Erase Resume................................................................................................................34
Figure 4. Data# Polling Timing Waveforms (During Embedded Algorithms)........................................35
Figure 5. Data# Polling For Word Program/Erase ...............................................................................36
Figure 6. Toggle Bit Timing Waveforms (During Embedded Algorithms) .............................................36
Figure 7. Toggle Bit Algorithm ..............................................................................................................37
5-8. Configuration Register .......................................................................................................38
Table 8. Configuration Register............................................................................................................38
5-9. Enter/Exit Secured Silicon Sector Command Sequence.................................................39
5-9-1. Program Secured Silicon Sector Command Sequence.............................................................39
5-10. Auto Select Operations.......................................................................................................40
5-10-1. Auto Select Command Sequence............................................................................................40
5-11. Handshaking Feature..........................................................................................................41
Table 9. Dummy Cycles for Handshaking ............................................................................................41
P/N: PM1585
REV. 1.1, APR. 26, 2011
3
MULTIPLEXED, Burst Mode, Flash Memory
6. SECURITY FEATURES ..................................................................................................................42
6-1. Lock Register ...................................................................................................................42
6-1-1. Lock Register Bits .....................................................................................................................42
Table 10. Lock Register bits.................................................................................................................42
Figure 8. Lock Register Program Algorithm .........................................................................................43
6-1-2. Dynamic Write Protection Bits (DPBS)......................................................................................44
6-2. Hardware Data Protection Mode .......................................................................................44
6-2-1. Write Protect (WP#)...................................................................................................................44
6-2-2. WP# Boot Sector Protection......................................................................................................44
6-3. Security Sector Flash Memory Region ...........................................................................45
6-3-1. Factory Locked: Security Sector Programmed and Protected at the Factory............................45
6-3-2. Customer Lockable: Security Sector NOT Programmed or Protected at the Factory ...............45
7. COMMAND DEFINITIONS .............................................................................................................46
8. ENERGY SAVING MODE ..............................................................................................................48
8-1. Standby Mode......................................................................................................................48
8-2. Automatic Sleep Mode........................................................................................................48
Table 11. DC Characteristics................................................................................................................49
8-3. Reset Commands................................................................................................................50
8-3-1. Hardware Reset.........................................................................................................................50
Table 12. Hardware Reset....................................................................................................................50
Figure 9. Reset Timings .......................................................................................................................51
8-3-2. Software Reset ..........................................................................................................................51
9. COMMON FLASH MEMORY INTERFACE (CFI) MODE ...............................................................52
Table 13-1. CFI Mode: Identification Data Values................................................................................52
Table 13-2. CFI Mode: System Interface Data Values .........................................................................52
Table 13-3. CFI Mode: Device Geometry Data Values ........................................................................53
Table 13-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values...................................54
10. ELECTRICAL CHARACTERISTICS...............................................................................................55
10-1. Absolute Maximum Stress Ratings ...................................................................................55
10-2. Operating Temperatures and Voltages..............................................................................55
10-3. Test Conditions....................................................................................................................56
Figure 10. Test Setup...........................................................................................................................56
Figure 11. Input Waveforms and Measurement Levels........................................................................56
REV. 1.1, APR. 26, 2011
P/N: PM1585
4
MX29NS320/640/128E
10-4. AC Characteristics ..............................................................................................................57
Figure 12. VCC Power-up Diagram CLK Characterization ..................................................................57
Figure 13. Deep Power Down Mode Waveform ..................................................................................58
Figure 14. CLK Characterization..........................................................................................................58
Table 15. Synchronous / Burst Read....................................................................................................59
Figure 15. Burst Mode Read................................................................................................................59
Table 16. Asynchronous Read .............................................................................................................60
Figure 16. Asynchronous Mode Read..................................................................................................60
Table 17. Erase/Program Operations...................................................................................................61
Figure 17. Program Operation Timings................................................................................................62
Figure 18. Chip/Sector Erase Operations ............................................................................................63
Figure 19. Data# Polling Timings (During Embedded Algorithm).........................................................64
Figure 20. Toggle Bit Timings (During Embedded Algorithm) ..............................................................64
Figure 21. 8-, 16-Word Linear Burst Address Wrap Around.................................................................65
Figure 22. Latency with Boundary Crossing ........................................................................................65
10-5. Erase and Programming Performance..............................................................................66
10-5-1. BGA Ball Capacitance .............................................................................................................67
10-6. Low VCC Write Prohibit ......................................................................................................67
10-6-1. Write Pulse "Glitch" Protection ................................................................................................67
10-6-2. Logical Prohibit ........................................................................................................................67
10-6-3. Power-up Sequence ................................................................................................................67
10-6-4. Power-up Write Prohibit...........................................................................................................67
10-6-5. Power Supply Decoupling........................................................................................................67
11. PACKAGE INFORMATION.............................................................................................................68
12. REVISION HISTORY ......................................................................................................................69
P/N: PM1585
REV. 1.1, APR. 26, 2011
5
MULTIPLEXED, Burst Mode, Flash Memory
128/64/32M-BIT [8/4/2M x16-bit] CMOS 1.8 Volt-only,
Multiplexed Flash Memory
1. FEATURES
Characteristics
Burst Length
VI/O Feature
• Continuous linear burst
• Generates data output voltages
and tolerates data input voltages as
determined by the voltage on the VI/O pin
• 8/16 word linear burst length with wrap
around
• 1.8V compatible I/O signals
Sector Architecture
Read Access Time
• Single bank Architecture.
• Burst access times: 7 ns (at industrial
temperature range)
• Four 8 Kword sectors in upper-most
address range (MX29NS320E/640E)
• 80 ns of Asynchronous random access
times
• Four 16Kword sectors in upper-most
address range (MX29NS128E)
• 80 ns of Synchronous random access times
• MX29NS320E: Sixty-three 32 KWord
• MX29NS640E: One hundred twenty-
seven 32 Kword sectors
Secured Silicon Sector Region
• 256 words accessible through a command
sequence
• MX29NS128E: One hundred twenty
seven 64 Kword sectors
• 128 words for the factory secured silicon
sector
Power Supply Operations
• 128 words for the customer secured
silicon sector
• 1.8V for read, program and erase
operations (1.70V to 1.95V)
• Deep power down mode
Power Dissipation
• Typical values: 8 bits switching,
CL = 10 pF at 108 MHz, CIN excluded
• 32 mA for Continuous burst read mode
• 20 mA for Program/Erase Operations
• 40 uA for Standby mode
Performance
High Performance
• 40 μs - Word programming time
• 9.4 μs - Effective word programming time
utilizing a 32 word Write Buffer at VCC
level
Program/Erase Cycles
• 4.8 μs - Effective word programming time
of utilizing a 32 word Write Buffer at ACC
level
• 100,000 cycles typical
Data Retention
Sector Erase Time
• 20 years
• 600 ms for 32 Kword sectors
• 800 ms for 64 Kword sectors
REV. 1.1, APR. 26, 2011
P/N: PM1585
6
MX29NS320/640/128E
Software Features
Hardware Features
• Supports multiplexing data and address
for reduced I/O count.
Advanced Security Features
• Volatile Sector Protection
• A15–A0 multiplexed as Q15–Q0 Sector
Architecture
• A command sector protection method
that protects individual sectors from being
programmed or erased.
Hardware Sector Protection
• Sectors can be locked or unlocked in-
system at VCC level.
- WP# protects two highest sectors
-
All sectors locked when ACC = VIL
Package
• 56-Ball Thin FBGA (Fine-Pitch Ball Grid
Array)
• REACH SVHC Free and RoHS Compliant
Handshaking Feature
• Allows system to determine the read
operation of burst data with minimum
possible latency by monitoring RDY.
Data# Polling and Toggle Bits
• Provides a software method of detecting
and sending signals to indicate the
completion of program and erase
operations.
Erase Suspend/Erase Resume
• Erase operation will be halted when
the device receives an Erase Suspend
command. And will be restarted when
the device receives the Erase Resume
command.
Program Suspend/Program Resume
• Program operation will be halted when
the device receives a Program Suspend
command. It will be restarted when the
device receives the Program Resume
command.
Electronic Identification
• Software command set compatible with
JEDEC 42.4 standards
• Common Flash Interface (CFI) supported
P/N: PM1585
REV. 1.1, APR. 26, 2011
7
MULTIPLEXED, Burst Mode, Flash Memory
2. GENERAL INFORMATION
2-1. Operating Speeds
Output
Loading
Burst Access
Synch. Initial
Access (ns)
Asynch. Initial
Access (ns)
Clock Speed
(ns)
108 MHz
7
80
80
10 pF
The operating temperature range is -40°C to +85°C.
2-2. Ordering Information
Part Number
Access Time (ns)
Package
Remark
MX29NS320E XJI-80G
MX29NS640E XJI-80G
MX29NS128EXJI-80G
80
56 TFBGA
VI/O=VCC
NOTES:
1.
MX29NS320/640/128E have been pre-released and in mass production.
MX29NS128E is for the validation of MCP products. Please contact Macronix
2.
.
local sales for discrete product support
REV. 1.1, APR. 26, 2011
P/N: PM1585
8
MX29NS320/640/128E
2-3. Part Name Description
MX 29 NS 640 E XJ I - 80 G
G: RoHS Compliant
Speed:
80: 80ns
Temperature Range:
I: Indsustrial
-40°C ~ +85°C
Package:
XJ: TFBGA
Revision: E
Density & Mode:
128: 128Mb;
640: 64Mb
320: 32Mb
NS: 1.8V Burst Mode
Device:
29: Flash
Brand:
MX
P/N: PM1585
REV. 1.1, APR. 26, 2011
9
MULTIPLEXED, Burst Mode, Flash Memory
3. PIN CONFIGURATION / SYMBOL DESCRIPTION
56-Ball Thin FBGA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
B
C
D
E
F
A1
A14
NC
NC
C7
NC
C12
NC
C4
NC
C8
NC
C3
NC
C11
NC
D3
D4
D5
D6
D7
D8
D9
D10
A19
D11
A17
D12
A22
VSS
CLK
VCC
WE#
ACC
RDY
A21
E3
E4
E5
E6
E7
NC
E8
E9
E10
A18
E11
CE#
E12
VSSQ
A20
AVD#
RESET#
WP#
VI/O
A16
F3
F4
F5
F6
F7
F8
F9
F10
F11
A/Q8
F12
OE#
VSS
A/Q7
A/Q6
A/Q13
A/Q12
A/Q3
A/Q2
A/Q9
G3
G4
G5
G6
G7
G8
G9
G10
VI/O
G11
A/Q1
G12
A/Q0
G
H
J
A/Q15
A/Q14
VSSQ
A/Q5
A/Q4
A/Q11
A/Q10
H3
NC
H4
NC
H7
NC
H8
NC
H11
NC
H12
NC
K14
NC
K1
NC
K
NOTE: A22 is for MX29NS128E;
A21 is for MX29NS640E.
16 I/O
A16-Amax
CLK
A/Q0-15
3-1. Logic Symbol
CE#
OE#
WE#
RESET#
WP
RDY
AVD#
VI/O
ACC
VSSQ
REV. 1.1, APR. 26, 2011
P/N: PM1585
10
MX29NS320/640/128E
3-2. Pin Descriptions
SYMBOL
DESCRIPTIONS
A22-A16
A21-A16
A20-A16
A/Q15~
Address Inputs for MX29NS128E
Address Inputs for MX29NS640E
Address Inputs for MX29NS320E
Multiplexed Data Inputs/Outputs
A/Q0
CE#
OE#
WE#
VCC
VI/O
VSS
VSSQ
NC
Chip Enable Input
Output Enable Input
Write Enable Input
Device Power Supply (1.70V~1.95V)
Input/Output Power Supply (1.70V~1.95V)
Device Ground
Input/Output Ground
No Connection
RDY
Ready output, the status of the Burst Read
Refer to configuration register table
The first rising edge of CLK in conjunction with AVD# low latches address input
and activates burst mode operation.
CLK
Address Valid input. Indicates to device that the valid address is present on the
address inputs (Address bits A15–A0 are multiplexed, address bits Amax–A16
are address only).
AVD#
VIL= For asynchronous mode, indicates valid address; for burst mode, causes
starting address to be latched on rising edge of CLK.
VIH = Device ignores address inputs
Hardware Reset Pin, Active Low
Hardware Write Protect
RESET#
WP#
ACC
Programming Acceleration Input
NOTES:
1. WP# and ACC have internal pull up. WP# VIL protects the upper most two sectors from
write; ACC=Vhv enters into the ACC programming mode. ACC=VIL, erase/program function
disabled.
2. VI/O Voltage must tight up with VCC.
VI/O = VCC = 1.70V~1.95V
P/N: PM1585
REV. 1.1, APR. 26, 2011
11
MULTIPLEXED, Burst Mode, Flash Memory
4. BLOCK DIAGRAM
CE#
WRITE
STATE
OE#
CONTROL
PROGRAM/ERASE
HIGH VOLTAGE
WE#
INPUT
RESET#
ACC
MACHINE
(WSM)
LOGIC
WP#
CLK
AVD#
STATE
FLASH
ARRAY
ADDRESS
LATCH
REGISTER
ARRAY
AM-A16
AND
SOURCE
HV
BUFFER
Y-PASS GATE
COMMAND
DATA
DECODER
PGM
SENSE
DATA
HV
AMPLIFIER
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
AQ[15:0]
I/O BUFFER
RDY
AM: MSB address
REV. 1.1, APR. 26, 2011
P/N: PM1585
12
MX29NS320/640/128E
4-1. Block Structure
The main flash memory array is organized as Word mode (x16). The details of the address ranges
and the corresponding sector addresses are shown in Table 1.
Table 1-1. Sector Address Table (MX29NS320E)
Sector Size
Kwords
32
Sector Size
Kwords
32
Sector
Address Range
Sector
Address Range
SA0
SA1
SA2
000000h-007FFFh
008000h-00FFFFh
010000h-017FFFh
SA41
SA42
SA43
148000h-14FFFFh
150000h-157FFFh
158000h-15FFFFh
32
32
32
32
018000h-01FFFFh
020000h-027FFFh
028000h-02FFFFh
030000h-037FFFh
038000h-03FFFFh
040000h-047FFFh
048000h-04FFFFh
050000h-057FFFh
058000h-05FFFFh
060000h-067FFFh
068000h-06FFFFh
070000h-077FFFh
078000h-07FFFFh
080000h-087FFFh
088000h-08FFFFh
090000h-097FFFh
098000h-09FFFFh
0A0000h-0A7FFFh
0A8000h-0AFFFFh
0B0000h-0B7FFFh
0B8000h-0BFFFFh
0C0000h-0C7FFFh
0C8000h-0CFFFFh
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
160000h-167FFFh
168000h-16FFFFh
170000h-177FFFh
178000h-17FFFFh
180000h-187FFFh
188000h-18FFFFh
190000h-197FFFh
198000h-19FFFFh
1A0000h-1A7FFFh
1A8000h-1AFFFFh
1B0000h-1B7FFFh
1B8000h-1BFFFFh
1C0000h-1C7FFFh
1C8000h-1CFFFFh
1D0000h-1D7FFFh
1D8000h-1DFFFFh
1E0000h-1E7FFFh
1E8000h-1EFFFFh
1F0000h-1F7FFFh
1F8000h-1F9FFFh
1FA000h-1FBFFFh
1FC000h-1FDFFFh
1FE000h-1FFFFFh
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
SA3
SA4
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
8
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
8
8
32
32
32
32
32
32
32
32
32
32
32
32
32
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
8
0D0000h-0D7FFFh
0D8000h-0DFFFFh
0E0000h-0E7FFFh
0E8000h-0EFFFFh
0F0000h-0F7FFFh
0F8000h-0FFFFFh
100000h-107FFFh
108000h-10FFFFh
110000h-117FFFh
118000h-11FFFFh
120000h-127FFFh
128000h-12FFFFh
130000h-137FFFh
32
32
32
SA38
SA39
SA40
138000h-13FFFFh
140000h-147FFFh
P/N: PM1585
REV. 1.1, APR. 26, 2011
13
MULTIPLEXED, Burst Mode, Flash Memory
Table 1-2. Sector Address Table (MX29NS640E)
Sector Size
Sector Size
Kwords
32
Sector
Address Range
Sector
Address Range
Kwords
32
SA47
SA48
SA49
178000h-17FFFFh
180000h-187FFFh
188000h-18FFFFh
SA0
SA1
SA2
SA3
000000h-007FFFh
008000h-00FFFFh
010000h-017FFFh
018000h-01FFFFh
32
32
32
32
32
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
190000h-197FFFh
198000h-19FFFFh
1A0000h-1A7FFFh
1A8000h-1AFFFFh
1B0000h-1B7FFFh
1B8000h-1BFFFFh
1C0000h-1C7FFFh
1C8000h-1CFFFFh
1D0000h-1D7FFFh
1D8000h-1DFFFFh
1E0000h-1E7FFFh
1E8000h-1EFFFFh
1F0000h-1F7FFFh
1F8000h-1FFFFFh
200000h-207FFFh
208000h-20FFFFh
210000h-217FFFh
218000h-21FFFFh
220000h-227FFFh
228000h-22FFFFh
230000h-237FFFh
238000h-23FFFFh
240000h-247FFFh
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
020000h-027FFFh
028000h-02FFFFh
030000h-037FFFh
038000h-03FFFFh
040000h-047FFFh
048000h-04FFFFh
050000h-057FFFh
058000h-05FFFFh
060000h-067FFFh
068000h-06FFFFh
070000h-077FFFh
078000h-07FFFFh
080000h-087FFFh
088000h-08FFFFh
090000h-097FFFh
098000h-09FFFFh
0A0000h-0A7FFFh
0A8000h-0AFFFFh
0B0000h-0B7FFFh
0B8000h-0BFFFFh
0C0000h-0C7FFFh
0C8000h-0CFFFFh
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
32
32
32
32
32
32
32
32
32
32
32
32
32
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
32
32
32
32
32
32
32
32
32
32
32
32
32
0D0000h-0D7FFFh
0D8000h-0DFFFFh
0E0000h-0E7FFFh
0E8000h-0EFFFFh
0F0000h-0F7FFFh
0F8000h-0FFFFFh
100000h-107FFFh
108000h-10FFFFh
110000h-117FFFh
118000h-11FFFFh
120000h-127FFFh
128000h-12FFFFh
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
248000h-24FFFFh
250000h-257FFFh
258000h-25FFFFh
260000h-267FFFh
268000h-26FFFFh
270000h-277FFFh
278000h-2F7FFFh
280000h-287FFFh
288000h-28FFFFh
290000h-297FFFh
298000h-29FFFFh
2A0000h-2A7FFFh
130000h-137FFFh
138000h-13FFFFh
140000h-147FFFh
32
32
32
SA38
SA39
SA40
SA85
SA86
SA87
SA88
SA89
2A8000h-2AFFFFh
2B0000h-2B7FFFh
2B8000h-2BFFFFh
2C0000h-2C7FFFh
2C8000h-2CFFFFh
32
32
32
148000h-14FFFFh
150000h-157FFFh
158000h-15FFFFh
160000h-167FFFh
168000h-16FFFFh
32
SA41
32
32
32
32
32
SA42
SA43
SA44
SA45
32
32
32
32
SA90
SA91
SA92
2D0000h-2D7FFFh
2D8000h-2DFFFFh
2E0000h-2E7FFFh
REV. 1.1, APR. 26, 2011
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MX29NS320/640/128E
Sector Size
Kwords
32
Sector
Address Range
SA93
SA94
SA95
2E8000h-2EFFFFh
2F0000h-2F7FFFh
2F8000h-2FFFFFh
32
32
SA96
SA97
300000h-307FFFh
308000h-30FFFFh
310000h-317FFFh
318000h-31FFFFh
320000h-327FFFh
328000h-32FFFFh
330000h-337FFFh
338000h-33FFFFh
340000h-347FFFh
348000h-34FFFFh
350000h-357FFFh
358000h-35FFFFh
360000h-367FFFh
368000h-36FFFFh
370000h-377FFFh
378000h-37FFFFh
380000h-387FFFh
388000h-38FFFFh
390000h-397FFFh
398000h-39FFFFh
3A0000h-3A7FFFh
3A8000h-3AFFFFh
3B0000h-3B7FFFh
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
32
32
32
32
32
32
32
32
32
8
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA128
SA129
SA130
3B8000h-3BFFFFh
3C0000h-3C7FFFh
3C8000h-3CFFFFh
3D0000h-3D7FFFh
3D8000h-3DFFFFh
3E0000h-3E7FFFh
3E8000h-3EFFFFh
3F0000h-3F7FFFh
3F8000h-3F9FFFh
3FA000h-3FBFFFh
3FC000h-3FDFFFh
3FE000h-3FFFFFh
8
8
8
P/N: PM1585
REV. 1.1, APR. 26, 2011
15
MULTIPLEXED, Burst Mode, Flash Memory
Table 1-3. Sector Address Table (MX29NS128E)
Sector Size
Kwords
64
Sector Size
Kwords
64
Sector Size
Kwords
64
Sector
Address Range
Sector
Address Range
Sector
Address Range
2A0000h-2AFFFFh
2B0000h-2BFFFFh
2C0000h-2CFFFFh
2D0000h-2DFFFFh
2E0000h-2EFFFFh
2F0000h-2FFFFFh
300000h-30FFFFh
310000h-31FFFFh
320000h-32FFFFh
330000h-33FFFFh
340000h-34FFFFh
350000h-35FFFFh
360000h-36FFFFh
370000h-37FFFFh
380000h-38FFFFh
390000h-39FFFFh
3A0000h-3AFFFFh
3B0000h-3BFFFFh
3C0000h-3CFFFFh
3D0000h-3DFFFFh
3E0000h-3EFFFFh
3F0000h-3FFFFFh
400000h-40FFFFh
410000h-41FFFFh
420000h-42FFFFh
430000h-43FFFFh
440000h-44FFFFh
450000h-45FFFFh
460000h-46FFFFh
470000h-47FFFFh
480000h-48FFFFh
490000h-49FFFFh
4A0000h-4AFFFFh
4B0000h-4BFFFFh
4C0000h-4CFFFFh
4D0000h-4DFFFFh
4E0000h-4EFFFFh
4F0000h-4FFFFFh
500000h-50FFFFh
510000h-51FFFFh
520000h-52FFFFh
530000h-53FFFFh
540000h-54FFFFh
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
550000h-55FFFFh
560000h-56FFFFh
570000h-57FFFFh
580000h-58FFFFh
590000h-59FFFFh
5A0000h-5AFFFFh
5B0000h-5BFFFFh
5C0000h-5CFFFFh
5D0000h-5DFFFFh
5E0000h-5EFFFFh
5F0000h-5FFFFFh
600000h-60FFFFh
610000h-61FFFFh
620000h-62FFFFh
630000h-63FFFFh
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA0
SA1
SA2
SA3
000000h-00FFFFh
010000h-01FFFFh
020000h-02FFFFh
030000h-03FFFFh
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
16
16
16
16
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
SA4
SA5
SA6
SA7
SA8
SA9
040000h-04FFFFh
050000h-05FFFFh
060000h-06FFFFh
070000h-07FFFFh
080000h-08FFFFh
090000h-09FFFFh
SA10 0A0000h-0AFFFFh
SA11 0B0000h-0BFFFFh
SA12 0C0000h-0CFFFFh
SA13 0D0000h-0DFFFFh
SA14 0E0000h-0EFFFFh
SA15 0F0000h-0FFFFFh
SA16 100000h-10FFFFh
SA100 640000h-64FFFFh
SA101 650000h-65FFFFh
SA102 660000h-66FFFFh
SA103 670000h-67FFFFh
SA104 680000h-68FFFFh
SA105 690000h-69FFFFh
SA106 6A0000h-6AFFFFh
SA107 6B0000h-6BFFFFh
SA108 6C0000h-6CFFFFh
SA109 6D0000h-6DFFFFh
SA110 6E0000h-6EFFFFh
SA111 6F0000h-6FFFFFh
SA112 700000h-70FFFFh
SA113 710000h-71FFFFh
SA114 720000h-72FFFFh
SA115 730000h-73FFFFh
SA116 740000h-74FFFFh
SA117 750000h-75FFFFh
SA118 760000h-76FFFFh
SA119 770000h-77FFFFh
SA120 780000h-78FFFFh
SA121 790000h-79FFFFh
SA122 7A0000h-7AFFFFh
SA123 7B0000h-7BFFFFh
SA124 7C0000h-7CFFFFh
SA125 7D0000h-7DFFFFh
SA126 7E0000h-7EFFFFh
SA127 7F0000h-7F3FFFh
SA128 7F4000h-7F7FFFh
SA129 7F8000h-7FBFFFh
SA130 7FC000h-7FFFFFh
SA17
110000h-11FFFFh
SA18 120000h-12FFFFh
SA19 130000h-13FFFFh
SA20 140000h-14FFFFh
SA21 150000h-15FFFFh
SA22 160000h-16FFFFh
SA23 170000h-17FFFFh
SA24 180000h-18FFFFh
SA25 190000h-19FFFFh
64
64
64
64
64
64
64
64
64
64
64
64
SA26 1A0000h-1AFFFFh
SA27 1B0000h-1BFFFFh
SA28 1C0000h-1CFFFFh
SA29 1D0000h-1DFFFFh
SA30 1E0000h-1EFFFFh
SA31 1F0000h-1FFFFFh
SA32 200000h-20FFFFh
SA33 210000h-21FFFFh
SA34 220000h-22FFFFh
SA35 230000h-23FFFFh
SA36 240000h-24FFFFh
SA37 250000h-25FFFFh
64
64
64
64
SA38 260000h-26FFFFh
SA39 270000h-27FFFFh
SA40 280000h-28FFFFh
SA41 290000h-29FFFFh
REV. 1.1, APR. 26, 2011
P/N: PM1585
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MX29NS320/640/128E
5. BUS OPERATIONS
This chapter indicates the functions and utilizations of Bus Operations. Bus operations are initiated
through the internal command register and executed by a bus interface or similar logic circuitry. The
command register itself does not occupy any memory addresses. The register is formed of latches
that store the commands, along with the address and data information needed for executing the
command.
The content of the register acts as inputs to the internal state machine. The state machine outputs
determine the function of the device.
Table 2. shows all the bus operations, inputs and control levels required, and the resulting output.
All the operations are described in the following sections in details.
NOTE: Falling edge of AVD# determines when to disable the current burst cycle while a
new burst read cycle is started by the rising edge of CLK.
Table 2. Bus Operations
Operation
CE# OE# WE# CLK AVD# Address Data RDY RESET#
Synchronous Operations
Output
Invalid
Latch Starting Burst Address by CLK
Advance Burst Read to Next Address
Terminate Current Burst Read Cycle
L
L
H
L
H
H
X
X
H
R
R
X
X
R
L
H
X
X
L
Addr In
X
H
H
H
H
L
Output
Valid
X
H
X
L
X
X
H
X
X
HighZ HighZ
HighZ HighZ
Terminate Current Burst Read Cycle
through RESET#
Terminate Current Burst Read Cycle
and Start New Burst Read Cycle
Output
X
Addr In
H
Invalid
Asynchronous Operations
Asynchronous Read - Addresses
Latched
L
L
L
L
H
L
H
H
L
L
L
L
L
R
H
R
H
Addr In
X
H
H
H
H
H
H
H
H
Output
Data
Asynchronous Read - Data on Bus
X
Addr In
X
Asynchronous Program (AVD#
Latched Addresses)
H
H
X
Asynchronous Program (WE#
Latched Data)
Input
Valid
R
Non-Operations
Standby (CE#)
H
X
X
X
X
X
X
X
X
X
X
X
HighZ HighZ
HighZ HighZ
H
L
Hardware Reset
Legend:
L = 0; H = 1; X = VIL or VIH; R = Rising ege; h-l = High to low.
P/N: PM1585
REV. 1.1, APR. 26, 2011
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MULTIPLEXED, Burst Mode, Flash Memory
NOTES:
1. WP# protects the top two sectors.
2. ACC low protects all sectors.
3. Q0~Q15 are input (DIN) or output (DOUT) pins according to the requests of command
sequence, sector protection, or data polling algorithm.
4. In Word Mode, the addresses are AM to A0, AM: MSB of address.
5-1. Non-Burst (Asynchronous) Read Operation
Upon device's power-up, non-burst mode read is as the default state. To perform a read operation,
the system addresses the desired memory array or status register location by providing its address
on the address pins and simultaneously enabling the chip by driving AVD# & CE# LOW, and WE#
HIGH. The CLK keeps low during asynchronous read operation. The address is latched on the
rising edge of AVD#; OE# will be driven low afterwards. A/Q15-A/Q0 output the data after previous
operations is complete.
5-2. Burst (Synchronous) Read Operation
The device supports the following burst read modes:
- Continuous burst read
- Linear burst reads (8/16 words) with/without wrap around
5-2-1. Continuous Burst Read
Burst read mode is enabled when first CLK rising edge meets AVD# low period. The AVD# keeps
low for no more than one clock cycle.
The number of dummy cycles should be set (for tIACC for each burst session) before the clock
signal is being activated. Before the burst read mode is activated, the number of dummy cycle will
be determined by the setting configuration register command.
The process of the continuous burst read operation is as follows:
First CLK cycle's rising edge --> Initial word output tIACC --> Wait for dummy cycle --> Rising
rising edge of each consecutive clock, following words output (tBACC) (Automatically increase the
internal address counter)
1. For address boundary every 8 words, the first boundary starts with 000007h, next with 00000Fh
by adding 8 words address; and etc.
2. For address boundary every 128 words, the first boundary starts with 00007Fh, next with
0000FFh by adding 128 words address; and etc.
3. Additional dummy cycles are needed if the start address for the output cannot be divided by 4.
RDY status indicates the condition of the device by de-asserting.
NOTE: There is a permanent internal address boundary in the device that occurs
8 or 128 words. Boundary crossing latency is needed when the device
operates with dummy cycles set from 5 to 10.
REV. 1.1, APR. 26, 2011
P/N: PM1585
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MX29NS320/640/128E
Table 3-1. Address Latency for 10, 9 and 8 Dummy Cycles
Word
0
1
2
3
4
5
6
7
D0 D1 D2 D3 D4 D5 D6 D7 1dc D8 D9 D10 D11 D12 D13 D14 D15
D1 D2 D3 1dc D4 D5 D6 D7 1dc D8 D9 D10 D11 D12 D13 D14 D15
D2 D3 1dc 1dc D4 D5 D6 D7 1dc D8 D9 D10 D11 D12 D13 D14 D15
D3 1dc 1dc 1dc D4 D5 D6 D7 1dc D8 D9 D10 D11 D12 D13 D14 D15
D4 D5 D6 D7 1dc D8 D9 D10 D11 D12 D13 D14 D15 1dc D16 D17 D18
D5 D6 D7 1dc 1dc D8 D9 D10 D11 D12 D13 D14 D15 1dc D16 D17 D18
D6 D7 1dc 1dc 1dc D8 D9 D10 D11 D12 D13 D14 D15 1dc D16 D17 D18
D7 1dc 1dc 1dc 1dc D8 D9 D10 D11 D12 D13 D14 D15 1dc D16 D17 D18
10, 9
and
8 dc
Table 3-2. Address Latency for 7, 6, and 5 Dummy Cycles
Word
0
1
2
3
D0
D1
D2
D3
D1
D2
D3
D2
D3
1 dc
1 dc
D3
D4
D4
D4
D4
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
D8
D8
D8
D8
7, 6,
1 dc
1 dc
1 dc
and 5 dc
1 dc
Table 3-3. Address Latency for 4 Dummy Cycles
Word
0
1
2
3
D0
D1
D2
D3
D1
D2
D3
D2
D3
1 dc
1 dc
D3
D4
D4
D4
D4
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
D8
D8
D8
D8
D9
D9
D9
4 dc
1 dc
Table 3-4. Address Latency for 3 Dummy Cycles
Word
0
1
2
3
D0
D1
D2
D3
D1
D2
D3
D2
D3
D4
D4
D3
D4
D5
D5
D4
D5
D6
D6
D5
D6
D7
D7
D6
D7
D8
D8
D7
D8
D9
D9
D8
D9
D10
D10
3 dc
1 dc
Table 3-5. Address/8-word Boundary Crossing Latency for 10, 9 and 8 Dummy Cycles
Word
0
1
2
3
4
5
6
7
D0 D1 D2 D3 D4 D5 D6 D7 1dc D8 D9 D10 D11 D12 D13 D14 D15
D1 D2 D3 1dc D4 D5 D6 D7 1dc D8 D9 D10 D11 D12 D13 D14 D15
D2 D3 1dc 1dc D4 D5 D6 D7 1dc D8 D9 D10 D11 D12 D13 D14 D15
D3 1dc 1dc 1dc D4 D5 D6 D7 1dc D8 D9 D10 D11 D12 D13 D14 D15
D4 D5 D6 D7 1dc D8 D9 D10 D11 D12 D13 D14 D15 1dc D16 D17 D18
D5 D6 D7 1dc 1dc D8 D9 D10 D11 D12 D13 D14 D15 1dc D16 D17 D18
D6 D7 1dc 1dc 1dc D8 D9 D10 D11 D12 D13 D14 D15 1dc D16 D17 D18
D7 1dc 1dc 1dc 1dc D8 D9 D10 D11 D12 D13 D14 D15 1dc D16 D17 D18
10, 9
and
8 dc
P/N: PM1585
REV. 1.1, APR. 26, 2011
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MULTIPLEXED, Burst Mode, Flash Memory
Table 3-6. Address/128-word Boundary Crossing Latency for 7, 6, and 5 Dummy Cycles
Word
0
1
2
3
D0
D1
D2
D3
D1
D2
D3
D2
D3
1 dc
1 dc
D3
1 dc
1 dc
1 dc
1 dc
D4
D4
D4
D4
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
7, 6,
1 dc
1 dc
1 dc
and 5 dc
1 dc
Table 3-7. Address/128-word Boundary Crossing Latency for 4 Dummy Cycles
Word
0
1
2
3
D0
D1
D2
D3
D1
D2
D3
D2
D3
1 dc
1 dc
D3
D4
D4
D4
D4
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
D8
D8
D8
D8
1 dc
1 dc
1 dc
4 dc
1 dc
Table 3-8. Address/128-word Boundary Crossing Latency for 3 Dummy Cycles
Word
0
1
2
3
D0
D1
D2
D3
D1
D2
D3
D2
D3
1 dc
1 dc
D3
D4
D4
D4
D4
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
D8
D8
D8
D8
D9
D9
D9
3 dc
1 dc
5-2-2. 8-, 16-Word Modes Linear Burst with Wrap Around
Fixed amount of data (8 or 16 words) is output from continuous address for the linear wrap around
mode. (in the unit of words). The origin burst read address is decided by the group where the origin
address falls. The definition of groups is as illustrated in Table 4 below.
Table 4. Burst Address Groups
Mode
Group Size
Group Address Ranges
8-word
8 words
0-7h, 8-Fh, 10-17h, 18-1Fh...
16-word
16 words
0-Fh, 10-1Fh, 20-2Fh, 30-3Fh...
REV. 1.1, APR. 26, 2011
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MX29NS320/640/128E
5-2-3. Reading Memory Array
Read mode is the default state after a power-up or a reset operation.
An erase operation will be paused (after a time delay less than tESL) and the device will enter
Erase-Suspended Read mode if the device receives an Erase Suspend command while in the
Sector Erase state. While in the Erase-Suspended Read mode, data can be programmed or read
from any sector which is not being erased. Reading from addresses within sector (s) being erased
will only return the contents of the status register, which is the current status of the device.
If a program command is issued to any inactive (not currently being erased) sector during Erase-
Suspended Read mode, the device will perform the program operation and automatically return to
Erase-Suspended Read mode after the program operation completes successfully.
While in Erase-Suspended Read mode, an Erase Resume command must be issued by the system
to reactivate the erase operation. The erase operation will resume from where it was suspended
and will continue the operation until it completely finishes or another Erase Suspend command is
received.
After the memory device completes an embedded operation (automatic Chip Erase, Sector Erase,
or Program) successfully, it will automatically return to Read mode and data can be read from any
address in the array. If the embedded operation fails to complete, as indicated by status register
bit Q5 (exceeds time limitation flag) going HIGH during the operations, the system must perform a
reset operation to set the device back to Read mode.
There are several situations requiring a reset operation to return to Read mode:
- A program or erase failure – can be indicated by status register bit Q5 going HIGH during the
operation. Failures happened during the both operations will not cause the device automatically
returning to Read mode.
- The device is in Auto Select, CFI mode or read configure register mode – All of the states will
remain active until they are terminated by a reset operation.
In the two situations above, if a reset operation (either hardware reset or software reset command)
is not performed, the device will not return to Read mode and the system will not be able to read
array data.
5-3. Set Configuration Register Command Sequence
The burst mode parameter is set by the configuration register. The following modes are configured:
Burst read mode, RDY configuration, synchronous mode active & number of dummy cycles. Before
entering burst mode, the configuration register needs to be set. It's consisted of 4 cycles. Cycle 1 & 2:
Unlock sequences. Cycle 3: Data D0h & address 555h. Cycle 4: Configuration code with address
(000h). To reset the device to read or suspended read, a software reset command needs to be
issued. The device's default state after power up or hardware reset is asynchronous read mode.
Before entering synchronous mode, the register needs to be set. During bus operation, the register
can not be modified.
P/N: PM1585
REV. 1.1, APR. 26, 2011
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MULTIPLEXED, Burst Mode, Flash Memory
5-3-1. Programmable Dummy Cycle
This feature is able to indicate the device the configurable period of time for the number of
additional clock cycles. And then address data will be available after the time elapsed and AVD#
is driven active.The dummy cycle will be set to default value after power up. The total number of
dummy cycles is programmable from 3rd to 10th cycles. Refer to Section 5.3 Set Configuration
Register Command Sequence in above section for more details.
5-3-2. Configurable Dummy Cycle
The Configurable Dummy Cycle settings can be decided by the input frequency of the device - The
Configuration Bit (CR14–CR11) determines the setting. Refer to Table 5. Configurable Dummy
Cycles vs. Frequency as below.
The certain number of cycles for original burst read is set by the dummy cycle command sequence.
The clock frequency determines the number of dummy cycles configured.
NOTE: After a power-up or hardware reset, the default setting of dummy cycle will be set to 10.
In order to ensure the device is set as expected, it is recommended that dummy cycle command
sequence should to be written even if the default dummy cycle value is desired. Default state can
also be obtained by hardware reset.
Other setting not listed in the table above will be reserved as invalid.
If the setting CR[14:11] is not in legal setting as table listed, the device will output CR[14:11] to
0001 and RDY will be disasserted.
5-3-3. Burst Length Configuration
Three different burst read modes are supported: 8 & 16 word linear burst read with wrap around;
continuous burst read. The device's default burst read is continuous read. It launches with starting
address till the burst read ends. When reaches the highest address, it wraps around to the lowest
address. The wrap around occurs in the 8 or 16 word boundary.
REV. 1.1, APR. 26, 2011
P/N: PM1585
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MX29NS320/640/128E
Table 5. Configurable Dummy Cycles vs. Frequency
Freq Max
(Mhz)
CR [14:11]
Dummy Cycles
0001
0010
0011
0100
0101
0110
0111
1000
3
4
25
38
50
63
75
87
98
108
5
6
7
8
9
10
5-3-4. Burst Wrap Around
CR3 is set to "1" by default. When it changes to "0", the burst warp around mode is disabled.
5-3-5. Output Drive Strength
User may tune the strength of output driver from full strength to half strength depends on the
configuration bit CR7.
The default setting is CR7=1; with full strength.
If CR7=0, the strength of output buffer will be reduced to half strength.
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MULTIPLEXED, Burst Mode, Flash Memory
5-4. Program Operation
All three devices provide the ability to program the memory array in Word mode. As long as users
enter the correct cycle defined in the Chapter 7. Command Definitions (including 2 unlock
cycles and the A0H program command), word data provided on the data lines by the system will
automatically be programmed into the array at the specified location.
After the program command sequence has been executed, the internal write state machine (WSM)
automatically executes the algorithms and timings necessary for programming and verification,
which includes generating suitable program pulses, checking cell threshold voltage margins, and
repeating the program pulse if any cells do not pass verification or have low margins. The internal
controller protects cells that do pass verification and margin tests from being over-programmed by
inhibiting further program pulses to these passing cells as weaker cells continue to be programmed.
With the internal WSM automatically controlling the programming process, users only need to enter
the program command and data once.
Programming will only change the bit status from "1" to "0". It is not possible to change the bit
status from "0" to "1" by programming. This can only be done with an erase operation. Furthermore,
the internal write verification only checks and detects errors in cases where a "1" is not successfully
programmed to "0".
Any commands written to the device during programming will be ignored except hardware reset
or program suspend. Hardware reset will terminate the program operation after a period of time
not more than tPSL. When the program is complete or the program operation is terminated by a
hardware reset, the device will return to Read mode. When program suspend is ready, the device
will enter program suspend read mode.
After the embedded program operation has begun, users can check for completion by reading the
following bits in the status register table below:
Q7*1
Q6
Q5
Q1
Status
Q7#
Q7#
Toggling
Toggling
0
1
0
In progress
Exceed Time Limit
N/A
NOTE: DQ7 (Data# Polling bit) shows the status of on-going or completion for program and
erase operations or in erase suspend mode.
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MX29NS320/640/128E
5-4-1. Programming Commands/Command Sequences
To perform a program operation, the system provides the desired address on the address pins,
enables the chip by asserting CE# & WE# LOW & OE# to HIGH, and disables the Data (I/O) pins
by holding OE# HIGH. To Latch address, AVD# needs to be asserted LOW. On 1st falling edge of
WE#, address latched. On 1st rising edge of WE#, data latched.
Table2. Bus Operation on page 16, described the detail of the combinations.
To see an example of the implementation on waveform, please refer to Figure 17. Program
Operation Timings Waveform. The system is not allowed to write invalid commands (commands
not defined in this datasheet) to the device. Writing an invalid command may put the device in an
undefined state.
5-4-2. Accelerated Program and Erase Operations
By applying high voltage (Vhv) to the ACC pin, the device will enter the Accelerated Programming
mode. This mode permits the system to skip the normal command unlock sequences and program
locations directly. During accelerated programming, the current drawn from the ACC pin is no more
than ICP1.
5-4-3. Write Buffer Programming Operation
The devices program 32 words in a programming operation. To trigger the Write Buffer
Programming, start with the first two unlock cycles, then third cycle writes the Write Buffer Load
command at the predefined programming Sector Address. The fourth cycle writes the "word
locations subtract one" number.
Following the above operations, system starts to write the mingling of address and data. After
the programming of the first address or data, the "write-buffer-page" is selected. The following
data should be within the above mentioned page. The "write-buffer-page" is selected by choosing
address Amax-A5. "Write-Buffer-Page" address has to be the same for all address/data write into
the write buffer. If not, operation will be aborted.
To program the content of the write buffer page this command must be followed by a write to
buffer Program confirm command. The operation of write-buffer can be suspended or resumed by
the standard commands, once the write buffer programming operation is finished, it will return to
normal READ mode.
“Abort” will be executed for the Write Buffer Programming Sequence if the following conditions
occurred:
- The value loaded is bigger than the page buffer size during "Number of Locations to Program"
- Address written in a sector is not the same as the one assigned during the Write-Buffer-Load
command.
- Address/ Data pair written to a different write-buffer-page than the one assigned by the
"Starting Address" during the "write buffer data loading" operation.
- Writing not "Confirm Command" after the assigned number of "data load" cycles.
At Write Buffer Abort mode, the status register will be Q1=1, Q7=DATA# (last address written),
Q6=toggle, Q5=0. A Write-to-Buffer-Abort Reset command sequence has to be written to reset the
device for the next operation.
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MULTIPLEXED, Burst Mode, Flash Memory
Write buffer programming can be conducted in any sequence. However the CFI functions, Auto-
select, Secured Silicon sectors are not functional when program operation is in progress. Multiple
write buffer programming operations on the same write buffer address range without intervening
erases is available. Any bit in a write buffer address range can not be programmed from 0 back to 1.
5-4-4. Write Buffer Programming Command Sequence
Write Buffer Programming Sequence is able to facilitate faster programming as compared to the
standard Program Command Sequence.
See Table 7. and Figure 1. below for the program command sequence.
5-4-5. Buffer Write Abort
In the table below, Q1 is the indicator of Buffer Write Abort. When Q1=1, the device will abort from
buffer write and go back to read status register:
Status
Q7
Q6
Q5
Q3
Q2
Q1
Buffer Write Busy
Q7#
Toggle
0
N/A
N/A
0
Buffer Write Abort
Q7#
Q7#
Toggle
Toggle
0
1
N/A
N/A
N/A
N/A
1
0
Buffer Write Exceeded Time Limit
Table 6. Write Buffer Command Sequence
Sequence
Command
Address
Data
Remarks
1
Unlock (1)
555
00AA
0055
2
3
4
Unlock (2)
2AA
Load Write Buffer
Start Address 0025h
Indicate # of Program
Locations
Word
Start Address
Count
(# of locations) - 1
Addresses need to be within write-buffer-
page boundaries, but no need to be
loaded in any order.
5
Load 1st word
Start Address
Write
Write Buffer
Location
6-X
Load next word
Load last word
Write
Write
Same as above
Write Buffer
Location
X+1
Same as above
This command must come after the
0029h last write buffer location loaded, or the
operation will ABORT.
Write Buffer Program
Confirm
Sector
Address
X+2
X+3
Device goes busy
Status monitoring
through Q pins (Conduct
Data Bar Polling on the
Last Loaded Address)
Last
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MX29NS320/640/128E
Figure 1. Write Buffer Programming Operation
Write “Write to Buffer”
command and
Sector Address
Part of “Write to Buffer”
Command Sequence
Write number of addresses
to program minus 1(DC)
and Sector Address
Write first address/data
Yes
DC = 0 ?
Write to a different
sector address
No
Yes
Abort Write to
Buffer Operation?
Write to buffer ABORTED.
Must write “Write-to-buffer
Abort Reset” command
sequence to return
No
Write next address/data pair
to read mode.
DC = DC - 1
Write program buffer to
flash sector address
Read Q15 - Q0 at
Last Loaded Address
Yes
Q7 = Data?
No
No
No
Q1 = 1?
Q5 = 1?
Yes
Yes
Read Q15 - Q0 with
address = Last Loaded
Address
Yes
Q7 = Data?
No
PASS
FAIL or ABORT
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MULTIPLEXED, Burst Mode, Flash Memory
Figure 2. Status Polling For Write Buffer Program
Start
Read Q7~Q0 at last write
address (Note 1)
No
Q7 = Data# ?
Yes
Q1=1 ?
Yes
Only for write
buffer program
No
No
Q5=1 ?
Write Buffer Abort
Yes
Read Q7~Q0 at last write
address (Note 1)
No
Q7 = Data# ?
(Note 2)
Yes
FAIL
Pass
NOTES:
1. For programming, valid address means program address. For erasing, valid address
means erase sectors address.
2. Q7 should be rechecked even Q5="1" because Q7 may change simultaneously with Q5.
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5-5. Erase Operation
There are two types of erase operations performed on the memory array -- Sector Erase and Chip
Erase. Sector Erase operation erases one selected sector.
Chip erase will not be conducted if any of the sectors is protected. It can be done after the sector is
being un-protected.
5-5-1. Sector Erase
The sector erase operation is used to clear data within a sector by returning all the memory
location to the “1” state. It requires six command cycles to initiate the erase operation.
The first two are "unlock cycles", the third is a configuration cycle, the fourth and fifth ones are also
"unlock cycles", and the last cycle is the Sector Erase command. After the sector erase command
sequence has been issued, the embedded sector erase operation will then begin.
After the embedded sector erase operation begins, all commands except Erase Suspend will be
ignored. The only way to interrupt the operation is with an Erase Suspend command or with a
hardware reset. The hardware reset will completely abort the operation and return the device to
Read mode.
The system can determine the status of the embedded sector erase operation by the following
methods:
Status
In progress
Q7
Q6
Q5
Q3
Q2
0
Toggling
0
NA
Toggling
Exceeded time limit
0
Toggling
1
NA
Toggling
NOTE:
Q2 is a localized indicator showing a specified sector is undergoing erase operation or
not. Q2 toggles when user reads at addresses where the sectors are actively being
erased (in erase mode) or to be erased (in erase suspend mode).
5-5-2. Chip Erase
The Chip Erase operation is used to erase all the data within the memory array. All memory cells
containing a "0" will be returned to the erased state of "1". This operation requires 6 write cycles
to initiate the action. The first two cycles are "unlock" cycles, the third is a configuration cycle, the
fourth and fifth are also "unlock" cycles, and the sixth cycle initiates the chip erase operation.
During the chip erase operation, no other software commands will be accepted, but if a hardware
reset is received or the working voltage is too low, that chip erase will be terminated. After Chip
Erase operation completes, the chip will automatically return to Read mode. If any of the sectors is
locked, chip erase will not start.
The system is able to determine the status of the embedded chip erase operation by the following
methods:
Status
Q7
0
Q6
Q5
0
Q2
In progress
Toggling
Toggling
Toggling
Toggling
Exceed time limit
0
1
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MULTIPLEXED, Burst Mode, Flash Memory
5-5-3. Sector Erase Command Sequence
There are six bus cycles in normal sector erase operation in normal mode. Sector erase command
sequence is as follows: Write 2 unlock cycles --> Set-up command --> 2 more unlock cycles
-->Address of sector to be erased --> sector erase command.
Erase operation doesn't require the pre-programming in advance. An all zero data pattern before
erase initiation will come to pass for programming & verifying the device per the Erase. No controls
or timing is needed during sector erase operation.
After the writing of command sequence, the erase operation will start.
Upon completion of the erase operation, the device's address will not be latched and returns to
read status. When Embedded Erase operation is on-going, the device cannot be read.
When erase operation is engaged, only erase suspend can be conducted. A hardware reset will
terminate the erase operation.
5-5-4. Accelerated Sector Erase
An accelerated erase function is provided to erase no more than 100 times per sector erase. ACC
erase operation should be conducted in the range of 30C +/-10C. The ACC erase provides much
faster erase operation compare with standard erase operations.
Operations below are needed prior to ACC sector erase operation:
1. Unlock the sectors should be erased with DPB before hand. Locked sectors can not be erased.
2. Vhv must be applied to ACC input at least 1 μs before executing step 3.
3. Chip erase command is issued.
4. Q2/Q6 or Q7 status bits should be monitored so to verify when erase operation is complete.
This procedure is the same as in the standard erase operation.
5. ACC is lowered from Vhv to VCC.
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MX29NS320/640/128E
Figure 3. Erase Operation
START
Erase
Command Sequence
Poll Data
from System
Erase
Operation
on-going
No
Data = FFh?
Yes
Erase Completion
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MULTIPLEXED, Burst Mode, Flash Memory
5-6. Program/Erase Operation Status
Program or erase operation status is disaplayed in the following status bits: Q2, Q3, Q5, Q6, and
Q7. Descriptions of the bits is in the following tables & sections. Q6 and Q7 indicate if program or
erase is finished or not.
Table 7. Program Operation Status
Q7
Q6
Q5
Q3
Q2
Q1
Status
(Note 2)
(Note 1)
(Note 2) (Note 4)
Program
Suspend
Mode
Read from Program Suspended Sector
Invalid data will output from address under programming.
Read in Non-Program Suspended Sector
Program
Data
(Note 3)
No
Q7#
0
Toggle
Toggle
0
0
0
N/A
1
0
Standard
Mode
Toggle
Erase
Toggle
N/A
N/A
Erase Suspended
No
1
N/A
Toggle
Data
Erase
Erase-Suspend-
Read
Sector
Toggle
Suspend
Mode
Non-Erase Suspended
Sector
Data
Data
Data
Data
Data
Erase-Suspend-Program
BUSY
Exceeded Timing Limits
Q7#
Q7#
Q7#
Toggle
Toggle
Toggle
0
0
1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
0
Write to
Buffer
ABORT
Q7#
Toggle
0
N/A
N/A
1
(Note 5)
Legend: T - Toggle; NT - No toggle.
NOTES:
1. When embedded program/erase exceed max. time limit, Q5 changes to "1".
2. A valid address is needed for reading status info from Q7 & Q2.
3. When program is suspended, output data is invalid.
4. During write buffer program, Q1 indicates the write to buffer abort status.
5. During write buffer program, data-bar polling algorithm needs to be conducted.
Data-bar of Q7 shows the last address loaded for write buffer.
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5-7. Program/Erase Suspend/Resume
5-7-1. Program Suspend
After a program operation begins, Program Suspend is the only valid command that can be issued.
The system will determine if the device has entered the Program-Suspended Read mode through
Q6.
After the device has entered Program-Suspended mode, the system can read any sector (s)
except that being programmed by the suspended program operation. Reading the array being
program suspended is invalid. Whenever a suspend command is issued, user must issue a resume
command and check Q6 toggle bit status, before issue another program command. The system
can use the Status Register bits shown in Table 7 to determine the current state of the device:
When the device is Program/Erase suspended, user is allowed to execute read array, Auto Select,
read CFI, read security silicon commands.
5-7-2. Program Resume
The Program Resume command is valid only when the device is in Program-Suspended mode.
After program resumes, users are allowed to issue another Program Suspend command, but there
should be a 25us interval between Program Resume and the next Program Suspend command.
5-7-3. Program Suspend/Program Resume Commands
The Program suspend command is for pausing the "Write to Buffer" operation.
The Program suspend operation is as follows: Issuing Programming Suspend Command -->
Device's programming operation suspended paused within tPSL; Status Bits updated; Address
defined --> Data to be read from non-suspended sectors.
Note that when an erase suspend is in operation, program suspend can also be conducted, data
can then be read from non-suspended sectors.
If read from OTP sectors needed, it needs to exit the region with proper command sequences.
Auto Select code can also be read from suspended sectors. When exit from Auto select mode, it
returns to suspend mode.
For Program Resume, it operates as thus: Issuing Program Resume command --> Device resumes
programming (Status to be checked by Status bit Q7 or Q6)
It must exit the suspend by issuing resume command. After programming being resumed, another
program suspend can be issued.
NOTE: While a program operation is suspended and resumed more than once, a minimum
delay of tPRS (Program Resume to Program Suspend) is required between next
resume and suspend command.
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MULTIPLEXED, Burst Mode, Flash Memory
5-7-4. Erase Suspend
After a sector erase operation begins, Erase Suspend is the only valid command that can be
issued. If the system issues an Erase Suspend command after the sector erase operation has
already begun, the device will not enter Erase-Suspended Read mode until tESL has elapsed. The
system is able to determine if the device has entered the Erase-Suspended Read mode through
Q6 and Q7.
After the device has entered Erase-Suspended Read mode, the system can read or program
any sector (s) except that being erased by the suspended erase operation. Reading any sector
being erased or programmed will return the contents of the status register. Whenever a suspend
command is issued, users must issue a resume command and check Q6 toggle bit status, before
issue another erase command.
When the device reads from a erase suspended sector during burst read mode, the burst read
operation will stop and RDY will be disabled when crossing the boundary to the suspended sector.
User may restart the burst operation by issuing new address and AVD# pulse.
The system is able to use the status register bits shown in the following table to determine the
current state of the device:
Status
Q7
Q6
Q5
Q3
Q2
Q1
Erase suspend read in erase
suspended sector
1
No toggle
0
N/A
Toggle
N/A
Erase suspend read in non-erase
suspended sector
Data
Q7#
Data
Data
0
Data
N/A
Data
N/A
Data
N/A
Erase suspend program in non-
erase suspended sector
Toggle
5-7-5. Sector Erase Resume
The Sector Erase Resume command is valid only when the device is in Erase-Suspended Read
mode. After erase operation resumes, users can issue another Erase Suspend command, but
there should be a 400us interval between Erase Resume and the next Erase Suspend command.
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Figure 4. Data# Polling Timing Waveforms (During Embedded Algorithms)
High Z
High Z
Status Data
Status Data
A/Q15-A/Q0
VA
VA
t
ACC
A
–
A16
max
VA
VA
t
CEZ
t
CE
CE#
t
CH
AVD#
WE#
t
OEH
t
OEZ
t
OE
OE#
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MULTIPLEXED, Burst Mode, Flash Memory
Figure 5. Data# Polling For Word Program/Erase
Start
Read Q7~Q0 at valid address
No
Q7 = Data# ?
Yes
No
Q5 = 1 ?
Yes
Read Q7~Q0 at valid address
No
Q7 = Data# ?
Yes
FAIL
Pass
Figure 6. Toggle Bit Timing Waveforms (During Embedded Algorithms)
High Z
High Z
A/Q15
–
A/Q0
Status Data
Status Data
VA
VA
VA
tACC
A
–
A16
VA
max
tCEZ
tCE
CE#
tCH
AVD#
WE#
tOEH
tOEZ
tOE
OE#
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MX29NS320/640/128E
Figure 7. Toggle Bit Algorithm
Start
Read Q7-Q0 Twice
(Note 1)
NO
Q6 Toggle ?
YES
NO
Q5 = 1?
YES
Read Q7~Q0 Twice
NO
Q6 Toggle ?
YES
PGM/ERS fail
Write Reset CMD
PGM/ERS Complete
NOTES:
1. Read toggle bit twice to determine whether or not it is toggling.
2. Recheck toggle bit because it may stop toggling as Q5 changes to "1".
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MULTIPLEXED, Burst Mode, Flash Memory
5-8. Configuration Register
A configuration register is used to set the various burst parameters: number of dummy cycles, burst
read mode, burst length, RDY configuration, and synchronous mode active.
The Configuration Register Table displays the address bits of configuration register settings
represent various device functions.
Table 8. Configuration Register
Function
CR Bit
Settings (Binary)
Reserved
CR15
0 = Default
0000 = Reserved
0001 = Data is valid on the 3rd active CLK rising edge (Default Value)
0010 = Data is valid on the 4th active CLK rising edge
0011 = Data is valid on the 5th active CLK rising edge
0100 = Data is valid on the 6th active CLK rising edge
0101 = Data is valid on the 7th active CLK rising edge
0110 = Data is valid on the 8th active CLK rising edge
0111 = Data is valid on the 9th active CLK rising edge
1000 = data is valid on the 10th active CLK rising edge
1001 = Reserved
CR14
CR13
CR12
Programmable
Dummy Cycles
1010 = Reserved
1011 = Reserved
1100 = Reserved
1101 = Reserved
CR11
1110 = Reserved
1111 = Reserved
0 = RDY signal is active low
RDY Polarity
Reserved
RDY
CR10
CR9
CR8
1 = RDY signal is active high (default)
1 = Default
0 = RDY active one clock cycle before data
1 = RDY active with data (Default)
Driver Strength
Reserved
CR7
CR6
CR5
CR4
1 = Full driver strength (Default) 0=Half driver strength
1 = Default
0 = Default
0 = Default
Reserved
Reserved
0 = No Wrap Around Burst
Burst Wrap
Around
CR3
1 = Wrap Around Burst (Default)
000 = Continuous (Default)
010 = 8-Word Linear Burst
011 = 16-Word Linear Burst
(All other bit settings are reserved)
CR2
CR1
CR0
Burst Length
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NOTES:
1. RDY Configuration - MX29NS320/640/128E are all able to set RDY to output VOH with
valid data by default. RDY goes active one data cycle ahead of the active data. CR8
sets to "1" for RDY being active; "0" for RDY being active one cycle ahead of the valid
data to be output.
2. RDY Polarity - All devices have this default setting to indicate if the system is
ready for CR10 to set to "1" when RDY is high. Set to "0" will set RDY to low. When
RDY is low, RDY shows the device is ready.
5-9. Enter/Exit Secured Silicon Sector Command Sequence
A 8-word, random ESN (Electronic Serial Number) is in the Secured Silicon Sector region. The
operation of this region is thus: 3-cycle command to enter the region --> Access of the region -->
4-cycle command to exit the region --> Return to normal operation
Not the Secured Silicon Region cannot be accessed when program/erase is in operation.
In the Secured Silicon Sector region, 128-word region is factory locked, while the other 128-word
region is customer locked.
5-9-1. Program Secured Silicon Sector Command Sequence
Programming Secured Silicon is a two-cycle command. It is initiated by A0h command followed by
program address with program data. The program operation then starts.
The system can monitor Q7 or Q2/Q6 to check the status of the embedded operation as the
system does when programming the normal array.
Programming the Secured Silicon will only change the bit status from “1” to “0”. It is not possible
to change the bit status from “0” to “1” by programming. Furthermore, the internal write verification
only checks and detects errors in case where a ”1” is not successfully programmed to “0”.
When program is complete, the device then returns to Read Secured Silicon Sector mode.
If embedded program exceeds max. time limit (a failure occurs), Q5 changes to “1” and Q6 keeps
toggling. Under this condition, a soft ware reset command is needed and the device returns to
Read Secured Silicon Sector mode.
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MULTIPLEXED, Burst Mode, Flash Memory
5-10. Auto Select Operations
Users are allowed to issue the Auto Select command (two unlock cycles followed by the Auto
Select command 90H) to enter Auto Select mode when the device is in either:
After entering Auto Select mode, user can query the following status multiple times without issuing
a new Auto Select command:
1. Manufacturer ID
2. Device ID
3. Security Sector locked status
4. Sector protected status
While In Auto Select mode, issuing a Reset command (F0H) will return the device to one of the
following modes:
•
•
•
Read mode
Erase-Suspended Read mode (if Erase-Suspend is active)
Program Suspended Read mode (if Program Suspend is active).
NOTE: After entering Auto Select mode, no other commands are allowed except the
reset command.
5-10-1. Auto Select Command Sequence
The Auto Select mode has four command cycles. The first two are unlock cycles, and followed by a
specific command. The fourth cycle is a normal read cycle, and user can read at any address any
number of times without entering another command sequence. The Reset command is necessary
to exit the Auto Select mode and back to reading memory array. The following table shows the
identification code with corresponding address.
Address
Data (Hex)
Manufacturer ID
X00
C2
Device ID
MX29NS640E
MX29NS320E
MX29NS128E
X01/0E/0F
X01/0E/0F
2B7E/2B33/2B00
2A7E/2A31/2A00
Device ID
Device ID
X01/0E/0F
(Sector address)
X02
2C7E/2C35/2C00
00/01
Sector Protect Verify
Q0-Q2 = Reserved
Q4 & Q3 - WP# Protections Boot Code
01 = WP# Protects only the Top Boot Sectors
Q5 Handshake Bit
0 = Handshake, 1 = Reserved
Q6 - Customer Lock Bit
Secured Silicon
X07
0 = Un-Locked, 1 = Locked,
Q7 - Factory Lock Bit
0 = Un-Locked, 1 = Locked
Q8 - Q15 = Reserved
NOTE: After entering Auto Select mode, no other commands are allowed except the
reset command.
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5-11. Handshaking Feature
By conducting the host to detect the Ready (RDY) signal, the handshaking feature enables the
system to decide when the initial burst data is ready.
The operation is as thus: Configure the # of dummy cycle by Configuration Register --> CE# goes
low --> Rising edge of RDY indicates the initial burst word data indicated
The Burst read may be optimized by configuring the setting the number of dummy cycle per clock
frequency.
The Auto Select Function helps the host to see if the device is ready for handshaking operation.
Table 9. Dummy Cycles for Handshaking
Clock Cycles after AVD# Low (Typical No.)
Address Issuing Condition
108 MHz
10
Initial address (VI/O = 1.8 V)
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MULTIPLEXED, Burst Mode, Flash Memory
6. SECURITY FEATURES
This device is able to provide security protection features to prevent unintentional program or
erase operations.
6-1. Lock Register
A Lock Register allows the Secured Silicon Sector Protection to be configured or not.
6-1-1. Lock Register Bits
User can choose if Q0 = 1 with default OTP or Q0 = 0 to lock Secured Silicon Sector.
After the Lock Register Bits Command Set Entry command sequence is issued, the read and write
operations for normal sectors are disabled until this mode exits.
Table 10. Lock Register bits
Q15-Q1
Q0
Don't care
Secured Silicon Sector Protection Bit
Please refer to the command for Lock Register command set to read and program the Lock
register.
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MX29NS320/640/128E
Figure 8. Lock Register Program Algorithm
START
Write Data AAH, Address 555H
Write Data 55H, Address 2AAH
Write Data 40H, Address 555H
Lock register command set Entry
Write Data A0H,
Address don’t care
Lock register data program
Write Program Data,
Address don’t care
Data # Polling Algorithm
YES
Done
NO
Pass
NO
Q5 = 1
YES
Fail
Exit Lock Register
command
Reset command
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MULTIPLEXED, Burst Mode, Flash Memory
6-1-2. Dynamic Write Protection Bits (DPBS)
The Dynamic Protection allows the software application to easily protect sectors against inadvertent
change. However, the protection can be easily disabled when changes are necessary.
All Dynamic Protection bit (DPB) are volatile and assigned to each sector. It can be modify
individual.To modify the DPB status by issuing the DPB Set (programmed to “0”) or DPB Clear (erased
to “1”) commands, then placing each sector in the protected or unprotected state separately. The
DPBs are set as protected by default.
6-2. Hardware Data Protection Mode
Two types of hardware protections is provided:
1. WP# low protects the top two sectors.
2. ACC low protects all sectors.
NOTES:
1. Q0~Q15 are input (DIN) or output (DOUT) pins according to the requests of
command sequence, sector protection, or data polling algorithm.
2. In Word Mode, the addresses are AM to A0, AM: MSB of address.
6-2-1. Write Protect (WP#)
The hardware protection provided by WP# is by asserting the WP# to low. After WP# goes low, the
upper two sectors will be protected. The erase & program function in these two sectors are disabled
after WP# protection enabled. The WP# protection will override the software protection method.
When WP# is asserted high, software protection mode determines which array to protect.
6-2-2. WP# Boot Sector Protection
The WP# should be asserted low on the last cycle of program or erase command so it can protect
the top two sectors. (4th cycle in program; 6th cycle in erase).
NOTE: The WP# should not be left floating or unconnected; or it may cause inconsistent
behavior of the device.
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MX29NS320/640/128E
6-3. Security Sector Flash Memory Region
The Security Sector region is an extra OTP memory space of 256 words in length. The security
sector can be locked upon shipping from factory, or it can be locked by customer after shipping.
Customer can issue Security Sector Factory Protect Verify and/or Security Sector Protect Verify to
query the lock status of the device.
In factory-locked device, security sector region is protected when shipped from factory and the
security silicon sector indicator bit is set to "1". In customer lockable device, security sector region
is unprotected when shipped from factory and the security silicon indicator bit is set to "0".
6-3-1. Factory Locked: Security Sector Programmed and Protected at the Factory
In a factory-locked device, the Security Sector is permanently locked before shipping from the
factory. The device will have a 8-word ESN in the security region. The ESN occupies 00000h to
00007h in word mode.
Secured Silicon Sector
Address Range
Express Flash
Factory Locked
Standard Factory Locked
000000h-00007Fh
ESN
Factory lock
000080h-0000FFh
Unavailable
Determined by Customer
6-3-2. Customer Lockable: Security Sector NOT Programmed or Protected
at the Factory
When the security feature is not required, the security region can act as an extra memory space.
Security silicon sector can also be protected by two methods. Note that once the security silicon
sector is protected, there is no way to unprotect the security silicon sector and the content of it can
no longer be altered.
After the security silicon is locked and verified, system must write Exit Security Sector Region, go
through a power cycle, or issue a hardware reset to return the device to read normal array mode.
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MULTIPLEXED, Burst Mode, Flash Memory
7. COMMAND DEFINITIONS
Command Definitions Tables shows the address and data requirements for both command
sequences.
Automatic Select
Asyn.
Read
Reset
Mode
Sector
Protect
Verify
Command
Cycles
Manuf.
ID
Device
ID
Indicator
Bits
1
1
1
4
6
4
4
Addr
RA
XXX
555
555
555
555
1st Bus
Cycle
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
RD
F0
AA
2AA
55
555
90
AA
2AA
55
555
90
X01
ID1
X0E
ID2
X0F
ID3
AA
2AA
55
555
90
AA
2AA
55
555
90
2nd Bus
Cycle
3rd Bus
Cycle
X00
C2
07
Data
02
Data
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Program
Program
Buffer to
Flash
Program/ Program/
Set
Read
Program
to Buffer
to Buffer
Abort
Reset
3
Chip
Sector
Erase
Command
CFI Program
Erase
Erase
Config.
Config.
Erase
Suspend Resume Register Register
Cycles
1
4
6
1
6
6
1
1
4
4
1st Bus Addr
55
98
555
AA
2AA
55
555
A0
555
AA
2AA
55
SA
25
SA
WC
PA
PD
WBL
PD
SA
29
555
AA
2AA
55
555
555
AA
2AA
55
555
80
555
AA
2AA
55
555
10
555
AA
2AA
55
555
80
555
AA
2AA
55
SA
30
XXX
B0
XXX
30
555
AA
2AA
55
555
D0
X00
CR
555
AA
2AA
55
555
C6
Cycle
2nd Bus Addr
Cycle
3rd Bus Addr
Cycle
4th Bus Addr
Cycle
5th Bus Addr
Cycle
6th Bus Addr
Data
Data
Data
F0
PA
PD
XX
CR
Data
Data
Cycle
Data
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first.
PD(0) = Secured Silicon Sector Lock Bit. PD(0), or bit[0].
PD(1) = Persistent Protection Mode Lock Bit. PD(1), or bit[1], must be set to ‘0’ for protection while PD(2), bit[2] must be left as ‘1’.
PD(2) = Password Protection Mode Lock Bit. PD(2), or bit[2], must be set to ‘0’ for protection while PD(1), bit[1] must be left as ‘1’.
PD(3) = Protection Mode OTP Bit. PD(3) or bit[3].
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MX29NS320/640/128E
Deep Power Down
Lock
Command
Sequence
Lock Register
Command Set
Entry
Lock Register
Command Set
Exit
Lock Register
Bit Program
Enter
Exit
Cycles
Word
Word
3
2
2
555
AA
XXX
AB
Addr
Data
Addr
Data
Addr
Data
Addr
Data
555
AA
2AA
55
555
40
XXX
A0
00
XX
90
XX
00
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
2AA
55
Data
XXX
B9
4thBus
Cycle
Addr
Data
Addr
Data
Addr
Data
5th Bus
Cycle
6th Bus
Cycle
7th Bus
Cycle
Secured Silicon Sector
Dynamic Protection Bits
DPB
DPB Set DPB Clear Status
Read
Command
Sector
Entry
Sector
Sector
Read
Sector
Exit
Command
Set Entry
Command
Set Exit
Sequence
Program
3
2
1
4
3
2
2
1
2
Cycles
Addr
555
AA
2AA
55
555
88
XX
A0
PA
RA
Data
555
AA
2AA
55
555
90
555
AA
2AA
55
555
E0
XX
A0
SA
00
XX
A0
SA
01
SA
RD(0)
XX
90
XX
00
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
Data
Addr
Data
Addr
Data
Addr
Data
Data
XX
00
4th Bus
Cycle
Addr
Data
5th Bus
Cycle
SA = Address of the sector to be verified (in autoselect mode) or erased.
Address bits Amax - A13 uniquely select any sector.
RD(0) = Q0 protection indicator bit. If protected, Q0 = 0, if unprotected, Q0 = 1.
RD(1) = Q1 protection indicator bit. If protected, Q1 = 0, if unprotected, Q1 = 1.
RD(2) = Q2 protection indicator bit. If protected, Q2 = 0, if unprotected, Q2 = 1.
RD(4) = Q4 protection indicator bit. If protected, Q4 = 0, if unprotected, Q4 = 1.
WBL = Write Buffer Location. Address must be within the same write buffer page as PA.
WC = Word Count. Number of write buffer locations to load minus 1.
NOTE: It is not recommended to adopt any other code not in the command definition table
which will potentially enter the hidden mode.
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MULTIPLEXED, Burst Mode, Flash Memory
8. ENERGY SAVING MODE
8-1. Standby Mode
The device enters Standby mode whenever the RESET# and CE# pins are both held High except
in the embedded mode. While in this mode, WE# and OE# will be ignored, all Data Output pins will
be in a high impedance state, and the device will draw minimal (ICC3) current.
8-2. Automatic Sleep Mode
Automatic Sleep mode is able to minimize power consumption of flash device. The device
automatically enters this mode when the addresses and clock stays stable for tACC + 20 ns. The
automatic sleep mode will not be influenced by the CE#, WE#, and OE# control signals. Standard
address access timings are responsible for offering new data when addresses are changed.
Output data will be always available to the system and latched in sleep mode.
ICC6 in the Table 11. DC Characteristics indicates the current specifications for Automatic Sleep
mode.
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MX29NS320/640/128E
Table 11. DC Characteristics
Parameter
Description
Test Conditions
Min Typ
Max
Unit
VIN = VSS to VCC,
VCC = VCC max
ILI
Input Leakage Current
±1
uA
VOUT = VSS to VCC,
ILO
Output Leakage Current
±1
uA
VCC = VCC max
High Voltage Pin Leakage
Current
VIN=Vhv,
VCC=VCC max
CE# = VIL, OE# = VIL,
burst length = 8
CE# = VIL, OE# = VIL,
burst length = 16
CE# = VIL, OE# = VIL,
ILHV
35
33
35
39
18
4
uA
mA
mA
mA
mA
mA
108
MHz
108
MHz
108
26
26
30
15
3
VCC Active Burst Read
Current
ICCB
ICC1
burst length = continuous MHz
5 MHz
CE# = VIL, OE# = VIH
1 MHz
VCC Active Asynchronous
Read Current
ICC2
ICC3
VCC Active Write Current CE# = VIL, OE# = VIH, ACC = VIH
20
40
60
mA
uA
VCC Standby Current
CE# = VIH, RESET# = VIH (Note 8)
100
ICC4
ICC6
IDPD
VCC Reset Current
VCC Sleep Current
RESET# = VIL, CLK = VIL (Note 8)
CE# = VIL, OE# = VIH
80
40
10
150
100
50
uA
uA
uA
Vcc Deep Power Down
Current
Accelerated Program
Current
IPPW
ACC = Vhv
ACC = Vhv
20
30
mA
IPPE
VIL
Accelerated Erase Current
Input Low Voltage
20
30
mA
V
-0.1
0.3xVI/O
0.7xVI/
O
VIH
VOL
VOH
Input High Voltage
Output Low Voltage
Output High Voltage
VI/O+0.3
0.45
V
V
V
IOL = 100 uA, VCC = VCC min
IOH = –100 uA, VCC = VCC min
0.85x
VI/O
Very High Voltage for
Auto Select/Accelerated
Program
Vhv
9.5
1.0
10.5
1.4
V
V
VLKO
Low VCC Lock-out Voltage
NOTE: Not 100% tested in production.
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MULTIPLEXED, Burst Mode, Flash Memory
8-3. Reset Commands
Executing the Reset command is able to reset the device to the Read or Erase-Suspend-Read
mode. For this command, address bits are don’t care.
The reset command can be written between the sequence cycles of an erase command and before
the erase operation begins. It resets the device back to read mode. As soon as erase operation
begins, the reset command will be ignored until it is complete.
The reset command can be written between the sequence cycles of an program command
and before a program operation begins. It resets the device back to read mode. If the program
command sequence is written when in the Erase Suspend mode, writing the reset command will
return the device to the erase-suspend-read mode. As soon as program operation begins, the
reset command will be ignored until it is complete.
The reset command can be written between the sequence cycles in Auto Select command
sequence. It resets the device back to read mode when in Auto Select mode. Writing the reset
command will cause the device return to the erase-suspend-read mode if the device enters the
Auto Select mode while it is in Erase Suspend mode.
During a program or erase operation, if Q5 goes high, writing the reset command will either:
1. Return to read mode
2. Returns to erase-suspend-read mode (if the device was in Erase Suspend)
NOTE: The system must write the “Write to Buffer Abort Reset” command sequence
to reset the device to read mode if Q1 goes high during a Write Buffer
Programming operation. The standard reset command will not function.
8-3-1. Hardware Reset
Driving the RESET# pin LOW for a period of Trp or more will return the device to Read mode. If
the device is in the process of a program or erase operation, the reset operation will take at most a
period of Tready1 before the device returns to Read mode.
When the RESET# pin is held at GND±0.3V, the device only consumes standby (Isbr) current.
However, the device draws larger current if the RESET# pin is held at a voltage greater than
GND+0.3V and less than or equal to Vil.
It is recommended to tie the system reset signal to the RESET# pin of the flash memory. This al-
lows the device to be reset with the system and puts it in a state where the system can immedi-
ately begin reading boot code from it.
Table 12. Hardware Reset
Parameter
Description
Speed
Unit
RESET at Embedded
Program / Erase Operation
tRP
25
us
RESET# Waveform Width
RESET at Read Operation
5
us
ns
tRH
Reset High Time Before Read
200
NOTE: Not 100% tested.
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MX29NS320/640/128E
Figure 9. Reset Timings
CE#, OE#
RESET#
tRH
tRP
8-3-2. Software Reset
Software reset is one of command in the command set (See Chapter 7. Command Definitions)
that is able to returns the device to read array memory after reset. It must be used under the
following conditions:
1. Exit from the Autoselect mode.
2. Erase or program cycle is not complete successfully that status bit Q5 goes high during write
procedure.
3. Return to erase-suspend-read mode if the device was previously in Erase Suspend mode.
4. Return to initial state after any aborted operations.
5. Exit read configuration registration mode.
6. Exit CFI mode.
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MULTIPLEXED, Burst Mode, Flash Memory
9. COMMON FLASH MEMORY INTERFACE (CFI) MODE
The device features CFI mode. Host system can retrieve the operating characteristics, structure
and vendor-specified information such as identifying information, memory size, byte/word
configuration, operating voltages and timing information of this device by CFI mode. If the system
writes the CFI Query command "98h", to address "55h", the device will enter the CFI Query Mode.
The system can read CFI information at the addresses given in Table 13.
Once user enters CFI query mode, users are allowed to issue reset command to exit CFI mode
and return to read array mode.
Table 13-1. CFI Mode: Identification Data Values
Address (h)
Description
Data (h)
(Word Mode)
10
11
12
13
14
15
16
17
18
19
1A
0051h
0052h
0059h
0002h
0000h
0040h
0000h
0000h
0000h
0000h
0000h
Query-unique ASCII string "QRY"
Primary vendor command set and control interface ID code
Address for primary algorithm extended query table
Alternate vendor command set and control interface ID code
Address for alternate algorithm extended query table
Table 13-2. CFI Mode: System Interface Data Values
Description
Address (h)
(Word Mode)
1Bh
Data (h)
VCC Min. (program/erase) D7–D4: volt, D3–D0: 100 millivolt
VCC Max. (program/erase) D7–D4: volt, D3–D0: 100 millivolt
ACC Min. voltage (00h = no ACC pin present) Refer to 4Dh
ACC Max. voltage (00h = no ACC pin present) Refer to 4Eh
Typical timeout per single word write 2N us
Typical timeout for Min. size buffer write 2N us (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for word write 2N times typical
Max. timeout for buffer write 2N times typical
0017h
0019h
0000h
0000h
0004h
0008h
0009h
0010h
0005h
0002h
0003h
0002h
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
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MX29NS320/640/128E
Table 13-3. CFI Mode: Device Geometry Data Values
Data
Description
Address
320E
640E
128E
Device Size = 2N byte
27h
28h
016h
0017h
0018h
0001h
Flash Device Interface description (refer to
CFI publication 100)
0000h
0005h
0000h
29h
2Ah
Max. number of bytes in multi-byte write = 2N
(00h = not supported)
2Bh
2Ch
Number of Erase Block Regions within device
0002h
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
003Eh
0001h
0040h
007Eh
007Eh
0002h
0080h
0000h
0000h
Erase Block Region 1 Information (refer to the
CFI specification or CFI publication 100)
0001h
0003h
0000h
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
0040h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
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MULTIPLEXED, Burst Mode, Flash Memory
Table 13-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values
Address (h)
Description
Data (h)
(Word Mode)
40h
41h
42h
43h
44h
0050h
0052h
0049h
0031h
0033h
Query - Primary extended table, unique ASCII
string, PRI
Major version number, ASCII
Minor version number, ASCII
Unlock recognizes address (Bits 1-0)
0= recognize, 1= don't recognize
45h
0014h
Process Technology (Bits 7-2) 0101b=110nm
Erase suspend (2= to both read and program)
Sector protect (N= # of sectors/group)
46h
47h
48h
0002h
0001h
Temporary sector unprotect (1=supported)
0000h
49h
4Ah
4Bh
Sector protect/Chip unprotect scheme
Simultaneous R/W operation (0=not supported)
Burst mode (0=not supported)
0008h
0000h
0001h
Page mode (0=not supported, 01 = 4 word page, 02
= 8 word page)
4Ch
4Dh
0000h
0095h
Minimum ACC(acceleration) supply (0= not
supported), [D7:D4] for volt, [D3:D0] for 100mV
Maximum ACC(acceleration) supply (0= not
supported), [D7:D4] for volt, [D3:D0] for 100mV
4Eh
00A5h
WP# Protection Flag
4Fh
50h
0003h
0001h
Program Suspend (0=not supported, 1=supported)
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MX29NS320/640/128E
10. ELECTRICAL CHARACTERISTICS
10-1. Absolute Maximum Stress Ratings
Surrounding Temperature with Bias
Storage Temperature
-65°C to +125°C
-65°C to +150°C
-0.5V to +2.0V
VCC
VI/O
ACC
-0.5V to +2.0V
-0.5V to +10.5V
-0.5V to Vcc +0.5V
200 mA
Voltage Range
The other pins.
Output Short Circuit Current (less than one second)
10-2. Operating Temperatures and Voltages
A
Commercial (C) Grade
Industrial (I) Grade
Surrounding Temperature (T )
0°C to +70°C
-40°C to +85°C
1.7~1.95V
A
Surrounding Temperature (T )
range
Full VCC
Supply Voltages
VCC
range
VI/O
= VCC
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is stress rating only and functional operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended period may affect reliability.
2. Specifications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods
up to 20ns, see Figures below.
4. Not 100% tested.
Maximum Positive Overshoot Waveform
Maximum Negative Overshoot Waveform
20ns
20ns
20ns
Vss
Vcc + 2.0V
Vss - 2.0V
Vcc
20ns
20ns
20ns
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MULTIPLEXED, Burst Mode, Flash Memory
10-3. Test Conditions
Figure 10. Test Setup
1.8V
2.7KΩ
DEVICE UNDER
TEST
CL
6.2KΩ
Testing Conditions:
•
•
•
•
Output Load Capacitance, CL : 1TTL gate, 10pF
Rise/Fall Times : 2ns
Input Pulse levels :0.0 ~ VI/O
I/O
In/Out reference levels :0.5V
Figure 11. Input Waveforms and Measurement Levels
VI/O
VI/O/2
Input
Measurement Level
Output
VI/O /2
0.0 V
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MX29NS320/640/128E
10-4. AC Characteristics
VCC Power-up and Power-down Sequencing
Once VCC attains its operating voltage, de-assertion of RESET# to VIH is permitted. VCC power-
up and power-down sequencing are not restricted. During the entire VCC power sequence,
RESET# needs to be asserted to VIL until the respective supplies reach their operating voltages.
Once VCC operating voltage has been achieved, RESET# to VIH is allowed to be de-asserted.
Output Disable Mode
Once OE# is input is at VIH, output from the device is disabled and placed in the state of high
impedance.
VCC Power-up
Parameter
Description
Test Setup
Speed
Unit
tVCS
VCC Setup Time
Min
1
ms
VCC Power-down
Symbol
Description
Test Setup
Speed
Unit
tVCS
VCC Setup Time
Max
200
us
NOTES:
1. VCC >+ VI/O - 100 mV
2. VCC ramp rate is >1 V/100 us
3. Not 100% tested.
Figure 12. VCC Power-up Diagram CLK Characterization
tVCS
VCC
VI/O
RESET#
Frequency
Parameter
Description
Unit
ns
66
15
83
12
108
9.26
tCLK
tCLKR
tCLKF
CLK Cycle
CLK Rise Time
CLK Fall Time
Min
Max
Min
3
7
2.5
5.5
1.9
4.2
ns
tCLKH/L
CLK High or Low Time
ns
NOTES:
1. Clock jitter of +/- 5% permitted.
2. Values guaranteed by characterization, not 100% tested in production.
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MULTIPLEXED, Burst Mode, Flash Memory
AC CHARACTERISTICS
ITEM
TYP
100us
10us
MAX
200us
20us
WEB high to release from deep power down mode
WEB high to deep power down mode
tRDP
tDP
NOTE: Not 100% tested.
Figure 13. Deep Power Down Mode Waveform
CEB
WEB
tDP
tRDP
ADD
XX
55
2AA
XX (don't care)
DATA
AA
55
B9
AB
Standby mode
Standby mode
Deep power down mode
Figure 14. CLK Characterization
t
CLK
t
t
CL
CH
CLK
t
t
CF
CR
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MX29NS320/640/128E
Table 15. Synchronous / Burst Read
Parameter
Description
Speed
Unit
tIACC
tBACC
tAVDS
tAVDH
tAVDO
tACS
tACH
tBDH
tCEZ
tOEZ
Initial Access Time
Burst Access Time Valid Clock to Output Delay
AVD# Setup Time to CLK
AVD# Hold Time from CLK
AVD# High to OE# Low
Address Setup Time to CLK
Address Hold Time from CLK
Data Hold Time from Next Clock Cycle
Chip Enable to High Z (Note)
Output Enable to High Z (Note)
CE# Setup Time to CLK
Ready access time from CLK
First CLK rising to RDY de-asserted
CLK low to AVD# low
Max
Max
Min
Min
Min
Min
Min
Min
Max
Max
Max
Max
Max
Min
Max
80
7
4
5
4
4
5
0
10
10
4
7
10
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCES
tRACC
tCLKR
tCLKS
tOECS
OE# Enable to First Output CLK Setup Time
8
NOTE: Not 100% tested.
Figure 15. Burst Mode Read
NOTE: Chip enters burst mode when 1st CLK rises.
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REV. 1.1, APR. 26, 2011
59
MULTIPLEXED, Burst Mode, Flash Memory
Table 16. Asynchronous Read
Parameter
Description
Speed
Unit
tCE
tACC
tAVDP
tAAVDS
tAAVDH
tOE
Access Time from CE# Low
Asynchronous Access Time
AVD# Low Time
Address Setup Time to Rising Edge of AVD
Address Hold Time from Rising Edge of AVD
Output Enable to Output Valid
Read
Max
Max
Min
Min
Min
Max
Min
80
80
7
3.5
3.2
15
0
ns
ns
ns
ns
ns
ns
ns
tOEH
Output Enable Hold Time
Toggle and Data#
Polling
Min
10
ns
tOEZ
tOAVD
tAVDO
tOEQX
tCR
Output Enable to High Z (See Note)
AVDB disable to OEB enable
OEB disable to AVDB enable
Output Enable to Data Low Z
CEB enable to RDY ready
Max
Min
Min
Min
Max
Max
10
10
10
15
10
10
ns
ns
ns
ns
ns
ns
tCEZ
CEB disable to RDY HiZ
NOTE: Not 100% tested.
Figure 16. Asynchronous Mode Read
REV. 1.1, APR. 26, 2011
P/N: PM1585
60
MX29NS320/640/128E
Table 17. Erase/Program Operations
Parameter
Description
Speed
Unit
tWC
tAS
tAH
tAVDP
tDS
tDH
tGHWL
tCS
tCH
tWP/tWRL
tWPH
tSR/W
tACC
tVPS
tVCS
tESL
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
AVD# Low Time
Data Setup Time
Data Hold Time
Read Recovery Time Before Write
CE# Setup Time to WE#
CE# Hold Time
Write Pulse Width
Write Pulse Width High
Min
Min
Min
Min
Min
Min
Typ
Typ
Typ
Typ
Typ
Min
Min
Min
Min
Max
Max
Min
Min
Min
45
4
6
7
25
0
0
8
0
30
20
0
500
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ms
us
us
us
us
ns
Latency Between Read and Write Operations
ACC Rise and Fall Time
ACC Setup Time (During Accelerated Programming)
VCC Setup Time
1
Erase Suspend Latency
25
25
400
25
10
tPSL
Program Suspend Latency
Erase Resume to Erase Suspend
Program Resume to Program Suspend
WEB disable to AVDB enable
tERS
tPRS
tWEA
NOTES:
1. Not 100% tested.
2. See the Erase and Programming Performance section for more information.
3. Does not include the preprogramming time.
P/N: PM1585
REV. 1.1, APR. 26, 2011
61
MULTIPLEXED, Burst Mode, Flash Memory
Figure 17. Program Operation Timings
Program Command Sequence (last two cycles)
Read Status Data
V
IH
CLK
AVD
V
IL
tAVDP
tAH
tAS
Amax–
A16
SA(55h)
SA(55h)
PA
PA
PA
PA
PA
Data
Polling
Data
Polling
A/Q15–
A/Q0
PA
PD
29h
tDS
tDH
CE#
t
WEA
tCH
OE#
WE
t
WP
tCS
tWPH
tWC
tVCS
VCC
NOTES:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. Amax–A16 are "Don’t care" during command sequence unlock cycles.
REV. 1.1, APR. 26, 2011
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MX29NS320/640/128E
Figure 18. Chip/Sector Erase Operations
Erase Command Sequence (last two cycles)
Read Status Data
tAS
AVD
tAH
tAVDP
SA
555h for
chip erase
VA
VA
VA
Amax–A16
10h for
chip erase
In
A/Q15
–
A/Q0
2AAh
Complete
55h
SA
30h
VA
Progress
tDS
tDH
CE#
OE#
tCH
tWP
WE#
tWHWH2
tCS
tWPH
tWC
V
IH
CLK
VCC
V
IL
tVCS
NOTES:
1. SA is the sector address for Sector Erase.
2. Address bits Amax–A16 are don’t cares during unlock cycles in the command sequence.
P/N: PM1585
REV. 1.1, APR. 26, 2011
63
MULTIPLEXED, Burst Mode, Flash Memory
Figure 19. Data# Polling Timings (During Embedded Algorithm)
High Z
High Z
Status Data
Status Data
A/Q15-A/Q0
VA
VA
t
ACC
A
–
A16
max
VA
VA
t
CEZ
t
CE
CE#
t
CH
AVD#
WE#
t
OEH
t
OEZ
t
OE
OE#
NOTES:
1. All status reads are asynchronous.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded
Algorithm operation is complete, and Data# Polling will output true data.
Figure 20. Toggle Bit Timings (During Embedded Algorithm)
AVD#
tCEZ
tCE
CE#
tOEZ
tCH
tOE
OE#
tOEH
WE#
tACC
High Z
VA
VA
VA
A
–A16
max
High Z
Status Data
Status Data
VA
A/Q15–A/Q0
NOTES:
1. All status reads are asynchronous.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded
Algorithm operation is complete, the toggle bits will stop toggling.
REV. 1.1, APR. 26, 2011
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MX29NS320/640/128E
Figure 21. 8-, 16-Word Linear Burst Address Wrap Around
Address wraps back to beginning of address group.
Initial Access
39
CLK
39
3A
3B
3C
3D
3E
3F
38
Address (hex)
D0
D1
D2
D3
D4
D5
D6
D7
A/Q15–A/Q0
V
IH
AVD#
OE#
V
V
IL
IH
(stays low)
(stays low)
V
IL
V
CE#
IL
NOTE: 8-word linear burst mode shown. 16-word linear burst read modes behave similarly.
D0 represents the first word of the linear burst.
Figure 22. Latency with Boundary Crossing
Address boundary occurs every 128 words, beginning at address
00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
C124
C125
7D
C126
7E
C127
7F
C127
7F
C128
80
C129
81
C130
82
C131
83
CLK
7C
Address (hex)
(stays high)
AVD#
RDY(1)
RDY(2)
tRACC
tRACC
latency
tRACC
tRACC
latency
Data
D124
D125
D126
D127
D128
D129
D130
OE#,
CE#
(stays low)
NOTES:
1. Cxx indicates the clock that triggers data Dxx on the outputs; for example, C60 triggers D60.
2. Please reference burst read related tables for details.
P/N: PM1585
REV. 1.1, APR. 26, 2011
65
MULTIPLEXED, Burst Mode, Flash Memory
10-5. Erase and Programming Performance
LIMITS
TYP. (1)
20
PARAMETER
UNITS
MIN.
MAX. (2)
Chip Programming Time (32Mb)
Chip Programming Time (64Mb)
Chip Programming Time (128Mb)
Chip Erase Time (32Mb)
sec
sec
sec
sec
sec
sec
sec
sec
us
40
80
32
75
150
300
5
7
360
Chip Erase Time (64Mb)
64
Chip Erase Time (128Mb)
Sector Erase Time (32KW)
Sector Erase Time (64KW)
Word Program Time
128
0.6
0.8
40
Total Write Buffer Time
300
150
100,000
9.4
us
ACC Total Write Buffer Time
Erase/Program Cycles
Effective Word Programming Time
us
cycles
us
NOTES:
1. Typical program and erase times assume the following conditions: 25°C, 1.8V VCC.
Programming specifications assume checkboard data pattern.
2. Maximum values are measured at VCC = 1.8 V, worst case temperature. Maximum
values are valid up to and including 100,000 program/erase cycles.
3. Erase/Program cycles comply with JEDEC JESD-47E & A117A standard.
4. Exclude 00h program before erase operation.
5. Not 100% tested.
Data Retention
PARAMETER
Condition
Min.
Max.
UNIT
Data retention
55˚C
20
years
Latch-up Characteristics
MIN.
-1.0V
MAX.
10.5V
Input Voltage voltage difference with GND on ACC pins
Input Voltage voltage difference with GND on all normal pins input
Vcc Current
-1.0V
1.5Vcc
+100mA
-100mA
All pins included except Vcc. Test conditions: Vcc = 1.8V, one pin per testing
Pin
Capacitance
Parameter Symbol
Parameter Description Test Setup
TYP
MAX
UNIT
CIN2
COUT
CIN
Control Pin Capacitance
Output Capacitance
Input Capacitance
VIN=0
VOUT=0
VIN=0
7.5
8.5
6
9
pF
pF
pF
12
7.5
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MX29NS320/640/128E
10-5-1. BGA Ball Capacitance
Parameter Symbol
Parameter Description Test Setup
Typ
Max
Unit
CIN
COUT
CIN2
Input Capacitance
Output Capacitance
Control Pin Capacitance
VIN = 0
VOUT = 0
VIN = 0
4.2
5.4
3.9
5.0
6.5
4.7
pF
pF
pF
NOTES:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
10-6. Low VCC Write Prohibit
The device refuses to accept any write command when Vcc is less than VLKO. This prevents data
from spuriously being altered during power-up, power-down, or temporary power interruptions. The
device automatically resets itself when Vcc is lower than VLKO and write cycles are ignored until
Vcc is greater than VLKO. The system must provide proper signals on control pins after Vcc rises
above VLKO to avoid unintentional program or erase operations.
10-6-1. Write Pulse "Glitch" Protection
CE#, WE#, OE# pulses shorter than 5ns are treated as glitches and will not be regarded as an
effective write cycle. On WE#, noise pulses of less than 5ns do not initiate a write cycle.
10-6-2. Logical Prohibit
A valid write cycle requires both CE# and WE# at Vil with OE# at Vih. While initiating a write cycle,
CE# and WE# must be a logical "0" while OE# is a logical "1". Write cycle is ignored when either
CE# at Vih, WE# at Vih, or OE# at Vil.
10-6-3. Power-up Sequence
Upon power-up, the device is placed in Read mode. Furthermore, program or erase operation will
begin only after successful completion of specified command sequences.
10-6-4. Power-up Write Prohibit
When WE#, CE# is held at Vil and OE# is held at Vih during power up, the device ignores the first
command on the rising edge of WE#.
10-6-5. Power Supply Decoupling
A 0.1uF capacitor should be connected between the Vcc and GND to reduce the noise effect.
P/N: PM1585
REV. 1.1, APR. 26, 2011
67
MULTIPLEXED, Burst Mode, Flash Memory
11. PACKAGE INFORMATION
REV. 1.1, APR. 26, 2011
P/N: PM1585
68
MX29NS320/640/128E
12. REVISION HISTORY
Revision No. Description
Page
Date
1.0
1. A note added to Table 2-2 Ordering Information. P8
2. A note added to Table 11. DC Characteristics. P49
MAR/23/2011
MAR/23/2011
MAR/23/2011
APR/26/2011
3. A note revised for CLK Characteristics.
P57
P8
1.1
1
. Modified: MX29NS320/640/128E have been
pre-released & in mass production.
2. Table 17. Parameters tPSP & tASP removed
P61
P/N: PM1585
REV. 1.1, APR. 26, 2011
69
MULTIPLEXED, Burst Mode, Flash Memory
Except for customized products which has been expressly identified in the applicable agreement,
Macronix's products are designed, developed, and/or manufactured for ordinary business,
industrial, personal, and/or household applications only, and not for use in any applications which
may, directly or indirectly, cause death, personal injury, or severe property damages. In the event
Macronix products are used in contradicted to their target usage above, the buyer shall take any
and all actions to ensure said Macronix's product qualified for its actual use in accordance with the
applicable laws and regulations; and Macronix as well as it’s suppliers and/or distributors shall be
released from any and all liability arisen therefrom.
Copyright© Macronix International Co., Ltd. 2011. All rights reserved.
Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, NBiit, Macronix
NBit, eLiteFlash, XtraROM, Phines, BE-SONOS, KSMC, Kingtech, MXSMIO, Macronix vEE are
trademarks or registered trademarks of Macronix International Co., Ltd. The names and brands
of other companies are for identification purposes only and may be claimed as the property of the
respective companies.
For more information, please visit Macronix’s Web site at http://www.macronix.com
MACRONIX INTERNATIONAL CO., LTD reserves the right to change product and specifications without notice.
REV. 1.1, APR. 26, 2011
P/N: PM1585
70
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