MX97102_技术文档

MX97102

ISDN S/T CONTROLLER

FEATURES

• Pin-to-Pin and Register-to-Register compatible with

Siemens 2186

• Programmable SDS1,SDS2

• D-channel access control

• Full duplex 2B+D ISDN S/T Transceiver according to

CCITT I.430

• LAPD(HDLC) support with FIFO(2x64) buffers

• Activation/Deactivation

• GCI digital interface

• Multiframing with S and Q bit access

• CPU access to B and IC channels

• Watchdog timer

• 3 types of 8-bit CPU interface

• Receive timing recovery with adaptively switched

thresholds

• Package types : P-LCC-44, P-LQFP-64

• E-channel Monitoring

GENERAL DESCRIPTIONS

MX97102 implements the 4-wire S/T interface used to

link voice/data terminals to an ISDN. It is designed for

the user site of the ISDN-basic access, two 64kbit/s B

channels and a 16kbit/s D channel.

multiframe S and Q channels, and D-channel access

and priority control for communicating with remote

equipments.

The Second is the microprocessor interface controller

which offers the registers compatible with Siemens

PSB2186, provides three types of microprocessor in-

terface, such as Motorola bus mode, Intel multiplexed

mode and Intel non-multiplexed mode.

MX97102 can be mainly divided into three portions ac-

cording to their interfaces. Except these three interface

functions, it also provides the LAPD controller which

handles the HDLC packets of the ISDN D-channel for

the associated microprocessor.

The last portion is the GCI interface controller which is

used to connect different voice/data application mod-

ules for local digital data exchangements.

The first, S/T interface controller, provides all electrical

and logical functions of the S/T interface, such as S/T

transceiver, activation/deactivation, timing recovery,

PIN CONFIGURATION

44-PLCC

64-PLQFP

6

1

44

40

39

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

NC

PA2

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

PRDN(DS)

PWRN(R/W)

PCSN

PALE

PSDS1

PSDS2

PRST

7

NC

PA0

PA1

PRDN(D5)

PWRN(R/W)

PCSN

PALE

PIDP1

PIDP0

PSX2

PSX1

VDD

PSDS1

PSDS2

PRST

PA5(EAW)

NC

PA5(EAW)

VSSD

PDCL

PIDP1

PIDP0

PSX2

12

34

MX97102

PFSC1

NC

VSSD

PDCL

PFSC1

NC

MX97102

PSX1

VDD

VSSD

ECHO

PA4

NC

VSSD

ECHO

PA4

NC

17

29

28

NC

18

23

NC

PA3

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MX97102

BLOCK DIAGRAM

Control and Data

Interface signals

PIDP0 PIDP1

S/T Interface

LAP-D

Transmitter

Multiframe

control

Activation/

Deactivation

GCI

Interface

B-channel

Switching

FIFO

Receiver

WATCH

DOG

RESET

SOURCE

DPLL

uP

Interface

7.68MHZ

OSC

ECHO

PDCL PFSC1

PINTN

microprocessor interface

PRST

FIGURE 2: FUNCTIONAL BLOCK DIAGRAM

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MX97102

PIN DESCRIPTION (44-PIN)

TABLE 1: MX97102 PIN DESCRIPTIONS

LQFP

PAD#

37

PLCC

PAD# PIN NAME I/O DESCRIPTION

41

42

43

44

1

PAD0(D0)

PAD1(D1)

PAD2(D2)

PAD3(D3)

PAD4(D4)

PAD5(D5)

PAD6(D6)

PAD7(D7)

PCSN

Multiplexed Bus Mode:Address/data bus from the CPU system to this devic

,and data between the CPU system and this device.

38

39

Non-Multiplexed Bus Mode:Data bus between the CPU system and this

40

I/O device.

41

42

2

43

3

44

4

27

37

38

I

ChipSelect:A logic "LOW" enable this device for a read/write operation.

Read/Write:A logic "HIGH" indicates a valid read operation by CPU.

A logic "LOW" indicates a valid write operation by CPU.(Motorola bus

mode) Write:A logic "LOW" indicates a write operation.(Intel bus mode)

Data Strobe:

28

PWRN(R/W) I

29

39

PRDN(DS)

I

The rising edge marks the end of a valid read or write operation (Motorola

bus mode).Read:A logic "LOW" indicates a read operation.(Intel bus mode)

Open Interrupt Request:The signal is a logic "LOW" when this device

requests an Drain interrupt. It is an open drain output.

8

23

14

PINTN

NC

1~5,

9,13,15 19,20

17~20 29,30

31~36

No used.

45~49

56,60

26

54

59

58

36

9

PALE

I

Address Latch Enable:A logic "HIGH" indicates an address on the address/

data bus(Multiplexed bus type only). ALE also selects the micro-processor

interface type (multiplexed or non-multiplexed).

PRST

PFSC1

PDCL

ECHO

I/O Reset:A logic "HIGH" on this input forces this device into reset state. The

minimum pulse length is four DCL-clock periods or four ms. If the terminal

specific functions are enabled,this device may also output a reset signal.

O(I) Frame Sync 1:Frame sync output. Logic "HIGH" during channel 0 on the

GCI interface.This pin becomes Input if Test Mode is programmed (register

ADF1).

13

12

16

O(I) Data Clock:Clock of frequency, 1536kHz output, equals to twice the GCI

data rate.

This pin becomes Input if Test Mode is programmed (register ADF1)

62

O

This pin output the Echo bit from the receiving line.

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MX97102

TABLE 1: MX97102 PIN DESCRIPTIONS(Continued)

LQFP

PAD#

PLCC

PAD#

PIN NAME I/O

DESCRIPTION

(non-multiplexed bus mode)

Address Bit 0

30

51

50

64

63

55

40

6

PA0

I

PA1

Address Bit 1

5

PA2

Address Bit 2

18

17

10

PA3

Address Bit 3

PA4

Address Bit 4

PA5(EAW)

Address Bit 5; External Awake, when terminal specific function en

abled, this pin is used as an external awake line.If a falling edge on this

input is detected, it generates an interrupt and a reset pulse.

Bit Clock:Clock of frequency 768kHz equal to the GCI data rate.

Serial Data Strobe 1&2 : programmable strobe signals, selecting either

one or two B or IC channels on GCI interface, is supplied via this line.

(registers ADF2,4)

7

22

PBCL

O

52,53

7,8

PSDS1,2

6,57,61 11, 15

21

VSSD

VSSA

-

Digital ground

10

21

12

11

24

31

26

25

-

Analog ground

VDD

-

Power supply (5V±5%)

PXTAL1

PXTAL2

I

Connection for crystal or external clock input.

O

Connection for external crystal. Left unconnected if external clock is

used.

14

16

22

23

24

25

27

28

32

33

34

35

PSR2

PSR1

I

S-Bus Receiver Input

PSX1

S-Bus Transmitter Output(positive)

S-Bus Transmitter Output(negative)

GCI-Data Port 0 (DD)

PSX2

O

PIDP0(DD)

PIDP1(DU) I/O

GCI-Data Port 1 (DU)

Open drain without internal pull-up resister or push-pull.

ABSOLUTE MAXIMUM RATINGS

TABLE 2: ABSOLUTE MAXIMUM RATINGS

RATING

VALUE

Maximum Supply Voltage (VDD)

DC Input Voltage on any pin

Storage Temperature Range

6V

-0.4Vto VDD+0.4V

-55°C to 150°C

Operating Free Air Temperature Range 0°C to 70°C

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MX97102

DC CHARACTERISTICS

TABLE 3: DC CHARACTERISTICS

Temperature from 0 to 70°C; VDD = 5V±5%, VSSA = 0V, VSSD = 0V

Symbol Parameter

Conditions

Min. Value Max. Value Unit

Remarks

VIL

L-input voltage

-0.4

2.0

0.8

V

VIH

H-input voltage

L-output voltage

VDD+0.4

0.45

All pins except

PSX1, PSX2,

PSR1, PSR2

VOL

VOL1

VOH

IOL= 2mA

L-output voltage (IDP0) IOL= 7mA

0.45

H-output voltage

IOH= -400uA

IOH= -100uA

2.4

VDD-0.75

V

ILI

Input leakage current

0<VIN<VDD to 0V

±10

All pins except

BCL, PSX1,2,

PSR1,2, PA0,

PA1, PA3, PA4

ILO

ILIPD

Output leakage current 0<VOUT<VDD to 0V

Input leakage current,

uA

V

internal pull-down

0<VIN<VDD to 0V

120

PA0, PA1, PA3,

PA4, BCL

VX

Absolute value of

RL = 50ohm

2.03

2.35

2.31

2.65

output pulse amplitude RL = 400ohm

(VSX2 - VSX1)

PSX1, PSX2

IX

Transmitter out-

put current

RL = 5.6ohm

7.5

13.4

mA

RX

Transmitter out-

put impedance

Inactive or during

binary one

10

0

kohm

ohm

during binary zero

RL = 50ohm

VSR1

VTR

Receiver output voltage IO < 5uA

2.35

225

2.63

375

V

PSR1, PSR2

Receiver threshold

Dependent on

voltage (VSR2 - VSR1) peak level

mV

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MX97102

AC CHARACTERICS

TABLE 4: CRYSTAL SPECIFICATION

PARAMETER

SYMBOL

f

Limit values

7.680

UNIT

MHz

ppm

pF

Frequency

Frequency calibration tolerance

Load capacitance

max. 100

max. 50

CL

Oscillator mode

fundamental

XTAL1 Clock Characteristics (external oscillator

input)

TABLE 5: CLOCK CHARACTERISTICS

Temperature from 0 to 70°C, VDD = 5V±5%

Parameter

Limit values

Inputs are driven to 2.4V for a logical "1" and to 0.4V

for a logical "0" . Timing measurements are made at

2.0V for a logical "1" and 0.8V for a logical "0". The AC-

testing output is loaded with a 150pF capacitor.

min.

1:2

max.

2:1

Duty cycle

TIMING WAVE FORM

MICROPROCESSOR INTERFACE TIMING----INTERL BUS MODE

tRR

tRI

RD x CS

AD0-AD7

tDF

tRD

Data

FIGURE 3(a) MICROPRCESSOR READ CYCLE IN INTEL BUS MODE

tAD

tAA

ALE

WR x CS or

RD x CS

tALS

tAL

tLA

AD0-AD7

Address

FIGURE 3(b) MICROPROCESSOR WRITE CYCLE IN INTEL BUS MODE

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MX97102

tAD

tAA

ALE

WR x CS or

RD x CS

tALS

tAL

tLA

AD0-AD7

Address

FIGURE 3(c) MULTIPLEXED ADDRESS TIMING IN INTEL BUS MODE

WR x CS or

RD x CS

tAS

tAH

A0-A5

Address

FIGURE 3(d) NON-MULTIPLEXED ADDRESS TIMING IN INTEL BUS MODE

MOTOROLA BUS MODE

ALE

tDSD

tRWD

tRI

tRR

CS x DS

D0-D7

tDF

tRD

Data

FIGURE 4(a) MICROPROCESSOR READ TIMING IN MOTOROLA BUS MODE

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MX97102

R/W

CS x DS

D0-D7

tDSD

tWI

tWW

tWD

tDW

Data

FIGURE 4(b) MICROPROCESSOR WRITE TIMING IN MOTOROLA BUS MODE

CS x DS

tAS

tAH

AD0-AD5

Address

FIGURE 4(c) NON-MULTIPLEXED ADDRESS TIMING IN MOTOROLA BUS MODE

TABLE 6: PARAMETERS FOR MICROPROCESSOR INTERFACE TIMING

PARAMETER

SYMBOL

Limit Value

UNIT

min.

40

10

0

max.

ALE pulse witdh

tAA

tAL

ns

Address setup time to ALE

Address hold time to ALE

Address latch setup time to WR, RD

Address setup time

tLA

tALS

tAS

tAH

tAD

tDSD

tRR

tRD

tDF

tRI

10

15

0

Address hold time

ALE guard time

DS delay after RW setup

RD pulse width

50

Data ouput delay from RD

Data float from RD

50

52

RD control interval

50

10

50

W pulse width

tWW

tDW

tWD

tWI

Data setup time to W, CS

Data hold time from W, CS

W control interval

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MX97102

Functional and Operational Description

ISDN ACCESS ARCHITECTURE

change and the S interface at the user premises. The

NT may be either an NT1 only or an NT1 together with

an NT2 connected via the T interface which is physi-

cally identical to the S interface.NT2 may include higher

level functions like multiplexing and switching as in a

PBX. Figure 5 illustrates the connections between the

user site to the public domain of central office.

MX97102 is designed especially for subscriber termi-

nal equipment with S/T interfaces, Four wire, two pairs

for transmission and receiption separately, are con-

nected to the NT equipment at the user site.Via the NT

equipment, subscribers could dial up to the wide-area

network with the traditional telephone line. The NT

serves a converter between the U interface at the ex-

ISDN

central office

TE(1)

U

T

S

TE(8)

TE(1)

LT-S

LT-T

NT1

LT

telephone

line

S

LT-S

TE(1)

TE(8)

PBX(NT2)

S

NT1

LT

Direct Subscriber Access

where - TE is an ISDN terminal

= MX97102

- LT-S is a subscriber line termination

- LT-T is a trunk line termination

- LT is a trunk line termination in the central office

FIGURE 5 : ISDN - BASIC SUBSCRIBER ACCESS ACHITECTURE

MX97102 is based on the ISDN basic access, 192kbit/

s, which consists of two circuit-switched 64 kbit/s B

channels and a message oriented 16kbit/s D channel

for packetized data, signaling and telemetry informa-

tion. The D channel is processed by the LAPD control-

ler contained in the MX97102 and routed via a parallel

CPU interface to the terminal processor.The high level

support of the LAPD protocol which is implemented by

the MX97102 allows the use of a low cost processor in

cost sensitive applications.

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MX97102

GCI CONNECTION

individual address. Two intercommunication channels

IC1 and IC2 allow a 2*64kbit/s transfer rate between

voice/data modules. Figure 6 shows one GCI connec-

tion, data module A uses D-channel for data transfer, a

voice processor is connected to a programmable digi-

tal processing codec filter via IC1 and a data encryp-

tion module to a data device via IC2. Meanwhile, B1 is

used for voice communication, B2 for data communi-

cation.

With the GCI interface, MX97102 could connect differ-

ent voice/data (V/D) application modules. Up to eight

D-channel components may be connected to the D and

C/I (Command/Indication) channels (TIC-bus).TIC-bus

arbitration is also implemented in MX97102.

Data transfers between the MX97102 and theV/D mod-

ules are done with the help of the GCI MONITOR chan-

nel protocol. Each V/D module can be accessed by an

D, C/I

B1

Data

Module

A

Speech

Processing

DSP Codec

Module

Data

Encryption

Data

Module

B

MX97102

Data

Module

Speech Modules

Data Modules

Microprocessor

FIGURE 6: EXAMPLES OF GCI CONNECTION

GCI FUNCTIONS

In terminal applications, the GCI constitutes a powerful backplane bus offering intercommunication and sophisti-

cated control capabilities for peripheral modules. GCI frame is composed of three channels ( see Figure 6-1 below):

- Channel 0 contains 144kbit/s (for 2B+D) plus MONITOR and command/indication

channels for the layer-1 device.

- Channel 1 contains two 64kbit/s intercommunication channels plus MONITOR and

command/indication channels for other GCI devices.

- Channel 2 is used for GCI-bus arbitration. Only the command/indication are used in channel 2.

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MX97102

125 us

FSC1

CH0

CH1

CH2

IPD0

(DD)

CIO

MR

B1

B2

MONO

D

IC1

IC2

MON1

CI1

MR

MX

S/G

A/B

IPD1

(DU)

CIO

MR

CI1

MR

BAC TAD

SDS1

IDP0,1:768 kbit/s

BCL :768 kHz bit clock

DCL :1536 kHz

FSC1 :8 kHz

SDS1 :8kHz programmable data strobe signal for

selecting one or both B/IC channel(s)

Figure 6-1 Frame structure of GCI

The GCI interface is operated in the“open drain” mode

in order to takes advantage of the bus capability. In this

case pull-up resisters (1kohm-5kohm) are required on

PIDP0 and PIDP1.

GCI has the 12-byte frame structure consisting of chan-

nels 0, 1 and 2. (see figure 6-1 above)

- IDP0 carries the 2B+D channels from the S/T inter-

face, and the MONITOR 0 and C/I 0 channels coming

from the S/T controller;

GCI OFF Function

- IDP1 carries the MONITOR 0 and C/I 0 channels to

the layer-1.

In GCI terminal mode (SPCR:SPM=0) the GCI inter-

face can be switched off for external devices via IOF bit

in ADF1 register. If IOF=1, the interface is switched off.

Thus, DCL, FSC1, IDP0/1 and BCL are high impedence.

Channel 1 of GCI interface is used for internal commu-

nication in terminal applications. Two cases have to be

distinguished, according to whether the MX97102 is op-

erated as a master device or as a slave device.

GCI Direction Control

For test applications, the direction of IDP0 (DD) and

IDP1 (DU) can be reversed during certain time-slots

within the GCI frame. This is performed via the IDC bit

in the SQXR register. For normal operation SQXR:IDC

should be set to “0”.

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MX97102

If IDC is set to "0" (master mode):

- IDP0 carries the MONITOR 1 and C/I 1 channels as output to peripheral (voice/data) devices;

- IDP0 also carries the IC channels as output to other devices, if programmed (CxC1-0=01 in register SPCR).

If IDC is set to "1" (slave mode):

- IDP1 carries the MONITOR 1 and C/I 1 channels as output to a master device;

- IDP0 carries the IC channels as output to other devices, if if programmed (CxC1-0=01 in register SPCR).

Figure 6-2shows the connection in a multifunctional terminal with the MX97102 as a master and a Voice/Data

module as a slave device.

S/T interface

GCI interface

IDP0

DD

DU

IDP0

IDP1

MON1, C/I1, IC1, IC2

2B+D, C/I0, S/G, TIC

Layer1

IDP1

IDP0

IDP1

IDP0

MX97102

as Master

Voice/Data

Module as slave

Layer2

Figure 6-2 GCI port connection and Data direction

If GCI-0 of MODE register is programmed, bit 5 of the last byte in channel 2 on IDP0 can be used to indicate the

S-bus state (stop/go bit) and bit 2 to 5 of the last byte are used for TIC-bus access arbitration.

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MX97102

Microprocessor Access to B and IC Channels

The microprocessor can access the B and IC channels

at the GCI interface by reading the B1CR/B2CR or by

reading and writing the C1R/C2R registers.Furthermore

it is possible to loop back the B channels from/to the S/

T interface or to loop back the IC channels from/to the

GCI interface without CPU intervention.

Four different functions are selected by the bits CxC1

and CxC0 in the SPCR register. Moreover, each chan-

nel, B channel 0/1 and IC channel 0/1, is programmed

individually. Table7-1 shows the configurations.

CxC1 CxC0 CxR Read

CxR Write

BxCR Read Output to GCI

Applications

0

1

ICx

-

Bx

-

Bx, ICx monitoring

ICx

Bx monitoring, ICx looping

from/to GCI

1

0

1

-

Bx

-

Bx

Bx access from/to S;

transmission of a constant

value in Bx channel to S

Bx looping from S;

Bx

transmission of a variable

pattern in Bx channels to S

Table 7-1 CPU access to B/IC channels by SPCR register

Note: x=1 for channel 1 or x=2 for channel 2

If the B-channel access is used for transferring 64kbit/

s voice/data information directly from the CPU port to

the ISDN S/T interface, the access can be synchro-

nized to the GCI interface by means of a synchronous

transfer interrupt programmed in the STCR register.

Same procedure could be used at ST1 and SC1 bits in

the STCR register. The only difference is ST1 gener-

ates an SIN interrupt at the middle of an GCI frame

instead of at the beginning.

When CPU accesses B channels, we can set the IOF

bit to switch off the GCI function.Thus, external B-chan-

nel sources (voice/data modules) can not disturb the

B-channel access on the GCI interface.

The general sequence of operations to access the B/

IC channels is:

1. Program synchronous interrupt (ST0) which causes

the device to generate an SIN interrupt at the begin-

ning of an GCI frame.

2. Read or write register (BxCR, CxR)

3. Set SC0 bit in the STCR to acknowledge SIN inter-

rupt.

repeat this sequence from 1 to 3.

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MX97102

S/T Interface

GCI Interface

IDP0(DD)

Layer-1

Functions

IDP1(DU)

Bx

ICx

BxCR

CxR

uP

FSC

IDP0

(DD)

B1 B2

B1CR

IC1 IC2

B1 B2

IC1 IC2

C2R

B2CR

C1R

IDP1

(DU)

B1 B2

IC1 IC2

B1 B2

IC1 IC2

ST0

SCO=1

Figure 6-3(a) SPCR : (CxC1, CxC0) = (0,0) Bx and ICx monitoring

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MX97102

S/T Interface

GCI Interface

IDP0(DD)

Layer-1

Functions

IDP1(DU)

Bx

ICx

BxCR

CxR

uP

FSC

IDP0

(DD)

B1 B2

B1CR

IC1 IC2

B1 B2

IC1 IC2

C2R

B2CR

C1R

IDP1

(DU)

B1 B2

IC1 IC2

B1 B2

IC1 IC2

ST0

SCO=1

Figure 6-3(b) SPCR : (CxC1, CxC0) = (0,0) Bx and ICx monitoring, ICx looping (SQXR : IDC = 0)

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MX97102

S/T Interface

GCI Interface

IDP0(DD)

Layer-1

Functions

IDP1(DU)

Bx

BxCR

CxR

uP

FSC

IDP0

(DD)

B1 B2

B1CR

IC1 IC2

B1 B2

IC1 IC2

C1R

C2R

B2CR

IDP1

(DU)

B1 B2

IC1 IC2

B1 B2

IC1 IC2

ST0

SCO=1

Figure 6-3(c) SPCR : (CxC1, CxC0) = (1,0) Bx access from/to S/T

transmission of constant value of S/T

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MX97102

S/T Interface

GCI Interface

IDP0(DD)

Layer-1

Functions

IDP1(DU)

Bx

CxR

uP

FSC

IDP0

(DD)

B1 B2

B1CR

IC1 IC2

B1 B2

IC1 IC2

B2CR

IDP1

(DU)

B1 B2

IC1 IC2

B1 B2

IC1 IC2

ST0

SCO=1

Figure 6-3(c) SPCR : (CxC1, CxC0) = (1,1) Bx looping from/to S/T

transmission of variable pattern of S/T

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MX97102

MONITOR channel handling

- For data exchange between two microcontroller sys-

tems attached to two different devices on one GCI

backplane. Use of the MONITOR channel avoids the

necessity of a dedicated serial communication path be-

tween the two systems. This simplifies the system de-

sign of terminal equipments.

The MONITOR channel protocol is a handshake proto-

col used for high speed information exchange between

the MX97102 and other devices.

The usage of the MONITOR channel protocol (see Fig-

ure 6-4 below):

- For programming and controlling devices attached to

the GCI. Examples of such devices are layer-1 trans-

ceivers (using MONITOR channel 0), and peripheral V/

D modules that do not need a parallel microcontroller

interface (by using MONITOR channel 1), such as the

Audio Ringing Codec Filter.

Note:MX97102 does not support the“MONITOR chan-

nel 0” operation. The implemented MONITOR handler

can however be used with external layer-1 transceivers

in case only the ICC part of this device is used (ADF1:

TEM, PFS).

Data Communication

(MONITOR1)

Control (MONITOR1)

V/D Module

MX97102

CPU

Figure 6-4 MONITOR channel applications in GCI interface

The MONITOR channel operates on an asynchronous basis. While data transfers on the bus take place synchro-

nized to frame sync, the flow of data is controlled by a handshake procedure using the MONITOR Channel Receive

(MR0 or MR1) and MONITOR Channel Transmit (MX0 or MX1) bits. For example: data is placed onto the MONI-

TOR channel and the MX bit is activated. The data will be transmitted repeatedly once per 8kHz frame until the

transfer is acknowledge via the MR bit.

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MX97102

The microprocessor may either enforce a "1" in MR,

MX by setting the control bit MRC1, MRC0 or MXC1,

MXC0 of the MOCR register to logic 0, or enable the

control of these bits internally by the MX97102 accord-

ing to the MONITOR channel protocol. Thus, before a

data exchange can begin, the control bit MRC(1,0) or

MXC(1,0) should be set to "1" by the microprocessor.

ence of valid MONITOR data (contents of MOX) in the

corresponding frame and remains active until an inac-

tive-to-active transition (MDA) of MR is received, indi-

cating the receiver has read the data off the bus. As a

result, the receiving device stores the MONITOR byte

in its MONITOR Receive register (MOR) and gener-

ates an MDR interrupt status.

There are two different cases, general case and maxi-

mum speed case, of the MONITOR handshake proto-

col. Bit MAX0(1) in the ADF3 register is set to "1" for

selecting the maximum speed case of MONITOR 0(1).

* As a general case (MAX=0):

MONITOR handshake procedure

- Idle

The MX and MR pair being held inactive for

two or more frames constitutes the channel being idle

in that direction.

The next byte is placed on the bus after the

inactive to active transmission of MR as early as the

next frame ( there is no limit to the maximum number of

frames). At the time that the second byte is transmit-

ted, MX is returned inactive for one frame time (MX

inactive for more than one frame time indicates an end

of message). In response to MX going active, MR will

be deactivated for one frame time (the MX inactive to

MR inactive delay can be any number of frame times)

after MOR is read.This procedure is repeated for each

additional byte. (see Figure6-5)

- Start of transmission

Before starting a transmission, the CPU should

verify that the transmitter is inactive, i.e. that a possible

previous transmission has been terminated. This is in-

dicated by a "0" in the MONITOR Channel Active (MAC)

status bit. After having written the MONITOR Data

Transmit (MOX) register, the microprocessor sets the

MONITOR Transmit Control bit (MXC) to "1". This en-

ables the MX bit to go active (0), indicating the pres-

MOX=2nd

MOX=nth

MXC=0

MOX=1st

MXE=1

MXC=1

MAC=1

MAC=0

MDA

1st byte

2nd byte

nth byte

Transmitter

EOM

MX

125us

MR

Receiver

RD MOR

MDR

RD MOR

MDR

MER

MRC=0

Figure 6-5 Timing chart of general case

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MX97102

As a maximum speed case (MAX=1):

MR will be reactivated one frame time after it is deacti-

vated, minimizing the delay between bytes (see Figure

6-6). Note that MR being held inactive for two or more

frame times indicates an abort is being signaled by the

receiver.

The transmitter can be designed for a higher

data throughput than is provided by the general case

described above. The transmitter can deactivate MX

and transmit new data one frame time after MR is de-

activated. In this way, the transmitter is anticipating that

1st byte

2nd byte

nth byte

Transmitter

EOM

MX

125us

MR

Receiver

* Transmitter anticipates the falling edge of the receiver's acknowledgment

*Signals from/to CPU are the same with general case(Figure6-8)

Figure 6-6 Timing chart of maximum speed case

- First byte reception

At the time the receiver sees the the first byte,

This "MDA interrupt - write data - MDR inter-

rupt - read data - MDA interrupt" handshake is repeated

as long as the transmitter has data to send.

-End of transmission (EOM)

indicated by the inactive-to-active transition of MX

(MDR), MR is by definition inactive. In response to the

activation of MX, microprocessor reads the MONITOR

Receive (MOR) register.When it is ready to accept data

(e.g. based on the value in MOR, which in a point-to-

multipoint application might be the address of the

destinating device), it sets the MR contol bit (MRC) to

"1" to enable the receiver to store succeeding MONI-

TOR channel bytes and acknowledge them according

to the MONITOR channel protocol. In addition, it en-

ables other MONITOR channel interrupts by setting

MONITOR Interrupt Enable (MRE) to "1".

When the last byte has been acknowledged by

the receiver, the microprocessor sets the MONITOR

Transmit Control bit (MXC) to "0". This enforces an in-

active "1" state in the MX bit. Two frames of MX inac-

tive signifies the end of a message. Thus, a MONITOR

Channel End of Receiption (MER) interrupt status is

generated by the receiver when the MX bit is received

in the inactive state in two consecutive frames. As a

result, the microprocessor sets the MRC to 0, which in

turn enforces an inactive state in the MR bit.This marks

the end of the transmission, making the MONITOR

Channel Active (MAC) bit return to “0”.

- Subsequent reception

Data is received from the bus on each falling

edge of MX, and a MDR is generated. Note that the

data may actually be valid at the time that MX went

inactive, one frame time prior to going active. MR is

deactivated after the data is read and reactivated one

frame time later. The transmitter will detect MR going

inactive and anticipate its reactivation one frame time

later. The transmission of the next data byte will begin

at the same time that MR is going active.

- Abort

During a transmission process, it is possible

for the receiver to ask a transmission to be aborted by

sending an inactive MR bit value in two consecutive

frames. This is effected by the microprocessor writing

the MRC bit to "0". An aborted transmission is indi-

cated by a MONITOR Channel Data Abort (MAB) in-

terrupt status at the transmitter.

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MX97102

C/I-Channel Handling & TIC-Bus Access

The command/indication channel carries real-time sta-

tus information between the MX97102 and another de-

vice connected to the GCI.

- One C/I channel (called C/I 0) conveys the commands

and indications between the layer-1 and the layer-2 parts

of the MX97102. It can be accessed by an external

layer-2 device e.g. to control the layer-1 activation/de-

activation procedures. C/I 0 channel access may be

arbitrated via the TIC bus access protocol. In this case

the arbitration is done in C/I channel 2.

The C/I 0 code is four bits long, could be read from

CIR0 (layer-1 to layer-2) and write to CIX0 (layer-2 to

layer-1).

In the receive direction, the code from layer-1 is con-

tinuously monitored, with an interrupt being generated

any time a change occurs (CISQ). A new code must be

found in two consecutive GCI frames to be considered

valid and to trigger a C/I code change interrupt status

(double last look criterion).

- A second C/I channel (called C/I 1) can be used to

convey real time status information between the

MX97102 and various non-layer-1 peripheral devices

such as ARCOFI. The channel consists of six bits in

each direction.

The C/I 1 channel is accessed via registers CIR1 and

CIX1. A change in the received C/I 1 code is indicated

by an interrupt status without double last look criterion.

An access request to the TIC bus may either be gener-

ated by software (CPU access to the C/I channel) or by

the MX97102 itself (transmission of an HDLC frame).

A software access request to the bus is effected by

setting the BAC bit (CIX0 register) to “1”.

In the case of an access request, the MX97102 checks

the Bus Accessed-bit (bit 5 of IDP1 last octet of CH2,

see Figure6-1) for the status “ bus free”, which is indi-

cated by a logical “1”. If the bus is free, the MX97102

transmits its individual TIC-bus address programmed

in the STCR register. The TIC bus is occupied by the

device which sends is address error-free. If more than

one device attempt to seize the bus simultaneously,

the one with the lowest address value wins.

When the TIC bus is seized by the MX97102, the BAC-

bit on IDP1 is “0” until the access request is withdrawn.

After a successful bus access, the MX97102 is auto-

matically set into lower priority class, that is, a new bus

access cannot be performed until the status “ bus free”

is indicated in two successive frames.

If none of the devices connected to the GCI interface

request access to the D and C/I channels, the TIC-bus

address 7 will be present.The device with this address

will therefore have access, by default, to the D and C/I

channels. The availability of the S/T interface D chan-

nel is indicated in bit5 “Stop/Go” (S/G=1: stop, S/G=0:

go) of the IDP0 last octet of C/I channel (Figure6-1).

TheTIC-bus arbitration mechanism implemented in the

last octet of GCI channel 2 of the GCI allows the ac-

cess of external communication controller (up to 7) to

the layer-1 functions provided in the MX97102 and to

the D channel. To this effect the outputs of the control-

lers are wired-and connected to pin IDP1.The inputs of

the ICCs are connected to pin IDP0. External pull-up

resistors on IDP0/1 are required.The arbitration mecha-

nism must be activated by setting MODE:DIM2-0=001.

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MX97102

S/T interface

Line transceiver functions for the S/Y interface follow the electrical specifications of CCITT I.430. According to this

standard, pseudo-ternary encoding with 100% pulse width is used on the S/T interface. For both receive and

transmit direction, a 2:1 transformer is used to connect the MX97102 transceiver to the 4 wire S/T interface.

+5V

2 : 1

PSX1

PSX2

PSR1

PSR2

VDD

Transmit Pair

10uf

MX97102

2 : 1

VSSD

VSSA

Receive Pair

Protection Circuits

GND

FIGURE 6-7: MX97102 EXTERNAL S-INTERFACE CIRCUITRY

- Pre-Filter Compensation

To compensate for the extra delay introduced into the received signal by a filter, the sampling of the receive

signal can be delayed by programming bits TEM and PFS in the ADF1 register as shown below.

TEM

PFS

0

1

0

1

0

no delay

delay 650ns

advance 390ns

test mode

The receiver is designed as a threshold detector with adaptively switched threshold levels. Pin PSR1 delivers 2.5V

as an output, which is the virtual ground of the input signal on pin PSR2.The detector controls the switching of the

receiver between two sensitivity levels (see Figure6-8).

VSR2-

VSR1

VSR2-VSR1

+375mv

0v

logical 0

|Vmax| > 1v

in two consecutive frames

+225mv

0v

logical 1

logical 0

2

1

-225mv

750mv<|Vmax|<1v

-375mv

Vmax<750mv or

Vmax>750mv

state 1

state 2

Vtr1, Vtr2:threshold voltages of the receiver threshold detector

Vmax:maximum value of VSR2-VSR1 during one frame

High sensitivity

with Vtr1=+225mV

Low sensitivity

with Vtr2=+375mV

Figure 6-8 State diagram of the adaptive receiver

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MX97102

Activation/Deactivation

An incorporated finite state machine controls ISDN layer-1 activation/deactivation according to CCITT I.430. Fig-

ure6-9 shows the state diagrams. Table7-2 and Table7-3 indicate the command and indication code descriptions.

OUT

IN

IOM2

Ind.

iX

DID

F3 Power Down

i0

Cmd.

DIU

TIM

State

RST

iR

i0

S

i0

ARU

DIU

PU

F4 Pend. Act.

ARU

PU

F3 Power Up

i0

TIM

ARU

i0

i1

i0

RSYD

X

F5 Unsynchron.

i0

X

, X

i4

i2

TIM

i0.DIU

Uncond. States

ARD

X

i0

F6 Synchron.

i3 i2

i2

DIU

ARU

F3 Pend. Deact.

i0

X

i4

RSYD

X

DR

i0

TIM

F8 Lost frame

i0

i2

i4

AID

F7 Activated

i3

ARU

i0

i4

i0

X : unconditional command (ARL, RS, SSZ, SCZ)

Figure 6-9(a) State diagram

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MX97102

PU

Loop 3 closed

i3

TI

EI

Reset State

i0

ARL

SCZ

RS

Test Mode

Continuous Pulse

ARL

SCZ

RS

ic

*

X

i3

TI

ATI

TIS

ARL

SSZ

is:Single pulse, 4kHz

ic:Test pulse, 96kHz

X:Forcing commands

Test Mode

Single Pulse

Loop 3 Act.

i3

SSZ

is

*

i0

i0/

X

Figure 6-9(b) State diagram : unconditional transitions

Command (upstream)

Timing

Abbr. Code

Reamrks

TIM

RS

0000

0001

Activation of all output clocks is requested

(X)

Reset

Send continuous zeros

Send single zeros

Activate request

set priority 8

SCZ 0100

SSZ 0010

AR8 1000

Transmission of pseudo-ternary pulses at 96kHz frequency (X)

Transmission of pseudo-ternary pulses at 2kHz (X)

Activation command, set D-channel priority to 8

Activate request

set priority 10

AR10 1001

ARL 1010

Activation command, set D-channel priority to 10

Activate request loop

Deactivate indication

upstream

Activation of test loop 3 (X)

DIU

1111

GCI-interface clocks can be disabled

Table 7-2 C/I command code descriptions

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MX97102

Note: When in the activated state (AI8/AI10) the 2B+D channels are only transferred from the GCI to the S/T

interface if an “Activate Request” command is written to the CIX0 register.

Indication

Abbr. Code

Reamrks

Power up

PU

DR

EI

0111

0000

0110

GCI clocking is provided

Deactivate request

Error indication

Level detected

Deactivation request by S interface

Either : (pin PRST = 1 and bit CFS = 0) or RS

Signal received, receiver not synchronous

Info 2 received

RSYD 0100

ARD 1000

Activate request

downstream

Test indication

TI

1010

1011

1100

Test loop 3 activated or continuous zeros transmitted

Level detected during test loop

Awake test indication

Activate indication

with priority class 8

Activate indication

Deactivate indication

downstream

ATI

AI8

Info 4 received, D-channel priority is 8 or 9

AII0

DID

1101

1111

Info 4 received, D-channel priority is 10 or 11

Clocks will be disabled in MX97102, quiescent state

Single zero transmitted

TIS

0101

Send single zeros at 2kHz frequency

Table 7-3 C/I command code descriptions

Level Detection Power Down

In power down state, only an analog level detector is active. All clocks, including the GCI interface, are stopped.The

data lines are "high" whereas the clocks are "low".

An activation initiated from the exchange side (Info2 in S bus detected) will have the consequence that a clock

signal is provided automatically.

From the terminal side an activation must be started by setting and resetting the SPU bit in the SPCR register.

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MX97102

D-channel Access

- When synchronism is achieved, the four received S

bits in frames 1, 6, 11, 16 are stored as SQR1 to SQR4

in the SQRR register if the complete M bit multiframe

pattern was correctly received in the corresponding

multiframe. A change in any of the received four bits is

indicated by an interrupt (CISQ in ISTA and SQC in

CIR0).

The D-channel access procedure according to CCITT

I.430 including priority management is fully implemented

in the MX97102. By programmed the DIM2-0 (MODE

register) to 001 or 011, stop/go bit is evaluated for D-

channel access handling, that is, a collision is detected

if the corresponding echo-bit value is different from the

transmitted D-bit value. When this occurs, D-channel

transmission is immediately stopped, and the echo

channel is monitored to enable a subsequent D-chan-

nel access to be attempted.

- When an M bit is observed to have a value different

from that expected, the synchronism is considered lost.

The SQR bits are not updated until synchronism is re-

gained.The synchronization state is constantly indicated

by the SYN bit in the SQRR register.

The priority class (priority 8 or priority 10) is selected

by transferring the appropriate activation command via

the command/indication (C/I) channel of the GCI inter-

face to the layer-1 controller.

- When synchronism with the received multiframe is

achieved, the four bits SQX1 to SQX4 stored in the

SQXR register are transmitted ad the four Q bit (FA-bit

position) in frames 1, 6, 11, 16 respectively (starting

from frame number one). Otherwise the bit transmitted

a mirror of the received FA-bit. At loss of synchronism

(mismatch in M bit) the mirroring is resumed starting

with the next FA-bit.

6.3.10 S- and Q- channel access

Access to the received/transmitted S- or Q- channel is

provided via registers. As specified by CCITT I.430,

the Q bit is transmited from TE to NT in the position

normally occupied by the auxiliary framing bit (FA) in

one frame out of 5, whereas the S bit is transmitted

from NT toTE in a spare bit (S).The functions provided

by the MX97102 are:

-

The S/T multiframe synchronization can be dis-

abled in the STAR register (MULT bit).

- Synchronization to the received 20 frame multiframe

by means of the received M bit pattern. Synchronism is

achieved when the M bit has been correctly received

during 20 consecutive frames starting from frame num-

ber 1 (Table7-4).

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MX97102

Frame Number NT-to-TE FA-Bit position NT-to-TE M Bit NT-to-TE S Bit TE-to-NT FA-Bit position

1

ONE

S1

Q1

2

ZERO

ONE

ZERO

ONE

ZERO

S2

ZERO

Q1

3

4

5

6

7

ZERO

ONE

ZERO

S3

ZERO

Q3

8

9

10

11

12

13

14

15

16

17

18

19

20

1

ZERO

ONE

ZERO

S4

ZERO

Q4

ZERO

ONE

ZERO

S1

ZERO

Q1

2

ZERO

etc.

Table 7-4 S- and Q-channel Structure

Terminal Specific Functions

External Awake Function

The MX97102 provides the following optional functions

by setting bit TSF (STCR register) to “1”. When termi-

nal specific functions are activated (TSF=1), bit RSS

(CIX0 register) is programmed for selecting Watchdog

Function (RSS=1) or External Awake Function (RSS=0).

Deactivating the terminal specific functions is only pos-

sible with a hardware reset.

A 16ms reset signal is generated by either a falling edge

on the EAW line (subscriber awake) or a C/I code

change (exchange awake). A corresponding interrupt

status (SAW or CISQ) is also generated. Moreover, It

forces the IDP1 line of the GCI interface to zero. The

consequence of this is that the GCI interface and the

MX97102 leaves the power-down state.

Watchdog Function (TSF=1, RSS=1):

During every time period of 128ms the processor has

to program the WTC1 and WTC2 bits in the sequence,

(WTC1, WTC2) = (1, 0) then (0, 1), to reset and restart

the watchdog timer. Otherwise, the timer expires and a

WOV interrupt (EXIR) together with a 125ms reset pulse

is generated.

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MX97102

Test Functions

an intelligent FIFO controller permit flexible transfer of

protocol data units to and from the CPU system.

The MX97102 provides several test and diagnostic func-

tions which can be grouped ad follows:

- digital loop via TLP (Test Loop, SPCR register) com-

mand bit: IDP1 is internally connected with IDP0, out-

put from layer 1 (S/T) on IDP0 is ignored; this is used

for testing MX97102 functionality excluding layer 1;

The HDLC controller can be programmed to operate in

various modes, which are different in the treatment of

the HDLC frame in receive direction. Thus, the receive

data flow and the address recognition features can be

programmed in a flexible way.

- test of layer-2 functions while disabling all layer-1 func-

tions and pins associated with them (including clock-

ing), via bits TEM and PFS (Test Mode in ADF1 regis-

ter); the MX97102 is then fully compatible to the ICC

(Siemens PEB2070) seen at the IOM2 interface.

In the auto mode the MX97102 handles elements of

procedure of the LAPD (S and I frames) according to

CCITT I.441 fully autonomously. For the address rec-

ognition the MX97102 contains four programmable reg-

isters for individual SAPI and TEI values SAP1-2 and

TEI1-2, plus two fixed values for "group" SAPI and TEI,

SAPG and TEIG.

- loop at the analog end of the S interface;

Test loop 3 is activated with the C/I-channel command

Activate Request Loop (ARL). An S interface is not re-

quired since INFO3 is looped back to the receiver.When

the receiver has synchronized itself to this signal, the

message "Test Indication" ( or "Awake Test Indication")

is delivered in the C/I channel.

There are 5 different operating modes which can be

set via the MODE register.

-Auto-mode (MDS2, MDS1 = 00)

Characteristics:

* Full address recognition (1 or 2 bytes)

* Normal (mod 8) or extended (mod 128) con-

trol field format

* Automatic processing of numbered frames of

an HDLC procedure

In the test loop mode the S-interface awake detector is

enabled i.e. if a level is detected (e.g. Info2 /Info4) this

will be reported by the Awake Test Indication (ATI).The

loop function is not effected by this condition and the

internally generated 192 kHz line clock does not de-

pend on the signal received at the S interface.

If a 2-byte address field is selected, the high address

byte is compared with the fixed hex value FE or FC

(group address) ad well ad with two individually pro-

grammable values in SAP1 and SAP2 registers. Ac-

cording to the ISDN LAPD protocol, bit 1 of the high

byte address will be interpreted as command/response

bit (C/R) dependent on the setting of the CRI bit in SAP1,

and will be excluded from the address comparison.Simi-

larly, the low address byte is compared with the fixed

hex value FF (group TEI) and two compare values pro-

grammed in special registers (TEI1, TEI2). A valid ad-

dress will be recognized in case the high and low byte

of the address field match one of the compare values.

The MX97102 can be called (addressed) with the fol-

lowing address combination:

Layer-2 Functions for the ISDN-Basic Access

LAPD, layer 2 of the D-channel protocol (CCITT I.441)

includes functions for:

- Provision of one or more data link connections on a D

channel (multiple LAP).Discrimination between the data

link connections is performed by means of a data link

connection identifier (DLCI = SAPI + TEI).

- HDLC framing

- Application of a balanced class of procedure in point-

multipoint configuration.

* SAP1/TEI1

* SAP1/FF (hex value)

For the support of LAPD the MX97102 contains an

HDLC transceiver which is responsible for flag genera-

tion/recognition, bit stuffing mechanism, CRC check and

address recognition.A powerful FIFO structure with two

64-byte pools for transmit and receive directions and

* SAP2/ TEI2

* SAP2/FF (hex value)

* FE or FC (hex value)/TEI1

* FE or FC (hex value)/TEI2

* FE or FC (hex value)/FF (hex value)

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MX97102

Only the logical connection identified through the ad-

dress combination SAP1, TEI1 will be processed in the

auto mode, all others are handled as in the non-auto

mode.The logical connection handled in the auto-mode

must have a window size 1 between transmitted and

acknowledged frames.HDLC frames with address fields

that do not match with any of the address combina-

tions, are ignored by the MX97102. In case of a 1-byte

address, TEI1 and TEI2 will be used as compare regis-

ters. According to the X.25 LAPB protocol, the value in

TEI1 will be interpreted ad command and the value in

TEI2 as response. The control field is stored in the

RHCR register and the I field in the RFIFO. Additional

information is available in the RSTA.

- Transparent mode 3 (MDS2, MDS1, MDS0 = 111)

Characteristic: SAPI recognition

A comparison is performed on the first byte after the

opening flag with SAP1, SAP2 and group SAPI (FE/FC

hex value). In the case of match, all the following bytes

are stored in the RFIFO. Additional information is avail-

able in the RSTA.

Reception of Frames

A 2*32 byte FIFO buffer (receive pools) is provided in

the receive direction. The control of the data transfer

between the CPU and the MX97102 is handled via in-

terrupts.

- Non-auto mode (MDS2, MDS1 = 01)

Characteristic:

- RPF (Receive Pool Full) interrupt, indicating that a

32-byte block of data can be read from the RFIFO and

the received message is not yet complete.

* Full address recognition (1 or 2 bytes)

* Arbitrary window size

- RME (Receive Message End) interrupt, indicating that

the reception of one message is completed, i.e. either

one message * 32 bytes or the last part of a message >

32bytes is stored in the RFIFO.

All frames with valid addresses (address recognition

identical to auto mode) are accepted and the bytes fol-

lowing the address are transferred to the CPU via RHCR

and RFIFO. Additional information is available in the

RSTA.

The organization of the RFIFO is such that up to two

short (* 32 bytes), successive messages, with all addi-

tional information can be stored (see Figure6-13).

- Transparent mode 1 (MDS2, MDS1, MDS0 = 101)

Characteristic: TEI recognition

0

A comparison is performed only on the second byte

after the opening flag, with TEI1, TEI2 and group TEI

(FF hex value), and the rest of the frame in the RFIFO.

Additional information is available in the RSTA.

Receive

Message 1

(< 32 bytes)

- Transparent mode 2 (MDS2, MDS1, MDS0 = 110)

Characteristic: No address recognition

RME

31

0

Every received frame is stored in the RFIFO (first byte

after opening flag to CRC field). Additional information

is available in the RSTA.

Receive

Message 2

(< 32 bytes)

RME

31

Figure 6-10 Contents of RFIFO (short message)

P/N:PM0473

REV. 2.5, SEP. 05, 2000

29

MX97102

Depending on the message transfer mode the address and control fields of received frames are processed and

stored in the Receive FIFO or in special registers as depicted in Figure 6-11.

Address

lligh

Address

Low

Control

Flag

Information

Flag

CRC

Auto-Mode

(U-and I-Frames)

SAP1,SAP2

FE, FC

(Note 1)

TEI1, TEI2

FF

(Note 2)

RHCR

RSTA

RFIFO

(Note 3)

Non-Auto

Mode

TEI1, TEI2

FF

(Note 2)

SAP1,SAP2

FE, FC

(Note 1)

RSTA

RHCR

(Note 4)

Transparent

Mode 1

TEI1, TEI2

FF

RHCR

SAPR

(Note 4)

Transparent

Mode 2

RSTA

RFIFO

Transparent

Mode 3

SAP1,SAP2

FE, FC

RFIFO

Symbol Descriptions

:Checked automatically by MX97102

:Compared with Register or Fixed Value

:Stored Information Register or RFIFO

Figure 6-11 Receive Data Flow

Note 1: Only if a 2-byte address field is defined (MDS0=1 in MODE register).

Note 2: Comparison with Group TEI is only made if a 2-byte address field is defined (MDS0=1).

Note 3: In the case of an extended, modulo 128 control field format (MCS=1 in SAP2 register) the control field is

stored in the RHCR in compressed form (I frames).

Note 4: In the case of extended control field, only the first byte is stored in the RHCR, the second in the RFIFO.

P/N:PM0473

REV. 2.5, SEP. 05, 2000

30

MX97102

When 32 bytes of a message longer than that are stored

in the RFIFO, the CPU is prompted to read out the

data by an RPF interrupt. The CPU must handle this

interrupt before more than 32 additional bytes are re-

ceived, which would cause a "data overflow", This cor-

responds to a maximum CPU reaction time of 16ms

(data rate 16 kbit/s).

message in "frame overflow" (EXIR: RFO). The gener-

ated interrupts are inserted together with all additional

information into a queue to be individually passed to

the CPU.

After an RPF or RME interrupt has been processed,

i.e. the received data has been read from the RFIFO,

this must be explicitly acknowledged by the CPU issu-

ing an RMC (Receive Message Complete) command.

The MX97102 can then release the associated FIFO

pool for new data. If there is an additional interrupt in

the queue it will be generated after the RMC

acknowledgement.

After a remaining block of less than or equal to 16 bytes

has been stored, it is possible to store the first 16 bytes

of a new message (see Figure6-12). The internal

memory is now full. The arrival of additional bytes will

result in "data overflow" (RSTA: RDO) and a third new

RFIFO

0

Receive

Message 1

(< 48 bytes)

Long

Message

31

RPF

0

15

RME

16

Message 2

(< 32 bytes)

31

RPF

RME

Figure 6-12 Contents of the RFIFO (long messages)

Transmission of Frames

Two different frames types can be transmit-

ted :Transparent frame (command: XTF) or

I frames (command: XIF) as shown in Fig-

ure6-16. For transparent frames, the whole

frame including address and control field

must be written to the XFIFO.

A 2*32 byte FIFO buffer (transmit pools) is provided in

the transmit direction.If the transmit pool is ready (which

is true after an XPR interrupt or if the XFW bit in STAR

is set), the CPU can write a data block of up to 32

bytes to the transmit FIFO. After this, data transmis-

sion can be initiated by command.

P/N:PM0473

REV. 2.5, SEP. 05, 2000

31

MX97102

Address

XAD1

Control

CRC

Flag

Information

XFIFO

Flag

HDLC Frame

Transmit I-Frame

(XIF)

CRC

Flag

Auto Mode, 8-Bit Addr.

Transmit I-Frame

(XIF)

Auto Mode, 16-Bit Addr.

Control

CRC

XFIFO

Flag

XAD1

XAD2

Flag

Transmit Transparent

Frame(XTF)

All Modes

Symbol Descriptions

:Generated automatically by MX97102

:Written initially by CPU (Info Register)

:Loaded (repeatedly) by CPU upon MX97102 request (XPR interrupt)

Note: Length of Control Field is 8 or 16 Bit

Figure 6-13 Transmit Data Flow

P/N:PM0473

REV. 2.5, SEP. 05, 2000

32

MX97102

If a 2-byte address field has been selected, the

MX97102 takes the contents of the XAD1 register to

build the high byte of the address field, and the XAD2

register to build to low byte of the address field. Addi-

tionally the C/R bit (bit 1of the high byte address, as

defined by LAPD protocol ) is set to "1" or "0" depen-

dent on whether the frame is a command or a response.

In the case of a 1 byte address, the MX97102 takes

either the XAD1 or XAD2 register to differentiate be-

tween command or response frame (as defined by X.25

LAPB).

causes an XPR interrupt.

After an end of message indication from the CPU

(CMDR: XME command), the termination of the trans-

mission operation is indicated differently, depending on

the selected message transfer mode and the transmit-

ted frame type.

If the MX97102 is operating in the auto mode, the win-

dow size is limited to"1";therefore an acknowledgement

may be provided either by a received S or I frame with

corresponding receive sequence number. If no

acknowledgement is received within a certain time (pro-

grammable), the MX97102 requests an

acknowledgement by sending an S frame with the poll

bit set (P=1) (RR or RNR). If no response is received

again, this process is repeated in total N2 times (retry

count, programmable via TIMR register).

The control field is also generated by the MX97102 in-

cluding the receive and send sequence number and

the poll/final (P/F) bit. For this purpose, the MX97102

internally manages send and receive sequence num-

ber counters.

In the auto-mode, S frames are sent autonomously by

the MX97102. The transmission of U frames, however,

must be done by the CPU. U frames must be sent as

transparent frames (CMDR:XTF), i.e.address and con-

trol field must be defined by the CPU. Once the data

transmission has been initiated by command (CMDR:

XTF or XIF), the data transfer between CPU and the

MX97102 is controlled by interrupts.

The termination of the transmission operation may be

indicated either with:

- XPR interrupt, if a positive acknowledgement has been

received,

- XMR interrupt, if a negative acknowledgement had

been received, i.e. the transmitted message must be

repeated (XMR = Transmit Message Repeat),

- TIN interrupt, if no acknowledgement has been re-

ceived at all after N2 times the expiration of the time

period t1 (TIN = Timer INterrupt, XPR interrupt is is-

sued additionally).

The MX97102 repeatedly requests another data packet

or block by means of an ISTA:XPR interrupt, every time

no more than 32 bytes are stored in the XFIFO. The

processor can then write further data to the XFIFO and

enable the continuation of frame transmission by issu-

ing an XIT/XTF command. If the data block which has

been written last to the XFIFO completes the current

frame, this must be indicated additionally by setting the

XME (Transmit Message End) command bit. The

MX97102 then terminates the frame properly by ap-

pending the CRC and closing flag.

Note:Prerequisite for sending I frames in the auto-mode

(XIF) is that the internal operational mode of the timer

has been selected in the MODE register (TMD bit = 1).

The transparent transmission of frames (XTF command)

is possible in all message transfer mode.The success-

ful termination of a transparent transmission is indicated

by an XPR interrupt.

If the CPU fails to respond to an XPR interrupt within

the given reaction time, a data underrun condition oc-

curs (XFIFO holds no further valid data). In this case,

the MX97102 automatically aborts the current frame

by sending seven consecutive "ones" (ABORT se-

quence). And the CPU is informed about this via an

XDU (Transmit Data Underrun) interrupt. It is also pos-

sible to abort a message by software by issuing a

CMDR:XRES (Transmitter Reset) command, which

In all cases, collisions which occur on the S-Bus (D

channel) before the first XFIFO pool has been com-

pletely transmitted and released are treated without

CPU interaction.The MX97102 will retransmit the frame

automatically.If a collision is detected after the first pool

has been released, the MX97102 aborts the frame and

requests the processor to repeat the frame with an XMR

interrupt.

P/N:PM0473

REV. 2.5, SEP. 05, 2000

33

MX97102

Interrupt Structure and Logic

Since the MX97102 provides only one interrupt request

output (INT), the cause of an interrupt is determined by

the microprocessor by reading the Interrupt Status Reg-

ister (ISTA).In this register, seven interrupt sources can

be directly read. The LSB of the ISTA points to eight

non-critical interrupt sources which are indicated in the

Extend Interrupt Register (EXIR).Figure6-16 shows the

MX97102 interrupt structure.

INT

RME

RPF

RSC

XPR

TIN

CISQ

SIN

EXI

SQIE

SQC

BAS

SQRR

MASK

ISTA

XMR

XDU

PCE

RFO

SOV

MOS

C

O

D

R

0

CIC0

CIC1

CIR0

CIR1

CI1E

SAW

WOV

SQXR

EXIR

MOCR

MOSR

MDR1

MER1

MDA1

MAB1

MDR0

MRE1

MXE1

MRE0

MXE0

MER0

MDA0

MAB0

Figure6-14 MX97102 Interrupt Structure

P/N:PM0473

REV. 2.5, SEP. 05, 2000

34

MX97102

A read of the ISTA register clears all bits expect EXI

and CISQ. CISQ is cleared by reading CIR0.

A read of EXIR clears the EXI bit in ISTA as well as the

EXIR register. When all bits in ISTA are cleared, the

interrupt line (PINTN) in deactivated.

previous contents have been read. When this is done

and a second code change has already occurred, a

new interrupt is immediately generated and the new

code replaces the previous one in the register.The code

registers are buffered with a FIFO size of two. Thus, if

several consecutive codes are detected, only the first

and the last code is obtained at the first and second

register read, respectively.

Each interrupt source in ISTA register can be selec-

tively masked by setting to “ 1 ” the corresponding bit in

MASK. Masked interrupt status bits are not indicated

when ISTA is read.Instead, they remain internally stored

and pending, until the mask bit is reset to zero. Read-

ing the ISTA while a mask bit is active has no effect on

the pending interrupt.

The MONITOR Data Receive (MDR) and the MONI-

TOR End of Reception (MER) interrupt status bits have

two enable bits, MONITOR Receive interrupt Enable

(MRE) and MR bit Control (MRC).The MONITOR chan-

nel Data Acknowledged (MDA) and MONITOR chan-

nel Data Abort (MAB) interrupt status bits have a com-

mon enable bit MONITOR Interrupt Enable (MXE).

In the event of an extended interrupt and of a C/I or S/

Q channel change, EXI and CISQ are set even when

the corresponding mask bits in MASK are active, but

no interrupt (INT) is generated. Except for CISQ and

MOS all interrupt sources are directly determined by a

read of ISTA and (possibly) EXIR.

MRE prevents the occurrence of the MDR status, in-

cluding when the first byte of a packet is received, When

MRE is active (1) but MRC is inactive, the MDR-inter-

rupt status is generated only for the first byte of a re-

ceive packet. When both MRE and MRC are active,

MDR is generated and all received monitor bytes -

marked by a 1-to-0 transition in MX bit - are stored.

A CISQ interrupt may originate from a change in the

received S/Q code (SQC), from a change in the re-

ceived C/I channel 0 code (CIC0) or form a change in

the received C/I channel 1 code (CIC1).These three

corresponding status bits SQC, CIC0 and CIC1 are read

then cleared in the CIR0 register. SQC and CIC1 can

be individually disabled by clearing the enable bit SQIE

(SQXR register) or, respectively, CI1E (SQXR regis-

ter).

The INT output is level active. It stays active until all

interrupt sources have been serviced. If a new status

bit is set while an interrupt serviced, the INT line stays

active.This may cause problem if the MX97102 is con-

nected to edge-triggered interrupt controllers. To avoid

these problems, it is recommended to mask all inter-

rupts at the end of the interrupt service program and to

enable the interrupts again. This is done by writing FF

hex value to the MASK register and to write back the

old value of the MASK register.

An interrupt status is indicated every time a valid new

code is loaded in SQRR, CIR0 or CIR1. But in case of

a code change, the new code is not loaded until the

P/N:PM0473

REV. 2.5, SEP. 05, 2000

35

MX97102

MICROPROCESSOR INTERFACE CONNECTION

Single-chip microcontroller, such as 8048, 8031 or 8051,

can meet the need of MX97102. MX97102 is built in

various microprocessor interface, it fits perfectly into

almost any 8-bit microprocessor system environment.

The microprocessor interface can be selected to be ei-

ther of the Motorola type (with control signals CS, R/W,

DS) of the Siemens/Intel non-multiplexed bus type (with

control signals CS, WR, RD) or of the Siemens/Intel

multiplexed address/data bus type (with WR, RD, ALE).

+5V

S

PINTN

PRDN

INT(INTX)

RD

PWRN

PALE

PCSN

PSX1

PSX2

WR

ALE

(PSCX)

80C51

(80C188)

PSR1

PSR2

PAD7....0

AD7....AD0

A15....A8

Latch

MX97102

GCI

Common Bus A15-A0, D7-D0

Memory

FIGURE 7: CONNECTING THE MX97102 TO INTEL MICROCONTROLLER

P/N:PM0473

REV. 2.5, SEP. 05, 2000

36

MX97102

S/T INTERFACE

Line transceiver functions for the S/T interface follows

the electrical specifications of CCITTI.430. According

to this standard, pseudo-ternary encoding with 100%

pulse width is used on the S/T interface. For both re-

ceive and transmit direction, a 2:1 transformer is used

to connect the MX97102 transceiver to the 4 wire S/T

interface.

+5V

2 : 1

PSX1

PSX2

PSR1

PSR2

VDD

Transmit Pair

10uf

MX97102

2 : 1

VSSD

VSSA

Receive Pair

Protection Circuits

( * please see the Application note, PM 0624)

GND

FIGURE 8: MX97102 EXTERNAL S-INTERFACE CIRCUITRY

The receiver is changed as a threshold detector with

adaptively switched threshold levels. Pin PSR1 deliv-

ers 2.5V as an output, which is the virtual ground of the

input signal on pin PSR2.

SDSX Programming

E-channel Monitoring

Strobes 1 and 2 are provided, please see the Applica-

tion Note for defails.

This feature is provided by two ways, one way is to

allow cpu to access two serial E-bits in a register, the

other way is to get the E-bit signal from one pin of this

chip. (please see Application Note PM0624 for details.)

P/N:PM0473

REV. 2.5, SEP. 05, 2000

37

MX97102

INTERNAL REGISTER

TABLE 8 : HDLC OPERATION AND STATUS REGISTERS

Addr. Name R/W Bit7

(hex)

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Description

00-1F FIFO

R/W

R

Tx/Rx FIFO address

Interrupt Status Register

Mask Register

20

21

22

23

24

ISTA

RME

RPF

RSC

XPR

TIN

CISQ

MAC1

XIF

SIN

X

EXI

MASK

STAR

CMDR

W

R

XDOV XFW

XRNR RRNR MBR

MAC0 Status Register

W

RMC RRES RNR

STI

XTF

RAC

A

XME

XRES Command Register

MODE R/W MDS2 MDS1 MDS0 TMD

DIM2

L

DIM1 DIM0

Mode Register

Timer Register

Extended Interrupt

Register

TIMR

EXIR

R/W CNT

CNT

XDU

CNT

PCE

V

U

E

R

XMR

RFO

SOV

MOS

SAW

WOV

24

25

XAD1

RBCL

W

R

Transmit Address 1

RBC7 RBC6 RBC5 RBC4 RBC3

RBC2

RBC1 RBC0 Receive Frame

Byte Count Low

25

26

27

28

29

2A

XAD2

SAPR

SAP1

RSTA

SAP2

TEI1

W

R

Transmit Address 2

Received SAPI

W

R

SAPI1 SAPI1 SAPI1 SAPI1 SAPI1

SAPI1

SA0

CRI

0

Individual SAPI 1

Receive Status Register

Individual SAPI 2

Individual TEI 1

RDA

RDO

CRC

RAB

SA1

C/R

TA

0

W

R

SAPI2 SAPI2 SAPI2 SAPI2 SAPI2

SAPI2

TEI1

MCS

TEI1

TEI2

EA

RHCR

TEI2

Receive HDLC Control

Individual TEI 2

W

R

TEI2

XAC

TEI2

VN1

TEI2

VN0

TEI2

OV

TEI2

EA

RBCH

RBC11 RBC10 RBC9 RBC8 Receive Fram Byte Count

High

2B

STAR2

R

0

WFA

0

MULT

TREC SDET Status Register 2

Status Register 2

W

0

P/N:PM0473

REV. 2.5, SEP. 05, 2000

38

MX97102

TABLE 9 : SPECIAL PURPOSE REGISTERS

Addr.

(hex)

30

Name

R/W Bit7

Bit6

Bit5

Bit4

TLP

Bit3

Bit2

Bit1

Bit0

Description

SPCR

CIR0

R/W SPU

0

C1C1

C1C0

C2C1

C2C0

CIC1

Serial Port Control Reg.

Command/Indication

Receive 0

31

R

SQC

RSS

BAS

CODR0 CODR0 CODR0 CODR0 CIC0

31

CIX0

W

BAC

CODX0 CODX0 CODX0

CODX0

1

Command/Indication

Transmit 0

32

33

MOR0

MOX0

CIR1

R

MONITOR Receive 0

MONITORTransmit 0

Command/Indication

Receive 1

W

R

CODR1 CODR1 CODR1 CODR1 CODR1 CODR1 MR1

MX1

1

33

CIX1

W

CODX1 CODX1 CODX1 CODX1 CODX1

CODX1

1

Command/Indication

Transmit 1

34

35

36

37

MOR1

MOX1

C1R

R

MONITOR Receive 1

MONITORTransmit 1

Channel Register 1

Channel Register 2

B1-Channel Register

SyncTransfer Control

Register

W

R/W

R

C2R

B1CR

STCR

W

TSF

TBA2

TBA1

TBA0

ST1

ST0

SC1

SC0

38

39

3A

3B

B2CR

ADF1

ADF2

MOSR

MOCR

SQRR

R

B2-Channel Register

Additional Feature Reg.1

Additional Feature Reg.2

MONITOR Status Reg.

MONITOR Control Reg.

S-,Q-Channel Receive

Register

W

WTC1 WTC2 TEM

PFS

0

IOF

0

ITF

R/W IMS

0

ODS

D1C2

MER0

MRC0

SQR2

D1C1

MDA0

MXE0

SQR3

D1C0

MAB0

MXC0

SQR4

R

W

R

MDR1 MER1

MDA1

MAB1

MXC1

SYN

MDR0

MRE0

SQR1

MRE1

IDC

MRC1 MXE1

CFS

CI1E

3B

SQXR

W

IDC

CFS

CI1E

SQIE

SQX1

SQX2

SQX3

SQX4

S-,Q-ChannelTransmit

Register

3C

3D

3E

ADF3

EMR

EDR

R/W

R

0

1

0

STM1

0

STM0

0

MAX1

EMR1

MAX0

EMR0

Additional Feature Reg.3

E-channel bits reg.

D/E channel Control reg.

B-exchang, SDS2 reg.

W

D_SIZER0 D_SFLAGS D_UNARBEMON

ADF4

R/W IMS

BFWD

D2C2

D2C1

D2C0

ORDERING INFORMATION

PART NO.

PACKAGE

MX97102QC

MX97102UC

44 PIN PLCC

64 PIN LQFP

P/N:PM0473

REV. 2.5, SEP. 05, 2000

39

MX97102

REVISION HISTORY

Rev. No.

1.1

1.2

Description

Preliminary release

Change editing

Page

Date

JULY/28/1997

NOV/1997

Add ordering information and revision history

Change words in drawings

Add "not used" pins in pin descriptions

Page6, Table 3 changed

Wording errors

Change feature description

Storage Temperature Range " -65°C to 125°C" replaced by "-55°C to 150°C" P4

Add 64-pin package

Made for CD-ROM release

Modify 64-pin package outline data

64 PIN P-LQFP PACKAGE INFORMATION content changed

New revision adds E-channel monitoring function, extra SDS2 pin

Add one E-bit pin

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

NOV/1997

APR/14/1998

MAY/21/1998

JUN./15/1998

AUG/21/1998

SEP/15/1998

OCT/20/1998

OCT/27/1998

APR/01/1999

DEC/17/1999

P16

P1,3,4,

P10~35

Add LQFP pin description

Revise figure 8

Add LQFP package data

Add more descriptions

2.3

2.4

2.5

Add Pre-Filter Compensation

Contents modify

Modify state diagram 6-9(a)&6-9(b)

P22

P5,8

P23,24

JAN/21/2000

APR/28/2000

SEP/05/2000

P/N:PM0473

REV. 2.5, SEP. 05, 2000

40

MX97102

PACKAGE INFORMATION

44-PIN PLASTIC LEADED CHIP CARRIER (PLCC)

A

ITEM

A

MILLIMETERS INCHES

B

1

17.53 ±.12

16.59 ±.12

17.53 ±.12

1.95

.699 ±.005

.653 ±.12

.690 ±.12

.077

6

44

40

B

7

39

33

29

C

D

E

F

4.70 max.

2.55 ±.25

.51 min.

.185 max.

.100 ±.010

.020 min.

.050 [Typ.]

.028 ±.004

.018±.004

.610 ±.020

.025 R

13

C

D

G

H

I

1.27 [Typ.]

.71 ±.10

.46 ±.10

15.50 ±.51

.53 R

J

17

K

18

28

23

L

E

M

N

.25 [Typ.]

.010 [Typ.]

N

F

G

H

M

NOTE: Each lead centerline is located within .25

mm[.01 inch] of its true position [TP] at

maximum material condition.

I

J

K

L

64-PIN PLASTIC LOW-PROFILE QUAD FLAT PACKAGE (P-LQFP)

A

B

ITEM

A

MILLIMETERS INCHES

16

.63

B

14

.55

C

D

E

14

.55

16

.63

C

D

12 [Typ.]

1 [Typ.]

.35 ±.05

0.8

.47 [Typ.]

.039 [Typ.]

.014 ±.002

.031

F

G

H

I

E

J

1

.039

O

F

K

.6 ±.15

.15 ±.05

1.4 ±.05

.1 ±.05

1.6 [max.]

.024±.006

.006 ±.002

.057 ±.002

.004 ±.002

.063 [max.]

L

N

M

N

O

G

I

H

J

M

L

NOTE: Each lead centerline is located within .25

mm[.01 inch] of its true position [TP] at

maximum material condition.

K

P/N:PM0473

REV. 2.5, SEP. 05, 2000

41

MX97102

MACRONIX INTERNATIONAL CO., LTD.

HEADQUARTERS:

TEL:+886-3-578-6688

FAX:+886-3-563-2888

EUROPE OFFICE:

TEL:+32-2-456-8020

FAX:+32-2-456-8021

JAPAN OFFICE:

TEL:+81-44-246-9100

FAX:+81-44-246-9105

SINGAPORE OFFICE:

TEL:+65-348-8385

FAX:+65-348-8096

TAIPEI OFFICE:

TEL:+886-2-2509-3300

FAX:+886-2-2509-2200

MACRONIX AMERICA, INC.

TEL:+1-408-453-8088

FAX:+1-408-453-8488

CHICAGO OFFICE:

TEL:+1-847-963-1900

FAX:+1-847-963-1909

http : //www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.

42


型号：	MX97102
厂家：	MACRONIX INTERNATIONAL
描述：	ISDN S/T CONTROLLER ISDN S / T控制器综合业务数字网控制器
文件：	总42页 (文件大小：308K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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