N02L163WN1AT2-55I [NANOAMP]
2Mb Ultra-Low Power Asynchronous CMOS SRAM; 2MB超低功耗异步SRAM CMOS
| 型号： | N02L163WN1AT2-55I |
| 厂家： | 
NANOAMP SOLUTIONS, INC. |
| 描述： | 2Mb Ultra-Low Power Asynchronous CMOS SRAM |
| 文件： | 总11页 (文件大小：264K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NanoAmp Solutions, Inc.
1982 Zanker Road, San Jose, CA 95112
ph: 408-573-8878, FAX: 408-573-8877
www.nanoamp.com
N02L163WN1A
2Mb Ultra-Low Power Asynchronous CMOS SRAM
128K × 16bit
Overview
Features
The N02L163WN1A is an integrated memory
device containing a 2 Mbit Static Random Access
Memory organized as 131,072 words by 16 bits.
The device is designed and fabricated using
NanoAmp’s advanced CMOS technology to
provide both high-speed performance and ultra-low
power. The device operates with a single chip
enable (CE) control and output enable (OE) to
allow for easy memory expansion. Byte controls
(UB and LB) allow the upper and lower bytes to be
accessed independently. The N02L163WN1A is
optimal for various applications where low-power is
critical such as battery backup and hand-held
devices. The device can operate over a very wide
• Single Wide Power Supply Range
2.3 to 3.6 Volts
• Very low standby current
2.0µA at 3.0V (Typical)
• Very low operating current
2.0mA at 3.0V and 1µs (Typical)
• Very low Page Mode operating current
0.8mA at 3.0V and 1µs (Typical)
• Simple memory control
Single Chip Enable (CE)
Byte control for independent byte operation
Output Enable (OE) for memory expansion
• Low voltage data retention
o
o
temperature range of -40 C to +85 C and is
available in JEDEC standard packages compatible
with other standard 128Kb x 16 SRAMs.
Vcc = 1.8V
• Very fast output enable access time
30ns OE access time
• Automatic power down to standby mode
• TTL compatible three-state output driver
• Compact space saving BGA package avail-
able
Product Family
Standby
Power
Supply
(Vcc)
Operating
Current (Icc),
Typical
Operating
Current (ISB),
Part Number
Package Type
Speed
Temperature
Typical
N02L163WN1AB
N02L163WN1AT
N02L163WN1AB1
48 - BGA
44 - TSOP II
55ns @ 2.7V
70ns @ 2.3V
-40oC to +85oC
2.3V - 3.6V
2 µA
2 mA @ 1MHz
48 - BGA Pb-Free
N02L163WN1AT2 44 - TSOP II Green
(DOC# 14-02-014 REV L ECN# 01-1000)
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
1
NanoAmp Solutions, Inc.
Pin Configurations
N02L163WN1A
1
2
3
A0
A3
4
5
A2
6
A4
1
PIN
A5
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A3
2
ONE
A6
A1
A4
A6
A7
A2
3
LB
OE
NC
A7
A
B
C
D
E
F
A1
4
OE
A0
5
UB
I/O8
I/O0
UB
CE
CE
6
LB
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
7
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
I/O9 I/O10 A5
I/O1 I/O2
I/O3 VCC
8
9
VSS I/O11
VCC I/O12
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
NC
A16 I/O4 VSS
A15 I/O5 I/O6
I/O14 I/O13 A14
I/O15
NC
A12
A9
A13
A10
I/O7
NC
NC
A8
WE
A11
G
H
A8
A9
A10
A11
48 Pin BGA (top)
6 x 8 mm
NC
Pin Descriptions
Pin Name
A0-A16
Pin Function
Address Inputs
Write Enable Input
Chip Enable Input
Output Enable Input
WE
CE
OE
LB
UB
I/O0-I/O15
Lower Byte Enable Input
Upper Byte Enable Input
Data Inputs/Outputs
Not Connected
NC
VCC
Power
VSS
Ground
(DOC# 14-02-014 REV L ECN# 01-1000)
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
2
NanoAmp Solutions, Inc.
Functional Block Diagram
N02L163WN1A
Word
Address
Inputs
Address
Decode
Logic
A0 - A3
Input/
Page
32K Page
x 16 word
x 16 bit
Address
Inputs
Output
I/O0 - I/O7
Mux
Address
Decode
Logic
A4 - A16
and
RAM Array
Buffers
I/O8 - I/O15
CE
WE
OE
UB
LB
Control
Logic
Functional Description
1
CE
WE
OE
UB
LB
MODE
POWER
I/O0 - I/O15
Standby2
Active
Write3
H
L
L
L
L
X
X
L
X
X
X3
L
H
X
H
L1
L1
X
X
H
L1
L1
X
High Z
High Z
Data In
Data Out
High Z
Standby
Active
Active
Active
Active
H
H
Read
Active
1. When UB and LB are in select mode (low), I/O0 - I/O15 are affected as shown. When LB only is in the select mode only I/O0 - I/O7
are affected as shown. When UB is in the select mode only I/O8 - I/O15 are affected as shown.
2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally
isolated from any external influence and disabled from exerting any influence externally.
3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.
1
Capacitance
Item
Symbol
CIN
Test Condition
Min
Max
8
Unit
pF
VIN = 0V, f = 1 MHz, TA = 25oC
VIN = 0V, f = 1 MHz, TA = 25oC
Input Capacitance
I/O Capacitance
CI/O
8
pF
1. These parameters are verified in device characterization and are not 100% tested
(DOC# 14-02-014 REV L ECN# 01-1000)
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
3
NanoAmp Solutions, Inc.
N02L163WN1A
1
Absolute Maximum Ratings
Item
Symbol
VIN,OUT
VCC
Rating
–0.3 to VCC+0.3
–0.3 to 4.5
500
Unit
V
Voltage on any pin relative to VSS
Voltage on VCC Supply Relative to VSS
Power Dissipation
V
PD
mW
oC
oC
oC
TSTG
Storage Temperature
–40 to 125
TA
Operating Temperature
-40 to +85
260oC, 10sec
TSOLDER
Soldering Temperature and Time
1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operating section of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Operating Characteristics (Over Specified Temperature Range)
Typ1
Item
Symbol
Test Conditions
Min.
Max
Unit
VCC
VDR
VIH
VIL
Supply Voltage
Data Retention Voltage
Input High Voltage
2.3
1.8
3.6
V
V
Chip Disabled2
VCC+0.3
0.6
1.8
V
Input Low Voltage
–0.3
V
VOH
VOL
ILI
IOH = 0.2mA
IOL = -0.2mA
VCC–0.2
Output High Voltage
Output Low Voltage
Input Leakage Current
Output Leakage Current
V
0.2
0.5
0.5
V
VIN = 0 to VCC
µA
µA
ILO
OE = VIH or Chip Disabled
VCC=3.6 V, VIN=VIH or VIL
Chip Enabled, IOUT = 0
Read/Write Operating Supply Current
ICC1
ICC2
2.0
12
4.0
mA
mA
@ 1 µs Cycle Time2
VCC=3.6 V, VIN=VIH or VIL
Chip Enabled, IOUT = 0
Read/Write Operating Supply Current
16.0
@ 70 ns Cycle Time2
Page Mode Operating Supply Current
@ 70ns Cycle Time2 (Refer to Power
Savings with Page Mode Operation
diagram)
VCC=3.6 V, VIN=VIH or VIL
Chip Enabled, IOUT = 0
ICC3
4
mA
mA
VCC=3.6 V, VIN=VIH or VIL
Chip Enabled, IOUT = 0,
f = 0
Read/Write Quiescent Operating Sup-
ply Current3
ICC4
3.0
VIN = VCC or 0V
Maximum Standby Current3
Chip Disabled
ISB1
2.0
20
10
µA
µA
tA= 85oC, VCC = 3.6 V
VCC = 1.8V, VIN = VCC or 0
Chip Disabled, tA= 85oC
Maximum Data Retention Current3
IDR
1. Typical values are measured at Vcc=Vcc Typ., TA=25°C and are not 100% tested.
2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive
output capacitance expected in the actual system.
3. This device assumes a standby mode if the chip is disabled (CE high). In order to achieve low standby current all inputs must be
within 0.2 volts of either VCC or VSS
(DOC# 14-02-014 REV L ECN# 01-1000)
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
4
NanoAmp Solutions, Inc.
Power Savings with Page Mode Operation (WE = V )
N02L163WN1A
IH
Page Address (A4 - A16 )
Word Address (A0 - A3)
CE
Open page
...
Word 16
Word 1
Word 2
OE
LB, UB
Note: Page mode operation is a method of addressing the SRAM to save operating current. The internal
organization of the SRAM is optimized to allow this unique operating mode to be used as a valuable power
saving feature.
The only thing that needs to be done is to address the SRAM in a manner that the internal page is left open
and 16-bit words of data are read from the open page. By treating addresses A0-A3 as the least significant
bits and addressing the 16 words within the open page, power is reduced to the page mode value which is
considerably lower than standard operating currents for low power SRAMs.
(DOC# 14-02-014 REV L ECN# 01-1000)
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
5
NanoAmp Solutions, Inc.
Timing Test Conditions
N02L163WN1A
Item
0.1VCC to 0.9 VCC
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
5ns
0.5 VCC
CL = 30pF
-40 to +85 oC
Operating Temperature
Timing
2.3 - 3.6 V
2.7 - 3.6 V
Item
Symbol
Units
Min.
Max.
Min.
Max.
tRC
tAA
tCO
tOE
Read Cycle Time
70
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
70
70
35
35
55
55
30
30
Chip Enable to Valid Output
Output Enable to Valid Output
Byte Select to Valid Output
Chip Enable to Low-Z output
Output Enable to Low-Z Output
Byte Select to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Byte Select Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
t
LB, tUB
tLZ
10
5
10
5
tOLZ
tLBZ, tUBZ
tHZ
10
0
10
0
20
20
20
20
20
20
tOHZ
0
0
t
LBHZ, tUBHZ
tOH
0
0
10
70
50
50
50
40
0
10
55
40
40
40
40
0
tWC
tCW
Chip Enable to End of Write
Address Valid to End of Write
Byte Select to End of Write
Write Pulse Width
tAW
tLBW, tUBW
tWP
tAS
Address Setup Time
tWR
Write Recovery Time
0
0
tWHZ
tDW
Write to High-Z Output
20
20
Data to Write Time Overlap
Data Hold from Write Time
End Write to Low-Z Output
40
0
35
0
tDH
tOW
10
10
ns
(DOC# 14-02-014 REV L ECN# 01-1000)
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
6
NanoAmp Solutions, Inc.
Timing of Read Cycle (CE = OE = V , WE = V )
N02L163WN1A
IL
IH
t
RC
Address
t
AA
t
OH
Previous Data Valid
Data Valid
Data Out
Timing Waveform of Read Cycle (WE= V )
IH
t
RC
Address
t
AA
t
HZ
t
CO
CE
OE
t
LZ
t
OHZ
t
OE
t
OLZ
t
t
LB, UB
LB, UB
t
t
t
t
LBLZ, UBLZ
LBHZ, UBHZ
High-Z
Data Valid
Data Out
(DOC# 14-02-014 REV L ECN# 01-1000)
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
7
NanoAmp Solutions, Inc.
N02L163WN1A
Timing Waveform of Write Cycle (WE control)
t
WC
Address
t
WR
t
AW
t
CW
CE
t
, t
LBW UBW
LB, UB
t
WP
t
AS
WE
t
t
DH
DW
High-Z
Data Valid
Data In
Data Out
t
WHZ
t
OW
High-Z
Timing Waveform of Write Cycle (CE Control)
t
WC
Address
CE
t
t
AW
WR
t
CW
t
AS
t
, t
LBW UBW
LB, UB
WE
t
WP
t
t
DH
DW
Data Valid
Data In
t
LZ
t
WHZ
High-Z
Data Out
(DOC# 14-02-014 REV L ECN# 01-1000)
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
8
NanoAmp Solutions, Inc.
N02L163WN1A
44-Lead TSOP II Package (T44)
18.41±0.13
11.76±0.20
10.16±0.13
0.80mm REF
0.45
0.30
SEE DETAIL B
DETAIL B
1.10±0.15
o
o
0 -8
0.20
0.00
0.80mm REF
Note:
1. All dimensions in inches (Millimeters)
2. Package dimensions exclude molding flash
(DOC# 14-02-014 REV L ECN# 01-1000)
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
9
NanoAmp Solutions, Inc.
Ball Grid Array Package
N02L163WN1A
0.28±0.05
1.24±0.10
D
A1 BALL PAD
CORNER (3)
1. 0.35±0.05 DIA.
E
2. SEATING PLANE - Z
0.15
Z
0.05
Z
TOP VIEW
SIDE VIEW
1. DIMENSION IS MEASURED AT THE
MAXIMUM SOLDER BALL DIAMETER.
PARALLEL TO PRIMARY Z.
A1 BALL PAD
CORNER
SD
2. PRIMARY DATUM Z AND SEATING
PLANE ARE DEFINED BY THE
SPHERICAL CROWNS OF THE
SOLDER BALLS.
e
SE
3. A1 BALL PAD CORNER I.D. TO BE
MARKED BY INK.
K TYP
J TYP
e
BOTTOM VIEW
Dimensions (mm)
e = 0.75
BALL
D
E
MATRIX
TYPE
SD
SE
J
K
6±0.10
8±0.10
0.375
0.375
1.125
1.375
FULL
(DOC# 14-02-014 REV L ECN# 01-1000)
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
10
NanoAmp Solutions, Inc.
Ordering Information
N02L163WN1A
N02L163WN1AX-XX X
I = Industrial, -40°C to 85°C
Temperature
55 = 55ns
Performance
T = 44-pin TSOP II
B = 48-ball BGA
Package Type
T2 = 44-pin TSOP II Green Package
B1 = 48-ball BGA Pb-Free Package
Revision History
Revision #
Date
Change Description
A
B
C
D
E
F
G
H
I
Dec. 1999
Sept. 2000
Oct. 2000
Oct. 2000
Jan. 2001
Mar. 2001
May 2001
June 2001
Sept. 2001
Initial Preliminary Release
Modified Voltage Range and Standby Current Limits.
Added Missing Tas Parameter Specification.
Modified Standby Current Specifications.
Extensive Modification to use voltage regulator design
Modified BGA pinout, access time 70ns @ 2.7V, misc. errata
Changed access time to 55ns, modified 44-Lead TSOP Package diagram
Revised voltage range in Timing table, revised Dimensions table
Minor parametric modifications, full production release
Part number change from EM128L16, modified Overview and Features, added
Page Mode Operation diagram, revised Operating Characteristics table, Package
diagram, Functional Description table and Ordering Information diagram
J
Dec. 2001
K
L
Nov. 2002
Oct. 2004
Replaced Isb and Icc on Product Family table with typical values
Added Pb-Free and Green Package Option
© 2001 - 2002 Nanoamp Solutions, Inc. All rights reserved.
NanoAmp Solutions, Inc. ("NanoAmp") reserves the right to change or modify the information contained in this data sheet and the products described therein, without prior notice.
NanoAmp does not convey any license under its patent rights nor the rights of others. Charts, drawings and schedules contained in this data sheet are provided for illustration pur-
poses only and they vary depending upon specific applications.
NanoAmp makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does NanoAmp assume any liability arising out of the application
or use of any product or circuit described herein. NanoAmp does not authorize use of its products as critical components in any application in which the failure of the NanoAmp
product may be expected to result in significant injury or death, including life support systems and critical medical instruments.
(DOC# 14-02-014 REV L ECN# 01-1000)
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
11
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