NM14F8KSLAXAQ-3BNA_技术文档

4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

Level: Property

NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

MCP Specification

4Gb SLC NAND Flash (X16) + 4Gb LPDDR2 (X32)

4Gb SLC NAND Flash (X16) + 8Gb LPDDR2 (X32)

4Gb SLC NAND Flash (X8) + 4Gb LPDDR2 (X32)

Nanya Technology Corporation

Version 1.5

1

Nanya Technology Corp.

05/2018

NTC has the rights to change any specifications or product without notification.

4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

Level: Property

NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

Ordering Information

MCP

NAND

DRAM

Density

(Org.)

Program Erase

Time Time

Density

(Org.)

Part Number

Package

Type

Speed RL

4Gb

(256Mb X16)

4Gb

1066

NM14F4KSLAXAQ-3B 168b FBGA(-Q) SLC

NM14F4KSLAXA3-3B 240b FBGA(-3) SLC

NM14F8KSLAXA3-3B 240b FBGA(-3) SLC

NM1484KSLAXAJ-3B 162b FBGA(-J) SLC

300μs 3.5ms LPDDR2

8

(X 32, SDP) Mbps

4Gb

(256Mb X 16)

4Gb

1066

(X 32, SDP) Mbps

4Gb

(256Mb X 16)

8Gb

1066

(X 32, DDP) Mbps

4Gb

(512Mb X8)

4Gb

1066

(X 32, SDP) Mbps

Version 1.5

2

Nanya Technology Corp.

05/2018

4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

Level: Property

NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

NANYA MCP Part Numbering Guide

NM

1

4F

4K

S

L

AX

A

Q

3

B

Grade

NA = Commercial Grade

NANYA

MCP

DRAM Speed

Product Family

B = 1066Mbps @ RL=8

1 =SLC NAND + LPDDR2

NAND Organization

(Density, Config)

4F= 4Gb x16

NAND Speed

3 = 300μs

DRAM Organization

(Density, Config)

4K= 4Gb x32 (SDP)

8K= 8Gb x32 (DDP)

Package

Q = 168-ball FBGA 12.00 x 12.00 (mm)

3 = 240-ball FBGA 14.00 x 14.00 (mm)

J = 162-ball FBGA 11.50 x 13.00 (mm)

Device Version

NAND Voltage

S= 1.8V

A = 1^stversion

Reserve Code

Interface & Power (V_DD1, V_DD2, V_DDQ, V_DDCA

)

AX=Default

L = HSUL_12 (1.8V, 1.2V, 1.2V, 1.2V)

Version 1.5

3

Nanya Technology Corp.

05/2018

4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

Level: Property

NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

Features

MCP

 Separate SLC NAND and LPDDR2 RAM interfaces

 Lead-free (RoHS compliant) and Halogen-free Package :

162-ball FBGA (11.50mm x 13.00mm x 0.80mm) ;168-ball FBGA (12.00mm x 12.00mm x 0.80mm) ;

240-ball FBGA (14.00mm x 14.00mm x 0.80mm) ; 240-ball FBGA (14.00mm x 14.00mm x 0.90mm)

 Operating temperature range: –25°C to +85°C

4Gb X8 /X16 SLC NAND

 Voltage Supply(VCC/VCCQ): 1.70V ~ 1.95V

 Organization

4Gb(SDP)/8Gb(DDP) X32 LPDDR2

 Speed, Addressing and Retention Specification

Organization

128Mb x 32

- X8 Memory Cell Array: 4352 x 128K x 8

- X8 Register: 4352 x 8

Speed Grade

Device Type

Number of Banks

Bank Address

Row

1066 / RL=8

S4B

- X8 Page size: 4352 Bytes

8

- X8 Block size: (256K + 16K) Bytes

- X16 Memory Cell Array: 2176 x 128K x 16

- X16 Data Register: 2176 x 16

BA[2:0]

R[13:0]

C[9:0]

3.9

Column

- X16 Page Program: 2176 Words

- X16 Block Erase: (128K + 8K) Bytes

tREFI (us)

 JEDEC LPDDR2 Compliant

- Low Power Consumption

 Modes

Read, Reset, Auto Page Program, Auto Block Erase,

Status Read, Page Copy, Multi Page Program,

Multi Block Erase, Multi Page Copy, Multi Page Read

 Mode control

- Double-data rate on DQs, DQS, DM and CA bus

- 4n Prefetch Architecture

 HSUL12 interface and Power Supply

- VDD1= 1.70 to 1.95V

- Serial input/output

- Command control

- VDD2/VDDQ/VDDCA = 1.14 to 1.3V

 Signal Integrity

 Number of valid blocks

- Configurable DS for system compatibility

- Min 2008 blocks

- Max 2048 blocks

 Access time

- ZQ calibration for the accuracy of output driver strength

over Process, Voltage and Temperature

 Training for Signals’ Synchronization

- DQ Calibration offering specific DQ output patterns

 Data Integrity

- Cell array to register: 25μs max

- Serial Read Cycle: 25ns min (CL=30pF)

 Program/Erase time

- DRAM built-in Temperature Sensor for Temperature

Compensated Self Refresh (TCSR)

- Auto Page Program: 300μs/page typical

- Auto Block Erase: 3.5ms/block typical

 Operating current

- Auto Refresh, Self Refresh and PASR Modes

 Power Saving Modes

- Read (25ns cycle): 30 mA max

- Program (avg.): 30 mA max

- Deep Power Down Mode (DPD)

- Partial Array Self Refresh (PASR)

- Clock Stop capability during idle period

 Programmable Function

- Erase (avg.): 30 mA max

- Standby: 50 μA max

 8 bit ECC for each 512 Bytes is required.

- Output Drive Impedance (34.3/40/48/60/80/120)

- Burst Lengths (4/8/16)

- Burst Type (Sequential/Interleaved)

- Read Latency (3/4/5/6/7/8),Write Latency (1/2/3/4)

- nWR (3/4/5/6/7/8)

Version 1.5

4

Nanya Technology Corp.

05/2018

4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

Level: Property

NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

Ball Assignment – (162b Flash X 8 + DRAM X 32)

Part Number: NM1484KSLAXAJ-XXX

Top View, A1 in Top Left Corner

●

NAND

LPDDR2

●

1

2

3

4

5

6

7

8

9

10

A

B

C

D

DNU

NC

DNU

VCC

I/O 1

I/O 0



NC

CLE

ALE





VCC



I/O 4

I/O 5

I/O 6

NC

I/O 7

NC

VCC

NC

NB

DNU

VSS

NB

DNU

NB

A

B

C

D

I/O 3

I/O 2

R/

NC

NB

NC

NB

E

VSS

NC

NB

VDD2

VDD1

DQ31

DQ29

DQ26

DNU

E

F

G

H

J

VDD1

VSS

VDD2

CA9

CA6

CA5

VSS

NC

ZQ

NB

4

VSS

VDDQ

DQ28

VSS

DQ30

DQ24

DQ11

DQS1

VDDQ

DQS0

DQ4

VDDQ DQ25

VSS

VDDQ

VSS

VDDQ

VSS

NB

F

G

H

J

DQ27

DM3

DQ13

DQ10

NB

DQS3



VSS

CA8

CA7

VREFCA



DQ15 VDDQ

VDDCA

VDD2

VDDCA

VSS

DQ14

DQ9

NB

DQ12

DQ8

NB

K



DM1

VSS

K

L

M

N

P

CK

VDD2

NB

VSS VREFDQ

NB

M

N

P

CKE



NC

DM0



VSS

NB

DQ6

DQ1

DQ0

DQS2

NB

DQ7

DQ3

VDDQ



VSS

DQ21

DNU

9

NB

NC

DQ5

DQ2

DM2

DQ20

VSS

VDDQ

VSS

VDDQ

DNU

10

R

T

CA4

CA3

VDDCA

VDD2

VSS

NC

CA2

CA1

CA0

NC

R

T

VSS

DQ19

VDDQ

VSS

DQ23

DQ17

VSS

U

V

W

Y

VSS

U

V

W

Y

VDD1

DNU

1

VDDQ DQ22

NC

VDD2

NB

VDD1

NB

DQ16

NB

7

DQ18

NB

8

DNU

2

NB

3

5

6

Version 1.5

5

Nanya Technology Corp.

05/2018

4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

Level: Property

NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

Ball Assignment – (168b Flash X 16 + DRAM X32)

Part Number: NM14F4KSLAXAQ-XXX

< TOP View>

See the balls through the package

A1

a

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

A

B

C

D

E

F

A

B

NC

R/

NC I/O 11 VCC I/O 10 I/O 9 VCC I/O 8 VDD1 VSS DQ30 DQ29 VSS DQ26 DQ25 VSS  VDD1 VSS

NC

VDDQ

NC VDD1 I/O3 VSS I/O2

I/O1 VSS I/O0 VSS VDD2 DQ31

DQ28 DQ27

DQ24 DQS3

DM3 VDD2 NC

C

D

E

VSS VDD2

I/O 12 I/O4

I/O 13 I/O5

VCC VSS

I/O 14 I/O6

I/O 15 I/O7

VCC VSS

DQ15 VSS

DQ14

VDDQ

DQ12 DQ13

DQ11 VSS

F

G

H

J

VDDQ

G

H

J

DQ10

DQ8 DQ9

DQS1 VSS

K

L

VDDQ

K







L

CLE ALE

VDD2 DM1

VREF

M

N

P

R

T

M

N

P

 VSS

VSS

DQ

 VDD1

VDD1 DM0

VREF

ZQ

CA

 VSS

VDDQ

R

T

VSS VDD2

DQS0

CA9 CA8

VDD

DQ6 DQ7

DQ5 VSS

U

V

W

Y

U

V

CA7

CA

VDDQ

VSS CA6

VDD

DQ4

W

Y

CA5

CA

DQ2 DQ3

DQ1 VSS



CK

AA

AB

AC

VDDQ

AA

AB

AC

VSS VDD2

DQ0

NC

VDDQ

DQ22 DQS2

NC



NC VDD1 CA1 VSS CA3 CA4 VDD2 VSS DQ16

VDD

DQ18 DQ20

DM2 VDD2 NC

CKE

NC

VSS CA0 CA2

NC

VCC

NC

VSS DQ17 DQ19 VSS DQ21 DQ23 VSS  VDD1 VSS

NC

22

NC

CA

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

23

Version 1.5

6

Nanya Technology Corp.

05/2018

4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

Level: Property

NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

Ball Assignment – (240b Flash X 16 + DRAM X32)

Part Number: NM14F4KSLAXA3-XXX

< TOP View>

See the balls through the package

A1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

NC

a

VREF

DQ

NC

VSS VDD2 DQ31 VDDQ VSS DQ26 DQ24 DQS3 DM3 DQ15 DQ13 VSS VDDQ DQ8 VSS

VDD1 VDDQ VSS DQ7 DQ5 VSS VDDQ VDD1 VSS

A

B

NC

VSS DQ30 DQ29 DQ27 VDDQ VSS  VSS DQ14 DQ12 DQ11 DQ9  VDDQ VSS VDD2  DM0 DQ6 DQ4 DQ3 DQ1 DQ0

NC

VSS

VDD2

C

D

E

VDD1

NC

DQ28

DQ25

VDDQ

DQ10

DQS1

DM1

DQS0

VDDQ

DQ2

DM2

C

NC

VDDQ 

VSS DQS2 DQ23

DQ22 VDDQ

D

NC

VSS

NC

VSS

E

F

NC

F

NC

DQ21 DQ20

VSS

G

H

J

G

NC

DQ19 DQ18

H

NC

VDDQ DQ17 DQ16

J

K

NC

VSS

VDD1

NC

VDD2

VSS

NC

K

L

NC

L

M

N

P

NC

M

N

NC

P

R

T

VCC

I/O 8

I/O 9

I/O 10

VCC

I/O 11

R/

NC

R

VSS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

NC

T

U

V

U

V

W

Y

W

Y

AA

AB

AC

AD

AE

AF

AG

AB I/O 12

AC

VCC

AD I/O 13

I/O 14

NC

VSS

RE

NC

WP

CE

NC

VDD2

CA6

CA7

CA8

CA5

VSS

VDD2

CK

CA4



NC

VSS

NC

AE

AF

AG

VDD

CA

VDD

CA

NC

I/O7

ALE

CLE

NC

VSS CA9

CKE

NC

CA2

CA3

VSS CA0 VDD2 NC

NC

VREF

CA

VDD

NC

I/O 15 VCC

WE

NC VDD1 ZQ

VSS

14

VSS

16



CA1 VDD1 NC

CA

1

2

3

4

5

6

7

8

9

10

11

12

13

15

17

18

19

20

21

22

23

24

25

26

27

Version 1.5

7

Nanya Technology Corp.

05/2018

4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

Level: Property

NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

Ball Assignment – (240b Flash X 16 + DRAM X32)

LPDDR2 14x14 PoP-FBGA 1-channelX32 (/) ballout

Part Number: NM14F8KSLAXA3-XXX

< TOP View>

See the balls through the package

A1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

NC

a

VREF

DQ

A

NC

VSS VDD2 DQ31 VDDQ VSS DQ26 DQ24 DQS3 DM3 DQ15 DQ13 VSS VDDQ DQ8 VSS

VDD1 VDDQ VSS DQ7 DQ5 VSS VDDQ VDD1 VSS

A

B

NC

VSS DQ30 DQ29 DQ27 VDDQ VSS  VSS DQ14 DQ12 DQ11 DQ9  VDDQ VSS VDD2  DM0 DQ6 DQ4 DQ3 DQ1 DQ0

NC

VSS

VDD2

C

D

E

VDD1

NC

DQ28

DQ25

VDDQ

DQ10

DQS1

DM1

DQS0

VDDQ

DQ2

DM2

C

NC

VDDQ 

VSS DQS2 DQ23

DQ22 VDDQ

D

NC

VSS

NC

VSS

E

F

NC

F

G

H

J

NC

DQ21 DQ20

VSS

G

NC

DQ19 DQ18

H

NC

VDDQ DQ17 DQ16

J

K

NC

VSS

VDD1

NC

VDD2

VSS

NC

K

NC

L

M

N

P

NC

M

N

NC

P

R

T

VCC

I/O 8

I/O 9

I/O 10

VCC

I/O 11

R/

NC

R

VSS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

NC

T

U

V

U

V

W

Y

W

Y

AA

AB

AC

AD

AE

AF

AG

AB I/O 12

VCC

AC

AD I/O 13

AE I/O 14

NC

VSS

RE

NC

WP

CE

NC

VDD2

CA6

CA7

CA8

CA5

VSS

VDD2

CA4

VSS

NC

VDD

CA

VDD

CA

AF

NC

I/O7

ALE

CLE

NC

VSS CA9

CK CKE0  CA2

 CKE1  CA3

VSS CA0 VDD2 NC

NC

VREF

CA

VDD

AG

NC

I/O 15 VCC

WE

NC VDD1 ZQ

VSS

14

VSS

16

CA1 VDD1 NC

CA

1

2

3

4

5

6

7

8

9

10

11

12

13

15

17

18

19

20

21

22

23

24

25

26

27

Version 1.5

8

Nanya Technology Corp.

05/2018

4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

Level: Property

NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

Package Outline Drawing (162-ball-4Gb SLC NAND + 4Gb LPDDR2)

Unit: mm

* BSC (Basic Spacing between Center)

Version 1.5

9

Nanya Technology Corp.

05/2018

4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

Level: Property

NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

Package Outline Drawing (168-ball-4Gb SLC NAND + 4Gb LPDDR2)

Unit: mm

* BSC (Basic Spacing between Center)

Version 1.5

10

Nanya Technology Corp.

05/2018

4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

Level: Property

NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

Package Outline Drawing (240-ball-4Gb SLC NAND + 4Gb LPDDR2)

Unit: mm

* BSC (Basic Spacing between Center)

Version 1.5

11

Nanya Technology Corp.

05/2018

4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

Level: Property

NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

Package Outline Drawing (240-ball-4Gb SLC NAND + 8Gb LPDDR2)

Unit: mm

* BSC (Basic Spacing between Center)

Version 1.5

12

Nanya Technology Corp.

05/2018

4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

Level: Property

NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

Ball Description - 4Gb X8/X16 SLC NAND

Symbol

Type

Function

Data Bus: The I/O0 to 7 pins are used as a port for transferring address, command and input/output data to

and from the device.

X8: I/O[7:0]

Input/output

X16: I/O[15:0]

The I/O8 to 15 pins are used as a port for transferring input/ouput data to and from the device. I/O8 to 15

pins must be low level(V ) when address and command are input.

IL

Command Latch Enable: The CLE input signal is used to control loading of the operation mode command

into the internal command register. The command is latched into the command register from the I/O port on

the rising edge of the  signal while CLE is High.

CLE

ALE



Input

Address Latch Enable: The ALE signal is used to control loading address information into the internal

address register. Address information is latched into the address register from the I/O ports on the rising

edge of  while ALE is High.

Chip Enable: The device goes into a low-power Standby mode when  goes High during the device is in

Ready state. The  signal is ignored when device is in Busy state ( RY /  = L), such as during a Program

or Erase or Read operation, and will not enter Standby mode even if the  input goes High.

Read Enable: The  signal controls serial data output. Data is available tREA after the falling edge of .



The internal column address counter is also incremented (Address = Address +1) on this falling edge.





Input

Write Enable: The  signal is used to control the acquisition of data from the I/O port.

Write Protect: The  signal is used to protect the device from accidental programming or erasing. The

internal voltage regulator is reset when  is Low. This signal is usually used protecting the data during the

power-on/off sequence when input signals are invalid.

Ready / Busy Output: The RY /  output signal is used to indicate the operation condition of the device.

The RY /  signal is in Busy state ( RY /  =L) during the Program, Erase and Read operations and will

return to Ready state ( RY /  =H) afeter completion of the operation. The output buffer for this signal is an

open drain and has to be pulled-up to Vccq with an appropriate resister.

RY/

Output

If RY /  signal is not pulled-up to Vccq ( “Open” state ), device operation cannot guarantee.

VCC

VSS

NC

Supply

─

Power

Ground

No Connect: These pins should be left unconnected.

Version 1.5

13

Nanya Technology Corp.

05/2018

4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

Level: Property

NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

Ball Description - 4Gb(SDP)/8Gb(DDP) X32 LPDDR2

Symbol

Type

Function

Clock: CK and  are differential clock inputs. All Double Data Rate (DDR) CA inputs are sampled

on both positive and negative edge of CK. Single Data Rate (SDR) inputs,  and CKE, are sampled

at the positive Clock edge. Clock is defined as the differential pair, CK and . The positive Clock

edge is defined by the crosspoint of a rising CK and a falling . The negative Clock edge is defined

by the crosspoint of a falling CK and a rising .

CK, 

Input

Clock Enable: CKE high activates, and CKE low deactivates internal clock signals, and device input

buffers and output drivers. Power saving modes are entered and exited through CKE transitions. CKE

is considered part of the command code. CKE is sampled at the positive Clock edge.

CKE0, CKE1

, 

CA[9:0]

Input

Chip Select:  is considered part of the command code.  is sampled at the positive Clock edge.

Command/Address Inputs: Uni-directional command/address bus inputs. Provide the command

and address inputs according to the command truth table. CA is considered part of the command

code.

Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is

sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of

DQS. Although DM pins are input-only, the DM loading matched the DQ and DQS (or ).

DM0 corresponds to the data on DQ0-DQ7, DM1 corresponds to the data on DQ8-DQ15, DM2

corresponds to the data on DQ16-DQ23, and DM3 corresponds to the data on DQ24-DQ31.

DM[3:0]

Input

DQ[31:0]

Input/output

Data Bus: Bi-directional Input / Output data bus.

Data Strobe (Bi-directional, Differential): The data strobe is bi-directional (used for read and write

data) and Differential (DQS and ). It is output with read data and input with write data. DQS is

edge-aligned to read data, and centered with write data.

DQS,

DQS[3:0]

[3:0]

Input/output

DQS0 &  corresponds to the data on DQ0-DQ7, DQS1 &  corresponds to the data on

DQ8-DQ15, DQS2 &  corresponds to the data on DQ16-DQ23, DQS3 &  corresponds to

the data on DQ24-DQ31.

NC

ZQ

-

No Connect: No internal electrical connection is present.

Reference Pin for Output Drive Strength Calibration. External impedance (240-ohm): this signal is

Input

used to calibrate the device output impedance.

Supply

VDD1

VDD2

VDDQ

VDDCA

Core Power Supply 1: Core power supply

Core Power Supply 2: Core power supply

DQ Power Supply: Isolated on the die for improved noise immunity.

Input Receiver Power Supply: Power supply for CA0-9, CKE, , CK, and  input buffers.

Reference Voltage: VREFDQ is reference for DQ input buffers. VREFCA is reference for Command /

VREFDQ, VREFCA

VSS

Supply

Address input buffers.

Ground

NOTE 1: The signal may show up in a different symbol but it indicates to the same thing. e.g., /CK = CK# =  = CKb,

/DQS = DQS# =  = DQSb, /CS = CS# =  = CSb.

Version 1.5

14

Nanya Technology Corp.

05/2018

4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

Level: Property

NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

Functional Block Diagram (4Gb SLC NAND + 4Gb LPDDR2)

V_DD1V_DD2V_DDQV_DDCA

V_ss

V_REFCA

V_REFDQ



ZQ

RZQ

CKE

CK

4Gb Mobile DDR2



DM[3:0]

CA[9:0]

DQ[31:0]

DQS[3:0]



NAND

CLE

ALE



4Gb NAND Flash

X8: I/O[7:0]

X16: I/O[15:0]







R/

V_CCV_SS

Version 1.5

05/2018

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Nanya Technology Corp.

4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

Level: Property

NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

Functional Block Diagram (4Gb SLC NAND + 8Gb LPDDR2)

V_DD1V_DD2V_DDQV_DDCA

V_ss

V_REFCA

V_REFDQ



CKE1

ZQ

RZQ



CKE0

CK

4Gb

Mobile DDR2

Die 0

4Gb

Mobile DDR2

Die 1



DM[3:0]

CA[9:0]

DQ[31:0]

DQS[3:0]



NAND

CLE

ALE



4Gb NAND Flash

X16: I/O[15:0]







R/

V_CCV_SS

Version 1.5

05/2018

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Nanya Technology Corp.

4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

Level: Property

NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

4Gb(X8/X16) SLC NAND Flash

Version 1.5

17

Nanya Technology Corp.

05/2018

4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

Level: Property

NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

Descriptions

The device is a single 1.8V 4Gbit (4,563,402,752 bits) NAND Electrically Erasable and Programmable

2

Read-Only Memory (NAND E PROM) organized as X8: (4096 +256) bytes x 64 pages x 2048 blocks or X16:

(2048 + 128) words x 64 pages x 2048 blocks.

The device has two 4352-bytes or 2176-words static registers which allow program and read data to be

transferred between the register ad the memory cell array in 4352-bytes or 2176-words increments. The

Erase operation is implemented in a single block unit (X8=256 Kbytes + 16 Kbytes: 4352 bytes x 64 pages

or X16=128 Kwords + 8 Kwords: 2176 words x 64 pages).

The device is a serial-type memory device which utilizes the I/O pins for both address and data input/output

as well as for command inputs. The Erase and Program operations are automatically executed making the

device most suitable for applications such as solid-state file storage, voice recording, image file memory for

still cameras and other systems which require high-density non-volatile memory data storage.

Version 1.5

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Nanya Technology Corp.

05/2018

4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

Level: Property

NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

Function Block Diagram (X8)

V_CC

V_SS

Status register

Address register

I/O 0

Column buffer

Column decoder

Data register

I/O

to

I/O 7

Control circuit

Command register



CLE

ALE

Memory cell array

Logic control

Control circuit







RY/

HV generator

Schematic Cell Layout and Address Assignment (X8)

The Program operation works on page units while the Erase operation works on block units

A page consists of 4352 bytes in which 4096 bytes are used for

main memory storage and 256 bytes are for redundancy or for

other uses.

I/O 0

I/O 7

1 Page = 4352 Bytes

1 Block = 4352 Bytes x 64 Pages = (256K + 16K) Bytes

Capacity = 4352 Bytes x 64 Pages x 2048 Blocks

1 Block = 64 Pages

(256K + 16K) Bytes

Array Address (X8)

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

Address

1^stcycle

2^ndcycle

3^rdcycle

4^thcycle

5^thcycle

CA₀

CA₈

PA₀

PA₈

PA₁₆

CA₁

CA₉

PA₁

PA₉

L

CA₂

CA₁₀

PA₂

PA₁₀

L

CA₃

CA₁₁

PA₃

PA₁₁

L

CA₄

CA₁₂

PA₄

PA₁₂

L

CA₅

L

CA₆

L

CA₇

L

Column Address

Page Address

PA₅

PA₁₃

L

PA₆

PA₁₄

L

PA₇

PA₁₅

L

PA6 to PA16: Block address

PA0 to PA5: NAND address in block

Version 1.5

05/2018

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Nanya Technology Corp.

4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

Level: Property

NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

Function Block Diagram (X16)

V_CC

V_SS

Status register

Address register

I/O 0

Column buffer

Column decoder

Data register

I/O

to

I/O 15

Control circuit

Command register



CLE

ALE

Memory cell array

Logic control

Control circuit







RY/

HV generator

Schematic Cell Layout and Address Assignment (X16)

The Program operation works on page units while the Erase operation works on block units

A page consists of 2176 words in which 2048 words are used

for main memory storage and 128 words are for redundancy or

for other uses.

I/O 0

I/O 15

1 Page = 2176 Words

1 Block = 2176 Words x 64 Pages = (128K + 8K) Words

Capacity = 2176 Words x 64 Pages x 2048 Blocks

1 Block = 64 Pages

(128K + 8K) Words

Array Address (X16)

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 8 ~ I/O 15

Address

1^stcycle

2^ndcycle

3^rdcycle

4^thcycle

5^thcycle

CA₀

CA₈

PA₀

PA₈

PA₁₆

CA₁

CA₉

PA₁

PA₉

L

CA₂

CA₁₀

PA₂

PA₁₀

L

CA₃

CA₁₁

PA₃

PA₁₁

L

CA₄

L

CA₅

L

CA₆

L

CA₇

L

Column Address

Page Address

PA₄

PA₁₂

L

PA₅

PA₁₃

L

PA₆

PA₁₄

L

PA₇

PA₁₅

L

PA6 to PA16: Block address

PA0 to PA5: NAND address in block

Note I/O8 ~ 15 must be held low when address is input.

Version 1.5

05/2018

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Nanya Technology Corp.

4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

Level: Property

NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

Absolute Maximum Ratings

Symbol

V_CC

Rating

Value

-0.6 to +2.5

-0.6 to Vcc + 0.3 (≤2.5V)

0.3

Unit

Power Supply Voltage

Input Voltage

V_IN

V

V_I/O

Input / Output Voltage

Power Dissipation

P_D

W

^oC

T_SOLDER

T_STG

Soldering Temperature (10 s)

Storage Temperature

260

-55 to +125

Capacitance¹

(T_A=25℃, f=1.0MHz)

Symbol

C_IN

Parameter

Input

Test Condition

Min

－

Max

Unit

pF

V_IN=0V

10

C_OUT

Output

V_OUT=0V

－

pF

NOTE 1

This parameter is periodically sampled and is not tested for every device.

Version 1.5

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05/2018

4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

Level: Property

NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

Valid Blocks

Symbol

NVB

Parameter

Min

Typ.

－

Max

2,048

Unit

Number of Valid Blocks

2,008

Blocks

NOTE 1

The device occasionally contains unusable blocks.

The first block (Block 0) is guaranteed to be a valid block at the time of shipment.

The specification for the minimum number of valid blocks is applicable over lifetime.

The number of valid blocks is on the basis of single plane operations, and this may be decreased with two

plane operations.

Recommended DC Operating Conditions

Symbol

V_CC

Parameter

Power Supply Voltage

Min

1.70

Typ.

－

Max

1.95

Unit

V

V_IH

High Level Input Voltage

Low Level Input Voltage

V_CCx 0.8

-0.3¹

－

V_CC+ 0.3

V_CCx 0.2

V

V_IL

－

V

Note 1

-2V (pulse width lower than 20 ns)

DC and Operation Characteristics

(Ta= -25 to 85℃, V_CC=1.70 to 1.95V )

Symbol

I_IL

Parameter

Input Leakage Current

Output Leakage Current

Serial Read Current

Test Conditions

Min

Typ.

－

4

Max

±10

30

Unit

μA

V_IN=0 to V_CC

－

I_LO

V_OUT=0 to V_CC

－

mA

I_CCO1

I_CCO2

I_CCO3

I_CCS

=V_IL,I_OUT= 0 mA, tcycle=25ns

－

Programming Current

Erasing Current

－

30

mA

μA

V

Standby Current

= V_CC- 0.2 V,  = 0 V/V_CC

I_OH= -0.1mA

－

50

V_OH

V_OL

High Level Output Voltage

Low Level Output Voltage

V_CC- 0.2

－

I_OL= 0.1mA

0.2

－

V

I_OL(RY/) Output Current of (RY/) pin

V_OL=0.2V

－

mA

Version 1.5

05/2018

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Nanya Technology Corp.

4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

Level: Property

NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

AC Timing Characteristics for Command / Address / Data Input

(Ta= -25 to 85℃, V_CC=1.70 to 1.95V)

Symbol

Parameter

Min

Max

Unit

tCLS

tCLH

tCS

CLE Setup Time

CLE Hold Time

 Setup Time

 Hold Time

12

5

–

ns

20

5

tCH

tWP

tALS

tALH

tDS

Write Pulse Width

ALE Setup Time

ALE Hold Time

Data Setup Time

Data Hold Time

Write Cycle Time

 High Hold Time

12

5

12

5

tDH

tWC

tWH

25

10

AC Characteristics for Operation

Symbol

Parameter

Min

Max

Unit

tWW

tRR

 High to  Low

100

20

12

25

–

ns

μs

ns

μs

Ready to  Falling Edge

–

tRW

tRP

Ready to  Falling Edge

Read Pulse Width

–

tRC

Read Cycle Time

–

tREA

tCEA

tCLR

 Access Time

20

 Access Time

–

25

CLE Low to  Low

10

25

5

–

tAR

ALE Low to  Low

–

tRHOH

tRLOH

tRHZ

tCHZ

tCSD

tREH

tIR

 High to Output Hold Time

 Low to Output Hold Time

 High to Output High Impedance

 High to Output High Impedance

 High to ALE or CLE Don’t care

 High Hold Time

–

60

–

20

0

–

10

0

–

Output-High-impedance-to- Falling Edge

 High to  Low

–

tRHW

tWHC

tWHR

tR

30

60

–

 High to  Low

–

 High to  Low

–

25

Memory Cell Array to Starting Address

Data Cache Busy in Read Cache (following 31h and 3Fh)

Data Cache Busy in Page Copy (following 3Ah)

 High to Busy

tDCBSYR1

tDCBSYR2

tWB

–

25

–

30

–

100

tRST

Device Reset Time (Ready/Read/Program/Erase)

–

5/5/10/500

NOTE 1 tCLS and tALS cannot be shorter than tWP.

NOTE 2 tCS should be longer than tWP + 8ns.

Version 1.5

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05/2018

4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

Level: Property

NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

AC Test Condition

Condition

VCC : 1.70 to 1.95V

VCC – 0.2 V, 0.2 V

3ns

Parameter

Input level

Input pulse rise and fall time

Input comparison level

Output data comparison level

Output Load

Vcc / 2

1 TTL GATE and CL=30pF

NOTE 1

Busy to ready time depends on the pull-up resistor tied to the RY/ pin.

Programming / Erasing Characteristics

(Ta= -25 to 85℃, V_CC=1.70 to 1.95V)

Symbol

tPROG

Parameter

Average Programming Time

Min

–

Typ.

300

–

Max

700

10

Unit

μs

tDCBSYW1 Data Cache Busy Time in Write Cache (following 11h)

tDCBSYW2¹Data Cache Busy Time in Write Cache (following 15h)

–

μs

–

700

4

μs

N

Number of Partial Program Cycles in the Same Page

Block Erase Time

–

cycle

ms

tBERASE

NOTE 1

–

3.5

10

t

depends on the timing between internal programming time and data in time.

DCBSYW2

Data Output

When tREH is long, output buffers are disabled by =High, and the hold time of data output depend on tRHOH

(25ns MIN). On this condition, waveforms look like normal serial read mode.

When tREH is short, output buffers are not disabled by  =High, and the hold time of data output depend on

tRLOH (5ns MIN). On this condition, output buffers are disabled by the rising edge of CLE, ALE,  or falling

edge of , and waveforms look like Extended Data Output Mode.

Version 1.5

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Nanya Technology Corp.

05/2018

4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

Level: Property

NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

Operation Mode: Logic and Command Tables

The operation modes such as Program, Erase, Read and Reset are controlled by operations shown in

command table. Address input, command input and data input/output are controlled by the CLE, ALE, , ,

 and  signals, as shown in Mode Selection Table.

Logic Table

CLE

H

ALE

L



L





H



Mode

Command Input

Data Input

＊

H

L

H

L

H

L

H

＊

Address Input

L

H

＊

Serial Data Output

During Program (Busy)

During Erase (Busy)

＊

H

＊

H¹

＊

H¹

＊

H

＊

During Read (Busy)

L

＊

H

L

Program, Erase Inhibit

Stand-by

0V/V_CC

H: V_IH, L=V_IL*: V_IHor V_IL.

Note 1: If  is low during read busy.  and  must be held High to avoid unintended command/address input to

device or read to device. Reset or Status Read command can be input during Read Busy.

Version 1.5

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Nanya Technology Corp.

05/2018

4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

Level: Property

NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

Command Table

Function

1^stCycle

80_H

00_H

05_H

31_H

3F_H

80_H

85_H

80_H

81_H

00_H

8C_H

60_H

90_H

70_H

71_H

FF_H

2^ndCycle

－

Acceptable Command during Busy

Serial Data Input

Read

30_H

E0_H

－

Column Address Change in Serial Data Output

Read with Data Cache

Read Start for Last Page in Read Cycle with Data Cache

Auto Page Program

－

10_H

－

Column Address Change in Serial Data Input

Auto Program with Data Cache

15_H

11_H

15_H

10_H

3A_H

15_H

10_H

D0_H

－

Multi Page Program

Read for Page Copy (2) with Data Out

Auto Program with Data Cache during Page Copy (2)

Auto Program for last page during Page Copy (2)

Auto Block Erase

ID Read

－

Status Read

O

－

Status Read for Multi-Page Program or Multi Block Erase

Reset

－

Read mode operation states

CLE

L

ALE

L



L



H



L

I/O0 to I/O15

Data output

Power

Active

Output Select

Output Deselect

L

H

High impedance

H: V_IH, L=V_IL

Version 1.5

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Nanya Technology Corp.

05/2018

4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

Level: Property

NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

DEVICE OPERATION

Read Mode

Read mode is set when the "00h" and “30h” commands are issued to the Command register. Between the two

commands, a start address for the Read mode needs to be issued. After initial power on sequence, “00h”

command is latched into the internal command register. Therefore read operation after power on sequence is

executed by the setting of only five address cycles and “30h” command. Refer to the figures below for the

sequence and the block diagram (Refer to the detailed timing chart.).

For X8 :

For X16 :

A data transfer operation from the cell array to the Data Cache via Page Buffer starts on the rising edge of 

in the 30h command input cycle (after the address information has been latched). The device will be in the Busy

state during this transfer period.

After the transfer period, the device returns to Ready state. Serial data can be output synchronously with the 

clock from the start address designated in the address input cycle.

Version 1.5

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05/2018

4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

Level: Property

NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

Random Column Address Change in Read Cycle

During the serial data output from the Data Cache, the column address can be changed by inputting a new

column address using the 05h and E0h commands. The data is read out in serial starting at the new column

address. Random Column Address Change operation can be done multiple times within the same page.

Version 1.5

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Nanya Technology Corp.

05/2018

4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

Level: Property

NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

Read Operation with Read Cahe

The device has a Read operation with Data Cache that enables the high speed read operation shown below.

When the block address changes, this sequence has to be started from the beginning.

For X8 :

For X16 :

If the 31h command is issued to the device, the data content of the next page is transferred to the Page Buffer

during serial data out from the Data Cache, and therefore the tR (Data transfer from memory cell to data

register) will be reduced.

1 Normal read. Data is transferred from Page N to Data Cache through Page Buffer. During this time period, the device outputs Busy state

for tR max.

2 After the Ready/Busy returns to Ready, 31h command is issued and data is transferred to Data Cache from Page Buffer again. This data

transfer takes tDCBSYR1 max and the completion of this time period can be detected by Ready/Busy signal.

3 Data of Page N + 1 is transferred to Page Buffer from cell while the data of Page N in Data cache can be read out by  clock

simultaneously.

4 The 31h command makes data of Page N + 1 transfer to Data Cache from Page Buffer after the completion of the transfer from cell to

Page Buffer. The device outputs Busy state for tDCBSYR1 max.

This Busy period depends on the combination of the internal data transfer time from cell to Page buffer and the serial data out time.

5 Data of Page N + 2 is transferred to Page Buffer from cell while the data of Page N + 1 in Data cache can be read out by  clock

simultaneously.

6 The 3Fh command makes the data of Page N + 2 transfer to the Data Cache from the Page Buffer after the completion of the transfer

from cell to Page Buffer. The device outputs Busy state for tDCBSYR1 max. This Busy period depends on the combination of the internal

data transfer time from cell to Page buffer and the serial data out time.

7 Data of Page N + 2 in Data Cache can be read out, but since the 3Fh command does not transfer the data from the memory cell to Page

Buffer, the device can accept new command input immediately after the completion of serial data out.

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Multi Page Read Operation

The device has a Multi Page Read operation and Multi Page Read with Data Cache operation.

(1) Multi Page Read without Data Cache

The sequence of command and address input is shown below.

Same page address (PA0 to PA5) within each district has to be selected.

For X8 :

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For X16 :

The data transfer operation from the cell array to the Data Cache via Page Buffer starts on the rising edge of

 in the 30h command input cycle (after the 2 Districts address information has been latched). The device will

be in the Busy state during this transfer period.

After the transfer period, the device returns to Ready state. Serial data can be output synchronously with the 

clock from the start address designated in the address input cycle.

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(2) Multi Page Read with Data Cache

When the block address changes (increments) this sequenced has to be started from the beginning.

The sequence of command and address input is shown below.

Same page address (PA0 to PA5) within each district has to be selected.

For X8 :

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For X16 :

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(3) Notes

(a) Internal addressing in relation with the Districts

To use Multi Page Read operation, the internal addressing should be considered in relation with the District.

• The device consists from 2 Districts.

• Each District consists from 1024 erase blocks.

• The allocation rule is follows.

District 0: Block 0, Block 2, Block 4, Block 6,···, Block 2046

District 1: Block 1, Block 3, Block 5, Block 7,···, Block 2047

(b) Address input restriction for the Multi Page Read operation

There are following restrictions in using Multi Page Read;

(Restriction)

Maximum one block should be selected from each District.

Same page address (PA0 to PA5) within two districts has to be selected.

For example;

(60) [District 0, Page Address 0x00000] (60) [District 1, Page Address 0x00040] (30)

(60) [District 0, Page Address 0x00001] (60) [District 1, Page Address 0x00041] (30)

(Acceptance)

There is no order limitation of the District for the address input.

For example, following operation is accepted;

(60) [District 0] (60) [District 1] (30)

(60) [District 1] (60) [District 0] (30)

It requires no mutual address relation between the selected blocks from each District.

(c)  signal

Make sure  is held to High level when Multi Page Read operation is performed

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Auto Page Program Operation

The device carries out an Automatic Page Program operation when it receives a "10h" Program command

after the address and data have been input. The sequence of command, address and data input is shown

below.

(Refer to the detailed timing chart.)

The data is transferred (programmed) from the Data Cache via the Page Buffer to the selected page on the

rising edge of  following input of the “10h” command. After programming, the programmed data is

transferred back to the Page Buffer to be automatically verified by the device.

If the programming does not succeed, the Program/Verify operation is repeated by the device until success is

achieved or until the maximum loop number set in the device is reached.

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Random Column Address Change in Auto Page Program Operation

The column address can be changed by the 85h command during the data input sequence of the Auto Page

Program operation.

Two address input cycles after the 85h command are recognized as a new column address for the data input.

After the new data is input to the new column address, the 10h command initiates the actual data program into

the selected page automatically. The Random Column Address Change operation can be repeated multiple

times within the same page.

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Multi Page Program

The device has a Multi Page Program, which enables even higher speed program operation compared to Auto

Page Program. The sequence of command, address and data input is shown below. (Refer to the detailed

timing chart.)

Although two planes are programmed simultaneously, pass/fail is not available for each page by "70h"

command when the program operation completes. Status bit of I/O 1 is set to “1” when any of the pages fails.

Limitation in addressing with Multi Page Program is shown below.

For X8 :

For X16 :

NOTE: Any command between 11h and 81h is prohibited except 70h and FFh.

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Auto Page Program Operation with Data Cache

The device has an Auto Page Program with Data Cache operation enabling the high speed program operation

shown below. When the block address changes this

sequenced has to be started from the beginning.

Issuing the 15h command to the device after serial data input initiates the program operation with Data Cache

1 Data for Page N is input to Data Cache.

2 Data is transferred to the Page Buffer by the 15h command. During the transfer the Ready/Busy outputs Busy State (tDCBSYW2).

3 Data is programmed to the selected page while the data for page N + 1 is input to the Data Cache.

4 By the 15h command, the data in the Data Cache is transferred to the Page Buffer after the programming of page N is completed. The

device output busy state from the 15h command until the Data Cache becomes empty. The duration of this period depends on timing

between the internal programming of page N and serial data input for Page N + 1 (tDCBSYW2).

5 Data for Page N + P is input to the Data Cache while the data of the Page N + P − 1 is being programmed.

6 The programming with Data Cache is terminated by the 10h command. When the device becomes Ready, it shows that the internal

programming of the Page N + P is completed.

NOTE: Since the last page programming by the 10h command is initiated after the previous cache program, the tPROG during cache

programming is given by the following;

tPROG = tPROG for the last page +tPROG of the previous page − ( command input cycle +address input cycle +data input cycle time of

the last page)

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Pass/fail status for each page programmed by the Auto Page Programming with Data Cache operation can be detected by the Status

Read operation.



I/O1 : Pass/fail of the current page program operation.

I/O2 : Pass/fail of the previous page program operation.

The Pass/Fail status on I/O1 and I/O2 are valid under the following conditions.



Status on I/O1: Page Buffer Ready/Busy is Ready State.

The Page Buffer Ready/Busy is output on I/O6 by Status Read operation or RY /  pin after the 10h command

Status on I/O2: Data Cache Read/Busy is Ready State.

The Data Cache Ready/Busy is output on I/O7 by Status Read operation or RY /  pin after the 15h command.

If the Page Buffer Busy returns to Ready before the next 80h command input, and if Status Read is done during

this Ready period, the Status Read provides pass/fail for Page 2 on I/O1 and pass/fail result for Page1 on I/O2

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Multi Page Program with Data Cache

The device has a Multi Page Program with Data Cache operation, which enables even higher speed program

operation compared to Auto Page Program with Data Cache as shown below. When the block address

changes (increments) this sequenced has to be started from the beginning.

The sequence of command, address and data input is shown below. (Refer to the detailed timing chart.)

For X8 :

For X16 :

After “15h” or “10h” Program command is input to device, physical programing starts as follows. For details

of Auto Program with Data Cache, refer to “Auto Page Program with Data Cache”.

The data is transferred (programmed) from the page buffer to the selected page on the rising edge of  following input of the “15h” or

“10h” command. After programming, the programmed data is transferred back to the register to be automatically verified by the device. If

the programming does not succeed, the Program/Verify operation is repeated by the device until success is achieved or until the maximum

loop number set in the device is reached.

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Starting the above operation from 1st page of the selected erase blocks, and then repeating the operation

total 64 times with incrementing the page address in the blocks, and then input the last page data of the

blocks, “10h” command executes final programming. Make sure to terminate with 81h-10h- command

sequence.

In this full sequence, the command sequence is following.

After the “15h” or “10h” command, the results of the above operation is shown through the “71h”Status Read

command.

The 71_HCommand Status Description

I/O

Status

Output

Pass : 0 / Fail : 1

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

Chip Status1 : Pass / Fail

Pass : 0 / Fail : 1

District 0 Chip Status1 : Pass / Fail

District 1 Chip Status2 : Pass / Fail

District 0 Chip Status1 : Pass / Fail

District 1 Chip Status2 : Pass / Fail

I/O 5

I/O 6

I/O 7

Ready / Busy

Data Cache Ready / Busy

Write Protect

Busy : 0 / Ready : 1

Protected : 0 / Not Protected : 1

I/O0 describes Pass/Fail condition of district 0 and 1 (OR data of I/O1 and I/O2). If one of the districts fails during multi

page program operation, it shows “Fail”.

I/O1 to I/O4 shows the Pass/Fail condition of each district. For details on “Chip Status 1” and “Chip Status2” refer to

section “Status Read”.

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Internal addressing in relation with the Districts

To use Multi Page Program operation, the internal addressing should be considered in relation with the

District.

• The device consists from 2 Districts.

• Each District consists from 1024 erase blocks.

• The allocation rule is follows.

District 0: Block 0, Block 2, Block 4, Block 6,···, Block 2046

District 1: Block 1, Block 3, Block 5, Block 7,···, Block 2047

Address input restriction for the Multi Page Program with Data Cache operation

There are following restrictions in using Multi Page Program with Data Cache;

(Restriction)

Maximum one block should be selected from each District.

Same page address (PA0 to PA5) within two districts has to be selected.

For example;

(80) [District 0, Page Address 0x00000] (11) (81) [District 1, Page Address 0x00040] (15 or 10)

(80) [District 0, Page Address 0x00001] (11) (81) [District 1, Page Address 0x00041] (15 or 10)

(Acceptance)

There is no order limitation of the District for the address input.

For example, following operation is accepted;

(80) [District 0] (11) (81) [District 1] (15 or 10)

(80) [District 1] (11) (81) [District 0] (15 or 10)

It requires no mutual address relation between the selected blocks from each District.

Operating restriction during the Multi Page Program with Data Cache operation

(Restriction)

The operation has to be terminated with “10h” command.

Once the operation is started, no commands other than the commands shown in the timing diagram is allowed

to be input except for Status Read command and reset command.

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Page Copy (2)

By using Page Copy (2), data in a page can be copied to another page after the data has been read out.

When the block address changes (increments) this sequenced has to be started from the beginning.

For X8 :

For X16 :

Pa

ge Copy (2) operation is as following.

1 Data for Page N is transferred to the Data Cache.

2 Data for Page N is read out.

3 Copy Page address M is input and if the data needs to be changed, changed data is input.

4 Data Cache for Page M is transferred to the Page Buffer.

5 After the Ready state, Data for Page N + P1 is output from the Data Cache while the data of Page M is being programmed.

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For X8 :

For X16 :

6 Copy Page address (M + R1) is input and if the data needs to be changed, changed data is input.

7 After programming of page M is completed, Data Cache for Page M + R1 is transferred to the Page Buffer.

8 By the 15h command, the data in the Page Buffer is programmed to Page M + R1. Data for Page N + P2 is transferred to the Data cache.

9 The data in the Page Buffer is programmed to Page M + Rn − 1. Data for Page N + Pn is transferred to the Data Cache.

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For X8 :

For X16 :

10 Copy Page address (M + Rn) is input and if the data needs to be changed, changed data is input.

11 By issuing the 10h command, the data in the Page Buffer is programmed to Page M + Rn.

(*1) Since the last page programming by the 10h command is initiated after the previous cache program, the tPROG here will be expected

as the following,

tPROG = tPROG of the last page + tPROG of the previous page − ( command input cycle + address input cycle + data output/input cycle

time of the last page)

NOTE) This operation needs to be executed within District-0 or District-1.

Data input is required only if previous data output needs to be altered.

If the data has to be changed, locate the desired address with the column and page address input after the 8Ch command, and

change only the data that needs be changed.

If the data does not have to be changed, data input cycles are not required.

Make sure  is held to High level when Page Copy (2) operation is performed.

Also make sure the Page Copy operation is terminated with 8Ch-10h command sequence

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Mutil Page Copy (2)

By using Multi Page Copy (2), data in two pages can be copied to other pages after the data has been read out.

When each block address changes (increments) this sequence has to be started from the beginning.

Same page address (PA0 to PA5) within two districts has to be selected.

For X8 :

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For X16 :

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Auto Block Erase

The Auto Block Erase operation starts on the rising edge of WE after the Erase Start command “D0h” which

follows the Erase Setup command “60h”. This two-cycle process for Erase operations acts as an extra layer of

protection from accidental erasure of data due to external noise. The device automatically executes the Erase

and Verify operations.

Multi Block Erase

The Multi Block Erase operation starts by selecting two block addresses before D0h command as in below

diagram. The device automatically executes the Erase and Verify operations and the result can be monitored

by checking the status by 71h status read command. For details on 71h status read command, refer to section

“Multi Page Program with Data Cache”.

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Internal addressing in relation with the Districts

To use Multi Block Erase operation, the internal addressing should be considered in relation with the District.

• The device consists from 2 Districts.

• Each District consists from 1024 erase blocks.

• The allocation rule is follows.

District 0: Block 0, Block 2, Block 4, Block 6,···, Block 2046

District 1: Block 1, Block 3, Block 5, Block 7,···, Block 2047

Address input restriction for the Multi Block Erase

There are following restrictions in using Multi Block Erase

(Restriction)

Maximum one block should be selected from each District.

For example;

(60) [District 0] (60) [District 1] (D0)

(Acceptance)

There is no order limitation of the District for the address input.

For example, following operation is accepted;

(60) [District 1] (60) [District 0] (D0)

It requires no mutual address relation between the selected blocks from each District.

Make sure to terminate the operation with D0h command. If the operation needs to be terminated before D0h

command input, input the FFh reset command to terminate the operation.

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ID Read

The device contains ID codes which can be used to identify the device type, the manufacturer, and features of

the device. The ID codes can be read out under the following timing conditions:

ID Definition Table (X8)

I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Hex Data

Description

1^stData

2^ndData

3^rdData

4^thData

5^thData

Maker Code

Device Code

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

98_H

AC_H

90_H

26_H

76_H

Chip Number, Cell Type

Page Size, Block Size, I/O Width

Plane Number

ID Definition Table (X16)

I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Hex Data

Description

1^stData

2^ndData

3^rdData

4^thData

5^thData

Maker Code

Device Code

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

98_H

BC_H

90_H

66_H

76_H

Chip Number, Cell Type

Page Size, Block Size, I/O Width

Plane Number

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3rd ID Data

Item

Description

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

1

2

4

8

0

1

0

1

0

1

Internal Chip Number

2 Level Cell

4 Level Cell

8 Level Cell

16 Level Cell

0

1

0

1

0

1

Cell Type

Reserved

1

0

1

4th ID Data

Item

Description

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

1 KB

2 KB

4 KB

0

1

0

1

0

1

Page Size

(without redundant area)

8 KB

64 KB

128 KB

256 KB

512 KB

X8

0

1

0

1

0

1

Block Size

(without redundant area)

0

1

I/O Width

Reserved

X16

0

1

5th ID Data

Item

Description

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

1 Plane

2 Plane

4 Plane

8 Plane

0

1

0

1

0

1

Plane Number

Reserved

0

1

0

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Status Read

The device automatically implements the execution and verification of the Program and Erase operations. The

status Read function is used to monitor the Ready/Busy status of the device, determine the result (pass/fail) of

a Program or Erase operation, and determine whether the device is in Protect mode. The device status is

output via the I/O port using  after a “70h” command input. The Status Read can also be used during a Read

operation to find out the Ready/Busy status.

Status Register Definition for ommand

I/O

Page Program

Block Erase

Read

Cache Read

Cache Program

Definition

Chip Status1

Pass : 0 / Fail : 1

Chip Status2

I/O 0

Pass / Fail

Invalid

Pass / Fail

I/O 1

Invalid

Pass / Fail

Pass : 0 / Fail : 1

I/O 2

I/O 3

I/O 4

0

Not Used

Page Buffer

Busy : 0 / Ready : 1

Data Cache

I/O 5

I/O 6

Ready / Busy

Busy : 0 / Ready : 1

Write Prot

I/O 7

Write Protect

Invalid

Write Protect

Invalid

Write Protect

Invalid

Write Protect

Invalid

Write Protect

Invalid

Protected : 0

/ Not Protected : 1

I/O 8 to 15

Not used

NOTE

The Pass/Fail status on I/O0 and I/O1 is only valid during a Program/Erase operation when the device is in the

Ready state.

Chip Status 1:

During a Auto Page Program or Auto Block Erase operation this bit indicates the pass/fail result.

During a Auto Page Programming with Data Cache operation, this bit shows the pass/fail results of the current

page program operation, and therefore this bit is only valid when I/O5 shows the Ready state.

Chip Status 2:

This bit shows the pass/fail result of the previous page program operation during Auto Page Programming with

Data Cache. This status is valid when I/O6 shows the Ready State.

The status output on the I/O5 is the same as that of I/O6 if the command input just before the 70h is not 15h or

31h.

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An application example with multiple devices is shown in the figure below.

System Design Note: If the  /  pin signals from multiple devices are wired together as shown in the

diagram, the Status Read function can be used to determine the status of each individual device.

Reset

The Reset mode stops all operations. For example, in case of a Program or Erase operation, the internally

generated voltage is discharged to 0 volt and the device enters the Wait state.

Reset during a Cache Program/Page Copy may not just stop the most recent page program but it may also

stop the previous program to a page depending on when the FF reset is input.

The response to a “FFh” Reset command input during the various device operations is as follows:

When a Reset (FFh) command is input during programming

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When a Reset (FFh) command is input during erasing

When a Reset (FFh) command is input during Read operation

When a Reset (FFh) command is input during Ready

When a Status Read command (70h) is input after a Reset

When two or more Reset commands are input in succession

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APPLICATION NOTES AND COMMENTS

(1)Power-on/off sequence

The timing sequence shown in the figure below is necessary for the power-on/off sequence.

The device internal initialization starts after the power supply reaches an appropriate level in the power on

sequence.

During the initialization the device Ready/Busy signal indicates the Busy state as shown in the figure below. In

this time period, the acceptable commands are FFh or 70h.

The  signal is useful for protecting against data corruption at power-on/off.

(2)Do not turn off the power before write/erase operation is complete. Avoid using the device when the battery

is low. Power shortage and/or power failure before write/erase operation is complete will cause loss of data

and/or damage to data.

(3)Power-on Reset

The following sequence is necessary because some input signals may not be stable at power-on.

(4)Prohibition of unspecified commands

The operation commands are listed in Logic Table. Input of a command other than those specified in Logic

Table is prohibited. Stored data may be corrupted if an unknown command is entered during the command

cycle.

(5)Restriction of commands while in the Busy state

During the Busy state, do not input any command except 70h(71h) and FFh.

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(6)Acceptable commands after Serial Input command “80h”

Once the Serial Input command “80h” has been input, do not input any command other than the Column

Address Change in Serial Data Input command “85h”, Auto Program command “10h”, Multi Page Program

command “11h”, Auto Program with Data Cache Command “15h”, or the Reset command “FFh”.

If a command other than “85h” , “10h” , “11h” , “15h” or “FFh” is input, the Program operation is not performed

and the device operation is set to the mode which the input command specifies.

(7)Addressing for Program Operation

Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the

block to MSB (most significant bit) page of the block. Random page address programming is prohibited.

Page 63

Page 31

Page 63

Page 31

(64)

‧

(1)

(32)

‧

Page2

Page 1

Page 0

Page2

Page 1

Page 0

(3)

(32)

(2)

(3)

(2)

(1)

Data Register

From the LSB page to MSB page

DATA IN: Data(1)  Data (64)

Ex.) Random page program (Prohibition)

DATA IN: Data(1)  Data (64)

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(8)Status Read during a Read operation

The device status can be read out by inputting the Status Read command “70h” in Read mode. Once the

device has been set to Status Read mode by a “70h” command, the device will not return to Read mode

unless the Read command “00h” is inputted during [A]. If the Read command “00h” is inputted during [A],

Status Read mode is reset, and the device returns to Read mode. In this case, data output starts

automatically from address N and address input is unnecessary

(9)Auto programming failure

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(10)RY /  : termination for the Ready/Busy pin (RY /  )

A pull-up resistor needs to be used for termination because the RY /  buffer consists of an open drain

circuit.

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(11)Note regarding the  signal

The Erase and Program operations are automatically reset when WP goes Low. The operations are

enabled and disabled as follows:

Enable Programming

Disable Programming

Enable Erasing

Disable Erasing

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(12)When six address cycles are input

Although the device may read in a sixth address, it is ignored inside the chip.

Read operation

Program operation

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(13)Several programming cycles on the same page (Partial Page Program)

Each segment can be programmed individually as follows:

1st Programming

2nd Programming

Data Pattern 1

All 1 s

Data Pattern 2

4th Programming

Result

All 1 s

Data Pattern 4

Data Pattern 1

Data Pattern 2

-------------------------------------

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(14)Invalid blocks (bad blocks)

The device occasionally contains unusable blocks. Therefore, the following issues must be recognized:

Please do not perform an erase operation to bad blocks. It may be impossible to recover

the bad block information if the information is erased.

Check if the device has any bad blocks after installation into the system.

Refer to the test flow for bad block detection. Bad blocks which are detected by the test

flow must be managed as unusable blocks by the system.

A bad block does not affect the performance of good blocks because it is isolated from

the bit lines by select gates.

The number of valid blocks over the device lifetime is as follows:

Symbol

Valid(Good) Block Number

Min

Typ.

－

Max

Unit

2,008

2,048

Blocks

Bad Block Test Flow

Regarding invalid blocks, bad block mark is in whole pages.

Please read one column of any page in each block. It makes sure that every invalid block has Majority “0” data

at this column. If the data of the column is Majority “0”, define the block as a bad block.

Start

Block No = 1

Fail

Read Check

Pass

Block No. = Block No. + 1

Bad Block¹

No

Last Block

Yes

End

Note1: No erase operation is allowed to detected bad blocks.

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(15)Failure phenomena for Program and Erase Operations

The device may fail during a Program or Erase operation.

The following possible failure modes should be considered when implementing a highly reliable system.

Failure Mode

Erase Failure

Programming Failure

Bit Error

Detection and Countermeasure Sequence

Read Status after Erase → Block Replacement

Read Status after Program → Block Replacement

ECC Correction / Block Refresh

Block

Page

Read

NOTE 1

ECC: Error Correction Code. 8 bit correction per 512 Bytes is necessary.

Block Replacement

Program

When an error happens in Block A, try to reprogram the data into another Block (Block B) by loading from an

external buffer. Then, prevent further system accesses to Block A (by creating a bad block table or by using

another appropriate scheme).

Erase

When an error occurs during an Erase operation, prevent future accesses to this bad block (again by creating a

table within the system or by using another appropriate scheme).

(16)The number of valid blocks is on the basis of single plane operations, and this may be decreased with two

plane operations.

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(17)Reliability Guidance

This reliability guidance is intended to notify some guidance related to using NAND flash with 8bit ECC for each

512 bytes. For detailed reliability data, please refer to TOSHIBA’s reliability note.

Although random bit errors may occur during use, it does not necessarily mean that a block is bad.

Generally, a block should be marked as bad when a program status failure or erase status failure is detected.

The other failure modes may be recovered by a block erase.

ECC treatment for read data is mandatory due to the following Data Retention and Read Disturb failures.

 Write/Erase Endurance

Write/Erase endurance failures may occur in a cell, page, or block, and are detected by doing a status read

after either an auto program or auto block erase operation. The cumulative bad block count will increase

along with the number of write/erase cycles.

 Data Retention

The data in memory may change after a certain amount of storage time. This is due to charge loss or charge

gain. After block erasure and reprogramming, the block may become usable again.

Here is the combined characteristics image of Write/Erase Endurance and Data Retention.

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TIMING DIAGRAMS

Latch Timing Diagram for Command/Address/Data

Command Input Cycle Timing Diagram

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Address Input Cycle Timing Diagram

Data Input Cycle Timing Diagram

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Serial Read Cycle Timing Diagram

Status Read Cycle Timing Diagram

*: 70h represents the hexadecimal number

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Read Cycle Timing Diagram

Read Cycle Timing Diagram: When Interrupted by 

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Read Cycle with Data Cache Timing Diagram (1/2)

*: The column address will be reset to 0 by the 31h command input.

Read Cycle with Data Cache Timing Diagram (2/2)

Make sure to terminate the operation with 3Fh command

.

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Column Address Change in Read Cycle Timing Diagram (1/2)

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Column Address Change in Read Cycle Timing Diagram (2/2)

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Data Output Timing Diagram

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Auto-Program Operation Timing Diagram

*: M: up to 4351 (byte input data for ×8 device).

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Auto-Program Operation with Data Cache Timing Diagram (1/3)

CA0 to CA12 is 0 in this diagram.

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Auto-Program Operation with Data Cache Timing Diagram (2/3)

Repeat a max of 62 times

(in order to program pages 1 to 62 of a block).

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Auto-Program Operation with Data Cache Timing Diagram (3/3)

(*1)

tPROG: Since the last page programming by 10h command is initiated after the previous cache

program, the tPROG during cache programming is given by the following equation.

tPROG = tPROG of the last page + tPROG of the previous page − A

A = (command input cycle + address input cycle + data input cycle time of the last page)

If “A” exceeds the tPROG of previous page, tPROG of the last page is tPROG max.

NOTE : Make sure to terminate the operation with 80h-10h- command sequence.

If the operation is terminated by 80h-15h command sequence, monitor I/O 6 (Ready / Busy) by

issuing Status Read command (70h) and make sure the previous page program operation is

completed. If the page program operation is completed issue FFh reset before next operation.

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Multi-Page Program Operation with Data Cache Timing Diagram (1/4)

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Multi-Page Program Operation with Data Cache Timing Diagram (2/4)

Repeat a max of 63 times

(in order to program pages 0 to 62 of a block).

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Multi-Page Program Operation with Data Cache Timing Diagram (3/4)

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Multi-Page Program Operation with Data Cache Timing Diagram (4/4)

(*1)

tPROG: Since the last page programming by 10h command is initiated after the previous cache

program, the tPROG during cache programming is given by the following equation.

tPROG = tPROG of the last page + tPROG of the previous page − A

A = (command input cycle + address input cycle + data input cycle time of the last page)

If “A” exceeds the tPROG of previous page, tPROG of the last page is tPROG max.

NOTE : Make sure to terminate the operation with 81h-10h- command sequence.

If the operation is terminated by 81h-15h command sequence, monitor I/O 6 (Ready / Busy)

by issuing Status

Read command (70h) and make sure the previous page program operation is completed.

If the page program operation is completed issue FFh reset before next operation.

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Auto Block Erase Timing Diagram

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Multi Block Erase Timing Diagram

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ID Read Operation Timing Diagram

Table 5: ID Definition Table

4Gb(X32, SDP)/8Gb(X32, DDP) LPDDR2

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LPDDR2 Descriptions

LPDDR2-S4 uses the double data rate architecture on the Command/Address (CA) bus to reduce the number

of input pins in the system. The 10-bit CA bus contains command, address, and Bank/Row Buffer information.

Each command uses one clock cycle, during which command information is transferred on both the positive

and negative edge of the clock.

To achieve high-speed operation, our LPDDR2-S4 SDRAM uses the double data rate architecture and adopt

4n-prefetch interface designed to transfer two data per clock cycle at the I/O pins. A single read or write

access for the LPDDR2-S4 effectively consists of a single 4n-bit wide, one clock cycle data transfer at the

internal SDRAM core and four corresponding n-bit wide, one-half-clock-cycle data transfer at the I/O pins.

Read and write accesses to the LPDDR2-S4 are burst oriented; accesses start at a selected location and

continue for a programmed number of locations in a programmed sequence.

For LPDDR2-S4 devices, accesses begin with the registration of an Active command, which is then followed

by a Read or Write command. The address and BA bits registered coincident with the Active command are

used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or

Write command are used to select the Bank and the starting column location for the burst access.

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Absolute Maximum Ratings

Symbol

Parameter

Min

Max

Units

V

V_DD1

V_DD2

Voltage on V_DD1pin relative to Vss

Voltage on V_DD2pin relative to Vss

Voltage on V_DDCApin relative to Vss

Voltage on V_DDQpin relative to Vss

Voltage on any pin relative to Vss

Storage Temperature (plastic)

-0.4

-55

2.3

1.6

V

V_DDCA

V_DDQ

1.6

V

1.6

V

Vin, Vout

Tstg

1.6

+125

C

Notes:

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or any other conditions above those indicated in the

operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended

periods may affect reliability.

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For measurement conditions,

refer to the JESD51-2 standard.

3. VDD2 and VDDQ / VDDCA must be within 200mV of each other at all times.

4. Voltage on any I/O may not exceed voltage on VDDQ; Voltage on any CA input may not exceed voltage on VDDCA.

5. VREF must always be less than all other supply voltages.

6. The voltage difference between any VSS pins may not exceed 100mV.

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AC/DC Operating Conditions

DC Operating Conditions

Symbol

Parameter

Min

Typical

Max

Unit

Notes

Power Supply

1.70

1.14

1.80

1.20

1.95

1.30

V

V_DD1

V_DD2

Core Supply voltage 1

Core Supply voltage 2

V_DDCA

V_DDQ

Leakage current

Input leakage current

Input Supply Voltage (Command / Address)

I/O Supply voltage (DQ)

Any input 0 ≦ V_IN≦ V_DDQ/ V_DDCA

,

-2

-1

-

2

1

uA

1

I_I

All other pins not under test = 0V

V_REFleakage current; V_REFDQ= V_DDQ/2 or

V_REFCA= V_DDCA/2 (all other pins not under test

= 0V)

I_VREF

Notes:

1. The minimum limit requirement is for testing purposes. The leakage current on VREFCA and VREFDQ pins should be minimal.

Although DM is for input only, the DM leakage shall match the DQ and DQS,  output leakage specification.

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AC/DC Input Measurement Level

AC and DC Logic Levels for Single-Ended Signals

CA inputs (Address and Command) and  inputs

LPDDR2 1066

Symbol

Parameter

Unit Notes

Min

Max

AC Input logic HIGH voltage

DC Input logic HIGH voltage

AC Input logic LOW voltage

DC Input logic LOW voltage

mV

V

1,3

1

V_IHCA(AC)

V_IHCA(DC)

V_ILCA(AC)

V_ILCA(DC)

V_REFCA(DC)

V_REFCA+ 220 mV

-

V_REFCA+ 130 mV

V_DDCA

1,3

1

-

V_REFCA– 220 mV

V_REFCA– 130 mV

0.51 x V_DDCA

V_SS

Reference voltage for CA and 

4,5

0.49 x V_DDCA

inputs

Data inputs (DQ & DM)

AC Input logic HIGH voltage

mV

V

2,3

1

V_IHDQ(AC)

V_IHDQ(DC)

V_ILDQ(AC)

V_ILDQ(DC)

V_REFDQ(DC)

V_REFDQ+ 220 mV

-

DC Input logic HIGH voltage

AC Input logic LOW voltage

DC Input logic LOW voltage

V_REFDQ+ 130 mV

V_DDQ

2,3

1

-

V_REFDQ– 220 mV

V_REFDQ– 130 mV

0.51 x V_DDQ

V_SS

Reference voltage for DQ and DM

inputs

4,5

0.49 x V_DDQ

Clock enable inputs (CKE)

Symbol

Parameter

Min

Max

Unit Notes

CKE AC Input HIGH voltage

CKE AC Input LOW voltage

V

3

V_{IHCKE (AC)}

V_{ILCKE (AC)}

0.8 * V_DDCA

-

0.2 * V_DDCA

NOTE 1 For CA and  input only pins. Vref = VrefCA(DC).

NOTE 2 For DQ input only pins. Vref = VrefDQ(DC).

NOTE 3 See “Overshoot and Undershoot Specifications”

NOTE 4 The ac peak noise on VRefCA may not allow VRefCA to deviate from VRefCA(DC) by more than +/-1% VDDCA (for reference:

approx. +/- 12 mV).

NOTE 5 For reference: approx. VDDCA/2 +/- 12 mV.

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NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

Differential AC and DC Input Levels

Differential Inputs logical levels (CK,  – V_REF= V_REFCA(DC); DQS, : V_REF= V_REFDQ(DC)

)

LPDDR2 1066

Symbol

Parameter

Unit

Min

Max

Differential input voltage HIGH AC

Differential input voltage LOW AC

Differential input voltage HIGH DC

Differential input voltage LOW DC

2 x (V_IH(AC)-V_REF

)

Note 3

2 x (V_REF-V_IL(AC)

Note 3

V_IHdiff(AC)

V_ILdiff(AC)

V_IHdiff(DC)

V_ILdiff(DC)

V

Note 3

)

V

2 x (V_IH(DC)-V_REF

)

Note 3

2 x (V_REF-V_IL(DC)

)

Notes:

1. Used to define a differential signal slew-rate. For CK –  use VIH/VIL(dc) of CA and VREFCA; for DQS – , use VIH/VIL(dc) of

DQs and VREFDQ; if a reduced dc-high or dc-low level is used for a signal group, then the reduced level applies also here.

2. For CK and , use V_IH/VIL(AC)of CA and V_REFCA; for DQS and , use V_IH/VIL(AC)of DQ and V_REFDQ. If a reduced AC HIGH or AC

LOW is used for a signal group, the reduced voltage level also applies.

3. These values are not defined, however the single-ended signals CK, , DQS, and  must be within the respective limits

(V_IH(DC)max, V_IL(DC)min) for single-ended signals and must comply with the specified limitations for overshoot and undershoot.

CK,  and DQS,  Time Requirement before Ring back (t_DVAC

)

t_DVAC(ps) at

Slew Rate

V_IH/V_ILdiff(AC)= 440 mV

(V/ns)

Min

175

170

167

163

162

161

159

155

150

>4.0

4.0

3.0

2.0

1.8

1.6

1.4

1.2

1.0

<1.0

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Single-Ended Requirements for Differential Signals

LPDDR2 1066

Symbol

Parameter

Unit

Min

Max

Single-ended HIGH level for strobes

Single-ended HIGH level for CK, 

Single-ended LOW level for strobes

Single-ended LOW level for CK, 

(V_DDQ/2) + 0.22

Note 3

V

V_SEH(AC)

(V_DDCA/2) + 0.22

Note 3

(V_DDQ/2) - 0.22

(V_DDCA/2) - 0.22

V

V_SEL(AC)

Note 3

Notes:

1. For CK and , use VSEH/VSEL(AC) of CA; for strobes (DQS[3:0] and [3:0]) use VIH/VIL(AC) of DQ.

2. VIH(AC) and VIL(AC) for DQ are based on VREFDQ; VSEH(AC) and VSEL(AC) for CA are based on VREFCA. If a reduced AC HIGH or AC

LOW is used for a signal group, the reduced level applies.

3. These values are not defined, however the single-ended signals CK, , DQS0, , DQS1, , DQS2, , DQS3,

 must be within the respective limits (VIH(DC)max, VIL(DC)min) for single-ended signals, and must comply with the

specified limitations for overshoot and undershoot.

Differential input Cross-Point Voltage

LPDDR2 1066

Symbol

Parameter

Unit

Min

Max

Differential input cross-point voltage relative to VDDCA/2 for CK and 

Differential input cross-point voltage relative to VDDQ/2 for DQS and 

-120

+120

mV

V_IXCA(AC)

-120

+120

V_IXDQ(AC)

Notes:

1. The typical value of VIX(AC) is expected to be about 0.5 × VDD of the transmitting device, and it is expected to track variations

in VDD. VIX(AC) indicates the voltage at which differential input signals must cross.

2. For CK and , VREF = VREFCA(DC). For DQS and , VREF = VREFDQ(DC).

Slew Rate Definitions for Differential Input Signals

Measured

Description

Defined by

From

To

Differential input slew rate for rising edge

(CK,  and DQS, )

[VIHdiffmin – VILdiffmax] / ΔTRdiff

[VIHdiffmin – VILdiffmax] / ΔTFdiff

VILdiffmax

VIHdiffmin

Differential input slew rate for falling edge

(CK,  and DQS, )

VIHdiffmin

VILdiffmax

Notes:

1. The differential signals (CK,  and DQS, ) must be linear between these thresholds.

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AC/DC Output Measurement Level

Single-Ended AC and DC Output Levels

Symbol

Parameter

LPDDR2 1066

Unit Notes

VREF + 0.12

VREF – 0.12

0.9 x VDDQ

0.1 x VDDQ

-5

V

VOH(AC)

AC output HIGH measurement level (for output slew rate)

AC output LOW measurement level (for output slew rate)

DC output HIGH measurement level (for I-V curve linearity)

DC output LOW measurement level (for I-V curve linearity)

VOL(AC)

VOH(DC)

VOL(DC)

V

1

2

Min

uA

Output leakage current (DQ, DM, DQS, )

(DQ, DQS,  are disabled; 0V ≤ VOUT ≤ VDDQ)

IOZ

Max

5

Min

-15

15

%

Delta output impedance between pull-up and pull-down

for DQ/DM

MMpupd

Max

Notes:

1. I_OH= –0.1mA

2. I_OL= 0.1mA

Differential AC and DC Output Levels

Symbol

Parameter

LPDDR2 1066

Unit Notes

+ 0.20 x VDDQ

- 0.20 x VDDQ

V

1

2

VOHdiff(AC)

AC differential output HIGH measurement level (for output SR)

AC differential output LOW measurement level (for output SR)

VOLdiff(AC)

Notes:

1. I_OH= –0.1mA

2. I_OL= 0.1mA

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Single Ended Output Slew Rate

LPDDR2 1066

Symbol

Parameter

Unit

Min

Max

Single-ended output slew rate (output impedance = 40Ω ± 30%)

Single-ended output slew rate (output impedance = 60Ω ± 30%)

Output slew-rate-matching ratio (pull-up to pull-down)

1.5

3.5

V/ns

SRQSE

1.0

0.7

2.5

1.4

Definitions:

SR = slew rate, Q = query output (similar to DQ = data-in, query-output), se = single-ended signals

NOTE 1 Measured with output reference load.

NOTE 2 The ratio of pull-up to pull-down slew rate is specified for the same temperature and voltage, over the entire

temperature and voltage range. For a given output, it represents the maximum difference between pull-up and

pull-down drivers due to process variation.

NOTE 3 The output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC).

NOTE 4 Slew rates are measured under normal SSO conditions, with 1/2 of DQ signals per data byte driving logic-high and 1/2 of

DQ signals per data byte driving logic-low.

Differential Output Slew Rate

LPDDR2 1066

Symbol

Parameter

Unit

Min

Max

3.0

7.0

V/ns

SRQdiff

Differential output slew rate (output impedance = 40Ω ± 30%)

Differential output slew rate (output impedance = 60Ω ± 30%)

2.0

5.0

SRQdiff

Definitions:

SR = slew rate, Q = query output (similar to DQ = data-in, query-output), diff = differential signals

NOTE 1 Measured with output reference load.

NOTE 2 The output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC).

NOTE 3 Slew rates are measured under normal SSO conditions, with 1/2 of DQ signals per data byte driving logic-high and 1/2 of

DQ signals per data byte driving logic-low.

AC Overshoot/Undershoot Specification

Parameter

1066

Unit

Maximum peak amplitude provided for overshoot area

Maximum peak amplitude provided for undershoot area

Maximum area above VDD

Max

0.35

0.15

V

V-ns

Maximum area below VSS

Notes:

1. VDD stands for VDDCA for CA[9:0], CK, , , and CKE. VDD stands for VDDQ for DQ, DM, DQS, and .

2. Values are referenced from actual VDDQ and VDDCA levels.

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Input / Output Capacitance

TOPER; VDDQ = 1.14-1.3V; VDDCA = 1.14-1.3V; VDD1 = 1.7-1.95V

LPDDR2 1066

Symbol

C_CK

C_DCK

C_I

Parameter

Unit

Min

Max

Input capacitance :

0.5

2

pF

CK, 

Input capacitance delta :

CK, 

0

1

0.2

2

Input capacitance:

all other input-only pins

Input capacitance delta:

all other input-only pins

-0.4

1.25

0.4

2.5

C_DI

Input/output capacitance :

C_IO

DQ, DQS, , DM

0

-0.5

0

0.25

0.5

pF

Input/output capacitance delta : DQS, 

Input/output capacitance delta : DQ, DM

Input/output capacitance : ZQ

C_DDQS

C_DIO

C_ZQ

2.5

Notes:

1. This parameter applies to die devices only (does not include package capacitance).

2. This parameter is not subject to production testing. It is verified by design and characterization. The capacitance is measured

according to JEP147 (procedure for measuring input capacitance using a vector network analyzer), with VDD1, VDD2, VDDQ,

VSS applied; all other pins are left floating.

3. Absolute value of CCK - .

4. CI applies to , CKE, and CA[9:0].

5. CDI = CI – 0.5 × (CCK + )

6. DM loading matches DQ and DQS.

7. MR3 I/O configuration DS OP[3:0] = 0001B (34.3 ohm typical)

8. Absolute value of CDQS and .

9. CDIO = CIO – 0.5 × (CDQS + ) in byte-lane.

10. Maximum external load capacitance on ZQ pin, including packaging, board, pin, resistor, and other LPDDR2 devices: 5pf.

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IDD Specifications and Measurement Conditions

VDD2/VDDQ/VDDCA = 1.14~1.30V; VDD1 = 1.70~1.95V

1066

Symbol

Supply

Unit

SDP

15

DDP

30

I_DD01

I_DD02

V_DD1

V_DD2

IDD0

70

140

20

mA

I_DD0IN

V_DDCA+ V_DDQ

V_DD1

10

I_DD2P1

I_DD2P2

I_DD2PIN

I_DD2PS1

I_DD2PS2

I_DD2PSIN

I_DD2N1

600

800

120

600

800

120

2

1200

1600

240

1200

1600

240

4

IDD2P

V_DD2

uA

V_DDCA+ V_DDQ

V_DD1

IDD2PS

IDD2N

V_DD2

uA

mA

V_DDCA+ V_DDQ

V_DD1

I_DD2N2

I_DD2NIN

I_DD2NS1

V_DD2

V_DDCA+ V_DDQ

V_DD1

20

40

10

20

1.7

3.4

IDD2NS

I_DD2NS2

I_DD2NSIN

I_DD3P1

V_DD2

V_DDCA+ V_DDQ

V_DD1

10

6

20

12

1000

7.5

150

1200

7.5

150

2

2000

15

uA

mA

uA

mA

uA

IDD3P

IDD3PS

IDD3N

I_DD3P2

V_DD2

I_DD3PIN

I_DD3PS1

I_DD3PS2

I_DD3PSIN

I_DD3N1

I_DD3N2

I_DD3NIN

I_DD3N1

I_DD3N2

I_DD3SIN

I_DD4R1

I_DD4R2

I_DD4RIN

V_DDCA+ V_DDQ

V_DD1

300

2400

15

V_DD2

V_DDCA+ V_DDQ

V_DD1

300

4

V_DD2

25

50

mA

V_DDCA+ V_DDQ

V_DD1

10

20

2

4

IDD3NS

IDD4R

V_DD2

20

40

V_DDCA+ V_DDQ

V_DD1

6

12

3

6

V_DD2

250

10

500

20

V_DDCA

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1066

Symbol

Supply

Unit

SDP

3

DDP

6

I_DD4W1

I_DD4W2

I_DD4WIN

I_DD51

V_DD1

V_DD2

IDD4W

250

35

500

70

mA

V_DDCA+ V_DDQ

V_DD1

20

40

IDD5

IDD5AB

IDD5PB

IDD6

I_DD52

V_DD2

150

10

300

20

mA

uA

I_DD5IN

V_DDCA+ V_DDQ

V_DD1

I_DD5AB1

I_DD5AB2

I_DD5ABIN

I_DD5PB1

I_DD5PB2

I_DD5PBIN

I_DD61

5

10

V_DD2

25

50

V_DDCA+ V_DDQ

V_DD1

10

20

5

10

V_DD2

25

50

V_DDCA+ V_DDQ

V_DD1

10

20

1000

4000

120

2000

8000

240

I_DD62

V_DD2

I_DD6IN

V_DDCA+ V_DDQ

Continue to next page

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IDD Specifications and Measurement Conditions

VDD2/VDDQ/VDDCA = 1.14~1.30V; VDD1 = 1.70~1.95V

IDD6 Partial Array Self-refresh current;

1066

PASR

Supply

Unit

SDP

1000

4000

120

DDP

2000

8000

240

V_DD1

V_DD2

Full Array

V_DDCA+ V_DDQ

V_DD1

950

1900

4600

240

1/2 Array

1/4 Array

1/8 Array

V_DD2

2300

120

V_DDCA+ V_DDQ

V_DD1

uA

900

1800

3000

240

V_DD2

1500

120

V_DDCA+ V_DDQ

V_DD1

850

1700

2120

240

V_DD2

1060

120

V_DDCA+ V_DDQ

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LPDDR2-S4 Refresh Requirement Parameters

Symbol

Parameter

4Gb (SDP)

8Gb (DDP)

Unit

8

Number of banks

tREFW

R

32

ms

Refresh window: TCASE ≤ 85°

8192

3.9

8192

3.9

Required number of REFRESH commands (MIN)

tREFI

us

ns

us

Average time between REFRESH commands

TCASE ≤ 85°C

tREFIpb

tRFCab

tRFCpb

tREFBW

0.4875

130

0.4875

130

Refresh cycle time

60

Per-bank REFRESH cycle time

Burst REFRESH window = 4 × 8 × tRFCab

4.16

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Electrical Characteristics and Recommended AC Timing

V_DD2,V_DDQ,V_DDCA= 1.14~1.30V; V_DD1= 1.70~1.95V

min/

Parameter

1066

Unit

Symbol

max

Clock Timing

533

MHz

ns

Max. Frequency

~

1.875

min

max

min

max

min

max

min

max

min

max

Average Clock Period

tCK(avg)

tCH(avg)

100

ns

0.45

tCK(avg)

ps

Average high pulse width

0.55

0.45

Average low pulse width

Absolute Clock Period

tCL(avg)

tCK(abs)

0.55

tCK(avg)min + tJIT(per),min

0.43

0.57

0.43

0.57

tCK(avg)

Absolute clock HIGH pulse width

(with allowed jitter)

tCH(abs),

allowed

Absolute clock LOW pulse width

(with allowed jitter)

tCL(abs),

allowed

min/

max

Parameter

1066

Unit

Symbol

-90

90

ps

min

Clock Period Jitter

(with allowed jitter)

tJIT(per),

allowed

max

Maximum Clock Jitter between two

consecutive clock cycles

(with allowed jitter)

tJIT(cc),

allowed

180

ps

max

min

min((tCH(abs),min - tCH(avg),min), (tCL(abs),min - tCL(avg),min)) *

ps

tCK(avg)

max((tCH(abs),max - tCH(avg),max), (tCL(abs),max - tCL(avg),max)) *

tCK(avg)

Duty cycle Jitter

tJIT(duty),

allowed

(with allowed jitter)

max

-132

132

-157

157

-175

175

ps

min

max

min

tERR(2per),

allowed

Cumulative error across 2 cycles

Cumulative error across 3 cycles

Cumulative error across 4 cycles

tERR(3per),

allowed

max

min

tERR(4per),

allowed

max

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min/

Parameter

1066

Unit

Symbol

max

-188

188

-200

200

-209

209

-217

217

-224

224

-231

231

-237

237

-242

242

ps

min

max

min

max

min

max

min

max

min

max

min

max

min

max

min

max

min

max

tERR(5per),

allowed

Cumulative error across 5 cycles

Cumulative error across 6 cycles

Cumulative error across 7 cycles

Cumulative error across 8 cycles

Cumulative error across 9 cycles

Cumulative error across 10 cycles

Cumulative error across 11 cycles

Cumulative error across 12 cycles

tERR(6per),

allowed

tERR(7per),

allowed

tERR(8per),

allowed

tERR(9per),

allowed

tERR(10per),

allowed

tERR(11per),

allowed

tERR(12per),

allowed

tERR(nper), allowed, min = (1 + 0.68ln(n)) * tJIT(per), allowed, min

tERR(nper), allowed, max = (1 + 0.68ln(n)) * tJIT(per), allowed, max

ps

Cumulative error across n = 13,

14 . . . 49, 50 cycles

tERR(nper),

allowed

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Electrical Characteristics and Recommended AC Timing

V_DD2,V_DDQ,V_DDCA= 1.14~1.30V; V_DD1= 1.70~1.95V

Speed Grade

min/ min

Symbol

Parameter

Unit

max ^tCK

1066

ZQ calibration parameters

tZQINIT

tZQCL

Calibration initialization Time

min

1

us

ns

Long (Full) Calibration Time

Short Calibration Time

Calibration Reset Time

6

3

360

90

tZQCS

tZQRESET

50

Read parameters

min

max

2500

5500

330

ps

DQS output access time from CK, 

tDQSCK

tDQSCKDS

tDQSCKDM

tDQSCKDL

DQSCK Delta Short

DQSCK Delta Medium

DQSCK Delta Long

680

920

DQS-DQ skew, DQS to last DQ valid, per group,

per access

tDQSQ

max

200

ps

tQHS

tQSH

tQSL

tQHP

tQH

Data Hold Skew Factor

max

min

230

ps

tCK(avg)

DQS output HIGH pulse width

DQS output LOW pulse width

Data half period

tCH(abs) - 0.05

tCL(abs) - 0.05

min(tQSH, tQSL)

tQHP - tQHS

Speed Grade

1066

tCK(avg)

DQ / DQS output hold time from DQS

ps

min/ min

max ^tCK

Symbol

Parameter

Unit

Read parameters

tCK(avg)

tRPRE

tRPST

READ Preamble

min

0.9

READ Postamble

DQS Low-Z from CK

tCL(abs) - 0.05

tDQSCK_min– 300

tLZ(DQS)

ps

tDQSCK(MIN) – (1.4 ×

tLZ(DQ)

tHZ(DQS)

tHZ(DQ)

DQ Low-Z from CK

DQS High-Z from CK

DQ High-Z from CK

min

max

tQHS(MAX))

tDQSCK_max– 100

tDQSCK(MAX) + (1.4 ×

tDQSQ(MAX))

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Speed Grade

min/ min

Symbol

Parameter

Unit

max ^tCK

1066

Write parameters

tDH

tDS

DQ and DM input hold time (V_REFbased)

DQ and DM input setup time (V_REFbased)

DQ and DM input pulse width

min

210

0.35

0.75

1.25

0.4

ps

tCK(avg)

tDIPW

tCK(avg)

Write command to 1^stDQS latching transition

tDQSS

max

min

tDQSH

tDQSL

tDSS

DQS input high-level width

min

DQS input low-level width

0.4

DQS falling edge to CK setup time

DQS falling edge hold time from CK

0.2

tDSH

min

0.2

tWPST

tWPRE

Write postamble

Write preamble

0.4

0.35

Speed Grade

1066

min/ min

max ^tCK

Symbol

Parameter

Unit

CKE input parameters

tCK(avg)

tCKE

CKE min. pulse width (high and low)

CKE input setup time

min

3

tISCKE

tIHCKE

0.25

CKE input hold time

Command / Address Input parameters

tIH

tIS

Address and Control input hold time

min

220

0.4

ps

Address and Control input setup time

Address and Control input pulse width

ps

tCK(avg)

tIPW

Mode register parameters

tCK(avg)

tMRR

tMRW

MODE Register Read command period

MODE Register Write command period

min

2

5

2

5

SDRAM core parameters

tCK(avg)

RL

Read Latency

Write Latency

min

3

1

8

4

WL

CKE minimum pulse width during SELF REFRESH

(low pulse width during SELF REFRESH)

tCKESR

tXSR

min

3

2

15

ns

Exit SELF REFRESH to first valid command (min)

tRFC_AB+10

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4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

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Speed Grade

min/ min

Symbol

Parameter

Unit

max ^tCK

SDRAM core parameters

1066

tXP

Exit power-down mode to first valid command

Minimum Deep Power-Down time

min

2

-

7.5

500

50

ns

us

ns

tDPD

tFAW

tWTR

Four-Bank Activate Window

8

2

Internal WRITE to READ command delay

7.5

tRAS + tRPAB (with all-bank Precharge)

tRAS + tRPPB (with per-bank Precharge)

tRC

ACTIVE to ACTIVE command period

min

ns

tCK(avg)

tCCD

tRTP

tRCD

CAS-to-CAS delay

min

max

min

2

3

-

2

Internal READ to PRECHARGE command delay

RAS-to-CAS delay

7.5

18

42

70

15

18

ns

us

ns

tRAS

Row Active Time

tWR

Write recovery time

3

tRPpb

PRECHARGE command period (single bank)

PRECHARGE command period

tRPab

tRRD

min

3

2

21

10

ns

(all banks – 8bank)

ACTIVE bank-a to ACTIVE bank-b command

min/ min

max ^tCK

Speed Grade

1066

Symbol

Parameter

Unit

Boot parameters (10MHz ~ 55MHz)

min

max

min

18

100

2.5

ns

ps

ns

tCKb

Clock cycle time

tISCKEb

tIHCKEb

tISb

CKE input setup time

CKE input hold time

Input setup time

2.5

1150

2.0

tIHb

Input hold time

tDQSCKb

Access window of DQS from CK, 

max

10.0

1.2

tDQSQb

tQHSb

DQS-DQ skew

Data hold skew factor

1.2

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NTC Proprietary

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Notes for Electrical Characteristics and Recommended AC Timing

1. Frequency values are for reference only. Clock cycle time (tCK) is used to determine device capabilities.

2. All AC timings assume an input slew rate of 1 V/ns.

3. READ, WRITE, and input setup and hold values are referenced to VREF.

4. tDQSCKDS is the absolute value of the difference between any two tDQSCK measurements (in a byte lane) within a contiguous

sequence of bursts in a 160ns rolling window. tDQSCKDS is not tested and is guaranteed by design. Temperature drift in the system

is < 10°C/s. Values do not include clock jitter.

5. tDQSCKdm is the absolute value of the difference between any two tDQSCK measurements (in a byte lane) within a 1.6μs rolling

window. tDQSCKdm is not tested and is guaranteed by design. Temperature drift in the system is < 10 °C/s. Values do not include

clock jitter.

6. tDQSCKDL is the absolute value of the difference between any two tDQSCK measurements (in a byte lane) within a 32ms rolling

window. tDQSCKDL is not tested and is guaranteed by design. Temperature drift in the system is < 10 °C/s. Values do not include

clock jitter.

7. For LOW-to-HIGH and HIGH-to-LOW transitions, the timing reference is at the point when the signal crosses the transition threshold

(VTT). tHZ and tLZ transitions occur in the same access time (with respect to clock) as valid data transitions. These parameters are

not referenced to a specific voltage level but to the time when the device output is no longer driving (for tRPST, tHZ(DQS) and

tHZ(DQ)), or begins driving (for tRPRE, tLZ(DQS), tLZ(DQ)). Figure shows a method to calculate the point when device is no longer

driving tHZ (DQS) and tHZ (DQ), or begins driving tLZ (DQS), tLZ (DQ) by measuring the signal at two different voltages. The actual

voltage measurement points are not critical as long as the calculation is consistent.

Data Out measurement reference points

The parameters tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) are defined as single-ended. The timing parameters tRPRE and

tRPST are determined from the differential signal DQS, .

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Notes for Electrical Characteristics and Recommended AC Timing

8. Measured from the point when DQS,  begins driving the signal to the point when DQS,  begins driving the first rising strobe

edge.

9. Measured from the last falling strobe edge of DQS,  to the point when DQS,  finishes driving the signal.

10. CKE input setup time is measured from CKE reaching a HIGH/LOW voltage level to CK,  crossing.

11. CKE input hold time is measured from CK,  crossing to CKE reaching a HIGH/LOW voltage level.

12. Input set-up/hold time for signal (CA[9:0], ).

13. To ensure device operation before the device is configured, a number of AC boot-timing parameters are defined in this table. Boot

parameter symbols have the letter b appended (for example, tCK during boot is tCKb).

14. The LPDDR device will set some mode register default values upon receiving a RESET command as specified in “Mode Register

Definition”.

15. The output skew parameters are measured with default output impedance settings using the reference load.

16. The minimum tCK column applies only when tCK is greater than 6ns.

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CA and  Setup and Hold Base Values

Data Rate

Parameter

Reference

1066

0

VIH/VIL(AC) = VREF(DC) ± 220 mV

VIH/VIL(DC) = VREF(DC) ± 130 mV

tIS (base)

90

tIH (base)

Notes: AC/DC referenced for 1 V/ns CA and  slew rate and 2 V/ns differential CK,  slew rate.

Derating Values for AC/DC-based tIS/tIH (AC220, DC130)

AC220 DC130 Threshold

CK,  Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4 V/ns

1.2 V/ns

1.0 V/ns

△tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH

2

110

74

65

43

110

73

65

43

110

73

65

43

1.5

89

16

59

16

1

0

32

CA,

Slew rate

V/ns

0.9

0.8

0.7

0.6

0.5

0.4

-3

-5

-3

-8

-5

13

8

11

3

29

24

18

10

27

19

10

-3

45

40

34

26

4

43

35

26

13

-4

-13

56

50

42

20

-7

55

46

33

16

2

-6

66

58

36

17

78

65

48

34

Notes: Cell contents shaded in light yellow are defined as “not supported.”

Required time tVAC above VIH(ac) {below VIL(ac)} for valid transition

tVAC @ 220mV [ps]

Slew Rate (V/ns)

Min

175

170

167

163

162

161

159

155

150

Max

>2.0

2.0

1.5

1.0

0.9

0.8

0.7

0.6

0.5

<0.5

–

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Data Setup and Hold Base Values

Data Rate

Parameter

Reference

1066

-10

VIH/VIL(AC) = VREF(DC) ± 220 mV

VIH/VIL(DC) = VREF(DC) ± 130 mV

tDS (base)

80

tDH (base)

Notes: AC/DC referenced for 1 V/ns DQ, DM slew rate, and 2 V/ns differential DQS,  slew rate.

Derating Values for AC/DC-based tDS/tDH (AC220, DC130)

AC220 DC130 Threshold

DQS,  Differential Slew Rate

4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns

△tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH

2

110

74

65

43

110

73

65

43

110

73

65

43

1.5

89

16

59

16

1

0

32

DQ,DM

Slew rate

V/ns

0.9

0.8

0.7

0.6

0.5

0.4

-3

-5

-3

-8

-5

13

8

11

3

29

24

18

10

27

19

10

-3

45

40

34

26

4

43

35

26

13

-4

-13

56

50

42

20

-7

55

46

33

16

2

-6

66

58

36

17

78

65

48

34

Notes: Cell contents shaded in light purple are defined as “not supported.”

Required time tVAC above VIH(ac) {below VIL(ac)} for valid transition

tVAC @ 220mV [ps]

Slew Rate (V/ns)

Min

175

170

167

163

162

161

159

155

150

Max

>2.0

2.0

1.5

1.0

0.9

0.8

0.7

0.6

0.5

<0.5

–

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Initialization Timing Parameters

Symbol

Parameter

Value

Unit

min

-

max

^tINIT0

^tINIT1

^tINIT2

^tINIT3

^tINIT4

Maximum Power Ramp Time

Minimum CKE low time after completion of power ramp

Minimum stable clock before first CKE high

Minimum idle time after first CKE assertion

Minimum idle time after Reset command,

this time will be about 2 x ^tRFCab + ^tRPab

Maximum duration of Device Auto-Initialization

ZQ Initial Calibration

20

-

ms

ns

100

5

-

^tCK

us

200

-

1

-

us

^tINIT5

^tZQINIT

^tCKb

-

10

-

us

ns

1

Clock cycle time during boot

18

100

Power-Off Timing

Symbol

Parameter

Min

Max

Unit

tPOFF

Maximum power-off ramp time

-

2

s

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Mode Register Assignment

MR#

MA <7:0>

Function

Access OP7 OP6

OP5 OP4 OP3 OP2 OP1 OP0

Device Info

Device Feature1

Device Feature2

I/O Config-1

R

W

R

(RFU)

nWR (for AP)

(RFU)

0

1

00_H

01_H

RZQI

WC BT

DI

DAI

BL

2

02_H

RL & WL

DS

3

03_H

(RFU)

Refresh Rate

Basic Config-1

Basic Config-2

Basic Config-3

Basic Config-4

Test Mode

(RFU)

4

04_H

TUF

Refresh Rate

R

5

05_H

Manufacturer ID

Revision ID1

Revision ID2

Density

R

6

06_H

R

7

07_H

R

8

08_H

I/O width

Type

W

9

09_H

Specific Test Mode

Calibration Code

(RFU)

IO Calibration

(Reserved)

10

0A_H

11~15

16

0B_H~0F_H

10_H

PASR_BANK

PASR_Seg

W

Bank Mask (4-Bank or 8-Bank)

Segment Mask

17

11_H

(Reserved)

(RFU)

18-19

20-31

32

12_H-13_H

18_H-1F_H

20_H

Reserved for NVM

DQ calibration pattern A

(Do Not Use)

DQ calibration pattern B

(Do Not Use)

(Reserved)

R

See “Data Calibration Pattern Description”

33-39

40

21_H-27_H

28_H

See “Data Calibration Pattern Description”

41-47

48-62

63

29_H-2F_H

30_H-3E_H

3F_H

(DNU)

(RFU)

X

Reset

W

(Reserved)

(RFU)

(DNU)

(RFU)

(DNU)

(RFU)

(DNU)

64-126

127

128-190

191

192-254

40_H-7E_H

7F_H

(Do Not Use)

(Reserved)

80_H-BE_H

BF_H

(Do Not Use)

(Reserved)

C0_H-FE_H

FF_H

(Do Not Use)

255

Notes:

1. RFU bits shall be set to “0” during Mode Register writes. RFU bits shall be read as “0” during Mode Register reads. All Mode Registers that are

specified as RFU shall not be written. Writes to read-only registers shall have no impact on the functionality of the device.

2.All Mode Registers from that are specified as RFU or write-only shall return undefined data when read and DQS shall be toggled.

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MR0_Device Information (MA<7:0> = 00H)

MR#

0

MA <7:0>

00_H

Function

Access OP7 OP6 OP5 OP4 OP3 OP2 OP1

OP0

DAI

RZQI

Device Info

R

(RFU)

(RFU) DI

(Optional)

DAI (Device Auto-Initialization

Status)

0_B: DAI complete

OP0

Read-only

1_B: DAI still in progress

0_B: S2 or S4 SDRAM

1_B: Do Not Use

OP1

DI (Device Information)

Read-only

00_B: RZQ self test not supported

01_B: ZQ-pin may connect to VDDCA or float

10_B: ZQ-pin may short to GND

RZQI (Built in Self Test for RZQ

Information)

OP<4:3>

Read-only

11_B:ZQ-pin self test completed, no error condition

detected (ZQpin may not connect to VDDCA or float nor

short to GND)

Notes:

1.

RZQI, if supported, will be set upon completion of the MRW ZQ Initialization Calibration command.

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MR1_Device Feature 1 (MA<7:0> = 01_H)

MR#

1

MA <7:0>

01_H

Function

Access

OP7

OP6

OP5

OP4

WC

OP3

BT

OP2

OP1

BL

OP0

Device Feature1

W

nWR (for AP)

010_B: BL4 (default)

011_B: BL8

OP<2:0>

BL (Burst Length)

Write-only

100_B: BL16

All others: reserved

0_B: Sequential (default)

1_B: Interleaved

OP3

OP4

BT*1 (Burst Type)

WC (Wrap)

Write-only

0_B: Wrap (default)

1_B: No wrap (allowed for SDRAM BL4 only)

001_B: nWR=3 (default)

010_B: nWR =4

011_B: nWR =5

OP<7:5>

nWR (for AP)

Write-only

100_B: nWR =6

101_B: nWR =7

110_B: nWR =8

All others: reserved

Notes:

1. BL16, interleaved is not an official combination to be supported.

2. Programmed value in nWR register is the number of clock cycles which determines when to start internal precharge

operation for a write burst with AP enabled. It is determined by RU(^tWR/^tCK).

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4Gb SLC NAND + 8Gb LPDDR2

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Burst Sequence by BL, BT, WC and column address

Burst Cycle Number and Burst Address Sequence

C3

C2

C1 C0

WC

BT

BL

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

BL4

0

2

y

1

3

2

0

3

1

x

0_B

1_B

x

0_B

wrap any

4

y+1 y+2 y+3

BL8

nw

any

0

2

4

6

0

2

4

6

1

3

5

7

1

3

5

7

2

4

6

0

2

0

6

4

3

4

6

0

2

4

6

0

2

5

7

1

3

5

7

1

3

6

0

2

4

6

4

2

0

7

1

3

5

7

5

3

1

x

0_B

1_B

0_B

1_B

x

0_B

1_B

0_B

1_B

0_B

1_B

0_B

1_B

x

0_B

5

7

1

3

1

7

5

seq

wrap

8

int

nw

any

illegal (not allowed)

Burst Cycle Number and Burst Address Sequence

C3

C2

C1 C0

WC

BT

BL

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

BL16

0

2

1

3

5

7

9

B

D

F

2

4

3

5

7

9

B

D

F

1

4

6

5

7

9

B

D

F

1

3

6

8

7

9

B

D

F

1

3

5

8

A

C

E

0

9

B

D

F

1

3

5

7

A

C

E

0

2

4

6

8

B

D

F

1

3

5

7

9

C

E

0

2

4

6

8

A

D

F

1

3

5

7

9

B

E

0

2

4

6

8

A

C

F

1

3

5

7

9

B

D

0_B

1_B

0_B

1_B

x

0_B

1_B

0_B

1_B

0_B

1_B

0_B

1_B

x

0_B

4

6

8

A

C

E

0

0_B

6

8

A

C

E

0

0_B

seq

8

A

C

E

0

1_B

wrap

16

A

C

E

2

1_B

2

4

1_B

2

4

6

1_B

x

int

illegal (not allowed)

x

nw

any

Notes:

1. C0 input is not present on CA bus. It is implied zero.

2. For BL=4, the burst address represents C1~C0.

3. For BL=8, the burst address represents C2~C0.

4. For BL=16, the burst address represents C3~C0.

5. For no-wrap, BL4, the burst must not cross the page boundary or the sub-page boundary. The variable y can start at any address with C0 equal

to 0, but must not start at any address shown bellow.

Version 1.5

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4Gb SLC NAND + 8Gb LPDDR2

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Level: Property

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Non-Wrap Restrictions

Width

64Mb

128Mb/256Mb

512Mb/1Gb/2Gb

4Gb/8Gb

Cannot cross full page boundary

X16

X32

FE, FF, 00, 01

7E, 7F, 00, 01

1FE, 1FF, 000, 001

FE, FF, 00, 01

3FE, 3FF, 000, 001

1FE, 1FF, 000, 001

7FE, 7FF, 000, 001

3FE, 3FF, 000, 001

Cannot cross sub-page boundary

X16

X32

7E, 7F, 80, 81

none

0FE, 0FF, 100, 101

none

1FE, 1FF, 200, 201

none

3FE, 3FF, 400, 401

none

Notes: Non-wrap BL= 4 data orders shown are prohibited.

Version 1.5

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4Gb SLC NAND + 8Gb LPDDR2

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Level: Property

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MR2_DeviceFeature 2 (MA<7:0> = 02_H)

MR#

2

MA <7:0>

02_H

Function

Access

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

Device Feature2

W

(RFU)

RL & WL

0001_B: RL3 / WL1 (default)

0010_B: RL4 / WL2

0011_B: RL5 / WL2

0100_B: RL6 / WL3

0101_B: RL7 / WL4

0110_B: RL8 / WL4

All others: reserved

RL & WL

OP<3:0>

(Read Latency &

Write Latency)

Write-only

MR3_I/O Configuration 1 (MA<7:0> = 03_H)

MR#

3

MA <7:0>

03_H

Function

Access

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

I/O Config-1

W

(RFU)

DS

0000_B: reserved

0001_B: 34.3 ohm typical

0010_B: 40.0 ohm typical (default)

0011_B: 48.0 ohm typical

0100_B: 60.0 ohm typical

0101_B: reserved

OP<3:0>

DS (Drive Strength)

Write-only

0110_B: 80.0 ohm typical

0111_B: 120.0 ohm typical

All others: reserved

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4Gb SLC NAND + 8Gb LPDDR2

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MR4_Device Temperature (MA<7:0> = 04_H)

MR#

4

MA <7:0>

04_H

Function

Access OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

Refresh Rate

R

TUF

(RFU)

Refresh Rate

000_B: SDRAM Low temperature operating limit exceeded

001_B: 4x tREFI, 4x tREFIpb, 4x tREFW

010_B: 2x tREFI, 2x tREFIpb, 2x tREFW

011_B: 1x tREFI, 1x tREFIpb, 1x tREFW (<=85C)

100_B: RFU

OP<2:0>

Refresh Rate

Read-only

101_B: 0.25x tREFI, 0.25x tREFIpb, 0.25x tREFW,

do not de-rate SDRAM AC timing

110_B: 0.25x tREFI, 0.25x tREFIpb, 0.25x tREFW,

de-rate SDRAM AC timing

111_B: SDRAM High temperature operating limit exceeded

0_B: OP<2:0> value has not changed since last read of MR4.

1_B: OP<2:0> value has changed since last read of MR4.

TUF

(Temperature Update Flag)

OP7

Read-only

Notes:

1. A Mode Register Read from MR4 will reset OP7 to “0”.

2. OP7 is reset to “0” at power-up.

3. If OP2 equals “1”, the device temperature is greater than 85C.

4. OP7 is set to “1”, if OP2~OP0 has changed at any time since the last read of MR4.

5. LPDDR2 might not operate properly when OP<2:0> = 000_Bor 111_B.

6. For specified operating temperature range and maximum operating temperature.

7. LPDDR2 devices must be derated by adding 1.875ns to the following core timing parameters: tRCD, tRC, tRAS, tRP and tRRD.

The tDQSCK parameter must be derated. Prevailing clock frequency specifications and related setup and hold timings remain

unchanged.

8. The recommended frequency for reading MR4 is provided in “Temperature Sensor”.

Version 1.5

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05/2018

4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

Level: Property

NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

MR5_Basic Configuration-1 (MA<7:0> = 05_H)

MR#

5

MA <7:0>

05_H

Function

Access OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

Basic Config-1

R

Manufacturer ID

0000 0000_B: Reserved

0000 0001_B: Samsung

0000 0010_B: Qimonda

0000 0011_B: Elpida

0000 0100_B: Etron

0000 0101_B: Nanya

0000 0110_B: Hynix

0000 0111_B: Mosel

0000 1000_B: Winbond

0000 1001_B: ESMT

0000 1010_B: Reserved

0000 1011_B: Spansion

0000 1100_B: SST

OP<7:0>

Manufacturer ID

Read-only

0000 1101_B: ZMOS

0000 1110_B: Intel

1111 1110_B: Numonyx

1111 1111_B: Micron

All Others : Reserved

MR6_Basic Configuration-2 (MA<7:0> = 06_H)

MR#

6

MA <7:0>

06_H

Function

Access

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

Basic Config-2

R

Revision ID1

OP<7:0>

Revision ID1

Read-only

Reserved ¹

Notes:

1. Please contact with NTC for details

Version 1.5

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4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

Level: Property

NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

MR7_Basic Configuration-3 (MA<7:0> = 07_H)

MR#

7

MA <7:0>

07_H

Function

Access

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

Basic Config-3

R

Revision ID2

OP<7:0>

Revision ID2

Read-only

Reserved ¹

Notes:

1. Please contact with NTC for details

MR8_Basic Configuration-4 (MA<7:0> = 08H)

MR#

8

MA <7:0>

08_H

Function

Access OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

Basic Config-4

R

I/O width

Density

Type

00_B: S4 SDRAM

01_B: S2 SDRAM

10_B: N NVM

11_B: Reserved

0000_B: 64Mb

0001_B: 128Mb

0010_B: 256Mb

0011_B: 512Mb

0100_B: 1Gb

OP<1:0>

OP<5:2>

OP<7:6>

Type

Read-only

Density

Read-only

0101_B: 2Gb

0110_B: 4Gb

0111_B: 8Gb

1000_B: 16Gb

1001_B: 32Gb

All others: reserved

00_B: x32

01_B: x16

I/O width

Read-only

10_B: x8

11_B: not used

Version 1.5

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4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

Level: Property

NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

MR9_Test Mode (MA<7:0> = 09H)

MR#

9

MA <7:0>

09_H

Function

Access OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

Test Mode

W

Specific Test Mode

OP<7:0>

Specific Test Mode

Reserved ¹

Notes:

1. Please contact with NTC for details

MR10_Calibration (MA<7:0> = 0A_H)

MR#

10

MA <7:0>

0A_H

Function

Access

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

IO Calibration

W

Calibration Code

0xFF: Calibration command after initialization

0xAB: Long calibration

0x56: Short calibration

OP<7:0>

Calibration Code

Write-only

0xC3: ZQ Reset

others: Reserved

Notes:

1. Host processor shall not write MR10 with “Reserved” values.

2. LPDDR2 devices shall ignore calibration command, when a “Reserved” values is written into MR10.

3. See AC timing table for the calibration latency.

4. If ZQ is connected to VSS through RZQ, either the ZQ calibration function (see “MRW ZQ Calibration Command”) or default calibration

(through the ZQ RESET command) is supported. If ZQ is connected to VDDCA, the device operates with default calibration, and ZQ

calibration commands are ignored. In both cases, the ZQ connection must not change after power is supplied to the device. Devices that

do not support calibration ignore the ZQ calibration command.

Version 1.5

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4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

Level: Property

NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

MR11:15_(Reserved) (MA<7:0> = 0B_H- 0F_H)

MR#

MA <7:0>

0B_H~0F_H

Function

Access

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

11~15

(reserved)

(RFU)

OP<7:0>

RFU

Reserved for Future Use

MR16_PASR_Bank Mask (MA<7:0> = 010_H)

MR#

16

MA <7:0>

10_H

Function

Access OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

PASR_BANK

W

Bank Mask (4-Bank or 8-Bank)

0_B: refresh enable to the bank (=unmasked, default)

1_B: refresh blocked (=masked)

OP<7:0>

Bank Mask (4-Bank or 8-Bank)

Write-only

For 4-bank S4 SDRAM, only OP<3:0> are used.

OP

Bank Mask

4 Bank

8 Bank

0

1

2

3

4

5

6

7

XXXXXXX1

XXXXXX1X

XXXXX1XX

XXXX1XXX

XXX1XXXX

XX1XXXXX

X1XXXXXX

1XXXXXXX

Bank 0

Bank 1

Bank 2

Bank 3

Bank 4

Bank 5

Bank 6

Bank 7

Bank 1

Bank 2

Bank 3

-

Version 1.5

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4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

Level: Property

NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

MR17_PASR_Segment Mask (MA<7:0> = 011_H)

MR#

17

MA <7:0>

11_H

Function

Access OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

PASR_Seg

W

Segment Mask

0_B: refresh enable to the segment (=unmasked, default)

1_B: refresh blocked (=masked)

OP<7:0>

Segment Mask

Write-only

This table indicates the range of row addresses in each masked segment. X is don’t care for a particular segment.

2Gb, 4Gb

R13:11

000_B

1Gb

8Gb

Segment

OP

Bank Mask

R12:10

R14:12

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

XXXXXXX1

XXXXXX1X

XXXXX1XX

XXXX1XXX

XXX1XXXX

XX1XXXXX

X1XXXXXX

1XXXXXXX

001_B

010_B

011_B

100_B

101_B

110_B

111_B

Version 1.5

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4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

Level: Property

NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

MR18:19_(Reserved) (MA<7:0> = 012_H- 013_H)

MR#

MA <7:0>

12_H-13_H

Function

Access OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

18-19

(Reserved)

(RFU)

OP<7:0>

RFU

Reserved for Future Use

MR20:31_(Do Not Use) (MA<7:0> = 014H- 01FH)

MR#

MA <7:0>

18_H-1F_H

Function

Access OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

20-31

Reserved for NVM

OP<7:0>

Reserved for NVM

N/A

MR32_ DQ calibration pattern A (MA<7:0> = 020H)

MR40_ DQ calibration pattern B (MA<7:0> = 028H)

MR#

MA <7:0>

Function

Access OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

32

40

20_H

28_H

DQ calibration pattern A

DQ calibration pattern B

R

See “Data Calibration Pattern Description”

OP<7:0>

DQ calibration pattern A

DQ calibration pattern B

See “Data Calibration Pattern Description”

Version 1.5

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4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

Level: Property

NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

MR63_Reset (MA<7:0> = 03F_H): MRW only

MR#

63

MA <7:0>

3FH

Function

Access OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

Reset

W

X

OP<7:0>

Reset

(For additional information on MRW RESET, see “Mode Register Write Command” on

Timing Spec)

Do Not Use and Reserved functions

MR#

MA <7:0>

Function

Access OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

33-39

41-47

48-62

64-126

127

21_H-27_H

29H-2FH

30H-3EH

40H-7EH

7FH

(Do Not Use)

(Reserved)

(DNU)

(RFU)

(DNU)

(RFU)

(DNU)

(RFU)

(DNU)

(Reserved)

(Do Not Use)

(Reserved)

128-190

191

80H-BEH

BFH

(Do Not Use)

(Reserved)

192-254

255

C0H-FEH

FFH

(Do Not Use)

Version 1.5

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4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

Level: Property

NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

Revision History

Rev

Page

Modified

Description

Released

1.3

-

Official Release

New

06/2017

P27-49

P53-64

P62,63

Device Operation

1.4

1.5

04/2018

05/2018

-

Add Application notes

Correct typo.

Version 1.5

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05/2018

4Gb SLC NAND + 4Gb LPDDR2

4Gb SLC NAND + 8Gb LPDDR2

NTC Proprietary

Level: Property

NM14F4KSLAXAQ(3)/NM14F8KSLAXA3/NM1484KSLAXAJ

http://www.nanya.com/

Version 1.5

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Nanya Technology Corp.

05/2018


型号：	NM14F8KSLAXAQ-3BNA
厂家：	Nanya Technology Corporation.
描述：	MCP Specification
文件：	总122页 (文件大小：6131K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NM14F8KSLAXAQ-3BNA [NANYA]

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