NM21F0NSMAXBH-3T_技术文档

1Gb SLC NAND + 512Mb LPDDR

NM21F0NSMAXBH

MCP Specification

1Gb SLC NAND Flash (X16) + 512Mb LPDDR (X16)

Nanya Technology Corporation

Version 1.3

1

Nanya Technology Corp.

NTC has the rights to change any specifications or product without notification.

09//2016

1Gb SLC NAND + 512Mb LPDDR

NM21F0NSMAXBH

Ordering Information

MCP

NAND

DRAM

Density Program Erase

Density

(Org.)

Part Number

Type

Speed CL

(Org.)

Time

1Gb

(64Mb X16)

512Mb

(32Mb X 16)

NM21F0NSMAXBH-3T SLC

300μs

3.5ms LPDDR

400

3

Version 1.3

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Nanya Technology Corp.

1Gb SLC NAND + 512Mb LPDDR

NM21F0NSMAXBH

NANYA MCP Part Numbering Guide

NM

2

1F

0N

H

S

M

AX

B

3

T

Grade

NA = Commercial Grade

NANYA

MCP

DRAM Speed

T = 400Mbps @ CL=3

Product Family

2 =SLC NAND + LPDDR1

NAND Speed

3 = 300μs

NAND Organization

(Density, Config)

1F= 1Gb x16

Package

H = 130ball BGA

Device Version

B = 2^ndversion

DRAM Organization

(Density, Config)

0N= 512Mb x16

Reserve Code

AX=Default

NAND Voltage

S= 1.8V

DRAM Interface (V_DD/V_DDQ)

M = LVCMOS (1.8V, 1.8V)

Version 1.3

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1Gb SLC NAND + 512Mb LPDDR

NM21F0NSMAXBH

Features

MCP

 Separate SLC NAND and LPDDR RAM interfaces

 Lead-free (RoHS compliant) and Halogen-free Package : 130-ball VFBGA (9.00mm x 8.00mm, pitch 0.65mm)

 Operating temperature range: –25°C to +85°C

1Gb X16 SLC NAND

 Voltage Supply: 1.70V ~ 1.95V

 Organization

512Mb X16 LPDDR

 Speed, Addressing and Retention Specification

Organization

32Mb X 16

- Memory Cell Array: 1088 x 64K x 16

- Data Register: 1088 x 16

- Page Program: 1088 Words

- Block Erase: (64K + 4K) Words

 Modes

Speed Grade

Number of Banks

Bank Address

Row

400-3-3-3

4

BA[1:0]

A[12:0]

A[9:0]

7.8µs

Column

Read, Reset, Auto Page Program, Auto Block Erase,

Status Read, Page Copy

tREFI

tRFC

110ns

 Mode control

 JEDEC LPDDR Compliant

- Serial input/output

- Command control

- Low Power Consumption

- Double-data rate on DQs, DQS and DM

- 2n Prefetch Architecture

 Number of valid blocks

- Min 1004 blocks

- Max 1024 blocks

 Access time

 LVCMOS interface and Power Supply

- VDD/VDDQ= 1.70 to 1.95V

 Signal Integrity

- Cell array to register: 25μs max

- Serial Read Cycle: 25ns min (CL=30pF)

 Program/Erase time

- Configurable DS for system compatibility

 Data Integrity

- DRAM built-in Temperature Sensor for Temperature

Compensated Self Refresh (TCSR)

- Auto Page Program: 300μs/page typical

- Auto Block Erase: 3.5ms/block typical

 Operating current

- Auto Refresh, Self Refresh and PASR Modes

 Power Saving Modes

- Deep Power Down Mode (DPD)

- Read (25ns cycle): 30 mA max

- Program (avg.): 30 mA max

- Partial Array Self Refresh (PASR)

- Clock Stop capability during idle period

 Programmable Mode Register Function

- Output Drive Impedance (full, 3/4, 1/2, 1/4)

- Burst Lengths (2, 4, 8, 16)

- Erase (avg.): 30 mA max

- Standby: 50 μA max

 8 bit ECC for each 512 Bytes is required.

- Burst Type (Sequential, Interleaved)

- Partial Array Self Refresh (1, 1/2, 1/4, 1/8, 1/16)

Version 1.3

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09//2016

1Gb SLC NAND + 512Mb LPDDR

NM21F0NSMAXBH

130b Ball Assignment– Flash X16 + DRAM X16

Part Number: NM21F0NSMAXBH-XXX

1

2

3

4

5

6

7

8

9

10

NC



CLE

VCC





VDD

VSS

NC

A

B

C

D

E

F

A

B

C

D

E

F

VSS

VDD

A6

A4

A5



A7

ALE

A9

VSS

DQ9

R/

DQ15 DQ14 VDDQ VSSQ

DQ11 DQ13 DQ12 VSSQ VDDQ

UDM DQ10 VDDQ VSSQ

A8

CKE

NC

RFU UDQS RFU

A12

NC

A11







RFU

A0

RFU

DQ7

DQ1

I/O 3

VCC

DQ8

RFU

DQ2

RFU

LDQS

DQ6

DQ3

RFU

CK

VSSQ VDDQ

VDDQ VSSQ

RFU

BA0

A10

A3

VDD

VSS



A1



VSS

VDD

G

H

J

G

H

J

Power

Ground

DRAM

Flash

RFU

LDM VSSQ VDDQ

DQ4 VDDQ VSSQ

DQ5 VDDQ VSSQ

BA1

A2

DQ0

RFU

K

L

K

L

VDD

I/O 0

VSS

I/O 1

NC

I/O 5 I/O 14 I/O 7 VSSQ VDDQ

I/O 6 I/O 13 I/O 15 VDDQ VSSQ

I/O 2 I/O 10

M

N

M

N

NC

RFU

1

I/O 8

2

I/O 9 I/O 11 I/O 12

VSS

6

I/O 4

7

VDD

8

VSS

9

RFU¹

10

3

4

5

NOTE 1 This pin is reserved for TEST purpose and it must be connected to Ground.

Version 1.3

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09//2016

1Gb SLC NAND + 512Mb LPDDR

NM21F0NSMAXBH

130b Package Outline Drawing (9.00mm x 8.00mm, pitch 0.65mm)

Unit: mm

* BSC (Basic Spacing between Center)

Version 1.3

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1Gb SLC NAND + 512Mb LPDDR

NM21F0NSMAXBH

Ball Description – 1Gb X16 SLC NAND

Symbol

Type

Function

Data Bus: The I/O0 to 7 pins are used as a port for transferring address, command and input/output data to

and from the device.

X16: I/O[15:0] Input/output

The I/O8 to 15 pins are used as a port for transferring input/output data to and from the device. I/O8 to 15

pins must be low level (V ) when address and command are input.

IL

Command Latch Enable: The CLE input signal is used to control loading of the operation mode command

into the internal command register. The command is latched into the command register from the I/O port on

the rising edge of the  signal while CLE is High

CLE

ALE



Input

Address Latch Enable: The ALE signal is used to control loading address information into the internal

address register. Address information is latched into the address register from the I/O port on the rising edge

of  while ALE is High

Chip Enable: The device goes into a low-power Standby mode when  goes High during the device is in

Ready state. The  signal is ignored when device is in Busy state ( RY /  = L), such as during a Program

or Erase or Read operation, and will not enter Standby mode even if the  input goes High

Read Enable: The  signal controls serial data output. Data is available tREA after the falling edge of .



The internal column address counter is also incremented (Address = Address +1) on the falling edge.





Input

Write Enable: The  signal is used to control the acquisition of data from the I/O port.

Write Protect: The  signal is used to protect the device from accidental programming or erasing. The

internal voltage regulator is reset when  is Low. This signal is usually used for protecting the data during

the power-on/off sequence when input signals are invalid.

Ready / Busy Output: The RY /  output signal is used to indicate the operating condition of the device.

The RY /  signal is in Busy state ( RY /  = L) during the Program, Erase and Read operations and will

return to Ready state ( RY /  = H) after completion of the operation. The output buffer for this signal is an

open drain and has to be pulled-up to Vccq with an appropriate resister.

R/

Output

If RY /  signal is not pulled-up to Vccq ( “Open” state), device operation cannot guarantee

VCC

VSS

NC

Supply

─

Power Supply

Ground

No Connect: These pins should be left unconnected.

Version 1.3

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1Gb SLC NAND + 512Mb LPDDR

NM21F0NSMAXBH

Ball Description – 512Mb X16 LPDDR

Symbol ¹

Type

Function

Clock: CK and  are differential clock inputs. All address and control input signals are sampled on

the crossing of the positive edge of CK and negative edge of . Input and output data is referenced to

the crossing of CK and  (both directions of crossing). Internal clock signals are derived from CK, .

Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device

input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF

REFRESH operation (all banks idle), or ACTIVE POWERDOWN (row ACTIVE in any bank). CKE is

synchronous for all functions except for SELF REFRESH EXIT, which is achieved asynchronously.

Input buffers, excluding CK,  and CKE, are disabled during power-down and self refresh mode

which are contrived for low standby power consumption.

CK, 

Input

CKE

Input

Chip Select:  enables (registered LOW) and disables (registered HIGH) the command decoder. All

commands are masked when  is registered HIGH.  provides for external bank selection on

systems with multiple banks.  is considered part of the command code.



Input

, , 

Command Inputs: ,  and  (along with ) define the command being entered.

Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled

HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS.

Although DM pins are input-only, the DM loading matches the DQ and DQS loading.

X16:

Input

LDM, UDM

X16:DQ[15:0]

Input/output Data Bus: Bi-directional Input / Output data bus.

X16:

Data Strobe: Output with read data, input with write data. Edge-aligned with read data. Centered with

Input/output

LDQS, UDQS

write data to capture write data.

Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE, or

BA[1:0]

A[12:0]

Input

PRECHARGE command is being applied. BA0 and BA1 also determine which mode register is loaded

during a LOAD MODE REGISTER command.

Address Inputs: provide the row address for ACTIVE commands, and the column address and auto

precharge bit(A10) for READ or WRITE commands, to select one location out of the memory array in

the respective bank. During a PRECHARGE command, A10 determines whether the PRECHARGE

applies to one bank (A10 LOW, bank selected by Bank Address Inputs) or all banks (A10 HIGH). The

address inputs also provide the opcode during a MODE REGISTER SET command.

Power Supply

VDD

VSS

Supply

-

Ground

VDDQ

VSSQ

NC

DQ Power Supply: Isolated on the die for improved noise immunity.

DQ Ground: Provide isolated ground to DQs for improved noise immunity.

No Connect: These pins should be left unconnected.

NOTE 1 The signal may show up in a different symbol but it indicates to the same thing. e.g., /CK = CK# =  = CKb, /DQS = DQS#

=  = DQSb

Version 1.3

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1Gb SLC NAND + 512Mb LPDDR

NM21F0NSMAXBH

Functional Block Diagram

V_SS

V_DDV_DDQV_SSQ



CKE

CK

512Mb Mobile DDR



DM[1:0]

A[12:0]

BA[1:0]

DQ[15:0]

DQS[1:0]

[1:0]

NAND

CLE

ALE



1Gb NAND Flash

X16: I/O[15:0]







R/

V_CC

Version 1.3

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Nanya Technology Corp.

1Gb SLC NAND + 512Mb LPDDR

NM21F0NSMAXBH

1Gb(X16) SLC NAND Flash

Version 1.3

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Nanya Technology Corp.

09//2016

1Gb SLC NAND + 512Mb LPDDR

NM21F0NSMAXBH

Descriptions

The device is a single 1.8V 1Gbit (1,140,850,688bits) NAND Electrically Erasable and Programmable

2

Read-Only Memory (NAND E PROM) organized as (1024 + 64) words x 64 pages x 1024blocks.

The device has a 1088-word static registers which allow program and read data to be transferred between the

register and the memory cell array in 1088 words increments. The Erase operation is implemented in a single

block unit (64Kwords + 4Kwords: 1088 words x 64 pages).

The device is a serial-type memory device which utilizes the I/O pins for both address and data input/output as

well as for command inputs. The Erase and Program operations are automatically executed making the device

most suitable for applications such as solid-state file storage, voice recording, image file memory for still

cameras and other systems which require high-density non-volatile memory data storage.

Version 1.3

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1Gb SLC NAND + 512Mb LPDDR

NM21F0NSMAXBH

Function Block Diagram (X16)

V_CC

V_SS

Status register

Address register

Command register

Column buffer

Column decoder

Data register

I/O 0

I/O

to

Control circuit

I/O 15

Command register





CLE

ALE

Memory cell array

Logic control

Control circuit







RY/

HV generator

Array Organization (X16)

The Program operation works on page units while the Erase operation works on block units

A page consists of 1088 words in which 1024 words are used

for main memory storage and 64 words are for redundancy or

for other uses.

I/O 0

I/O 15

1 Page = 1088 Words

1 Block = 1088 Words x 64 Pages = (64K + 4K) Words

Capacity= 1088 Words x 64 Pages x1024 blocks

1 Block = 64 Pages

(64K + 4K) Words

Array Address (X16)

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 8 ~ I/O 15

Address

1^stcycle

2^ndcycle

3^rdcycle

4^thcycle

CA₀

CA₈

PA₀

PA₈

CA₁

CA₉

PA₁

PA₉

CA₂

CA₁₀

PA₂

CA₃

L

CA₄

L

CA₅

L

CA₆

L

CA₇

L

Column Address

Page Address

PA₃

PA₁₁

PA₄

PA₁₂

PA₅

PA₁₃

PA₆

PA₁₄

PA₇

PA₁₅

PA₁₀

Page Address

PA6 to PA16: Block address

PA0 to PA5: NAND address in block

Note I/O 8 ~ 15 must be held low when address is input.

Version 1.3

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1Gb SLC NAND + 512Mb LPDDR

NM21F0NSMAXBH

Absolute Maximum Ratings

Symbol

V_CC

Rating

Value

-0.6 to +2.5

-0.6 to Vcc + 0.3(≤2.5V)

0.3

Unit

Power Supply Voltage

Input Voltage

V_IN

V

V_I/O

Input / Output Voltage

Power Dissipation

P_D

W

^oC

T_SOLDER

T_STG

Soldering Temperature (10 s)

Storage Temperature

260

-55 to +125

Capacitance¹

(T_A=25℃, f=1.0MHz)

Symbol

C_IN

Parameter

Input

Test Condition

Min

－

Max

10

Unit

pF

V_IN=0V

C_OUT

Output

V_OUT=0V

－

10

pF

NOTE 1

This parameter is periodically sampled and is not tested for every device.

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1Gb SLC NAND + 512Mb LPDDR

NM21F0NSMAXBH

Valid Blocks

Symbol

NVB

Parameter

Min

Typ.

－

Max

Unit

Number of Valid Blocks

1,004

1,024

Blocks

NOTE 1

The device occasionally contains unusable blocks.

The first block (Block 0) is guaranteed to be a valid block at the time of shipment.

The specification for the minimum number of valid blocks is applicable over lifetime.

Recommended DC Operating Conditions

Symbol

V_CC

Parameter

Power Supply Voltage

Min

1.70

Typ.

－

Max

1.95

Unit

V

V_IH

High Level Input Voltage

Low Level Input Voltage

V_CCx 0.8

-0.3¹

－

V_CC+ 0.3

V_CCx 0.2

V

V_IL

－

V

NOTE 1

-2 V (pulse width lower than 20 ns)

DC and Operation Characteristics

(Ta= -25 to 85℃, V_CC=1.70 to 1.95V)

Symbol

Parameter

Input Leakage Current

Output Leakage Current

Serial Read Current

Test Conditions

Min

Typ.

－

4

Max

±10

30

Unit

μA

I_IL

V_IN=0 to V_CC

－

I_LO

V_OUT=0 to V_CC

－

mA

I_CCO1

I_CCO2

I_CCO3

I_CCS

=V_IL,I_OUT= 0 mA, tcycle=25ns

－

Programming Current

Erasing Current

－

30

mA

μA

V

Standby Current

= V_CC- 0.2 V,  = 0 V/V_CC

I_OH= -0.1mA

－

50

V_OH

V_OL

High Level Output Voltage

Low Level Output Voltage

V_CC- 0.2

－

I_OL= 0.1mA

0.2

－

V

I_OL(RY/) Output Current of (RY/) pin

V_OL=0.2V

－

mA

Version 1.3

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1Gb SLC NAND + 512Mb LPDDR

NM21F0NSMAXBH

AC Timing Characteristics for Command / Address / Data Input

(Ta= -25 to 85℃, V_CC=1.70 to 1.95V)

Symbol

Parameter

Min

Max

Unit

tCLS

tCLH

tCS

CLE Setup Time

CLE Hold Time

 Setup Time

 Hold Time

12

5

–

ns

20

5

tCH

tWP

tALS

tALH

tDS

Write Pulse Width

ALE Setup Time

ALE Hold Time

Data Setup Time

Data Hold Time

Write Cycle Time

 High Hold Time

12

5

12

5

tDH

tWC

tWH

25

10

AC Characteristics for Operation

Symbol

Parameter

Min

Max

Unit

tWW

tRR

 High to  Low

100

20

12

25

–

ns

μs

ns

μs

Ready to  Falling Edge

–

tRW

tRP

Ready to  Falling Edge

Read Pulse Width

–

tRC

Read Cycle Time

–

tREA

tCEA

tCLR

 Access Time

20

 Access Time

–

25

CLE Low to  Low

10

25

5

–

tAR

ALE Low to  Low

–

tRHOH

tRLOH

tRHZ

tCHZ

tCSD

tREH

tIR

 High to Output Hold Time

 Low to Output Hold Time

 High to Output High Impedance

 High to Output High Impedance

 High to ALE or CLE Don’t care

 High Hold Time

–

60

–

20

0

–

10

0

–

Output-High-impedance-to- Falling Edge

 High to  Low

–

tRHW

tWHC

tWHR

tR

30

60

–

 High to  Low

–

 High to  Low

–

25

Memory Cell Array to Starting Address

Data Cache Busy in Read Cache (following 31h and 3Fh)

Data Cache Busy in Page Copy (following 3Ah)

 High to Busy

tDCBSYR1

tDCBSYR2

tWB

–

25

–

30

–

100

tRST

Device Reset Time (Ready/Read/Program/Erase)

–

5/5/10/500

NOTE1 tCLS and tALS cannot be shorter than tWP.

NOTE2 tCS should be longer than tWP + 8ns.

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1Gb SLC NAND + 512Mb LPDDR

NM21F0NSMAXBH

AC Test Conditions

Condition

VCC : 1.70 to 1.95V

VCC – 0.2 V, 0.2 V

3ns

Parameter

Input level

Input pulse rise and fall time

Input comparison level

Output data comparison level

Output Load

Vcc / 2

1 TTL GATE and CL=30pF

NOTE 1

Busy to ready time depends on the pull-up resistor tied to the RY/ pin.

Program / Erase Characteristics

(Ta= -25 to 85℃, V_CC=1.70 to 1.95V)

Symbol

tPROG

Parameter

Average Programming Time

tDCBSYW2¹Data Cache Busy Time in Write Cache (following 15h)

Min

–

Typ

300

–

Max

700

4

Unit

μs

–

μs

Nop

Number of Partial Program Cycles in the Same Page

Block Erase Time

–

cycle

ms

tBERASE

NOTE 1

–

3.5

10

t

depends on the timing between internal programming time and data in time.

DCBSYW2

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1Gb SLC NAND + 512Mb LPDDR

NM21F0NSMAXBH

Operation Mode: Logic and Command Tables

The operation modes such as Program, Erase, Read and Reset are controlled by operations shown in

command table. Address input, command input and data input/output are controlled by the CLE, ALE, , ,

 and  signals, as shown in Mode Selection Table.

Mode Selection Table

CLE

H

ALE

L







H



Mode

Command Input

Data Input

L

＊

H

L

H

L

H

L

H

＊

Address Input

L

H

＊

Serial Data Output

During Program (Busy)

During Erase (Busy)

＊

H

＊

H¹

＊

H¹

＊

H

＊

During Read (Busy)

L

＊

H

L

Program, Erase Inhibit

Stand-by

0V/V_CC

H: V_IH, L=V_IL＊: V_IHor V_IL.

Note 1: If  is low during read busy.  and  must be held High to avoid unintended command/address input to

device or read to device. Reset or Status Read command can be input during Read Busy.

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1Gb SLC NAND + 512Mb LPDDR

NM21F0NSMAXBH

Command Table

Function

1^stCycle

80_H

00_H

05_H

31_H

3F_H

80_H

85_H

80_H

00_H

8C_H

60_H

90_H

70_H

FF_H

2^ndCycle

－

Acceptable Command during Busy

Serial Data Input

Read

30_H

E0_H

－

Column Address Change in Serial Data Output

Read with Data Cache

－

Read Start for Last Page in Read Cycle with Data Cache

Auto Page Program

10_H

－

Column Address Change in Serial Data Input

Auto Program with Data Cache

Read for Page Copy (2) with Data Out

Auto Program with Data Cache during Page Copy (2)

Auto Program for last page during Page Copy (2)

Auto Block Erase

15_H

3A_H

15_H

10_H

D0_H

－

ID Read

Status Read

O

－

Reset

－

Read mode operation states

CLE

ALE



L





I/O0 to I/O15

Data output

Power

Active

Output select

L

H

L

Output Deselect

L

H

High impedance

H: V_IH, L=V_IL

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ID Read

The device contains ID codes which can be used to identify the device type, the manufacturer, and features of

the device. The ID codes can be read out under the following timing conditions:

ID Definition Table (X16)

I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Hex Data

Description

1^stData

2^ndData

3^rdData

4^thData

5^thData

Maker Code

Device Code

1

0

1

0

98_H

1

0

1

0

1

B1_H

Internal Chip Number, Cell Type

Page Size, Block Size

Plane Number

－

See table

3rd ID Data

Item

Description

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

1

2

4

8

0

1

0

1

0

1

Internal Chip Number

Cell Type

2 Level Cell

4 Level Cell

8 Level Cell

16 Level Cell

0

1

0

1

0

1

4th ID Data

Item

Description

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

1KB

2KB

4KB

0

1

0

1

0

1

Page Size

(w/o redundant area)

8KB

64KB

128KB

256KB

512KB

0

1

0

1

0

1

Block Size

(w/o redundant area)

5th ID Data

Item

Description

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

1 Plane

2 Plane

4 Plane

8 Plane

0

1

0

1

0

1

Plane Number

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Status Read

The device automatically implements the execution and verification of the Program and Erase operations. The

status Read function is used to monitor the Ready/Busy status of the device, determine the result (pass/fail) of

a Program or Erase operation, and determine whether the device is in Protect mode. The device status is

output via the I/O port using RE after a “70h” command input. The Status Read can also be used during a Read

operation to find out the Ready/Busy status.

Status Register Definition for 70_HCommand

I/O

Page Program

Block Erase

Read

Cache Read

Cache Program

Definition

Chip Status1

Pass : 0 / Fail : 1

Chip Status2

I/O 0

Pass / Fail

Invalid

Pass / Fail

I/O 1

Invalid

Pass / Fail

Pass : 0 / Fail : 1

I/O 2

I/O 3

I/O 4

0

Not Used

Page Buffer

Busy : 0 / Ready : 1

Data Cache

I/O 5

I/O 6

Ready / Busy

Busy : 0 / Ready : 1

Write Protect

I/O 7

Write Protect

Not Used

Write Protect

Not Used

Write Protect

Not Used

Write Protect

Not Used

Write Protect

Not Used

Protected :0

/ Not Protected : 1

I/O8 to 15

Not Used

NOTE

The Pass/Fail status on I/O0 and I/O1 is only valid during a Program/Erase operation when the device is in

the Ready state.

Chip Status 1:

During a Auto Page Program or Auto Block Erase operation this bit indicates the pass/fail result.

During a Auto Page Programming with Data Cache operation, this bit shows the pass/fail results of the current

page program operation, and therefore this bit is only valid when I/O5 shows the Ready state.

Chip Status 2:

This bit shows the pass/fail result of the previous page program operation during Auto Page Programming with

Data Cache. This status is valid when I/O6 shows the Ready State.

The status output on the I/O5 is the same as that of I/O6 if the command input just before the 70h is not 15h or

31h.

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Addressing for Program Operation

Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the

block to MSB (most significant bit) pages of the block. Random page address programming is prohibited.

Page 63

Page 31

Page 63

Page 31

(64)

‧

(1)

(32)

‧

Page2

Page 1

Page 0

Page2

Page 1

Page 0

(3)

(32)

(2)

(3)

(2)

(1)

Data Register

From the LSB page to MSB page

DATA IN: Data(1)  Data (64)

Ex.) Random page program (Prohibition)

DATA IN: Data(1)  Data (64)

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Several programming cycles on the same page (Partial Page Program)

Each segment can be programmed individually as follows:

1st Programming

2nd Programming

Data Pattern 1

All 1 s

Data Pattern 2

4th Programming

Result

All 1 s

Data Pattern 4

Data Pattern 1

Data Pattern 2

-------------------------------------

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Bad Block Test Flow

Regarding invalid blocks, bad block mark is in whole pages.

Please read one column of any page in each block. It makes sure that every invalid block has Marjority “0” data

at this column. If the data of the column is Marjority “0”, define the block as a bad block.

Start

Block No = 1

Fail

Read Check

Pass

Bad Block¹

Block No. = Block No. +1

No

Last Block

Yes

End

Note1: No erase operation is allowed to detected bad blocks

Failure phenomena for Program and Erase Operations

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The device may fail during a Program or Erase operation.

The following possible failure modes should be considered when implementing a highly reliable system.

Failure Mode

Erase failure

Program failure

Bit Error

Detection and Countermeasure Sequence

Read Status after Erase → Block Replacement

Read Status after Program → Block Replacement

ECC Correction / Block Refresh

Block

Page

Read

NOTE 1

ECC: Error Correction Code. 8 bit correction per 512 Bytes is necessary.

Block Replacement

Program

When an error happens in Block A, try to reprogram the data into another Block (Block B) by loading from an

external buffer. Then, prevent further system accesses to Block A ( by creating a bad block table or by using

anther appropriate scheme).

Erase

When an error occurs during an Erase operation, prevent future accesses to this bad block (again by creating a

table within the system or by using another appropriate scheme).

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Power-on/off sequence

The timing sequence shown in the figure below is necessary for the power-on/off sequence.

The device internal initialization starts after the power supply reaches an appropriate level in the power on

sequence.

During the initialization the device Ready/Busy signal indicates the Busy state as shown in the figure below. In

this time period, the acceptable commands are FFh or 70h.

The  signal is useful for protecting against data corruption at power-on/off.

Do not turn off the power before write/erase operation is complete. Avoid using the device when the battery

is low. Power shortage and/or power failure before write/erase operation is complete will cause loss of data

and/or damage to data.

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TIMING DIAGRAMS

Latch Timing Diagram for Command/Address/Data

Command Input Cycle Timing Diagram

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Address Input Cycle Timing Diagram

Data Input Cycle Timing Diagram

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Serial Read Cycle Timing Diagram

Status Read Cycle Timing Diagram

*: 70h represents the hexadecimal number

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Read Cycle Timing Diagram

Read Cycle Timing Diagram: When Interrupted by

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Read Cycle with Data Cache Timing Diagram (1/2)

*: The column address will be reset to 0 by the 31h command input

Read Cycle with Data Cache Timing Diagram (2/2)

Make sure to terminate the operation with 3Fh command

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Column Address Change in Read Cycle Timing Diagram (1/2)

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Column Address Change in Read Cycle Timing Diagram (2/2)

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Data Output Timing Diagram

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Auto-Program Operation Timing Diagram

*: M: up to 1087

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Auto-Program Operation with Data Cache Timing Diagram (1/3)

CA0 to CA10 is 0 in this diagram.

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Auto-Program Operation with Data Cache Timing Diagram (2/3)

Repeat a max of 62 times

(in order to program pages 1 to 62 of a block).

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Auto-Program Operation with Data Cache Timing Diagram (3/3)

(*1)

tPROG: Since the last page programming by 10h command is initiated after the previous cache

program, the tPROG during cache programming is given by the following equation.

tPROG = tPROG of the last page + tPROG of the previous page − A

A = (command input cycle + address input cycle + data input cycle time of the last page)

If “A” exceeds the tPROG of previous page, tPROG of the last page is tPROG max.

NOTE: Make sure to terminate the operation with 80h-10h- command sequence.

If the operation is terminated by 80h-15h command sequence, monitor I/O 6 (Ready / Busy) by

issuing Status Read command (70h) and make sure the previous page program operation is

completed. If the page program operation is completed issue FFh reset before next operation.

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Auto Block Erase Timing Diagram

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ID Read Operation Timing Diagram

Table 5: ID Definition Table

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512Mb(X16) LPDDR

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Descriptions

The 512Mb Mobile LPDDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits.

It is internally configured as a quad-bank DRAM.

The 512Mb chip is organized as 8Mbit x 4 banks x 16 I/O. Each of the x16’s 134,217,728-bit banks is organized as 8,192

rows by 1,024 columns by 16 bits. To achieve high-speed operation, our LPDDR SDRAM uses the double data rate

architecture and adopt 2n-prefetch interface designed to transfer two data per clock cycle at the I/O pins.

The chip is designed to comply with all key Mobile Double-Data-Rate SDRAM key features. All of the control and address

inputs are synchronized with a pair of externally supplied differential clocks, and latched at the cross point of differential

clocks (CK rising and  falling). The input data is registered at both edges of DQS, and the output data is referenced to

both edges of DQS, as well as to both edges of CK. DQS is a bidirectional data strobe signal, transmitted by the LPDDR

SDRAM during READs (edge-aligned with data), and by the memory controller during WRITEs (center-aligned with data).

LPDDR SDRAM, Read and Write access are burst oriented. The address bits registered coincident with the ACTIVE

command to select the row in the specific bank. And then the address bits registered with the READ or WRITE command to

select the starting column location in the bank for the burst access. The burst length can be programmed as 2, 4, 8 or 16.

An Auto Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of burst

access.

LPDDR SDRAM with Auto Refresh mode, and the Power-down mode for power saving. And the Deep Power Down Mode

can achieve the maximum power reduction by removing the memory array power within Low Power DDR SDRAM. With this

feature, the system can cut off almost all DRAM power without adding the cost of a power switch and giving up

month-board power-line layout flexibility. Self Refresh mode with Temperature Compensated Self Refresh (TCSR) and

Partial Array Self Refresh (PASR) options, which allow users to achieve additional power saving. The TCSR and PASR

options can be programmed via the extended mode register. The two features may be combined to achieve even greater

power saving. The DLL that is typically used on standard DDR devices is not necessary on the Mobile DDR SDRAM. It has

been omitted to save power.

All inputs are LVCMOS compatible. Devices will have a V_DDand V_DDQsupply of 1.8V (nominal).

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Absolute Maximum DC Ratings

Symbol

Parameter

Min

Max

2.4

Units

V_DD/ V_DDQ

V_DD/ V_DDQsupply voltage relative to Vss

-1.0

V

2.4 or (V_DDQ+ 0.3V),

Whichever is less

+150

Vin

Voltage on any pin relative to Vss

Storage Temperature (plastic)

-0.5

-55

V

Tstg

C

Notes:

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or any other conditions above those indicated in the

operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods

may affect reliability.

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM.

3. V_DDand V_DDQmust be within 300mV of each other at all times. V_DDQmust not exceed V_DD

.

Input / Output Capacitance

Symbol

Parameter

Min

Max

Unit

Notes

CCK

CDCK

CI

Input capacitance: CK, 

1.5

-

3.0

0.25

3.0

pF

Input capacitance delta: CK, 

2

3

Input capacitance, all other input-only pins

Input capacitance delta, all other input-only pins

Input/output capacitance, DQ, DM, DQS

Input/output capacitance delta, DQ, DM, DQS

1.5

-

CDI

0.5

CIO

3.0

-

5.0

0.5

CDIO

Notes:

1. These values are guaranteed by design and are tested on a sample base only.

2. These capacitance values are for single monolithic devices only. Multiple die packages will have parallel capacitive loads.

3. Input capacitance is measured according to JEP147 procedure for measuring capacitance using a vector network analyzer. VDD,

VDDQ are applied and all other pins (except the pin under test) floating. DQs should be in high impedance state. This may be

achieved by pulling CKE to low level.

4. Although DM is an input-only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins.

This is required to match signal propagation times of DQ, DQS and DM in the system.

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AC/DC Electrical Characteristics and Operating Conditions

Apply Note 1-3 to whole the table.

Symbol

V_DD

Parameter

Min

1.70

Max

1.95

Unit

V

Notes

Supply voltage

-

V_DDQ

I/O Supply voltage

V

Address and Command inputs

V_IH

V_IL

Input voltage high

Input voltage low

0.8 x V_DDQ

-0.3

V_DDQ+ 0.3

0.2 x V_DDQ

V

-

Clock inputs (CK, )

V_IN

V_ID(DC)

V_ID(AC)

V_IX

DC input voltage

-0.3

V_DDQ+ 0.3

V_DDQ+ 0.6

0.6 x V_DDQ

V

-

DC input differential voltage

AC Input Differential Voltage

AC Differential Crosspoint Voltage

0.4 x V_DDQ

0.6 x V_DDQ

0.4 x V_DDQ

2

3

Data inputs

V_IH(DC)

V_IL(DC)

V_IH(AC)

V_IL(AC)

DC input high voltage

0.7 x V_DDQ

-0.3

V_DDQ+ 0.3

0.3 x V_DDQ

V_DDQ+ 0.3

0.2 x V_DDQ

V

-

DC input low voltage

AC input high voltage

AC input low voltage

0.8 x V_DDQ

-0.3

Data outputs

V_OH

V_OL

DC output high voltage: Logic 1 (I_OH= -0.1mA)

DC output low voltage: Logic 0 (I_OL= -0.1mA)

0.9 x V_DDQ

-

V

-

0.1 x V_DDQ

Leakage current

Input leakage current

Any input 0 ≦ V_IN≦ V_DD

,

I_I

-1

-5

1

5

uA

All other pins not under test = 0V

Output leakage current

I_OZ

DQs are disabled; 0 ≦ V_OUT≦ V_DDQ

Notes:

1.All voltages referenced to VSS and VSSQ must be same potential.

2.VID(DC) and VID(AC) are the magnitude of the difference between the input level on CK and the input level on .

3.The value of VIX is expected to be 0.5 * VDDQ and must track variations in the DC level of the same.

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IDD Specifications and Measurement Conditions (32Mx16)

Notes 1–5 apply to all the parameters/conditions in this table

Symbol

Parameter/Condition

LPDDR400

Unit Notes

Operating one bank active-precharge current:

IDD0

IDD2P

IDD2PS

IDD2N

IDD2NS

IDD3P

IDD3PS

IDD3N

IDD3NS

IDD4R

IDD4W

tRC = tRCmin; tCK = tCKmin; CKE is HIGH;  is HIGH between valid commands;

address inputs are SWITCHING; data bus inputs are STABLE

70

300

15

mA

uA

6

7,8

7

Precharge power-down standby current:

all banks idle, CKE is LOW;  is HIGH, tCK = tCKmin;