NT5TU128M8HE-BENA_技术文档

1Gb DDR2 SDRAM

DDR2 1Gb SDRAM H-Die

Nanya Technology Corp.

NT5TU128M8HE / NT5TU64M16HG(Z)

Commercial, Industrial and Automotive DDR2 1Gb SDRAM

Features

 JEDEC DDR2 Compliant

 Data Integrity

- Double-data rate on DQs, DQS, DM bus

- 4n Prefetch Architecture

- Auto Refresh and Self Refresh Modes

 Power Saving Modes

 Throughput of valid Commands

- Posted CAS and Additive Latency (AL)

 Signal Integrity

- Power Down Mode

- Partial Array Self Refresh (PASR)

 SSTL_18 compliance and Power Supply

- VDD/VDDQ = 1.70 to 1.90V

- Configurable DS for system compatibility

- Configurable On-Die Termination

Options

 Temperature Range (Tc) ²

 Speed Grade ( DataRate/CL-tRCD-tRP)

- Commercial Grade = 0℃ to + 95℃

- 1066 Mbps / 7-7-7

- Industrial Grade (-I)= - 40℃ to + 95℃

- Automotive Grade 2 (-H)= - 40℃ to + 105℃

- Automotive Grade 3(-A) = - 40℃ to + 95℃

-

800 Mbps / 5-5-5

 Additional Features

- OCD adjustment Mode for DS tuning ¹

Programmable functions

 CAS Latency (5, 6, 7)

 Output Drive Impedance (Full, Reduced)

 Burst Length (4, 8)

 Additive Latency (0, 1, 2, 3, 4, 5, 6)

 WR (2, 3, 4, 5, 6, 7, 8)

 Burst Type (Sequential, Interleaved)

 Rtt (50, 75, 150)

 PASR (full, 3/4, 1/2, 1/4, 1/8)

Package / Density information

Lead-free RoHS compliance and Halogen-free

Density and Addressing

Configuration

128Mb x 8

64Mb x 16

1Gb

Length x Width

(mm)

Ball pitch

(mm)

(Org / Package)

Number of Banks

Bank Address

Auto Precharge

Row Address

Column Address

Page Size

8

60-ball

BA0 - BA2

A10/AP

A0 - A13

A0 - A9

1 KB

BA0 - BA2

A10/AP

A0 - A12

A0 - A9

2 KB

8.00 x 10.00(E)

8.00 x 12.50(G)

8.00 x 12.50(Z)

0.80

128Mb x 8

64Mb x 16

TFBGA

84-ball

TFBGA

84-ball

VFBGA

Notes:

1. This is enabled by using an electrical fuse. Please contact with NTC for the demand.

2. If TC exceeds 85°C, the DRAM must be refreshed externally at 2x refresh. It is required to set tREFI=3.9μs in auto refresh mode and to

set ‘1’ for EMRS (2) bit A7 in self refresh mode.

1

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NTC has the rights to change any specifications or product without notification.

1Gb DDR2 SDRAM

NT5TU128M8HE / NT5TU64M16HG(Z)

Major Timing Specifications for Corresponding Bins

DDR2-1066, DDR2-800 and DDR2-667

Speed Bin

CL-tRCD-tRP

Parameter

DDR2-1066

7-7-7

DDR2-800

5-5-5 6-6-6

DDR2-667

5-5-5

Units

min

max

min

max

min

max

min

max

13.125

58.125

45

-

12.5

57.5

45

-

15

60

45

3

-

15

60

45

3

-

ns

tRCD

tRP¹

-

tRC

70K

7.5

70K

8

70K

8

70K

8

tRAS

3

2.5

tCK(avg), CL=5

tCK(avg), CL=6

2.5

Option²

2.5

8

Option ²

1.875

Option ²

tCK(avg), CL=7

Notes

1. 8 bank device Precharge All Allowance : tRPall for a Precharge All command for an 8 Bank device is equal to tRP +

1 x tCK, where tRP is the value for a single bank precharge, which are shown in this table.

2. Please confirm with NTC for its availability.

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1Gb DDR2 SDRAM

NT5TU128M8HE / NT5TU64M16HG(Z)

Ordering Information

Lead-free RoHS compliance and Halogen-free

Commercial Grade

Speed

Data Rate(Mbps)

Organization

Part Number

Package

CL-TRCD-TRP

7-7-7

NT5TU128M8HE-BE

NT5TU128M8HE-AC

NT5TU64M16HG-BE

NT5TU64M16HG-AC

NT5TU64M16HZ-AC¹

NT5TU64M16HG-ACL²

1066

800

128 Mb x 8

60-Ball

5-5-5

1066

800

7-7-7

5-5-5

64 Mb x 16

84-Ball

800

5-5-5

800

5-5-5

Industrial Grade

Package

Speed

Organization

Part Number

Data Rate(Mbps)

CL-TRCD-TRP

5-5-5

128 Mb x 8

64 Mb x 16

NT5TU128M8HE-ACI

NT5TU64M16HG-ACI

60-Ball

84-Ball

800

5-5-5

Automotive Grade 2

Speed

Data Rate(Mbps)

Organization

Part Number

Package

CL-TRCD-TRP

5-5-5

128 Mb x 8

64 Mb x 16

NT5TU128M8HE-ACH

NT5TU64M16HG-ACH

60-Ball

84-Ball

800

5-5-5

Automotive Grade 3

128 Mb x 8

64 Mb x 16

Notes

NT5TU128M8HE-ACA

NT5TU64M16HG-ACA

60-Ball

84-Ball

800

5-5-5

1. Z=84-Ball BGA(Thin package)

2. L=Low IDD6

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1Gb DDR2 SDRAM

NT5TU128M8HE / NT5TU64M16HG(Z)

NANYA Component Part Numbering Guide

5T

U

L

NT

64M16

H

G

AC

Special Type Option

NA = Commercial Grade

I = Industrial Grade

H = Automotive Grade 2

A = Automotive Grade 3

L = Low IDD6

NANYA

Technology

Product Family

5T = DDR2 SDRAM

Interface & Power ( VDD & VDDQ )

U = SSTL_ 18 (1.8V,1.8V)

Speed

DDR2 SDRAM

AC = DDR2 - 800

BE = DDR2-1066

5-5-5

7-7-7

Organization (Depth , Width)

64M 16 = 128M 8 = 1Gb

Note:M=Mono

Package Code

RoHS + Halogen Free

Device Version

H = 8 Version

th

E=60 -Ball TFBGA

G=84- Ball TFBGA

Z=84-Ball VFBGA

Operating frequency

The backward compatibility of each speed grade is listed in a table below. If an application operates at specific frequency

which is not defined herein but within the highest and the lowest supporting grade, then the comparative loose

specifications to DRAM must be adopted from the neighboring defined speed bins.

For instance, DRAMs of -BE grade can support not only DDR3-1066 but also low speed bin like DDR3-800 or DDR3-667.

In case AP cooperates with DRAM of -BE grade and operates at undefined DDR3-900 condition, then CL must be set to 7

which is a comparative looser spec than 6. Do the same way for the rest parameters.

CL[nCK]

VDD[V]

7

6 or 5

1.8

5

Frequency

[Mbps]

1.8

667

DDR2-BE

DDR2-AC

1066

N/A

800

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1Gb DDR2 SDRAM

NT5TU128M8HE / NT5TU64M16HG(Z)

60-ball TFBGA Ballout and Package Outline Drawing (X8)

< TOP View>

See the balls through the package

1

2

3

4

5

6

7

8

DQS

VSSQ

DQ0

VSSQ

CK

9

A

B

C

D

E

F

NU/RDQS

A

B

C

D

E

F

VDD

DQ6

VDDQ

DQ4

VDDL

VSS

VSSQ

DQS

VDDQ

DQ2

VSSDL

RAS

CAS

A2

VDDQ

DQ7

DM/RDQS

VSSQ

DQ1

VDDQ

DQ3

VSS

WE

VDDQ

DQ5

VSSQ

VREF

CKE

VDD

ODT

CK

G

H

J

G

H

J

BA2

VSS

BA0

BA1

A1

CS

A10/AP

A3

A0

VDD

A5

A6

A4

K

L

K

L

A7

A9

A11

A8

VSS

VDD

A12

NC

A13

1

2

3

4

5

6

7

8

9

Unit: mm

* BSC (Basic Spacing between Center)

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1Gb DDR2 SDRAM

NT5TU128M8HE / NT5TU64M16HG(Z)

84-ball TFBGA Ballout and Package 8.00x12.50x1.20(mm) (X16)

< TOP View>

See the balls through the package

1

2

NC

3

VSS

UDM

VDDQ

DQ11

VSS

LDM

VDDQ

DQ3

VSS

WE

4

5

6

7

8

9

A

B

C

D

E

F

A

B

C

D

E

F

VDD

VSSQ

UDQS

VDDQ

DQ10

VSSQ

LDQS

VDDQ

DQ2

VSSDL

RAS

UDQS

VSSQ

DQ8

VSSQ

LDQS

VSSQ

DQ0

VSSQ

CK

VDDQ

DQ15

VDDQ

DQ13

VDDQ

DQ7

DQ14

VDDQ

DQ12

VDD

VSSQ

DQ9

VSSQ

NC

DQ6

VSSQ

DQ1

VSSQ

VREF

CKE

BA0

A10/AP

A3

G

H

J

G

H

J

VDDQ

DQ4

VDDQ

DQ5

VDDL

VDD

K

L

M

N

P

K

L

M

N

P

CK

ODT

BA2

VSS

BA1

A1

CAS

A2

CS

A0

VDD

VSS

9

A5

A6

A4

A7

A9

A11

A8

R

VDD

A12

NC

1

2

3

4

5

6

7

8

Unit: mm

* BSC (Basic Spacing between Center)

6

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03/2016

Nanya Technology Corporation ©

1Gb DDR2 SDRAM

NT5TU128M8HE / NT5TU64M16HG(Z)

84-ball VFBGA Ballout and Thin Package 8.00x12.50x1.00(mm) (X16)

< TOP View>

See the balls through the package

1

2

NC

3

VSS

UDM

VDDQ

DQ11

VSS

LDM

VDDQ

DQ3

VSS

WE

4

5

6

7

8

9

A

B

C

D

E

F

A

B

C

D

E

F

VDD

VSSQ

UDQS

VDDQ

DQ10

VSSQ

LDQS

VDDQ

DQ2

VSSDL

RAS

UDQS

VSSQ

DQ8

VSSQ

LDQS

VSSQ

DQ0

VSSQ

CK

VDDQ

DQ15

VDDQ

DQ13

VDDQ

DQ7

DQ14

VDDQ

DQ12

VDD

VSSQ

DQ9

VSSQ

NC

DQ6

VSSQ

DQ1

VSSQ

VREF

CKE

BA0

A10/AP

A3

G

H

J

G

H

J

VDDQ

DQ4

VDDQ

DQ5

VDDL

VDD

K

L

M

N

P

K

L

M

N

P

CK

ODT

BA2

VSS

BA1

A1

CAS

A2

CS

A0

VDD

VSS

9

A5

A6

A4

A7

A9

A11

A8

R

VDD

A12

NC

1

2

3

4

5

6

7

8

Unit: mm

* BSC (Basic Spacing between Center)

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1Gb DDR2 SDRAM

NT5TU128M8HE / NT5TU64M16HG(Z)

Ball Descriptions

Symbol

Type

Function

Clock: CK and CK are differential clock inputs. All address and control input signals are

sampled on the crossing of the positive edge of CK and negative edge of CK. Output

(read) data is referenced to the crossings of CK and CK (both directions of crossing).

CK, CK

Input

Clock Enable: CKE high activates, and CKE low deactivates, internal clock signals and

device input buffers and output drivers. Taking CKE low provides Precharge

Power-Down and Self-Refresh operation (all banks idle), or Active Power-Down (row

Active in any bank). CKE is synchronous for power down entry and exit and for

Self-Refresh entry. CKE is asynchronous for Self-Refresh exit. After VREF has become

stable during the power on and initialization sequence, it must be maintained for proper

operation of the CKE receiver. For proper self-refresh entry and exit, VREF must

maintain to this input. CKE must be maintained high throughout read and write

accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during Power

Down. Input buffers, excluding CKE, are disabled during Self-Refresh.

CKE

Input

Chip Select: All commands are masked when CS is registered high. CS provides for

external rank selection on systems with multiple memory ranks. CS is considered part

of the command code.

CS

Input

Command Inputs: RAS, CAS and WE (along with CS) define the command being

entered.

RAS, CAS,WE

Input Data Mask: DM is an input mask signal for write data. Input data is masked when

DM is sampled high coincident with that input data during a Write access. DM is sampled

on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ

and DQS loading. For x8 device, the function of DM or RDQS/RDQS is enabled by EMRS

command to EMR(1).

DM

Input

(LDM, UDM)

Bank Address Inputs: BA0 and BA2 define to which bank an Active, Read, Write or

Precharge command is being applied. Bank address also determines if the mode

register or extended mode register is to be accessed during a MRS or EMRS cycle.

Address Inputs: Provides the row address for Activate commands and the column

address and Auto Precharge or Read/Write commands to select one location out of the

memory array in the respective bank. A10 is sampled during a Precharge command to

determine whether the precharge applies to one bank (A10=low) or all banks

(A10=high). If only one bank is to be precharged, the bank is selected by BA0-BA2. The

address inputs also provide the op-code during Mode Register Set commands.

BA0 – BA2

A0 – A13

Input

DQ

Input/output Data Inputs/Output: Bi-directional data bus.

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1Gb DDR2 SDRAM

NT5TU128M8HE / NT5TU64M16HG(Z)

Symbol

Type

Function

Data Strobe: output with read data, input with write data. Edge aligned with read data,

centered with write data. For the x16, LDQS corresponds to the data on DQ0 - DQ7;

UDQS corresponds to the data on DQ8-DQ15. For the x8, an RDQS option using DM pin

can be enabled via the EMR(1) to simplify read timing. The data strobes DQS, LDQS and

UDQS may be used in single ended mode or paired with the optional complementary

signals DQS, LDQS and UDQS to provide differential pair signaling to the system during

both reads and writes. An EMRS(1) control bit enables or disables the complementary

data strobe signals.

DQS, (DQS)

(UDQS), (UDQS)

(LDQS), (LDQS)

(RDQS), (RDQS)

Input/output

On Die Termination: ODT (registered HIGH) enables termination resistance internal to

the DDR2 SDRAM. For x16 configuration ODT is applied to each DQ, UDQS, UDQS,

LDQS, LDQS, UDM and LDM signal. The ODT pin will be ignored if the EMRS (1) is

programmed to disable ODT.

ODT

Input

NC

VDDQ

VSSQ

VDDL

VSSDL

VDD

-

No Connect: No internal electrical connection is present.

DQ Power Supply: 1.8V ± 0.1V

Supply

DQ Ground

DLL Power Supply: 1.8V ± 0.1V

DLL Ground

Power Supply: 1.8V ± 0.1V

VSS

Ground

VREF

SSTL_1.8 reference voltage

NOTE: The signal may show up in a different symbol but it indicates the same thing. e.g., /CK = CK# = CK = CKb,

/DQS = DQS# = DQS = DQSb, /CS = CS# = CS = CSb.

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1Gb DDR2 SDRAM

NT5TU128M8HE / NT5TU64M16HG(Z)

Functional Descriptions

The 1Gb DDR2 SDRAM is a high-speed CMOS, dynamic random-access memory containing 1,073,741,824

bits.

Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and

continue for the burst length of four or eight in a programmed sequence. Accesses begin with the registration

of an Activate command, which is followed by a Read or Write command. The address bits registered

coincident with the activate command are used to select the bank and row to be accesses (BA0-BA2 select

the bank, A0-A13 select the row). The address bits registered coincident with the Read or Write command

are used to select the starting column location for the burst access and to determine if the Auto-Precharge

command is to be issued.

Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed

information covering device initialization, register definition, command description and device operation.

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1Gb DDR2 SDRAM

NT5TU128M8HE / NT5TU64M16HG(Z)

Power-up and Initialization

DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those

specified may result in undefined operation.

The following sequence is required for POWER UP and Initialization.

1. Either one of the following sequence is required for Power-up.

(1)

While applying power, attempt to maintain CKE below 0.2 x VDDQ and ODT at a Low state (all other inputs may be

undefined) The VDD voltage ramp time must be no greater than 200ms from when VDD ramps from 300mV to VDD

min; and during the VDD voltage ramp up, IVDD-VDDQI≦0.3 volts. Once the ramping of the supply voltages is

complete (when VDDQ crosses VDDQ min), the supply voltage specifications in Re-commanded DC operating

conditions table.

- VDD, VDDL, and VDDQ are driven from a signal power converter output, AND

- VTT is limited to 0.95V max, AND

- Vref tracks VDDQ/2; Vref must be within ±300mV with respect to VDDQ/2 during supply ramp time.

- VDDQ>=VREF must be met at all times.

(2)

While applying power, attempt to maintain CKE below 0.2 x VDDQ and ODT at a Low state, all other inputs may be

undefined, voltage levels at I/Os and outputs must be less than VDDQ during voltage ramp time to avoid DRAM

latch-up. During the ramping of the supply voltages, VDD≧VDDL≧VDDQ must be maintained and is applicable to

both AC and DC levels until the ramping of the supply voltages is complete, which is when VDDQ crosses VDDQ min.

Once the ramping of the supply voltages is complete, the supply voltage specifications provided in Re-commanded DC

operating conditions table.

- Apply VDD/VDDL before or at the same time as VDDQ.

- VDD/VDDL voltage ramp time must be no greater than 200ms from when VDD ramps from 300mV to VDDmin.

- Apply VDDQ before or at the same time as VTT.

- The VDDQ voltage ramp time from when VDD min is achieved on VDD to when VDDQ min is achieved on VDDQ

must be no greater than 500ms. (Note: While VDD is ramping, current may be supplied from VDD through the

DRAM to VDDQ.)

- Vref must track VDDQ/2; Vref must be within ±300mV with respect to VDDQ/2 during supply ramp time.

- VDDQ ≧ VREF must be met at all time.

- Apply VTT.

2. Start clock (CK, CK) and maintain stable condition.

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1Gb DDR2 SDRAM

NT5TU128M8HE / NT5TU64M16HG(Z)

3. For the minimum of 200us after stable power (VDD, VDDL, VDDQ, VREF, and VTT are between their minimum and

maximum values as stated in Re-commanded DC operating conditions table, and stable clock, then apply NOP or

Deselect & take CKE HIGH.

4. Wait minimum of 400 ns then issue precharge all command. NOP or Deselect applied during 400 ns period.

5. Issue an EMRS command to EMR(2). (To issue EMRS command to EMR(2), provide LOW to BA0 and BA2,HIGH to

BA1.)

6. Issue an EMRS command to EMR(3). (To issue EMRS command to EMR(3), provide LOW to BA2, HIGH to BA0 and

BA1.)

7. Issue EMRS to enable DLL. (To issue DLL Enable command, provide LOW to A0, HIGH to BA0 and LOW to BA1-BA2

and A13. And A9=A8=A7=LOW must be used when issuing this command.)

8. Issue a Mode Register Set command for DLL reset.(To issue DLL Reset command, provide HIGH to A8 and LOW to

BA0-BA2, and A13.)

9. Issue a precharge all command.

10. Issue 2 more auto-refresh commands.

11. Issue a MRS command with LOW to A8 to initialize device operation (i.e. to program operating parameters without

resetting the DLL.)

12. At least 200 clocks after step 7, execute OCD Calibration (Off Chip Driver impedance adjustment). If OCD calibration

is not used, EMRs to EMR (1) to set OCD Calibration Default (A9=A8=A7=HIGH) followed by EMRS to EMR (1) to

exit OCD Calibration Mode (A9=A8=A7=LOW) must be issued with other operating parameters of EMR(1).

13. The DDR2 DRAM is now ready for normal operation.

* To guarantee ODT off, VREF must be valid and a low level must be applied to the ODT pin.

Example:

CK, CK

CKE

ODT "low"

Follow OCD

flowchart

tMRD

tRP

tRFC

tRP

tRFC

400 ns

PRE

ALL

PRE

ALL

2nd Auto

refresh

1st Auto

refresh

EMRS

MRS

EMRS

MRS

NOP

EMRS

Extended Mode

Register Set

with DLL enable

Follow OCD

flowchart

min. 200 cycles to

lock the DLL

Mode Register Set

with DLL reset

Command

CMD

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1Gb DDR2 SDRAM

NT5TU128M8HE / NT5TU64M16HG(Z)

Register Definition

Programming the Mode Registration and Extended Mode Registers

For application flexibility, burst length, burst type, CAS latency, DLL reset function, write recovery time (tWR) are user

defined variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLL disable

function, additive CAS latency, driver impedance, ODT (On Die Termination), single-ended strobe and OCD (off chip

driver impedance adjustment) are also user defined variables and must be programmed with an Extended Mode Register

Set (EMRS) command. Contents of the Mode Register (MR) and Extended Mode Registers (EMR (#)) can be altered by

re-executing the MRS and EMRS Commands. If the user chooses to modify only a subset of the MRS or EMRS variables,

all variables must be redefined when the MRS or EMRS commands are issued. MRS, EMRS and DLL Reset do not affect

array contents, which mean re-initialization including those can be executed any time after power-up without affecting

array contents.

Mode Registration Set (MRS)

The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls CAS latency,

burst length, burst sequence, test mode, DLL reset, tWR and various vendor specific options to make DDR2 SDRAM

useful for various applications. The default value of the mode register is not defined, therefore the mode register must be

written after power-up for proper operation. The mode register is written by asserting low on CS, RAS, CAS, WE, BA0,

BA1 and BA2, while controlling the state of address pins A0 ~ A13. The DDR2 SDRAM should be in all banks precharged

(idle) mode with CKE already high prior to writing into the mode register. The mode register set command cycle time (t_MRD

is required to complete the write operation to the mode register. The mode register contents can be changed using the

same command and clock cycle requirements during normal operation as long as all banks are in the precharged state.

The mode register is divided into various fields depending on functionality. Burst length is defined by A0 ~ A2 with options

of 4 and 8 bit burst length. Burst address sequence type is defined by A3 and CAS latency is defined by A4 ~ A6. A7 is

used for test mode and must be set to low for normal MRS operation. A8 is used for DLL reset. A9 ~ A11 are used for

write recovery time (WR) definition for Auto-Precharge mode.

)

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1Gb DDR2 SDRAM

NT5TU128M8HE / NT5TU64M16HG(Z)

Mode Register – MR Programming

BA2 BA1 BA0 A13 A12 A11 A10 A9

A8

A7

A6

A5

A4

A3

↓

A2

A1

A0

↓

MR select

WR

CAS latency

Burst Length

0

PPD

DLL TM

BT

PPD

DLL Reset

No

Burst Type

A12

A8

0

A3

Fast exit (tXARD)

Sequential

Interleave

0

1

0

1

Slow exit (tXARDS)

Yes

1

MR select

MR

mode

Normal

Test

BA1 BA0

A7

0

1

0

1

0

1

EMRS(1)

EMRS(2)

EMRS(3)

1

A2

A1

1

A0

BL

4

0

1

8

WR

CAS Latency

A11 A10

A9

0

A6

A5

0

A4

0

Reserved

0

1

0

1

0

1

0

1

2

3

4

5

6

7

8

Reserved

1

0

1

Reserved

0

1

0

3

4

5

6

7

1

0

1

0

1

0

1

0

1

NOTE 1 Bits of Reserved for future use must be set to 0 when programming the MR.

NOTE 2 For DDR2-400/533, WR (write recovery for autoprecharge) min is determined by tCK max and WR max is determined by

tCK min. WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer

(WR[cycles] = RU{ tWR[ns] / tCK[ns] }, where RU stands for round up). For DDR2-667/800/1066, WR min is

determined by tCK(avg) max and WR max is determined by tCK(avg) min. WR[cycles] = RU{ tWR[ns] / tCK(avg)[ns] },

where RU stands for round up. The mode register must be programmed to this value. This is also used with tRP to

determine tDAL.

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Extended Mode Register Set -EMRS (1) Programming

BA2 BA1 BA0

A13

A12

A11

A10

A9

A8

A7

A6

↓

A5

A4

↓

AL

A3

A2

↓

A1

A0

↓

Rtt_Nom

MR select

OCD Cal

0

Qoff RDQS /DQS

D.I.C DLL

MR select

MR

EMRS(1)

EMRS(2)

EMRS(3)

DLL Enable

Enable

Disable

BA1 BA0

A10

0

1

/DQS

Enabled

A0

0

1

0

1

0

1

0

1

Disabled

Rtt_Nom

Disabled

75 ohm

150 ohm

50 ohm

A11 RDQS

A6

0

1

A2

0

1

0

1

Output Driver

Impedance

Full Strength

A1

Disabled

0

1

Enabled

0

1

Reduced Strength

Qoff

A12

0

1

Output buffer enabled

Output buffer disabled

AL

0

A5

0

A4

0

A3

0

1

0

1

OCD Cal ¹

A9

A8

A7

0

1

0

2

Maintain setting ;Exit

Drive(1)

Drive(0)

Adjust mode

Calibration default

3

4

5

6

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Reserved

Single-ended and Differential Data Strobe Signals

A11

A10

Strobe Function Matrix

RDQS

DQS

RDQS/DM

DM

RDQS

Hi-z

DQS

DQS

Hi-z

0(Disable)

1(Enable)

0(Enable)

1(Disable)

0(Enable)

1(Disable)

DM

Hi-z

RDQS

RDQS

Hi-z

DQS

Hi-z

NOTE 1 Default must be set to 0. This is enabled by using an electrical fuse. Please contact with NTC for the demand.

NOTE 2 Bits of Reserved for future use must be set to 0 when programming the EMR(1).

NOTE 3 When Adjust mode is issued, AL from previously set value must be applied.

NOTE 4 After setting to default, OCD calibration mode needs to be exited by setting A9-A7 to 000.

NOTE 5 Output disabled - DQs, DQSs, DQSs, RDQS, RDQS. This feature is used in conjunction with DIMM IDD measurements

when IDDQ is not desired to be included.

NOTE 6 If RDQS is enabled, the DM function is disabled. RDQS is active for reads and don’t care for writes.

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Extended Mode Register Set –EMRS (1)

The extended mode register EMRS(1) stores the data for enabling or disabling the DLL, output driver strength, additive

latency, ODT, DQS disable, OCD program, RQDS enable. The default value of the extended mode register EMRS(1) is

not defined, therefore the extended mode register must be written after power-up for proper operation. The extended

mode register is written by asserting low on CS, RAS, CAS, WE, BA1, BA2 and high on BA0, while controlling the state of

the address pins. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the

extended mode register. The mode register set command cycle time (t_MRD) must be satisfied to complete the write

operation to the EMRS (1). Mode register contents can be changed using the same command and clock cycle

requirements during normal operation as long as all banks are in precharge state. A0 is used for DLL enable or disable.

A1 is used for enabling a half strength output driver. A3-A5 determines the additive latency, A7-A9 are used for OCD

control, A10 is used for DQS disable and A11 is used for RDQS enable. A2 and A6 are used for ODT setting.

DLL Enable/Disable

The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning

to normal operation after having the DLL disabled. The DLL is automatically disabled when entering Self-Refresh

operation and is automatically re-enabled and reset upon exit of Self-Refresh operation. Any time the DLL is reset, 200

clock cycles must occur before a Read command can be issued to allow time for the internal clock to be synchronized

with the external clock. Less clock cycles may result in a violation of the t_ACor t_DQSCKparameters.

Output Disable (Qoff)

Under normal operation, the DRAM outputs are enabled during Read operation for driving data (Q_offbit in the EMRS (1) is

set to 0). When the Q_offbit is set to 1, the DRAM outputs will be disabled. Disabling the DRAM outputs allows users to

measure I_DDcurrents during Read operations, without including the output buffer current and external load currents.

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Extended Mode Register Set -EMRS (2) Programming

BA2 BA1 BA0 A13 A12 A11 A10 A9

A8

A7

↓

A6

A5

A4

A3

↓

A2

A1

A0

↓

0

↓

PASR

↓

MR select

0

SRF

DCC

High Temperature Self-Refresh Rate ³

DCC ¹

Disable

Enable

A7

0

1

A3

0

1

Disable

Enable

PASR ²

MR select

MR0

EMRS(1)

EMRS(2)

EMRS(3)

BA1 BA0

A2

0

A1

0

1

A0

0

1

0

1

Full Array

0

1

0

1

0

1

1/2 (BA[2:0]=000,001,010 and 011)

1/4 (BA[2:0]=000 and 001)

1/8 (BA[2:0]=000)

1

0

1

0

1

0

3/4 (BA[2:0]=010,011,100,101,110 and 111)

1/2 (BA[2:0]=100,101,110 and 111)

1/4 (BA[2:0]=110 and 111)

1

1/8 (BA[2:0]=111)

NOTE 1 Default must be set to 0. This is enabled by using an electrical fuse. Please contact with NTC for the demand.

NOTE 2 If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified address range will

be lost if self refresh is entered. Data integrity will be maintained if tREF conditions are met and no Self Refresh command

is issued.

NOTE 3 Controller must set the EMR(2)[A7] bit to enable the self-refresh rate in case of higher than 85 °C temperature self-refresh

operation.

NOTE 4 Bits of Reserved for future use must be set to 0 when programming the EMR(2).

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Extended Mode Register Set EMRS (2)

The Extended Mode Registers (2) controls refresh related features. The default value of the extended mode register(2) is

not defined, therefore the extended mode register(2) is written by asserting low on CS, RAS, CAS, WE, BA0, high on BA1

and low on BA2, while controlling the states of address pin A0-A13. The DDR2 SDRAM should be in all bank precharge

with CKE already high prior to writing into the extended mode register (2). The mode register set command cycle time

(tMRD) must be satisfied to complete the write operation to the extended mode register (2). Mode register contents can

be changed using the same command and clock cycle requirements during normal operation as long as all banks are in

the precharge state.

Extended Mode Register Set -EMRS (3) Programming

All bits in EMRS(3) expect BA0, BA1 and BA2 are reserved for future use and must be programmed to 0 when setting the

mode register during initialization.

BA2 BA1 BA0 A13 A12 A11 A10 A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

↓

0

1

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Off-Chip Driver (OCD) Impedance Adjustment

DDR2 SDRAM supports driver calibration feature and the flow chart below is an example of the sequence. Every

calibration mode command should be followed by “OCD calibration mode exit” before any other command being issued.

MRS should be set before entering OCD impedance adjustment and ODT (On Die Termination) should be carefully

controlled depending on system environment.

MRS should

be set before entering OCD impedance adjustment and ODT should

be carefully controlled depending on system environment

Start

EMRS: OCD calibration mode exit

EMRS: Drive(1)

EMRS: Drive(0)

DQ & DQS High; DQSLow

DQ & DQS Low; DQSHigh

ALL OK

Test

Need Calibration

EMRS: OCD calibration mode exit

EMRS :

Enter Adjus t Mode

Enter Adjust Mode

BL=4 code inpu t to all DQs

Inc, Dec, or NOP

BL=4 code input to all DQs

Inc, Dec, or NOP

EMRS: OCD calibration mode exit

End

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Extended Mode Register Set for OCD impedance adjustment

OCD impedance adjustment can be done using the following EMRS (1) mode. In drive mode all outputs are driven out by

DDR2 SDRAM and drive of RDQS is dependent on EMRS (1) bit enabling RDQS operation. In Drive (1) mode, all DQ, DQS

(and RDQS) signals are driven high and all DQS (and RDQS) signals are driven low. In Drive (0) mode, all DQ, DQS (and

RDQS) signals are driven low and all DQS (and RDQS) signals are driven high. In adjust mode, BL = 4 of operation code

data must be used. In case of OCD calibration default, output driver characteristics have a nominal impedance value of 18

Ohms during nominal temperature and voltage conditions. Output driver characteristics for OCD calibration default are

specified in the following table. OCD applies only to normal full strength output drive setting defined by EMRS (1) and if half

strength is set, OCD default driver characteristics are not applicable. When OCD calibration adjust mode is used, OCD

default output driver characteristics are not applicable. After OCD calibration is completed or driver strength is set to default,

subsequent EMRS(1) commands not intended to adjust OCD characteristics must specify A7~A9 as ’000’ in order to

maintain the default or calibrated value.

Off- Chip-Driver program

A9

A8

A7

Operation

OCD calibration mode exit

0

1

0

1

0

1

0

1

0

1

Drive(1) DQ, DQS, (RDQS) high and DQS low

Drive(0) DQ, DQS, (RDQS) low and DQS high

Adjust mode

OCD calibration default

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OCD impedance adjust

To adjust output driver impedance, controllers must issue the ADJUST EMRS (1) command along with a 4 bit burst code to

DDR2 SDRAM as in the following table. For this operation, Burst Length has to be set to BL = 4 via MRS command before

activating OCD and controllers must drive the burst code to all DQs at the same time. DT0 is the table means all DQ bits at

bit time 0, DT1 at bit time 1, and so forth. The driver output impedance is adjusted for all DDR2 SDRAM DQs

simultaneously and after OCD calibration, all DQs of a given DDR2 SDRAM will be adjusted to the same driver strength

setting. The maximum step count for adjustment can be up to 16 and when the limit is reached, further increment or

decrement code has no effect. The default setting may be any step within the maximum step count range. When Adjust

mode command is issued, AL from previously set value must be applied.

4 bit burst code inputs to all DQs

Operation

DT0

0

DT1

0

DT2

0

DT3

0

Pull-up driver strength Pull-down driver strength

NOP (no operation)

Increase by 1 step

Decrease by 1 step

NOP

NOP (no operation)

NOP

0

1

0

1

0

NOP

0

1

0

Increase by 1 step

Decrease by 1 step

Increase by 1 step

Decrease by 1 step

1

0

NOP

0

1

0

1

Increase by 1 step

Decrease by 1 step

Increase by 1 step

Decrease by 1 step

0

1

0

1

0

1

0

1

0

Other Combinations

Reserved

For proper operation of adjust mode, WL = RL - 1 = AL + CL -1 clocks and t_DS/ t_DHshould be met as the following timing

diagram. Input data pattern for adjustment, DT0 ~ DT3 is fixed and not affected by MRS addressing mode (i.e. sequential or

interleave).

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OCD Adjust Mode

OCD calibration

mode exit

OCD adjust mode

CK

EMRS

NOP

WL

NOP

DQS

NOP

WR

EMRS

NOP

CMD

DQS

tDS

tDH

DT0 DT1 DT2

DQ

DM

DT3

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Drive Mode

Drive mode, both Drive (1) and Drive (0), is used for controllers to measure DDR2 SDRAM Driver impedance before OCD

impedance adjustment. In this mode, all outputs are driven out t_OITafter “enter drive mode” command and all output drivers

are turned-off t_OITafter “OCD calibration mode exit” command as the following timing diagram.

CK, CK

CMD

NOP

EMRS(1)

NOP

EMRS(1)

NOP

tOIT

DQS_in

DQ_in

DQS high & DQS low for Drive(1), DQS low & DQS high for Drive 0

DQS high for Drive(1)

DQS high for Drive(0)

OCD calibration

mode exit

Enter Drive Mode

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On-Die Termination (ODT)

ODT (On-Die Termination) is a feature that allows a DRAM to turn on/off termination resistance for each DQ, DQ, DQS,

DQS, RDQS, RDQS, and DM signal for x16 configuration ODT is applied to each DQ, UDQS, UDQS, LDQS, LDQS, UDM

and LDM signal via the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel by

allowing the DRAM controller to independently turn on/off termination resistance for any or all DRAM devices.

The ODT function can be used for all active and standby modes. ODT is turned off and not supported in Self-Refresh mode.

Functional Representation of ODT

VDDQ

sw2

sw3

sw1

Rval2

Rval1

Rval3

DRAM

Input

Buffer

Input

Rval2

sw2

Rval1

sw1

Rval3

sw3

VSSQ

Switch sw1, sw2, or sw3 is enabled by the ODT pin. Selection between sw1, sw2, or sw3 is determined by “Rtt (nominal)” in

EMRS. Termination included on all DQs, DM, DQS, DQS, RDQS, and RDQS pins.

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ODT related timings

MRS command to ODT update delay

During normal operation the value of the effective termination resistance can be changed with an EMRS command. The

update of the Rtt setting is done between tMOD, min and tMOD, max, and CKE must remain HIGH for the entire duration of

tMOD window for proper operation. The timings are shown in the following timing diagram.

EMRS

NOP

CMD

CK, CK

CKE

t_IS

tMOD, max

tMOD, min

tAOFD

Old setting

Updating

New setting

Rtt

EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt(Nominal)

Setting in this diagram is the Register and I/O setting, not what is measured from outside.

However, to prevent any impedance glitch on the channel, the following conditions must be met.

- tAOFD must be met before issuing the EMRS command.

- ODT must remain LOW for the entire duration of tMOD window, until tMOD, max is met.

Now the ODT is ready for normal operation with the new setting, and the ODT may be raised again to turn on the ODT.

Following timing diagram shows the proper Rtt update procedure.

EMRS

NOP

CMD

CK, CK

CKE

t_IS

tAOND

tMOD, max

tAOFD

Old setting

New setting

Rtt

EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt(Nominal)

Setting in this diagram is the Register and I/O setting, not what is measured from outside.

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ODT On/Off timings

ODT timing for active/standby mode

T-1

T-0

T-2

T-3

T-4

T-6

T-5

CK ,CK

CKE

IS

t

IS

t

IS

ODT

tAOND

2 5 tck

( .

)

tAOFD

Rtt

Internal

Term Res.

tAON min

,

tAOF min

,

tAON max

,

tAOF max

,

ODT Timing for Power-down mode

T5

T6

T0

T1

T2

T3

T4

CK, CK

CKE

IS

t

ODT

DQ

t

IS

max

tAOFPD

,

min

tAOFPD

,

Rtt

tAONPD min

,

tAONPD max

,

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Bank Activate Command

The Bank Activate command is issued by holding CAS and WE high plus CS and RAS low at the rising edge of the clock.

The bank addresses BA0 ~ BA2 are used to select the desired bank. Row addresses A0 through A13 have to be applied.

The Bank Activate command must be applied before any Read or Write operation can be executed. Immediately after the

bank active command, the DDR2 SDRAM can accept a read or write command (with or without Auto-Precharge) on the

following clock cycle. If an R/W command is issued to a bank that has not satisfied the t_RCDminspecification, then additive

latency must be programmed into the device to delay the R/W command which is internally issued to the device. The

additive latency value must be chosen to assure t_RCDminis satisfied. Additive latencies of 0, 1, 2, 3, 4, 5, and 6 are supported.

Once a bank has been activated it must be precharged before another Bank Activate command can be applied to the same

bank. The bank active and precharge times are defined as t_RASand t_RP, respectively. The minimum time interval between

successive Bank Activate commands to the same bank is determined (t_RC). The minimum time interval between Bank

Active commands, to other bank, is the Bank A to Bank B delay time (t_RRD).

In order to ensure that 8 bank devices do not exceed the instantaneous current supplying capability of 4 bank devices,

certain restrictions on operation of the 8 bank devices must be observed. There are two rules. One for restricting the

number of sequential ACT commands that can be issued and another for allowing more time for RAS precharge for a

Precharge All command. The rules are list as follow:

* 8 bank device sequential Bank Activation Restriction: No more than 4 banks may be activated in a rolling tFAW window.

Converting to clocks is done by dividing tFAW by tCK and rounding up to next integer value. As an example of the rolling

window, if (tFAW/tCK) rounds up to 10 clocks, and an activate command is issued in clock N, no more than three further

activate commands may be issued in clock N+1 through N+9.

*8 bank device Precharge All Allowance: tRP for a Precharge All command for an 8 Bank device will equal to tRP+tCK,

where tRP is the value for a single bank pre-charge.

Bank Activate Command Cycle: t_RCD= 3, AL = 2, t_RP= 3, t_RRD= 2, t_CCD= 2

T0

T1

T2

T3

T4

Tn

Tn+1

Tn+2

Tn+3

CK, CK

Internal RAS-CAS delay tRCDmin.

Bank A

Col. Addr.

Bank B

Col. Addr.

Bank B

Addr.

Bank A

Row Addr.

Bank B

Row Addr.

Bank A

Addr.

Bank A

Row Addr.

NOP

Address

Bank A to Bank B delay tRRD.

additive latency AL=2

RAS-RAS delay tRRD.

Read A

Begins

Posted CAS

Read

Posted CAS

Read B

Bank A

Activate

Bank B

Activate

Bank A

Precharge

Bank B

Precharge

Bank A

Activate

Command

NOP

A

tRP Row Precharge Time (Bank A)

tRAS Row Active Time (Bank A)

ACT

tRC Row Cycle Time (Bank A)

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Read and Write Commands and Access Modes

After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS high, CS and

CAS low at the clock’s rising edge. WE must also be defined at this time to determine whether the access cycle is a read

operation (WE high) or a write operation (WE low). The DDR2 SDRAM provides a fast column access operation. A single

Read or Write Command will initiate a serial read or write operation on successive clock cycles. The boundary of the burst

cycle is restricted to specific segments of the page length.

A new burst access must not interrupt the previous 4 bit burst operation in case of BL = 4 setting. However, in case of

BL=8 setting, two cases of interrupt by a new burst access are allowed, one reads interrupted by a read, the other writes

interrupted by a write with 4 bit burst boundary respectively, and the minimum CAS to CAS delay (t_CCD) is minimum 2

clocks for read or write cycles.

Posted CAS

Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2

SDRAM. In this operation, the DDR2 SDRAM allows a Read or Write command to be issued immediately after the RAS

bank activate command (or any time during the RAS to CAS delay time, t_RCD, period). The command is held for the time of

the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is the sum of AL and the CAS

latency (CL). Therefore if a user chooses to issue a Read/Write command before the tRCDmin, then AL greater than 0

must be written into the EMRS (1). The Write Latency (WL) is always defined as RL - 1 (Read Latency -1) where Read

Latency is defined as the sum of Additive Latency plus CAS latency (RL=AL+CL). If a user chooses to issue a Read

command after the t_RCDminperiod, the Read Latency is also defined as RL = AL + CL.

Example of posted CAS operation:

Read followed by a write to the same bank:

AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 4

2

-1

0

1

3

4

5

6

7

8

9

10

11

12

CK, CK

CMD

Read

Write

Activate

Bank A

Bank A Bank A

WL = RL -1 = 4

AL = 2

CL = 3

DQS,

DQS

>=tRCD

RL = AL + CL = 5

Dout3

Dout2

DQ

Dout0

Din1

Din3

Din2

Dout1

Din0

PostCAS1

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Read followed by a write to the same bank:

AL = 0, CL = 3, RL = (AL + CL) = 3, WL = (RL -1) = 2, BL = 4

1

-1

0

3

4

5

6

7

8

9

10

11

12

2

CK, CK

CMD

AL=0

Read

Activate

Bank A

Write

Bank A

WL = RL – 1 = 2

>=tRCD

CL=3

DQS,

DQS

RL = AL + CL = 3

DQ

Din0

Din1

Din3

Dout2

Din2

Dout0 Dout1

Dout3

PostCAS5

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Burst Mode Operation

Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from

memory locations (read cycle). The parameters that define how the burst mode will operate are burst sequence

and burst length. The DDR2 SDRAM supports 4 bit and 8 bit burst modes only. For 8 bit burst mode, full

interleave address ordering is supported, however, sequential address ordering is nibble based for ease of

implementation. The burst type, either sequential or interleaved, is programmable and defined by the address

bit 3 (A3) of the MRS. Seamless burst read or write operations are supported. Interruption of a burst read or

write operation is prohibited, when burst length = 4 is programmed. For burst interruption of a read or write

burst when burst length = 8 is used, see the “Burst Interruption “section of this datasheet. A Burst Stop

command is not supported on DDR2 SDRAM devices.

Burst Length and Sequence

Starting Address

Sequential Addressing

(decimal)

Interleave Addressing

(decimal)

Burst Length

A2

-

A1

0

1

0

1

0

1

A0

0

1

0

1

0

1

0

1

0

1

0

1

0, 1, 2, 3

-

1, 2, 3, 0

1, 0, 3, 2

4

-

2, 3, 0, 1

-

3, 0, 1, 2

3, 2, 1, 0

0

1

0, 1, 2, 3, 4, 5, 6, 7

1, 2, 3, 0, 5, 6, 7, 4

2, 3, 0, 1, 6, 7, 4, 5

3, 0, 1, 2, 7, 4, 5, 6

4, 5, 6, 7, 0, 1, 2, 3

5, 6, 7, 4, 1, 2, 3, 0

6, 7, 4, 5, 2, 3, 0, 1

7, 4, 5, 6, 3, 0, 1, 2

0, 1, 2, 3, 4, 5, 6, 7

1, 0, 3, 2, 5, 4, 7, 6

2, 3, 0, 1, 6, 7, 4, 5

3, 2, 1, 0, 7, 6, 5, 4

4, 5, 6, 7, 0, 1, 2, 3

5, 4, 7, 6, 1, 0, 3, 2

6, 7, 4, 5, 2, 3, 0, 1

7, 6, 5, 4, 3, 2, 1, 0

8

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Burst Read Command

The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the

clock. The address inputs determine the starting column address for the burst. The delay from the start of the command

until the data from the first cell appears on the outputs is equal to the value of the read latency (RL). The data strobe output

(DQS) is driven low one clock cycle before valid data (DQ) is driven onto the data bus. The first bit of the burst is

synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out appears on the DQ pin in phase with

the DQS signal in a source synchronous manner. The RL is equal to an additive latency (AL) plus CAS latency (CL). The

CL is defined by the Mode Register Set (MRS). The AL is defined by the Extended Mode Register Set (EMRS (1))

Basic Burst Read Timing

t_CH

t_CL

t_CK

CLK

CLK, CLK

t_DQSCK

t_AC

DQS

DQS,

DQS

t_RPST

t_RPRE

t_HZ

t_LZ

DQ

Dout

t_DQSQmax

t_QH

DO-Read

Examples:

Burst Read Operation: RL = 5 (AL = 2, CL = 3, BL = 4)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK, CK

CMD

Post CAS

READ A

NOP

<= tDQSCK

DQS,

DQS

AL= 2

CL= 3

RL= 5

DQ

Dout A0 Dout A1

Dout A2 Dout A3

BRead523

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Burst Read Operation: RL = 3 (AL = 0, CL = 3, BL = 8)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK, CK

NOP

READ A

NOP

CMD

<= tDQSCK

DQS,

DQS

CL = 3

RL = 3

DQ's

Dout A0 Dout A1

Dout A2 Dout A3

Dout A4 Dout A5

Dout A6 Dout A7

BRead303

Burst Read followed by Burst Write : RL = 5, WL = (RL-1) = 4, BL = 4

The minimum time from the burst read command to the burst write command is defined by a read-to-write-turn-around

time(tRTW), which is 4 clocks in case of BL=4 operation, 6 clocks in case of BL=8 operation.

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Seamless Burst Read Operation: RL = 5, AL = 2, CL = 3, BL = 4

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK, CK

CMD

Post CAS

READ B

Post CAS

READ A

NOP

DQS,

DQS

AL= 2

CL= 3

RL= 5

DQ

Dout A0 Dout A1

Dout A2 Dout A3 Dout B0 Dout B1

Dout B2 Dout B3

SBR523

The seamless burst read operation’s supported by enabling a read command at every clock for BL=4 operation, and every

4 clock for BL=8 operation. This operation allows regardless of same or different banks as long as the banks activated.

Burst Write Command

The Burst Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising edge of the clock.

The address inputs determine the starting column address. Write latency (WL) is defined by a read latency (RL) minus one

and is equal to (AL + CL -1). A data strobe signal (DQS) has to be driven low (preamble) a time tWPRE prior to the WL. The

first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble. The

tDQSS specification must be satisfied for write cycles. The subsequent burst bit data are issued on successive edges of the

DQS until the burst length is completed, which is 4 or 8 bit burst. When the burst has finished, any additional data supplied

to the DQ pins will be ignored. The DQ signal is ignored after the burst write operation is complete. The time from the

completion of the burst write to bank precharge is named “write recovery time” (WR).

DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the

EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by which

the DDR2 SDRAM pin timing measured is mode dependent.

Basic Burst Write Timing

t_DQSH

t_DQSL

DQS

DQS,

DQS

t _WPST

t_WPRE

Din

t _DS

t_DH

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Example:

Burst Write Operation: RL = 5 (AL = 2, CL = 3), WL = 4, BL = 4

T0

T1

T2

T3

T4

T5

T6

T7

T9

CK, CK

CMD

Post CAS

WRITE A

NOP

Precharge

<= tDQSS

Completion of

the Burst Write

DQS,

DQS

tWR

WL = RL-1 = 4

DQ

DIN A0

DIN A1 DIN A2 DIN A3

BW543

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Burst Read followed by Burst Write : RL = 5, WL = (RL-1) = 4, BL = 4

The minimum time from the burst read command to the burst write command is defined by a read-to-write-turn-around

time(tRTW), which is 4 clocks in case of BL=4 operation, 6 clocks in case of BL=8 operation.

Burst Write followed by Burst Read: RL = 5 (AL = 2, CL = 3), WL = 4, tWTR = 2, BL = 4

T9

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK, CK

Write to Read = (CL - 1)+ BL/2 +tWTR(2) = 6

Post CAS

READ A

CMD

NOP

DQS,

DQS

CL=3

AL=2

tWTR

WL = RL - 1 = 4

DQ

DIN A0

DIN A1 DIN A2 DIN A3

RL=5

BWBR

The minimum number of clocks from the burst write command to the burst read command is (CL - 1) +BL/2 + t_WTRwhere

t_WTRis the write-to-read turn-around time t_WTRexpressed in clock cycles. The t_WTRis not a write recovery time (t_WR) but the

time required to transfer 4 bit write data from the input buffer into sense amplifiers in the array.

Seamless Burst Write Operation: RL = 5, WL = 4, BL = 4

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK, CK

CMD

Post CAS

WRITE B

Post CAS

WRITE A

NOP

DQS,

DQS

WL = RL - 1 = 4

DQ

DIN B0

DIN B1 DIN B2 DIN B3

DIN A0

DIN A1 DIN A2 DIN A3

SBR

The seamless burst write operation is supported by enabling a write command every BL / 2 number of clocks. This

operation is allowed regardless of same or different banks as long as the banks are activated.

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Write Data Mask

One write data mask input (DM) pin for each 8 data bits (DQ) will be supported on DDR2 SDRAMs, consistent with the

implementation on DDR SDRAMs. It has identical timings on write operations as the data bits, and though used in a

uni-directional manner, is internally loaded identically to data bits to insure matched system timing. DM of x16 bit

organization is not used during read cycles.

Write Data Mask Timing

t_DQSH

DQS

t_DQSL

DQS,

DQS

t _WPST

t_WPRE

DQ

DM

Din

t_DS

t_DH

don't care

Burst Write Operation with Data Mask: RL = 3 (AL = 0, CL = 3), WL = 2, t_WR= 3, BL = 4

T0

T1

T2

T3

T4

T5

T6

T7

T9

CK, CK

CMD

Bank A

Activate

NOP

WRITE A

NOP

Precharge

NOP

<= tDQSS

DQS,

DQS

WL = RL-1 = 2

tRP

tWR

DQ

DM

DIN A0

DIN A1 DIN A2 DIN A3

DM

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Burst Interruption

Interruption of a read or write burst is only allowed on burst of 8. Burst interrupt of 4 is prohibited.

Below are the constraints of burst interruption:

1. A Read Burst of 8 can only be interrupted by another Read command.

Read burst interruption by a Write or Precharge Command is prohibited.

2. A Write Burst of 8 can only be interrupted by another Write command.

Write burst interruption by a Read or Precharge Command is prohibited.

3. Read burst interrupt occur exactly two clocks after the previous Read command.

Any other Read burst interrupt timings are prohibited.

4. Write burst interrupt occur exactly two clocks after the previous Write command.

Any other Read burst interrupt timings are prohibited.

3. Read or Write burst interruption is allowed to any bank inside the DDR2 SDRAM.

4. Read or Write burst with Auto-Precharge enabled is not allowed to be interrupted.

5. Read burst interruption is allowed by a Read with Auto-Precharge command.

6. Write burst interruption is allowed by a Write with Auto-Precharge command.

Notes:

1. All command timings are referenced to burst length set in the mode register. They are not referenced to the

actual burst. For example, Minimum Read to Precharge timing is AL + BL/2 where BL is the burst length set

in the mode register and not the actual burst (which is shorter because of interrupt). Minimum Write to

Precharge timing is WL + BL/ 2 + tWR, where tWR starts with the rising clock after the un-interrupted burst

end and not form the end of the actual burst end.

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Examples:

Read Burst Interrupt Timing Example: (CL = 3, AL = 0, RL = 3, BL = 8)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK, CK

CMD

NOP

READ B

NOP

READ A

NOP

DQS,

DQS

DQ

Dout A0 Dout A1 Dout A2 Dout A3 Dout B0 Dout B1

Dout B2 Dout B3 Dout B4 Dout B5

Dout B6 Dout B7

RBI

Write Burst Interrupt Timing Example: (CL = 3, AL = 0, WL = 2, BL = 8)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK, CK

CMD

NOP

WRITE A

NOP

WRITE B

NOP

DQS,

DQS

DQ

Din A0

Din A1

Din A2

Din A3

Din B0

Din B1

Din B2

Din B3

Dout B4 Din B5

Din B6

Din B7

WBI

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Precharge Command

The Precharge Command is used to precharge or close a bank that has been activated. The Precharge

Command is triggered when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The

Pre-charge Command can be used to precharge each bank independently or all banks simultaneously. Three

address bits A10, BA0, BA1, and BA2 are used to define which bank to precharge when the command is

issued.

Bank Selection for Precharge by Address Bit

Precharge

A10

BA2

BA1

BA0

Bank(s)

Bank 0 only

Bank 1 only

Bank 2 only

Bank 3 only

Bank 4 only

Bank 5 only

Bank 6 only

Bank 7 only

All banks

LOW

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

Don't Care Don't Care Don't Care

Burst Read Operation Followed by a Precharge

Minimum Read to Precharge command spacing to the same bank = AL + BL/2 + max (RTP, 2) - 2 clocks.

For the earliest possible precharge, the Precharge command may be issued on the rising edge which is “Additive Latency

(AL) + BL/2 clocks” after a Read Command, as long as the minimum tRAS timing is satisfied.

The minimum Read to Precharge spacing has also to satisfy a minimum analog time from the rising clock edge that initiates

the last 4-bit prefetch of a Read to Precharge command. This time is call tRTP (Read to Precharge). For BL=4 this is the

time from the actual read (AL after the Read command) to Precharge command. For BL=8 this is the time from AL + 2

clocks after the Read to the Precharge command.

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Examples:

Burst Read Operation Followed by Precharge: RL = 4 (AL = 1, CL = 3), BL = 4, t_RTP≦ 2 clocks

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK, CK

CMD

Bank A

Activate

Post CAS

READ A

NOP

Precharge

NOP

AL + BL/2 clks

>=tRP

DQS,

DQS

AL = 1

CL = 3

RL = 4

DQ

Dout A0 Dout A1

Dout A2 Dout A3

>=tRAS

CL = 3

>=tRC

>=tRTP

BR-P413

Burst Read Operation Followed by Precharge: RL = 4 (AL = 1, CL = 3), BL = 8, t_RTP≦ 2 clocks

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK, CK

CMD

Post CAS

READ A

NOP

AL + BL/2 clks

NOP

Precharge

NOP

DQS,

DQS

AL = 1

CL = 3

RL = 4

DQ

Dout A0 Dout A1

Dout A2 Dout A3 Dout A4 Dout A5

Dout A6 Dout A7

>=tRAS

CL = 3

>=tRC

>=tRTP

BR-P413(8)

second 4-bit prefetch

first 4-bit prefetch

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Burst Read Operation Followed by Precharge: RL = 5 (AL = 2, CL = 3), BL = 4, t_RTP≦ 2 clocks

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK, CK

CMD

Bank A

Activate

Post CAS

READ A

NOP

>=tRP

NOP

Precharge

AL + BL/2 clks

DQS,

DQS

CL = 3

AL = 2

RL = 5

DQ

Dout A0 Dout A1

Dout A2 Dout A3

>=tRAS

CL = 3

>=tRC

>=tRTP

BR-P523

Burst Read Operation Followed by Precharge: RL = 6, (AL = 2, CL = 4), BL = 4, t_RTP≦ 2 clocks

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK, CK

CMD

Bank A

Activate

Precharge

A

Post CAS

READ A

NOP

>=tRP

NOP

AL + BL/2 clocks

DQS,

DQS

AL = 2

RL = 6

CL = 4

DQ

Dout A0 Dout A1

Dout A2 Dout A3

>=tRAS

CL = 4

>=tRC

>=tRTP

BR-P624

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Burst Read Operation Followed by Precharge: RL = 4, (AL = 0, CL = 4), BL = 8, t_RTP> 2 clocks

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK, CK

CMD

Bank A

Activate

NOP

Precharge

READ A

NOP

AL + BL/2 clks + 1

>=tRP

DQS,

DQS

CL = 4

RL = 4

DQ

Dout A0 Dout A1

Dout A2 Dout A3 Dout A4 Dout A5

Dout A6 Dout A7

>=tRAS

>=tRTP

BR-P404(8)

first 4-bit prefetch

second 4-bit prefetch

Burst Write followed by Precharge

Minimum Write to Precharge command spacing to the same bank = WL + BL/2 + t

. For write cycles, a delay

WR

must be satisfied from the completion of the last burst write cycle until the Precharge command can be issued.

This delay is known as a write recovery time (t_WR) referenced from the completion of the burst write to the

Precharge command. No Precharge command should be issued prior to the t_WRdelay, as DDR2 SDRAM does

not support any burst interrupt by a Precharge command. t_WRis an analog timing parameter (see the AC table

in this datasheet) and is not the programmed value for t_WRin the MRS.

Examples:

Burst Write followed by Precharge : WL = (RL - 1) = 3, BL = 4, t_WR= 3

T

0

T

1

T

2

T

3

T

4

T

5

T

6

T

7

T

8

CK, CK

CMD

Precharge

A

Post CAS

WRITE A

NOP

Completion of

the Burst Write

DQS,

DQS

>=tWR

WL = 3

DIN

A0

DIN

A1

DIN

A2

DIN

A3

DQ

BW-P3

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Burst Write followed by Precharge : WL = (RL - 1) = 4, BL = 4, t_WR= 3

T0

T1

T2

T3

T4

T5

T6

T7

T9

CK, CK

CMD

Precharge

A

Post CAS

WRITE A

NOP

Completion of

the Burst Write

DQS,

DQS

tWR

WL=4

DQ

DIN A0

DIN A1 DIN A2 DIN A3

BW-P4

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Auto-Precharge Operation

Before a new row in an active bank can be opened, the active bank must be precharged using either the Pre-charge

Command or the Auto-Precharge function. When a Read or a Write Command is given to the DDR2 SDRAM, the CAS

timing accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at the

earliest possible moment during the burst read or write cycle. If A10 is low when the Read or Write Command is issued,

then normal Read or Write burst operation is executed and the bank remains active at the completion of the burst sequence.

If A10 is high when the Read or Write Command is issued, then the Auto-Precharge function is enabled. During

Auto-Precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge

internally on the rising edge which is CAS Latency (CL) clock cycles before the end of the read burst. Auto-Precharge is

also implemented for Write Commands. The precharge operation engaged by the Auto-Precharge command will not begin

until the last data of the write burst sequence is properly stored in the memory array. This feature allows the precharge

operation to be partially or completely hidden during burst read cycles (dependent upon CAS Latency) thus improving

system performance for random data access. The RAS lockout circuit internally delays the precharge operation until the

array restore operation has been completed so that the Auto-Precharge command may be issued with any read or write

command.

Burst Read with Auto-Precharge

If A10 is high when a Read Command is issued, the Read with Auto-Precharge function is engaged. The DDR2 SDRAM

starts an Auto-Precharge operation on the rising edge which is (AL + BL/2) cycles later from the Read with AP command if

t_RAS(min) and t_RTPare satisfied. If t_RAS(min) is not satisfied at the edge, the start point of Auto-Precharge operation will be

delayed until t_RAS(min) is satisfied. If t_RTP(min) is not satisfied at the edge, the start point of Auto-Precharge operation will

be delayed until t_RTP(min) is satisfied.

In case the internal precharge is pushed out by t_RTP, t_RPstarts at the point where the internal precharge happens (not at the

next rising clock edge after this event). So for BL = 4 the minimum time from Read with Auto-Precharge to the next Activate

command becomes AL + t_RTP+ t_RP. For BL = 8 the time from Read with Auto-Precharge to the next Activate command is AL

+ 2 + t_RTP+ t_RP. Note that both parameters t_RTPand t_RPhave to be rounded up to the next integer value. In any event internal

precharge does not start earlier than two clocks after the last 4-bit prefetch.

A new bank active (command) may be issued to the same bank if the following two conditions are satisfied simultaneously:

(1) The RAS precharge time (t_RP) has been satisfied from the clock at which the Auto-Precharge begins.

(2) The RAS cycle time (t_RC) from the previous bank activation has been satisfied.

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Examples:

Burst Read with Auto-Precharge followed by an activation to the Same Bank (t_RCLimit)

RL = 5 (AL = 2, CL = 3), BL = 4, t_RTP≦ 2 clocks

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK, CK

CMD

Bank

Activate

Posted CAS

READ w/AP

NOP

A10 ="high"

Auto-Precharge Begins

AL + BL/2

RL = 5

DQS,

DQS

AL = 2

CL = 3

tRP

DQ

Dout A0 Dout A1

Dout A2 Dout A3

tRAS

tRCmin.

BR-AP5231

Burst Read with Auto-Precharge followed by an Activation to the Same Bank (tRAS Limit):

RL = 5 (AL = 2, CL = 3), BL = 4, tRTP ≦ 2 clocks

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK, CK

CMD

Bank

Activate

Posted CAS

READ w/AP

NOP

A10 ="high"

Auto-Precharge Begins

tRAS(min)

DQS,

DQS

AL = 2

CL = 3

tRP

RL = 5

DQ

Dout A0 Dout A1

Dout A2 Dout A3

tRC

BR-AP5232

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Burst Read with Auto-Precharge followed by an Activation to the Same Bank:

RL = 4 ( AL = 1, CL = 3), BL = 8, t_RTP≦ 2 clocks

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK, CK

CMD

Bank

Activate

Posted CAS

READ w/AP

NOP

A10 ="high"

AL + BL/2

tRP

Auto-Precharge Begins

DQS,

DQS

AL = 1

CL = 3

RL = 4

DQ

Dout A4 Dout A5

Dout A2 Dout A3

Dout A6 Dout A7

Dout A0 Dout A1

>= tRTP

BR-AP413(8)2

second 4-bit prefetch

first 4-bit prefetch

Burst Read with Auto-Precharge followed by an Activation to the Same Bank:

RL = 4 ( AL = 1, CL = 3), BL = 4, t_RTP> 2 clocks

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK, CK

CMD

Bank

Activate

Posted CAS

READ w/AP

NOP

A10 ="high"

AL + tRTP + tRP

Auto-Precharge Begins

DQS,

DQS

AL = 1

CL = 3

RL = 4

DQ

Dout A0 Dout A1

Dout A2 Dout A3

tRP

tRTP

BR-AP4133

first 4-bit prefetch

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Burst Write with Auto-Precharge

If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is engaged. The DDR2 SDRAM

automatically begins precharge operation after the completion of the write burst plus the write recovery time delay (WR),

programmed in the MRS register, as long as t_RASis satisfied. The bank undergoing Auto-Precharge from the completion of

the write burst may be reactivated if the following two conditions are satisfied.

(1) The last data-in to bank activate delay time (t_DAL= WR + t_RP) has been satisfied.

(2) The RAS cycle time (t_RC) from the previous bank activation has been satisfied.

Examples:

Burst Write with Auto-Precharge (t_RCLimit): WL = 2, t_DAL= 6 (WR = 3, t_RP= 3), BL = 4

T0

T1

T2

T3

T4

T5

T6

T7

CK, CK

CMD

WRITE

w/AP

Bank A

Activate

NOP

Completion of the Burst Write

NOP

A10 ="high"

Auto-Precharge Begins

DQS,

DQS

WR

tRP

WL = RL-1 = 2

tDAL

DQ

DIN A0

DIN A1 DIN A2 DIN A3

tRCmin.

>=tRASmin.

BW-AP223

Burst Write with Auto-Precharge (t_WR+ t_RPLimit) : WL = 4, t_DAL= 6 (t_WR= 3, t_RP= 3), BL = 4

0

3

4

5

6

7

8

T12

9

CK, CK

CMD

Bank A

Activate

Posted CAS

WRITE w/AP

NOP

Completion of the Burst Write

A10 ="high"

Auto-Precharge Begins

DQS,

DQS

tRP

tWR

tDAL

WL = RL-1 = 4

DIN

A0

DIN

A1

DIN

A2

DIN

A3

DQ

>=tRC

>=tRAS

BW-AP423

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Precharge & Auto Precharge Clarification

From

Minimum Delay between "From

command" to "to command"

To Command

Command

Units Note

AL + BL/2 + max(RTP,2) - 2

tCK

1,2

2

Precharge (to same Bank as Read)

Read

AL + BL/2 + max(RTP,2) - 2

Precharge All

AL + BL/2 + max(RTP,2) - 2

Precharge ( to same Bank as Read w/AP)

Read w/AP

AL + BL/2 + max(RTP,2) - 2

Precharge All

WL + BL/2 + tWR

Precharge (to same Bank as Write)

Write

WL + BL/2 + tWR

2

Precharge All

WL + BL/2 + WR

2

Precharge (to same bank as Write w/AP)

Write w/AP

WL + BL/2 + WR

2

Precharge All

1

2

Precharge (to same bank as Precharge)

Precharge

2

Precharge All

2

Precharge

Precharge All

2

Precharge All

Note:

1) RTP [cycles] = RU {tRTP(ns)/tCK(ns)}, where RI stands for round up.

2) For a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge or

precharge all, issued to that bank. The precharge period is satisfied after tRP or tRPa depending on the latest precharge command

issued to that bank.

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Refresh

SDRAMs require a refresh of all rows in any rolling 64 ms interval. Each refresh is generated in one of two ways: by an

explicit Auto-Refresh command, or by an internally timed event in Self-Refresh mode. Dividing the number of device rows

into the rolling 64 ms interval defined the average refresh interval t_REFI, which is a guideline to control for distributed refresh

timing. For example, a 1Gbit DDR2 SDRAM has 8392 rows resulting in a t_REFIof 7.8 µs.

Auto-Refresh Command

Auto-Refresh is used during normal operation of the DDR2 SDRAMs. This command is non persistent, so it must be issued

each time a refresh is required. The refresh addressing is generated by the internal refresh controller. This makes the

address bits ”Don’t Care” during an Auto-Refresh command. The DDR2 SDRAM requires Auto-Refresh cycles at an

average periodic interval of t_REFI(maximum).

When CS, RAS and CAS are held low and WE high at the rising edge of the clock, the chip enters the Auto-Refresh mode.

All banks of the SDRAM must be precharged and idle for a minimum of the precharge time (t_RP) before the Auto-Refresh

Command can be applied. An internal address counter supplies the addresses during the refresh cycle. No control of the

external address bus is required once this cycle has started.

When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the

Auto-Refresh Command and the next Activate Command or subsequent Auto-Refresh Command must be greater than or

equal to the Auto-Refresh cycle time (t_RFC).

To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval

is provided. A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM, meaning that the

maximum absolute interval between any Auto-Refresh command and the next Auto-Refresh command is 9 * t_REFI

.

T0

T1

T2

T3

CK, CK

"high"

CKE

> = t

RFC

NOP

RP

RFC

AUTO

REFRESH

AUTO

REFRESH

CMD

NOP

ANY

Precharge

NOP

AR

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Self-Refresh Command

The Self-Refresh command can be used to retain data, even if the rest of the system is powered down. When in the

Self-Refresh mode, the DDR2 SDRAM retains data without external clocking.

The DDR2 SDRAM device has a built-in timer to accommodate Self-Refresh operation. The Self-Refresh Command is

defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. ODT must be turned off

before issuing Self Refresh command, by either driving ODT pin low or using EMRS (1) command. Once the command is

registered, CKE must be held low to keep the device in Self-Refresh mode. When the DDR2 SDRAM has entered

Self-Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during

Self-Refresh Operation to save power. The user may change the external clock frequency or halt the external clock one

clock after Self-Refresh entry is registered, however, the clock must be restarted and stable before the device can exit

Self-Refresh operation. Once Self-Refresh Exit command is registered, a delay equal or longer than the t_XSNRor t_XSRDmust

be satisfied before a valid command can be issued to the device. CKE must remain high for the entire Self-Refresh exit

period (t_XSNRor t_XSRD) for proper operation. NOP or DESELECT commands must be registered on each positive clock edge

during the Self-Refresh exit interval. Since the ODT function is not supported during Self-Refresh operation, ODT has to be

turned off t_AOFDbefore entering Self-Refresh Mode and can be turned on again when the t_XSRDtiming is satisfied.

T4

T0

T5

Tm

Tr

T1

T2

T3

Tn

CK/CK

CKE

tRP*

tis

>=tXSRD

tis

tAOFD

>= tXSNR

ODT

CMD

Read

Command

Self Refresh

Entry

Non-Read

Command

NOP

CK/CK may

be halted

CK/CK must

be stable

* Device must be in theing "All banks idle" state to enter Self Refresh mode.

* ODT must be turned off prior to entering Self Refresh mode.

* tXSRD (>=200 tCK) has to be satisfied for a Read or as Read with Auto-Precharge commend.

* tXSNR has to be satisfied for any command execept Read or a Read with Auto-Precharge command, where tXSNR is defined as tRFC + 10ns.

* The minium CKE low time is defined by the tCKEmin. timming paramester.

* Since CKE is an SSTL input, VREF must maintained during Self-Refresh.

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Power-Down

Power-down is synchronously entered when CKE is registered low, along with NOP or Deselect command. CKE is not

allowed to go low while mode register or extended mode register command time, or read or write operation is in progress.

CKE is allowed to go low while any other operation such as row activation, Precharge, Auto-Precharge or Auto-Refresh is

in progress, but power-down IDD specification will not be applied until finishing those operations.

The DLL should be in a locked state when power-down is entered. Otherwise DLL should be reset after exiting power-down

mode for proper read operation.

If power-down occurs when all banks are precharged, this mode is referred to as Precharge Power-down; if power-down

occurs when there is a row active in any bank, this mode is referred to as Active Power-down. For Active Power-down two

different power saving modes can be selected within the MRS register, address bit A12. When A12 is set to “low” this mode

is referred as “standard active power-down mode” and a fast power-down exit timing defined by the t_XARDtiming parameter

can be used. When A12 is set to “high” this mode is referred as a power saving “low power active power-down mode”. This

mode takes longer to exit from the power-down mode and the t_XARDStiming parameter has to be satisfied.

Entering power-down deactivates the input and output buffers, excluding CK, CK, ODT and CKE. Also the DLL is disabled

upon entering Precharge Power-down or slow exit active power-down, but the DLL is kept enabled during fast exit active

power-down. In power-down mode, CKE low and a stable clock signal must be maintained at the inputs of the DDR2

SDRAM, and all other input signals are “Don’t Care”. Power-down duration is limited by 9 times tREFI of the device.

The power-down state is synchronously exited when CKE is registered high (along with a NOP or Deselect command). A

valid, executable command can be applied with power-down exit latency, t_XP, t_XARDor t_XARDS, after CKE goes high.

Power-down exit latencies are defined in the AC spec table of this data sheet.

Power-Down Entry

Active Power-down mode can be entered after an activate command. Precharge Power-down mode can be entered after a

precharge, Precharge-All or internal precharge command. It is also allowed to enter power-mode after an Auto-Refresh

command or MRS / EMRS(1) command when t_MRDis satisfied.

Active Power-down mode entry is prohibited as long as a Read Burst is in progress, meaning CKE should be kept high until

the burst operation is finished. Therefore Active Power-Down mode entry after a Read or Read with Auto-Precharge

command is allowed after RL + BL/2 is satisfied.

Active Power-down mode entry is prohibited as long as a Write Burst and the internal write recovery is in progress. In case

of a write command, active power-down mode entry is allowed then WL + BL/2 + tWTR is satisfied.

In case of a write command with Auto-Precharge, Power-down mode entry is allowed after the internal precharge command

has been executed, which WL + BL/2 + WR is starting from the write with Auto-Precharge command. In case the DDR2

SDRAM enters the Precharge Power-down mode.

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Examples:

Active Power-Down Mode Entry and Exit after an Activate Command

T0

T1

T2

Tn

Tn+1

Tn+2

CK, CK

Valid

Command

CMD

CKE

NOP

Activate

NOP

tIS

tXARD or

tXARDS *)

Act.PD 0

Active

Power-Down

Exit

Active

Power-Down

Entry

Active Power-Down Mode Entry and Exit after a Read Burst: RL = 4 (AL = 1, CL =3), BL = 4

Tn

Tn+1

T0

T1

T2

T3

T4

T5

T6

T7

T8

Tn+2

CK, CK

Valid

Command

READ

READ w/AP

CMD

CKE

NOP

tIS

RL + BL/2

tIS

DQS,

DQS

CL = 3

RL = 4

tXARD or

tXARDS *)

AL = 1

DQ

Dout A0 Dout A1 Dout A2 Dout A3

Active

Power-Down

Entry

Active

Power-Down

Exit

Act.PD 1

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Active Power-Down Mode Entry and Exit after a Write Burst: WL = 2, tWTR = 2, BL = 4

Tn

Tn+1

T0

T1

T2

T3

T4

T5

T6

T7

Tn+2

CK, CK

Valid

Command

CMD

CKE

NOP

WRITE

NOP

tIS

WL + BL/2 + tWTR

tIS

DQS,

DQS

WL = RL - 1 = 2

tWTR

tXARD or

tXARDS *)

DIN

A0

DIN

A1

DIN

A2

DIN

A3

DQ

Active

Power-Down

Exit

Active

Power-Down

Entry

Act.PD 2

Precharge Power Down Mode Entry and Exit

T0

T1

T2

T3

Tn

Tn+1

Tn+2

CK, CK

Valid

Command

Precharge

*)

CMD

CKE

NOP

tIS

tXP

tRP

Precharge

Power-Down

Entry

Precharge

Power-Down

Exit

*) "Precharge" may be an external command or an internal

precharge following Write with AP.

PrePD

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No Operation Command

The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state. The purpose of the No

Operation Command is to prevent the SDRAM from registering any unwanted commands between operations. A No

Operation Command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the clock. A No

Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle.

Deselect Command

The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is

brought high, the RAS, CAS, and WE signals become don’t care.

Input Clock Frequency Change

During operation the DRAM input clock frequency can be changed under the following conditions:

a) During Self-Refresh operation

b) DRAM is in Precharge Power-down mode and ODT is completely turned off.

The DDR2-SDRAM has to be in Precharged Power-down mode and idle. ODT must be already turned off and CKE must be

at a logic “low” state. After a minimum of two clock cycles after tRP and tAOFD have been satisfied the input clock

frequency can be changed. A stable new clock frequency has to be provided, before CKE can be changed to a “high” logic

level again. After t_XPhas been satisfied a DLL RESET command via EMRS(1) has to be issued. During the following DLL

re-lock period of 200 clock cycles, ODT must remain off. After the DLL-re-lock period the DRAM is ready to operate with the

new clock frequency.

Example:

Input frequency change during Precharge Power-Down mode

Ty+2

Tz

Ty+3

T0

T1

T2

T3

T4

Tx

Tx+1

Ty

Ty+1

CK, CK

DLL

RESET

Valid

Command

CMD

CKE

NOP

tRP

tAOFD

tXP

200 clocks

Minimum 2 clocks

required before

changing the frequency

Frequency Change

occurs here

Stable new clock

before power-down exit

ODT is off during

DLL RESET

Frequ.Ch.

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Asynchronous CKE Low Event

DRAM requires CKE to be maintained “high” for all valid operations as defined in this data sheet. If CKE asynchronously

drops “low” during any valid operation DRAM is not guaranteed to preserve the contents of the memory array. If this event

occurs, the memory controller must satisfy a time delay ( t_delay) before turning off the clocks. Stable clocks must exist at the

input of DRAM before CKE is raised “high” again. The DRAM must be fully re-initialized as described the the initialization

sequence. DRAM is ready for normal operation after the initialization sequence. See AC timing parametric table for t_delay

specification.

Asynchronous CKE Low Event

stable clocks

CK, CK

tdelay

CKE

CKE drops low due to an

asynchronous reset event

Clocks can be turned off after this point

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Command Truth Table

CKE

BA0-

BA2

A11-

A13

A0-

A9

Function

CS

RAS CAS WE

A10

Notes

Previous Current

Cycle

(Extended) Mode Register Set

Auto-Refresh

H

L

H

L

H

L

H

L

H

X

H

L

BA

X

OP Code

1, 2

1

X

Self-Refresh Entry

L

X

1,8

X

H

L

X

H

L

Self-Refresh Exit

L

H

X

1,7,8

Single Bank Precharge

Precharge all Banks

Bank Activate

H

X

BA

X

L

X

1,2

1

L

H

L

H

L

BA

X

Row Address

1,2

1,2,3

1

Write

H

X

H

X

H

Column

X

L

H

L

Column

X

Write with Auto-Precharge

Read

L

H

X

H

X

H

Read with Auto-Precharge

No Operation

L

H

X

H

X

H

X

H

Device Deselect

X

1

Power Down Entry

H

L

X

1,4

Power Down Exit

H

Notes:

1. All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS, and CKE at the rising edge of the clock.

2. Bank addresses (BAx) determine which bank is to be operated upon. For (E) MRS BAx selects an (Extended) Mode Register.

3. Burst reads or writes at BL = 4 cannot be terminated.

4. The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh

requirements outlined.

5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.

6. X means "H or L (but a defined logic level)".

7. Self refresh exit is asynchronous.

8. Vref must be maintained during Self Refresh operation.

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Clock Enable (CKE) Truth Table for Synchronous Transitions

CKE

Command (N)

Current State

Power-Down

Action (N)

Notes

Previous Current

RAS, CAS, WE, CS

Cycle

L

Cycle

L

X

Maintain Power-Down

Power-Down Exit

11, 13, 15

4, 8, 11, 13

11, 15, 16

L

H

L

H

L

DESELECT or NOP

X

Maintain Self Refresh

Self Refresh Exit

Self Refresh

Bank(s) Active

All Banks Idle

L

DESELECT or NOP

AUTOREFRESH

4, 5, 9, 16

H

Active Power-Down Entry

Precharge Power-Down Entry

Self Refresh Entry

4,8,10,11,13

6, 9, 11,13

Any State other than

listed above

H

Refer to the Command Truth Table

7

Notes:

1. CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.

2. Current state is the state of the DDR2 SDRAM immediately prior to clock edge N.

3. Command (N) is the command registered at clock edge N, and Action (N) is a result of Command (N).

4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.

5. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period.

Read commands may be issued only after tXSRD (200 clocks) is satisfied.

6. Self Refresh mode can only be entered from the All Banks Idle state.

7. Must be a legal command as defined in the Command Truth Table.

8. Valid commands for Power-Down Entry and Exit are NOP and DESELECT only.

9. Valid commands for Self Refresh Exit are NOP and DESELCT only.

10. Power-Down and Self Refresh cannot be entered while Read or Write operations, (Extended) mode Register operations, Precharge

or Refresh operations are in progress. See section 2.8 "Power Down" and section 2.7.2 "Self Refresh Command" for a detailed

list of restrictions.

11. Minimum CKE high time is 3 clocks, minimum CKE low time is 3 clocks.

12. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.

13. The Power-Down Mode does not perform any refresh operations. The duration of Power-Down Mode is therefore limited by the

refresh requirements.

14. CKE must be maintained high while the device is in OCD calibration mode.

15. "X" means "don't care (including floating around VREF)" in Self Refresh and Power Down. However DT must be driven high or

low in Power Down if the ODT function is enabled (Bit A2 or A6 set to "1" in MRS(1)).

16. Vref must be maintained during Self Refresh operation

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Operating Conditions

Absolute Maximum DC Ratings

Symbol

VDD

Parameter

Rating

Units Notes

Voltage on VDD pin relative to VSS

Voltage on VDDQ pin relative to VSS

Voltage on VDDL pin relative to VSS

Voltage on any pin relative to VSS

Storage Temperature

-1.0 to +2.3

-0.5 to +2.3

-55 to +150

V

1,3

1,4

1,2

VDDQ

V

VDDL

V

VIN, VOUT

TSTG

℃

Notes:

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress

rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections

of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM.

3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must be not greater than 0.6 x VDDQ. When VDD

and VDDQ and VDDL are less than 500 mV, Vref may be equal to or less than 300 mV.

4. Voltage on any input or I/O may not exceed voltage on VDDQ.

DRAM Component Temperature Range

Grade

Parameter

Rating

Units

Notes

1

Normal Operating Temperature Range

Extended Temperature Range

0 ≤Toper ≤ 85

Commercial

85 < Toper ≤ 95

-40 ≤ Toper ≤ 85

85 < Toper ≤ 95

-40 ≤ Toper ≤ 85

85 < Toper ≤ 105

-40 ≤ Toper ≤ 85

85 < Toper ≤ 95

1,2

1

Normal Operating Temperature Range

Extended Temperature Range

Industrial

1,2

1

C

Normal Operating Temperature Range

Extended Temperature Range

Automotive 2

Automotive 3

1,2

1

Normal Operating Temperature Range

Extended Temperature Range

1,2

Notes:

1. Operating temperature is the case surface temperature (TCASE) on the center/top side of the DRAM.

2. If TC exceeds 85°C,, the DRAM must be refreshed externally at 2x refresh. It is required to set tREFI=3.9μs in auto refresh

mode and to set ‘1’ for EMRS (2) bit A7 in self refresh mode.

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AC & DC Operating Conditions

DC Operating Conditions

Recommended DC Operating Conditions (SSTL_1.8)

Rating

Typ

Symbol

Parameter

Supply Voltage

Units

Notes

Min

1.7

Max

1.9

1.8

V

1

5

VDD

VDDDL

VDDQ

VREF

VTT

Supply Voltage for DLL

Supply Voltage for Output

Input Reference Voltage

Termination Voltage

1.7

1.8

1.9

1.7

1.8

1.9

1,5

2, 3

4

0.49 * VDDQ

VREF - 0.04

0.5 * VDDQ

VREF

0.51 * VDDQ

VREF + 0.04

Notes:

1. There is no specific device VDD supply voltage requirement for SSTL_18 compliance. However under all conditions VDDQ must be less

than or equal to VDD.

2. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to

be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.

3. Peak to peak ac noise on VREF may not exceed +/- 2% VREF (dc).

4. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors is expected to be set equal to VREF and

must track variations in die dc level of VREF.

5. VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ, and VDDL tied together.

ODT DC Electrical Characteristic

Parameter / Condition

Rtt eff. impedance value for EMRS(1)(A6,A2)=0,1; 75Ω

Rtt eff. impedance value for EMRS(1)(A6,A2)=1,0; 150Ω

Rtt eff. impedance value for EMRS(1)(A6,A2)=1,1; 50Ω

Deviation of VM with respect to VDDQ / 2

Notes:

Symbol

Rtt1(eff)

Rtt2(eff)

Rtt3(eff)

delta VM

Min

60

Nom

75

Max Units Notes

90

180

60

Ω

%

1

2

120

40

150

50

- 6

+ 6

1. Measurement Definition for Rtt(eff):

VIH (ac) - VIL (ac)

Rtt(eff) =

I(VIH (ac)) - I(VIL (ac))

2. Measurement Definition for VM:

2 x Vm

ΔVM = (

- 1 )

x

100%

VDDQ

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DC & AC Logic Input Levels

DDR2 SDRAM pin timing are specified for either single ended or differential mode depending on the setting of the EMRS(1)

“Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by which the

DDR2 SDRAM pin timing are measured is mode dependent. In single ended mode, timing relationships are measured

relative to the rising or falling edges of DQS crossing at VREF. In differential mode, these timing relationships are

measured relative to the cross point of DQS and its complement, DQS. This distinction in timing methods is guaranteed by

design and characterization. In single ended mode, the DQS (and RDQS) signals are internally disabled and don’t care.

Input DC logic level

Symbol

VIH(dc)

VIL(dc)

Parameter

Min

VREF + 0.125

-0.3

Max

Units

VDDQ + 0.3

VREF - 0.125

DC input logic high

DC input logic low

V

Input AC logic level

Symbol

DDR2-1066

DDR2-667, DDR2-800

Parameter

Units

Min

Max

Min

Max

VREF + 0.200

-

VREF + 0.200

VSSQ-Vpeak

VDDQ+Vpeak

VREF - 0.200

VIH(ac)

VIL(ac)

AC input logic high

AC input logic low

V

VREF - 0.200

NOTE 1 Refer to Overshoot/undershoot specifications for Vpeak value: maximum peak amplitude allowed for overshoot and undershoot.

AC input test conditions

Symbol

VREF

Condition

Value

0.5 x VDDQ

1.0

Units

V

Notes

Input reference voltage

1

VSWING(MAX)

SLEW

Input signal maximum peak to peak swing

Input signal minimum slew rate

V

1.0

V/ns

2,3

NOTE 1 Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test.

NOTE 2 The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges and the

range from VREF to VIL(ac) max for falling edges as shown in the below figure.

NOTE 3 AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac)

to VIL(ac) on the negative transitions.

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Differential input AC logic level

Units Notes

Symbol

VID (ac)

VIX (ac)

Parameter

Min

Max

VDDQ

DDR2-667/800

DDR2-1066

0.5

2,4

1

V

ac differential input voltage

VDDQ + 0.6

0.5 x VDDQ + 0.175

ac differential crosspoint voltage

0.5 x VDDQ - 0.175

3

NOTE 1 Follow JEDEC 1066 specification (JESD208)

NOTE 2 VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such

as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The

minimum value is equal to VIH(AC) - VIL(AC).

NOTE 3 The typical value of VIX(AC) is expected to be about 0.5 x VDDQ of the transmitting device and VIX(AC) is expected to

track variations in VDDQ. VIX(AC) indicates the voltage at which differential input signals must cross.

NOTE 4 Refer to Overshoot/undershoot specifications for Vpeak value: maximum peak amplitude allowed for overshoot and

undershoot.

Differential AC output parameters

Symbol

Parameter

Min

Max

Units Notes

ac differential crosspoint voltage

0.5 x VDDQ - 0.125

0.5 x VDDQ + 0.125

1

VOX (ac)

V

NOTE 1 The typical value of VOX(AC) is expected to be about 0.5 x VDDQ of the transmitting device and VOX(AC) is expected

to track variations in VDDQ . VOX(AC) indicates the voltage at which differential output signals must cross.

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Overshoot and Undershoot Specification

AC Overshoot / Undershoot Specification for Address and Control Pins

Parameter

DDR2-1066

DDR2-800

DDR2-667

Units

V

0.5(0.9) ¹

0.5

0.5(0.9) ¹

0.66

0.5(0.9) ¹

0.8

Maximum peak amplitude allowed for overshoot area

Maximum peak amplitude allowed for undershoot area

Maximum overshoot area above VDD

V

V/ns

Maximum undershoot area below VSS

0.5

0.66

0.8

NOTE 1 The maximum requirements for peak amplitude were reduced from 0.9V to 0.5V.

Maximum Amplitude

Overshoot Area

VDD

VSS

Undershoot Area

Maximum Amplitude

Time (ns)

AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins

Parameter

DDR2-1066

0.5

DDR2-800

0.5

DDR2-667

0.5

Units

V

Maximum peak amplitude allowed for overshoot area

Maximum peak amplitude allowed for undershoot area

Maximum overshoot area above VDD

0.5

V

0.19

0.23

V/ns

Maximum undershoot area below VSS

0.19

0.23

Maximum Amplitude

Overshoot Area

VDDQ

VSSQ

Undershoot Area

Maximum Amplitude

Time (ns)

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Power & Ground Clamp V-I Characteristics

Power and Ground clamps are provided on address, RAS, CAS, CS, WE, CKE, and ODT pins.

V-I characteristics for input-only pins with clamps

Voltage across Minimum Power Minimum Ground

Units

clamp (V)

Clamp Current

0.0

mA

0.1

0.2

0.0

0.3

0.0

0.4

0.0

0.5

0.0

0.6

0.0

0.7

0.0

0.8

0.1

0.9

1.0

2.5

1.1

4.7

1.2

6.8

1.3

9.1

1.4

11.0

13.5

16.0

18.2

21.0

11.0

13.5

16.0

18.2

21.0

1.5

1.6

1.7

1.8

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Output Buffer Levels

Output AC test conditions

Symbol

Parameter

SSTL_18

Units Notes

Output Timing Measurement Reference Level

0.5 x VDDQ

1

VOTR

V

NOTE 1 The VDDQ of the device under test is referenced.

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OCD default characteristics

Description

Parameter

Sout

Min

Nom

Max

Units

Notes

1-6

Output slew rate

1.5

-

5

V/ns

NOTE 1 Absolute Specifications (TOPER; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V). DRAM I/O specifications for timing,

voltage, and slew rate are no longer applicable if OCD is changed from default settings.

NOTE 2 Slew rate measured from vil(ac) to vih(ac).

NOTE 3 The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from

AC to AC. This is guaranteed by design and characterization.

NOTE 4 DRAM output slew rate specification applies to 400 MT/s, 533 MT/s & 667 MT/s speed bins.

NOTE 5 Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQ’s is included in tDQSQ and

tQHS specification.

NOTE 5 DDR2 SDRAM output slew rate test load is defined in the AC Timing specification Table.

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IDD Measurement Conditions

IDD values are for full operating range of Voltage and Temperature

Symbol

IDD0

Parameter/Condition

Operating one bank active-precharge current;

tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD);

CKE is HIGH, CS is HIGH between valid commands;

Address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

IDD1

Operating one bank active-read-precharge current;

IOUT = 0mA;

BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD);

CKE is HIGH, CS is HIGH between valid commands;

Address bus inputs are SWITCHING;

Data pattern is same as IDD4W

IDD2P

IDD2N

IDD2Q

Precharge power-down current;

All banks idle;

tCK = tCK(IDD);

CKE is LOW;

Other control and address bus inputs are STABLE;

Data bus inputs are FLOATING

Precharge standby current;

All banks idle;

tCK = tCK(IDD);

CKE is HIGH, CS is HIGH;

Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

Precharge quiet standby current;

All banks idle;

tCK = tCK(IDD);

CKE is HIGH, CS is HIGH;

Other control and address bus inputs are STABLE;

Data bus inputs are FLOATING

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IDD3P(0) Active power-down current;

All banks open;

tCK = tCK(IDD);

CKE is LOW;

Other control and address bus inputs are STABLE;

Data bus inputs are FLOATING

MRS A12 bit is set to "0"( Fast Power-down Exit);

IDD3P(1) Active power-down current;

All banks open;

tCK = tCK(IDD);

CKE is LOW;

Other control and address bus inputs are STABLE;

Data bus inputs are FLOATING

MRS A12 bit is set to "1"( Slow Power-down Exit);

IDD3N

Active standby current;

All banks open;

tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD);

CKE is HIGH, CS is HIGH between valid commands;

Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

IDD4R

Operating burst read current;

All banks open, Continuous burst reads, IOUT = 0 mA;

BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD);

CKE is HIGH, CS is HIGH between valid commands;

Address bus inputs are SWITCHING;

Data pattern is same as IDD4W

IDD4W

Operating burst write current;

All banks open, Continuous burst writes;

BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD);

CKE is HIGH, CS is HIGH between valid commands;

Address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

IDD5B

Burst refresh current;

tCK = tCK(IDD);

Refresh command at every tRFC(IDD) interval;

CKE is HIGH, CS is HIGH between valid commands;

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Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

IDD6

IDD7

Self refresh current;

CK and CK at 0 V;

CKE ≤ 0.2 V;

Other control and address bus inputs are FLOATING;

Data bus inputs are FLOATING

Operating bank interleave read current;

All bank interleaving reads, IOUT = 0mA;

BL = 4, CL = CL(IDD), AL = tRCD(IDD) - 1 x tCK(IDD);

tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tFAW = tFAW(IDD),

tRCD = 1 x tCK(IDD);

CKE is HIGH, CS is HIGH between valid commands;

Address bus inputs are STABLE during DESELECTs;

Data pattern is same as IDD4R;

- Refer to the following pages for detailed timing conditions

Notes:

1. IDD specifications are tested after the device is properly initialized

2. Input slew rate is specified by AC Parametric Test Condition

3. IDD parameters are specified with ODT disabled.

4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with

all combinations of EMRS bits 10 and 11.

5. For DDR2-667/800 testing, tCK in the Conditions should be interpreted as tCK(avg)

6. Definitions for IDD

- LOW = Vin ≤ VILAC(max)

- HIGH = Vin ≥ VIHAC(min)

- STABLE = inputs stable at a HIGH or LOW level

- FLOATING = inputs at VREF = VDDQ/2

- SWITCHING = inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and

control signals, and inputs changing between

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IDD testing parameters

Speed

DDR2-1066

7-7-7

DDR2-800

Units

CL-tRCD-tRP

5-5-5

CL(IDD)

7

13.125

58.125

7.5

5

12.5

57.5

7.5

tCK

ns

tRCD(IDD)

tRC(IDD)

tRRD(IDD) - X8

tRRD(IDD) - X16

tFAW(IDD) - X8

tFAW(IDD) - X16

tCK(IDD)

10

35

45

1.875

45

2.5

tRASmin(IDD)

tRASmax(IDD)

tRP(IDD)

45

70K

12.5

127.5

13.125

127.5

tRFC(IDD)

Detailed IDD7

Legend: A = Active; RA = Read with Autoprecharge; D = Deselect

IDD7: Operating Current: All Bank Interleave Read operation

All banks are being interleaved at minimum tRC(IDD) without violating tRRD(IDD) and tFAW(IDD) using a burst length of 4.

Control and address bus inputs are STABLE during DESELECTs. IOUT = 0 mA

Timing Patterns for 8 bank devices with 1 KB page size

-DDR2-667 all bins: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D

-DDR2-800 all bins: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D

-DDR2-1066 all bins: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D D

Timing Patterns for 8 bank devices with 2 KB page size

-DDR2-667 all bins: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D

-DDR2-800 all bins: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D

-DDR2-1066 all bins: A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D A4 RA4 D D D D A5 RA5 D D D D A6 RA6 D D

D D A7 RA7 D D D D

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IDD Specifications

Full operating range of Voltage and Temperature;

DDR2-800 DDR2-1066

X16

Symbol

Unit

X8

X16

X8

mA

IDD0

IDD1

55

70

9

60

75

9

65

80

10

30

23

70

85

10

30

23

IDD2P

IDD2N

IDD2Q

25

18

25

18

IDD3P0

mA

23

16

23

16

25

20

25

20

( Fast Exit )

IDD3P1

( Slow Exit )

mA

IDD3N

IDD4R

IDD4W

IDD5

32

100

115

100

9

32

115

130

100

9

37

135

150

125

10

37

150

165

125

10

IDD6

Low IDD6¹

-

5

-

IDD7

180

200

215

240

Note 1 It is only available for the specific part number which special type option is equal to 'L'.

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Input/output capacitance

DDR2-1066 DDR2-800 DDR2-667

Parameter

Symbol

Units

Min Max Min Max Min Max

Input capacitance, CK and CK

CCK

CDCK

CI

1.0

x

2.0

0.25

1.75

0.25

3.5

1.0

x

2.0

0.25

1.75

0.25

3.5

1.0

x

2.0

0.25

2.0

pF

Input capacitance delta, CK and CK

Input capacitance, all other input-only pins

Input capacitance delta, all other input-only pins

Input/output capacitance, DQ, DM, DQS, DQS

Input/output capacitance delta, DQ, DM, DQS, DQS

1.0

x

1.0

x

1.0

x

CDI

0.25

3.5

CIO

2.5

x

2.5

x

2.5

x

CDIO

0.5

Refresh parameters

Parameter

Symbol

Unit Notes

1Gb

Refresh to active/Refresh

1

tRFC

ns

127.5

command time

0℃≦Tcase≦85℃

1

1,2,3

1

7.8

3.9

7.8

3.9

7.8

3.9

7.8

3.9

Commercial

85℃≦Tcase≦95℃

- 40℃≦Tcase≦85℃

85℃≦Tcase≦95℃

- 40℃≦Tcase≦85℃

85℃≦Tcase≦105℃

- 40℃≦Tcase≦85℃

85℃≦Tcase≦95℃

Industrial

Average periodic

Refresh interval

1,2,3

1

tREFI

μs

Automotive 2

Automotive 3

1,2,3

1

1,2,3

NOTE 1 If refresh timing is violated, data corruption may occur and the data must be re-written with valid data

before a valid READ can be executed.

NOTE 2 This is an additional feature. For detailed information, please refer to “operating temperature condition”

chapter in this spec

NOTE 3 If TC exceeds 85°C, the DRAM must be refreshed externally at 2x refresh. It is required to set tREFI=3.9μs

in auto refresh mode and to set ‘1’ for EMRS (2) bit A7 in self refresh mode.

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AC & DC operating conditions

Timing parameters (DDR2-1066 and DDR2-800)

DDR2-1066

DDR2-800

Parameter

Symbol

Units³⁴

Notes

Min

Max

Min

Max

35,36

tCK

tCH

tCL

WL

ps

Clock cycle time

1875

0.48

7500

0.52

2500

0.48

8000

0.52

tCK(avg)

CK HIGH pulse width

CK LOW pulse width

Write command to DQS associated clock edge

RL - 1

DQS latching rising transitions to associated

clock edges

30

tDQSS

tCK(avg)

- 0.25

0.25

- 0.25

0.25

30

tDSS

tDSH

tCK(avg)

DQS falling edge to CK setup time

DQS falling edge hold time from CK

DQS input HIGH pulse width

DQS input LOW pulse width

Write preamble

0.2

-

0.2

-

tDQSH

tDQSL

tWPRE

tWPST

0.35

0.4

0.35

0.4

-

10

5,7,9,22

,29

Write postamble

0.6

tIS(base)

ps

Address and control input setup time

Address and control input hold time

125

-

175

-

5,7,9,23

,29

tIH(base)

tIPW

ps

tCK(avg)

ps

200

0.6

0

-

250

0.6

50

-

Control & Address input pulse width for each

input

6,7,8,20

,28,31

tDS(base)

DQ and DM input setup time (differential strobe)

DQ and DM input hold time (differential strobe)

6,7,8,21

,28,31

tDH(base)

ps

75

-

125

-

tDIPW

tAC

tCK(avg)

DQ and DM input pulse width for each input

DQ output access time from CK,CK

0.35

- 350

-

0.35

- 400

-

40

ps

350

400

350

40

tDQSCK

tHZ

DQS output access time from CK,CK

Data-out high-impedance time from CK,CK

DQS(DQS) low-impedance time from CK,CK

DQ low-impedance time from CK,CK

-325

325

- 350

18,40

-

tAC,max

-

tAC,max

tLZ(DQS)

tLZ(DQ)

tAC,min

2 x tAC,min

tAC,min

2 x tAC,min

DQS-DQ skew for DQS and associated DQ

signals

13

37

tDQSQ

tHP

ps

-

175

-

200

-

Min(tCH(abs

),tCL(abs) )

Min(tCH(abs

),tCL(abs) )

CK half pulse width

38

39

tQHS

tQH

ps

DQ hold skew factor

-

250

-

300

-

DQ/DQS output hold time from DQS

Read preamble

tHP-tQHS

0.9

tHP-tQHS

0.9

19,41

tRPRE

tCK(avg)

1.1

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DDR2-1066

Max

DDR2-800

Parameter

Symbol

Units³⁴

Notes

Min

0.4

Min

0.4

Max

0.6

19,42

4,32

tRPST

tRRD

tCK(avg)

ns

Read postamble

0.6

-

Active to active command period for 1KB page

7.5

10

7.5

10

size

Active to active command period for 2KB page

size

4,32

tRRD

ns

-

32

tFAW

tCCD

tWR

ns

Four Activate Window for 1KB page size

Four Activate Window for 2KB page size

CAS to CAS command delay

35

-

35

45

2

-

45

nCK

ns

2

15

32

33

Write recovery time

15

tDAL

tWTR

tRTP

nCK

ns

Auto precharge write recovery + precharge time

Internal write to read command delay

Internal read to precharge command delay

WR+tnRP

7.5

WR+tnRP

7.5

24,32

3,32

ns

7.5

CKE minimum pulse width (HIGH and LOW

pulse width)

27

32

tCKE

nCK

3

-

3

-

tXSNR

tXSRD

ns

Exit self refresh to a non-read command

Exit self refresh to a read command

tRFC + 10

200

-

tRFC + 10

200

-

nCK

Exit precharge power down to any non-read

command

tXP

nCK

ns

3

-

2

-

1

1,2

tXARD

tXARDS

tAOND

tAON

Exit active power down to read command

-

Exit active power down to read command (slow

exit, lower power)

10 - AL

2

-

8 - AL

2

-

16

ODT turn-on delay

ODT turn-on

2

tAC,max +

2.575

6,16,40

tAC,min

tACmax + 0.7

3 x tCK(avg)

+tAC,max + 1

2 x tCK(avg)

tAONPD

tAOFD

ns

ODT turn-on (Power-Down mode)

ODT turn-off delay

tAC,min + 2

2.5

tAC,min + 2

2.5

+tAC,max + 1

17,45

17,43,4

5

nCK

2.5

tAOF

ns

ODT turn-off

tAC,min

tAC,max + 0.6

tAC,min

tAC,max + 0.6

2.5 x tCK(avg)

+ tAC,max + 1

2.5 x tCK(avg)

+ tAC,max + 1

tAOFPD

ODT turn-off (Power-Down mode)

tAC,min + 2

tANPD

tAXPD

tMRD

tMOD

tOIT

nCK

ns

ODT to power down entry latency

ODT power down exit latency

4

11

2

-

3

8

2

0

-

Mode register set command cycle time

MRS command to ODT update delay

OCD drive mode output delay

-

32

0

12

ns

0

Minimum time clocks remains ON after CKE

asynchronously drops LOW

tIS +tCK(avg)

+tIH

tIS +tCK(avg)

+tIH

15

tDelay

ns

-

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AC & DC operating conditions

Timing parameters (DDR2-667)

DDR2-667

Parameter

Symbol

Units³⁴

Notes

Min

Max

35,36

tCK

tCH

ps

tCK(avg)

nCK

Clock cycle time

3000

0.48

8000

0.52

CK HIGH pulse width

tCL

CK LOW pulse width

WL

Write command to DQS associated clock edge

DQS latching rising transitions to associated clock edges

DQS falling edge to CK setup time

DQS falling edge hold time from CK

DQS input HIGH pulse width

RL - 1

30

tDQSS

tDSS

tCK(avg)

ps

- 0.25

0.2

0.25

-

tDSH

0.2

-

tDQSH

tDQSL

tWPRE

tWPST

tIS(base)

tIH(base)

tIPW

0.35

0.4

-

DQS input LOW pulse width

-

Write preamble

-

10

Write postamble

0.6

5,7,9,22,29

5,7,9,23,29

Address and control input setup time

Address and control input hold time

Control & Address input pulse width for each input

DQ and DM input setup time (differential strobe)

DQ and DM input hold time (differential strobe)

DQ and DM input pulse width for each input

DQ output access time from CK,CK

DQS output access time from CK,CK

Data-out high-impedance time from CK,CK

DQS(DQS) low-impedance time from CK,CK

DQ low-impedance time from CK,CK

DQS-DQ skew for DQS and associated DQ signals

200

-

ps

275

-

tCK(avg)

ps

0.6

-

6,7,8,20,28,31

6,7,8,21,28,31

tDS(base)

tDH(base)

tDIPW

tAC

100

-

ps

175

tCK(avg)

ps

0.35

- 450

- 400

-

40

450

tDQSCK

tHZ

ps

400

18,40

13

ps

tAC,max

240

tLZ(DQS)

tLZ(DQ)

tDQSQ

ps

tAC,min

2 x tAC,min

-

ps

Min(tCH(abs),tCL

(abs) )

37

tHP

ps

CK half pulse width

-

38

39

tQHS

tQH

ps

DQ hold skew factor

-

tHP - tQHS

0.9

340

DQ/DQS output hold time from DQS

Read preamble

-

19,41

19,42

4,32

32

tRPRE

tRPST

tRRD

tFAW

tCK(avg)

ns

1.1

Read postamble

0.4

0.6

Active to active command period for 1KB page size

Active to active command period for 2KB page size

Four Activate Window for 1KB page size

Four Activate Window for 2KB page size

7.5

-

ns

10

ns

37.5

50

32

ns

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DDR2-667

Parameter

Symbol

Units³⁴

Notes

Min

Max

tCCD

tWR

nCK

ns

CAS to CAS command delay

2

-

32

33

Write recovery time

15

tDAL

nCK

ns

Auto precharge write recovery + precharge time

Internal write to read command delay

Internal read to precharge command delay

CKE minimum pulse width(HIGH and LOW pulse width)

Exit self refresh to a non-read command

Exit self refresh to a read command

WR + tnRP

24,32

3,32

27

tWTR

tRTP

tCKE

tXSNR

tXSRD

tXP

7.5

ns

7.5

nCK

ns

3

32

tRFC + 10

nCK

200

2

Exit precharge power down to any non-read command

Exit active power down to read command

1

tXARD

2

Exit active power down to read command (slow exit, lower

power)

1,2

tXARDS

nCK

7 - AL

-

16

tAOND

tAON

nCK

ns

ODT turn-on delay

ODT turn-on

2

6,16,40

tAC,min

tACmax + 0.7

2 x tCK(avg)

tAONPD

ns

ODT turn-on (Power-Down mode)

tAC,min + 2

+tAC,max + 1

17,45

tAOFD

tAOF

nCK

ns

ODT turn-off delay

ODT turn-off

2.5

17,43,45

tAC,min

tAC,max + 0.6

2.5 x tCK(avg)

+ tAC,max + 1

tAOFPD

ns

ODT turn-off (Power-Down mode)

tAC,min + 2

tANPD

tAXPD

tMRD

tMOD

tOIT

nCK

ns

ODT to power down entry latency

ODT power down exit latency

3

8

2

0

-

Mode register set command cycle time

MRS command to ODT update delay

OCD drive mode output delay

-

32

12

ns

Minimum time clocks remains ON after CKE

asynchronously drops LOW

tIS +tCK(avg)

+tIH

15

tDelay

ns

-

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General notes, which may apply for all AC parameters

General Note 1 DDR2 SDRAM AC timing reference load

The figure represents the timing reference load used in defining the relevant timing parameters of the device. It is not intended to either a

precise representation of the typical system environment or a depiction of the actual load presented by a production tester. System

designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate

to their production test conditions, generally a coaxial transmission line terminated at the tester electronics. This reference load is also

used for output slew rate characterization.

The output timing reference voltage level for single ended signals is the cross point with VTT.

The output timing reference voltage level for differential signals is the cross point of the true (e.g. DQS) and the complement (e.g. DQS)

signal.

General Note 2 Slew Rate Measurement Levels

a) Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended

signals. For differential signals (e.g. DQS - DQS) output slew rate is measured between DQS - DQS = - 500mV and DQS -

DQS = + 500 mV. Output slew rate is guaranteed by design, but is not necessarily tested on each device.

b) Input slew rate for single ended signals is measured from Vref(dc) to VIH(ac),min for rising edges and from Vref(dc) to

VIL(ac),max for falling edges.

For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = - 250 mV to CK - CK = + 500 mV

(+ 250 mV to - 500 mV for falling edges).

c) VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between DQS and

DQS for differential strobe.

General Note 3 DDR2 SDRAM output slew rate test load

Output slew rate is characterized under the test conditions as following

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General Note 4 Differential data strobe

DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS “Enable

DQS” mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings

are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS

crossing at VREF. In differential mode, these timing relationships are measured relative to the cross point of DQS and its complement, DQS.

This distinction in timing methods is guaranteed by design and characterization. Note that when differential data strobe mode is disabled

via the EMRS, the complementary pin, DQS, must be tied externally to VSS through a 20 Ω to 10 kΩ resistor to insure proper operation.

General Note 5 AC timings are for linear signal transitions. See Specific Notes on derating for other signal transitions.

General Note 6 All voltages are referenced to VSS.

General Note 7 These parameters guarantee device behavior, but they are not necessarily tested on each device..

General Note 8 Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply

voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.

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Specific notes for dedicated AC parameters

Specific Note 1 User can choose which active power down exit timing to use via MRS (bit 12). tXARD is expected to be used for fast

active power down exit timing. tXARDS is expected to be used for slow active power down exit timing where a lower power value is defined

by each vendor data sheet.

Specific Note 2 AL = Additive Latency.

Specific Note 3 This is a minimum requirement. Minimum read to precharge timing is AL + BL / 2 provided that the tRTP and tRAS(min)

have been satisfied.

Specific Note 4 A minimum of two clocks (2 x tCK or 2 x nCK) is required irrespective of operating frequency.

Specific Note 5 Timings are specified with command/address input slew rate of 1.0 V/ns. See Specific Notes on derating for other slew

rate values.

Specific Note 6 Timings are specified with DQs, DM, and DQS’s (DQS/RDQS in single ended mode) input slew rate of 1.0V/ns. See

Specific Notes on derating for other slew rate values.

Specific Note 7 Timings are specified with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS signals with a

differential slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1 V/ns in single ended mode. See Specific Notes on derating

for other slew rate values.

Specific Note 8 Data setup and hold time derating.

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tDS/tDH derating with differential data strobe (DDR2-1066, DDR2-800, DDR2-667)

Δ tDS, Δ tDH Derating Values

DQS, DQS Differential Slew Rate

(Units: ps)

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4 V/ns

1.2 V/ns

1.0 V/ns

0.8 V/ns

△tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH

2

100

45

21

100

67

45

21

100

67

45

21

-

1.5 67

79

33

1

0

12

24

-

DQ

0.9

0.8

0.7

0.6

0.5

0.4

-

-5

-

-14

-5

-14

7

-2

19

11

2

10

-7

31

23

22

5

-

Slew rate

(V/ns)

-

-13 -31

-1

-19

35

17

-6

-

-10 -42

-30 14 -18 26

-47 14

-24 -89 -12

38

26

0

6

-

-10 -59

2

-35

-77

-23

-65

38

12

-11

-53

-

-52 -140 -40 -128 -28 -116

For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS(base) and

tDH(base) value to the ΔtDS and ΔtDH derating value respectively. Example: tDS (total setup time) = tDS(base) + ΔtDS.

Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of Vih(ac)min.

Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of Vil(ac)max.

If the actual signal is always earlier than the nominal slew rate line between shaded ‘VREF(dc) to ac region’, use nominal slew rate for derating value.

If the actual signal is later than the nominal slew rate line anywhere between shaded ‘VREF(dc) to ac region’, the slew rate of a tangent line to the

actual signal from the ac level to dc level is used for derating value.

Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vil(dc)max and the first crossing of VREF(dc).

Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of Vih(dc)min and the first crossing of VREF(dc).

If the actual signal is always later than the nominal slew rate line between shaded ‘dc level to VREF(dc) region’, use nominal slew rate for derating

value (see Figure 79 for differential data strobe.) If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to

VREF(dc) region’, the slew rate of a tangent line to the actual signal from the dc level to VREF(dc) level is used for derating value.

Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at the time of the rising

clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).

The derating values may be obtained by linear interpolation.

These values are typically not subject to production test. They are verified by design and characterization.

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Illustration of nominal slew rate for tDS (differential DQS, DQS)

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Illustration of nominal slew rate for tDS (single-ended DQS)

NOTE 1 DQS signal must be monotonic between Vil(dc)max and Vih(dc)min.

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Illustration of tangent line for tDS (differential DQS, DQS)

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Illustration of tangent line for tDS (single-ended DQS)

NOTE DQS signal must be monotonic between Vil(dc)max and Vih(dc)min.

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Illustration of nominal slew rate for tDH (differential DQS, DQS)

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Illustration of nominal slew rate for tDH (single-ended DQS)

NOTE DQS signal must be monotonic between Vil(dc)max and Vih(dc)min.

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Illustration tangent line for tDH (differential DQS, DQS)

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Illustration tangent line for tDH (single-ended DQS)

NOTE DQS signal must be monotonic between Vil(dc)max and Vih(dc)min.

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Specific Note 9 tIS and tIH (input setup and hold) derating

tIS/tIH derating with differential data strobe (DDR2-1066, DDR2-800, DDR2-667)

Δ tIS, Δ tIH Derating Values

CK, CK Differential Slew Rate

2.0 V/ns

1.5 V/ns

1.0 V/ns

Units

ΔtIS

ΔtIH

ΔtIS

ΔtIH

ΔtIS

ΔtIH

4.00

3.50

3.00

2.50

2.00

1.50

150

143

133

120

100

67

94

89

83

75

45

21

180

173

163

150

130

97

124

119

113

105

75

210

203

193

180

160

127

154

149

143

135

105

81

ps

Command

Address

Slew rate

(V/ns)

51

1.00

0.90

0.80

0.70

0.60

0.50

0.40

0.30

0.25

0.20

0.15

0.10

0

30

25

30

16

60

55

60

46

ps

-5

-14

-13

-31

17

-1

47

29

-22

-54

8

-24

38

6

-34

-83

-4

-53

26

-23

-60

-125

-188

-292

-375

-500

-708

-1125

-30

-70

-138

-170

-295

-487

-970

-95

0

-65

-100

-168

-200

-325

-517

-1000

-158

-262

-345

-470

-678

-1095

-40

-108

-140

-265

-457

-940

-128

-232

-315

-440

-648

-1065

For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH(base) value to the

Δ tIS and Δ tIH derating value respectively. Example: tIS (total setup time) = tIS(base) + Δ tIS Setup (tIS) nominal slew rate for a rising signal is

defined as the slew rate between the last crossing of VREF(dc) and the first crossing of Vih(ac)min. Setup (tIS) nominal slew rate for a falling signal

is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of Vil(ac)max. If the actual signal is always earlier than the

nominal slew rate line between shaded ‘VREF(dc) to ac region’, use nominal slew rate for derating value (see Figure 81). If the actual signal is later

than the nominal slew rate line anywhere between shaded ‘VREF(dc) to ac region’, the slew rate of a tangent line to the actual signal from the ac

level to dc level is used for derating value.

Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vil(dc)max and the first crossing of VREF(dc)

or the last crossing of Vih(dc)min and the first crossing of VREF(dc). If the actual signal is always later than the nominal slew rate line between

shaded ‘dc to VREF(dc) region’, use nominal slew rate for derating value. If the actual signal is earlier than the nominal slew rate line anywhere

between shaded ‘dc to VREF(dc) region’, the slew rate of a tangent line to the actual signal from the dc level to VREF(dc) level is used for derating

value.

Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at the time of the rising

clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac). For slew rates in between the values listed, the

derating values may obtained by linear interpolation. These values are typically not subject to production test. They are verified by design and

characterization.

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Illustration of nominal slew rate for tIS

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Illustration of tangent line for tIS

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Illustration of nominal slew rate for tIH

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Illustration tangent line for tIH

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Specific Note 10 The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this

parameter, but system performance (bus turnaround) will degrade accordingly.

Specific Note 11 MIN ( tCL, tCH) refers to the smaller of the actual clock LOW time and the actual clock HIGH

time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH).For example, tCL and

tCH are = 50% of the period, less the half period jitter ( tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk

( tJIT(crosstalk)) into the clock traces.

Specific Note 12 tQH = tHP – tQHS, where:

tHP = minimum half clock period for any given cycle and is defined by clock HIGH or clock LOW (tCH, tCL).

tQHS accounts for:

1) The pulse duration distortion of on-chip clock circuits; and

2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next

transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to

n-channel variation of the output drivers.

Specific Note 13 tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output

drivers as well as output slew rate mismatch between DQS / DQS and associated DQ in any given cycle.

Specific Note 14 tDAL = WR + RU{ tRP[ns] / tCK[ns] }, where RU stands for round up.

WR refers to the tWR parameter stored in the MRS. For tRP, if the result of the division is not already an integer,round up to the next

highest integer. tCK refers to the application clock period.

Example: For DDR533 at tCK = 3.75ns with WR programmed to 4 clocks.

tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.

Specific Note 15 The clock frequency is allowed to change during self–refresh mode or precharge power-down mode. In case of clock

frequency change during precharge power-down, a specific procedure is required.

Specific Note 16 ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on

time max is when the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For

DDR2-667/800, tAOND is 2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges.

Specific Note 17 ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time

max is when the bus is in high impedance. Both are measured from tAOFD, which is interpreted differently per

speed bin. For DDR2-667/800, if tCK(avg) = 3 ns is assumed, tAOFD is 1.5 ns (= 0.5 x 3 ns) after the second trailing clock edge counting

from the clock edge that registered a first ODT LOW and by counting the actual input clock edges.

Specific Note 18 tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a

specific voltage level which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) .The following figure shows a

method to calculate the point when device is no longer driving (tHZ), or begins driving (tLZ) by measuring the signal at two different

voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. tLZ(DQ) refers to tLZ of the DQ’s

and tLZ(DQS) refers to tLZ of the (U/L/R)DQS and ULRDQS each treated as single-ended signal.

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Specific Note 19 tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device

output is no longer driving (tRPST), or begins driving (tRPRE). The following figure shows a method to calculate these points when the

device is no longer driving (tRPST), or begins driving (tRPRE) by measuring the signal at two different voltages. The actual voltage

measurement points are not critical as long as the calculation is consistent.

Specific Note 20 Input waveform timing tDS with differential data strobe enabled MR[bit10]=0, is referenced from the input signal

crossing at the VIH(ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL(ac)

level to the differential data strobe crosspoint for a falling signal applied to the device under test. DQS, DQSsignals must be monotonic

between Vil(dc)max and Vih(dc)min.

Specific Note 21 Input waveform timing tDH with differential data strobe enabled MR[bit10]=0, is referenced

from the differential data strobe crosspoint to the input signal crossing at the VIH(dc) level for a falling signal and from the differential data

strobe crosspoint to the input signal crossing at the VIL(dc) level for a rising signal applied to the device under test. DQS,DQSsignals must

be monotonic between Vil(dc)max and Vih(dc)min.

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Specific Note 22 Input waveform timing is referenced from the input signal crossing at the VIH(ac) level for a rising signal and VIL(ac)

for a falling signal applied to the device under test.

Specific Note 23 Input waveform timing is referenced from the input signal crossing at the VIL(dc) level for a rising signal and VIH(dc)

for a falling signal applied to the device under test.

Specific Note 24 tWTR is at lease two clocks (2 x tCK or 2 x nCK) independent of operation frequency.

Specific Note 25 Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal

crossing at the VIH(ac) level to the single-ended data strobe crossing VIH/L(dc) at the start of its transition for a rising signal, and from the

input signal crossing at the VIL(ac) level to the single-ended data strobe crossing VIH/L(dc) at the start of its transition for a falling signal

applied to the device under test. The DQS signal must be monotonic between Vil(dc)max and Vih(dc)min.

Specific Note 26 Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal

crossing at the VIH(dc) level to the single-ended data strobe crossing VIH/L(ac) at the end of its transition for a rising signal, and from the

input signal crossing at the VIL(dc) level to the single-ended data strobe crossing VIH/L(ac) at the end of its transition for a falling signal

applied to the device under test. The DQS signal must be monotonic between Vil(dc)max and Vih(dc)min.

Specific Note 27 tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges.CKE must remain at

the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition

from its valid level during the time period of tIS + 2 x tCK + tIH.

Specific Note 28 If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid

data before a valid READ can be executed.

Specific Note 29 These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE,ODT, BA0, A0, A1, etc.)

transition edge to its respective clock signal (CK/CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e.

tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these

parameters should be met whether clock jitter is present or not.

Specific Note 30 These parameters are measured from a data strobe signal ((L/U/R)DQS/DQS) crossing to its

respective clock signal (CK/CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.),

as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not.

Specific Note 31 These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.)

transition edge to its respective data strobe signal ((L/U/R)DQS/DQS) crossing.

Specific Note 32 For these parameters, the DDR2 SDRAM device is characterized and verified to support

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tnPARAM = RU{tPARAM / tCK(avg)}, which is in clock cycles, assuming all input clock jitter specifications are satisfied.

For example, the device will support tnRP = RU{tRP / tCK(avg)}, which is in clock cycles, if all input clock jitter specifications are met. This

means: For DDR2-667 5-5-5, of which tRP = 15ns, the device will support tnRP =RU{tRP / tCK(avg)} = 5, i.e. as long as the input clock

jitter specifications are met, Precharge command at Tm and active command at Tm+5 is valid even if (Tm+5 - Tm) is less than 15ns due to

input clock jitter.

Specific Note 33 tDAL [nCK] = WR [nCK] + tnRP [nCK] = WR + RU {tRP [ps] / tCK(avg) [ps] }, where WR is the value programmed in

the mode register set.

ex) For DDR2-1066 7-7-7 at tCK(avg) = 1.875 ns with WR programmed to 8 nCK,

tDAL = 8 + RU{13.125 ns / 1.875 ns} [nCK] = 8 + 7 [nCK] = 15 [nCK]

Specific Note 34 New units, ‘tCK(avg)’ and ‘nCK’, are introduced in DDR2-667, DDR2-800 and DDR2-1066

Unit ‘tCK(avg)’ represents the actual tCK(avg) of the input clock under operation.

Unit ‘nCK’ represents one clock cycle of the input clock, counting the actual clock edges.

ex) tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm+2,even if (Tm+2 - Tm) is 2

x tCK(avg) + tERR(2per),min.

ex) tXP = 3 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm+3, even if (Tm+3 -

Tm) is 3 x tCK(avg) + tERR(3per),min.

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Specific Note 35 Input clock jitter spec parameter. These parameters and the ones in the table below are referred to as 'input clock jitter

spec parameters' and these parameters apply. The jitter specified is a random jitter meeting a Gaussian distribution.

Input clock jitter spec parameter apply

DDR2-1066

DDR2-800

DDR2-667

Parameter

Symbol

Units

min

-90

max

90

min

-100

-80

max

100

80

min

-125

-100

-250

-200

-175

-225

-250

-350

-450

-125

max

125

100

250

200

175

225

250

350

450

125

Clock period jitter

tJIT(per)

tJIT(per,lck)

tJIT(cc)

ps

Clock period jitter during DLL locking period

Cycle to cycle clock period jitter

-80

80

-180

-160

-132

-157

-175

-188

-250

180

160

132

157

175

188

250

425

75

-200

-160

-150

-175

-200

-300

-450

-100

200

160

150

175

200

300

450

100

Cycle to cycle clock period jitter during DLL locking period

Cumulative error across 2 cycles

tJIT(cc,lck)

tERR(2per)

tERR(3per)

tERR(4per)

tERR(5per)

tERR(6-10per)

Cumulative error across 3 cycles

Cumulative error across 4 cycles

Cumulative error across 5 cycles

Cumulative error across n cycles,n = 6 ... 10, inclusive

Cumulative error across n cycles,n = 11 ... 50, inclusive

Duty cycle jitter

tERR(11-50per) -425

tJIT(duty) -75

Definitions:

- tCK(avg)

tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window.

- tCH(avg) and tCL(avg)

tCH(avg) is defined as the average HIGH pulse width, as calculated across any consecutive 200 HIGH pulses.

tCL(avg) is defined as the average LOW pulse width, as calculated across any consecutive 200 LOW pulses.

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- tJIT(duty)

tJIT(duty) is defined as the cumulative set of tCH jitter and tCL jitter. tCH jitter is the largest deviation of

any single tCH from tCH(avg). tCL jitter is the largest deviation of any single tCL from tCL(avg).

tJIT(duty) = Min/max of {tJIT(CH), tJIT(CL)}

where,

tJIT(CH) = {tCHi- tCH(avg) where i=1 to 200}

tJIT(CL) = {tCLi- tCL(avg) where i=1 to 200}

- tJIT(per), tJIT(per,lck)

tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg).

tJIT(per) = Min/max of {tCKi- tCK(avg) where i=1 to 200}

tJIT(per) defines the single period jitter when the DLL is already locked.

tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only.

tJIT(per) and tJIT(per,lck) are not guaranteed through final production testing.

- tJIT(cc), tJIT(cc,lck)

tJIT(cc) is defined as the difference in clock period between two consecutive clock cycles:

tJIT(cc) = Max of |tCKi+1 – tCKi|

tJIT(cc) defines the cycle to cycle jitter when the DLL is already locked.

tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only.

tJIT(cc) and tJIT(cc,lck) are not guaranteed through final production testing.

- tERR(2per), tERR (3per), tERR (4per), tERR (5per), tERR (6-10per) and tERR (11-50per)

tERR is defined as the cumulative error across multiple consecutive cycles from tCK(avg).

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Specific Note 36 These parameters are specified per their average values, however it is understood that the following relationship

between the average timing and the absolute instantaneous timing holds at all times. (min and max of SPEC values are to be used for

calculations in the table below.)

Parameter

Symbol

min

max

Units

Absolute clock period

tCK(abs)

tCK(avg),min + tJIT(per),min

tCK(avg),max + tJIT(per),max

ps

tCH(avg),min x tCK(avg),min

+tJIT(duty),min

tCH(avg),max x tCK(avg),max +

tJIT(duty),max

Absolute clock HIGH pulse width

Absolute clock LOW pulse width

tCH(abs)

tCL(abs)

ps

tCL(avg),min x tCK(avg),min +

tJIT(duty),min

tCL(avg),max x tCK(avg),max +

tJIT(duty),max

Example: For DDR2-667, tCH(abs),min = ( 0.48 x 3000 ps ) - 125 ps = 1315 ps

Specific Note 37 tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input

specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation

is determined by the following equation;

tHP = Min ( tCH(abs), tCL(abs) ),

where,

tCH(abs) is the minimum of the actual instantaneous clock HIGH time;

tCL(abs) is the minimum of the actual instantaneous clock LOW time;

Specific Note 38 tQHS accounts for:

1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is transferred to the output;

and

2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are

independent of each other, due to data pin skew, output pattern effects, and p-channel to n-channel variation of the output drivers

Specific Note 39 tQH = tHP – tQHS, where:

tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under the max column.

{The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.}

Examples:

1) If the system provides tHP of 1315 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 975 ps minimum.

2) If the system provides tHP of 1420 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 1080 ps minimum.

3) If the system provides tHP of 825 ps into a DDR2-1066 SDRAM, the DRAM provides tQH of 575 ps minimum.

4) If the system provides tHP of 900 ps into a DDR2-1066 SDRAM, the DRAM provides tQH of 650 ps minimum.

Specific Note 40 When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per)

of the input clock. (output deratings are relative to the SDRAM input clock.)

For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10per),min = - 272 ps and tERR(6-10per),max = + 293 ps,

then tDQSCK,min(derated) = tDQSCK,min - tERR(6-10per),max = - 400 ps - 293 ps = - 693 ps and tDQSCK,max(derated) =

tDQSCK,max - tERR(6-10per),min = 400 ps + 272 ps = + 672 ps. Similarly, tLZ(DQ) for DDR2-667 derates to tLZ(DQ),min(derated) = -

900 ps - 293 ps = - 1193 ps and tLZ(DQ),max(derated)= 450 ps + 272 ps = + 722 ps. (Caution on the min/max usage!)

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Specific Note 41 When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per) of the

input clock. (output deratings are relative to the SDRAM input clock.)

For example, if the measured jitter into a DDR2-667 SDRAM has tJIT(per),min = - 72 ps and tJIT(per),max = + 93 ps, then

tRPRE,min(derated) = tRPRE,min + tJIT(per),min = 0.9 x tCK(avg) - 72 ps = + 2178 ps and

tRPRE,max(derated) = tRPRE,max + tJIT(per),max = 1.1 x tCK(avg) + 93 ps = + 2843 ps. (Caution on the min/max usage!)

Specific Note 42 When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(duty) of the

input clock. (output deratings are relative to the SDRAM input clock.)

For example, if the measured jitter into a DDR2-667 SDRAM has tJIT(duty),min = - 72 ps and tJIT(duty),max = + 93ps, then

tRPST,min(derated) = tRPST,min + tJIT(duty),min = 0.4 x tCK(avg) - 72 ps = + 928 ps and

tRPST,max(derated) = tRPST,max + tJIT(duty),max = 0.6 x tCK(avg) + 93 ps = + 1592 ps. (Caution on the min/max usage!)

Specific Note 43 When the device is operated with input clock jitter, this parameter needs to be derated by { -tJIT(duty),max -

tERR(6-10per),max } and { - tJIT(duty),min - tERR(6-10per),min } of the actual input clock.(output deratings are relative to the SDRAM

input clock.)

For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10per),min = - 272 ps, tERR(6-10per),max = + 293 ps,

tJIT(duty),min = - 106 ps and tJIT(duty),max = + 94 ps, then tAOF,min(derated) = tAOF,min+ { - tJIT(duty),max - tERR(6-10per),max } = -

450 ps + { - 94 ps - 293 ps} = - 837 ps and tAOF,max(derated) =tAOF,max + { - tJIT(duty),min - tERR(6-10per),min } = 1050 ps + { 106 ps +

272 ps } = + 1428 ps. (Caution on the min/max usage!)

Specific Note 44 For tAOFD of DDR2-667/800, the 1/2 clock of nCK in the 2.5 x nCK assumes a tCH(avg),average input clock HIGH

pulse width of 0.5 relative to tCK(avg). tAOF,min and tAOF,max should each be derated by the same amount as the actual amount of

tCH(avg) offset present at the DRAM input with respect to 0.5. For example, if an input clock has a worst case tCH(avg) of 0.48, the

tAOF,min should be derated by subtracting 0.02 x tCK(avg) from it, whereas if an input clock has a worst case tCH(avg) of 0.52, the

tAOF,max should be derated by adding 0.02 x tCK(avg) to it. Therefore, we have;

tAOF,min(derated) = tAC,min - [0.5 - Min(0.5, tCH(avg),min)] x tCK(avg)

tAOF,max(derated) = tAC,max + 0.6 + [Max(0.5, tCH(avg),max) - 0.5] x tCK(avg)

or

tAOF,min(derated) = Min(tAC,min, tAC,min - [0.5 - tCH(avg),min] x tCK(avg))

tAOF,max(derated) = 0.6 + Max(tAC,max, tAC,max + [tCH(avg),max - 0.5] x tCK(avg))

where tCH(avg),min and tCH(avg),max are the minimum and maximum of tCH(avg) actually measured at the DRAM input balls.

Note that these deratings are in addition to the tAOF derating per input clock jitter, i.e. tJIT(duty) and tERR(6-10per).

However tAC values used in the equations shown above are from the timing parameter table and are not derated.

Thus the final derated values for tAOF are;

tAOF,min(derated_final) = tAOF,min(derated) + { - tJIT(duty),max - tERR(6-10per),max }

tAOF,max(derated_final) = tAOF,max(derated) + { - tJIT(duty),min - tERR(6-10per),min }

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Revision History

Description

Preliminary Release.(based on NTC-DDR2-128Mb-A-R1.2, JESD208 and JESD79-F)

Official Release.

Version

1.0

Page

All

Modified

Released

07/2013

08/2013

-

1.1

All

-

Warning

DDR2-1066

CL2

P1

Add: NTC has the rights to change any specifications or product without notification.

Add DDR2-1066 IDD Specifications and release DDR2-1066.

Remove CL2 function.

1.2

1.3

1.4

1.5

1.6

11/2013

03/2014

08/2014

09/2014

10/2014

P1,3,69

P1,2,13

P3

-

Add PN: NT5TU64M16HG-ACA, NT5TU64M16HG-ACH

P4

Part Number Guide Simplify part number guide.

P1,3,4,7

P3,4

P70

-

Add P/N: NT5TU64M16HZ-AC

Add P/N: NT5TU64M16HG-ACL

IDD Specifications

DC Ratings

Add 800Mhz x16 Low IDD6 spec.

Modify TSTG storage temperature spec: -55C~150C (was: -55C~100C)

1.7

P58

01/2015

Temperature Range Format change.

P1

-

Add P/N: NT5TU128M8HE-ACH, NT5TU128M8HE-ACA

1.8

1.9

P1-4

P4-7

Operating frequency New.

11/2015

03/2016

-

Package naming: VFBGA, TFBGA (was: BGA)

NOTE align with content.

Differential input AC

logic level

P61

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NT5TU128M8HE / NT5TU64M16HG(Z)

http://www.nanya.com/

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型号：	NT5TU128M8HE-BENA
厂家：	Nanya Technology Corporation.
描述：	Commercial, Industrial and Automotive DDR2 1Gb SDRAM 动态存储器双倍数据速率
文件：	总102页 (文件大小：5024K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NT5TU128M8HE-BENA [NANYA]

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