NT6AN256T32AV-J3NA [NANYA]
Commercial Mobile LPDDR 4Gb/ 8 G b(DDP) SDRAM;
| 型号： | NT6AN256T32AV-J3NA |
| 厂家： | 
Nanya Technology Corporation. |
| 描述： | Commercial Mobile LPDDR 4Gb/ 8 G b(DDP) SDRAM 动态存储器 双倍数据速率 光电二极管 |
| 文件： | 总324页 (文件大小：11795K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NTC Proprietary
Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Commercial Mobile LPDDR4 4Gb/8Gb(DDP) SDRAM
Features
Data Integrity
Basis LPDDR4 Compliant
- Low Power Consumption
- DRAM built-in Temperature Sensor for
Temperature Compensated Self Refresh (TCSR)
- 16n Prefetch Architecture and BL16, BL32 (OTF)
- Auto Refresh and Self Refresh Modes
Power Saving Modes
Signal Integrity
- Internal VREF and VREF Training
- Configurable DS for system compatibility
- Configurable On-Die Termination
- Partial Array Self Refresh (PASR)
- Frequency Set Point(WR/OP)
- ZQ Calibration for DS/ODT impedance accuracy via
external ZQ pad (240Ω± 1%)
- Clock-stop capability
LVSTL interface and Power Supply
- VDD1/VDD2/VDDQ = 1.8V/1.1V/1.1V
- Data bus inversion (DBI)
Training for Signals’ Synchronization
- DQ Calibration offering specific DQ output patterns
Programmable
RL/WL Select (Set A / Set B)
nWR (X16 mode / X8 Byte mode)
PASR (bank/segment)
RON (Typical:40/48/60/80/120/240)
RTT (40/48/60/80/120/240)
Options
Speed Grade (DataRate)
Temperature Range (Tc)
- Commercial Grade : - 30℃ to +85℃, extending 105℃2
-4267 Mbps / RL=36
-3733 Mbps / RL=32
-3200 Mbps / RL=28
Package Information
Density and Addressing
Lead-free RoHS compliance and Halogen-free
Items
Width x Length x Height
(mm)
Ball pitch
(mm)
Items
X16_1CH
X16_2CH
(FBGA Package)
Die Quantity
Number of Banks
Bank Address
Row
Single Die
8
Dual Die
8
BA[2:0]
R[14:0]
C[9:0]
BA[2:0]
R[14:0]
C[9:0]
0.65/0.80
Mixed
200 Ball
10.00 x 15.00 x 0.83
Column
3.9μs
1.95μs
0.975μs
Tc≦85℃
tREFI 1 85℃<Tc≦95℃
95℃<Tc≦105℃
Notes:
1.
2.
tREFI values for all bank refresh is within temperature specification (<= 85°C).
AC/DC will be derated when above 85°C.
1
Version 1.2
Nanya Technology Corp.
09/2018
NTC has the rights to change any specifications or product without notification.
All Rights Reserved ©
NTC Proprietary
Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Ordering Information
Speed
Density Organization
Part Number
Package
tCK
(ns)
Data Rate
RL
(Mb/s/pin)
LPDDR4 Commercial Grade
NT6AN256M16AV-J1
0.468
0.535
0.625
0.468
0.535
0.625
LPDDR4-4267
LPDDR4-3733
LPDDR4-3200
LPDDR4-4267
LPDDR4-3733
LPDDR4-3200
36
32
28
36
32
28
4Gb
(SDP)
256M x 16
(2-CH)
NT6AN256M16AV-J2
NT6AN256M16AV-J3
NT6AN256T32AV-J1
NT6AN256T32AV-J2
NT6AN256T32AV-J3
200 Ball1
8Gb
(DDP)
256M x 32
(2-CH)
NOTE:
1.Please confirm with NTC for the available schedule.
2
Version 1.2
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Nanya Technology Corp.
All Rights Reserved ©
NTC Proprietary
Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
NANYA Part Number Guide
NT
6A
N
256T32
A
V
J1
Grade
NANYA
N/A =Commercial Grade
Technology
Speed
Product Family
6A = LPDDR4 SDRAM
LPDDR4
J1 = 0.468ns @ RL=36
J2 = 0.535ns @ RL=32
J3 = 0.625ns @ RL=28
Interface & Power (VDD1 , VDD2 , VDDQ
)
N = LVSTL (1.8V, 1.1V, 1.1V)
Organization (Depth, Width): M=Mono, T=DDP1
Package Code
4Gb = 256M16
ROHS+Halogen-Free
8Gb = 256T32
V = 200-Ball FBGA
Note: DDP－Dual Die Package
Device Version
A = 1st version
Operating Frequency
The backward compatibility of each frequency is listed in the following table. If an application operates at specific frequency
which is not defined herein but within the highest and the lowest frequencies, then the comparative loose specifications to DRAM
must be adopted from the neighboring defined frequency. Please confirm with NTC when the operating frequency is slower than
the defined frequency.
Frequency [MHz]
RL [nCK]
2133
36
1866
32
1600
28
1333
24
1200
24
1066
20
800
14
Unit
VDDQ [V]
1.1
1.1
1.1
1.1
1.1
1.1
1.1
2400
2400
2400
2400
2400
2400
NT6AN256T32AV-J1
NT6AN256M16AV-J1
NT6AN256T32AV-J2
NT6AN256M16AV-J2
NT6AN256T32AV-J3
NT6AN256M16AV-J3
4267
4267
N/A
N/A
N/A
N/A
3733
3733
3733
3733
N/A
3200
3200
3200
3200
3200
3200
2667
2667
2667
2667
2667
2667
2133
2133
2133
2133
2133
2133
1600
1600
1600
1600
1600
1600
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
N/A
Notes:
Any part number also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but
has been verified.
3
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09/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Package Block Diagram
Single Die, Single Channel Package Part Number: NT6AN256M16AV-XXX
Available: 200b
VDD1 VDD2 VDDQ Vss
VDDQ
RZQ
ZQ
CSa
CKEa
CKa
4Gb
a
Device
CAa [5:0]
ODT_CAa
(256Mb x 16)
Channel A
DMIa [1:0]
DQa [15:0]
DQSa [1:0]
a [1:0]
4
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Nanya Technology Corp.
All Rights Reserved ©
NTC Proprietary
Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Package Block Diagram
Dual Die, Dual Channel Package Part Number: NT6AN256T32AV-XXX
Available: 200b
VDD1 VDD2 VDDQ Vss
VDDQ
RZQ
ZQ
CSa
CKEa
CKa
a
CSb
CKEb
CKb
b
4Gb
4Gb
Device
Device
CAb [5:0]
ODT_CAb
CAa [5:0]
ODT_CAa
(256Mb x 16)
Channel A
(256Mb x 16)
Channel B
DMIb [1:0]
DQb [15:0]
DQSb [1:0]
b [1:0]
DMIa [1:0]
DQa [15:0]
DQSa [1:0]
a [1:0]
5
Version 1.2
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Nanya Technology Corp.
All Rights Reserved ©
NTC Proprietary
Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Ball Assignments
LPDDR4 200-ball FBGA SDP X16_1ch
Part Number: NT6AN256M16AV-XXX
A1
1
2
3
4
5
6
7
8
9
10
11
12
A
DNU
DNU
VSS
VDD2
ZQ
NC
VDD2
VSS
DNU
DNU
A
B
B
DNU
VSS
DQ0_a
VDDQ
DQ7_a
VDDQ
VSS
VDDQ
VSS
VDD2
VSS
VDD2
NC
VDDQ DQ15_a VDDQ
DQ8_a
DNU
VSS
C
D
E
DQ1_a DMI0_a DQ6_a
VSS
VDDQ
VSS
DQ14_a DMI1_a DQ9_a
C
D
E
VDDQ
VSS
VSS
DQ2_a
DQS0_a
VSS
DQ5_a
DQ4_a
VDD1
CS_a
VSS
DQS1_a
VSS
VDDQ
VSS
DQ13_a
DQ10_a
0_a
VDDQ
VSS
1_a
F
VDD1
VSS
DQ3_a
VDD2 DQ12_a VDDQ DQ11_a
VDD1
VSS
F
ODT_CA_a
G
H
J
VSS
VDD2
CK_a
NC
VDD1
VSS
CA3_a
VSS
NC
G
H
J
VDD2
VSS
CA0_a
CA1_a
VSS
NC
CA2_a
CA4_a
CA5_a
VSS
VDD2
VSS
VSS
CKE_a
VSS
_a
K
VDD2
VDD2
NC
VSS
VDD2
VDD2
K
L
L
M
N
P
M
N
P
VDD2
VSS
VSS
NC
VDD2
VSS
NC
VSS
NC
NC
NC
NC
NC
VSS
NC
VDD2
VSS
NC
VSS
NC
VDD2
VSS
R
T
VDD2
VSS
NC
NC
VDD2
VSS
VDD2
VSS
NC
NC
VDD2
VSS
R
T
NC
VSS
VDDQ
NC
VDD1
NC
VDD1
NC
VSS
VDDQ
NC
NC
U
V
VDD1
VSS
NC
VDD2
VSS
VDD2
VSS
VDD1
VSS
U
V
NC
NC
NC
NC
W
Y
VDDQ
VSS
VSS
NC
NC
VSS
NC
VDDQ
VSS
VDDQ
VSS
VSS
NC
NC
VSS
NC
VDDQ
VSS
W
Y
NC
NC
AA
AB
DNU
NC
VDDQ
NC
VDDQ
VDDQ
NC
VDDQ
NC
DNU
AA
AB
DNU
1
DNU
2
VSS
3
VDD2
4
VSS
5
VSS
8
VDD2
9
VSS
10
DNU
11
DNU
12
6
7
Notes:
1. 0.8mm pitch (X-axis), 0.65mm pitch (Y-axis), 22 rows.
2. Top View, A1 in top left corner.
3. Die pad VSS and VSSQ signals are combined to VSS package balls.
6
Version 1.2
Nanya Technology Corp.
09/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Ball Assignments
LPDDR4 200-ball FBGA DDP X16_2ch
Part Number: NT6AN256T32AV-XXX
A1
1
2
3
4
5
6
7
8
9
10
11
12
A
DNU
DNU
VSS
VDD2
ZQ
NC
VDD2
VSS
DNU
DNU
A
B
B
DNU
VSS
DQ0_a
VDDQ
DQ7_a
VDDQ
VSS
VDDQ
VSS
VDD2
VSS
VDD2
NC
VDDQ DQ15_a VDDQ
DQ8_a
DNU
VSS
C
D
E
DQ1_a DMI0_a DQ6_a
VSS
VDDQ
VSS
DQ14_a DMI1_a DQ9_a
C
D
E
VDDQ
VSS
VSS
DQ2_a
DQS0_a
VSS
DQ5_a
DQ4_a
VDD1
CS_a
VSS
DQS1_a
VSS
VDDQ
VSS
DQ13_a
DQ10_a
0_a
VDDQ
VSS
1_a
F
VDD1
VSS
DQ3_a
VDD2 DQ12_a VDDQ DQ11_a
VDD1
VSS
F
ODT_CA_a
G
H
J
VSS
VDD2
CK_a
NC
VDD1
VSS
CA3_a
VSS
NC
G
H
J
VDD2
VSS
CA0_a
CA1_a
VSS
NC
CA2_a
CA4_a
CA5_a
VSS
VDD2
VSS
VSS
CKE_a
VSS
_a
K
VDD2
VDD2
NC
VSS
VDD2
VDD2
K
L
L
M
N
P
M
N
P
VDD2
VSS
VSS
CA1_b
VDD2
VSS
NC
VSS
CKE_b
CS_b
NC
NC
NC
VSS
VDD2
VSS
VSS
VDD2
VSS
CK_b
VDD2
VSS
CA5_b
CA4_b
_b
CA2_b
VDD1
R
T
VDD2
VSS
CA0_b
VDD2
VSS
CA3_b
VSS
VDD2
VSS
R
T
ODT_CA_b
VSS
VDDQ
VDD1
DQ4_b
DQ5_b
VSS
U
V
VDD1
VSS
DQ3_b
DQ2_b
VSS
VDD2
VSS
VDD2 DQ12_b VDDQ DQ11_b
VDD1
VSS
U
V
VSS
VDDQ
VSS
DQ13_b
VSS
DQ10_b
VSS
0_b
1_b
W
Y
VDDQ
VSS
DQS0_b
VDDQ
VSS
DQS1_b
VDDQ
VSS
W
Y
DQ1_b DMI0_b DQ6_b
DQ14_b DMI1_b DQ9_b
AA
AB
DNU
DQ0_b
VDDQ
DQ7_b
VDDQ
VDDQ DQ15_b VDDQ
DQ8_b
DNU
AA
AB
DNU
1
DNU
2
VSS
3
VDD2
4
VSS
5
VSS
8
VDD2
9
VSS
10
DNU
11
DNU
12
6
7
Notes:
1. 0.8mm pitch (X-axis), 0.65mm pitch (Y-axis), 22 rows.
2. Top View, A1 in top left corner.
3. Die pad VSS and VSSQ signals are combined to VSS package balls.
7
Version 1.2
Nanya Technology Corp.
09/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Package Outline Drawing
Part Number: NT6AN256M16AV-XXX, NT6AN256T32AV-XXX
Unit: mm
* BSC (Basic Spacing between Center)
8
Version 1.2
Nanya Technology Corp.
09/2018
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NTC Proprietary
Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Ball Descriptions
Symbol
Type
Function
Clock: CK and are differential clock inputs. All address, command, and control input signals are
sampled on the crossing of the positive edge of CK and the negative edge of . AC timings for CA
parameters are referenced to CK. Each channel (A & B) has its own clock pair.
CK_A , _
CK_B , _
Input
Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock circuits, input buffers,
and output drivers. Power-saving modes are entered and exited via CKE transitions.
CKE is part of the command code. Each channel (A & B) has its own CKE signal.
CKE_A , CKE_B
Input
CS_A , CS_B
CA[5:0]_A
Input
Input
Chip Select: CS is part of the command code. Each channel (A & B) has its own CS signal.
Command/Address Inputs: CA signals provide the Command and Address inputs according
to the Command Truth Table. Each channel (A&B) has its own CA signals.
CA[5:0]_B
Data Mask Inversion: DMI is a bi-directional signal which is driven HIGH when the data on the data bus
is inverted, or driven LOW when the data is in its normal state. Data Inversion can be disabled via a
mode register setting. Each byte of data has a DMI signal. Each channel (A & B) has its own DMI signals.
This signal is also used along with the DQ signals to provide write data masking information to the
DRAM. The DMI pin function - Data Inversion or Data mask - depends on Mode Register setting.
DMI[1:0]_A
DMI[1:0]_B
Input/output
Input/output
DQ[15:0]_A
DQ[15:0]_B
Data Bus: Bi-direction data bus.
DQS[1:0]_A
10_
DQS[1:0]_B ,
10_
Data Strobe: DQS and are bi-directional differential output clock signals used to strobe data during
a READ or WRITE. The Data Strobe is generated by the DRAM for a READ and is edge-aligned with
Data. The Data Strobe is generated by the Memory Controller for a WRITE and must arrive prior to Data.
Each byte of data has a Data Strobe signal pair. Each channel (A & B) has its own DQS strobes.
Input/output
ODT_CA_A
ODT_CA_B
CA ODT Control: The ODT_CA pin is used in conjunction with the Mode
Input
Register to turn on/off the On-Die-Termination for CA pins.
Calibration Reference. Used to calibrate the output drive strength and the termination resistance. There
ZQ
Reference
is one ZQ pin per die. The ZQ pin shall be connected to VDDQ through a 240Ω ± 1% resistor.
Supply
Supply
Supply
GND
VDD1
VDD2
VDDQ
Power Supply 1: Core power supply
Power Supply 2: Core power supply
DQ Power Supply: Isolated on the die for improved noise immunity.
Ground
VSS, VSSQ
Input
Reset: When asserted LOW, the signal resets both channels of the die.
9
Version 1.2
09/2018
Nanya Technology Corp.
All Rights Reserved ©
NTC Proprietary
Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Simplified State Diagram
Power
On
MPC
Based
MRW
MRW
MRR
Training
SR
=L
MPC
MRR
MPC
Based
Power
Down
Training
CKE=L
CKE=H
Reset
MRW
Per
Bank
MPC
Command
Bus
MRW
MRW
REF
MRW
Refresh
=H
Training
MRW
MRW
MPC
Based
REF
All
SRE
SRX
MPC
Based
MPC
MRR
Self
Idle
Bank
Refresh
MPC
Training
Refresh
Training
CKE=H
CKE=L
Idle
MRW
Power
Down
MRR
MRW
Command
MRW
ACT
MRR
Bus
MRR
MRR
Training
MRW
MRR
Activing
Active
Power
Down
MRW
MRW
CKE=L
MRW
MRR
CKE=H
MRR
MRW
MPC
Bank
Based
REF
Active
Training
MPC
Based
Per
Bank
WR or
MWR
MPC
MRR
Training
RD
Refresh
Write
or
WR or
MWR
RD
Read
WRA or
MWRA
RDA
MPR
MRR
WRA or
MWRA
PRE or
PREA
RDA
Write or
MPR
PRE or
PREA
PRE or
PREA
Read
With Auto-
Precharge
With Auto-
Precharge
Command Sequence
Automatic Sequence
Precharging
Abbr.
Function
Abbr.
Function
PRE(A)
ACT
Precharge (All)
Activate
Write (w/ Autoprecharge)
Mask-Write (w/ Autoprecharge)
Read (w/ Autoprecharge)
Mode Register Write
CKE=L
CKE=H
SRE
SRX
REF
Enter Power Down
Exit Power Down
Enter Self Refresh
Exit Self Refresh
Refresh
WR(A)
MWR(A)
RD(A)
MRW
MRR
MPC
Multi-Purpose Command (w/ NOP)
Mode Register Read
10
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All Rights Reserved ©
NTC Proprietary
Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Simplified State Diagram
A) FIFO Based Write / Read Timing
MPC
MPC
MPC
MPC
Write
FIFO
Read
FIFO
MPC
Based
MPC
MWR
MPC
Training
MRW
MRW
B) Read DQ Calibration
MPC
MPC
DQ
Calibration
C) ZQ CAL Start
DQ
MPC
Calibration
Start
D) ZQ CAL Latch
DQ
Calibration
Latch
MPC
1. From the Self-Refresh state the device can enter Power-Down, MRR, MRW, or MPC states. See the section on Self-Refresh for more
information.
2. In IDLE state, all banks are pre-charged.
3. In the case of a MRW command to enter a training mode, the state machine will not automatically return to the IDLE state at the
conclusion of training.
See the applicable training section for more information.
4. In the case of a MPC command to enter a training mode, the state machine may not automatically return to the IDLE state at the
conclusion of training.
See the applicable training section for more information.
5. This simplified State Diagram is intended to provide an overview of the possible state transitions and the commands to control
them. In particular, situations involving more than one bank, the enabling or disabling of on-die termination, and some other
events are not captured in full detail.
6. States that have an “automatic return” and can be accessed from more than one prior state (Ex. MRW from either Idle or Active
states) will return to the state from when they were initiated (Ex. MRW from Idle will return to Idle).
7. The pin can be asserted from any state, and will cause the SDRAM to go to the Reset State. The diagram shows RESET
applied from the Power-On as an example, but the Diagram should not be construed as a restriction on .
11
Version 1.2
Nanya Technology Corp.
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NTC Proprietary
Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Power-up, Initialization and Power-off Procedure
For power-up and reset initialization, in order to prevent DRAM from functioning improperly, default values of the
following MR settings are defined.
MRS defaults settings
Item
FSP-OP/WR
WLS
MRS
Default Setting
00
Description
FSP-OP/WR[0] are enabled
Write Latency Set 0 is selected
WL = 4
MR13 OP[7:6]
MR2 OP[6]
B
0
B
WL
MR2 OP[5:3]
MR2 OP[2:0]
MR1 OP[6:4]
MR3 OP[7:6]
MR11 OP[6:4]
MR11 OP[2:0]
MR12 OP[6]
MR12 OP[5:0]
MR14 OP[6]
MR14 OP[5:0]
000
000
000
B
B
B
RL
RL = 6, nRTP=8
nWR
nWR = 6
DBI-WR/RD
CA ODT
DQ ODT
Write & Read DBI are disabled
CA ODT is disabled
DQ ODT is disabled
00
B
000
000
B
B
V
(CA) Setting
1
B
V
REF
(CA) Range[1] enabled
REF
V
(CA) Value
001101
Range1 : 27.2% of V
DD2
REF
B
B
V
(DQ) Setting
1
B
V
REF
(DQ) Range[1] enabled
REF
V
(DQ) Value
001101
Range1 : 27.2% of V
DDQ
REF
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Voltage Ramp and Device Initialization
The following sequence shall be used to power up the device. Unless specified otherwise, these steps are
mandatory. Note that the power-up sequence of all channels must proceed simultaneously.
Power Ramp and Initialization Sequence
Notes:
1. Training is optional and may be done at the system architects discretion. The training sequence after ZQ_CAL Latch
(Th, Sequence7~9) in Initialization Sequence is simplified recommendation and actual training sequence may vary depending on
systems.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
1) While applying power (after Ta), is recommended to be LOW (0.2 x VDD2) and all other inputs must be
between VILmin and VIHmax. The device outputs remain at High-Z while is held LOW.
Power supply voltage ramp requirements are provided. VDD1 must ramp at the same time or earlier than VDD2
.
VDD2 must ramp at the same time or earlier than VDDQ.
Voltage Ramp Conditions
After
Applicable Conditions
V
must be greater than V
DD1
DD2
Ta is reached
V
must be greater than V
- 200mV
DDQ
DD2
Notes:
1. Ta is the point when any power supply first reaches 300mV.
2. Voltage ramp conditions apply between Ta and power-off (controlled or uncontrolled).
3. Tb is the point at which all supply and reference voltages are within their defined ranges.
4. Power ramp duration tINIT0 (Tb-Ta) must not exceed 20ms.
5. The voltage difference between any of VSS and VSSQ pins must not excess 100mV.
2) Following the completion of the voltage ramp (Tb), must be maintained LOW. DQ, DMI, DQS and
voltage levels must be between VSSQ and VDDQ during voltage ramp to avoid latch-up. CKE, CK, , and
CA input levels must be between VSS and VDD2 during voltage ramp to avoid latch-up.
3) Beginning at Tb, must remain LOW for at least tINIT1 (Tc), after which can be de-asserted to
HIGH(Tc). At least 10ns before de-assertion, CKE is required to be set LOW. All other input signals are
"Don't Care".
4) After is de-asserted (Tc), wait at least tINIT3 before activating CKE. Clock (CK, ) is required to be
started and stabilized for tINIT4 before CKE goes active(Td). CS is required to be maintained LOW when
controller activates CKE.
5) After setting CKE high, wait minimum of tINIT5 to issue any MRR or MRW commands (Te). For both MRR and
MRW commands, the clock frequency must be within the range defined for tCKb. Some AC parameters (for
example, tDQSCK) could have relaxed timings (such as tDQSCKb) before the system is appropriately
configured.
6) After completing all MRW commands to set the Pull-up, Pull-down and Rx termination values, the DRAM
controller can issue ZQCAL Start command to the memory (Tf). This command is used to calibrate VOH level
and output impedance over process, voltage and temperature. In systems where more than one LPDDR4
DRAM devices share one external ZQ resistor, the controller must not overlap the ZQ calibration sequence of
each LPDDR4 device. ZQ calibration sequence is completed after tZQCAL (Tg) and the ZQCAL Latch
command must be issued to update the DQ drivers and DQ+CA ODT to the calibrated values.
7) After tZQLAT is satisfied (Th) the command bus (internal V
(CA), CS, and CA) should be trained for
REF
high-speed operation by issuing an MRW command (Command Bus Training Mode). This command is used to
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
calibrate the device's internal VREF and align CS/CA with CK for high-speed operation. The LPDDR4 device will
power-up with receivers configured for low-speed operations, and VREF(CA) set to a default factory setting.
Normal device operation at clock speeds higher than tCKb may not be possible until command bus training has
been completed.
NOTE: The command bus training MRW command uses the CA bus as inputs for the calibration data stream, and outputs the results
asynchronously on the DQ bus. See Command Bus Training, MRW for information on how to enter/exit the training mode.
8) After command bus training, DRAM controller must perform write leveling. Write leveling mode is enabled when
MR2 OP[7] is high (Ti). See Mode Register Write-WR Leveling Mode, for detailed description of write leveling
entry and exit sequence. In write leveling mode, the DRAM controller adjusts write DQS/ timing to the point
where the LPDDR4 device recognizes the start of write DQ data burst with desired write latency.
9) After write leveling, the DQ Bus (internal VREF(DQ), DQS, and DQ) should be trained for high-speed operation
using the MPC training commands and by issuing MRW commands to adjust VREF(DQ)(Tj). The LPDDR4
device will power-up with receivers configured for low-speed operations and VREF(DQ) set to a default factory
setting. Normal device operation at clock speeds higher than tCKb should not be attempted until DQ Bus
training has been completed. The MPC Read Calibration command is used together with MPC FIFO
Write/Read commands to train DQ bus without disturbing the memory array contents. See DQ Bus Training
section for detailed DQ Bus Training sequence.
10) At Tk the LPDDR4 device is ready for normal operation, and is ready to accept any valid command. Any more
registers that have not previously been set up for normal operation should be written at this time.
Initialization Timing Parameters
Value
Parameter
Unit
Comment
Min
Max
tINIT0
tINIT1
tINIT2
tINIT3
tINIT4
tINIT5
tZQCAL
tZQLAT
tCKb
-
20
-
ms Maximum voltage-ramp time
200
us Minimum LOW time after completion of voltage ramp
ns Minimum CKE low time before high
ms Minimum CKE low time after high
tCK Minimum stable clock before first CKE high
us Minimum idle time before first MRW/MRR command
us ZQ calibration time
10
-
2
-
5
-
2
-
1
-
Max(30ns, 8tCK)
-
ns ZQCAL latch quiet time.
*1,2
*1,2
ns Clock cycle time during boot
Note
Note
Notes:
1. Min tCKb guaranteed by DRAM test is 18ns.
2. The system may boot at a higher frequency than dictated by min tCKb. The higher boot frequency is system dependent.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Reset Initialization with Stable Power
The following sequence is required for RESET at no power interruption initialization.
1. Assert below 0.2 x VDD2 anytime when reset is needed. needs to be maintained for minimum
tPW_RESET. CKE must be pulled LOW at least 10 ns before de-asserting .
2. Repeat steps 4 to 10 in "Voltage Ramp and Device Initialization" section.
Reset Timing Parameter
Value
Parameter
Unit
Comment
Min
Max
tPW_RESET
100
-
ns Minimum low Time for Reset Initialization with stable power
Power-off Sequence
The following procedure is required to power off the device.
While powering off, CKE must be held LOW (0.2 X VDD2) and all other inputs must be between VILmin and
VIHmax. The device outputs remain at High-Z while CKE is held LOW. DQ, DMI, DQS and voltage levels
must be between VSSQ and VDDQ during voltage ramp to avoid latch-up. , CK, , CS and CA input levels
must be between VSS and VDD2 during voltage ramp to avoid latch-up.
Tx is the point where any power supply drops below the minimum value specified.
Tz is the point where all power supplies are below 300mV. After TZ, the device is powered off.
Power Supply Conditions
After
Applicable Conditions
V
must be greater than V
DD1
DD2
Tx and Tz
V
must be greater than V
- 200mV
DDQ
DD2
The voltage difference between any of VSS, VSSQ pins must not exceed 100mV.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Uncontrolled Power-Off Sequence
When an uncontrolled power-off occurs, the following conditions must be met:
At Tx, when the power supply drops below the minimum values specified, all power supplies must be turned off
and all power supply current capacity must be at zero, except any static charge remaining in the system.
After Tz (the point at which all power supplies first reach 300mV), the device must power off. During this period the
relative voltage between power supplies is uncontrolled. VDD1 and VDD2 must decrease with a slope lower than
0.5V/μs between Tx and Tz.
An uncontrolled power-off sequence can occur a maximum of 400 times over the life of the device.
Timing Parameters Power Off
Value
Symbol
Unit
Comment
Min
Max
tPOFF
-
2
s
Maximum Power-off ramp item
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Mode Register Definition
Mode Register Assignment and Definition in LPDDR4 SDRAM
Each register is denoted as "R" if it can be read but not written, "W" if it can be written but not read, and "R/W" if it
can be read and written. A Mode Register Read command is used to read a mode register. A Mode Register Write
command is used to write a mode register.
MR#
0
OP[7]
CATR
OP[6]
OP[5]
RFU
OP[4]
OP[3]
OP[2]
RFU
OP[1]
OP[0]
RFU
RZQI
Latency mode Refresh Mode
1
RPST
nWR (for AP)
RD-PRE
WR-PRE
BL
RL
2
WR Lev
DBI-WR
TUF
WLS
WL
3
DBI-RD
PDDS
PPRE
PPRP
WR PST
PU-CAL
4
Thermal Offset
SR Abort
Refresh Rate
5
LPDDR4 Manufacturer ID
Revision ID-1
6
7
Revision ID-2
8
IO Width
Density
Type
9
Vendor Specific Test Register
10
11
12
13
14
15
16
17
18
19
20
21
RFU
ZQ-Reset
CBT
RFU
CBT Mode
FSP-OP
RFU
CA ODT
DMD
RFU
DQ ODT
RPT
VR-CA
FSP-WR
VR(dq)
V
(CA)
REF
RRO
VRCG
VRO
(DQ)
V
REF
Lower-Byte Invert Register for DQ Calibration
PASR Bank Mask
PASR Segment Mask
DQS Oscillator Count - LSB
DQS Oscillator Count - MSB
Upper-Byte Invert Register for DQ Calibration
RFU
22 ODTD for x8 2ch(Byte) mode ODTD-CA
ODTE-CS
DQS interval timer run time setting
TRR Mode BAn
ODTE-CK
SOC ODT
23
24
TRR Mode
Unlimited MAC
MAC Value
25
PPR Resource
26~29
30
RFU
Reserved for testing – SDRAM will ignore
RFU
31 Byte mode Vref Selection
32
DQ Calibration Pattern “A” (default = 5AH)
RFU
33~38
39
40
Reserved for testing – SDRAM will ignore
DQ Calibration Pattern “B” (default = 3CH)
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
MR0 Register Information (MA[5:0] = 00H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
CATR
RFU
RFU
RZQI
RFU
Latency modeRefresh mode
Register
Type
Function
Operand
OP[0]
Data
0 : Both legacy & modified refresh mode supported
Notes
B
Refresh mode
Latency mode
1 : Only modified refresh mode supported
B
0 : Device supports normal latency
B
OP[1]
6
1,2,3,4
5
1 : Device supports byte mode latency
B
00 : RZQ Self-Test Not Supported
B
Read-only
01 : ZQ pin may connect to VSSQ or float
B
RZQI
10 : ZQ-pin may short to VDDQ
B
OP[4:3]
OP[7]
(Built-in Self-Test for RZQ)
11 : ZQ-pin Self-Test Completed, no error
B
condition detected (ZQ-pin may not connect
to VSSQ or float, nor short to VDDQ)
CATR
(CA Terminating Rank)
Notes:
0 : CA for this rank is not terminated
B
1 : Vendor specific
B
1. RZQI MR value, if supported, will be valid after the following sequence:
a. Completion of MPC ZQCAL Start command to either channel.
b. Completion of MPC ZQCAL Latch command to either channel then tZQLAT is satisfied.
RZQI value will be lost after Reset.
2. If the ZQ-pin is connected to VSSQ to set default calibration, OP[4:3] shall be set to 01B. If the ZQ-pin is not connected
to VSSQ, either OP[4:3] = 01B or OP[4:3] = 10B might indicate a ZQ-pin assembly error. It is recommended that the assembly error is
corrected.
3. In the case of possible assembly error, the LPDDR4-SDRAM device will default to factory trim settings for RON, and will ignore ZQ
Calibration commands. In either case, the device may not function as intended.
4. If ZQ Self-Test returns OP[4:3] = 11B, the device has detected a resistor connected to the ZQ-pin. However, this result cannot be used
to validate the ZQ resistor value or that the ZQ resistor tolerance meets the specified limits (i.e. 240Ω ± 1%).
5. CATR functionality is Vendor specific. CATR can either indicate the connection status of the ODTCA pad for the die or whether CA for
the rank is terminated. Consult the vendor device datasheet for details.
6. Byte mode latency for x16 device is only allowed when it is stacked in a same package with byte mode device.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
MR1 Register Information (MA[5:0] = 01H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
RPST
nWR (for AP)
RD-PRE
WR-PRE
BL
Register
Type
Function
Operand
Data
00 : BL=16 Sequential (default)
Notes
B
BL
01 : BL=32 Sequential
B
OP[1:0]
1,7
(Burst Length)
10 : BL=16 or 32 Sequential (on-the-fly)
B
All Others: Reserved
WR-PRE
(WR Pre-amble Length)
RD-PRE
0 : Reserved
B
OP[2]
OP[3]
5,6
1 : WR Pre-amble = 2*tCK
B
0 : RD Pre-amble = Static (default)
B
3,5,6
(RD Pre-amble Type)
1 : RD Pre-amble = Toggle
B
For x16 mode
000 : nWR = 6 (default)
B
001 : nWR = 10
B
010 : nWR = 16
B
011 : nWR = 20
B
100 : nWR = 24
B
Write-only
101 : nWR = 30
B
110 : nWR = 34
B
nWR
111 : nWR = 40
B
(Write-Recovery for Auto-
Pre-charge commands)
OP[6:4]
2,5,6
For Byte (x8) mode
000 : nWR = 6 (default)
B
001 : nWR = 12
B
010 : nWR = 16
B
011 : nWR = 22
B
100 : nWR = 28
B
101 : nWR = 32
B
110 : nWR = 38
B
111 : nWR = 44
B
RPST
0 : RD Post-amble = 0.5*tCK (default)
B
OP[7]
4,5,6
(RD Post-Amble Length)
1 : RD Post-amble = 1.5*tCK
B
Notes:
1. Burst length on-the-fly can be set to either BL=16 or BL=32 by setting the “BL” bit in the command operands. See the Command Truth
Table.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
2. The programmed value of nWR is the number of clock cycles the LPDDR4-SDRAM device uses to determine the starting point of an
internal Pre-charge operation after a Write burst with AP (auto-precharge) enabled.
(See section “Read and Write Latencies.)
3. For Read operations this bit must be set to select between a "toggling" pre-amble and a "Non-toggling"
Pre-amble.
(See Read Preamble and Postamble, for a drawing of each type of pre-amble.)
4. OP[7] provides an optional READ post-amble with an additional rising and falling edge of DQS. The optional postamble cycle is
provided for the benefit of certain memory controllers.
5. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1.
Only the registers for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be read from
with an MRR command to this MR address.
6. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1.
The device will operate only according to the values stored in the registers for the active set point, i.e., the set
point determined by the state of the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set
point will be ignored by the device, and may be changed without affecting device operation.
7. Supporting the two physical registers for Burst Length: MR1 OP[1:0] as optional feature. Applications requiring
support of both vendor options shall assure that both FSP-OP[0] and FSP-OP[1] are set to the same code. Refer
to vendor datasheets for detail.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Burst Sequence for READ
Burst Burst
Burst Cycle Number and Burst Address Sequence
C4 C3 C2 C1 C0
Length Type
1
0
4
8
C
0
4
8
C
2
1
5
9
D
1
5
9
D
3
2
6
A
E
2
6
A
E
4
3
7
B
F
5
4
8
C
0
4
8
C
0
6
5
9
D
1
5
9
D
1
7
6
A
E
2
6
A
E
2
8
7
B
F
9
8
C
0
4
8
C
0
4
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31 32
V
V
V
V
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
9
D
1
5
9
D
1
5
A
E
2
6
A
E
2
6
B
F
C
0
4
8
C
0
4
8
D
1
5
9
D
1
5
9
E
2
6
A
E
2
6
A
F
3
7
B
F
16
SEQ
3
7
B
F
3
7
B
F
3
7
B
F
10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 10 11 12 13
18 19 1A 1B 1C 1D 1E 1F 10 11 12 13 14 15 16 17
1C 1D 1E 1F 10 11 12 13 14 15 16 17 18 19 1A 1B
3
7
B
3
7
3
32
SEQ
10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 10 11 12 13
18 19 1A 1B 1C 1D 1E 1F 10 11 12 13 14 15 16 17
1C 1D 1E 1F 10 11 12 13 14 15 16 17 18 19 1A 1B
0
4
8
C
1
5
9
D
2
6
A
E
3
7
B
F
4
8
C
0
5
9
D
1
6
A
E
2
7
B
F
8
C
0
4
9
D
1
5
A
E
2
6
B
F
C
0
4
8
D
1
5
9
E
2
6
A
F
3
7
B
3
7
3
Notes:
1. C0-C1 are assumed to be '0', and are not transmitted on the command bus.
2. The starting burst address is on 64-bit (4n) boundaries.
Burst Sequence for Write
Burst Burst
Burst Cycle Number and Burst Address Sequence
C4 C3 C2 C1 C0
Length Type
1
0
0
2
1
1
3
2
2
4
3
3
5
4
4
6
5
5
7
6
6
8
7
7
9
8
8
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
16
32
SEQ
SEQ
V
0
0
0
0
0
0
0
0
0
9
9
A
A
B
B
C
C
D
D
E
E
F
F
10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
Notes:
1. C0-C1 are assumed to be '0', and are not transmitted on the command bus.
2. The starting address is on 256-bit(16n) boundaries for Burst length 16.
3. The starting address is on 512-bit(32n) boundaries for Burst length 32.
4. C2-C3 shall be set to '0' for all Write operations.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
MR2 Register Information (MA[5:0] = 02H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
WR Lev
WLS
WL
RL
Register
Type
Function
Operand
Data
Notes
For x16 mode
RL & nRTP for DBI-RD Disabled (MR3 OP[6]=0 )
B
000 : RL=6, nRTP = 8 (Default)
B
001 : RL=10, nRTP = 8
B
010 : RL=14, nRTP = 8
B
011 : RL=20, nRTP = 8
B
100 : RL=24, nRTP = 10
B
101 : RL=28, nRTP = 12
B
110 : RL=32, nRTP = 14
B
111 : RL=36, nRTP = 16
B
RL & nRTP for DBI-RD Enabled (MR3 OP[6]=1 )
B
000 : RL=6, nRTP = 8
B
001 : RL=12, nRTP = 8
B
010 : RL=16, nRTP = 8
B
011 : RL=22, nRTP = 8
B
100 : RL=28, nRTP = 10
B
101 : RL=32, nRTP = 12
B
110 : RL=36, nRTP = 14
B
RL
(Read latency)
111 : RL=40, nRTP = 16
B
Write-only
OP[2:0]
1,3,4
For Byte (x8) mode
RL & nRTP for DBI-RD Disabled (MR3 OP[6]=0 )
B
000 : RL=6, nRTP = 8 (Default)
B
001 : RL=10, nRTP = 8
B
010 : RL=16, nRTP = 8
B
011 : RL=22, nRTP = 8
B
100 : RL=26, nRTP = 10
B
101 : RL=32, nRTP = 12
B
110 : RL=36, nRTP = 14
B
111 : RL=40, nRTP = 16
B
RL & nRTP for DBI-RD Enabled (MR3 OP[6]=1 )
B
000 : RL=6, nRTP = 8
B
001 : RL=12, nRTP = 8
B
010 : RL=18, nRTP = 8
B
011 : RL=24, nRTP = 8
B
100 : RL=30, nRTP = 10
B
101 : RL=36, nRTP = 12
B
110 : RL=40, nRTP = 14
B
111 : RL=44, nRTP = 16
B
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Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Register
Type
Function
Operand
Data
Notes
For x16 mode
For Byte (x8) mode
WL Set "A”
WL Set "A”
(MR2 OP[6]=0 )
(MR2 OP[6]=0 )
B
B
000 : WL=4 (Default)
000 : WL=4 (Default)
B
B
001 : WL=6
001 : WL=6
B
B
010 : WL=8
010 : WL=8
B
B
011 : WL=10
011 : WL=10
B
B
100 : WL=12
100 : WL=12
B
B
101 : WL=14
101 : WL=14
B
B
110 : WL=16
110 : WL=16
B
B
WL
OP[5:3]
1,3,4
111 : WL=18
111 : WL=18
B
B
(Write latency)
WL Set "B"
WL Set "B"
(MR2 OP[6]=1 )
(MR2 OP[6]=1 )
B
B
000 : WL=4
000 : WL=4
B
B
001 : WL=8
001 : WL=8
B
B
010 : WL=12
010 : WL=12
B
B
011 : WL=18
011 : WL=18
B
B
100 : WL=22
100 : WL=22
B
B
101 : WL=26
101 : WL=26
B
B
110 : WL=30
110 : WL=30
B
B
111 : WL=34
111 : WL=34
B
B
WLS
0 : WL Set "A" (default)
B
OP[6]
OP[7]
1,3,4
2
(Write Latency Set)
WR LEV
1 : WL Set "B"
B
0 : Disabled (default)
B
(Write Leveling)
1 : Enabled
B
Notes:
1. See “Read and Write Latencies” for detail.
2. After a MRW to set the Write Leveling Enable bit (OP[7]=1B), the LPDDR4-SDRAM device remains in the MRW state until another MRW
command clears the bit (OP[7]=0B). No other commands are allowed until the Write Leveling Enable bit is cleared.
3. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. Only the registers
for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR
address, or read from with an MRR command to this address.
4. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. The device will
operate only according to the values stored in the registers for the active set point, i.e., the set point determined by the state of the
FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed
without affecting device operation.
24
Version 1.2
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NTC Proprietary
Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
MR3 Register Information (MA[5:0] = 03H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
DBI-WR
DBI-RD
PDDS
PPRP
WR PST
PU-CAL
Register
Type
Function
Operand
OP[0]
Data
Notes
1,4
PU-Cal
(Pull-up Calibration Point)
WR PST
0 : VDDQ/2.5
B
1 : VDDQ/3 (default)
B
0 : WR Post-amble = 0.5*tCK (default)
B
OP[1]
2,3,5
6
(WR Post-Amble Length)
Post Package Repair
Protection
1 : WR Post-amble = 1.5*tCK (Vendor specific function)
B
0 : PPR protection disabled (default)
B
OP[2]
1 : PPR protection enabled
B
000 : RFU
B
001 : RZQ/1
B
010 : RZQ/2
B
Write-only
PDDS
011 : RZQ/3
B
OP[5:3]
1,2,3
100 : RZQ/4
B
(Pull-Down Drive Strength)
101 : RZQ/5
B
110 : RZQ/6 (default)
B
111 : Reserved
B
DBI-RD
(DBI-Read Enable)
DBI-WR
0 : Disabled (default)
B
OP[6]
OP[7]
2,3
2,3
1 : Enabled
B
0 : Disabled (default)
B
(DBI-Write Enable)
Notes:
1B: Enabled
1. All values are "typical". The actual value after calibration will be within the specified tolerance for a given voltage
and temperature. Re-calibration may be required as voltage and temperature vary.
2. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1.
Only the registers for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to
with an MRW command to this MR address, or read from with an MRR command to this address.
3. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1.
The device will operate only according to the values stored in the registers for the active set point, i.e., the set point determined by
the state of the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may
be changed without affecting device operation.
4. For dual channel devices, PU-CAL setting is required as the same value for both Ch.A and Ch.B before issuing ZQ Cal start command.
5. Refer to the supplier data sheet for vender specific function. 1.5*tCK apply > 1.6GHz clock.
6. If MR3 OP[2] is set to 1b then PPR protection mode is enabled. The PPR Protection bit is a sticky bit and can only be set to 0b by a
power on reset.
MR4 OP[4] controls entry to PPR Mode. If PPR protection is enabled then DRAM will not allow writing of 1 to MR4 OP[4].
25
Version 1.2
Nanya Technology Corp.
09/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
MR4 Register Information (MA[5:0] = 04H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
TUF
Thermal Offset
PPRE
SR Abort
Refresh Rate
Register
Type
Function
Operand
Data
000 : SDRAM Low temperature operating limit exceeded
Notes
B
001 : 4x refresh
B
010 : 2x refresh
B
1,2,3,4,
7,8,9
011 : 1x refresh (default)
B
Refresh Rate
Read
OP[2:0]
100 : 0.5x refresh
B
101 : 0.25x refresh, no de-rating
B
110 : 0.25x refresh, with de-rating
B
111 : SDRAM High temperature operating limit exceeded
B
SR Abort
(Self Refresh Abort)
PPRE
0 : Disable (default)
B
Write
Write
OP[3]
OP[4]
9,11
5,9
1 : Enable
B
0 : Exit PPR mode (default)
B
(Post-package repair entry/exit)
1 : Enter PPR mode
B
00 : No offset, 0~5°C gradient (default)
B
Thermal Offset
01 : 5°C offset, 5~10°C gradient
B
Write
Read
OP[6:5]
OP[7]
10
(Vender Specific Function)
10 : 10°C offset, 10~15°C gradient
B
11 : Reserved
B
TUF
(Temperature Update Flag)
Notes:
0 : No change in OP[2:0] since last MR4 read (default)
B
6,7,8
1 : Change in OP[2:0] since last MR4 read
B
1. The refresh rate for each MR4-OP[2:0] setting applies to tREFI, tREFIpb, and tREFW. OP[2:0]=011B corresponds to a device
temperature of 85°C. Other values require either a longer (2x, 4x) refresh interval at lower temperatures, or a shorter (0.5x, 0.25x)
refresh interval at higher temperatures. If OP[2]=1B, the device temperature is greater than 85°C.
2. At higher temperatures (>85°C), AC timing derating may be required. If derating is required the LPDDR4-SDRAM will set OP[2:0]=110B.
See derating timing requirements.
3. DRAM vendors may or may not report all of the possible settings over the operating temperature range of the device. Each vendor
guarantees that their device will work at any temperature within the range using the refresh interval requested by their device.
4. The device may not operate properly when OP[2:0]=000B or 111B.
5. Post-package repair can be entered or exited by writing to OP[4].
6. When OP[7]=1, the refresh rate reported in OP[2:0] has changed since the last MR4 read. A mode register read from MR4 will reset
OP[7] to '0'.
7. OP[7]=0 at power-up. OP[2:0] bits are valid after initialization sequence(Te)
26
Version 1.2
Nanya Technology Corp.
09/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
8. See the section on "Temperature Sensor" for information on the recommended frequency of reading MR4.
9. OP[6:3] bits that can be written in this register. All other bits will be ignored by the DRAM during a MRW to this register.
10. Refer to the supplier data sheet for vender specific function.
11. Self refresh abort feature is available for higher density devices starting with 12Gb device.
27
Version 1.2
09/2018
Nanya Technology Corp.
All Rights Reserved ©
NTC Proprietary
Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
MR5 Register Information (MA[5:0] = 05H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
Manufacturer ID
Register
Function
Operand
Data
Notes
Type
0000 0101B: Nanya
All Others: Reserved
Manufacturer ID
Read-only
OP[7:0]
MR6 Register Information (MA[5:0] = 06H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
Revision ID-1
Register
Function
Operand
Data
Notes
Type
0000 0000B: A-die
Revision ID-1
Read-only
OP[7:0]
1
All Others: Reserved
Notes:
1. MR6 is vendor specific.
MR7 Register Information (MA[5:0] = 07H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
Revision ID-2
Register
Function
Operand
Data
Notes
Type
0000 0000B: A Version
All Others: Reserved
Revision ID-2
Read-only
OP[7:0]
1
Notes:
1. MR7 is vendor specific.
28
Version 1.2
Nanya Technology Corp.
09/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
MR8 Register Information (MA[5:0] = 08H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
IO Width
Density
Type
Register
Function
Operand
Data
Notes
Type
00 : S16 SDRAM (16n pre-fetch)
B
Type
OP[1:0]
OP[5:2]
OP[7:6]
All Others: Reserved
0000 : 4Gb dual channel die/2Gb single channel die
B
0001 : 6Gb dual channel die/3Gb single channel die
B
0010 : 8Gb dual channel die/4Gb single channel die
B
0011 : 12Gb dual channel die/6Gb single channel die
B
Density
Read-only
0100 : 16Gb dual channel die/8Gb single channel die
B
0101 : 24Gb dual channel die/12Gb single channel die
B
0110 : 32Gb dual channel die/16Gb single channel die
B
1100 : 2Gb dual channel die/1Gb single channel die
B
All Others: Reserved
00 : x16 (per channel)
B
IO Width
All Others: Reserved
MR9 Register Information (MA[5:0] = 09H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[2]
OP[1]
OP[1]
OP[0]
Vendor Specific Test Register
Notes:
1. Only 00H should be written to this register.
MR10 Register Information (MA[5:0] = 0AH)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[0]
RFU
ZQ-Reset
Register
Function
Operand
Data
0 : Normal Operation (Default)
Notes
Type
B
ZQ-Reset
Write-only
OP[0]
1,2
1 : ZQ Reset
B
Notes:
1. ZQCal Timing Parameters for calibration latency and timing.
2. If the ZQ-pin is connected to VDDQ through RZQ, either the ZQ calibration function or default calibration (via ZQ-Reset) is supported. If
the ZQ-pin is connected to VSS, the device operates with default calibration, and ZQ calibration commands are ignored. In both cases,
the ZQ connection shall not change after power is applied to the device.
29
Version 1.2
Nanya Technology Corp.
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NTC Proprietary
Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
MR11 Register Information (MA[5:0] = 0BH)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
RFU
CA ODT
RFU
DQ ODT
Register
Function
Operand
Data
000 : Disable (Default)
Notes
Type
B
001 : RZQ/1
B
010 : RZQ/2
B
DQ ODT
011 : RZQ/3
B
(DQ Bus Receiver
OP[2:0]
1,2,3
100 : RZQ/4
B
On-Die-Termination)
101 : RZQ/5
B
110 : RZQ/6
B
111 : RFU
B
Write-only
000 : Disable (Default)
B
001 : RZQ/1
B
010 : RZQ/2
B
CA ODT
011 : RZQ/3
B
(CA Bus Receiver
On-Die-Termination)
OP[6:4]
1,2,3
100 : RZQ/4
B
101 : RZQ/5
B
110 : RZQ/6
B
111 : RFU
B
Notes:
1. All values are "typical". The actual value after calibration will be within the specified tolerance for a given voltage and temperature.
Re-calibration may be required as voltage and temperature vary.
2. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. Only the registers
for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR
address, or read from with an MRR command to this address.
3. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. The device will
operate only according to the values stored in the registers for the active set point, i.e., the set point determined by the state of the
FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed
without affecting device operation.
30
Version 1.2
Nanya Technology Corp.
09/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
MR12 Register Information (MA[5:0] = 0CH)
OP[7]
CBT Mode
for Byte
Mode
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
VR-CA
VREF(CA)
Register
Function
Operand
Data
Notes
Type
000000 :
B
VREF(CA)
-- Thru --
1,2,3,
5,6
OP[5:0]
(VREF(CA) Setting)
110010 : See table below
B
All Others: Reserved
Read/
Write
VR-CA
1,2,4,
5,6
0 : VREF(CA) Range[0] enabled
B
OP[6]
OP[7]
(VREF(CA) Range)
1 : VREF(CA) Range[1] enabled (default)
B
0 : Mode1(Default)
B
CBT Mode for Byte Mode
7
1 : Mode2
B
Notes:
1. This register controls the VREF(CA) levels. Refer to VREF Settings for Range[0] and Range[1] for actual voltage of VREF(CA).
2. A read to this register places the contents of OP[7:0] on DQ[7:0]. Any RFU bits and unused DQ's shall be set to '0'. See the section on
MRR Operation.
3. A write to OP[5:0] sets the internal VREF(CA) level for FSP[0] when MR13 OP[6]=0B, or sets the internal VREF(CA) level for FSP[1] when
MR13 OP[6]=1B. The time required for VREF(CA) to reach the set level depends on the step size from the current level to the new
level. See the section on VREF(CA) training for more information.
4. A write to OP[6] switches the LPDDR4-SDRAM between two internal VREF(CA) ranges. The range (Range[0] or Range[1]) must be
selected when setting the VREF(CA) register. The value, once set, will be retained until overwritten, or until the next power-on or
RESET event.
5. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. Only the registers
for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR
address, or read from with an MRR command to this address.
6. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. The device will
operate only according to the values stored in the registers for the active set point, i.e., the set point determined by the state of the
FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed
without affecting device operation.
7. MR12 OP[7]=1 setting is only allowed for Byte Mode (x8) devices. MRR of MR12 OP[7] for a non-Byte Mode device will read an
undefined result.
31
Version 1.2
Nanya Technology Corp.
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All Rights Reserved ©
NTC Proprietary
Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
VREF Settings for Range[0] and Range[1]
Function Operand
Notes
Range[0] Values (% of V
)
Range[1] Values (% of V
)
DD2
DD2
000000 : 10.0%
011010 : 20.4%
000000 : 22.0%
011010 : 32.4%
B
B
B
B
000001 : 10.4%
011011 : 20.8%
000001 : 22.4%
011011 : 32.8%
B
B
B
B
000010 : 10.8%
011100 : 21.2%
000010 : 22.8%
011100 : 33.2%
B
B
B
B
000011 : 11.2%
011101 : 21.6%
000011 : 23.2%
011101 : 33.6%
B
B
B
B
000100 : 11.6%
011110 : 22.0%
000100 : 23.6%
011110 : 34.0%
B
B
B
B
000101 : 12.0%
011111 : 22.4%
000101 : 24.0%
011111 : 34.4%
B
B
B
B
000110 : 12.4%
100000 : 22.8%
000110 : 24.4%
100000 : 34.8%
B
B
B
B
000111 : 12.8%
100001 : 23.2%
000111 : 24.8%
100001 : 35.2%
B
B
B
B
001000 : 13.2%
100010 : 23.6%
001000 : 25.2%
100010 : 35.6%
B
B
B
B
001001 : 13.6%
100011 : 24.0%
001001 : 25.6%
100011 : 36.0%
B
B
B
B
001010 : 14.0%
100100 : 24.4%
001010 : 26.0%
100100 : 36.4%
B
B
B
B
001011 : 14.4%
100101 : 24.8%
001011 : 26.4%
100101 : 36.8%
B
B
B
B
V
REF
001100 : 14.8%
100110 : 25.2%
001100 : 26.8%
100110 : 37.2%
B
B
B
B
Settings
for
OP[5:0]
1,2,3
001101 : 27.2%
B
001101 : 15.2%
100111 : 25.6%
100111 : 37.6%
B
B
B
(Default)
MR12
001110 : 15.6%
101000 : 26.0%
001110 : 27.6%
101000 : 38.0%
B
B
B
B
001111 : 16.0%
101001 : 26.4%
001111 : 28.0%
101001 : 38.4%
B
B
B
B
010000 : 16.4%
101010 : 26.8%
010000 : 28.4%
101010 : 38.8%
B
B
B
B
010001 : 16.8%
101011 : 27.2%
010001 : 28.8%
101011 : 39.2%
B
B
B
B
010010 : 17.2%
101100 : 27.6%
010010 : 29.2%
101100 : 39.6%
B
B
B
B
010011 : 17.6%
101101 : 28.0%
010011 : 29.6%
101101 : 40.0%
B
B
B
B
010100 : 18.0%
101110 : 28.4%
010100 : 30.0%
101110 : 40.4%
B
B
B
B
010101 : 18.4%
101111 : 28.8%
010101 : 30.4%
101111 : 40.8%
B
B
B
B
010110 : 18.8%
110000 : 29.2%
010110 : 30.8%
110000 : 41.2%
B
B
B
B
010111 : 19.2%
110001 : 29.6%
010111 : 31.2%
110001 : 41.6%
B
B
B
B
011000 : 19.6%
110010 : 30.0%
011000 : 31.6%
110010 : 42.0%
B
B
B
B
All Others: Reserved
All Others: Reserved
011001 : 20.0%
011001 : 32.0%
B
B
Notes:
1. These values may be used for MR12 OP[5:0] to set the VREF(CA) levels in the LPDDR4-SDRAM.
2. The range may be selected in the MR12 register by setting OP[6] appropriately.
3. The MR12 registers represents either FSP[0] or FSP[1]. Two frequency-set-points each for CA and DQ are provided to allow for faster
switching between terminated and un-terminated operation, or between different high-frequency setting which may use different
terminations values.
32
Version 1.2
Nanya Technology Corp.
09/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
MR13 Register Information (MA[5:0] = 0DH)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
FSP-OP
FSP-WR
DMD
RRO
VRCG
VRO
RPT
CBT
Register
Function
CBT
Operand
Data
0 : Normal Operation (default)
Notes
Type
B
OP[0]
OP[1]
1
(Command Bus Training)
RPT
1 : Command Bus Training Mode Enabled
B
0 : Disable (default)
B
(Read Preamble Training Mode)
1 : Enable
B
0 : Normal operation (default)
B
VRO
OP[2]
2
1 : Output the V (CA) and V (DQ) values
B
REF
REF
(VREF Output)
on DQ bits
0 : Normal Operation (default)
VRCG
(VREF Current Generator)
RRO
B
OP[3]
OP[4]
OP[5]
OP[6]
3
4, 5
6
1 : V Fast Response (high current) mode
Write-only
B
REF
0 : Disable codes 001 and 010 in MR4 OP[2:0]
B
(Refresh rate option)
DMD
1 : Enable all codes in MR4 OP[2:0]
B
0 : Data Mask Operation Enabled (default)
B
(Data Mask Disable)
1 : Data Mask Operation Disabled
B
FSP-WR
0 : Frequency-Set-Point[0] (default)
B
7
(Frequency Set Point Write Enable)
1 : Frequency-Set-Point [1]
B
FSP-OP
0 : Frequency-Set-Point[0] (default)
B
OP[7]
8
(Frequency Set Point Operation Mode)
1 : Frequency-Set-Point [1]
B
Notes:
1. A write to set OP[0]=1 causes the LPDDR4-SDRAM to enter the Command Bus Training mode. When OP[0]=1 and CKE goes LOW,
commands are ignored and the contents of CA[5:0] are mapped to the DQ bus. CKE must be brought HIGH before doing a MRW to
clear this bit (OP[0]=0) and return to normal operation. See the Command Bus Training section for more information.
2. When set, the LPDDR4-SDRAM will output the VREF(CA) and VREF (DQ) voltages on DQ pins. Only the “active” frequency-set-point, as
defined by MR13 OP[7], will be output on the DQ pins. This function allows an external test system to measure the internal VREF
levels. The DQ pins used for VREF output are vendor specific.
3. When OP[3]=1, the VREF circuit uses a high-current mode to improve VREF settling time.
4. MR13 OP4 RRO bit is valid only when MR0 OP0 = 1. For LPDDR4 devices with MR0 OP0 = 0, MR4 OP[2:0] bits are not dependent on
MR13 OP4.
5. When OP[4] = 0, only 001B and 010B in MR4 OP[2:0] are disabled. LPDDR4 devices must report 011B instead of 001B or 010B in this
case. Controller should follow the refresh mode reported by MR4 OP[2:0], regardless of RRO setting. TCSR function does not depend
on RRO setting.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
6. When enabled (OP[5]=0B) data masking is enabled for the device. When disabled (OP[5]=1B), masked write command is illegal. See
LPDDR4 Data Mask (DM) and Data Bus Inversion (DBIdc) Function.
7. FSP-WR determines which frequency-set-point registers are accessed with MRW commands for the following functions such as
VREF(CA) Setting, VREF(CA) Range, VREF(DQ) Setting, VREF(DQ) Range. For more information, refer to “Frequency Set Point”.
8. FSP-OP determines which frequency-set-point register values are currently used to specify device operation for the following
functions such as VREF(CA) Setting, VREF(CA) Range, VREF(DQ) Setting, VREF(DQ) Range. For more information, refer to “Frequency Set
Point section”.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
MR14 Register Information (MA[5:0] = 0EH)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
RFU
VR(DQ)
VREF(DQ)
Register
Function
Operand
Data
Notes
Type
000000 :
B
-- Thru --
1,2,3,
5,6
V
(DQ)
REF
OP[5:0]
OP[6]
Read/
Write
(V (DQ) Setting)
REF
110010 : See table below
B
All Others: Reserved
VR(dq)
1,2,4,
5,6
0 : V (DQ) Range[0] enabled
B
REF
(V (DQ) Range)
REF
1 : V (DQ) Range[1] enabled (default)
B REF
Notes:
1. This register controls the VREF(DQ) levels for Frequency-Set-Point[1:0]. Values from either VR(DQ)[0] or VR(dq)[1] may be selected by
setting OP[6] appropriately.
2. A read (MRR) to this register places the contents of OP[7:0] on DQ[7:0]. Any RFU bits and unused DQ's shall be set to‘0’. See the
section on MRR Operation.
3. A write to OP[5:0] sets the internal VREF(DQ) level for FSP[0] when MR13 OP[6]=0B, or sets FSP[1] when MR13 OP[6]=1B. The time
required for VREF(DQ) to reach the set level depends on the step size from the cur-rent level to the new level. See the section on
VREF(DQ) training for more information.
4. A write to OP[6] switches the LPDDR4-SDRAM between two internal VREF(DQ) ranges. The range (Range[0] or Range[1]) must be
selected when setting the VREF(DQ) register. The value, once set, will be retained until overwritten, or until the next power-on or
RESET event.
5. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. Only the registers
for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR
address, or read from with an MRR command to this address.
6. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. The device will
operate only according to the values stored in the registers for the active set point, i.e., the set point determined by the state of the
FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed
without affecting device operation.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
VREF Settings for Range[0] and Range[1]
Function Operand
Notes
Range[0] Values (% of V
)
Range[1] Values (% of V
)
DDQ
DDQ
000000 : 10.0%
011010 : 20.4%
000000 : 22.0%
011010 : 32.4%
B
B
B
B
000001 : 10.4%
011011 : 20.8%
000001 : 22.4%
011011 : 32.8%
B
B
B
B
000010 : 10.8%
011100 : 21.2%
000010 : 22.8%
011100 : 33.2%
B
B
B
B
000011 : 11.2%
011101 : 21.6%
000011 : 23.2%
011101 : 33.6%
B
B
B
B
000100 : 11.6%
011110 : 22.0%
000100 : 23.6%
011110 : 34.0%
B
B
B
B
000101 : 12.0%
011111 : 22.4%
000101 : 24.0%
011111 : 34.4%
B
B
B
B
000110 : 12.4%
100000 : 22.8%
000110 : 24.4%
100000 : 34.8%
B
B
B
B
000111 : 12.8%
100001 : 23.2%
000111 : 24.8%
100001 : 35.2%
B
B
B
B
001000 : 13.2%
100010 : 23.6%
001000 : 25.2%
100010 : 35.6%
B
B
B
B
001001 : 13.6%
100011 : 24.0%
001001 : 25.6%
100011 : 36.0%
B
B
B
B
001010 : 14.0%
100100 : 24.4%
001010 : 26.0%
100100 : 36.4%
B
B
B
B
001011 : 14.4%
100101 : 24.8%
001011 : 26.4%
100101 : 36.8%
B
B
B
B
V
REF
001100 : 14.8%
100110 : 25.2%
001100 : 26.8%
100110 : 37.2%
B
B
B
B
Settings
for
OP[5:0]
1,2,3
001101 : 27.2%
B
001101 : 15.2%
100111 : 25.6%
100111 : 37.6%
B
B
B
(Default)
MR14
001110 : 15.6%
101000 : 26.0%
001110 : 27.6%
101000 : 38.0%
B
B
B
B
001111 : 16.0%
101001 : 26.4%
001111 : 28.0%
101001 : 38.4%
B
B
B
B
010000 : 16.4%
101010 : 26.8%
010000 : 28.4%
101010 : 38.8%
B
B
B
B
010001 : 16.8%
101011 : 27.2%
010001 : 28.8%
101011 : 39.2%
B
B
B
B
010010 : 17.2%
101100 : 27.6%
010010 : 29.2%
101100 : 39.6%
B
B
B
B
010011 : 17.6%
101101 : 28.0%
010011 : 29.6%
101101 : 40.0%
B
B
B
B
010100 : 18.0%
101110 : 28.4%
010100 : 30.0%
101110 : 40.4%
B
B
B
B
010101 : 18.4%
101111 : 28.8%
010101 : 30.4%
101111 : 40.8%
B
B
B
B
010110 : 18.8%
110000 : 29.2%
010110 : 30.8%
110000 : 41.2%
B
B
B
B
010111 : 19.2%
110001 : 29.6%
010111 : 31.2%
110001 : 41.6%
B
B
B
B
011000 : 19.6%
110010 : 30.0%
011000 : 31.6%
110010 : 42.0%
B
B
B
B
All Others: Reserved
All Others: Reserved
011001 : 20.0%
011001 : 32.0%
B
B
Notes:
1. These values may be used for MR14 OP[5:0] to set the VREF(DQ) levels in the LPDDR4-SDRAM.
2. The range may be selected in the MR14 register by setting OP[6] appropriately.
3. The MR14 registers represents either FSP[0] or FSP[1]. Two frequency-set-points each for CA and DQ are pro-vided to allow for faster
switching between terminated and un-terminated operation, or between different high frequency setting which may use different
terminations values.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
MR15 Register Information (MA[5:0] = 0FH)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
Lower-Byte Invert Register for DQ Calibration
Register
Operand
Type
Function
Data
Notes
The following values may be written for any
operand OP[7:0], and will be applied to the
corresponding DQ locations DQ[7:0] within a
byte lane:
Lower-Byte Invert
for DQ Calibration
Write-only
OP[7:0]
1,2,3
0 : Do not invert
B
1 : Invert the DQ Calibration patterns in MR32
B
and MR40
Default value for OP[7:0]=55
H
Notes:
1. This register will invert the DQ Calibration pattern found in MR32 and MR40 for any single DQ, or any combination of DQ's. Example:
If MR15 OP[7:0]=00010101B, then the DQ Calibration patterns transmitted on DQ[7,6,5,3,1] will not be inverted, but the DQ
Calibration patterns transmitted on DQ[4,2,0] will be inverted.
2. DMI[0] is not inverted, and always transmits the “true” data contained in MR32/MR40.
3. No Data Bus Inversion (DBI) function is enacted during DQ Read Calibration, even if DBI is enabled in MR3-OP[6].
MR15 Invert Register Pin Mapping
PIN
DQ0
DQ1
DQ2
DQ3
DMI0
DQ4
DQ5
DQ6
DQ7
MR15
OP0
OP1
OP2
OP3
NO-Invert
OP4
OP5
OP6
OP7
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
MR16 Register Information (MA[5:0] = 10H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
PASR Bank Mask
Register
Function
Operand
Data
0 : Bank Refresh enabled (default) : Unmasked
Notes
Type
B
Bank[7:0] Mask
Write-only
OP[7:0]
1
1 : Bank Refresh disabled : Masked
B
OP[n]
Bank Mask
8-Bank SDRAM
Bank 0
0
1
2
3
4
5
6
7
xxxxxxx1
xxxxxx1x
xxxxx1xx
xxxx1xxx
xxx1xxxx
xx1xxxxx
x1xxxxxx
1xxxxxxx
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
Notes:
1. When a mask bit is asserted (OP[n]=1), refresh to that bank is disabled.
2. PASR bank-masking is on a per-channel basis. The two channels on the die may have different bank masking in dual channel devices.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
MR17 Register Information (MA[5:0] = 11H) for x16 mode
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
PASR Segment Mask
Register
Function
Operand
Data
0 : Segment Refresh enabled (default)
Notes
Type
B
PASR Segment Mask
Write-only
OP[7:0]
1 : Segment Refresh disabled
B
1Gb
per
2Gb
per
3Gb
per
4Gb
per
6Gb
per
8Gb
per
12Gb
per
16Gb
per
Segment
Mask
Segment OP[n]
channel channel channel channel channel channel channel channel
R12:R10 R13:R11 R14:R12 R14:R12 R15:R13 R15:R13 R16:R14 R16:R14
0
1
0
1
xxxxxxx1
xxxxxx1x
000
001
B
B
2
2
3
4
5
6
7
xxxxx1xx
xxxx1xxx
xxx1xxxx
xx1xxxxx
x1xxxxxx
1xxxxxxx
010
011
100
101
B
B
B
B
3
4
5
6
110
111
110
111
110
111
110
111
110
111
B
B
B
B
B
Not
Allowed
Not
Allowed
Not
Allowed
7
B
B
B
B
B
Notes:
1. This table indicates the range of row addresses in each masked segment. "X" is don't care for a particular segment.
2. PASR segment-masking is on a per-channel basis. The two channels on the die may have different segment masking in dual channel
devices.
3. For 3Gb, 6Gb, and 12Gb densities, OP[7:6] must always be LOW (=00B).
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
MR17 Register Information (MA[5:0] = 11H) for Byte mode (x8_2ch)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
PASR Segment Mask
Register
Function
Operand
Data
0 : Segment Refresh enabled (default)
Notes
Type
B
PASR Segment Mask
Write-only
OP[7:0]
1 : Segment Refresh disabled
B
1Gb
per
2Gb
per
3Gb
per
4Gb
per
6Gb
per
8Gb
per
12Gb
per
16Gb
per
Segment
Mask
Segment OP[n]
channel channel channel channel channel channel channel channel
R13:R11 R14:R12 R15:R13 R15:R13 R16:R14 R16:R14 R17:R15 R17:R15
0
1
0
1
xxxxxxx1
xxxxxx1x
000
001
B
B
2
2
3
4
5
6
7
xxxxx1xx
xxxx1xxx
xxx1xxxx
xx1xxxxx
x1xxxxxx
1xxxxxxx
010
011
100
101
B
B
B
B
3
4
5
6
110
111
110
111
110
111
110
111
110
111
B
B
B
B
B
Not
Allowed
Not
Allowed
Not
Allowed
7
B
B
B
B
B
Notes:
1. This table indicates the range of row addresses in each masked segment. "X" is don't care for a particular segment.
2. PASR segment-masking is on a per-channel basis. The two channels on the die may have different segment masking.
3. For 3Gb, 6Gb, and 12Gb densities, OP[7:6] must always be LOW (=00B).
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
MR18 Register Information (MA[5:0] = 12H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
DQS Oscillator Count - LSB
Register
Function
Operand
Data
Notes
Type
DQS Oscillator
Read-only
OP[7:0]
0 - 255 LSB DRAM DQS Oscillator Count
1,2,3
(WR Training DQS Oscillator)
Notes:
1. MR18 reports the LSB bits of the DRAM DQS Oscillator count. The DRAM DQS Oscillator count value is used to train DQS to the DQ
data valid window. The value reported by the DRAM in this mode register can be used by the memory controller to periodically adjust
the phase of DQS relative to DQ.
2. Both MR18 and MR19 must be read (MRR) and combined to get the value of the DQS Oscillator count.
3. A new MPC [Start DQS Oscillator] should be issued to reset the contents of MR18/MR19.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
MR19 Register Information (MA[5:0] = 13H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
DQS Oscillator Count - MSB
Register
Type
Function
Operand
Data
Notes
DQS Oscillator
Read-only
OP[7:0]
0-255 MSB DRAM DQS Oscillator Count
1,2,3
(WR Training DQS Oscillator)
Notes:
1. MR19 reports the MSB bits of the DRAM DQS Oscillator count. The DRAM DQS Oscillator count value is used to train DQS to the DQ
data valid window. The value reported by the DRAM in this mode register can be used by the memory controller to periodically adjust
the phase of DQS relative to DQ.
2. Both MR18 and MR19 must be read (MRR) and combined to get the value of the DQS Oscillator count.
3. A new MPC [Start DQS Oscillator] should be issued to reset the contents of MR18/MR19.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
MR20 Register Information (MA[5:0] = 14H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
Upper-Byte Invert Register for DQ Calibration
Register
Operand
Type
Function
Data
Notes
The following values may be written for any
operand OP[7:0], and will be applied to the
corresponding DQ locations DQ[15:8] within a
byte lane:
Upper-Byte Invert
for DQ Calibration
Write-only
OP[7:0]
1,2
0 : Do not invert
B
1 : Invert the DQ Calibration patterns in MR32
B
and MR40
Default value for OP[7:0] = 55
H
Notes:
1. This register will invert the DQ Calibration pattern found in MR32 and MR40 for any single DQ, or any combination of DQ's. Example:
If MR20 OP[7:0]=00010101B, then the DQ Calibration patterns transmitted on DQ[15,14,13,11,9] will not be inverted, but the DQ
Calibration patterns transmitted on DQ[12,10,8] will be inverted.
2. DMI[1] is not inverted, and always transmits the "true" data contained in MR32/MR40.
3. No Data Bus Inversion (DBI) function is enacted during DQ Read Calibration, even if DBI is enabled in MR3-OP[6].
MR20 Invert Register Pin Mapping
PIN
DQ8
DQ9
DQ10
DQ11
DMI1
DQ12
DQ13
DQ14
DQ15
MR20
OP0
OP1
OP2
OP3
NO-Invert
OP4
OP5
OP6
OP7
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
MR22 Register Information (MA[5:0] = 16H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
ODTD for x8_2ch(Byte) mode
ODTD-CA
ODTE-CS
ODTE-CK
SOC ODT
Register
Function
Operand
Data
000 : Disable (Default)
Notes
Type
B
001 : RZQ/1
B
010 : RZQ/2
B
SoC ODT
011 : RZQ/3
B
(Controller ODT Value for
VOH calibration)
OP[2:0]
1,2,3
100 : RZQ/4
B
101 : RZQ/5
B
110 : RZQ/6
B
111 : RFU
B
ODTE-CK
(CK ODT enabled for non
terminating rank)
ODTE-CS
2,3,4,
6,8
0 : ODT-CK Over-ride Disabled (Default)
B
OP[3]
1 : ODT-CK Over-ride Enabled
B
Write-only
2,3,5,
6,8
0 : ODT-CS Over-ride Disabled (Default)
B
(CS ODT enable for non
terminating rank)
OP[4]
OP[5]
OP[6]
1 : ODT-CS Over-ride Enabled
B
ODTD-CA
2,3,6,
7,8
0 : ODT-CA Obeys ODT_CA bond pad (default)
B
(CA ODT termination disable)
1 : ODT-CA Disabled
B
X8ODTD[7:0]
(CA/CK ODT termination disable,
[7:0] Byte select)
x8_2ch only, [7:0] Byte selected Device
6,8,9,
11
0 : ODT-CA Obeys ODT_CA bond pad (default)
B
1 : ODT-CS/CA /CK Disabled
B
X8ODTD[15:8]
x8_2ch only, [15:8] Byte selected Device
6,8,10,
11
(CA/CK ODT termination disable,
[15:8] Byte select)
OP[7]
0 : ODT-CA Obeys ODT_CA bond pad (default)
B
1 : ODT-CS/CA /CK Disabled
B
Notes:
1. All values are “typical".
2. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. Only
the registers for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW
command to this MR address, or read from with an MRR command to this address.
3. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. The
device will operate only according to the values stored in the registers for the active set point, i.e., the set point
determined by the state of the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be
ignored by the device, and may be changed without affecting device operation.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
4. When OP[3]=1, then the CK signals will be terminated to the value set by MR11-OP[6:4] regardless of the state of the
ODT_CA bond pad. This overrides the ODT_CA bond pad for configurations where CA is shared by two or more DRAMs
but CK is not, allowing CK to terminate on all DRAMs.
5. When OP[4]=1, then the CS signal will be terminated to the value set by MR11-OP[6:4] regardless of the state of the
ODT_CA bond pad. This overrides the ODT_CA bond pad for configurations where CA is shared by two or more DRAMs
but CS is not, allowing CS to terminate on all DRAMs.
6. For system configurations where the CK, CS, and CA signals are shared between packages, the package design should
provide for the ODT_CA ball to be bonded on the system board outside of the memory package. This provides the
necessary control of the ODT function for all die with shared Command Bus signals.
7. When OP[5]=0, CA[5:0] will terminate when the ODT_CA bond pad is HIGH and MR11-OP[6:4] is VALID, and disables
termination when ODT_CA is LOW or MR11-OP[6:4] is disabled. When OP[5]=1, termination for CA[5:0] is disabled,
regardless of the state of the ODT_CA bond pad or MR11-OP[6:4].
8. To ensure proper operation in a multi-rank configuration, when CA, CK or CS ODT is enabled via MR11 OP[6:4] and also
via MR22 or CA-ODT pad setting, the rank providing ODT will continue to terminate the com-mand bus in all DRAM
states including Active Self Refresh, Self Refresh Power-down, Active Power-down and Precharge Power-down.
9. To ensure proper operation for x8_2ch devices, OP[6] disabled CS/CA/CLK ODT of lower byte selected device regardless
MR11 and MR22 OP[5:0] settings.
10. To ensure proper operation for x8_2ch devices, OP[7] disabled CS/CA/CLK ODT of upper byte selected device
regardless MR11 and MR22 OP[5:0] settings.
11. Upper [15:8] and lower [7:0] bytes are assigned by the manufacturer and cannot be assigned by the application.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
MR23 Register Information (MA[5:0] = 17H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
DQS interval timer run time setting
Register
Type
Function
Operand
Data
Notes
00000000 : DQS interval timer stop via
B
MPC Command (Default)
00000001 : DQS timer stops automatically
B
at 16th clocks after timer start
00000010 : DQS timer stops automatically
B
at 32nd clocks after timer start
00000011 : DQS timer stops automatically
B
at 48th clocks after timer start
00000100 : DQS timer stops automatically
B
DQS interval timer run time Write-only
OP[7:0]
at 64th clocks after timer start
1, 2
-------------- Thru --------------
00111111 : DQS timer stops automatically
B
at (63X16)th clocks after timer start
01XXXXXX : DQS timer stops automatically
B
at 2048th clocks after timer start
10XXXXXX : DQS timer stops automatically
B
at 4096th clocks after timer start
11XXXXXX : DQS timer stops automatically
B
at 8192nd clocks after timer start
Notes:
1. MPC command with OP[6:0]=1001101B (Stop DQS Interval Oscillator) stops DQS interval timer in case of MR23 OP[7:0] = 00000000B.
2. MPC command with OP[6:0]=1001101B (Stop DQS Interval Oscillator) is illegal with non-zero values in MR23 OP[7:0].
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
MR24 Register Information (MA[5:0] = 18H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
Unlimited MAC
TRR Mode
TRR Mode BAn
MAC Value
Register
Type
Function
Operand
Data
000 : Unknown when bit OP3=0 (Note 1)
Notes
B
Unlimited when bit OP3=1 (Note 2)
001 : 700K
B
010 : 600K
B
MAC Value
OP[2:0]
011 : 500K
B
Read-only
100 : 400K
B
101 : 300K
B
110 : 200K
B
111 : Reserved
B
0 : OP[2:0] define MAC value
B
Unlimited MAC
TRR Mode BAn
TRR Mode
OP[3]
OP[6:4]
OP[7]
1 : Unlimited MAC value (Note 2, Note 3)
B
000 : Bank 0
B
001 : Bank 1
B
010 : Bank 2
B
011 : Bank 3
B
100 : Bank 4
B
Write-only
101 : Bank 5
B
110 : Bank 6
B
111 : Bank 7
B
0 : Disabled (default)
B
1 : Enabled
B
Notes:
1. Unknown means that the device is not tested for tMAC and pass/fail value in unknown.
2. There is no restriction to number of activates.
3. MR24 OP [2:0] is set to zero.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
MR25 Register Information (MA[5:0] = 19H)
Mode Register 25 contains one bit of readout per bank indicating that at least one resource is available for Post
Package Repair programming.
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
Bank7
Bank6
Bank5
Bank4
Bank3
Bank2
Bank1
Bank0
Register
Function
Operand
Data
0 : PPR Resource is not available
Notes
Type
B
PPR Resource
Read-only
OP[7:0]
1 : PPR Resource is available
B
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
MR30 Register Information (MA[5:0] = 1EH)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
Valid 0 or 1
Register
Function
Operand
Data
Notes
Type
SDRAM will ignore
Write-only
OP[7:0]
Don’t care
Notes:
1. This register is reserved for testing purposes. The logical data values written to OP[7:0] shall have no effect on SDRAM operation,
however timings need to be observed as for any other MR access command..
MR31 Register Information (MA[5:0] = 1FH)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
Bytemode Vref Selection
RFU
Register
Function
Operand
Data
Notes
Type
0B: x16 device and no Byte mode
selection(Default)
Bytemode Vref Selection-
Lower Byte
OP[6]
1,2,3
1B: Disable to update MR12/MR14 for lower
byte
Write-only
0B: x16 device and no Byte mode
selection(Default)
Bytemode Vref Selection-
Upper Byte
OP[7]
1,2,3
1B: Disable to update MR12/MR14 for upperr
byte
Notes:
1. The byte mode Vref selecion is optional. Please consult with vendors for the availability to support feature.
2. When Byte mode Vref selection is applied, the non-targeted byte is required to disable to update VrefCA and VrefDQ setting,
assigned in MR12 and MR14 OP[6:0], for the other targeted byte.
- In order to update MR12/MR14 setting only for upper byte, it is required to disable byte mode selection on
lower byte, as applying MR31 OP[7:6] = 01B.
- In order to update MR12/MR14 setting only for lower byte, it is required to disable byte mode selection on
upper byte, as applying MR31 OP[7:6] = 10B.
- When OP[7:6] = 00B is applied, both lower byte and upper byte will be updated.
3. When the configuration is not composed of byte mode device, MR31 OP[7:6] shall be the default value, 00B.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
MR32 Register Information (MA[5:0] = 20H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
DQ Calibration Pattern “A” (default = 5A )
H
Register
Operand
Type
Function
Data
X : An MPC command with OP[6:0]= 1000011
Notes
B
B
causes the device to return the DQ Calibration
Pattern contained in this register and (followed
by) the contents of MR40. A default pattern
Return DQ Calibration
Pattern MR32 + MR40
Write
OP[7:0]
1,2,3
“5A ”is loaded at power-up or RESET, or the
H
pattern may be overwritten with a MRW to this
register. The contents of MR15 and MR20 will
invert the data pattern for a given DQ
(See MR15 for more information)
MR39 Register Information (MA[5:0] = 27H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
Valid 0 or 1
Register
Function
Operand
Data
Notes
Type
SDRAM will ignore
Write-only
OP[7:0]
Don’t care
1
Notes:
1. This register is reserved for testing purposes. The logical data values written to OP[7:0] shall have no effect on SDRAM operation,
however timings need to be observed as for any other MR access command.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
MR40 Register Information (MA[5:0] = 28H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
DQ Calibration Pattern “B” (default = 3C )
H
Register
Operand
Type
Function
Data
X : A default pattern “3C ” is loaded at
Notes
B
H
Return DQ Calibration
Pattern MR32 + MR40
Write
only
power-up or RESET, or the pattern may be
overwritten with a MRW to this register.
See MR32 for more information.
OP[7:0]
1,2,3
Notes:
1. The pattern contained in MR40 is concatenated to the end of MR32 and transmitted on DQ[15:0] and DMI[1:0] when DQ Read
Calibration is initiated via a MPC command. The pattern transmitted serially on each data lane, organized “little endian” such that the
low-order bit in a byte is transmitted first. If the data pattern in MR40 is 27H , then the first bit transmitted with be a '1', followed by
'1', '1', '0', '0', '1', '0', and '0'. The bit stream will be 00100111B.
2. MR15 and MR20 may be used to invert the MR32/MR40 data patterns on the DQ pins. See MR15 and MR20 for more information.
Data is never inverted on the DMI[1:0] pins..
3. The data pattern is not transmitted on the DMI[1:0] pins if DBI-RD is disabled via MR3-OP[6].
4. No Data Bus Inversion (DBI) function is enacted during DQ Read Calibration, even if DBI is enabled in MR3-OP[6].
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Command Definitions and Timing Diagrams
ACTIVATE Command
The ACTIVATE command is composed of two consecutive commands, Activate-1 command and Activate-2.
Activate-1 command is issued by holding CS HIGH, CA0 HIGH and CA1 LOW at the first rising edge of the clock
and Activate-2 command issued by holding CS HIGH, CA0 HIGH and CA1 HIGH at the first rising edge of the
clock. The bank addresses BA0, BA1 and BA2 are used to select desired bank. Row addresses are used to
determine which row to activate in the selected bank. The ACTIVATE command must be applied before any
READ or WRITE operation can be executed. The device can accept a READ or WRITE command at tRCD after
the ACTIVATE command is issed. After a bank has been activated it must be precharged before another
ACTIVATE commnand can be applied to the same bank. The bank active and precharge times are defined as
tRAS and tRP respectively. The minimum time interval between ACTIVATE commands to the same bank is
determined by the RAS cycle time of the device(tRC). The minimum time interval between ACTIVATE
commands to different banks is tRRD.
Notes:
1. A PRECHARGE command uses tRPab timing for all-bank PRECHARGE and tRPpb timing for single-bank PRECHARGE.
In this figure, tRP is used to denote either all-bank PRECHARGE or single-bank PRECHARGE.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
8-Bank Device Operation
Certain restrictions on operation of the 8-bank LPDDR4 devices must be observed. There are two rules: One rule
restricts the number of sequential ACTIVATE commands that can be issued; the other provides more time for
RAS precharge for a PRECHARGE ALL command. The rules are as follows:
8 bank device Sequential Bank Activation Restriction:
No more than 4 banks may be activated (or refreshed, in the case of REFpb) in a rolling tFAW window. The
number of clocks in a tFAW period is dependent upon the clock frequency, which may vary. If the clock
frequency is not changed over this period, converting clocks is done by dividing tFAW[ns] by tCK[ns], and
rounding up to the next integer value. As an example of the rolling window, if RU (tFAW/tCK) is 10 clocks, and
an ACTIVATE command is issued in clock n, no more than three further ACTIVATE commands can be issued
at or between clock n + 1 and n + 9. REFpb also counts as bank activation for purposes of tFAW. If the clock
frequency is changed during the tFAW period, the rolling tFAW window may be calculated in clock cycles by
adding up the time spent in each clock period. The tFAW requirement is met when the previous n clock cycles
exceeds the tFAW time.
The 8-Bank Device Precharge-All Allowance:
tRP for a PRECHRGE ALL command must equal tRPab, which is greater than tRPpb.
tFAW Timing
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Core Timing
Core AC Timing for x16 mode
Min/
Parameter
Symbol
Data Rate
Max
Unit
Note
Core Parameters
ACTIVATE-to-ACTIVATE
command period (same bank)
Minimum Self-Refresh Time
(Entry to Exit)
533/1066/1600/2133/2667/3200/3733
4267
tRAS + tRPab (with all-bank precharge)
tRAS + tRPpb (with per-bank precharge)
tRC
tSR
Min
Min
Min
ns
ns
ns
max(15ns, 3nCK)
SELF REFRESH exit to
next valid command delay
Exit Power-Down to next
valid command delay
CAS-to-CAS delay
tXSR
max(tRFCab + 7.5ns, 2nCK)
tXP
tCCD
tRTP
tRCD
tRPpb
Min
Min
Min
Min
Min
max(7.5ns, 5nCK)
8
ns
tCK(avg)
ns
3
Internal READ to
max(7.5ns, 8nCK)
max(18ns, 4nCK)
max(18ns, 4nCK)
PRECHARGE command delay
RAS-to-CAS delay
ns
Row precharge time
ns
(single bank)
Row precharge time (all banks) tRPab
Min
max(21ns, 4nCK)
ns
Min
Max
Min
Min
max(42ns, 3nCK)
Min(9 * tREFI * Refresh Rate, 70.2 us)
max(18ns, 6nCK)
ns
us
ns
ns
Row active time
tRAS
4
2
WRITE recovery time
WRITE-to-READ delay
tWR
tWTR
max(10ns, 8nCK)
max(7.5ns,
Active bank-A to active bank-B
tRRD
Min
max(10ns, 4nCK)
ns
4nCK)
Precharge to Precharge Delay4
Four-bank ACTIVATE window
Notes:
tPPD
Min
Min
4
tCK(avg)
ns
1
2
tFAW
40
30
1. Precharge to precharge timing restriction does not apply to Auto-Precharge commands.
2. Devices supporting 4267 Mbps specification shall support these timings at lower data rates.
3. The value is based on BL16. For BL32 need additional 8 tCK(avg) delay.
4. Refresh Rate is specified by MR4, OP[2:0]
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Core AC Timing for Byte (x8) mode
Min/
Max
Parameter
Symbol
Data Rate
Unit
Note
Core Parameters
533/1066/1600/2133/2667/3200/3733/4267
max(20ns, 6nCK)
WRITE recovery time
WRITE-to-READ delay
tWR
Min
Min
ns
ns
tWTR
max(12ns, 8nCK)
Notes:
1. The rest of the Core AC timing is the same as x16 mode.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Read and Write Access Operations
After a bank has been activated, a read or write command can be executed. This is accomplished by asserting
CKE asynchronously, with CS and CA[5:0] set to the proper state (see Command Truth Table) at a rising edge of
CK.
The LPDDR4-SDRAM provides a fast column access operation. A single Read or Write command will initiate a
burst read or write operation, where data is transferred to/from the DRAM on successive clock cycles. Burst
interrupts are not allowed, but the optimal burst length may be set on the fly (see command truth table).
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Read Preamble and Postamble
The DQS strobe for the LPDDR4-SDRAM requires a pre-amble prior to the first latching edge (the rising edge of
DQS with DATA "valid"), and it requires a post-amble after the last latching edge. The pre-amble and post-amble
lengths are set via mode register writes (MRW).
For READ operations the pre-amble is 2*tCK, but the pre-amble is static (no-toggle) or toggling, selectable via
mode register.
LPDDR4 will have a DQS Read post-amble of 0.5*tCK (or extended to 1.5*tCK). Standard DQS post-amble will
be 0.5*tCK driven by the DRAM for Reads. A mode register setting instructs the DRAM to drive an additional
(extended) one cycle DQS Read post-amble. The drawings below show examples of DQS Read post-amble for
both standard (tRPST) and extended (tRPSTE) post-amble operation.
DQS Read Preamble and Postamble: Toggling Preamble and 0.5nCK Postamble
Notes:
1. BL=16, Preamble = Toggling, Postamble = 0.5nCK
2. DQS and DQ terminated VSSQ
3. DQS/ is “don’t care” prior to the start of tRPRE.
No transition of DQS is implied, as DQS/ can be HIGH, LOW, or HI-Z prior to tRPRE.
DQS Read Preamble and Postamble: Static Preamble and 1.5nCK Postamble
Notes:
1. BL=16, Preamble = Toggling, Postamble = 1.5nCK (Extended)
2. DQS and DQ terminated VSSQ
3. DQS/ is “don’t care” prior to the start of tRPRE.
No transition of DQS is implied, as DQS/ can be HIGH, LOW, or HI-Z prior to tRPRE.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Burst Read Operation
A burst Read command is initiated with CS, and CA[5:0] asserted to the proper state at the rising edge of CK, as
defined by the Command Truth Table. The command address bus inputs determine the starting column address
for the burst. The two low-order address bits are not transmitted on the CA bus and are implied to be “0”, so that
the starting burst address is always a multiple of four (ex. 0x0, 0x4, 0x8, 0xC). The read latency (RL) is defined
from the last rising edge of the clock that completes a read command (Ex: the second rising edge of the CAS-2
command) to the rising edge of the clock from which the tDQSCK delay is measured. The first valid data is
available RL * tCK + tDQSCK + tDQSQ after the rising edge of Clock that completes a read command. The data
strobe output is driven tRPRE before the first valid rising strobe edge. The first data-bit of the burst is
synchronized with the first valid (i.e. post-preamble) rising edge of the data strobe. Each subsequent dataout
appears on each DQ pin, edge-aligned with the data strobe. At the end of a burst the DQS signals are driven for
another half cycle post-amble, or for a 1.5-cycle postamble if the programmable post-amble bit is set in the mode
register. The RL is programmed in the mode registers. Pin timings for the data strobe are measured relative to
the cross-point of DQS and .
Burst Read Timing
Notes:
1. BL=32 for column n, BL = 16 for column m, RL = 14, Preamble = Toggle, Postamble = 0.5nCK, DQ/DQS: VSSQ termination
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Burst Read followed by Burst Write or Burst Mask Write
Notes:
1. BL=16, Read Preamble = Toggle, Read Postamble = 0.5nCK, Write Preamble = 2nCK, Write Postamble = 0.5nCK, DQ/DQS: VSSQ
termination
2. Dout n = data-out from column n and Din n = data-in to column.n
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
The minimum time from a Burst Read command to a Write or MASK WRITE command is defined by the read
latency (RL) and the burst length (BL). Minimum READ-to-WRITE or MASK WRITE latency is
RL+RU(tDQSCK(max)/tCK)+BL/2+ RD(tRPST)-WL+tWPRE.
Seamless Burst Read
Notes:
1. BL=16, tCCD = 8, Preamble = Toggle, Postamble = 0.5nCK, DQ/DQS: VSSQ termination
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
The seamless Burst READ operation is supported by placing a READ command at every tCCD(Min) interval for
BL16 (or every 2 x tCCD(Min) for BL32). The seamless Burst READ can access any open bank.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Read Timing
Notes:
1. BL=16, Preamble = Toggling, Postamble = 0.5nCK
2. DQS, DQ and DMI terminated VSSQ
3. Output driver does not turn on before an end point of tLZ(DQS) and tLZ(DQ)
4. Output driver does not turn off before an end point of tHZ(DQS) and tHZ(DQ)
tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation
tHZ and tLZ transitions occur in the same time window as valid data transitions. These parameters are
referenced to a specific voltage level that specifies when the device output is no longer driving tHZ(DQS) and
tHZ(DQ), or begins driving tLZ(DQS), tLZ(DQ).
This section shows a method to calculate the point when the device is no longer driving tHZ(DQS) and tHZ(DQ),
or begins driving tLZ(DQS), tLZ(DQ), by measuring the signal at two different voltages. The actual voltage
measurement points are not critical as long as the calculation is consistent. The parameters tLZ(DQS), tLZ(DQ),
tHZ(DQS), and tHZ(DQ) are defined as single ended.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
tLZ(DQS) and tHZ(DQS) Calculation for ATE(Automatic Test Equipment)
CK- corssing at 2nd CAS-2 of Read Command
tLZ(DQS) method for calculating transitions and end point
Notes:
1. Conditions for Calibration: Pull Down Driver Ron = 40ohm, VOH = VDDQ/3
2. Termination condition for DQS and = 50ohm to VSSQ
3. The VOH level depends on MR22 OP[2:0] and MR3 OP[0] settings as well as device tolerances.
Use the actual VOH value for tHZ and tLZ measurements.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
CK- corssing at 2nd CAS-2 of Read Command
tHZ(DQS) method for calculating transitions and end point
Notes:
1. Conditions for Calibration: Pull Down Driver Ron = 40ohm, VOH = VDDQ/3
2. Termination condition for DQS and = 50ohm to VSSQ
3. The VOH level depends on MR22 OP[2:0] and MR3 OP[0] settings as well as device tolerances.
Use the actual VOH value for tHZ and tLZ measurements.
Reference Voltage for tLZ(DQS), tHZ(DQS) Timing Measurements
Measured Parameter
Symbol
tLZ(DQS)
tHZ(DQS)
Vsw1[V]
0.4 x VOH
0.4 x VOH
Vsw2[V]
0.6 x VOH
0.6 x VOH
Notes
low-impedance time from CK,
high impedance time from CK,
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
tLZ(DQ) and tHZ(DQ) Calculation for ATE(Automatic Test Equipment)
CK- corssing at 2nd CAS-2 of Read Command
tLZ(DQ) method for calculating transitions and end point
Notes:
1. Conditions for Calibration: Pull Down Driver Ron = 40ohm, VOH = VDDQ/3
2. Termination condition for DQS and DMI = 50ohm to VSSQ
3. The VOH level depends on MR22 OP[2:0] and MR3 OP[0] settings as well as device tolerances.
Use the actual VOH value for tHZ and tLZ measurements.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
CK- corssing at 2nd CAS-2 of Read Command
tHZ(DQ) method for calculating transitions and end point
Notes:
1. Conditions for Calibration: Pull Down Driver Ron = 40ohm, VOH = VDDQ/3
2. Termination condition for DQS and DMI = 50ohm to VSSQ
3. The VOH level depends on MR22 OP[2:0] and MR3 OP[0] settings as well as device tolerances.
Use the actual VOH value for tHZ and tLZ measurements.
Reference Voltage for tLZ(DQ), tHZ(DQ) Timing Measurements
Measured Parameter
Symbol
tLZ(DQ)
tHZ(DQ)
Vsw1[V]
0.4 x VOH
0.4 x VOH
Vsw2[V]
0.6 x VOH
0.6 x VOH
Notes
DQ Low-impedance time from CK,
DQ high impedance time from CK,
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
tRPRE Calculation for ATE(Automatic Test Equipment)
The method for calculating differential pulse widths for tRPRE is shown in figure below.
Method for calculating tRPRE transitions and endpoints
Notes:
1. Conditions for Calibration: Pull Down Driver Ron = 40ohm, VOH = VDDQ/3
2. Termination condition for DQS, , DQ and DMI = 50ohm to VSSQ
3. Preamble = Static
Method for calculating tRPRE transitions and endpoints
Notes:
1. Conditions for Calibration: Pull Down Driver Ron = 40ohm, VOH = VDDQ/3
2. Termination condition for DQS, , DQ and DMI = 50ohm to VSSQ
3. Preamble = Toggle
Reference Voltage for tRPRE Timing Measurements
Measured Parameter
Symbol
Vsw1[V]
Vsw2[V]
Notes
DQS, Differential Read Preamble
tRPRE
-(0.3 x VOH)
-(0.7 x VOH)
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
tRPST Calculation for ATE(Automatic Test Equipment)
The method for calculating differential pulse widths for tRPST is shown in figure below.
.
Method for calculating tRPST transitions and endpoints
Notes:
1. Conditions for Calibration: Pull Down Driver Ron = 40ohm, VOH = VDDQ/3
2. Termination condition for DQS, , DQ and DMI = 50ohm to VSSQ
3. Read Postamble: 0.5tCK
4. The method for calculating differential pulse widths for 1.5tCK Postamble is same as 0.5tCK Postamble.
Reference Voltage for tRPST Timing Measurements
Measured Parameter
Symbol
Vsw1[V]
Vsw2[V]
Notes
DQS, Differential Read Postamble
tRPST
-(0.7 x VOH)
-(0.3 x VOH)
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Read AC Timing
Parameter
Min/
Symbol
Data Rate
533/1066/1600/2133/2667/
Max
Unit
Read Timing
3200/3733/4267
READ preamble
tRPRE
tRPST
tRPST
Min
Min
Min
1.8
0.4
1.4
tCK(avg)
tCK(avg)
tCK(avg)
0.5 tCK READ postamble
1.5 tCK READ postamble
DQ low-impedance time from CK,
DQ high impedance time from CK,
tLZ(DQ)
Min
(RL x tCK) + tDQSCK(Min) - 200ps
ps
ps
(RL x tCK) + tDQSCK(Max) + tDQSQ(Max)
+ (BL/2 x tCK) - 100ps
tHZ(DQ) Max
tLZ(DQS) Min
(RL x tCK) + tDQSCK(Min)
- (tPRE(Max) x tCK) - 200ps
(RL x tCK) + tDQSCK(Max) + (BL/2 x tCK)
+ (RPST(Max) x tCK) - 100ps
0.18
low-impedance time from CK,
ps
high impedance time from CK, tHZ(DQS) Max
DQS-DQ skew tDQSQ Max
ps
UI
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
tDQSCK Timing Table
Parameter
Symbol
Min
Max
3.5
4
Unit Notes
DQS Output Access Time from CK/
tDQSCK
1.5
ns
1
2
3
DQS Output Access Time from CK/ - Temperature Variation tDQSCK_temp
DQS Output Access Time from CK/ - Voltage Variation tDQSCK_volt
Notes:
-
-
ps/°C
ps/mV
7
1. Includes DRAM process, voltage and temperature variation. It includes the AC noise impact for frequencies > 20 MHz and max voltage
of 45 mV pk-pk from DC-20 MHz at a fixed temperature on the package. The voltage supply noise must comply to the component
Min-Max DC Operating conditions.
2. tDQSCK_temp max delay variation as a function of Temperature.
3. tDQSCK_volt max delay variation as a function of DC voltage variation for VDDQ and VDD2. tDQSCK_volt should be used to calculate
timing variation due to VDDQ and VDD2 noise < 20 MHz. Host controller do not need to account for any variation due to VDDQ and VDD2
noise > 20 MHz. The voltage supply noise must comply to the component Min-Max DC Operating conditions. The voltage variation is
defined as the Max[abs{tDQSCKmin@V1- tDQSCKmax@V2}, abs{tDQSCKmax@V1-tDQSCKmin@V2}]/abs{V1-V2}. For tester
measurement VDDQ = VDD2 is assumed.
CK to DQS Rank to Rank variation
tDQSCK_rank2rank Timing Table
Min/
Parameter
Symbol
Data Rate
Max
Unit Notes
1600/1866/2133/2400/
3200/3733/4267
1.0
Read Timing
CK to DQS Rank to Rank variation
Notes:
1. The same voltage and temperature are applied to tDQS2CK_rank2rank.
tDQSCK_rank2rank
Max
ns
1,2
2. tDQSCK_rank2rank parameter is applied to multi-ranks per byte lane within a package consisting of the same design dies.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Write Preamble and Postamble
The DQS strobe for the LPDDR4-SDRAM requires a pre-amble prior to the first latching edge (the rising edge of
DQS with DATA "valid"), and it requires a post-amble after the last latching edge. The pre-amble and post-amble
lengths are set via mode register writes (MRW).
For WRITE operations, a 2*tCK pre-amble is required at all operating frequencies.
LPDDR4 will have a DQS Write post-amble of 0.5*tCK or extended to 1.5*tCK. Standard DQS post-amble will be
0.5*tCK driven by the memory controller for Writes. A mode register setting instructs the DRAM to drive an
additional (extended) one cycle DQS Write post-amble. The drawings below show examples of DQS Write
post-amble for both standard (tWPST) and extended (tWPSTE) post-amble operation.
DQS Write Preamble and Postamble: 0.5nCK Postamble
Notes:
1. BL = 16, Postamble = 0.5nCK
2. DQS and DQ terminated VSSQ
3. DQS/ is “don’t care” prior to the start of tWPRE
No transition of DQS is implied, as DQS/ can be HIGH, LOW or HI-Z prior to tWPRE
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
DQS Write Preamble and Postamble: 1.5nCK Postamble
Notes:
1. BL = 16, Postamble = 1.5nCK
2. DQS and DQ terminated VSSQ
3. DQS/ is “don’t care” prior to the start of tWPRE
No transition of DQS is implied, as DQS/ can be HIGH, LOW or HI-Z prior to tWPRE
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Burst Write Operation
A burst WRITE command is initiated with CS, and CA[5:0] asserted to the proper state at the rising edge of CK,
as defined by the Command Truth Table. Column addresses C[3:2] should be driven LOW for Burst WRITE
commands, and column addresses C[1:0] are not transmitted on the CA bus (and are assumed to be zero), so
that the starting column burst address is always aligned with a 32B boundary. The write latency (WL) is defined
from the last rising edge of the clock that completes a write command (Ex: the second rising edge of the CAS-2
command) to the rising edge of the clock from which tDQSS is measured. The first valid “latching” edge of DQS
must be driven WL * tCK + tDQSS after the rising edge of Clock that completes a write command.
The LPDDR4-SDRAM uses an un-matched DQS-DQ path for lower power, so the DQS-strobe must arrive at the
SDRAM ball prior to the DQ signal by the amount of tDQS2DQ. The DQS-strobe output is driven tWPRE before
the first valid rising strobe edge. The tWPRE pre-amble is required to be 2 x tCK. The DQS-strobe must be
trained to arrive at the DQ pad center-aligned with the DQ-data. The DQ-data must be held for tDIVW (data input
valid window) and the DQS must be periodically trained to stay centered in the tDIVW window to compensate for
timing changes due to temperature and voltage variation. Burst data is captured by the SDRAM on successive
edges of DQS until the 16 or 32 bit data burst is complete. The DQS-strobe must remain active (toggling) for
tWPST (WRITE post-amble) after the completion of the burst WRITE. After a burst WRITE operation, tWR must
be satisfied before a PRECHARGE command to the same bank can be issued. Pin input timings are measured
relative to the crosspoint of DQS and .
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Burst Write Operation
Notes:
1. BL = 16, Write Postamble = 0.5nCK, DQ/DQS: VSSQ termination
2. Din n = data-in to columnm n
3. The minimum number of clock cycles from the burst write command to burst read command for any bank is [WL +1 +BL/2 +
RU(tWR/tCK)]
4. tWR starts at the rising edge of CK after the last latching edge of DQS
5. DES commands are shown for ease of illustration; other commands may be valid at these times
Burst Write Followed by Burst Read
Notes:
1. BL = 16, Write Postamble = 0.5nCK, DQ/DQS: VSSQ termination
2. Din n = data-in to columnm n
3. The minimum number of clock cycles from the burst write command to burst read command for any bank is [WL +1 +BL/2 +
RU(tWTR/tCK)].
4. tWTR starts at the rising edge of CK after the last latching edge of DQS.
5. DES commands are shown for ease of illustration; other commands may be valid at these times.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Write Timing
Notes:
1. BL = 16, Write Postamble = 0.5nCK
2. Din n = data-in to columnm.n
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
tWPRE Calculation for ATE(Automatic Test Equipment)
The method for calculating differential pulse widths for tWPRE is shown in figure below.
Method for calculating tWPRE transitions and endpoints
Notes:
1. Termination condition for DQS, DQ and DMI = 50ohm to VSSQ.
Reference Voltage for tWPRE Timing Measurements
Measured Parameter
Symbol
Vsw1[V]
Vsw2[V]
Notes
DQS, differential WRITE Preamble
tWPRE
VIHL_AC x 0.3
VIHL_AC x 0.7
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
tWPST Calculation for ATE(Automatic Test Equipment)
The method for calculating differential pulse widths for tWPRE is shown in figure below.
Method for calculating tWPST transitions and endpoints
Notes:
1. Termination condition for DQS, DQ and DMI = 50ohm to VSSQ.
2. Wrtie Postamble: 0.5tCK
3. The method for calculating differential pulse widths for 1.5tCK Postamble is same as 0.5tCK Postamble.
Reference Voltage for tWPST Timing Measurements
Measured Parameter
Symbol
Vsw1[V]
Vsw2[V]
Notes
DQS, differential Write Postamble
tWPST
- (VIHL_AC x 0.7)
- (VIHL_AC x 0.3)
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Write AC Timing
Min/
Parameter
Symbol
Data Rate
Max
Unit
Notes
533/1066/1600/2133/
Write Timing
2667/3200/3733/4267
Min
Max
Min
Min
Min
Min
Min
Min
Min
0.75
1.25
0.4
0.4
0.2
0.2
1.8
0.4
1.4
Write command to 1st DQS latching transition
tDQSS
tCK(avg)
DQS input high-level width
DQS input low-level width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Write preamble
tDQSH
tDQSL
tDSS
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tDSH
tWPRE
tWPST
tWPST
0.5 tCK Write postamble
1
1
1.5 tCK Write postamble
Notes:
1. The length of Write Postamble depends on MR3 OP1 setting.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Read and Write Latencies
Read and Write Latencies for x16 mode
Read Latency Write Latency
Upper Clock Frequency
Lower Clock Frequency
Limit [MHz] (>)
nWR nRTP
No DBI
w/ DBI
Set A
Set B
Limit [MHz] ()
6
6
4
4
6
8
8
10
266
533
10
14
20
24
28
32
36
12
16
22
28
32
36
40
6
8
10
16
20
24
30
34
40
266
8
12
18
22
26
30
34
8
533
800
10
12
14
16
18
8
800
1066
1333
1600
1866
2133
10
12
14
16
1066
1333
1600
1866
Notes:
1. The LPDDR4 SDRAM device should not be operated at a frequency above the Upper Frequency Limit, or below the Lower Frequency
Limit, shown for each RL, WL, nRTP, or nWR value.
2. DBI for Read operations is enabled in MR3 OP[6]. When MR3 OP[6]=0, then the "No DBI" column should be used for Read Latency.
When MR3 OP[6]=1, then the "w/DBI" column should be used for Read Latency.
3. Write Latency Set "A" and Set "B" is determined by MR2 OP[6]. When MR2 OP[6]=0, then Write Latency Set "A" should be used.
When MR2 OP[6]=1, then Write Latency Set "B" should be used.
4. The programmed value of nWR is the number of clock cycles the LPDDR4 SDRAM device uses to determine the starting point of an
internal Precharge operation after a Write burst with AP (Auto Pre-charge). It is determined by RU(tWR/tCK).
5. The programmed value of nRTP is the number of clock cycles the LPDDR4 SDRAM device uses to determine the starting point of an
internal Precharge operation after a Read burst with AP (Auto-Pre-charge). It is determined by RU(tRTP/tCK).
6. nRTP shown in this table is valid for BL16 only. For BL32, the SDRAM will add 8 clocks to the nRTP value before starting a precharge.
7. Clock Frequency herewith is a reference base on JEDEC's. Precise tCK setting needs to follow where defined on speed compatible
table in section “Operating frequency”, exceptional setting please confirm with NTC.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Read and Write Latencies
Read and Write Latencies for Byte (x8) mode
Read Latency Write Latency
Upper Clock Frequency
Lower Clock Frequency
Limit [MHz] (>)
nWR nRTP
No DBI
w/ DBI
Set A
Set B
Limit [MHz] ()
6
6
4
4
6
8
8
10
266
533
10
16
22
26
32
36
40
12
18
24
30
36
40
44
6
8
12
16
22
28
32
38
44
266
8
12
18
22
26
30
34
8
533
800
10
12
14
16
18
8
800
1066
1333
1600
1866
2133
10
12
14
16
1066
1333
1600
1866
Notes:
1. The LPDDR4 SDRAM device should not be operated at a frequency above the Upper Frequency Limit, or below the Lower Frequency
Limit, shown for each RL, WL, nRTP, or nWR value.
2. DBI for Read operations is enabled in MR3 OP[6]. When MR3 OP[6]=0, then the "No DBI" column should be used for Read Latency.
When MR3 OP[6]=1, then the "w/DBI" column should be used for Read Latency.
3. Write Latency Set "A" and Set "B" is determined by MR2 OP[6]. When MR2 OP[6]=0, then Write Latency Set "A" should be used.
When MR2 OP[6]=1, then Write Latency Set "B" should be used.
4. The programmed value of nWR is the number of clock cycles the LPDDR4 SDRAM device uses to determine the starting point of an
internal Precharge operation after a Write burst with AP (Auto Pre-charge). It is determined by RU(tWR/tCK).
5. The programmed value of nRTP is the number of clock cycles the LPDDR4 SDRAM device uses to determine the starting point of an
internal Precharge operation after a Read burst with AP (Auto Pre-charge). It is determined by RU(tRTP/tCK).
6. nRTP shown in this table is valid for BL16 only. For BL32, the SDRAM will add 8 clocks to the nRTP value before starting a precharge.
7. Clock Frequency herewith is a reference base on JEDEC's. Precise tCK setting needs to follow where defined on speed compatible
table in section “Operating frequency”, exceptional setting please confirm with NTC.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Write and Masked Write operation DQS controls (WDQS Control)
LPDDR4-SDRAMs support write and masked write operations with the following DQS controls. Before and
after Write and Masked Write operations are issued, DQS/ is required to have a sufficient voltage
gap to make sure the write buffers operating normally without any risk of metastability.
The LPDDR4-SDRAM is supported by either of two WDQS control modes.
Mode 1: Read Based Control
Mode 2: WDQS_on / WDQS_off definition based control
Regardless of ODT enable/disable, WDQS related timing described in ‘WDQS Control’ does not allow any
change of existing command timing constraints for all read/write operations. In case of any conflict or ambiguity
on the command timing constraints caused by what is specified in ‘WDQS Control’, the specifications defined in
‘MPC’, ‘Timing Constraints for Training Commands’ should have higher priority than WDQS control
requirements.
Some legacy products may not provide WDQS control described below. However, in order to prevent the
write preamble related failure, it is strongly recommended to support either of two WDQS controls to
LPDDR4-SDRAMs. In the case of legacy SoC which may not provide WDQS control modes, it is required
to consult DRAM vendors to guarantee the write / masked write operation appropriately.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
WDQS Control Mode 1 - Read Based Control
controlled as described below. WDQS control requirements here can be ignored while differential read
DQS is operated or while DQS hands over from Read to Write and vice versa.
1.At the time a write / masked write command is issued, SoC makes the transition from driving
high to driving differential DQS/, followed by normal differential burst on DQS pins.
2.At the end of post amble of write /masked write burst, SoC resumes driving high through the
subsequent states except for DQS toggling and DQS turn around time of WT-RD and RD-WT as long
as CKE is high.
3.When CKE is low, the state of DQS and is allowed to be “Don’t Care”.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
WDQS Control Mode 2 - WDQS_on/off
After write / masked write command is issued, DQS and required to be differential from WDQS_on, and DQS
and can be “Don’t Care” status from WDQS_off of write / masked write
command. When ODT is enabled, WDQS_on and WDQS_off timing is located in the middle of the
operations. When host disables ODT, WDQS_on and WDQS_off constraints conflict with tRTW. The timing
does not conflict when ODT is enabled because WDQS_on and WDQS_off timing is covered in ODTLon
and ODTLoff. However, regardless of ODT on/off, WDQS_on/off timing below does not change any
command timing constraints for all read and write operations. In order to prevent the conflict, WDQS_on/off
requirement can be ignored when WDQS_on/off timing is overlapped with read operation period including
Read burst period and tRPST or overlapped with turn-around time (RD-WT or WT-RD). In addition, the
period during DQS toggling caused by Read and Write can be counted as WDQS_on/off.
Parameters
• WDQS_on: the max delay from write / masked write command to differential DQS and .
• WDQS_off : the min delay for DQS and differential input after the last write / masked write
command.
• WDQS_Exception : the period where WDQS_on and WDQS_off timing is overlapped with read
operation or with DQS turn around (RD-WT, WT-RD).
- WDQS_Exception @ ODT disable = max (WL-WDQS_on+tDQSTA- tWPRE - n*tCK, 0 tCK)
where RD to WT command gap = tRTW(min)@ODT disable + n*tCK
- WDQS_Exception @ ODT enable = tDQSTA
WDQS_on / WDQS_off Definition
WDQS_on
(max)
WDQS_off
(min)
Write Latency
Lower Clock Frequency Upper Clock Frequency
nWR
nRTP
Limit [MHz] (>)
Limit [MHz] ()
Set A
Set B
Set A
Set B Set A
15
18
Set B
15
4
4
6
12
16
20
24
30
34
40
nCK
8
8
0
0
10
266
533
6
8
8
12
18
22
26
30
34
nCK
0
0
0
20
25
266
8
6
12
14
18
20
24
nCK
21
24
533
800
10
8
4
32
800
1066
1333
1600
1866
2133
MHz
12
10
12
14
16
nCK
4
27
37
1066
1333
1600
1866
MHz
14
6
30
42
16
6
33
47
18
8
36
52
nCK
Notes:
nCK
nCK
nCK
1. WDQS_on/off requirement can be ignored when WDQS_on/off timing is overlapped with read operation period including Read burst
period and tRPST or overlapped with turn-around time (RD-WT or WT-RD).
2. The period during which DQS is toggling because of a Read or Write can be counted as part of the WDQS_on/off requirement.
3. Clock Frequency herewith is a reference base on JEDEC's. Precise tCK setting needs to follow where defined on speed compatible
table in section “Operating frequency”, exceptional setting please confirm with NTC.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
WDQS_on / WDQS_off Allowable Variation Range
Min Max
-0.25 0.25
-0.25 0.25
Unit
WDQS_On
WDQS_Off
tCK(avg)
tCK(avg)
Burst Write Operation
Burst Write Operation
Notes:
1. BL=16, Write Postamble = 0.5nCK, DQ/DQS: VSSQ termination
2. Din n = data-in to columnm n
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
4. DRAM RTT is only applied when ODT is enabled (MR11 OP[2:0] is not 000B)
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Burst Read followed by Burst Write or Burst Mask Write (ODT Disable)
Notes:
1. BL=16, Read Preamble = Toggle, Read Postamble = 0.5nCK, Write Preamble = 2nCK, Write Postamble = 0.5nCK
2. Dout n = data-out from column n and Din n = data-in to columnm n
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
4. WDQS_on and WDQS_off requirement can be ignored where WDQS_on/off timing is overlapped with read operation period
including Read burst period and tRPST or overlapped with turn-around time (RD-WT or WT-RD)
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Burst Read followed by Burst Write or Burst Mask Write (ODT Enable)
Notes:
1. BL=16, Read Preamble = Toggle, Read Postamble = 0.5nCK, Write Preamble = 2nCK, Write Postamble = 0.5nCK, DQ/DQS: VSSQ
termination
2. Dout n = data-out from column n and Din n = data-in to columnm n
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
4. WDQS_on and WDQS_off requirement can be ignored where WDQS_on/off timing is overlapped with read operation period
including Read burst period and tRPST or overlapped with turn-around time (RD-WT or WT-RD)
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Postamble and Preamble merging behavior
The DQS strobe for the device requires a preamble prior to the first latching edge (the rising edge of DQS with
data valid), and it requires a postamble after the last latching edge. The preamble and postamble options are set
via Mode Register Write commands.
In Read to Read or Write to Write operations with tCCD=BL/2, postamble for 1st command and preamble for 2nd
command will disappear to create consecutive DQS latching edge for seamless burst operations. But in the case
of Read to Read or Write to Write operations with command interval of tCCD+1,tCCD+2, etc., they will not
completely disappear because it’s not seamless burst operations.
Timing diagrams in this material describe Postamble and Preamble merging behavior in Read to Read or Write
to Write operations with tCCD+n.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Read to Read Operation
Seamless Reads Operation: tCCD = Min, Preamble = Toggle, 1.5nCK Postamble
Notes:
1. BL = 16 for column n and column m, RL = 6, Preamble = Toggle, Postamble = 1.5nCK2. Dout n = data-out from column n and Din n =
data-in to columnm n
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
Consecutive Reads Operation: tCCD = Min +1, Preamble = Toggle, 1.5nCK Postamble
Notes:
1. BL = 16 for column n and column m, RL = 6, Preamble = Toggle, Postamble = 1.5nCK
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Consecutive Reads Operation: tCCD = Min +1, Preamble = Toggle, 0.5nCK Postamble
Notes:
1. BL = 16 for column n and column m, RL = 6, Preamble = Toggle, Postamble = 0.5nCK
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
Consecutive Reads Operation: tCCD = Min +1, Preamble = Static, 1.5nCK Postamble
Notes:
1. BL = 16 for column n and column m, RL = 6, Preamble = Static, Postamble = 1.5nCK
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
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4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Consecutive Reads Operation: tCCD = Min +1, Preamble = Static, 0.5nCK Postamble
Notes:
1. BL = 16 for column n and column m, RL = 6, Preamble = Static, Postamble = 0.5nCK
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
Consecutive Reads Operation: tCCD = Min +2, Preamble = Toggle, 1.5nCK Postamble
Notes:
1. BL = 16 for column n and column m, RL = 6, Preamble = Toggle, Postamble = 1.5nCK
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Consecutive Reads Operation: tCCD = Min +2, Preamble = Toggle, 0.5nCK Postamble
Notes:
1. BL = 16 for column n and column m, RL = 6, Preamble = Toggle, Postamble = 0.5nCK
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
Consecutive Reads Operation: tCCD = Min +2, Preamble = Static, 1.5nCK Postamble
Notes:
1. BL = 16 for column n and column m, RL = 6, Preamble = Static, Postamble = 1.5nCK
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Consecutive Reads Operation: tCCD = Min +2, Preamble = Static, 0.5nCK Postamble
Notes:
1. BL = 16 for column n and column m, RL = 6, Preamble = Static, Postamble = 0.5nCK
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
Consecutive Reads Operation: tCCD = Min +3, Preamble = Toggle, 1.5nCK Postamble
Notes:
1. BL = 16 for column n and column m, RL = 6, Preamble = Toggle, Postamble = 1.5nCK
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Consecutive Reads Operation: tCCD = Min +3, Preamble = Toggle, 0.5nCK Postamble
Notes:
1. BL = 16 for column n and column m, RL = 6, Preamble = Toggle, Postamble = 0.5nCK
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
Consecutive Reads Operation: tCCD = Min +3, Preamble = Static, 1.5nCK Postamble
Notes:
1. BL = 16 for column n and column m, RL = 6, Preamble = Static, Postamble = 1.5nCK
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Consecutive Reads Operation: tCCD = Min +3, Preamble = Static, 0.5nCK Postamble
Notes:
1. BL = 16 for column n and column m, RL = 6, Preamble = Static, Postamble = 0.5nCK
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Write to Write Operation
Seamless Writes Operation: tCCD = Min, 0.5nCK Postamble
Notes:
1. BL=16, Write Postamble = 0.5nCK
2. Dout n/m = data-in to column n and column m.
3. The minimum number of clock cycles from the burst write command to the burst write command for any bank is BL/2
4. DES commands are shown for ease of illustration; other commands may be valid at these times.
Seamless Writes Operation: tCCD = Min, 1.5nCK Postamble, 533MHz < Clock Freq. 800MHz,
ODT Worst Timing Case
Notes:
1. Clock Frequency = 800MHz, tCK(AVG) = 1.25ns
2. BL=16, Write Postamble = 1.5nCK
3. Dout n/m = data-in to column n and column m.
4. The minimum number of clock cycles from the burst write command to the burst write command for any bank is BL/2
5. DES commands are shown for ease of illustration; other commands may be valid at these times.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Seamless Writes Operation: tCCD = Min, 1.5nCK Postamble
Notes:
1. BL=16, Write Postamble = 1.5nCK
2. Dout n/m = data-in to column n and column m.
3. The minimum number of clock cycles from the burst write command to the burst write command for any bank is BL/2
4. DES commands are shown for ease of illustration; other commands may be valid at these times.
Consecutive Writes Operation: tCCD = Min + 1, 0.5nCK Postamble
Notes:
1. BL=16, Write Postamble = 0.5nCK
2. Dout n/m = data-in to column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Consecutive Writes Operation: tCCD = Min + 1, 1.5nCK Postamble
Notes:
1. BL=16, Write Postamble = 1.5nCK
2. Dout n/m = data-in to column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
Consecutive Writes Operation: tCCD = Min + 2, 0.5nCK Postamble
Notes:
1. BL=16, Write Postamble = 0.5nCK
2. Dout n/m = data-in to column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Consecutive Writes Operation: tCCD = Min + 2, 1.5nCK Postamble
Notes:
1. BL=16, Write Postamble = 1.5nCK
2. Dout n/m = data-in to column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
Consecutive Writes Operation: tCCD = Min + 3, 0.5nCK Postamble
Notes:
1. BL=16, Write Postamble = 0.5nCK
2. Dout n/m = data-in to column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Consecutive Writes Operation: tCCD = Min + 3, 1.5nCK Postamble
Notes:
1. BL=16, Write Postamble = 1.5nCK
2. Dout n/m = data-in to column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
Consecutive Writes Operation: tCCD = Min + 4, 1.5nCK Postamble
Notes:
1. BL=16, Write Postamble = 1.5nCK
2. Dout n/m = data-in to column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
MASKED WRITE OPERATION
The LPDDR4-SDRAM requires that Write operations which include a byte mask anywhere in the burst sequence
must use the Masked Write command. This allows the DRAM to implement efficient data protection schemes
based on larger data blocks. The Masked Write-1 command is used to begin the operation, followed by a CAS-2
command. A Masked Write command to the same bank cannot be issued until tCCDMW later, to allow the
LPDDR4-SDRAM to finish the internal Read-Modify-Write. One Data Mask-Invert (DMI) pin is provided per byte
lane, and the Data Mask-Invert timings match data bit (DQ) timing. See the section on "Data Mask Invert" for
more information on the use of the DMI signal.
Masked Write Command - Same Bank
Notes:
1. BL=16, Write Postamble = 0.5nCK, DQ/DQS: VSSQ termination
2. Din n = data-in to columnm n
3. Mask-Write supports only BL16 operations. For BL32 configuration, the system needs to insert only 16 bit wide data for masked write
operation.
4. DES commands are shown for ease of illustration; other commands may be valid at these times.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Masked Write Command - Different Bank
Notes:
1. BL=16, DQ/DQS/DMI: VSSQ termination
2. Din n = data-in to columnm n
3. Mask-Write supports only BL16 operations. For BL32 configuration, the system needs to insert only 16 bit wide data for masked write
operation.
4. DES commands are shown for ease of illustration; other commands may be valid at these times.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Masked Write Timing constraints for BL16
Timing constraints for Same bank: DQ ODT is Disabled
Next CMD
Current CMD
Active
Read
Write
(BL=16 or 32)
Active
illegal
illegal
Masked Write
Precharge
(BL=16 or 32)
RU(tRCD/tCK)
RU(tRCD/tCK)
RU(tRCD/tCK)
RU(tRAS/tCK)
BL/2+
Read with
BL = 16
RL+RU(tDQSCK(max)/tCK)
RL+RU(tDQSCK(max)/tCK)
81
+BL/2-WL+tWPRE+RD(tRPST) +BL/2-WL+tWPRE+RD(tRPST) max{(8,RU(tRTP/tCK)}-8
RL+RU(tDQSCK(max)/tCK) RL+RU(tDQSCK(max)/tCK) BL/2+
Read with
BL = 32
illegal
illegal
illegal
illegal
162
+BL/2-WL+tWPRE+RD(tRPST) +BL/2-WL+tWPRE+RD(tRPST) max{(8,RU(tRTP/tCK)}-8
WL+ 1 +
Write with
BL = 16
WL+1+BL/2
+RU(tWTR/tCK)
WL+1+BL/2
81
tCCDMW3
tCCDMW + 84
tCCDMW3
illegal
BL/2+RU(tWR/tCK)
WL+ 1 +
Write with
BL = 32
162
+RU(tWTR/tCK)
WL+1+BL/2
BL/2+RU(tWR/tCK)
WL+ 1 +
Masked Write
tCCD
illegal
+RU(tWTR/tCK)
BL/2+RU(tWR/tCK)
RU(tRP/tCK),
Precharge
Notes:
illegal
4
RU(tRPab/tCK)
1. In the case of BL = 16, tCCD is 8*tCK.
2. In the case of BL = 32, tCCD is 16*tCK.
3. tCCDMW = 32*tCK (4*tCCD at BL=16)
4. Write with BL=32 operation has 8*tCK longer than BL =16.
5. tRPST values depend on MR1-OP[7] respectively.
Timing constraints for Same bank: DQ ODT is Enabled
Next CMD
Read
Write
Active
Masked Write
Precharge
(BL=16 or 32)
(BL=16 or 32)
Current CMD
RL+RU(tDQSCK(max)/tCK) RL+RU(tDQSCK(max)/tCK)
+BL/2+RD(tRPST)-ODTLon +BL/2+RD(tRPST)-ODTLon
-RD(tODTon,min/tCK)+1 -RD(tODTon,min/tCK)+1
RL+RU(tDQSCK(max)/tCK) RL+RU(tDQSCK(max)/tCK)
+BL/2+RD(tRPST)-ODTLon +BL/2+RD(tRPST)-ODTLon
-RD(tODTon,min/tCK)+1 -RD(tODTon,min/tCK)+1
Read with
BL = 16
BL/2+
illegal
81
max{(8,RU(tRTP/tCK)}-8
Read with
BL = 32
BL/2+
illegal
162
max{(8,RU(tRTP/tCK)}-8
Notes:
1. In the case of BL = 16, tCCD is 8*tCK.
2. In the case of BL = 32, tCCD is 16*tCK.
3. The rest of the timing is same as DQ ODT is Disable case.
4. tRPST values depend on MR1-OP[7] respectively.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Timing constraints for Different bank: DQ ODT is Disabled
Next CMD
Current CMD
Active
Read
(BL=16 or 32)
4
Write
Active
RU(tRRD/tCK)
4
Masked Write
Precharge
(BL=16 or 32)
4
4
4
4
Read with
BL = 16
RL+RU(tDQSCK(max)/tCK)
+BL/2-WL+tWPRE+RD(tRPST)
RL+RU(tDQSCK(max)/tCK)
+BL/2-WL+tWPRE+RD(tRPST)
RL+RU(tDQSCK(max)/tCK)
+BL/2-WL+tWPRE+RD(tRPST)
RL+RU(tDQSCK(max)/tCK)
+BL/2-WL+tWPRE+RD(tRPST)
81
Read with
BL = 32
4
4
4
162
4
4
4
Write with
BL = 16
WL+1+BL/2
+RU(tWTR/tCK)
WL+1+BL/2
+RU(tWTR/tCK)
WL+1+BL/2
+RU(tWTR/tCK)
4
81
81
Write with
BL = 32
162
162
Masked Write
4
4
81
4
81
4
4
4
Precharge
Notes:
1. In the case of BL = 16, tCCD is 8*tCK.
2. In the case of BL = 32, tCCD is 16*tCK.
3. tRPST values depend MR1-OP[7] respectively
Timing constraints for Different bank: DQ ODT is Enabled
Next CMD
Read
Write
Active
Masked Write
Precharge
(BL=16 or 32)
(BL=16 or 32)
Current CMD
RL+RU(tDQSCK(max)/tCK)+BL/2 RL+RU(tDQSCK(max)/tCK)+BL/2
Read with
BL = 16
4
81
+RD(tRPST)-ODTLon
+RD(tRPST)-ODTLon
2
-RD(tODTon,min/tCK)+1
-RD(tODTon,min/tCK)+1
RL+RU(tDQSCK(max)/tCK)+BL/2 RL+RU(tDQSCK(max)/tCK)+BL/2
Read with
BL = 32
4
162
+RD(tRPST)-ODTLon
+RD(tRPST)-ODTLon
2
-RD(tODTon,min/tCK)+1
-RD(tODTon,min/tCK)+1
Notes:
1. In the case of BL = 16, tCCD is 8*tCK.
2. In the case of BL = 32, tCCD is 16*tCK.
3. The rest of the timing is same as DQ ODT is Disable case.
4. tRPST values depend MR1-OP[7] respectively
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
LPDDR4 Data Mask (DM) and Data Bus Inversion (DBIdc) Function
LPDDR4 SDRAM supports the function of Data Mask and Data Bus inversion. Details are shown below:
• LPDDR4 device supports Data Mask (DM) function for Write operation.
• LPDDR4 device supports Data Bus Inversion (DBIdc) function for Write and Read operation.
• LPDDR4 supports DM and DBIdc function with a byte granularity.
• DBIdc function during Write or Masked Write can be enabled or disabled through MR3 OP[7].
• DBIdc function during Read can be enabled or disabled through MR3 OP[6].
• DM function during Masked Write can be enabled or disabled through MR13 OP[5].
• LPDDR4 device has one Data Mask Inversion (DMI) signal pin per byte; total of 2 DMI signals per channel.
• DMI signal is a bi-directional DDR signal and is sampled along with the DQ signals for Read and Write or
Masked Write operation.
There are eight possible combinations for LPDDR4 device with DM and DBIdc function.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Function Behavior of DMI Signal During Write, Masked Write and Read Operation
Signal
during DMI Signal
Masked
Write
Command
DMI Signal
during DMI Signal
MPC DQ
Read
Training
DMI Signal
Read DBIdc during
DMI Signal DMI Signal
Write
DBIdc
Function
DM
Function
during
during
During
Read
During
MRR
Function
Write
Command
MPC WR MPC RD
FIFO
FIFO
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Notes:
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Disable
Enable
Enable
Disable
Disable
Enable
Enable
Notes: 1 Notes: 1, 3 Notes: 2
Notes: 4 Notes: 3 Notes: 2
Notes: 1 Notes: 3 Notes: 5
Notes: 4 Notes: 3 Notes: 5
Notes: 6 Notes: 7 Notes: 2
Notes: 4 Notes: 8 Notes: 2
Notes: 6 Notes: 7 Notes: 5
Notes: 4 Notes: 8 Notes: 5
Note: 1
Note: 9
Note: 9
Note: 9
Note: 9
Note: 9
Note: 9
Note: 9
Note: 2
Note: 2
Notes: 2
Note: 10 Note: 11 Notes: 2
Note: 10 Note: 11 Notes: 12
Note: 10 Note: 11 Notes: 12
Note: 10 Note: 11 Notes: 2
Note: 10 Note: 11 Notes: 2
Note: 10 Note: 11 Notes: 12
Note: 10 Note: 11 Notes: 12
1. DMI input signal is a don't care. DMI input receivers are turned OFF.
2. DMI output drivers are turned OFF.
3. Masked Write Command is not allowed and is considered an illegal command as DM function is disabled.
4. DMI signal is treated as DBI signal and it indicates whether DRAM needs to invert the Write data received on DQs within a byte. The
LPDDR4 device inverts Write data received on the DQ inputs in case DMI was sampled HIGH, or leaves the Write data non-inverted in
case DMI was sampled LOW.
5. The LPDDR4 DRAM inverts Read data on its DQ outputs associated within a byte and drives DMI signal HIGH when the number of ‘1’
data bits within a given byte lane is greater than four; otherwise the DRAM does not invert the read data and drives DMI signal LOW.
6. The LPDDR4 DRAM does not perform any mask operation when it receives Write command. During the Write burst associated with
Write command, DMI signal must be driven LOW.
7. The LPDDR4 DRAM requires an explicit Masked Write command for all masked write operations. DMI signal is treated as DM signal
and it indicates which bit time within the burst is to be masked. When DMI signal is HIGH, DRAM masks that bit time across all DQs
associated within a byte. All DQ input signals within a byte are don't care (either HIGH or LOW) when DMI signal is HIGH. When DMI
signal is LOW, the LPDDR4 DRAM does not perform mask operation and data received on DQ input is written to the array.
8. The LPDDR4 DRAM requires an explicit Masked Write command for all masked write operations. The LPDDR4 device masks the Write
data received on the DQ inputs if the total count of '1' data bits on DQ[2:7] or DQ[10:15] (for Lower Byte or Upper Byte respectively)
is equal to or greater than five and DMI signal is LOW. Otherwise the LPDDR4 DRAM does not perform mask operation and treats it as
a legal DBI pattern; DMI signal is treated as DBI signal and data received on DQ input is written to the array.
9. DMI signal is treated as a training pattern. The LPDDR4 DRAM does not perform any mask operation and does not invert Write data
received on the DQ inputs.
10. DMI signal is treated as a training pattern. The LPDDR4 DRAM returns DMI pattern written in WR FIFO.
11. DMI signal is treated as a training pattern. For more details, see ‘RD DQ Calibration’.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
12. DBI may apply or may not apply during normal MRR. It's vendor specific.
If read DBI is enable with MRS and vendor cannot support the DBI during MRR, DBI pin status should be low.
If read DBI is enable with MRS and vendor can support the DBI during MRR, the LPDDR4 DRAM inverts Mode Register Read data on
its DQ outputs associated within a byte and drives DMI signal HIGH when the number of ‘1’ data bits within a given byte lane is
greater than four; otherwise the DRAM does not invert the read data and drives DMI signal LOW.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Masked Write Command w/ Write DBI Enabled; DM Enabled
Notes:
1. Data Mask (DM) is Enable: MR13 OP [5] = 0, Data BUS Inversion (DBI) Write is Enable: MR3 OP[7] = 1
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4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Write Command w/ Write DBI Enabled; DM Enabled
Notes:
1. Data Mask (DM) is Disable: MR13 OP [5] = 1, Data BUS Inversion (DBI) Write is Enable: MR3 OP[7] = 1
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Pre-Charge Operation
The PRECHARGE command is used to precharge or close a bank that has been activated. The PRECHARGE
command is initiated with CS, and CA[5:0] in the proper state as defined by the Command Truth Table.
The PRECHARGE command can be used to precharge each bank independently or all banks simultaneously.
The AB flag and the bank address bit are used to determine which bank(s) to precharge. The precharged bank(s)
will be available for subsequent row access tRPab after an all-bank PRECHARGE command is issued, or tRPpb
after a single-bank PRECHARGE command is issued.
To ensure that LPDDR4 devices can meet the instantaneous current demands, the row-precharge time for an
all-bank PRECHARGE (tRPab) is longer than the perbank precharge time (tRPpb).
Precharge Bank Selection
AB
BA2
BA1
BA0
Precharged
Bank(s)
(CA[5], R1)
(CA[2], R2)
(CA[1], R2)
(CA[0], R2)
0
0
0
0
0
0
0
0
1
0
0
0
Bank 0 only
Bank 1 only
Bank 2 only
Bank 3 only
Bank 4 only
Bank 5 only
Bank 6 only
Bank 7 only
All Banks
0
0
1
0
1
0
0
1
1
1
1
0
0
0
1
1
1
0
1
1
1
Valid
Valid
Valid
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Burst Read Operation Followed by a PRECHARGE
The PRECHARGE command can be issued as early as BL/2 clock cycles after a READ command, but
PRECHARGE cannot be issued until after tRAS is satisfied. A new bank ACTIVATE command can be issued to
the same bank after the row PRECHARGE time (tRP) has elapsed. The minimum READ-to-PRECHARGE time
must also satisfy a minimum analog time from the 2nd rising clock edge of the CAS-2 command. tRTP begins
BL/2 - 8 clock cycles after the READ command. For LPDDR4 READ-to-PRECHARGE timings see table below.
Burst READ followed by PRECHARGE (Shown with BL16, 2tCK pre-amble)
Burst READ followed by PRECHARGE (Shown with BL32, 2tCK pre-amble)
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8Gb: NT6AN256T32AV
Burst WRITE Followed by PRECHARGE
A Write Recovery time (tWR) must be provided before a PRECHARGE command may be issued. This delay is
referenced from the next rising edge of CK after the last latching DQS clock of the burst.
LPDDR4-SDRAM devices write data to the memory array in prefetch multiples (prefetch=16). An internal WRITE
operation can only begin after a prefetch group has been clocked, so tWR starts at the prefetch boundaries. The
minimum WRITE-to-PRECHARGE time for commands to the same bank is WL + BL/2 + 1 + RU(tWR/tCK) clock
cycles.
Burst WRITE Followed by PRECHARGE (Shown with BL16, 2tCK pre-amble)
Auto-PRECHARGE Operation
Before a new row can be opened in an active bank, the active bank must be precharged using either the
PRECHARGE command or the Auto-PRECHARGE function. When a READ, a WRITE or Masked Write
command is issued to the device, the AP bit (CA5) can be set to enable the active bank to automatically begin
precharge at the earliest possible moment during the burst READ, WRITE or Masked Write cycle.
If AP is LOW when the READ or WRITE command is issued, then the normal READ, WRITE or Masked Write
burst operation is executed and the bank remains active at the completion of the burst.
If AP is HIGH when the READ, WRITE or Masked Write command is issued, the Auto-PRECHARGE function is
engaged. This feature enables the PRECHARGE operation to be partially or completely hidden during burst
READ cycles (dependent upon READ or WRITE latency), thus improving system performance for random data
access.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Burst READ with Auto-PRECHARGE
If AP is HIGH when a READ command is issued, the READ with Auto-PRECHARGE function is engaged. An
internal precharge procedure starts a following delay time after the READ command. And this delay time
depends on BL setting.
BL = 16: nRTP
BL = 32: 8nCK + nRTP
For LPDDR4 Auto-PRECHARGE calculations. Following an Auto-PRECHARGE operation, an ACTIVATE
command can be issued to the same bank if the following two conditions are both satisfied:
a. The RAS precharge time (tRP) has been satisfied from the clock at which the Auto-PRECHARGE began,
or
b. The RAS cycle time (tRC) from the previous bank activation has been satisfied.
Burst READ with Auto-PRECHARGE (Shown with BL16, 2tCK pre-amble)
Burst READ with Auto-PRECHARGE (Shown with BL32, 2tCK pre-amble)
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Burst WRITE with Auto-PRECHARGE
If AP is HIGH when a WRITE command is issued, the WRITE with Auto-PRECHARGE function is engaged. The
device starts an Auto-PRECHARGE on the rising edge tWR cycles after the completion of the Burst WRITE.
Following a WRITE with Auto-PRECHARGE, an ACTIVATE command can be issued to the same bank if the
following conditions are met:
a. The RAS precharge time (tRP) has been satisfied from the clock at which the Auto-PRECHARGE began,
and
b. The RAS cycle time (tRC) from the previous bank activation has been satisfied.
Burst WRITE with Auto-PRECHARGE (Shown with BL16, 2tCK pre-amble)
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Auto-Precharge Operation
Before a new row can be opened in an active bank, the active bank must be precharged using either the
PRECHARGE command or the Auto-Precharge function. When a READ, a WRITE or Masked Write
command is issued to the device, the AP bit (CA5) can be set to enable the active bank to automatically
begin precharge at the earliest possible moment during the burst READ, WRITE or Masked Write cycle.
If AP is LOW when the READ or WRITE command is issued, then the normal READ, WRITE or Masked
Write burst operation is executed and the bank remains active at the completion of the burst.
If AP is HIGH when the READ, WRITE or Masked Write command is issued, the Auto-Precharge function
is engaged. This feature enables the PRECHARGE operation to be partially or completely hidden during
burst READ cycles (dependent upon READ or WRITE latency), thus improving system performance for
random data access.
Read with Auto-Precharge or Write/Mask Write with Auto-Precharge commands may be issued after tRCD
has been satisfied. The LPDDR4 SDRAM RAS Lockout feature will schedule the internal precharge to
assure that tRAS is satisfied.
tRC needs to be satisfied prior to issuing subsequent Activate commands to the same bank.
The following figure shows example of RAS lock function.
Command Input Timing with RAS lock
Notes:
1. tCK(AVG) = 0.938ns, Data Rate = 2133Mbps, tRCD(Min) = Max(18ns, 4nCK), tRAS(Min) = Max(42ns, 3nCK), nRTP = 8nCK, BL = 32
2. tRCD = 20nCK comes from Roundup(18ns/0.938ns)
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Delay time from Write to Read with Auto-Precharge
In the case of write command followed by read with Auto-Precharge, controller must satisfy tWR for the
write command before initiating the DRAM internal Auto-Precharge. It means that (tWTR + nRTP) should
be equal or longer than (tWR) when BL setting is 16, as well as (tWTR + nRTP +8nCK) should be equal or
longer than (tWR) when BL setting is 32. Refer to the following figure for details.
Delay time from Write to Read with Auto-Precharge
Notes:
1. Burst Length at Read = 16
2. DES commands are shown for ease of illustration; other commands may be valid at these times.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Timing Between Commands (PRECHARGE and Auto-PRECHARGE): DQ ODT is Disable
From
Minimum Delay between "From Command"
and "To Command"
To Command
Unit
Notes
Command
PRECHARGE
(to same bank as Read)
PRECHARGE All
tRTP
tRTP
tCK
tCK
tCK
tCK
tCK
tCK
tCK
1,6
1,6
READ
BL=16
PRECHARGE
8tCK + tRTP
8tCK + tRTP
nRTP
1,6
READ
(to same bank as Read)
PRECHARGE All
BL=32
1,6
PRECHARGE
1,10
1,10
1,8,10
(to same bank as READ w/AP)
PRECHARGE All
nRTP
Activate
nRTP + tRPpb
(to same bank as READ w/AP)
WRITE or WRITE w/AP
(same bank)
Illegal
Illegal
-
MASK-WR or MASK-WR w/AP
(same bank)
READ w/AP
BL=16
-
WRITE or WRITE w/AP
(different bank)
RL+RU(tDQSCK(max)/tCK)+BL/2+
RD(tRPST)-WL+tWPRE
tCK
tCK
-
3,4,5
3,4,5
MASK-WR or MASK-WR w/AP
(different bank)
RL+RU(tDQSCK(max)/tCK)+BL/2+
RD(tRPST)-WL+tWPRE
READ or READ w/AP
(same bank)
Illegal
BL/2
READ or READ w/AP
(different bank)
tCK
3
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Timing Between Commands (PRECHARGE and Auto-PRECHARGE): DQ ODT is Disable (cont’d)
From
Minimum Delay between "From Command"
and "To Command"
To Command
Unit
Notes
Command
PRECHARGE
(to same bank as READ w/AP)
PRECHARGE All
8tCK + nRTP
8tCK + nRTP
tCK
tCK
tCK
1,10
1,10
Activate
8tCK + nRTP +tRPpb
1,8,10
(to same bank as READ w/AP)
WRITE or WRITE w/AP
(same bank)
Illegal
Illegal
-
-
MASK-WR or MASK-WR w/AP
(same bank)
READ w/AP
BL=32
WRITE or WRITE w/AP
(different bank)
RL+RU(tDQSCK(max)/tCK)+BL/2+RD(tRPST)-WL+tWPRE tCK
RL+RU(tDQSCK(max)/tCK)+BL/2+RD(tRPST)-WL+tWPRE tCK
3,4,5
3,4,5
MASK-WR or MASK-WR w/AP
(different bank)
READ or READ w/AP
(same bank)
Illegal
BL/2
-
READ or READ w/AP
(different bank)
tCK
3
PRECHARGE
WL + BL/2 + tWR + 1
WL + BL/2 + tWR + 1
WL + BL/2 + tWR + 1
WL + BL/2 + tWR + 1
tCK
tCK
tCK
tCK
1,7
1,7
1,7
1,7
WRITE
(to same bank as WRITE)
PRECHARGE All
BL=16 & 32
PRECHARGE
MASK-WR
BL=16
(to same bank as MASK-WR)
PRECHARGE All
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Timing Between Commands (PRECHARGE and Auto-PRECHARGE): DQ ODT is Disable (cont’d)
From
Minimum Delay between "From Command"
and "To Command"
To Command
Unit
Notes
Command
PRECHARGE
(to same bank as WRITE w/AP)
PRECHARGE All
WL + BL/2 + nWR + 1
WL + BL/2 + nWR + 1
tCK
tCK
tCK
1,11
1,11
ACTIVATE
WL + BL/2 +nWR + 1 + tRPpb
1,8,11
(to same bank as WRITE w/AP)
WRITE or WRITE w/AP
(same bank)
Illegal
-
WRITE w/AP
BL=16 & 32
READ or READ w/AP
(same bank)
Illegal
BL/2
-
WRITE or WRITE w/AP
(different bank)
tCK
tCK
tCK
3
3
MASK-WR or MASK-WR w/AP
(different bank)
BL/2
READ or READ w/AP
(different bank)
WL + BL/2 + tWTR + 1
3,9
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Timing Between Commands (PRECHARGE and Auto-PRECHARGE): DQ ODT is Disable (cont’d)
From
Minimum Delay between "From Command"
and "To Command"
To Command
Unit
Notes
Command
PRECHARGE
(to same bank as MASK-WR
w/AP)
WL + BL/2 + nWR + 1
WL + BL/2 +nWR + 1
tCK
tCK
tCK
1,11
1,11
PRECHARGE All
ACTIVATE
(to same bank as MASK-WR
w/AP)
WL + BL/2 + nWR + 1 + tRPpb
1,8,11
WRITE or WRITE w/AP
(same bank)
Illegal
-
3
3
MASK-WR
w/AP
MASK-WR or MASK-WR w/AP
(same bank)
Illegal
-
BL=16
WRITE or WRITE w/AP
(different bank)
BL/2
BL/2
tCK
tCK
-
3
MASK-WR or MASK-WR w/AP
(different bank)
3
READ or READ w/AP
(same bank)
Illegal
3
READ or READ w/AP
(different bank)
WL + BL/2 + tWTR + 1
tCK
3,9
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Timing Between Commands (PRECHARGE and Auto-PRECHARGE): DQ ODT is Disable (cont’d)
From
Minimum Delay between "From Command"
and "To Command"
To Command
Unit
Notes
Command
PRECHARGE
(to same bank as PRECHARGE)
PRECHARGE All
4
tCK
1
PRECHARGE
4
4
4
tCK
tCK
tCK
1
1
1
PRECHARGE
PRECHARGE
All
PRECHARGE All
Notes:
1. For a given bank, the precharge period should be counted from the latest precharge command, whether per-bank or all-bank, issued
to that bank. The precharge period is satisfied tRP after that latest precharge command.
2. Any command issued during the minimum delay time as specified in the table above is illegal.
3. After READ w/AP, seamless read operations to different banks are supported. After WRITE w/AP or MASK-WR w/AP, seamless write
operations to different banks are supported. READ, WRITE, and MASK-WR operations may not be truncated or interrupted.
4. tRPST values depend on MR1-OP[7] respectively.
5. tWPRE values depend on MR1-OP[2] respectively.
6. Minimum Delay between "From Command" and "To Command" in clock cycle is calculated by dividing tRTP(in ns) by tCK(in ns) and
rounding up to the next integer: Minimum Delay[cycles] = Roundup(tRTP[ns] / tCK[ns])
7. Minimum Delay between "From Command" and "To Command" in clock cycle is calculated by dividing tWR(in ns) by tCK(in ns) and
rounding up to the next integer: Minimum Delay[cycles] = Roundup(tWR[ns] / tCK[ns])
8. Minimum Delay between "From Command" and "To Command" in clock cycle is calculated by dividing tRPpb(in ns) by tCK(in ns) and
rounding up to the next integer: Minimum Delay[cycles] = Roundup(tRPpb[ns] / tCK[ns])
9. Minimum Delay between "From Command" and "To Command" in clock cycle is calculated by dividing tWTR(in ns) by tCK(in ns) and
rounding up to the next integer: Minimum Delay[cycles] = Roundup(tWTR[ns] / tCK[ns])
10. For Read w/AP the value is nRTP which is defined in Mode Register 2.
11. For Write w/AP the value is nWR which is defined in Mode Register 1.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Timing Between Commands (read w/ AP and write command): DQ ODT is Enabled
From
Minimum Delay between "From Command"
and "To Command"
To Command
Unit
tCK
tCK
tCK
tCK
Notes
2, 3
Command
WRITE or WRITE w/AP
(different bank)
RL+RU(tDQSCK(max)/tCK)+BL/2
+RD(tRPST)-ODTLon-RD(tODTon,min/tCK)+1
RL+RU(tDQSCK(max)/tCK)+BL/2
READ w/AP
BL=16
MASK-WR or MASK-WR w/AP
(different bank)
2, 3
+RD(tRPST)-ODTLon-RD(tODTon,min/tCK)+1
RL+RU(tDQSCK(max)/tCK)+BL/2
WRITE or WRITE w/AP
(different bank)
2, 3
+RD(tRPST)-ODTLon-RD(tODTon,min/tCK)+1
RL+RU(tDQSCK(max)/tCK)+BL/2
READ w/AP
BL=32
MASK-WR or MASK-WR w/AP
(different bank)
2, 3
+RD(tRPST)-ODTLon-RD(tODTon,min/tCK)+1
Notes:
1. The rest of the timing about prechage and Auto-Precharge is same as DQ ODT is Disable case.
2. After READ w/AP, seamless read operations to different banks are supported. READ, WRITE, and MASK-WR operations may not be
truncated or interrupted.
3. tRPST values depend on MR1-OP[7] respectively.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Refresh command
The REFRESH command is initiated with CS HIGH, CA0 LOW, CA1 LOW, CA2 LOW, CA3 HIGH and CA4 LOW
at the first rising edge of the clock. Per-bank REFRESH is initiated with CA5 LOW at the first rising edge of the
clock. All-bank REFRESH is initiated with CA5 HIGH at the first rising edge of the clock.
A per-bank REFRESH command (REFpb) is performed to the bank address as transferred on CA0, CA1 and CA2
at the second rising edge of the clock. Bank address BA0 is transferred on CA0, bank address BA1 is transferred
on CA1 and bank address BA2 is transferred on CA2. A per-bank REFRESH command (REFpb) to the eight
banks can be issued in any order. e.g. REFpb commands are issued in the following order: 1-3-0-2-4-7-5-6. After
the eight banks have been refreshed using the per-bank REFRESH command the controller can send another set
of per-bank REFRESH commands in the same order or a different order. e.g. REFpb commands are issued in the
following order that is different from the previous order: 7-1-3-5-0-4-2-6. One of the possible order can also be a
sequential round robin: 0-1-2-3-4-5-6-7. It is illegal to send a per-bank REFRESH command to the same bank
unless all eight banks have been refreshed using the per-bank REFRESH command. The count of eight REFpb
commands starts with the first REFpb command after a synchronization event.
The bank count is synchronized between the controller and the SDRAM by resetting the bank count to zero.
Synchronization can occur upon issuing a RESET command or at every exit from self refresh. REFab command
also synchronizes the counter between the controller and SDRAM to zero. The SDRAM device can be placed in
self-refresh or a REFab command can be issued at any time without cycling through all eight banks using per-bank
REFRESH command. After the bank count is synchronized to zero the controller can issue per-bank REFRESH
commands in any order as described in the previous paragraph.
A REFab command issued when the bank counter is not zero will reset the bank counter to zero and the DRAM
will perform refreshes to all banks as indicated by the row counter.
If another refresh command (REFab or
REFpb) is issued after the REFab command then it uses an incremented value of the row counter.
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8Gb: NT6AN256T32AV
Bank and Refresh counter increment behavior
The table below shows examples of both bank and refresh counter increment behavior.
Refresh
Bank#
Bank
Counter #
To 0
Ref Counter #
#
Sub# Command
BA0
BA1
BA2
(Row Address #)
0
1
0
Reset, SRX or REFab
-
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
0
1
2
REFpb
REFpb
REFpb
REFpb
REFpb
REFpb
REFpb
REFpb
REFpb
REFpb
REFpb
REFpb
REFpb
REFpb
REFpb
REFpb
REFpb
REFpb
REFpb
REFab
REFpb
REFpb
0
0
0
0
1
1
1
1
1
1
0
0
1
0
0
1
0
0
0
V
1
1
0
0
1
1
0
0
1
1
1
1
0
1
0
1
0
0
0
0
1
V
1
1
0
1
0
1
0
1
0
1
0
1
1
1
1
0
0
0
0
1
0
V
0
1
0
1
0 to 1
1 to 2
2 to 3
3 to 4
4 to 5
5 to 6
6 to 7
7 to 0
0 to 1
1 to 2
2 to 3
3 to 4
4 to 5
5 to 6
6 to 7
7 to 0
0 to 1
1 to 2
2 to 3
To 0
2
3
2
4
3
n
5
4
6
5
7
6
8
7
9
6
10
11
12
13
14
15
16
17
18
19
20
21
22
7
1
3
n + 1
5
2
0
4
0
1
n + 2
2
0~7
6
n + 2
0 to 1
1 to 2
n + 3
7
Snip
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A bank must be idle before it can be refreshed. The controller must track the bank being refreshed by the per-bank
REFRESH command.
The REFpb command must not be issued to the device until the following conditions are met:
- tRFCab has been satisfied after the prior REFab command.
- tRFCpb has been satisfied after the prior REFpb command.
- tRP has been satisfied after the prior PRECHARGE command to that bank.
- tRRD has been satisfied after the prior ACTIVATE command (if applicable, for example after activating a row
in a different bank than the one affected by the REFpb command).
The target bank is inaccessible during per-bank REFRESH cycle time (tRFCpb), however, other banks within the
device are accessible and can be addressed during the cycle. During the REFpb operation, any of the banks other
than the one being refreshed can be maintained in an active state or accessed by a READ or a WRITE command.
When the per-bank REFRESH cycle has completed, the affected bank will be in the idle state.
After issuing REFpb, these conditions must be met:
- tRFCpb must be satisfied before issuing a REFab command.
- tRFCpb must be satisfied before issuing an ACTIVATE command to the same bank.
- tRRD must be satisfied before issuing an ACTIVATE command to a different bank.
- tRFCpb must be satisfied before issuing another REFpb command.
An all-bank REFRESH command (REFab) issues a REFRESH command to all banks. All banks must be idle
when REFab is issued (for instance, by issuing a PRECHARGE-all command prior to issuing an all-bank
REFRESH command). REFab also synchronizes the bank count between the controller and the SDRAM to zero.
The REFab command must not be issued to the device until the following conditions have been met:
- tRFCab has been satisfied following the prior REFab command.
- tRFCpb has been satisfied following the prior REFpb command.
- tRP has been satisfied following the prior PRECHARGE commands.
When an all-bank refresh cycle has completed, all banks will be idle. After issuing REFab:
- tRFCab latency must be satisfied before issuing an ACTIVATE command.
- tRFCab latency must be satisfied before issuing a REFab or REFpb command.
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REFRESH Command Scheduling Separation requirements
Symbol
Minimum Delay From
To
Notes
REFab
tRFCab
REFab
Activate command to any bank
REFpb
REFab
tRFCpb
tRRD
REFpb
Activate command to same bank as REFpb
REFpb
REFpb
Activate command to different bank than REFpb
REFpb
1
Activate
Activate command to different bank than prior Activate command
Notes:
1. A bank must be in the idle state before it is refreshed, so following an ACTIVATE command REFab is prohibited; REFpb is supported only
if it affects a bank that is in the idle state.
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All-Bank Refresh Operation
Notes:
1. DES commands are shown for ease of illustration; other commands may be valid at these times.
2. Activate Command is shown as an example. Other commands may be valid provided the timing specification is satisfied.
Per Bank Refresh to a different bank Operation
Notes:
1. DES commands are shown for ease of illustration; other commands may be valid at these times.
2. In the beginning of this example, the REFpb bank is pointing to bank 0.
3. Operations to banks other than the bank being refreshed are supported during the tpbR2pbR period.
4. Activate Command is shown as an example. Other commands may be valid provided the timing specification is satisfied.
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Per Bank Refresh to the same bank Operation
Notes:
1. DES commands are shown for ease of illustration; other commands may be valid at these times.
2. In the beginning of this example, the REFpb bank is pointing to bank 0.
3. Operations to banks other than the bank being refreshed are supported during the tRFCpb period.
4. Activate Command is shown as an example. Other commands may be valid provided the timing specification is satisfied.
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In general, a Refresh command needs to be issued to the LPDDR4 SDRAM regularly every tREFI interval. To
allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh
interval is provided. A maximum of 8 Refresh commands can be postponed during operation of the LPDDR4
SDRAM, meaning that at no point in time more than a total of 8 Refresh commands are allowed to be postponed
and maximum number of pulled-in or postponed REF command is dependent on refresh rate. It is described in the
table below. In case that 8 Refresh commands are postponed in a row, the resulting maximum interval between
the surrounding Refresh commands is limited to 9 × tREFI. A maximum of 8 additional Refresh commands can be
issued in advance (“pulled in”), with each one reducing the number of regular Refresh commands required later by
one. Note that pulling in more than 8 Refresh commands in advance does not further reduce the number of regular
Refresh commands required later, so that the resulting maximum interval between two surrounding Refresh
commands is limited to 9 × tREFI.
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At any given time, a maximum of 16 REF commands can be issued within 2 x tREFI. Self-Refresh Mode may be
entered with a maximum of eight Refresh commands being postponed. After exiting Self-Refresh Mode with one or
more Refresh commands postponed, additional Refresh commands may be postponed to the extent that the total
number of postponed Refresh commands (before and after the Self-Refresh) will never exceed eight. During
Self-Refresh Mode, the number of postponed or pulled-in REF commands does not change.
And for per bank refresh, a maximum 8 x 8 per bank refresh commands can be postponed or pulled in for
scheduling efficiency. At any given time, a maximum of 2 x 8 x 8 per bank refresh commands can be
issued within 2 x tREFI.
Legacy Refresh Command Timing Constraints
Max. No. of
pulled-in or
postponed REFab
Max. Interval
between two
REFab
Max. No. of REFab within
max(2xtREFI x refresh rate Per-bank Refresh
multiplier, 16xtRFC)
MR4
OP[2:0]
Refresh rate
000B
001B
010B
011B
100B
101B
110B
111B
Low Temp. Limit
4x tREFI
N/A
8
N/A
N/A
16
N/A
9 x 4 x tREFI
9 x 2 x tREFI
9 x tREFI
1/8 of REFab
1/8 of REFab
1/8 of REFab
1/8 of REFab
1/8 of REFab
1/8 of REFab
N/A
2x tREFI
8
16
1x tREFI
8
16
0.5x tREFI
8
9 x 0.5 x tREFI
9 x 0.25 x tREFI
9 x 0.25 x tREFI
N/A
16
0.25x tREFI
0.25x tREFI
High Temp. Limit
8
16
8
16
N/A
N/A
Modified REFRESH Command Timing Constraints
Max. No. of
pulled-in or
postponed REFab
Max. Interval
between two
REFab
Max. No. of REFab within
max(2xtREFI x refresh rate Per-bank Refresh
multiplier, 16xtRFC)
MR4
OP[2:0]
Refresh rate
000B
001B
010B
011B
100B
101B
110B
Low Temp. Limit
4x tREFI
N/A
2
N/A
N/A
4
N/A
3 x 4 x tREFI
5 x 2 x tREFI
9 x tREFI
1/8 of REFab
1/8 of REFab
1/8 of REFab
1/8 of REFab
1/8 of REFab
1/8 of REFab
N/A
2x tREFI
4
8
1x tREFI
8
16
16
16
16
N/A
0.5x tREFI
8
9 x 0.5 x tREFI
9 x 0.25 x tREFI
9 x 0.25 x tREFI
N/A
0.25x tREFI
0.25x tREFI
High Temp. Limit
8
8
111B
N/A
Notes:
1. For any thermal transition phase where Refresh mode is transitioned to either 2x tREFIor 4x tREFI, DRAM will support the previous
postponed refresh requirement provided the number of postponed refreshes is monotonically reduced to meet the new requirement.
However, the pulled-in refresh commands in previous thermal phase are not applied in new thermal phase. Entering new thermal
phase the controller must count the number of pulled-in refresh commands as zero, regardless of remaining pulled-in refresh
commands in previous thermal phase.
2. LPDDR4 devices are refreshed properly if memory controller issues refresh commands with same or shorter refresh period than
reported by MR4 OP[2:0]. If shorter refresh period is applied, the corresponding requirements from Table apply. For example, when
MR4 OP[2:0]=001B, controller can be in any refresh rate from 4xtREFI to 0.25x tREFI. When MR4 OP[2:0]=010B, the only prohibited
refresh rate is 4x tREFI.
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Postponing Refresh Commands (Example)
Pulling-in Refresh Commands (Example)
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Burst Read operation followed by Per Bank Refresh
The Per Bank Refresh command can be issued after tRTP + tRPpb from Read command.
Burst Read operation followed by Per Bank Refresh
Notes:
1. BL = 16, Preamble = Toggle, Postamble = 0.5nCK, DQ/DQS: VSSQ termination
2. Dout n = data-out from column n.
3. In case of BL = 32, Delay time from Read to Per Bank Precharge is 8nCK + tRTP.
4. DES commands are shown for ease of illustration; other commands may be valid at these times.
The Per Bank Refresh command can be issued after tRC from Read with Auto Precharge command.
Burst Read with Auto-Precharge operation followed by Per Bank Refresh
Notes:
1. BL = 16, Preamble = Toggle, Postamble = 0.5nCK, DQ/DQS: VSSQ termination
2. Dout n = data-out from column n.
3. tRC needs to be satisfied prior to issuing subsequent Per Bank Refresh command.
4. DES commands are shown for ease of illustration; other commands may be valid at these times.
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Refresh Requirement
Refresh Requirement Parameters per die for Single Channel SDRAM devices
Refresh Requirements
Density per Channel
Symbol
4Gb
4Gb
8
Unit
Number of banks per channel
Refresh Window (tREFW)
tREFW
32
ms
(TCASE 85°C)
Refresh Window (tREFW)
(1/2 Rate Refresh, 85°C < TCASE 95°C)
Refresh Window (tREFW)
tREFW
tREFW
R
16
8
ms
ms
-
(1/4 Rate Refresh, 95°C < TCASE 105°C)
Required Number of REFRESH Commands
in a tREFW window
8192
REFAB
REFPB
REFAB
REFPB
REFAB
REFPB
tREFI
tREFIpb
tREFI
3.9
488
1.95
244
0.975
122
180
90
us
ns
us
ns
us
ns
ns
ns
Average Refresh Interval
(TCASE 85°C)
Average Refresh Interval
(85°C < TCASE 95°C)
Average Refresh Interval
(95°C < TCASE 105°C)
tREFIpb
tREFI
tREFIpb
tRFCab
tRFCpb
Refresh Cycle Time (All Banks)
Refresh Cycle Time (Per Bank)
Per-bank Refresh to Per-bank
Refresh different bank Time
tpbR2pbR
90
ns
Notes:
1. Self Refresh abort feature is available for higher density devices starting with12 Gb dual channel device and 6 Gb single channel
device and tXSR_abort(min) is defined as tRFCpb + 17.5ns.
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Self Refresh Operation
Self Refresh Entry and Exit
The Self Refresh command can be used to retain data in the LPDDR4 SDRAM, the SDRAM retains data without
external Refresh command. The device has a built-in timer to accommodate Self Refresh operation. The Self
Refresh is entered by Self Refresh Entry Command defined by having CS High, CA0 Low, CA1 Low, CA2 Low;
CA3 High; CA4 High, CA5 Valid (Valid that means it is Logic Level, High or Low) for the first rising edge and CS
Low, CA0 Valid, CA1 Valid, CA2 Valid, CA3 Valid, CA4 Valid, CA5 Valid at the second rising edge of the clock.
Self Refresh command is only allowed when read data burst is completed and SDRAM is idle state.
During Self Refresh mode, external clock input is needed and all input pin of SDRAM are activated. SDRAM can
accept the following commands, MRR-1, CAS-2, DES, SRX, MPC, MRW-1, and MRW-2 except PASR
Bank/Segment setting.
LPDDR4 SDRAM can operate in Self Refresh in both the standard or elevated temperature ranges. SDRAM will
also manage Self Refresh power consumption when the operating temperature changes, lower at low
temperature and higher at high temperatures.
For proper Self Refresh operation, power supply pins (VDD1, VDD2 and VDDQ) must be at valid levels. However
VDDQ may be turned off during Self-Refresh with Power Down after tESCKE is satisfied.
Prior to exiting Self-Refresh with Power Down, VDDQ must be within specified limits. The minimum time that the
SDRAM must remain in Self Refresh model is tSR,min. Once Self Refresh Exit is registered, only MRR-1, CAS-2,
DES, MPC, MRW-1 and MRW-2 except PASR Bank/Segment setting are allowed until tXSR is satisfied.
The use of Self Refresh mode introduces the possibility that an internally timed refresh event can be missed
when Self Refresh Exit is registered. Upon exit from Self Refresh, it is required that at least one REFRESH
command (8 per-bank or 1 all-bank) is issued before entry into a subsequent Self Refresh. This REFRESH
command is not included in the count of regular refresh commands required by the tREFI interval, and does not
modify the postponed or pulled-in refresh counts; the REFRESH command does count toward the maximum
refreshes permitted within 2 X tREFI.
Self Refresh Entry/Exit Timing
Notes:
1. MRR-1, CAS-2, DES, SRX, MPC, MRW-1 and MRW-2 except PASR Bank/Segment and SR Abort setting is allowed during Self Refresh.
2. DES commands are shown for ease of illustration; other commands may be valid at these times.
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Power Down Entry and Exit during Self Refresh
Entering/Exiting Power Down Mode is allowed during Self Refresh mode in SDRAM. The related timing
parameters between Self Refresh Entry/Exit and Power Down Entry/Exit are shown in figure below.
Self Refresh Entry/Exit Timing with Power Down Entry/Exit
Notes:
1. MRR-1, CAS-2, DES, SRX, MPC, MRW-1 and MRW-2 except PASR Bank/Segment and SR Abort setting is allowed during Self Refresh.
2. Input clock frequency can be changed or the input clock can be stopped or floated after tCKELCK satisfied and during power-down,
provided that upon exiting power-down, the clock is stable and within specified limits for a minimum of tCKCKEH of stable clock prior
to power-down exit and the clock frequency is between the minimum and maximum specified frequency for the speed grade in use.
3. 2 Clock command for example.
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Command input Timing after Power Down Exit
Command input timings after Power Down Exit during Self Refresh
Notes:
1. MRR-1, CAS-2, DES, SRX, MPC, MRW-1 and MRW-2 except PASR Bank/Segment setting is allowed during Self Refresh.
2. Input clock frequency can be changed or the input clock can be stopped or floated after tCKELCK satisfied and during power-down,
provided that upon exiting power-down, the clock is stable and within specified limits for a minimum of tCKCKEH of stable clock prior
to power-down exit and the clock frequency is between the minimum and maximum specified frequency for the speed grade in use.
3. 2 Clock command for example.
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AC Timing Table
Parameter
Min/
Symbol
Data Rate
Unit Notes
Max
Self Refresh Timing
Delay from SRE command to CKE Input low
Minimum Self Refresh Time
Exit Self Refresh to Valid commands
Notes:
tESCKE Min
Max(1.75ns, 3tCK)
Max(15ns, 3tCK)
ns
ns
ns
1
1
tSR
Min
Min
tXSR
Max(tRFCab + 7.5ns, 2tCK)
1,2
1. Delay time has to satisfy both analog time(ns) and clock count(tCK).
It means that tESCKE will not expire until CK has toggled through at least 3 full cycles (3 *tCK) and 1.75ns has transpired.
The case which 3tCK is applied to is shown below.
tESCKE Timing
2. MRR-1, CAS-2, DES, MPC, MRW-1 and MRW-2 except PASR Bank/Segment setting are only allowed during this period.
Self Refresh Abort
If MR4 OP[3] is enabled then DRAM aborts any ongoing refresh during Self Refresh exit and does not increment
the internal refresh counter. Controller can issue a valid command after a delay of tXSR_abort instead of tXSR.
The value of tXSR_abort(min) is defined as tRFCpb + 17.5 ns.
Upon exit from Self Refresh mode, the LPDDR4 SDRAM requires a minimum of one extra refresh (8 per bank or 1
all bank) before entry into a subsequent Self Refresh mode. This requirement remains the same irrespective of the
setting of the MR bit for self refresh abort.
Self refresh abort feature is available for higher density devices starting with12 Gb dual channel device and 6Gb
single channel device.
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MRR, MRW, MPC Command during tXSR, tRFC
Mode Register Read (MRR), Mode Register Write (MRW) and Multi Purpose Command (MPC) can be issued
during tXSR period.
MRR, MRW and MPC Commands Issuing Timing during tXSR
Notes:
1. MPC and MRW command are shown in figure at this time, Any combination of MRR, MRW and MPC is allowed during tXSR period.
2. Any command also includes MRR, MRW and all MPC command.
Mode Register Read (MRR), Mode Register Write (MRW) and Multi Purpose Command (MPC) can be issued
during tRFC period.
MRR, MRW and MPC Commands Issuing Timing during tRFC
Notes:
1. MPC and MRW command are shown in figure at this time, Any combination of MRR, MRW and MPC is allowed during tRFCab or
tRFCpb period.
2. Refresh cycle time depends on Refresh command. In case of REF per Bank command issued, Refresh cycle time will be tRFCpb.
3. Any command also includes MRR, MRW and all MPC command.
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MODE REGISTER READ(MRR)
The Mode Register Read (MRR) command is used to read configuration and status data from the
LPDDR4-SDRAM registers.The MRR command is initiated with CS and CA[5:0] in the proper state as defined by
the Command Truth Table. The mode register address operands (MA[5:0]) allow the user to select one of 64
registers. The mode register contents are available on the first 4UI's data bits of DQ[7:0] after RL x tCK +
tDQSCK + tDQSQ following the MRR command. Subsequent data bits contain valid but undefined content. DQS
is toggled for the duration of the Mode Register READ burst. The MRR has a command burst length 16.
MRR operation must not be interrupted.
DQ output mapping
BL
DQ0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
OP0
OP1
OP2
OP3
OP4
OP5
OP6
OP7
V
V
V
V
V
V
V
V
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8-15
DMI0-1
V
V
Notes:
1. MRR data are extended to first 4 UI’s for DRAM controller to sample data easily.
2. DBI may apply or may not apply during normal MRR. It’s vendor specific. If read DBI is enable with MRS and vendor cannot support
the DBI during MRR, DMI pin status should be low.
3. The read pre-amble and post-amble of MRR are same as normal read.
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Mode Register Read Operation
Notes:
1. Only BL=16 is supported
2. Only DES is allowed during tMRR period
3. There are some exceptions about issuing commands after tMRR. Refer to MRR/MRW Timing Constraints Table for detail.
4. DBI is Disable mode.
5. DES commands except tMRR period are shown for ease of illustration; other commands may be valid at these times.
6. DQ/DQS: VSSQ termination
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MRR after Read and Write command
After a prior READ command, the MRR command must not be issued earlier than BL/2 clock cycles, in a similar
way WL + BL/2 + 1 + RU(tWTR/tCK) clock cycles after a prior Write, Write with AP, Mask Write, Mask Write with
AP and MPC Write FIFO command in order to avoid the collision of Read and Write burst data on SDRAM’s
internal Data bus.
READ to MRR Timing
Notes:
1. The minimum number of clock cycles from the burst READ command to the MRR command is BL/2.
2. Read BL = 32, MRR BL = 16, RL = 14, Preamble = Toggle, Postamble = 0.5nCK, DBI = Disable, DQ/DQS: VSSQ termination
3. DES commands except tMRR period are shown for ease of illustration; other commands may be valid at these times.
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Write to MRR Timing
Notes:
1. Write BL=16, Write Postamble = 0.5nCK, DQ/DQS: VSSQ termination.
2. Only DES is allowed during tMRR period.
3. Din n = data-in to columnm n.
4. The minimum number of clock cycles from the burst write command to MRR command is WL + BL/2 + 1 + RU(tWTR/tCK).
5. tWTR starts at the rising edge of CK after the last latching edge of DQS.
6. DES commands except tMRR period are shown for ease of illustration; other commands may be valid at these times.
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MRR after Power-Down Exit
Following the power-down state, an additional time, tMRRI, is required prior to issuing the mode register read
(MRR) command. This additional time (equivalent to tRCD) is required in order to be able to maximize
power-down current savings by allowing more power-up time for the MRR data path after exit from power-down
mode.
MRR Following Power-Down
Notes:
1. Only DES is allowed during tMRR period.
2. DES commands except tMRR period are shown for ease of illustration; other commands may be valid at these times.
Mode Register Read/Write AC timing
Min/
Parameter
Symbol
Data Rate
Unit Notes
Max
Mode Register Read/Write Timing
Additional time after tXP has expired until
MRR command may be issued
tMRRI
Min
Min
tRCD + 3nCK
8
-
MODE REGISTER READ command period
MODE REGISTER WRITE command period
Mode register set command delay
tMRR
tMRW
tMRD
nCK
Min MAX(10ns, 10nCK)
Min max(14ns, 10nCK)
-
-
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Mode Register Write (MRW) Operation
The Mode Register Write (MRW) command is used to write configuration data to the mode registers. The MRW
command is initiated by setting CKE, CS, and CA[5:0] to valid levels at a rising edge of the clock (see Command
Truth Table). The mode register address and the data written to the mode registers is contained in CA[5:0]
according to the Command Truth Table. The MRW command period is defined by tMRW. Mode register Writes to
read-only registers have no impact on the functionality of the device.
Mode Register Write Timing
Notes:
1. Only Deselect command is allowed during tMRW and tMRD periods.
Mode Register Write
MRW can be issued from either a Bank-Idle or Bank-Active state. Certain restrictions may apply for MRW from an
Active state.
Truth Table for Mode Register Read (MRR) and Mode Register Write (MRW)
Current State
SDRAM
Intermediate State
SDRAM
Next State
SDRAM
Command
MRR
Mode Register Reading
(All Banks Idle)
All Banks Idle
All Banks Idle
All Banks Idle
Bank(s) Active
Mode Register Writing
(All Banks Idle)
MRW
MRR
Mode Register Reading
Mode Register Writing
Bank(s) Active
Bank(s) Active
MRW
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MRR/MRW Timing Constraints: DQ ODT is Disable
Minimum Delay between "From Command"
From Command
To Command
Unit Notes
and "To Command"
tMRR
MRR
RD/RDA
-
-
tMRR
MRR
WR/WRA/
MWR/MWRA
MRW
RL+RU(tDQSCK(max)/tCK)+BL/2
-WL+tWPRE+RD(tRPST)
RL+RU(tDQSCK(max)/tCK)+BL/2+3
BL/2
nCK
nCK
nCK
RD/RDA
WR/WRA/
WL+1+BL/2+RU(tWTR/tCK)
nCK
MWR/MWRA
MRW
MRR
tMRD
tXP+tMRRI
tMRD
-
-
-
Power Down Exit
RD/RDA
WR/WRA/
MWR/MWRA
MRW
MRW
tMRD
-
-
tMRW
RD/
RD FIFO/
RL+BL/2+RU(tDQSCKmax/tCK)+RD(tRPST)
+max(RU(7.5ns/tCK),8nCK)
nCK
nCK
nCK
nCK
RD DQ CAL
RD with
RL+BL/2+RU(tDQSCKmax/tCK)+RD(tRPST)
+max(RU(7.5ns/tCK),8nCK)+nRTP-8
Auto-Precharge
WR/
MRW
MWR/
WL+1+BL/2+max(RU(7.5ns/tCK),8nCK)
WR FIFO
WR/MWR with
Auto-Precharge
WL+1+BL/2+max(RU(7.5ns/tCK),8nCK)+nWR
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MRR/MRW Timing Constraints: DQ ODT is Enable
Minimum Delay between "From Command"
and "To Command"
From Command
To Command
Unit Notes
MRR
RD/RDA
Same as ODT Disable Case
-
MRR
WR/WRA/
MWR/MWRA
MRW
RL+RU(tDQSCK(max)/tCK)+BL/2-ODTLon
-RD(tODTon(min)/tCK)+RD(tRPST)+1
Same as ODT Disable Case
nCK
-
RD/RDA
WR/WRA/
MWR/MWRA
MRW
MRR
Same as ODT Disable Case
Same as ODT Disable Case
-
-
Powe Down Exit
RD/RDA
WR/WRA/
MWR/MWRA
MRW
MRW
RD/
RD FIFO/
RD DQ CAL
RD with
Auto-Precharge
WR/
MRW
Same as ODT Disable Case
-
MWR/
WR FIFO
WR/MWR with
Auto-Precharge
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VREF Current Generator (VRCG)
LPDDR4 SDRAM VREF current generators (VRCG) incorporate a high current mode to reduce the settling time of
the internal VREF(DQ) and VREF(CA) levels during training and when changing frequency set points during
operation. The high current mode is enabled by setting MR13[OP3] = 1. Only Deselect commands may be issued
until tVRCG_ENABLE is satisfied. tVRCG_ENABLE timing is shown in figure below.
VRCG Enable timing
VRCG high current mode is disabled by setting MR13[OP3] = 0. Only Deselect commands may be issued until
tVRCG_DISABLE is satisfied. tVRCG_DISABLE timing is shown in figure below.
VRCG Disable timing
Note that LPDDR4 SDRAM devices support VREF(CA) and VREF(DQ) range and value changes without enabling
VRCG high current mode.
VRCG Enable/Disable Timing
533/1066/1600/2133/2667/
Speed
3200/3733/4267
Unit Notes
Parameter
Symbol
Min
Max
200
100
VREF high current mode enable time
VREF high current mode disable time
tVRCG_ENABLE
tVRCG_DISABLE
-
-
ns
ns
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CA VREFTraining
The DRAM internal CA VREF specification parameters are voltage operating range, stepsize, VREF set tolerance,
VREF step time and VREF valid level.
The voltage operating range specifies the minimum required VREF setting range for LPDDR4 DRAM devices. The
minimum range is defined by VREFmax and VREFmin as depicted in figure below.
V
REF
operating range (V
min, V
max)
REF
REF
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The V
stepsize is defined as the stepsize between adjacent steps. However, for a given design, DRAM has
REF
one value for V
step size that falls within the range.
REF
The V
set tolerance is the variation in the V
voltage from the ideal setting. This accounts for accumulated
REF
REF
error over multiple steps. There are two ranges for V
uncertainty is a function of number of steps n.
set tolerance uncertainty. The range of V
set tolerance
REF
REF
The V
set tolerance is measured with respect to the ideal line which is based on the two endpoints. Where the
REF
endpoints are at the min and max V
values for a specified range. An illustration depicting an example of the
REF
stepsize and V
set tolerance is below.
REF
Example of V
set tolerance (max case only shown) and step size
REF
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The V
increment/decrement step times are define by V
_time-short, Middle and long. The VREF_time-short,
REF
REF
V
REF
_time-Middle and V
_time-long is defined from TS to TE as shown in the figure below where TE is
REF
referenced to when the V
voltage is at the final DC level within the V
valid tolerance(V
_val_tol).
REF
REF
REF
The V
valid level is defined by V
_val tolerance to qualify the step time TE as shown in figure below. This
REF
REF
parameter is used to insure an adequate RC time constant behavior of the voltage level change after any V
increment/decrement adjustment. This parameter is only applicable for DRAM component level
validation/characerization.
REF
V
V
_time-Short is for a single stepsize increment/decrement change in VREF voltage.
_time-Middle is at least 2 stepsizes increment/decrement change within the same V
REF
CA range in V
REF
REF
REF
voltage.
V
V
_time-Long is the time including up to V
min to V
REF
max or V max to V min change across the
REF REF REF
REF
CA Range in V
voltage.
REF
REF
TS - is referenced to MRS command clock
TE - is referenced to the V _val_tol
REF
V
REF
_time for Short, Middle and Long Timing Diagram
The MRW command to the mode register bits are as follows.
MR12 OP[5:0] : V
(CA) Setting
REF
MR12 OP[6] : V
(CA) Range
REF
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The minimum time required between two V
MRS commands is V
_time-short for single step and
REF
REF
V
REF
_time-Middle for a full voltage range step.
V
REF
step single stepsize increment case
V
REF
step single stepsize decrement case
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V
REF
full step from V
min to V
max case
REF
REF
V
REF
full step from V
max to V
min case
REF
REF
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CA Internal V
Specifications
REF
The table below contains the CA internal V
compliance.
specifications that will be characterized at the component level for
REF
Parameter
Symbol
_max_R0
Min
Typ
Max
30%
-
Unit
Notes
1,11
1,11
1,11
1,11
2
-
-
V
Max operating point Range0
Min operating point Range0
Max operating point Range1
Min operating point Range1
V
V
DD2
V
DD2
V
DD2
V
DD2
V
DD2
V
DD2
V
DD2
REF
REF
10%
-
V
V
_min_R0
REF
REF
REF
-
-
42%
-
V
V
_max_R1
REF
22%
-
V
REF
V
_min_R1
REF
0.30%
0.40%
0.50%
1.00%
0.10%
100
200
250
1
V
REF
Stepsize
V
REF
_step
-1.00%
0.00%
3,4,6
3,5,7
8
V
Set Tolerance
V
_set_tol
REF
REF
-0.10%
0.00%
-
-
ns
ns
V
REF
_time-Short
-
-
12
V
_time_Middle
REF
V
Step Time
REF
-
-
-
ns
9
V
_time-Long
REF
-
ms
13,14
10
V
_time_weak
REF
-0.10%
0.00%
0.10%
V
REF
Valid tolerance
V
_val_tol
V
DD2
REF
Notes:
1. VREF DC voltage referenced to VDD2_DC.
2. VREF stepsize increment/decrement range. VREF at DC level.
3. VREF_new = VREF_old + n*VREF_step; n= number of steps; if increment use "+"; If decrement use "-".
4. The minimum value of VREF setting tolerance = VREF_new - 1.0%*VDD2. The maximum value of VREF setting tolerance = VREF_new +
1.0%*VDD2. For n>4.
5. The minimum value of VREF setting tolerance = VREF_new - 0.10%*VDD2. The maximum value of VREF setting tolerance = VREF_new +
0.10%*VDD2. For n4.
6. Measured by recording the min and max values of the VREF output over the range, drawing a straight line between those points and
comparing all other VREF output settings to that line.
7. Measured by recording the min and max values of the VREF output across 4 consecutive steps(n=4), drawing a straight line between
those points and comparing all other VREF output settings to that line.
8. Time from MRS command to increment or decrement one step size for VREF
.
9. Time from MRS command to increment or decrement VREFmin to VREFmax or VREFmax to VREFmin change across the VREFCA Range in
VREF voltage.
10. Only applicable for DRAM component level test/characterization purpose. Not applicable for normal mode of operation. VREF valid is
to qualify the step times which will be characterized at the component level.
11. DRAM range 0 or 1 set by MR12 OP[6].
12. Time from MRS command to increment or decrement more than one step size up to a full range of VREF voltage withiin the same
VREFCA range.
13. Applies when VRCG high current mode is not enabled, specified by MR13[OP3] = 0.
14. VREF_time_weak covers all VREF(CA) Range and Value change conditions are applied to VREF_time_Short/Middle/Long.
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DQ VREF Training
The DRAM internal DQ V
specification parameters are voltage operating range, stepsize, V
set tolerance,
REF
REF
V
REF
step time and V
valid level.
REF
The voltage operating range specifies the minimum required V
setting range for LPDDR4 DRAM devices. The
REF
minimum range is defined by V
max and V min as depicted in figure below.
REF
REF
VREF operating range (V
min, V
max)
REF
REF
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The V
stepsize is defined as the stepsize between adjacent steps. However, for a given design, DRAM has
REF
one value for V
step size that falls within the range.
REF
The V
set tolerance is the variation in the V
voltage from the ideal setting. This accounts for accumulated
REF
REF
error over multiple steps. There are two ranges for V
set tolerance
REF
uncertainty. The range of V
set tolerance uncertainty is a function of number of steps n.
REF
The V
set tolerance is measured with respect to the ideal line which is based on the two endpoints. Where the
REF
endpoints are at the min and max V
values for a specified range. An illustration depicting an example of the
REF
stepsize and V
set tolerance is shown in below.
REF
Example of V
set tolerance (max case only shown) and stepsize
REF
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The V
increment/decrement step times are define by V
_time-short, Middle and long. The V
_time-short,
REF
REF
REF
V
REF
_time-Middle and V
_time-long is defined from TS to TE as shown in the figure below where TE is
REF
referenced to when the V
voltage is at the final DC level within the V
valid tolerance(V
_val_tol).
REF
REF
REF
The V
valid level is defined by V
_val tolerance to qualify the step time TE as shown in figure below. This
REF
REF
parameter is used to insure an adequate RC time constant behavior of the voltage level change after any V
increment/decrement adjustment. This parameter is only applicable for DRAM component level
validation/characerization.
REF
V
V
_time-Short is for a single stepsize increment/decrement change in V
voltage.
REF
REF
_time-Middle is at least 2 stepsizes increment/decrement change within the same V
DQ range in V
REF
REF
REF
voltage.
V
V
_time-Long is the time including up to V
min to V
REF
max or V max to V min change across the
REF REF REF
REF
DQ Range in V
voltage.
REF
REF
TS - is referenced to MRS command clock
TE - is referenced to the V _val_tol
REF
V
REF
_time for Short, Middle and Long Timing Diagram
The MRW command to the mode register bits are as follows.
MR14 OP[5:0] : V
(DQ) Setting
(DQ) Range
REF
MR14 OP[6] : V
REF
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The minimum time required between two V
MRS commands is V
_time-short for single step and
REF
REF
V
REF
_time-Middle for a full voltage range step.
V
REF
step single stepsize increment case
V
REF
step single stepsize decrement case
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V
REF
full step from V
min to V
max case
REF
REF
V
REF
full step from V
max to V
min case
REF
REF
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DQ Internal V
Specifications
REF
The table below contains the DQ internal V
compliance.
specifications that will be characterized at the component level for
REF
Parameter
Symbol
_max_R0
Min
Typ
Max
30%
-
Unit
Notes
1,11
1,11
1,11
1,11
2
-
-
V
Max operating point Range0
Min operating point Range0
Max operating point Range1
Min operating point Range1
V
V
REF
REF
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
10%
-
V
V
_min_R0
V
V
V
V
V
V
REF
REF
REF
-
-
42%
-
V
V
_max_R1
REF
22%
-
V
V
_min_R1
REF
REF
0.30%
0.40%
0.50%
1.00%
0.10%
100
200
250
1
V
REF
Stepsize
V
REF
_step
-1.00%
0.00%
3,4,6
3,5,7
8
V
Set Tolerance
V
_set_tol
REF
REF
-0.10%
0.00%
DDQ
-
-
ns
V
REF
_time-Short
-
-
ns
ns
12
V
_time_Middle
REF
V
Step Time
REF
-
-
-
9
V
_time-Long
REF
-
ms
13,14
10
V
_time_weak
REF
-0.10%
0.00%
0.10%
V
REF
Valid tolerance
V
_val_tol
V
DDQ
REF
Notes:
1. VREF DC voltage referenced to VDDQ_DC.
2. VREF stepsize increment/decrement range. VREF at DC level.
3. VREF_new = VREF_old + n*VREF_step; n= number of steps; if increment use "+"; If decrement use "-".
4. The minimum value of VREF setting tolerance = VREF_new - 1.0%*VDDQ. The maximum value of VREF setting tolerance = VREF_new +
1.0%*VDDQ. For n>4.
5. The minimum value of VREF setting tolerance = VREF_new - 0.10%*VDDQ. The maximum value of VREF setting tolerance = VREF_new +
0.10%*VDDQ. For n<4.
6. Measured by recording the min and max values of the VREF output over the range, drawing a straight line between those points and
comparing all other VREF output settings to that line.
7. Measured by recording the min and max values of the VREF output across 4 consectuive steps(n=4), drawing a straight line between
those points and comparing all other VREF output settings to that line.
8. Time from MRS command to increment or decrement one step size for VREF
.
9. Time from MRS command to increment or decrement VREFmin to VREFmax or VREFfmax to VREFmin change across the VREFDQ Range in
VREF voltage.
10.Only applicable for DRAM component level test/characterization purpose. Not applicable for normal mode of operation. VREF valid is
to qualify the step times which will be characterized at the component level.
11. DRAM range 0 or 1 set by MR14 OP[6].
12. Time from MRS command to increment or decrement more than one step size up to a full range of VREF voltage withiin the same
VREFDQ range.
13. Applies when VRCG high current mode is not enabled, specified by MR13[OP3] = 0.
14. VREF_time_weak covers all VREF(DQ) Range and Value change conditions are applied to VREF_time_Short/Middle/Long.
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Command Bus Training
Command Bus Trainging for x16 mode
The LPDDR4-SDRAM command bus must be trained before enabling termination for high-frequency operation.
LPDDR4 provides an internal VREF(CA) that defaults to a level suitable for un-terminated, low-frequency operation,
but the VREF(CA) must be trained to achieve suitable receiver voltage margin for terminated, high-frequency
operation. The training mode described here centers the internal VREF(CA) in the CAdata eye and at the same time
allows for timing adjustments of the CS and CA signals to meet setup/hold requirements. Because it can be
difficult to capture commands prior to training the CA inputs, the training mode described here uses a minimum of
external commands to enter, train, and exit the Command Bus Training mode.
NOTES: it is up to the system designer to determine what constitutes “low-frequency” and “high-frequency” based on the capabilities of
the system. Low-frequency should then be defined as an operating frequency in which the system can reliably communicate with
the SDRAM before Command Bus Training is executed.
The LPDDR4-SDRAM die has a bond-pad (ODT-CA) for multi-rank operation. In a multi-rank system, the
terminating rank should be trained first, followed by the nonterminating rank(s).
The LPDDR4-SDRAM uses Frequency Set-Points to enable multiple operating settings for the die. The
LPDDR4-SDRAM defaults to FSP-OP[0] at power-up, which has the default settings to operate in un-terminated,
low-frequency environments. Prior to training, the mode register settings should be configured by setting MR13
OP[6]=1B (FSP-WR[1]) and setting all other mode register bits for FSP-OP[1] to the desired settings for
high-frequency operation. Prior to entering Command Bus Training, the SDRAM will be operating from FSP-OP[x].
Upon Command Bus Training entry when CKE is driven LOW, the LPDDR4-SDRAM will automatically switch to
the alternate FSP register set (FSP-OP[y]) and use the alternate register settings during training. Upon training exit
when CKE is driven HIGH, the LPDDR4-SDRAM will automatically switch back to the original FSP register set
(FSP-OP[x]), returning to the “known-good” state that was operating prior to training. The training values for
V
REF
(CA) are not retained by the DRAM in FSP-OP[y] registers, and must be written to the registers after training
exit.
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1. To enter Command Bus Training mode, issue a MRW-1 command followed by a MRW-2 command to set MR13
OP[0]=1 (Command Bus Training Mode Enabled).
B
2. After time tMRD, CKE may be set LOW, causing the LPDDR4-SDRAM to switch from FSP-OP[x] to FSP-OP[y],
and completing the entry into Command Bus Training mode.
A status of DQS, , DQ and DMI are as follows, and DQ ODT state of DQS, , DQ and DMI will be
followed by MR11 OP[2:0]: DQ ODT and MR13 OP[7]: FSP-OP except output pins.
- DQS[0], [0] become input pins for capturing DQ[6:0] levels by its toggling.
- DQ[5:0] become input pins for setting V
- DQ[6] becomes a input pin for setting V
(CA) Level.
REF
(CA) Range.
REF
- DQ[7] and DMI[0] become input pins and their input level is Valid level or floating, either way is fine.
- DQ[13:8] become output pins to feedback its capturing value via command bus by CS signal.
- DQS[1], [1],DMI[1] and DQ[15:14] become output pins or disable, it means that SDRAM may drive to a
valid level or left floating.
3. At time tCAENT later, LPDDR4 SDRAM can accept to change its VFREF(ca) Range and Value using input
signals of DQS[0], [0] and DQ[6:0] from existing value that’s setting via MR12 OP[6:0]. The mapping
between MR12 OP code and DQs is shown in the following table. At least one V
before proceed to next training steps.
CA setting is required
REF
Mapping of MR12 OP Code and DQ Numbers
Mapping
MR12 OP Code
DQ Number
OP6
DQ6
OP5
DQ5
OP4
DQ4
OP3
DQ3
OP2
DQ2
OP1
DQ1
OP0
DQ0
4. The new V
(CA) value must “settle” for time tV
_LONG before attempting to latch CA information.
REF
REF
5. To verify that the receiver has the correct V
(CA) setting and to further train the CA eye relative to clock (CK),
REF
values latched at the receiver on the CA bus are asynchronously output to the DQ bus.
6. To exit Command Bus Training mode, drive CKE HIGH, and after time tVREF_LONG issue the MRW-1
command followed by the MRW-2 command to set MR13 OP[0]=0 . After time tMRW the LPDDR4-SDRAM is
B
ready for normal operation. After training exit the LPDDR4-SDRAM will automatically switch back to the
FSP-OP registers that were in use prior to training.
Command Bus Training may executed from IDLE or Self Refresh states. When executing CBT within the Self
Refresh state, the SDRAM must not be a power down state (i.e. CKE must be HIGH prior to training entry).
Command Bus Training entry and exit is the same, regardless of the SDRAM state from which CBT is initiated.
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Training Sequence for single-rank systems
Note that a example shown here is assuming an initial low-frequency, no-terminating operating point, training a
high-frequency, terminating operating point. The green text is low-frequency, magenta text is high-frequency. Any
operating point may be trained from any known good operating point.
1. Set MR13 OP[6]=1 to enable writing to Frequency Set Point ‘y’ (FSP-WR[y]) (or FSP-OP[x], See note).
B
2. Write FSP-WR[y] (or FSP-WR[x]) registers for all channels to set up high-frequency operating parameters.
3. Issue MRW-1 and MRW-2 commands to enter Command Bus Training mode.
4. Drive CKE LOW, and change CK frequency to the high-frequency operating point.
5. Perform Command Bus Training (V
CA, CS, and CA).
REF
6. Exit training, a change CK frequency to the low-frequency operating point prior to driving CKE HIGH, then issue
MRW-1 and MRW-2 commands. When CKE is driven HIGH, the SDRAM will automatically switch back to the
FSP-OP registers that were in use prior to training (i.e. trained values are not retained by the SDRAM).
7. Write the trained values to FSP-WR[y] (or FSP-WR[x]) by issuing MRW-1 and MRW-2 commands to the
SDRAM and setting all applicable mode register parameters.
8. Issue MRW-1 and MRW-2 commands to switch to FSP-OP[y] (or FSP-OP[x]), to turn on termination, and
change CK frequency to the high frequency operating point. At this point the Command Bus is trained and you
may proceed to other training or normal operation.
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Training Sequence for multi-rank systems
Note that a example shown here is assuming an initial low-frequency operating point, training a high-frequency
operating point. The green text is low-frequency, magenta text is high-frequency. Any operating point may be
trained from any known good operating point.
1. Set MR13 OP[6]=1 to enable writing to Frequency Set Point ‘y’ (FSP-WR[y]) (or FSP-WR[x], See Note).
B
2. Write FSP-WR[y] (or FSP-WR[x]) registers for all channels and ranks to set up high frequency operating
parameters.
3. Read MR0 OP[7] on all channels and ranks to determine which die are terminating, signified by
MR0 OP[7]=1 .
B
4. Issue MRW-1 and MRW-2 commands to enter Command Bus Training mode on the terminating rank.
5. Drive CKE LOW on the terminating rank (or all ranks), and change CK frequency to the high-frequency
operating point.
6. Perform Command Bus Training on the terminating rank (V
CA, CS, and CA).
REF
7. Exit training by driving CKE HIGH, change CK frequency to the low-frequency operating point, and issue
MRW-1 and MRW-2 commands to write the trained values to FSP-WR[y] (or FSP-WR[x]). When CKE is driven
HIGH, the SDRAM will automatically switch back to the FSP-OP registers that were in use prior to training (i.e.
trained values are not retained by the SDRAM).
8. Issue MRW-1 and MRW-2 command to enter training mode on the non-terminating rank (but keep CKE HIGH)
9. Issue MRW-1 and MRW-2 commands to switch the terminating rank to FSP-OP[y] (or FSP-OP[x]), to turn on
termination, and change CK frequency to the high frequency operating point.
10. Drive CKE LOW on the non-terminating (or all) ranks. The non-terminating rank(s) will now be using FSP-OP[y]
(or FSP-OP[x]).
11. Perform Command Bus Training on the non-terminating rank (V
CA, CS, and CA).
REF
12. Issue MRW-1 and MRW-2 commands to switch the terminating rank to FSP-OP[x] (or FSP-OP[y]) to turn off
termination.
13. Exit training by driving CKE HIGH on the non-terminating rank, change CK frequency to the low-frequency
operating point, and issue MRW-1 and MRW-2 commands. When CKE is driven HIGH, the SDRAM will
automatically switch back to the FSP-OP registers that were in use prior to training (i.e. trained values are not
retained by the SDRAM).
14. Write the trained values to FSP-WR[y] (or FSP-WR[x]) by issuing MRW-1 and MRW-2 commands to the
SDRAM and setting all applicable mode register parameters.
15. Issue MRW-1 and MRW-2 commands to switch the terminating rank to FSP-OP[y] (or FSP-OP[x]), to turn on
termination, and change CK frequency to the high frequency operating point. At this point the Command Bus is
trained for both ranks and you may proceed to other training or normal operation.
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Relation between CA input pin DQ output pin.
Mapping of CA Input pin and DQ Output pin.
Mapping
CA Number
DQ Number
CA5
CA4
CA3
CA2
CA1
CA0
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
Timing Diagram
The basic Timing diagrams of Command Bus Training are shown in the following figures.
Entering Command Bus Training Mode and CA Training Pattern Input
and Output with VREFCA Value Update
Notes:
1. After tCKELCK clock can be stopped or frequency changed any time.
2. The input clock condition should be satisfied tCKPRECS and tCKPSTCS.
3. Continue to Drive CK and Hold CS pins low until tCKELCK after CKE is low (which disables command decoding).
4. DRAM may or may not capture first rising/falling edge of DQS/ due to an unstable first rising edge. Hence provide at least
consecutive 2 pulses of DQS signal input is required in every DQS input signal at capturing DQ[6:0] signals. The captured value of DQ6:0
signal level by each DQS edges are overwritten at any time and the DRAM updates its VREFca setting of MR12 temporary after time
tVREFca_Long.
5. tVREF_LONG may be reduced to tVREF_SHORT if the following conditions are met: 1) The new Vref setting is a single step above or
below the old Vref setting, and 2) The DQS pulses a single time, or the new Vref setting value on DQ[6:0] is static and meets
tDSTRAIN/tDHTRAIN for every DQS pulse applied.
6. When CKE is driven LOW, the SDRAM will switch its FSP-OP registers to use the alternate (i.e. non-active) set. Example: If the SDRAM is
currently using FSP-OP[0], then it will switch to FSP-OP[1] when CKE is driven LOW. All operating parameters should be written to the
alternate mode registers before entering Command Bus Training to ensure that ODT settings, RL/WL/nWR setting, etc., are set to the
correct values. If the alternate FSP-OP has ODT_CA disabled then termination will not enable in CA Bus Training mode. If the ODT_CA
pad is bonded to Vss, ODT_CA termination will never enable for that die.
7. When CKE is driven low in Command Bus Training mode, the LPDDR4-SDRAM will change operation to the alternate FSP, i.e. the
inverse of the FSP programmed in the FSP-OP mode register.
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Consecutive VREFCA Value Update
Notes:
1. After tCKELCK clock can be stopped or frequency changed any time.
2. The input clock condition should be satisfied tCKPRECS.
3. Continue to Drive CK and Hold CS pins low until tCKELCK after CKE is low (which disables command decoding).
4. DRAM may or may not capture first rising/falling edge of DQS_t/c due to an unstable first rising edge. Hence provide at least
consecutive 2 pulses of DQS signal input is required in every DQS input signal at capturing DQ6:0 signals.
The captured value of DQ6:0 signal level by each DQS edges are overwritten at any time and the DRAM updates its VREFca setting of
MR12 temporary after time tVREFca_Long.
5. tVREF_LONG may be reduced to tVREF_SHORT if the following conditions are met: 1) The new Vref setting is a single step above or
below the old Vref setting, and 2) The DQS pulses a single time, or the new Vref setting value on DQ[6:0] is static and meets
tDSTRAIN/tDHTRAIN for every DQS pulse applied.
6. When CKE is driven LOW, the SDRAM will switch its FSP-OP registers to use the alternate (i.e. non-active) set. Example: If the SDRAM is
currently using FSP-OP[0], then it will switch to FSP-OP[1] when CKE is driven LOW. All operating parameters should be written to the
alternate mode registers before entering Command Bus Training to ensure that ODT settings, RL/WL/nWR setting, etc., are set to the
correct values. If the alternate FSP-OP has ODT_CA disabled then termination will not enable in CA Bus Training mode. If the ODT_CA
pad is bonded to Vss, ODT_CA termination will never enable for that die.
7. When CKE is driven low in Command Bus Training mode, the LPDDR4-SDRAM will change operation to the alternate FSP, i.e. the
inverse of the FSP programmed in the FSP-OP mode register.
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Exiting Command Bus Training Mode with Valid Command
Notes:
1. Clock can be stopped or frequency changed any time before tCKCKEH. CK must meet tCKCKEH before CKE is driven high.
When CKE is driven high the clock frequency must be returned to the original frequency (the frequency corresponding to the FSP at
which Command Bus Training mode was entered)
2. CS must be Deselect (low) tCKCKEH before CKE is driven high.
3. When CKE is driven high, the SDRAM’s ODT_CA will revert to the state/value defined by FSP-OP prior to Command Bus Training mode
entry, i.e. the original frequency set point (FSP-OP, MR13-OP[7]).
Example: If the SDRAM was using FSP-OP[1] for training, then it will switch to FSP-OP[0] when CKE is driven HIGH.
4. Training values are not retained by the SDRAM, and must be written to the FSP-OP register set before returning to operation at the
trained frequency.
Example: VREF(ca) will return to the value programmed in the original set point.
5. When CKE is driven high the LPDDR4-SDRAM will revert to the FSP in operation when Command Bus Training mode was entered.
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Exiting Command Bus Training Mode with Power Down Entry
Notes:
1. Clock can be stopped or frequency changed any time before tCKCKEH. CK must meet tCKCKEH before CKE is driven high. When CKE is
driven high the clock frequency must be returned to the original frequency (the frequency corresponding to the FSP at which
Command Bus Training mode was entered)
2. CS must be Deselect (low) tCKCKEH before CKE is driven high.
3. When CKE is driven high, the SDRAM’s ODT_CA will revert to the state/value defined by FSP-OP prior to Command Bus Training mode
entry, i.e. the original frequency set point (FSP-OP, MR13-OP[7]).
Example: If the SDRAM was using FSP-OP[1] for training, then it will switch to FSP-OP[0] when CKE is driven HIGH.
4. Training values are not retained by the SDRAM, and must be written to the FSP-OP register set before returning to operation at the
trained frequency. Example: VREF(ca) will return to the value programmed in the original set point.
5. When CKE is driven high the LPDDR4-SDRAM will revert to the FSP in operation when Command Bus Training mode was entered.
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Command Bus Training AC Timing Table
Data Rate
Min/
Max
Parameter
Symbol
Unit Notes
533/1066/1600/2133/2667/
3200/3733/4267
Command Bus Training Timing
Valid Clock Requirement
tCKELCK
Min
max(5ns, 5nCK)
tCK
after CKE Input low
Data Setup for VREF Training Mode
Data Hold forVREF Training Mode
Asynchronous Data Read
tDStrain
tDHtrain
tADR
Min
Min
Max
2
2
ns
ns
ns
20
CA Bus Training Command
tCACD
tDQSCKE
tCAENT
Min
Min
Min
RU(tADR/tCK)
tCK
ns
2
1
to CA Bus Training Command Delay
Valid Strobe Requirement before CKE Low
First CA Bus Training
10
250
ns
Command Following CKE Low
VREF Step Time – multiple steps
VREF Step Time – one step
tVREFCA_LONG Max
tVREFCA_SHORT Max
250
80
ns
ns
-
Valid Clock Requirement before CS High
Valid Clock Requirement after CS High
Minimum delay from
tCKPRECS
tCKPSTCS
Min 2tCK + tXP (tXP = max(7.5ns, 5nCK))
Min
max(7.5ns, 5nCK))
-
tCS_VREF
Min
2
tCK
ns
CS to DQS toggle in command bus training
Minimum delay from
tCKEHDQS
10
CKE High to Strobe High Impedance
Clock and Command Valid before CKE High
CA Bus Training CKE High to DQ Tri-state
ODT turn-on Latency from CKE
ODT turn-off Latency from CKE
tCKCKEH
tMRZ
Min
Min
max(1.75ns, 3nCK)
tCK
ns
ns
ns
-
1.5
20
tCKELODTon Min
tCKELODToff Min
tXCBT_Short Min
tXCBT_Middle Min
tXCBT_Long Min
20
max(5nCK, 200ns)
max(5nCK, 200ns)
max(5nCK, 250ns)
3
3
3
Exit Command Bus Training Mode
to next vaild command delay
-
-
Notes:
1. DQS has to retain a low level during tDQSCKE period, as well as has to retain a high level.
2. If tCACD is violated, the data for samples which violate tCACD will not be available, except for the last sample (where tCACD after this
sample is met). Valid data for the last sample will be available after tADR.
3. Exit Command Bus Training Mode to next valid command delay Time depends on value of VREF(CA) setting:
MR12 OP[5:0] and VREF(CA) Range: MR12 OP[6] of FSP-OP 0 and 1. The details are shown in tFC value mapping.
Additionally exit Command Bus Training Mode to next valid command delay Time may affect VREF(DQ) setting.
Settling time of VREF(DQ) level is same as VREF(CA) level.
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Command Bus Trainging for Byte (x8) mode
The LPDDR4-SDRAM command bus must be trained before enabling termination for high-frequency
operation. LPDDR4 provides an internal VREF(ca) that defaults to a level suitable for un-terminated, lowfrequency
operation, but the VREF(ca) must be trained to achieve suitable receiver voltage margin for
terminated, high-frequency operation. The training methodology described here centers the internal
VREF(ca) in the CAdata eye and at the same time allows for timing adjustments of the CS and CA signals
to meet setup/hold requirements. Because it can be difficult to capture commands prior to training the CA
inputs, the training methodology described here uses a minimum of external commands to enter, train, and
exit the Command Bus Training methodology.
NOTES: it is up to the system designer to determine what constitutes “low-frequency” and “high-frequency” based on the capabilities of
the system. Low-frequency should then be defined as an operating frequency in which the system can reliably communicate with
the SDRAM before Command Bus Training is executed.
The Byte mode LPDDR4-SDRAM (x8 2ch.) is supported two Command Bus Training (CBT) modes and
their feature is as follows.
Mode1: DQ[6:0] only uses as output and VrefCA input procedure removes from CBT function of x16 2ch. device.
Mode2: The status (Input or Output) of DQ[6:0] is controlled by DQ[7] pin.
Above-mentioned CBT mode is selected by MRx [OPy].
The LPDDR4-SDRAM die has a bond-pad (ODT-CA) for multi-rank operation. In a multi-rank system, the
terminating rank should be trained first, followed by the nonterminating rank(s). See the ODT section for
more information.
The corresponding DQ pins in this definition depends on the package configuration. DQ0 becomes DQ8 in
some cases, as well as DQ1 to DQ6.
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Training Mode 1
The LPDDR4-SDRAM uses Frequency Set-Points to enable multiple operating settings for the die. The
LPDDR4-SDRAM defaults to FSP-OP[0] at power-up, which has the default settings to operate in unterminated,
low-frequency environments. Prior to training, the mode register settings should be configured
by setting MR13 OP[6]=1B (FSP-WR[1]) and setting all other mode register bits including MR12 OP[6:0]
(VREF(CA) Range and Setting) for FSP-OP[1] to the desired settings for high-frequency operation. Prior to
entering Command Bus Training, the SDRAM will be operating from FSP-OP[x]. Upon Command Bus
Training entry when CKE is driven LOW, the LPDDR4-SDRAM will automatically switch to the alternate
FSP register set (FSP-OP[y]) and use the alternate register settings during training. Upon training exit when CKE
is driven HIGH, the LPDDR4-SDRAM will automatically switch back to the original FSP register set (FSP-OP[x]),
returning to the “known-good” state that was operating prior to training.
1. To set MRx OP[y] = 0: CBT Training Mode 1
2. To enter Command Bus Training mode, issue a MRW-1 command followed by a MRW-2 command to
set MR13 OP[0]=1 (Command Bus Training Mode Enabled).
B
3. After time tMRD, CKE may be set LOW, causing the LPDDR4-SDRAM to switch from FSP-OP[x] to
FSP-OP[y], and completing the entry into Command Bus Training mode.
A status of DQS, , DQ and DMI are as follows, and DQ ODT state will be followed Frequency
Set Point function except output pins.
4. At time tCAENT later, LPDDR4 SDRAM can accept to input CA training pattern via CA bus.
5. To verify that the receiver has the correct VREF(ca) setting and to further train the CA eye relative to
clock (CK), values latched at the receiver on the CA bus are asynchronously output to the DQ bus.
6. To exit Command Bus Training mode, drive CKE HIGH, and after time tXCBT issue the MRW-1
command followed by the MRW-2 command to set MR13 OP[0]=0 . After time tMRW the LPDDR4-
B
SDRAM is ready for normal operation. After training exit the LPDDR4-SDRAM will automatically
switch back to the FSP-OP registers that were in use prior to training.
Command Bus Training may executed from IDLE or Self Refresh states. When executing CBT within the
Self Refresh state, the SDRAM must not be in a power down state (i.e. CKE must be HIGH prior to training
entry). Command Bus Training entry and exit is the same, regardless of the SDRAM state from which CBT
is initiated.
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Training Sequence of mode 1 for single-rank systems
Note that a example shown here is assuming an initial low-frequency, no-terminating operating point, training
a high-frequency, terminating operating point. The green text is low-frequency, magenta text is high-frequency.
Any operating point may be trained from any known good operating point.
1. Set MR13 OP[6]=1 to enable writing to Frequency Set Point ‘y’ (FSP-WR[y]) (or FSP-OP[x], See
B
note).
2. Write FSP-WR[y] (or FSP-WR[x]) registers for all channels to set up high-frequency operating
parameters including VREF(CA) Range and Setting.
3. Issue MRW-1 and MRW-2 commands to enter Command Bus Training mode.
4. Drive CKE LOW, and change CK frequency to the high-frequency operating point.
5. Perform Command Bus Training (CS, and CA).
6. Exit training, a change CK frequency to the low-frequency operating point prior to driving CKE HIGH,
then issue MRW-1 and MRW-2 commands. When CKE is driven HIGH, the SDRAM will automatically
switch back to the FSP-OP registers that were in use prior to training (i.e. trained values are not
retained by the SDRAM).
7. Issue MRW-1 and MRW-2 commands to switch to FSP-OP[y] (or FSP-OP[x]), to turn on termination,
and change CK frequency to the high frequency operating point. At this point the Command Bus is
trained and you may proceed to other training or normal operation.
Note: Repeat steps 1 through 2 (Table- Timing constraints for Same bank: DQ ODT is Enabled) until the proper VREFCA level is
established.
Command Bus Training Steps.
Step
Mode
1
Normal
Low
0
2
3(1)
Normal
Low
0
4(2)
CBT
CBT
Operation Frequency
FSP-OP
High
1
High
1
FSP-WR
1
1
1
1
Training Pattern Input
then comparison
between output Data
and expected data.
Training Pattern Input
then comparison
between output Data
and expected data.
VREFCA Range/Value
Setting via MRW
VREFCA Range/Value
Setting via MRW
Operation
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Training Sequence of mode 1 for multi-rank systems
Note that a example shown here is assuming an initial low-frequency operating point, training a high-frequency
operating point. The green text is low-frequency, magenta text is high-frequency. Any operating
point may be trained from any known good operating point.
1. Set MR13 OP[6]=1 to enable writing to Frequency Set Point ‘y’ (FSP-WR[y]) (or FSP-WR[x], See
B
Note).
2. Write FSP-WR[y] (or FSP-WR[x]) registers for all channels and ranks to set up high frequency
operating parameters including VREF(CA) Range and Setting.
3. Read MR0 OP[7] on all channels and ranks to determine which die are terminating, signified by
MR0 OP[7]=1 .
B
4. Issue MRW-1 and MRW-2 commands to enter Command Bus Training mode on the terminating rank.
5. Drive CKE LOW on the terminating rank (or all ranks), and change CK frequency to the highfrequency
operating point.
6. Perform Command Bus Training on the terminating rank (CS, and CA).
7. Exit training by driving CKE HIGH, change CK frequency to the low-frequency operating point, and
issue MRW-1 and MRW-2 commands to write the trained values to FSP-WR[y] (or FSP-WR[x]). When
CKE is driven HIGH, the SDRAM will automatically switch back to the FSP-OP registers that were in
use prior to training.
8. Issue MRW-1 and MRW-2 command to enter training mode on the non-terminating rank (but keep
CKE HIGH)
9. Issue MRW-1 and MRW-2 commands to switch the terminating rank to FSP-OP[y] (or FSP-OP[x]), to
turn on termination, and change CK frequency to the high frequency operating point.
10. Drive CKE LOW on the non-terminating (or all) ranks. The non-terminating rank(s) will now be using
FSP-OP[y] (or FSP-OP[x]).
11. Perform Command Bus Training on the non-terminating rank (CS, and CA).
12. Issue MRW-1 and MRW-2 commands to switch the terminating rank to FSP-OP[x] (or FSP-OP[y]) to
turn off termination.
13. Exit training by driving CKE HIGH on the non-terminating rank, change CK frequency to the lowfrequency
operating point, and issue MRW-1 and MRW-2 commands. When CKE is driven HIGH, the
SDRAM will automatically switch back to the FSP-OP registers that were in use prior to training.
14. Write the trained values to FSP-WR[y] (or FSP-WR[x]) by issuing MRW-1 and MRW-2 commands to
the SDRAM and setting all applicable mode register parameters.
15. Issue MRW-1 and MRW-2 commands to switch the terminating rank to FSP-OP[y] (or FSP-OP[x]), to
turn on termination, and change CK frequency to the high frequency operating point. At this point the
Command Bus is trained for both ranks and you may proceed to other training or normal operation.
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8Gb: NT6AN256T32AV
Relation between CA input pin DQ output pin for mode 1
Mapping of CA Input pin and DQ Output pin.
Mapping
CA Number
DQ Number
CA5
CA4
CA3
CA2
CA1
CA0
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
Timing Diagram for mode 1
The basic Timing diagrams of Command Bus Training are shown in the following figures.
Entering Command Bus Training Mode and CA Training Pattern Input and Output
Notes:
1. After tCKELCK clock can be stopped or frequency changed any time.
2. The input clock condition should be satisfied tCKPRECS and tCKPSTCS.
3. Continue to Drive CK and Hold CA & CS pins low until tCKELCK after CKE is low (which disables command decoding).
4. When CKE is driven LOW, the SDRAM will switch its FSP-OP registers to use the alternate (i.e. non-active) set. Example: If the SDRAM is
currently using FSP-OP[0], then it will switch to FSP-OP[1] when CKE is driven LOW. All operating parameters should be written to the
alternate mode registers before entering Command Bus Training to ensure that ODT settings, RL/WL/nWR setting, etc., are set to the
correct values. If the alternate FSP-OP has ODT_CA disabled then termination will not enable in CA Bus Training mode. If the ODT_CA
pad is bonded to Vss or floating, ODT_CA termination will never enable for that die.
5. When CKE is driven low in Command Bus Training mode, the LPDDR4-SDRAM will change operation to the alternate FSP, i.e.
non-active FSP programmed in the FSP-OP mode register.
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Exiting Command Bus Training Mode with Valid Command
Notes:
1. CK must meet tCKCKEH before CKE is driven high.
When CKE is driven high the clock frequency must be returned to the original frequency (the frequency corresponding to the FSP at
which Command Bus Training mode was entered)
2. CS and CA[5:0] must be Deselect (all low) tCKCKEH before CKE is driven high.
3. When CKE is driven high, the SDRAM’s ODT_CA will revert to the state/value defined by FSP-OP prior to Command Bus Training mode
entry, i.e. the original frequency set point (FSP-OP, MR13-OP[7]).
Example: If the SDRAM was using FSP-OP[1] for training, then it will switch to FSP-OP[0] when CKE is driven HIGH.
4. When CKE is driven high the LPDDR4-SDRAM will revert to the FSP in operation when Command Bus Training mode was entered.
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8Gb: NT6AN256T32AV
Exiting Command Bus Training Mode with Power Down Entry
Notes:
1. Clock can be stopped or frequency changed any time before tCKCKEH. CK must meet tCKCKEH before CKE is driven high.
When CKE is driven high the clock frequency must be returned to the original frequency (the frequency corresponding to the FSP at
which Command Bus Training mode was entered)
2. CS and CA[5:0] must be Deselect (all low) tCKCKEH before CKE is driven high.
3. When CKE is driven high, the SDRAM’s ODT_CA will revert to the state/value defined by FSP-OP prior to Command Bus Training mode
entry, i.e. the original frequency set point (FSP-OP, MR13-OP[7]).
Example: If the SDRAM was using FSP-OP[1] for training, then it will switch to FSP-OP[0] when CKE is driven HIGH.
4. When CKE is driven high the LPDDR4-SDRAM will revert to the FSP in operation when Command Bus Training mode was entered.
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8Gb: NT6AN256T32AV
Command Bus Training AC Timing Table for Mode 1
Data Rate
Min/
Max
Parameter
Symbol
Unit Notes
533/1066/1600/2133/2667/
3200/3733/4267
Command Bus Training Timing
Clock and Command Valid after CKE Low
Asynchronous Data Read
tCKELCK
tADR
Min
Max
max(7.5ns, 3nCK)
20
tCK
ns
CA Bus Training Command
tCACD
Min
Min
RU(tADR/tCK )
250
tCK
ns
2
to CA Bus Training Command Delay
First CA Bus Training
tCAENT
Command Following CKE Low
Valid Clock Requirement before CS High
Valid Clock Requirement after CS High
Clock and Command Valid before CKE High
CA Bus Training CKE High to DQ Tri-state
ODT turn-on Latency from CKE
ODT turn-off Latency from CKE
tCKPRECS
tCKPSTCS
tCKCKEH
tMRZ
Min 2tCK + tXP (tXP = max(7.5ns, 5nCK))
-
-
Min
Min
Min
max(7.5ns, 5nCK))
2
tCK
ns
ns
ns
-
1.5
20
tCKELODTon Min
tCKELODToff Min
tXCBT_Short Min
tXCBT_Middle Min
tXCBT_Long Min
20
max(5nCK, 200ns)
max(5nCK, 200ns)
max(5nCK, 250ns)
3
3
3
Exit Command Bus Training Mode
to next vaild command delay
-
-
Notes:
1. If tCACD is violated, the data for samples which violate tCACD will not be available, except for the last sample (where tCACD after this
sample is met). Valid data for the last sample will be available after tADR.
2. Exit Command Bus Training Mode to next valid command delay Time depends on value of VREF(CA) setting:
MR12 OP[5:0] and VREF(CA) Range: MR12 OP[6] of FSP-OP 0 and 1. The details are shown in tFC value mapping.
Additionally exit Command Bus Training Mode to next valid command delay Time may affect VREF(DQ) setting.
Settling time of VREF(DQ) level is same as VREF(CA) level.
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Training Mode 2
The LPDDR4-SDRAM uses Frequency Set-Points to enable multiple operating settings for the die. The
LPDDR4-SDRAM defaults to FSP-OP[0] at power-up, which has the default settings to operate in unterminated,
low-frequency environments. Prior to training, the mode register settings should be configured by
setting MR13 OP[6]=1 (FSP-WR[1]) and setting all other mode register bits for FSP-OP[1] to the desired
B
settings for high-frequency operation. Prior to entering Command Bus Training, the SDRAM will be operating
from FSP-OP[x]. Upon Command Bus Training entry when CKE is driven LOW, the LPDDR4-SDRAM
will automatically switch to the alternate FSP register set (FSP-OP[y]) and use the alternate register settings
during training. (See note 6 in “MR22 Register Information”, example refers to section “Package Block Diagram”
for more information on FSP-OP register sets). Upon training exit when CKE is driven HIGH, the PDDR4-SDRAM
will automatically switch back to the original FSP register set (FSP-OP[x]), returning to the “known-good” state that
was operating prior to training. The training values for VREFCA are not retained by the DRAM in FSP-OP[y]
registers, and must be written to the registers after training exit.
1. To set MR12 OP[7] = 1: CBT Training Mode 2
2. To enter Command Bus Training mode, issue a MRW-1 command followed by a MRW-2 command to
set MR13 OP[0]=1 (Command Bus Training Mode Enabled).
B
3. After time tMRD, CKE may be set LOW, causing the LPDDR4-SDRAM to switch from FSP-OP[x] to
FSP-OP[y], and completing the entry into Command Bus Training mode.
A status of DQS, , DQ and DMI are as follows, and ODT state of DQS, , DQ and
DMI will be followed by MR11 OP[2:0]: DQ ODT and MR13 OP[7]: FSP-OP except when pin is output
or transition state.
- DQS, become input pins for capturing DQ[6:0] levels by its toggling. The ODT for the DQS, is
always enabled during CBT Mode 2. The DQS, ODT use the value specified by MR11 OP[2:0]: DQ
ODT and MR13 OP[7]: FSP-OP.
- DQ[5:0] become input pins for setting VREFCA Level during tDStrain + tDQSICYC + tDHtrain period.
- DQ[5:0] become output pins to feedback its capturing value via command bus by CS signal during
tADVW period.
- DQ[6] becomes a input pin for setting VREFCA Range during tDStrain + tDQSICYC + tDHtrain period.
- DQ[6] becomes an output pin during tADVW period and the output data is meaningless.
- DQ[7] becomes an output pin to indicate the meaningful data output by its toggling during tADVW period.
The meaningful data is its capturing value via command bus by CS signal. DQ[7] status except tADVW
period becomes input or disable, this state is vendor specific, as well as ODT behavior.
- DMI become Input, output or disable, The DMI state is vendor specific.
4. At time tCAENT later, LPDDR4 SDRAM can accept to change its V
CA Range and Value using input
REF
signals of DQS, and DQ[6:0] from existing value that’s setting via MR12 OP[6:0]. The mapping between
MR12 OP code and DQs is shown in following table. At least one V
to next training steps.
CA setting is required before proceed
REF
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Mapping of CA Input pin and DQ Output pin.
Mapping
OP3
MR12 OP Code
DQ Number
OP6
DQ6
OP5
DQ5
OP4
DQ4
OP2
DQ2
OP1
DQ1
OP0
DQ0
DQ3
5. The new VREFCA value must “settle” for time tVREF_LONG before attempting to latch CA information.
6. To verify that the receiver has the correct VREFCA setting and to further train the CA eye relative to clock
(CK), values latched at the receiver on the CA bus are asynchronously output to the DQ bus.
7. Command followed by the MRW-2 command to set MR13 OP[0]=0B. After time tMRW the LPDDR4-SDRAM
is ready for normal operation. After training exit the LPDDR4-SDRAM will automatically switch back to the
FSP-OP registers that were in use prior to training.
Command Bus Training may executed from IDLE or Self Refresh states. When executing CBT within the
Self Refresh state, the SDRAM must not be a power down state (i.e. CKE must be HIGH prior to training
entry). Command Bus Training entry and exit is the same, regardless of the SDRAM state from which CBT
is initiated.
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Training Sequence of mode 2 for single-rank systems
Note that a example shown here is assuming an initial low-frequency, no-terminating operating point, training
a high-frequency, terminating operating point. The green text is low-frequency, magenta text is high-frequency.
Any operating point may be trained from any known good operating point. This example is
assuming on the following condition. Frequency Set Point ‘x’ for low frequency operation and Frequency
Set Point ‘y’ for High frequency operation.
1. Set MR13 OP[6]=1 to enable writing to Frequency Set Point ‘y’ (FSP-WR[y]).
B
2. Write FSP-WR[y] registers for all channels to set up high-frequency operating parameters.
3. Issue MRW-1 and MRW-2 commands to enter Command Bus Training mode.
4. Drive CKE LOW, then change CK frequency to the high-frequency operating point.
5. Perform Command Bus Training (VREFCA, CS, and CA).
6. Exit training, a change CK frequency to the low-frequency operating point prior to driving CKE HIGH,
then issue MRW-1 and MRW-2 commands to exit Command Bus Training mode. When CKE is driven
HIGH, the SDRAM will automatically switch back to the FSP-OP registers that were in use prior to
training (i.e. trained values are not retained by the SDRAM).
7. Write the trained values to FSP-WR[y] by issuing MRW-1 and MRW-2 commands to the SDRAM and
setting all applicable mode register parameters.
8. Issue MRW-1 and MRW-2 commands to switch to FSP-OP[y] to turn on termination, and change CK
frequency to the high frequency operating point. At this point the Command Bus is trained and you
may proceed to other training or normal operation.
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8Gb: NT6AN256T32AV
Training Sequence of mode 2 for multi-rank systems
Note that a example shown here is assuming an initial low-frequency operating point, training a high-frequency
operating point. The green text is low-frequency, magenta text is high-frequency. Any operating
point may be trained from any known good operating point. This example is assuming on the following
condition. Frequency Set Point ‘x’ for low frequency operation and Frequency Set Point ‘y’ for High frequency
operation.
1. Set MR13 OP[6]=1 to enable writing to Frequency Set Point ‘y’ (FSP-WR[y]).
B
2. Write FSP-WR[y] registers for all channels and ranks to set up high frequency operating parameters.
3. Read MR0 OP[7] on all channels and ranks to determine which die are terminating, signified by MR0
OP[7]=1B.
4. Issue MRW-1 and MRW-2 commands to enter Command Bus Training mode on the terminating rank.
5. Drive CKE LOW on the terminating rank (or all ranks), and change CK frequency to the high
frequency operating point.
6. Perform Command Bus Training on the terminating rank (VREFCA, CS, and CA).
7. Exit training by driving CKE HIGH, change CK frequency to the low-frequency operating point, and
issue MRW-1 and MRW-2 commands to exit Command Bus Training mode. When CKE is driven
HIGH, the SDRAM will automatically switch back to the FSP-OP registers that were in use prior to
training (i.e. trained values are not retained by the SDRAM).
8. Write the trained values to FSP-WR[y] by issuing MRW-1 and MRW-2 commands to the SDRAM and
setting all applicable mode register parameters.
9. Issue MRW-1 and MRW-2 command to enter training mode on the non-terminating rank (but keep
CKE HIGH).
10. Issue MRW-1 and MRW-2 commands to switch the terminating rank to FSP-OP[y], to turn on
termination, and change CK frequency to the high frequency operating point.
11. Drive CKE LOW on the non-terminating (or all) ranks. The non-terminating rank(s) will now be using
FSP-OP[y].
12. Perform Command Bus Training on the non-terminating rank (VREFCA, CS, and CA).
13. Issue MRW-1 and MRW-2 commands to switch the terminating rank to FSP-OP[x] to turn off termination.
14. Exit training by driving CKE HIGH on the non-terminating rank, change CK frequency to the low
frequency operating point, and issue MRW-1 and MRW-2 commands to exit Command Bus Training
mode. When CKE is driven HIGH, the SDRAM will automatically switch back to the FSP-OP registers
that were in use prior to training (i.e. trained values are not retained by the SDRAM).
15. Write the trained values to FSP-WR[y] by issuing MRW-1 and MRW-2 commands to the SDRAM and
setting all applicable mode register parameters.
16. Issue MRW-1 and MRW-2 commands to switch the terminating rank to FSP-OP[y], to turn on
termination, and change CK frequency to the high frequency operating point. At this point the
Command Bus is trained for both ranks and you may proceed to other training or normal operation.
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8Gb: NT6AN256T32AV
Relation between CA input pin DQ output pin for mode 2
Mapping of CA Input pin and DQ Output pin.
Mapping
CA Number
DQ Number
CA5
CA4
CA3
CA2
CA1
CA0
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
Timing Diagram for mode 2
The basic Timing diagrams of Command Bus Training are shown in the following figures.
Entering Command Bus Training Mode and CA Training Pattern Input with VrefCA Value Update
Notes:
1. After tCKELCK clock can be stopped or frequency changed any time.
2. The input clock condition should be satisfied tCKPRECS and tCKPSTCS.
3. Continue to Drive CK and Hold CS pins low until tCKELCK after CKE is low (which disables command decoding).
4. The DRAM may or may not capture the first rising/falling edge of DQS_t/c due to an unstable first rising edge. At least 2 consecutive
pulses of DQS signal input are required for every DQS input signal when capturing DQ[6:0] signals.
The captured value of the DQ[6:0] signal level by each DQS edge is overwritten at any time. The DRAM updates its VREFca setting of
MR12 temporary, after time tVREFca_Long.
5. tVREFca_Long may be reduced to tVREFca_Middle or tVREFca_Short.
6. When CKE is driven LOW, the SDRAM will switch its FSP-OP registers to use the alternate (i.e. non-active) set. Example: If the SDRAM is
currently using FSP-OP[0], then it will switch to FSP-OP[1] when CKE is driven LOW. All operating parameters should be written to the
alternate mode registers before entering Command Bus Training to ensure that ODT settings, RL/WL/nWR setting, etc., are set to the
correct values. If the alternate FSP-OP has ODT_CA disabled then termination will not enable in CA Bus Training mode. If the ODT_CA
pad is bonded to Vss, ODT_CA termination will never enable for that die.
7. When CKE is driven low in Command Bus Training mode, the LPDDR4-SDRAM will change operation to the alternate FSP, i.e.
non-active FSP programmed in the FSP-OP mode register
8. tDStrai+ tDQSICYC + tDHtrain period on DQ7 become Input or disable, this state during CBT Mode 2 is vendor specific.
9. DMI become Input, output or disable, The DMI state during CBT Mode 2 is vendor specific
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CA pattern Input/Output to Vref setting Input
Notes:
1. The DRAM may or may not capture the first rising/falling edge of DQS_t/c due to an unstable first rising edge. At least 2 consecutive
pulses of DQS signal input are required for every DQS input signal when capturing DQ[6:0] signals.
The captured value of the DQ[6:0] signal level by each DQS edge is overwritten at any time. The DRAM updates its VREFca setting of
MR12 temporary, after time tVREFca_Long.
2. tVREFca_Long may be reduced to tVREFca_Middle or tVREFca_Short.
3. tDStrain + tDQSICYC + tDHtrain period on DQ7 become Input or disable, this state during CBT Mode 2 is vendor specific.
4. DMI become Input, output or disable, The DMI state during CBT Mode 2 is vendor specific.
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Consecutive CA training pattern Input/Output
Notes:
1. DMI become Input, output or disable, The DMI state during CBT Mode 2 is vendor specific.
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Exiting Command Bus Training Mode
Notes:
1. CK must meet tCKCKEH before CKE is driven high.
When CKE is driven high the clock frequency must be returned to the original frequency (the frequency corresponding to the FSP at
which Command Bus Training mode was entered)
2. CS and CA[5:0] must be all low tCKCKEH before CKE is driven high.
3. CKE must be held low from when CS transitions high to when tCBTRTW is satisfied. Exiting CBT mode is prohibited during this period.
4. When CKE is driven high, the SDRAM’s ODT_CA will revert to the state/value defined by FSP-OP prior to Command Bus Training mode
entry, i.e. the original frequency set point (FSP-OP, MR13-OP[7]).
Example: If the SDRAM was using FSP-OP[1] for training, then it will switch to FSP-OP[0] when CKE is driven HIGH.
5. Training values are not retained by the SDRAM, and must be written to the FSP-OP register set before returning to operation at the
trained frequency. Example: VREF(ca) will return to the value programmed in the original set point.
6. When CKE is driven high the LPDDR4-SDRAM will revert to the FSP in operation when Command Bus Training mode was entered.
7. DMI become Input, output or disable, The DMI state during CBT Mode 2 is vendor specific.
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DQS ODT Timing during Command Bus Training Mode 2
Notes:
1. After tCKELCK clock can be stopped or frequency changed any time.
2. Continue to Drive CK and Hold CS pins low until tCKELCK after CKE is low (which disables command decoding).
3. When CKE is driven low in Command Bus Training mode, the LPDDR4-SDRAM will change operation to the alternate FSP, i.e non-active
FSP programmed in the FSP-OP mode register.
4. CK must meet tCKCKEH before CKE is driven high.
When CKE is driven high the clock frequency must be returned to the original frequency (the frequency corresponding to the FSP at
which Command Bus Training mode was entered)
5. CS and CA[5:0] must be all low tCKCKEH before CKE is driven high.
6. When CKE is driven high the LPDDR4-SDRAM will revert to the FSP in operation when Command Bus Training mode was entered.
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Command Bus Training AC Timing Table for Mode 2
Data Rate
533/1066/1600/2133/2667/
Min/
Max
Parameter
Symbol
Unit Notes
3200/3733/4267
Command Bus Training Timing
Clock and Command Valid after CKE Low
Valid Clock Requirement before CS High
Valid Clock Requirement after CS High
Valid Strobe Requirement before CKE Low
First CA Bus Training
tCKELCK
tCKPRECS
tCKPSTCS
tDQSCKE
Min
max(5ns, 5nCK)
tCK
Min 2tck + tXP (tXP = max(7.5ns, 5nCK))
-
-
Min
Min
max(7.5ns, 5nCK))
10
ns
1
tCAENT
Min
250
ns
Command Following CKE Low
VREF Step Time – Long
Max
Max
Max
Min
Min
Min
Max
Min
Max
Max
Min
Min
Max
Min
Max
Min
Max
250
200
100
2
ns
ns
ns
ns
ns
Ns
ns
Ns
ns
ns
2
3
4
tVREFCA_LONG
tVREFCA_Middle
tVREFCA_SHORT
tDStrain
VREF Step Time – Middle
VREF Step Time – Short
Data Setup for VREF Training Mode
Data Hold forVREF Training Mode
tDHtrain
2
16
80
5
Asynchronous Data Read Valid Window
DQS Input period at CBT mode
tADVW
tDQSICYC
100
20
0
Asynchronous Data Read
tADR
high impedance time from CS High
tHZCBT
3
Asynchronous Data Read to DQ7 toggle
DQ7sample hold time
tAD2DQ7
tDQ7SH
tADSPW
10
10
60
3
Asynchronous Data Read Pulse Width
Hi-Z to asynchronous VrefCA valid data
10
tHZ2VREF
tCBTRTW
Min
Min
Max(10ns, 5nCK)
tCK
ns
Read to Write Delay at CBT mode
CA Bus Training Command to CA Bus
Training Command Delay
tCACD
Min
Max(110ns, 4nCK)
10
Minimum delay from
tCKEHDQS
tCKCKEH
Min
Min
ns
CKE High to Strobe High Impedance
Clock and Command Valid before CKE High
ODT turn-on Latency from CKE
max(1.75ns, 3nCK)
20
tCK
ns
tCKELODTon Max
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Data Rate
Min/
Max
Parameter
Symbol
Unit Notes
533/1066/1600/2133/2667/
3200/3733/4267
Command Bus Training Timing
ODT turn-off Latency from CKE for ODT_CA tCKELODToff Max
20
20
ns
ns
ODT turn-off Latency from CKE
tCKEHODToff Max
for ODT_DQ and DQS
ODT_DQ turn-off Latency from
tODToffCBT Max
20
ns
-
CS high during CB Training
ODT_DQ turn-on Latencyfrom
tODTonCBT Max
Max(10ns, 5nCK)
the end of Valid Data out
tXCBT_Short Min
Exit Command Bus Training Mode
tXCBT_Middle Min
max(5nCK, 200ns)
max(5nCK, 200ns)
max(5nCK, 250ns)
-
-
-
5
5
5
to next vaild command delay
tXCBT_Long Min
Notes:
1. DQS has to retain a low level during tDQSCKE period, as well as has to retain a high level.
2. VREFCA_Long is the time including up to VREFmin to VREFmax or VREFmax to VREFmin change across the VREFDQ Range in VREF
voltage.
3. VREF_Middle is at least 2 stepsizes increment/decrement change within the same VREFDQ range in VREF voltage.
4. VREF_Short is for a single stepsize increment/decrement change in VREF voltage.
5. Exit Command Bus Training Mode to next valid command delay Time depends on value of VREF(CA) setting: MR12 OP[5:0] and
VREF(CA) Range: MR12 OP[6] of FSP-OP 0 and 1. The details are shown in Table ‘tFC value mapping’.
Additionally exit Command Bus Training Mode to next valid command delay Time may affect VREF(DQ) setting. Settling time of
VREF(DQ)
level is same as VREF(CA) level.
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Frequency Set Point
Frequency Set-Points allow the LPDDR4-SDRAM CA Bus to be switched between two differing operating
frequencies, with changes in voltage swings and termination values, without ever being in an un-trained state
which could result in a loss of communication to the DRAM. This is accomplished by duplicating all CA Bus mode
register parameters, as well as other mode register parameters commonly changed with operating frequency.
These duplicated registers form two sets that use the same mode register addresses, with read/write access
controlled by MR bit FSP-WR (Frequency Set-Point Write/Read) and the DRAM operating point controlled by
another MR bit FSP-OP (Frequency Set-Point Operation). Changing the FSP-WR bit allows MR parameters to be
changed for an alternate Frequency Set-Point without affecting the LPDDR4-SDRAM's current operation. Once all
necessary parameters have been written to the alternate Set-Point, changing the FSP-OP bit will switch operation
to use all of the new parameters simultaneously (within tFC), eliminating the possibility of a loss of communication
that could be caused by a partial configuration change.
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Mode Register Function with two physical registers
Parameters which have two physical registers controlled by FSP-WR and FSP-OP include:
MR#
Operand
OP[2]
Function
WR-PRE (WR Pre-amble Length)
Notes
OP[3]
RD-PRE (RD Pre-amble Type)
MR1
1
OP[6:4]
OP[7]
nWR (Write-Recovery for Auto-Pre-charge commands)
PST (RD Post-Amble Length)
OP[2:0]
OP[5:3]
OP[6]
RL (Read latency)
MR2
MR3
WL (Write latency)
WLS (Write Latency Set)
OP[0]
PU-Cal (Pull-up Calibration Point)
WR PST(WR Post-Amble Length)
PDDS (Pull-Down Drive Strength)
DBI-RD (DBI-Read Enable)
2
OP[1]
OP[5:3]
OP[6]
OP[7]
DBI-WR (DBI-Write Enable)
OP[2:0]
OP[6:4]
OP[5:0]
OP[6]
DQ ODT (DQ Bus Receiver On-Die-Termination)
CA ODT (CA Bus Receiver On-Die-Termination)
VREF(ca) (VREF(ca) Setting)
MR11
MR12
MR14
VR-CA (VREF(ca) Range)
OP[5:0]
OP[6]
VREF(dq) (VREF(dq) Setting)
VR(dq) (VREF(dq) Range)
OP[2:0]
OP[3]
SoC ODT (Controller ODT Value for VOH calibration)
ODTE-CK (CK ODT enabled for nonterminating rank)
ODTE-CS (CS ODT enable for non terminating rank)
ODTD-CA (CA ODT termination disable)
MR22
OP[4]
OP[5]
Notes:
1. Supporting the two physical registers for Burst Length: MR1 OP[1:0] is optional.
Applications requiring support of both vendor options shall assure that both FSP-OP[0] and FSP-OP[1] are set to the
same code. Refer to vendor datasheets for detail.
2. For dual channel devices, PU-CAL setting is required as the same value for both Ch.A and Ch.B before issuing ZQ Cal start command.
See Mode Register Definition for more details.
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Relation between MR Setting and DRAM Operation
The following table shows how the two mode registers for each of the parameters above can be modified by
setting the appropriate FSP-WR value, and how device operation can be switched between operating points by
setting the appropriate FSP-OP value. The FSP-WR and FSP-OP functions operate completely independently.
Function
MR# & Operand
Data
Operation
Notes
Data write to Mode Register N for FSP-OP[0]
by MRW Command
0 (Default)
Data read from Mode Register N for FSP-OP[0] by MRR
Command.
FSP-WR
MR13 OP[6]
1
Data write to Mode Register N for FSP-OP[1]
by MRW Command.
1
Data read from Mode Register N for FSP-OP[1] by MRR
Command.
DRAM operates with Mode Register N for FSP-OP[0]
setting.
0 (Default)
1
FSP-OP
MR13 OP[7]
2
DRAM operates with Mode Register N for FSP-OP[1]
setting.
Notes:
1. FSP-WR stands for Frequency Set Point Write/Read.
2. FSP-OP stands for Frequency Set Point Operating Point.
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Frequency set point update Timing
The Frequency set point update timing is shown in following figure. When changing the frequency set point via
MR13 OP[7], the VRCG setting: MR13 OP[3] have to be changed into VREF Fast Response (high current) mode
at the same time. After Frequency change time(tFC) is satisfied. VRCG can be changed into Normal Operation
mode via MR13 OP[3].
Frequency Set Point Switching Timing
Notes:
1. The definition that is Clock frequency change during CKE HIGH should be followed at the frequency change operation.
For more information, refer to Section 4.49 Input Clock Stop and Frequency Change.
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AC Timing Table
Data Rate
Min/
Max
Parameter
Symbol
Unit Notes
533/1066/1600/2133/2667/
3200/3733/4267
Frequency Set Point parameters
tFC_Short
tFC_Middle
tFC_Long
Min
Min
Min
200
200
250
ns
ns
ns
1
1
1
Frequency Set Point Switching Time
Valid Clock Requirement
tCKFSPE
tCKFSPX
Min
Min
max(7.5ns, 4nCK)
max(7.5ns, 4nCK)
-
-
after Entering FSP Change
Valid Clock Requirement before 1st Valid
Command after FSP change
NOTE1. Frequency Set Point Switching Time depends on value of Vref(ca) setting: MR12 OP[5:0] and Vref(ca) Range: MR12 OP[6] of
FSP-OP 0 and 1. The details are shown in following table.
tFC value mapping
Additionally change of Frequency Set Point may affect Vref(dq) setting. Settling time of Vref(dq) level is same as Vref(ca) level.
Step Size
Range
Application
From
FSP -OP0
Base
To
From
FSP -OP0
Base
To
FSP-OP1
A single step size increment/decrement
Two or more step size increment/decrement
-
FSP-OP1
tFC_Short
tFC_Middle
tFC_Long
No Change
No Change
Change
Base
Base
-
Base
NOTE1. As well as change from FSP-OP1 to FSP-OP0.
tFC value mapping example
The following table provides an example of tFC value mapping when FSP-OP moves from OP0 to OP1.
FSP-OP:
VREF(ca) Setting:
MR12: OP[5:0]
001100
VREF(ca) Range:
Case
From/To
Application
Notes
MR13 OP[7]
MR12 OP[6]
From
To
0
1
0
1
0
1
0
0
0
0
0
1
1
2
3
tFC_Short
tFC_Middle
tFC_Long
1
2
3
001101
From
To
001100
001110
From
To
Don’t Care
Don’t Care
Notes:
1. A single step size increment/decrement for VREF(CA) Setting Value.
2. Two or more step size increment/decrement for VREF(CA) Setting Value.
3. VREF(CA) Range is changed. In tis case changing VREF(CA) Setting doesn’t affect tFC value.
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The LPDDR4-SDRAM defaults to FSP-OP[0] at power-up. Both Set-Points default to settings needed to operate in
un-terminated, low-frequency environments. To enable the LPDDR4-SDRAM to operate at higher frequencies,
Command Bus Training mode should be utilized to train the alternate Frequency Set-Point. See the section
Command Bus Training for more details on this training mode.
Prepare for CA Bus
Training of FSP[1] for
High Frequency
FSP-OP=0
Powerup/
Initialization
FSP-OP=0
FSP-WR=0
Freq = Boot
CA Bus Training,
FSP-OP[1]
FSP-WR=1
Freq = high
CKE high→low
FSP-WR=1
Freq = Boot
CKE low→high
Prepare for CA Bus
Training of FSP[0]
for Med. Frequency
FSP-OP=1
Exit CA Bus
Training
FSP-OP=0
FSP-WR=1
Freq = Boot
Switch to
High-Speed Mode
FSP-OP=1
FSP-WR=1
Freq = High
FSP-WR=0
Freq = high
CKE high→low
Exit CA Bus
Training
FSP-OP=1
FSP-WR=0
Freq = High
CA Bus Training,
FSP-OP[0]
Operate at
High speed
FSP-WR=0
Freq = Med
CKE low→high
Training Two Frequency Set-Points
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Once both Frequency Set-Points have been trained, switching between points can be performed by a
single MRW followed by waiting for tFC.
State n-1: FSP-OP=1
MWR Command
State n: FSP-OP=0
Operate at
Medium speed
Operate at
High speed
tFC
State n-1: FSP-OP=1
MWR Command
State n: FSP-OP=0
Operate at
High speed
tFC
Switching Between Two Trained Frequency Set-Points
Switching to a third (or more) Set-Point can be accomplished if the memory controller has stored the
previously-trained values (in particular the Vref-CA calibration value) and re-writes these to the alternate Set-Point
before switching FSP-OP.
MRW Vref-CA
CA-ODT, DQ-ODT,RL,
WL, Vref-DQ,...etc.
State n-1: FSP-OP=1
State n: FSP-OP=0
Operate at
High speed
tFC
Operate at
Third
State n-1: FSP-OP=1
State n: FSP-OP=0
speed
tFC
Switching to a Third Trained Frequency Set-Point
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Mode Reister Write-WR Leveling Mode
To improve signal-integrity performance, the LPDDR4 SDRAM provides a write-leveling feature to compensate
CK-to-DQS timing skew affecting timing parameters such as tDQSS, tDSS, and tDSH. The DRAM samples the
clock state with the rising edge of DQS signals, and asynchronously feeds back to the memory controller. The
memory controller references this feedback to adjust the clock-to-data strobe signal relationship for each
DQS/ signal pair.
All data bits (DQ[7:0] for DQS/[0], and DQ[15:8] for DQS/ [1]) carry the training feedback to the controller.
Both DQS signals in each channel must be leveled independently. Write-leveling entry/exit is independent
between channels.
The LPDDR4 SDRAM enters into write-leveling mode when mode register MR2-OP[7] is set HIGH. When entering
write-leveling mode, the state of the DQ pins is undefined. During write-leveling mode, only DESELECT
commands are allowed, or a MRW command to exit the write-leveling operation. Depending on the absolute
values of tDQSL and tDQSH in the application, the value of tDQSS may have to be better than the limits provided
in the Write AC Timing Table1 in order to satisfy the tDSS and tDSH specifications. Upon completion of the
write-leveling operation, the DRAM exits from write-leveling mode when MR2-OP[7] is reset LOW.
Write Leveling should be performed before Write Training (DQS2DQ Training).
NOTE1. As of publication of this document, under discussion by the formulating committee.
Write Leveling Procedure
1. Enter into Write-leveling mode by setting MR2-OP[7]=1.
2. Once entered into Write-leveling mode, DQS must be driven LOW and HIGH after a delay of tWLDQSEN.
3. Wait for a time tWLMRD before providing the first DQS signal input. The delay time tWLMRD(MAX) is controller
dependent.
4. DRAM may or may not capture first rising edge of DQS due to an unstable first risign edge. Hence provide at
least consecutive 2 pulses of DQS signal input is required in every DQS input signal during Write Training Mode.
The captured clock level by each DQS edges are overwritten at any time and the DRAM provides asynchronous
feedback on all the DQ bits after time tWLO.
5. The feedback provided by the DRAM is referenced by the controller to increment or decrement the DQS and/or
delay settings.
6. Repeat step 4 through step 5 until the proper DQS/ delay is established.
7. Exit from Write-leveling mode by setting MR2-OP[7]=0.
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A Write Leveling timing example is shown in figure below.
Write Leveling Timing, tDQSL(max)
Write Leveling Timing, tDQSL(min)
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Input Clock Frequency Stop and Change
The input clock frequency can be stopped or changed from one stable clock rate to another stable clock rate
during Write Leveling mode.
The Frequency stop or change timing is shown in following figure.
Clock Stop and Timing during Write Leveling
Notes:
1. CK is held LOW and is held HIGH during clock stop.
2. CS shall be held LOW during clock clock stop.
Write Leveling Timing Parameters
Min/
Parameter
Symbol
tWLDQSEN
tWLWPRE
tWLMRD
tWLO
Value
Unit Notes
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
20
DQS/ delay
tCK
tCK
tCK
ns
ns
-
after write leveling mode is programmed
-
20
Write preamble for Write Leveling
-
40
First DQS/ edge
after write leveling mode is programmed
-
0
Write leveling output delay
20
max(14ns, 10nCK)
Mode register set command delay
Valid Clock Requirement before DQS Toggle
Valid Clock Requirement after DQS Toggle
tMRD
-
max(7.5ns, 4nCK)
tCKPRDQS
tCKPSTDQS
-
max(7.5ns, 4nCK)
-
-
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Write Leveling Setup and Hold Time
Data Rate
Min/
Max
Parameter
Symbol
Unit
1600
2400
3200
3733
4267
Write Leveling Parameters
Write leveling hold time
tWLH
tWLS
Min
Min
Min
150
150
240
100
100
160
75
75
60
60
50
50
90
ps
ps
ps
Write leveling setup time
Write leveling input valid window
tWLIVW
120
100
Notes:
1. In addition to the traditional setup and hold time specifications above, there is value in a input valid window based specification for
write-leveling training. As the training is based on each device, worst case process skews for setup and hold do not make sense to
close timing between CK and DQS.
2. tWLIVW is defined in a similar manner to tdIVW_Total, except that here it is a DQS input valid window with respect to CK. This would
need to account for all VT (voltage and temperature) drift terms between CK and DQS within the DRAM that affect the write-leveling
input valid window.
The DQS input mask for timing with respect to CK is shown in following figure. The "total" mask (tWLIVW) defines
the time the input signal must not encroach in order for the DQS input to be successfully captured by CK with a
BER of lower than tbd. The mask is a receiver property and it is not the valid data-eye.
DQS/ and CK/ at DRAM Latch
DQS/ to CK/ timings at the DRAM pins referenced from the internal latch
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RD DQ Calibration
RD DQ Calibration for x16 mode
LPDDR4 devices feature a RD DQ Calibration training function that outputs a 16-bit user-defined pattern on the
DQ pins. RD DQ Calibration is initiated by issuing a MPC-1 [RD DQ Calibration] command followed by a CAS-2
command, cause the LPDDR4-SDRAM to drive the contents of MR32 followed by the contents of MR40 on each
of DQ[15:0] and DMI[1:0]. The pattern can be inverted on selected DQ pins according to user-defined invert masks
written to MR15 and MR20.
RD DQ Calibration Training Procedure
The procedure for executing RD DQ Calibration is:
• Issue MRW commands to write MR32 (first eight bits), MR40 (second eight bits), MR15 (eight-bit invert
mask for byte 0), and MR20 (eight-bit invert mask for byte 1).
• Optionally this step could be skipped to use the default patterns
- MR32 default = 5Ah
- MR40 default = 3Ch
- MR15 default = 55h
- MR20 default = 55h
•Issue an MPC-1 [RD DQ Calibration] command followed immediately by a CAS-2 command.
• Each time an MPC-1 [RD DQ Calibration] command followed by a CAS-2 is received by the LPDDR4
SDRAM, a 16-bit data burst will, after the currently set RL, drive the eight bits programmed in MR32
followed by the eight bits programmed in MR40 on all I/O pins.
• The data pattern will be inverted for I/O pins with a '1' programmed in the corresponding invert mask
mode register bit.
• Note that the pattern is driven on the DMI pins, but no data bus inversion function is enabled, even if
Read DBI is enabled in the DRAM mode register.
• The MPC-1 [RD DQ Calibration] command can be issued every tCCD seamlessly, and tRTRRD delay is
required between Array Read command and the MPC-1 [RD DQ Calibration] command as well the
delay required between the MPC-1 [RD DQ Calibration] command and an array read.
• The operands received with the CAS-2 command must be driven LOW.
• DQ Read Training can be performed with any or no banks active, during Refresh, or during SREF with CKE
high.
Invert Mask Assignments
DQ Pin
0
1
2
3
DMI0
4
5
6
7
MR15 bit
0
1
2
3
N/A
4
5
6
7
DQ Pin
8
9
10
11
DMI1
12
13
14
15
MR20 bit
0
1
2
3
N/A
4
5
6
7
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DQ Read Training Timing: Read to Read DQ Calibration
Notes:
1. Read-1 to MPC [RD DQ Calibration] Operation is shown as an example of command-to-command timing.
Timing from Read-1 to MPC [RD DQ Calibration] command is tRTRRD.
2. MPC [RD DQ Calibration] uses the same command-to-data timing relationship (RL, tDQSCK, tDQSQ) as a Read-1 command.
3. BL = 16, Read Preamble: Toggle, Read Postamble: 0.5nCK.
4. DES commands are shown for ease of illustration; other commands may be valid at these times.
DQ Read Training Timing: Read DQ Cal. to Read DQ Cal. / Read
Notes:
1. MPC [RD DQ Calibration] to MPC [RD DQ Calibration] Operation is shown as an example of command-to-command timing.
2. MPC [RD DQ Calibration] to Read-1 Operation is shown as an example of command-to-command timing.
3. MPC [RD DQ Calibration] uses the same command-to-data timing relationship (RL, tDQSCK, tDQSQ) as a Read-1 command.
4. Seamless MPC [RD DQ Calibration] commands may be executed by repeating the command every tCCD time.
5. Timing from MPC [RD DQ Calibration] command to Read-1 is tRTRRD.
6. BL = 16, Read Preamble: Toggle, Read Postamble: 0.5nCK.
7. DES commands are shown for ease of illustration; other commands may be valid at these times.
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DQ Read Training Example
An example of DQ Read Training output is shown in table below. This shows the 16-bit data pattern that will be
driven on each DQ in byte 0 when one DQ Read Training command is executed. This output assumes the
following mode register values are used:
- MR32 = 1CH
- MR40 = 59H
- MR15 = 55H
- MR20 = 55H
DQ Read Calibration Bit Ordering and Inversion Example
Bit Sequence
Pin
Invert
15 14 13 12 11 10
9
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
8
0
1
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
1
7
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
6
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
5
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
4
0
1
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
1
3
0
1
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
1
2
0
1
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
1
1
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
DQ0
DQ1
Yes
No
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
0
1
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
1
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
0
1
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
1
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
DQ2
Yes
No
DQ3
DMI0
DQ4
Never
Yes
No
DQ5
DQ6
Yes
No
DQ7
DQ8
Yes
No
DQ9
DQ10
DQ11
DMI1
DQ12
DQ13
DQ14
DQ15
Yes
No
Never
Yes
No
Yes
No
Notes:
1. The patterns contained in MR32 and MR40 are transmitted on DQ[15:0] and DMI[1:0] when RD DQ Calibration is initiated via a MPC-1
[RD DQ Calibration] command. The pattern transmitted serially on each data lane, organized "little endian" such that the low-order
bit in a byte is transmitted first. If the data pattern is 27H, then the first bit transmitted with be a '1', followed by '1', '1', '0', '0', '1', '0',
and '0'. The bit stream will be 00100111
2. MR15 and MR20 may be used to invert the MR32/MR40 data pattern on the DQ pins. See MR15 and MR20 for more information. Data
is never inverted on the DMI[1:0] pins.
3. DMI [1:0] outputs status follows table.
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MR Setting vs. DMI Status
DM Function
MR13 OP[5]
1: Disable
Write DBIdc Function
Read DBIdc Function
MR3 OP[6]
0: Disable
DMI Status
MR3 OP[7]
0: Disable
1: Enable
0: Disable
1: Enable
0: Disable
1: Enable
0: Disable
1: Enable
Hi-Z
1: Disable
0: Disable
The data pattern is transmitted
The data pattern is transmitted
The data pattern is transmitted
The data pattern is transmitted
The data pattern is transmitted
The data pattern is transmitted
The data pattern is transmitted
1: Disable
1: Enable
1: Disable
1: Enable
0: Enable
0: Disable
0: Enable
0: Disable
0: Enable
1: Enable
0: Enable
1: Enable
4. No Data Bus Inversion (DBI) function is enacted during RD DQ Calibration, even if DBI is enabled in MR3-OP[6].
MPC of Read DQ Calibration after Power-Down Exit
Following the power-down state, an additional time, tMRRI, is required prior to issuing the MPC of Read DQ
Calibration command. This additional time (equivalent to tRCD) is required in order to be able to maximize
power-down current savings by allowing more power-up time for the Read DQ data in MR32 and MR40 data path
after exit from standby, power-down mode.
MPC Read DQ Calibration Following Power-Down State
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RD DQ Calibration for Byte (x8) mode
LPDDR4 devices feature a RD DQ Calibration training function that outputs a 8-bit user-defined pattern on
the DQ pins. RD DQ Calibration is initiated by issuing a MPC-1 [RD DQ Calibration] command followed by
a CAS-2 command, cause the LPDDR4-SDRAM to drive the contents of MR32 followed by the contents of
MR40 on each of DQ[7:0] and DMI[0]. The pattern can be inverted on selected DQ pins according to userdefined
invert masks written to MR15 and MR20.
RD DQ Calibration Training Procedure
Issue MRW commands to write MR32 (first eight bits), MR40 (second eight bits),
MR15 (eight-bit invert mask for byte 0 : DQ[7:0] ) and MR20 (eight-bit invert mask for byte 1 : DQ[15:8] )
• Optionally this step could be skipped to use the default patterns
- MR32 default = 5Ah
- MR40 default = 3Ch
- MR15 default = 55h
- MR20 default = 55h
• Issue an MPC-1 [RD DQ Calibration] command followed immediately by a CAS-2 command
• Each time an MPC-1 [RD DQ Calibration] command followed by a CAS-2 is received by the
LPDDR4 SDRAM, a 16-bit data burst will, after the currently set RL, drive the eight bits programmed
in MR32 followed by the eight bits programmed in MR40 on all I/O pins.
• The data pattern will be inverted for I/O pins with a ‘1’ programmed in the corresponding invert mask
mode register bit (see Table ‘Invert Mask Assignments’).
• Note that the pattern is driven on the DMI pins, but no data bus inversion function is enabled, even if
Read DBI is enabled in the DRAM mode register.
• This command can be issued every tCCD seamlessly, and can be issued seamlessly with array
Read commands.
• The operands received with the CAS-2 command must be driven LOW.
• DQ Read Training can be performed with any or no banks active, during Refresh, or during SREF with
CKE high.
Invert Mask Assignments
DQ Pin
0
1
2
3
DMI0
4
5
6
7
MR 15 bit
0
1
2
3
N/A
4
5
6
7
DQ Pin
8
9
10
11 DMI1 12
N/A
13
14
15
MR 20 bit
0
1
2
3
4
5
6
7
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DQ Read Training Example
An example of DQ Read Training output is shown in table below. This shows the 16-bit data pattern that will be
driven on each DQ in byte 0 when one DQ Read Training command is executed. This output assumes the
following mode register values are used:
- MR32 = 1CH
- MR40 = 59H
- MR15 = 55H
- MR20 = 55H
DQ Read Calibration Bit Ordering and Inversion Example
Bit Sequence
Pin
Invert
Yes
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DQ0
(DQ8)
DQ1
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
1
0
1
1
1
0
0
0
1
1
No
0
1
1
0
0
1
0
1
0
1
1
0
1
0
1
0
0
1
0
1
(DQ9)
DQ2
Yes
(DQ10)
DQ3
No
Never
Yes
0
0
1
1
1
0
0
0
1
1
1
0
1
1
0
0
0
1
0
0
1
1
1
0
0
0
1
0
0
1
0
0
1
1
1
0
1
1
0
1
1
0
0
0
1
0
0
1
(DQ11)
DMI0
DQ4
(DQ12)
DQ5
No
Yes
No
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
0
0
1
0
(DQ13)
DQ6
(DQ14)
DQ7
(DQ15)
Notes:
1. The patterns contained in MR32 and MR40 are transmitted on lower byte select : DQ[7:0] or upper byte select : DQ[15:8], DMI[0] or
DMI[1] when RD DQ Calibration is initiated via a MPC-1 [RD DQ Calibration] command. The pattern transmitted serially on each data
lane, organized “little endian” such that the low-order bit in a byte is transmitted first. If the data pattern is 27H, then the first bit
transmitted with be a ‘1’, followed by ‘1’, ‘1’, ‘0’, ‘0’, ‘1’, ‘0’, and ‘0’. The bit stream will be 00100111.
2. MR15 and MR20 may be used to invert the MR32/MR40 data pattern on the DQ pins. See MR15 for more information. Data is never
inverted on the DMI[0] pins.
3. The data pattern is not transmitted on the DMI[0] or DMI[1] pins if DBI-RD is disabled via MR3 OP[6].
4. No Data Bus Inversion (DBI) function is enacted during RD DQ Calibration, even if DBI is enabled in MR3 OP[6].
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DQS-DQ Training
The LPDDR4-SDRAM uses an un-matched DQS-DQ path to enable high speed performance and save power in
the DRAM. As a result, the DQS strobe must be trained to arrive at the DQ latch center-aligned with the Data eye.
The SDRAM DQ receiver is located at the DQ pad, and has a shorter internal delay in the SDRAM than does the
DQS signal. The SDRAM DQ receiver will latch the data present on the DQ bus when DQS reaches the latch, and
training is accomplished by delaying the DQ signals relative to DQS such that the Data eye arrives at the receiver
latch centered on the DQS transition.
Two modes of training are available in LPDDR4:
• Command-based FIFO WR/RD with user patterns
• A internal DQS clock-tree oscillator, to determine the need for, and the magnitude of required training.
The command-based FIFO WR/RD uses the MPC command with operands to enable this special mode of
operation. When issuing the MPC command, if OP6 is set LOW then the DRAM will perform a NOP command.
When OP6 is set HIGH, then OP5:0 enable training functions or are reserved for future use (RFU). MPC
commands that initiate a Read FIFO, READ DQ Calibration or Write FIFO to the SDRAM must be followed
immediately by a CAS-2 command. See "Multi Purpose Command (MPC) Definition" for more information.
To perform Write Training, the controller can issue a MPC [Write DQ FIFO] command with OP[6:0] set as
described in the MPC Definition section, followed immediately by a CAS-2 command (CAS-2 operands should be
driven LOW) to initiate a Write DQ FIFO. Timings for MPC [Write DQ FIFO] are identical to a Write command, with
WL (Write Latency) timed from the 2nd rising clock edge of the CAS-2 command. Up to 5 consecutive MPC [Write
DQ FIFO] commands with user defined patterns may be issued to the SDRAM to store up to 80 values (BL16 x5)
per pin that can be read back via the MPC [Read DQ FIFO] command. Write/Read FIFO Pointer operation is
described later in this section.
After writing data to the SDRAM with the MPC [Write DQ FIFO] command, the data can be read back with the
MPC [Read DQ FIFO] command and results compared with “expect” data to see if further training (DQ delay) is
needed. MPC [Read DQ FIFO] is initiated by issuing a MPC command with OP[6:0] set as described in the MPC
Definition section, followed immediately by a CAS-2 command (CAS-2 operands must be driven LOW). Timings
for the MPC [Read DQ FIFO] command are identical to a Read command, with RL (Read Latency) timed from the
2nd rising clock edge of the CAS-2 command.
Read DQ FIFO is non-destructive to the data captured in the FIFO, so data may be read continuously until it is
either overwritten by a Write DQ FIFO command or disturbed by CKE LOW or any of the following commands;
Write, Masked Write, Read, Read DQ Calibration and a MRR. If fewer than 5 Write DQ FIFO commands were
executed, then unwritten registers will have un-defined (but valid) data when read back.
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The following command about MRW is only allowed from MPC [Write DQ FIFO] command to MPC [Read DQ
FIFO].
Allowing MRW command is for OP[7]:FSP-OP, OP[6]:FSP-WR and OP[3]:VRCG of MR13 and MR14. And the rest
of MRW command is prohibited.
For example: If 5 Write DQ FIFO commands are executed sequentially, then a series of Read DQ FIFO
commands will read valid data from FIFO[0], FIFO[1]….FIFO[4], and will then wrap back to FIFO[0] on the next
Read DQ FIFO.
On the other hand, if fewer than 5 Write DQ FIFO commands are executed sequentially (example=3), then a
series of Read DQ FIFO commands will return valid data for FIFO[0], FIFO[1], and FIFO[2], but the next two Read
DQ FIFO commands will return un-defined data for FIFO[3] and FIFO[4] before wrapping back to the valid data in
FIFO[0].
FIFO Pointer Reset and Synchronism
The Read and Write DQ FIFO pointers are reset under the following conditions:
• Power-up initialization
• asserted
• Power-down entry
• Self Refresh Power-Down entry
The MPC [Write DQ FIFO] command advances the WR-FIFO pointer, and the MPC [Read DQ FIFO] advances the
RD-FIFO pointer. Also any normal (non-FIFO) Read Operation (RD, RDA) advances both
WR-FIFO pointer and RD-FIFO pointer. Issuing (non-FIFO) Read Operation command is inhibited during Write
training period. To keep the pointers aligned, the SoC memory controller must adhere to the following restriction at
the end of Write training period:
•b = a + (n x c)
Where:
‘a’ is the number of MPC [Write DQ FIFO] commands
‘b’ is the number of MPC [Read DQ FIFO] commands
‘c’ is the FIFO depth (=5 for LPDDR4)
‘n’ is a positive integer,0
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Write to MPC [Write FIFO] Operation Timing
Notes:
1. MPC [WR FIFO] can be executed with a single bank or multiple banks active, during Refresh, or during SREF with CKE HIGH.
2. Write-1 to MPC is shown as an example of command-to-command timing for MPC. Timing from Write-1 to MPC [WR-FIFO] is tWRWTR.
3. Seamless MPC [WR-FIFO] commands may be executed by repeating the command every tCCD time.
4. MPC [WR-FIFO] uses the same command-to-data timing relationship (WL, tDQSS, tDQS2DQ) as a Write-1 command.
5. A maximum of 5 MPC [WR-FIFO] commands may be executed consecutively without corrupting FIFO data.
The 6th MPC [WR-FIFO] command will overwrite the FIFO data from the first command. If fewer than 5 MPC [WR-FIFO] commands are
executed, then the remaining FIFO locations will contain undefined data.
6. For the CAS-2 command following a MPC command, the CAS-2 operands must be driven “LOW.”
7. To avoid corrupting the FIFO contents, MPC [RD-FIFO] must immediately follow MPC [WR-FIFO]/CAS-2 without any other command
disturbing
FIFO pointers in-between. FIFO pointers are disturbed by CKE Low, Write, Masked Write, Read, Read DQ Calibration and MRR.
8. BL = 16, Write Postamble = 0.5nCK
9. DES commands are shown for ease of illustration; other commands may be valid at these times.
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MPC [Write FIFO] to MPC [Read FIFO] Timing
Notes:
1. MPC [WR FIFO] can be executed with a single bank or multiple banks active, during Refresh, or during SREF with CKE HIGH.
2. MPC [WR-FIFO] to MPC [RD-FIFO] is shown as an example of command-to-command timing for MPC.
Timing from MPC [WR-FIFO] to MPC [RD-FIFO] is specified in the command-to-command timing table.
3. Seamless MPC [RD-FIFO] commands may be executed by repeating the command every tCCD time.
4. MPC [RD-FIFO] uses the same command-to-data timing relationship (RL, tDQSCK, tDQSQ) as a Read-1 command.
5. Data may be continuously read from the FIFO without any data corruption. After 5 MPC [RD-FIFO] commands the FIFO pointer will
wrap back to the 1st FIFO and continue advancing. If fewer than 5 MPC [WR-FIFO] commands were executed, then the MPC [RD-FIFO]
commands to those FIFO locations will return undefined data. See the Write Training section for more information on the FIFO pointer
behavior.
6. For the CAS-2 command immediately following a MPC command, the CAS-2 operands must be driven “LOW.”
7. DMI[1:0] signals will be driven if any of WR-DBI, RD-DBI, or DM is enabled in the mode registers. See Write Training section for more
information on DMI behavior.
8. BL = 16, Write Postamble = 0.5nCK, Read Preamble: Toggle, Read Postamble: 0.5nCK
9. DES commands are shown for ease of illustration; other commands may be valid at these times.
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MPC [Read FIFO] to Read Timing
Notes:
1. MPC [WR FIFO] can be executed with a single bank or multiple banks active, during Refresh, or during SREF with CKE HIGH.
2. MPC [RD-FIFO] to Read-1 Operation is shown as an example of command-to-command timing for MPC. Timing from MPC [RD-FIFO]
command to Read is tRTRRD.
3. Seamless MPC [RD-FIFO] commands may be executed by repeating the command every tCCD time.
4. MPC [RD-FIFO] uses the same command-to-data timing relationship (RL, tDQSCK, tDQSQ) as a Read-1 command.
5. Data may be continuously read from the FIFO without any data corruption. After 5 MPC [RD-FIFO] commands the FIFO pointer will
wrap back to the 1st FIFO and continue advancing. If fewer than 5 MPC [WR-FIFO] commands were executed, then the MPC [RD-FIFO]
commands to those FIFO locations will return undefined data. See the Write Training section for more information on the FIFO pointer
behavior.
6. For the CAS-2 command immediately following a MPC command, the CAS-2 operands must be driven “LOW.”
7. DMI[1:0] signals will be driven if any of WR-DBI, RD-DBI, or DM is enabled in the mode registers. See Write Training section for more
information on DMI behavior.
8. BL = 16, Read Preamble: Toggle, Read Postamble: 0.5nCK
9. DES commands are shown for ease of illustration; other commands may be valid at these times.
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MPC [Write FIFO] with DQ ODT Timing
Notes:
1. MPC [WR FIFO] can be executed with a single bank or multiple banks active, during Refresh, or during SREF with CKE HIGH.
2. MPC [WR-FIFO] uses the same command-to-data/ODT timing relationship (WL, tDQSS, tDQS2DQ, ODTLon, ODTLoff, tODTon, tODToff)
as a Write-1 command.
3. For the CAS-2 command immediately following a MPC command, the CAS-2 operands must be driven “LOW.”
4. BL = 16, Write Postamble = 0.5nCK
5. DES commands are shown for ease of illustration; other commands may be valid at these times.
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Power Down Exit to MPC [Write FIFO] Timing
Notes:
1. Any commands except MPC WR FIFO and other exception commands defined other section in this document (i.e. MPC Read DQ Cal).
2. DES commands are shown for ease of illustration; other commands may be valid at these times.
MPC [Write FIFO] AC Timing
Min/
Parameter
Symbol
Data Rate
Unit Notes
Max
MPC Write FIFO Timing
Additional time after tXP has expired until
MPC [Write FIFO] command may be issued
tMPCWR
Min
tRCD + 3nCK
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DQS Interval Oscillator
As voltage and temperature change on the SDRAM die, the DQS clock tree delay will shift and may require
re-training. The LPDDR4-SDRAM includes an internal DQS clock-tree oscillator to measure the amount of delay
over a given time interval (determined by the controller), allowing the controller to compare the trained delay value
to the delay value seen at a later time. The DQS Oscillator will provide the controller with important information
regarding the need to re-train, and the magnitude of potential error.
The DQS Interval Oscillator is started by issuing a MPC [Start DQS Osc] command with OP[6:0] set as described
in the MPC Operation section, which will start an internal ring oscillator that counts the number of time a signal
propagates through a copy of the DQS clock tree.
The DQS Oscillator may be stopped by issuing a MPC [Stop DQS Osc] command with OP[6:0] set as described in
the MPC Operation section, or the controller may instruct the SDRAM to count for a specific number of clocks and
then stop automatically (See MR23 for more information). If MR23 is set to automatically stop the DQS Oscillator,
then the MPC [Stop DQS Osc] command should not be used (illegal). When the DQS Oscillator is stopped by
either method, the result of the oscillator counter is automatically stored in MR18 and MR19.
The controller may adjust the accuracy of the result by running the DQS Interval Oscillator for shorter (less
accurate) or longer (more accurate) duration. The accuracy of the result for a given temperature and voltage is
determined by the following equation:
2 * (DQS delay)
DQS Oscillator Granularity Error =
Run Time
Where:
Run Time = total time between start and stop commands
DQS delay = the value of the DQS clock tree delay (tDQS2DQ min/max)
Additional matching error must be included, which is the difference between DQS training circuit and the actual
DQS clock tree across voltage and temperature. The matching error is vendor specific.
Therefore, the total accuracy of the DQS Oscillator counter is given by:
DQS Oscillator Accuracy = 1 - Granularity Error - Matching Error
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Example: If the total time between start and stop commands is 100ns, and the maximum DQS clock tree delay is
800ps (tDQS2DQ max), then the DQS Oscillator Granularity Error is:
2 * (0.8ns)
100ns
DQS Oscillator Granularity Error =
= 1.6%
This equates to a granularity timing error of 12.8ps.
Assuming a circuit Matching Error of 5.5ps across voltage and temperature, then the accuracy is:
12.8 + 5.5
DQS Oscillator Accuracy = 1-
= 97.7%
800
Example: Running the DQS Oscillator for a longer period improves the accuracy. If the total time between start and
stop commands is 500ns, and the maximum DQS clock tree delay is 800ps (tDQS2DQ max), then the DQS
Oscillator Granularity Error is:
2 * (0.8ns)
500ns
DQS Oscillator Granularity Error =
= 0.32%
This equates to a granularity timing error or 2.56ps.
Assuming a circuit Matching Error of 5.5ps across voltage and temperature, then the accuracy is:
2.56 + 5.5
DQS Oscillator Accuracy = 1-
= 99.0%
800
The result of the DQS Interval Oscillator is defined as the number of DQS Clock Tree Delays that can be counted
within the “run time,” determined by the controller. The result is stored in MR18-OP[7:0] and MR19-OP[7:0]. MR18
contains the least significant bits (LSB) of the result, and MR19 contains the most significant bits (MSB) of the
result. MR18 and MR19 are overwritten by the SDRAM when a MPC-1 [Stop DQS Osc] command is received. The
SDRAM counter will count to its maximum value (=2^16) and stop. If the maximum value is read from the mode
registers, then the memory controller must assume that the counter overflowed the register and discard the result.
The longest “run time” for the oscillator that will not overflow the counter registers can be calculated as follows:
Longest Run Time Interval = 216 * tDQS2DQ(min) = 216 * 0.2ns = 13.1us
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Interval Oscillator matching error
The interval oscillator matching error is defined as the difference between the DQS training ckt(interval oscillator)
and the actual DQS clock tree across voltage and temperature.
• Parameters:
- tDQS2DQ: Actual DQS clock tree delay
- tDQSOSC: Training ckt(interval oscillator) delay
- OSCOffset: Average delay difference over voltage and temp.
- OSCMatch: DQS oscillator matching error
Interval oscillator offset OSCoffset
• OSCMatch
:
OSC Match = [ tDQS2DQ(V,T) – tDQSOSC(V,T) – OSCoffset
]
• tDQSOSC
:
Runtime
tDQS OSC(V,T)
=
2 * Count
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4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
DQS Oscillator Matching Error Specification
Parameter
Symbol
OSC
Min
-20
Max
20
Unit
ps
Notes
1,2,3,4,5,6,7
2,4,7
DQS Oscillator Matching Error
DQS Oscillator Offset
Match
-100
100
ps
OSC
offset
Notes:
1. The OSCMatch is the matching error per between the actual DQS and DQS interval oscillator over voltage and temp.
2. This parameter will be characterized or guaranteed by design.
3. The OSCMatch is defined as the following:
OSC Match = [ tDQS2DQ(V,T) – tDQSOSC(V,T) – OSCoffset
]
Where tDQS2DQ(V,T) and tDQSOSC(V,T) are determined over the same voltage and temp conditions.
4. The runtime of the oscillator must be at least 200ns for determining tDQSOSC(V,T)
Runtime
tDQS OSC(V,T)
=
2 * Count
5. The input stimulus for tDQS2DQ will be consistent over voltage and temp conditions.
6. The OSCoffset is the average difference of the endpoints across voltage and temp.
7. These parameters are defined per channel.
8. tDQS2DQ(V,T) delay will be the average of DQS to DQ delay over the runtime period.
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8Gb: NT6AN256T32AV
DQS Interval Oscillator Readout Timing
OSC Stop to its counting value readout timing is shown in figure below.
In case of DQS Interval Oscillator is stopped by MPC Command
Notes:
1. DQS interval timer run time setting : MR23 OP[7:0] = 00000000
2. DES commands are shown for ease of illustration; other commands may be valid at these times.
In case of DQS Interval Oscillator is stopped by DQS interval timer
Notes:
1. DQS interval timer run time setting : MR23 OP[7:0]≠00000000
2. Setting counts of MR23
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
DQS Interval Oscillator AC Timing
Min/
Parameter
Symbol
Value
Unit Notes
Max
Delay time from OSC stop to Mode Register Readout
Notes:
tOSCO
Min
Max(40ns,8nCK)
ns
1. Start DQS OSC command is prohibited until tOSCO(Min) is satisfied.
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8Gb: NT6AN256T32AV
READ Preamble Training
LPDDR4 READ Preamble Training is supported through the MPC function.
This mode can be used to train or read level the DQS receivers. Once READ Preamble Training is enabled by
MR13[OP1] = 1, the LPDDR4 DRAM will drive DQS LOW, HIGH within tSDO and remain at these levels until
an MPC DQ READ Calibration command is issued.
During READ Preamble Training the DQS preamble provided during normal operation will not be driven by the
DRAM. Once the MPC DQ READ Calibration command is issued, the DRAM will drive DQS/ and DQ like a
normal READ burst after RL and tDQSCK. Prior to the MPC DQ READ Calibration command, the DRAM may or
may not drive DQ[15:0] in this mode.
While in READ Preamble Training Mode, only READ DQ Calibration commands may be issued.
•Issue an MPC [RD DQ Calibration] command followed immediately by a CAS-2 command.
• Each time an MPC [RD DQ Calibration] command followed by a CAS-2 is received by the LPDDR4
SDRAM, a 16-bit data burst will, after the currently set RL, drive the eight bits programmed in MR32
followed by the eight bits programmed in MR40 on all I/O pins.
• The data pattern will be inverted for I/O pins with a '1' programmed in the corresponding invert mask mode
register bit.
• Note that the pattern is driven on the DMI pins, but no data bus inversion function is enabled, even if Read
DBI is enabled in the DRAM mode register.
• This command can be issued every tCCD seamlessly.
• The operands received with the CAS-2 command must be driven LOW.
READ Preamble Training is exited within tSDO after setting MR13[OP1] = 0.
LPDDR4 supports the READ Preamble Training as optional feature. Refer to vendor specific datasheets.
Read Preamble Training
Notes:
1. Read DQ Calibration supports only BL16 operation
Timing Parameters
Parameter
Symbol
Min
Max
Unit Notes
Delay from MRW command to DQS Driven Out
tSDO
-
Max(12nCK, 20ns)
-
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8Gb: NT6AN256T32AV
Multi-Purpose Command (MPC)
LPDDR4-SDRAMs use the MPC command to issue a NOP and to access various training modes. The MPC
command is initiated with CS, and CA[5:0] asserted to the proper state at the rising edge of CK, as defined by the
Command Truth Table. The MPC command has seven operands (OP[6:0]) that are decoded to execute specific
commands in the SDRAM. OP[6] is a special bit that is decoded on the first rising CK edge of the MPC command.
When OP[6]=0 then the SDRAM executes a NOP (no operation) command, and when OP[6]=1 then the SDRAM
further decodes one of several training commands.
When OP[6]=1 and when the training command includes a Read or Write operation, the MPC command must be
followed immediately by a CAS-2 command. For training commands that Read or Write the SDRAM, read latency
(RL) and write latency (WL) are counted from the second rising CK edge of the CAS-2 command with the same
timing relationship as any normal Read or Write command. The operands of the CAS-2 command following a MPC
Read/Write command must be driven LOW.
The following MPC commands must be followed by a CAS-2 command:
- Write FIFO
- Read FIFO
- Read DQ Calibration
All other MPC-1 commands do not require a CAS-2 command, including:
- NOP
- Start DQS Interval Oscillator
- Stop DQS Interval Oscillator
- Start ZQ Calibration
- Latch ZQ Calibration
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8Gb: NT6AN256T32AV
MPC Command Definition
SDR Command Pins
SDR CA Pins
SDRAM
CKE
CK
Notes
Command
CK(n-1)
EDGE
CS
CA0
CA1
CA2
CA3
CA4
CA5
CK(n)
H
L
L
L
L
L
L
OP6
OP5
R1
R2
MPC
H
H
1, 2
(Train, NOP)
OP0
OP1
OP2
OP3
OP4
MPC Command Definition for OP[6:0]
Function
Operand
Data
Notes
0XXXXXX : NOP
B
1000001 : RD FIFO: RD FIFO supports only BL16 operation
B
1000011 : RD DQ Calibration (MR32/MR40)
B
1000101 : RFU
B
1000111 : WR FIFO: WR FIFO supports only BL16 operation
B
Training Modes
OP[6:0]
1, 2, 3
1001001 : RFU
B
1001011 : Start DQS Osc
B
1001101 : Stop DQS Osc
B
1001111 : ZQCal Start
B
1010001 : ZQCal Latch
B
All Others: Reserved
Notes:
1. See command truth table for more information.
2. MPC commands for Read or Write training operations must be immediately followed by CAS-2 command consecutively without any
other commands in-between. MPC command must be issued first before issuing the CAS-2 command.
3. Write FIFO and Read FIFO commands will only operate as BL16, ignoring the burst length selected by MR1 OP[1:0].
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8Gb: NT6AN256T32AV
MPC [WRITE FIFO] Operation : tWPRE=2nCK, tWPST=0.5nCK
Notes:
1. MPC [WR FIFO] can be executed with a single bank or multiple banks active, during Refresh, or during SREF with CKE HIGH.
2. Write-1 to MPC is shown as an example of command-to-command timing for MPC. Timing from Write-1 to MPC [WR-FIFO] is tWRWTR.
3. Seamless MPC [WR-FIFO] commands may be executed by repeating the command every tCCD time.
4. MPC [WR-FIFO] uses the same command-to-data timing relationship (WL, tDQSS, tDQS2DQ) as a Write-1 command.
5. A maximum of 5 MPC [WR-FIFO] commands may be executed consecutively without corrupting FIFO data.
The 6th MPC [WR-FIFO] command will overwrite the FIFO data from the first command. If fewer than 5 MPC [WR-FIFO] commands
are executed, then the remaining FIFO locations will contain undefined data.
6. For the CAS-2 command following a MPC command, the CAS-2 operands must be driven “LOW.”
7. To avoid corrupting the FIFO contents, MPC-1 [RD-FIFO] must immediately follow MPC-1 [WR-FIFO]/CAS-2 without any other
command disturbing FIFO pointers in-between. FIFO pointers are disturbed by CKE Low, Write, Masked Write, Read, Read DQ
Calibration and MRR.
See Write Training session for more information on FIFO pointer behavior.
MPC [RD FIFO] Read Operation :
tWPRE=2nCK, tWPST=0.5nCK, tRPRE=toggling, tRPST=1.5nCK
Notes:
1. MPC [WR FIFO] can be executed with a single bank or multiple banks active, during Refresh, or during SREF with CKE HIGH.
2. Write-1 to MPC is shown as an example of command-to-command timing for MPC. Timing from Write-1 to MPC-1 [WR-FIFO] is
tWRWTR.
3. Seamless MPC [RD-FIFO] commands may be executed by repeating the command every tCCD time.
4. MPC [RD-FIFO] uses the same command-to-data timing relationship (RL, tDQSCK) as a Read-1 command.
5. Data may be continuously read from the FIFO without any data corruption. After 5 MPC [RD-FIFO] commands the FIFO pointer will
wrap back to the 1st FIFO and continue advancing. If fewer than 5 MPC [WR-FIFO] commands were executed, then the MPC [RD-FIFO]
commands to those FIFO locations will return undefined data. See the Write Training section for more information on the FIFO pointer
behavior.
6. For the CAS-2 command immediately following a MPC command, the CAS-2 operands must be driven “LOW.”
7. DMI[1:0] signals will be driven if any of WR-DBI, RD-DBI, or DM is enabled in the mode registers. See Write Training section for more
information on DMI behavior.
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8Gb: NT6AN256T32AV
MPC [RD FIFO] Operation : tRPRE=toggling, tRPST=1.5nCK
Notes:
1. MPC [WR FIFO] can be executed with a single bank or multiple banks active, during Refresh, or during SREF with CKE HIGH.
2. MPC [RD-FIFO] to Read-1 Operation is shown as an example of command-to-command timing for MPC. Timing from MPC-1 [RD-FIFO]
command to Read is tRTRRD.
3. Seamless MPC [RD-FIFO] commands may be executed by repeating the command every tCCD time.
4. MPC [RD-FIFO] uses the same command-to-data timing relationship (RL, tDQSCK) as a Read-1 command.
5. Data may be continuously read from the FIFO without any data corruption. After 5 MPC [RD-FIFO] commands the FIFO pointer will
wrap back tothe 1st FIFO and continue advancing. If fewer than 5 MPC [WR-FIFO] commands were executed, then the MPC [RD-FIFO]
commands to thoseFIFO locations will return undefined data. See the Write Training section for more information on the FIFO pointer
behavior.
6. For the CAS-2 command immediately following a MPC command, the CAS-2 operands must be driven “LOW.”
7. DMI[1:0] signals will be driven if any of WR-DBI, RD-DBI, or DM is enabled in the mode registers. See Write Training section for more
information on DMI behavior.
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8Gb: NT6AN256T32AV
Timing Constraints for Training Commands
Previous
Next Command
Minimum Delay
Unit Notes
Command
MPC [WR FIFO]
MPC [RD FIFO]
MPC
tWRWTR
nCK
-
1
2
Not Allowed
WR/MWR
RD/MRR
WL+RU(tDQSS(max)/tCK) +BL/2+RU(tWTR/tCK)
nCK
[RD DQ Calibration]
MPC [WR FIFO]
MPC [RD FIFO]
MPC
tRTW
nCK
-
3
2
Not Allowed
tRTRRD
nCK
3
2
[RD DQ Calibration]
WR/MWR
Not Allowed
-
MPC [WR FIFO]
RD/MRR
tCCD
Not Allowed
nCK
-
MPC
2
[WR FIFO]
MPC [RD FIFO]
MPC
WL+RU(tDQSS(max)/tCK) +BL/2+RU(tWTR/tCK)
nCK
Not Allowed
-
2
[RD DQ Calibration]
WR/MWR
tRTW
tRTW
nCK
nCK
nCK
nCK
3
4
3
MPC [WR FIFO]
RD/MRR
MPC
tRTRRD
tCCD
[RD FIFO]
MPC [RD FIFO]
MPC
tRTRRD
nCK
3
[RD DQ Calibration]
WR/MWR
tRTW
tRTW
nCK
nCK
nCK
-
4
4
3
2
MPC [WR FIFO]
RD/MRR
MPC
tRTRRD
[RD DQ Calibration]
MPC [RD FIFO]
MPC
Not Allowed
tCCD
nCK
[RD DQ Calibration]
Notes:
1. tWRWTR = WL + BL/2 + RU(tDQSS(max)/tCK) + max(RU(7.5ns/tCK),8nCK)
2. No commands are allowed between MPC [WR FIFO] and MPC-1 [RD FIFO] except MRW commands related to training parameters.
3. tRTRRD = RL + RU(tDQSCK(max)/tCK) + BL/2 + RD(tRPST) + max(RU(7.5ns/tCK),8nCK)
4. tRTW : In Case of DQ ODT Disable MR11 OP[2:0] = 000B:
RL+RU(tDQSCK(max)/tCK) + BL/2 - WL+tWPRE + RD(tRPST)
In Case of DQ ODT Enable MR11 OP[2:0] 000B:
RL + RU(tDQSCK(max)/tCK) + BL/2 + RD(tRPST) - ODTLon - RD(tODTon,min/tCK) + 1
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8Gb: NT6AN256T32AV
Thermal Offset
Because of their tight thermal coupling with the LPDDR4 device, hot spots on an SOC can induce thermal
gradients across the LPDDR4 device. As these hot spots may not be located near the device thermal sensor, the
devices’ temperature compensated self-refresh circuit may not generate enough refresh cycles to guarantee
memory retention. To address this shortcoming, the controller can provide a thermal offset that the memory uses
to adjust its TCSR circuit to ensure reliable operation.
This offset is provided through MR4(6:5) to either or to both the channels. This temperature offset may modify
refresh behavior for the channel to which the offset is provided. It will take a max of 200us to have the change
reflected in MR4(2:0) for the channel to which the offset is provided. If the induced thermal gradient from the
device temperature sensor location to the hot spot location of the controller is larger than 15 degrees C, then
self-refresh mode will not reliably maintain memory contents.
To accurately determine the temperature gradient between the memory thermal sensor and the induced hot spot,
the memory thermal sensor location must be provided to the LPDDR4 memory controller.
Support of thermal offset function is optional. Please refer to vendor datasheet to figure out if the function is
supported or not.
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8Gb: NT6AN256T32AV
Temperature Sensor
LPDDR4 devices feature a temperature sensor whose status can be read from MR4. This sensor can be used to
determine an appropriate refresh rate, determine whether AC timing de-rating is required in the elevated
temperature range, and/or monitor the operating temperature. Either the temperature sensor or the device TOPER
may be used to determine whether operating temperature requirements are being met.
LPDDR4 devices shall monitor device temperature and update MR4 according to tTSI. Upon assertion of CKE
(Low to High transition), the device temperature status bits shall be no older than tTSI. MR4 will be updated even
when device is in self refresh state with CKE HIGH.
When using the temperature sensor, the actual device case temperature may be higher than the TOPER
specification that applies for the standard or elevated temperature ranges. For example, TCASE may be above
85°C when MR4[2:0] equals ‘b011. LPDDR4 devices shall allow for 2°C temperature margin between the point at
which the device updates the MR4 value and the point at which the controller reconfigures the system accordingly.
In the case of tight thermal coupling of the memory device to external hot spots, the maximum device temperature
might be higher than what is indicated by MR4.
To assure proper operation using the temperature sensor, applications should consider the following factors:
• TempGradient is the maximum temperature gradient experienced by the memory device at the temperature
of interest over a range of 2°C.
• ReadInterval is the time period between MR4 reads from the system.
• TempSensorInterval (tTSI) is maximum delay between internal updates of MR4.
• SysRespDelay is the maximum time between a read of MR4 and the response by the system.
In order to determine the required frequency of polling MR4, the system shall use the maximum TempGradient
and the maximum response time of the system using the following equation:
TempGradient x (ReadInterval + tTSI + SysRespDelay) 2°C
Temperature Sensor
Max/
Parameter
Symbol
Value
Unit Notes
Min
Max
Max
Max
Max
Max
System Temperature Gradient
MR4 Read Interval
TempGradient
ReadInterval
tTSI
System Dependent
°C/s
ms
ms
ms
°C
System Dependent
Temperature Sensor Interval
System Response Delay
Device Temperature Margin
32
SysRespDelay
TempMargin
System Dependent
2
For example, if TempGradient is 10°C/s and the SysRespDelay is 1 ms:
(10°C/s) x (ReadInterval + 32ms + 1ms) 2°C
In this case, ReadInterval shall be no greater than 167 ms.
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Temp Sensor Timing
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ZQ Calibration
The MPC command is used to initiate ZQ Calibration, which calibrates the output driver impedance across process,
temperature, and voltage. ZQ Calibration occurs in the background of device operation, and is designed to
eliminate any need for coordination between channels (i.e. it allows for channel independence).
There are two ZQ Calibration modes initiated with the MPC command: ZQCal Start, and ZQCal Latch. ZQCal Start
initiates the SDRAM’s calibration procedure, and ZQCal Latch captures the result and loads it into the SDRAM's
drivers.
A ZQCal Start command may be issued anytime the LPDDR4-SDRAM is not in a power-down state. A ZQCal
Latch Command may be issued anytime outside of power-down after tZQCAL has expired and all DQ bus
operations have completed. The CA Bus must maintain a Deselect state during tZQLAT to allow CA ODT
calibration settings to be updated. The following mode register fields that modify I/O parameters cannot be
changed following a ZQCal Start command and before tZQCAL has expired:
• PU-Cal (Pull-up Calibration VOH Point)
• PDDS (Pull Down Drive Strength and Rx Termination)
• DQ-ODT (DQ ODT Value)
• CA-ODT (CA ODT Value)
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ZQCal Reset
The ZQCal Reset command resets the output impedance calibration to a default accuracy of +/- 30% across
process, voltage, and temperature. This command is used to ensure output impedance accuracy to +/- 30% when
ZQCal Start and ZQCal Latch commands are not used.
The ZQCal Reset command is executed by writing MR10 OP[0]=1B.
ZQCal Timing Parameters
Parameter
Symbol
tZQCAL
Min/Max
Min
Value
1
Unit
us
ZQ Calibration Time
ZQ Calibration Latch Time
ZQ Calibration Reset Time
tZQLAT
Min
max(30ns,8nCK)
max(50ns,3nCK)
ns
tZQRESET
Min
ns
ZQCal Timing
Notes:
1. Write and Precharge operations shown for illustrative purposes.
Any single or multiple valid commands may be executed within the tZQCAL time and prior to latching the results.
2. Before the ZQ-Latch command can be executed, any prior commands utilizing the DQ bus must have completed.
Write commands with DQ Termination must be given enough time to turn off the DQ-ODT before issuing the ZQ-Latch command.
See the ODT section for ODT timing.
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Multi-Channel Considerations for Dual Channel Devices
The LPDDR4-SDRAM includes a single ZQ pin and associated ZQ Calibration circuitry. Calibration values from
this circuit will be used by both channels according to the following protocol:
1. ZQCal Start commands may be issued to either or both channels.
2. ZQCal Start commands may be issued when either or both channels are executing other commands and
other commands may be issued during tZQCAL.
3. ZQCal Start commands may be issued to both channels simultaneously.
4. The ZQCal Start command will begin the calibration unless a previously requested ZQ calibration is in
progress.
5. If a ZQCal Start command is received while a ZQ calibration is in progress on the SDRAM, the ZQCal Start
command will be ignored and the in-progress calibration will not be interrupted.
6. ZQCal Latch commands are required for each channel.
7. ZQCal Latch commands may be issued to both channels simultaneously.
8. ZQCal Latch commands will latch results of the most recent ZQCal Start command provided tZQCAL has
been met.
9. ZQCal Latch commands which do not meet tZQCAL will latch the results of the most recently completed ZQ
calibration.
10. ZQ Reset MRW commands will only reset the calibration values for the channel issuing the command.
In compliance with complete channel independence, either channel may issue ZQCal Start and ZQCal Latch
commands as needed without regard to the state of the other channel.
ZQ External Resistor, Tolerance, and Capacitive Loading
To use the ZQ calibration function, a 240 ohm +/- 1% tolerance external resistor must be connected between the
ZQ pin and VDDQ
.
If the system configuration shares the CA bus to form a x32 (or wider) channel, the ZQ pin of each die’s x16
channel shall use a separate ZQCal resistor.
If the system configuration has more than one rank, and if the ZQ pins of both ranks are attached to a single
resistor, then the SDRAM controller must ensure that the ZQCal’s don’t overlap.
The total capacitive loading on the ZQ pin must be limited to 25pF.
Example: If a system configuration shares a CA bus between ‘n’ channels to form a n * 16 wide bus, and no means
are available to control the ZQCal separately for each channel (i.e. separate CS, CKE, or CK), then each x16
channel must have a separate ZQCal resistor.
Example: For a x32, two rank system, each x16 channel must have its own ZQCal resistor, but the ZQCal resistor
can be shared between ranks on each x16 channel. In this configuration, the CS signal can be used to ensure that
the ZQCal commands for Rank[0] and Rank[1] don't overlap.
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Pull Up/Pull Down Driver Characteristics and Calibration
Pull-down Driver Characteristics, with ZQ Calibration
Resistor
Min
0.9
0.9
0.9
0.9
0.9
0.9
Nom
Max
1.1
1.1
1.1
1.1
1.1
1.1
Unit
R
,nom
ONPD
40 Ohm
48 Ohm
60 Ohm
80 Ohm
1
1
1
1
1
1
RZQ/6
RZQ/5
RZQ/4
RZQ/3
RZQ/2
RZQ/1
R
R
R
R
ON40PD
ON48PD
ON60PD
ON80PD
120 Ohm
240 Ohm
R
ON120PD
ON240PD
R
Notes:
1. All value are after ZQ Calibration. Without ZQ Calibration RONPD values are ± 30%.
Pull-Up Characteristics, with ZQ Calibration
VOH,nom(mV)
Min
0.9
Nom
Max
1.1
Unit
VOH ,nom
PU
440
367
1
1
VOH,nom
VOH,nom
V /2.5
DDQ
0.9
1.1
V /3
DDQ
Notes:
1. All values are after ZQ Calibration. Without ZQ Calibration VOH(nom) values are ± 30%.
2. VOH,nom (mV) values are based on a nominal VDDQ = 1.1V.
Valid Calibration Points
ODT Value
VOHPU,nom
240
120
80
60
48
40
VALID
VALID
VALID
VALID
VALID
VALID
DNU
VALID
DNU
VALID
DNU
VALID
V
/2.5
DDQ
V
/3
DDQ
Notes:
1. Once the output is calibrated for a given VOH(nom) calibration point, the ODT value may be changed without recalibration.
2. If the VOH(nom) calibration point is changed, then re-calibration is required.
3. DNU = Do Not Use
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
On Die Termination for Command/Address Bus
ODT (On-Die Termination) is a feature of the LPDDR4 SDRAM that allows the SDRAM to turn on/off termination
resistance for CK, , CS and CA[5:0] signals without the ODT control pin.
The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to
turn on and off termination resistance for any target DRAM devices via Mode Register setting.
A simple functional representation of the DRAM ODT feature is shown in following figure.
Functional Representation of CA ODT
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8Gb: NT6AN256T32AV
ODT Mode Register and ODT State Table
ODT termination values are set and enabled via MR11. The CA bus (CK, , CS, CA[5:0]) ODT resistance values
are set by MR11 OP[6:4]. The default state for the CA is ODT disabled.
ODT is applied on the CA bus to the CK, , CS and CA[5:0] signals. The CA ODT of the device is designed to
enable one rank to terminate the entire command bus in a multirank system, so only one termination load will be
present even if multiple devices are sharing the command signals. For this reason, CA ODT remains on even
when the device is in the power-down or self-refresh power-down states.
The die has a bond-pad (ODT_CA) for multirank operations. When the ODT_CA pad is LOW, the die will not
terminate the CA bus regardless of the state of the mode register CA ODT bits (MR11 OP[6:4]). If, however, the
ODT_CA bond-pad is HIGH, and the mode register CA ODT bits are enabled, the die will terminate the CA bus
with the ODT values found in MR11 OP[6:4]. In a multirank system, the terminating rank should be trained first,
followed by the non-terminating rank(s).
Command Bus ODT State
ODTE-CA
MR11[6:4]
Disabled1
Valid3
ODT_CA
ODTD-CA
MR22[5]
Valid3
Valid3
Valid3
Valid3
Valid3
0
ODTF-CK
ODTF-CS
ODT State
for CA
Off
ODT State
ODT State
for CS
Off
bond pad
MR22[3]
MR22[4]
for CK/
Off
Valid2
Valid3
Valid3
0
0
0
0
1
1
0
0
Off
Off
Off
Valid3
Valid3
Valid3
Valid3
0
1
1
0
Off
Off
On
Off
On
Off
1
1
Off
On
On
Valid3
Valid3
Valid3
Valid3
On
On
On
Valid3
1
Off
On
On
Notes:
1. Default Value
2. “Valid” means “H or L (but a defined logic level)”
3. “Valid” means “0 or 1”
4. The state of ODT_CA is not changed when the DRAM enters power-down mode. This maintains termination for alternate ranks in
multi-rank systems.
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8Gb: NT6AN256T32AV
ODT Mode Register and ODT Characteristics
Vout
RTT =
｜Iout｜
On Die Termination for CA
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8Gb: NT6AN256T32AV
ODT DC Electrical Characteristics, assuming RZQ = 240 +/-1% over the entire operating temperature
range after a proper ZQ calibration up to 3200Mbps
MR11[6:4]
RTT
Vout
Min
0.8
0.9
0.9
0.8
0.9
0.9
0.8
0.9
0.9
0.8
0.9
0.9
0.8
0.9
0.9
0.8
0.9
0.9
Nom
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max
1.1
1.1
1.2
1.1
1.1
1.2
1.1
1.1
1.2
1.1
1.1
1.2
1.1
1.1
1.2
1.1
1.1
1.2
Unit
Notes
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
RZQ
VOLdc= 0.1 * V
DD2
001
RZQ
240
VOMdc= 0.33 * V
DD2
RZQ
VOHdc= 0.5 * V
DD2
RZQ/2
RZQ/2
RZQ/2
RZQ/3
RZQ/3
RZQ/3
RZQ/4
RZQ/4
RZQ/4
RZQ/5
RZQ/5
RZQ/5
RZQ/6
RZQ/6
RZQ/6
VOLdc= 0.1 * V
VOMdc= 0.33 * V
DD2
010
011
100
101
110
120
80
60
48
40
DD2
VOHdc= 0.5 * V
DD2
VOLdc= 0.1 * V
VOMdc= 0.33 * V
DD2
DD2
VOHdc= 0.5 * V
DD2
VOLdc= 0.1 * V
VOMdc= 0.33 * V
DD2
DD2
VOHdc= 0.5 * V
DD2
VOLdc= 0.1 * V
VOMdc= 0.33 * V
DD2
DD2
VOHdc= 0.5 * V
DD2
VOLdc= 0.1 * V
VOMdc= 0.33 * V
DD2
DD2
VOHdc= 0.5 * V
DD2
Mismatch CA-CA
within clk group
Notes:
1
-
%
1,2,4
0.33* V
TBD
DD2
1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if
temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity1.
2. Pull-dn ODT resistors are recommended to be calibrated at 0.33*VDD2. Other calibration schemes may be used to achieve the linearity
spec shown above, e.g. calibration at 0.5*VDD2 and 0.1*VDD2
.
3. Measurement definition for RTT: TBD1
4. CA to CA mismatch within clock group (CA,CS) variation for a given component including CK and (characterized).
RODT (max) – RODT(min)
CA- CA Mismatch
=
RODT(avg)
NOTE1. As of publication of this document, under discussion by the formulating committee.
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4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
ODT DC Electrical Characteristics, assuming RZQ = 240 +/-1% over the entire operating temperature
range after a proper ZQ calibration for beyond 3200Mbps
MR11[6:4]
RTT
Vout
Min
0.8
0.9
0.9
0.8
0.9
0.9
0.8
0.9
0.9
0.8
Nom
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max
1.1
1.1
1.3
1.1
1.1
1.3
1.1
1.1
1.3
1.1
Unit
RZQ
Notes
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
VOLdc= 0.1 * V
DD2
001
RZQ
240
VOMdc= 0.33 * V
DD2
RZQ
VOHdc= 0.5 * V
DD2
RZQ/2
RZQ/2
RZQ/2
RZQ/3
RZQ/3
RZQ/3
RZQ/4
VOLdc= 0.1 * V
VOMdc= 0.33 * V
DD2
010
011
120
80
DD2
VOHdc= 0.5 * V
DD2
VOLdc= 0.1 * V
VOMdc= 0.33 * V
DD2
DD2
VOHdc= 0.5 * V
DD2
VOLdc= 0.1 * V
VOMdc= 0.33 * V
DD2
100
101
110
0.9
1.0
1.1
RZQ/4
1,2,3
60
48
40
DD2
DD2
0.9
0.8
0.9
0.9
0.8
0.9
0.9
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.3
1.1
1.1
1.3
1.1
1.1
1.3
RZQ/4
RZQ/5
RZQ/5
RZQ/5
RZQ/6
RZQ/6
RZQ/6
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
VOHdc= 0.5 * V
DD2
VOLdc= 0.1 * V
VOMdc= 0.33 * V
DD2
VOHdc= 0.5 * V
DD2
VOLdc= 0.1 * V
VOMdc= 0.33 * V
DD2
DD2
VOHdc= 0.5 * V
DD2
Mismatch CA-CA
within clk group
Notes:
1
-
%
1,2,4
0.33* V
TBD
DD2
1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if
temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity1.
2. Pull-dn ODT resistors are recommended to be calibrated at 0.33*VDD2. Other calibration schemes may be used to achieve the linearity
spec shown above, e.g. calibration at 0.5*VDD2 and 0.1*VDD2
.
3. Measurement definition for RTT: TBD1
4. CA to CA mismatch within clock group (CA,CS) variation for a given component including CK and (characterized).
RODT (max) – RODT(min)
CA- CA Mismatch
=
RODT(avg)
NOTE1. As of publication of this document, under discussion by the formulating committee.
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4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
ODT for Command/Address update time
ODT for Command/Address update time after Mode Register set are shown in following figure.
ODT for Command/Address setting update timing in 4 Clock Cycle Command
Notes:
1. 4 Clock Cycle Command
ODT CA AC Timing
Speed
2133/2400/2667/3200/3733/4267
Unit Notes
Parameter
ODT CA Value Update Time
Symbol
Min
Max
tODTUP
RU(20ns/tCK(avg))
-
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
On-Die Termination
ODT (On-Die Termination) is a feature of the LPDDR4 SDRAM that allows the DRAM to turn on/off termination
resistance for each DQ, DQS, and DMI signals without the ODT control pin. The ODT feature is designed to
improve signal integrity of the memory channel by allowing the DRAM controller to turn on and off termination
resistance for any target DRAM devices during Write or Mask Write operation.
The ODT feature is off and cannot be supported in Power Down and Self-Refresh modes.
A simple functional representation of the DRAM ODT feature is shown in following figure.
Functional Representation of ODT
The switch is enabled by the internal ODT control logic, which uses the Write-1 or Mask Write-1 command and
other mode register control information. The value of RTT is determined by the settings of Mode Register bits.
ODT Mode Register
The ODT Mode is enabled if MR11 OP[3:0] are non zero. In this case, the value of RTT is determined by the
settings of those bits. The ODT Mode is disabled if MR11 OP[3] = 0.
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8Gb: NT6AN256T32AV
Asynchronous ODT
When ODT Mode is enabled in MR11 OP[3:0], DRAM ODT is always Hi-Z. DRAM ODT feature is automatically
turned ON asynchronously based on the Write-1 or Mask Write-1 command that DRAM samples. After the write
burst is complete, DRAM ODT featured is automatically turned OFF asynchronously.
Following timing parameters apply when DRAM ODT mode is enabled:
• ODTLon, tODTon,min, tODTon,max
• ODTLoff, tODToff,min, tODToff,max
ODTLon is a synchronous parameter and it is the latency from CAS-2 command to tODTon reference. ODTLon
latency is a fixed latency value for each speed bin. Each speed bin has a different ODTLon latency.
Minimum RTT turn-on time (tODTon,min) is the point in time when the device termination circuit leaves high
impedance state and ODT resistance begins to turn on.
Maximum RTT turn on time (tODTon,max) is the point in time when the ODT resistance is fully on.
tODTon,min and tODTon,max are measured once ODTLon latency is satisfied from CAS-2 command.
ODTLoff is a synchronous parameter and it is the latency from CAS-2 command to tODToff reference. ODTLoff
latency is a fixed latency value for each speed bin. Each speed bin has a different ODTLoff latency.
Minimum RTT turn-off time (tODToff,min) is the point in time when the device termination circuit starts to turn off
the ODT resistance.
Maximum ODT turn off time (tODToff,max) is the point in time when the on-die termination has reached high
impedance.
tODToff,min and tODToff,max are measured once ODTLoff latency is satisfied from CAS-2 command.
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8Gb: NT6AN256T32AV
ODTLon and ODTLoff Latency Values
1
ODTLon Latency
tWPRE = 2 tCK
2
Lower Clock
Upper Clock
ODTLoff Latency
Frequency Limit(>)
Frequency Limit()
WL Set "A"
WL Set "B"
WL Set "A"
N/A
N/A
N/A
20
WL Set "B"
N/A
N/A
N/A
4
N/A
N/A
6
N/A
N/A
22
10
266
533
266
533
800
12
28
800
1066
1333
1600
1866
2133
MHz
4
14
22
32
1066
1333
1600
1866
MHz
6
18
24
36
6
20
26
40
8
24
28
44
nCK
nCK
nCK
nCK
Notes:
1. ODTLon is referenced from CAS-2 command.
2. ODTLoff as shown in table assumes BL=16. For BL32, 8 tCK should be added.
3. Clock Frequency herewith is a reference base on JEDEC's. Precise tCK setting needs to follow where defined on speed compatible
table in section “Operating frequency”, exceptional setting please confirm with NTC.
Asynchronous ODT Turn On and Turn Off Timing
Parameter
tODTon, min
tODTon, max
tODToff, min
tODToff, max
800 - 2133 MHz
Unit
ns
1.5
3.5
1.5
3.5
ns
ns
ns
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8Gb: NT6AN256T32AV
Asynchronous ODTon/ODToff Timing
Notes:
1. BL=16, Write Postamble = 0.5nCK, DQ/DQS: VSSQ termination
2. Din n = data-in to columnm n
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
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ODT during Write Leveling
If ODT is enabled in MR11 OP[3:0], in Write Leveling mode, DRAM always provides the termination on DQS/
signals. DQ termination is always off in Write Leveling mode regardless.
DRAM Termination Function in Write Leveling Mode
ODT Enabled in MR11
Disabled
DQS/ termination
DQ termination
OFF
ON
OFF
OFF
Enabled
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On Die Termination for DQ, DQS and DMI
On-Die Termination effective resistance RTT is defined by MR11 OP[2:0].
ODT is applied to the DQ, DMI, DQS and pins.
A functional representation of the on-die termination is shown in the figure below.
Vout
RTT =
｜Iout｜
On Die Termination
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ODT DC Electrical Characteristics, assuming RZQ = 240Ω +/-1% over the entire operating temperature
range after a proper ZQ calibration for up to 3200Mbps
MR11
RTT
Vout
Min
Nom
Max
Unit
Notes
OP[2:0]
0.8
0.9
0.9
0.8
0.9
0.9
0.8
0.9
0.9
0.8
0.9
0.9
0.8
0.9
0.9
0.8
0.9
0.9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1.1
1.1
1.2
1.1
1.1
1.2
1.1
1.1
1.2
1.1
1.1
1.2
1.1
1.1
1.2
1.1
1.1
1.2
RZQ
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
VOLdc= 0.1* V
DDQ
001
240Ω
RZQ
VOMdc= 0.33* V
DDQ
RZQ
VOHdc= 0.5* V
DDQ
RZQ/2
RZQ/2
RZQ/2
RZQ/3
RZQ/3
RZQ/3
RZQ/4
RZQ/4
RZQ/4
RZQ/5
RZQ/5
RZQ/5
RZQ/6
RZQ/6
RZQ/6
VOLdc= 0.1* V
DDQ
010
011
100
101
110
120Ω
80Ω
60Ω
48Ω
40Ω
VOMdc= 0.33* V
DDQ
VOHdc= 0.5* V
DDQ
VOLdc= 0.1* V
DDQ
VOMdc= 0.33* V
DDQ
VOHdc= 0.5* V
DDQ
VOLdc= 0.1* V
DDQ
VOMdc= 0.33* V
DDQ
VOHdc= 0.5* V
DDQ
VOLdc= 0.1* V
DDQ
VOMdc= 0.33* V
DDQ
VOHdc= 0.5* V
DDQ
VOLdc= 0.1* V
DDQ
VOMdc= 0.33* V
DDQ
VOHdc= 0.5* V
DDQ
Mismatch DQ-DQ
within byte
-
2
%
1,2,4
0.33* V
DDQ
Notes:
1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if
temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity1.
2. Pull-dn ODT resistors are recommended to be calibrated at 0.33*VDDQ. Other calibration schemes may be used to achieve the linearity
spec shown above, e.g. calibration at 0.5*VDDQ and 0.1*VDDQ
3. Measurement definition for RTT: TBD1
.
4. DQ to DQ mismatch within byte variation for a given component including DQS and (characterized).
RODT (max) – RODT(min)
DQ - DQ Mismatch
=
RODT(avg)
NOTE1. As of publication of this document, under discussion by the formulating committee.
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8Gb: NT6AN256T32AV
ODT DC Electrical Characteristics, assuming RZQ = 240Ω +/-1% over the entire operating temperature
range after a proper ZQ calibration for beyond 3200Mbps
MR11
RTT
Vout
Min
Nom
Max
Unit
Notes
OP[2:0]
0.8
0.9
0.9
0.8
0.9
0.9
0.8
0.9
0.9
0.8
0.9
0.9
0.8
0.9
0.9
0.8
0.9
0.9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1.1
1.1
1.3
1.1
1.1
1.3
1.1
1.1
1.3
1.1
1.1
1.3
1.1
1.1
1.3
1.1
1.1
1.3
RZQ
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
VOLdc= 0.1* V
DDQ
001
240Ω
RZQ
VOMdc= 0.33* V
DDQ
DDQ
RZQ
VOHdc= 0.5* V
RZQ/2
RZQ/2
RZQ/2
RZQ/3
RZQ/3
RZQ/3
RZQ/4
RZQ/4
RZQ/4
RZQ/5
RZQ/5
RZQ/5
RZQ/6
RZQ/6
RZQ/6
VOLdc= 0.1* V
DDQ
010
011
100
101
110
120Ω
80Ω
60Ω
48Ω
40Ω
VOMdc= 0.33* V
DDQ
VOHdc= 0.5* V
DDQ
VOLdc= 0.1* V
DDQ
VOMdc= 0.33* V
DDQ
VOHdc= 0.5* V
DDQ
VOLdc= 0.1* V
DDQ
VOMdc= 0.33* V
DDQ
VOHdc= 0.5* V
DDQ
VOLdc= 0.1* V
DDQ
VOMdc= 0.33* V
DDQ
DDQ
VOHdc= 0.5* V
VOLdc= 0.1* V
DDQ
VOMdc= 0.33* V
DDQ
VOHdc= 0.5* V
DDQ
Mismatch DQ-DQ
within byte
-
2
%
1,2,4
0.33* V
DDQ
Notes:
1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if
temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity1.
2. Pull-dn ODT resistors are recommended to be calibrated at 0.33*VDDQ. Other calibration schemes may be used to achieve the linearity
spec shown above, e.g. calibration at 0.5*VDDQ and 0.1*VDDQ
3. Measurement definition for RTT: TBD1
.
4. DQ to DQ mismatch within byte variation for a given component including DQS and (characterized).
RODT (max) – RODT(min)
DQ - DQ Mismatch
=
RODT(avg)
NOTE1. As of publication of this document, under discussion by the formulating committee.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Output Driver and Termination Register Temperature and Voltage Sensitivity
If temperature and/or voltage change after calibration, the tolerance limits widen according to the tables shown
below.
Output Driver and Termination Register Sensitivity Definition
Definition
Resistor
Min
Max
Unit Notes
Point
0.33 x
VDDQ
0.33 x
VDDQ
0.33 x
VDDQ
0.33 x
VDD2
%
%
%
%
1,2
R
90-(dR dT x |T|)-(dR dV x |V|) 110+(dR dT x |T|)+(dR dV x |V|)
on on on on
ONPD
1,2,5
1,2,3
1,2,4
90-(dVOHdT x |T|)-(dVOHdV x |V|) 110+(dVOHdT x |T|)+(dVOHdV x|V|)
90-(dR dT x |T|)-(dR dV x |V|) 110+(dR dT x |T|)+(dR dV x |V|)
VOH
R
PU
)
TT(I/O
on
on
on
on
R
90-(dR dT x |T|)-(dR dV x |V|) 110+(dR dT x |T|)+(dR dV x |V|)
on on on on
TT(In)
Notes:
1. T = T - T(@ Calibration), V = V - V(@ Calibration)
2. dRONdT, dRONdV, dVOHdT, dVOHdV, dRTTdV, and dRTTdT are not subject to production test but are verified by design and
characterization.
3. This parameter applies to Input/Output pin such as DQS, DQ and DMI.
4. This parameter applies to Input pin such as CK, CA and CS.
5. Refer to Pull Up/Pull Down Driver Characteristics for VOHPU.
Output Driver and Termination Register Temperature and Voltage Sensitivity
Symbol
dR dT
Parameter
Min
0.00
0.00
0.00
0.00
0.00
0.00
Max
0.75
0.20
0.75
0.35
0.75
0.20
Unit
%/C
%/mV
%/C
%/mV
%/C
%/mV
R
Temperature Sensitivity
ON
ON
dR dV
R
Voltage Sensitivity
ON
ON
dVOHdT
dVOHdV
VOH Temperature Sensitivity
VOH Voltage Sensitivity
dR dT
R
Temperature Sensitivity
TT
TT
dR dV
R
Voltage Sensitivity
TT
TT
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Power-Down Mode
Power-Down Entry and Exit
Power-down is asynchronously entered when CKE is driven LOW. CKE must not go LOW while the following
operations are in progress:
• Mode Register Read
• Mode Register Write
• Read
• Write
• VREF(CA) Range and Value setting via MRW
• VREF(DQ) Range and Value setting via MRW
• Command Bus Training mode Entering/Exiting via MRW
• VRCG High Current mode Entering/Exiting via MRW
And the LPDDR4 DRAM cannot be placed in power-down state during “Start DQS Interval Oscillator” operation.
CKE can go LOW while any other operations such as row activation, Precharge, Auto Precharge, or Refresh are in
progress. The power-down IDD specification will not be applied until such operations are complete.
Entering power-down deactivates the input and output buffers, excluding CKE and . To ensure that there is
enough time to account for internal delay on the CKE signal path, CS input is required stable Low level and CA
input level is don’t care after CKE is driven LOW, this timing period is defined as tCKELCS. Clock input is required
after CKE is driven LOW, this timing period is defined as tCKELCK. CKE LOW will result in deactivation of all input
receivers except after tCKELCK has expired. In power-down mode, CKE must be held LOW; all other input
signals except are "Don't Care". CKE LOW must be maintained until tCKE,min is satisfied.
VDDQ can be turned off during power-down. Prior to exiting power-down, VDDQ must be within its
minimum/maximum operating range.
No refresh operations are performed in power-down mode except Self-Refresh power-down. The maximum
duration in non-Self-Refresh power-down mode is only limited by the refresh requirements outlined in the Refresh
command section.
The power-down state is asynchronously exited when CKE is driven HIGH. CKE HIGH must be maintained until
tCKE,min is satisfied. A valid, executable command can be applied with power-down exit latency tXP after CKE
goes HIGH. Power-down exit latency is defined in the AC timing parameter table.
Clock frequency change or Clock Stop is inhibited during tCMDCKE, tCKELCK, tCKCKEH, tXP, tMRWCKEL and
tZQCKE periods.
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4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
If power-down occurs when all banks are idle, this mode is referred to as idle power-down. if power-down occurs
when there is a row active in any bank, this mode is referred to as active power-down. And If power-down occurs
when Self Refresh is in progress, this mode is referred to as Self Refresh power-down in which the internal refresh
is continuing in the same way as Self Refresh mode.
When CA, CK and/or CS ODT is enabled via MR11 OP[6:4] and also via MR22 or CA-ODT pad setting, the rank
providing ODT will continue to terminate the command bus in all DRAM states including power-down.
Basic Power-Down Entry and Exit Timing
Notes:
1. Input clock frequency can be changed or the input clock can be stopped or floated during power-down, provided that upon exiting
power-down, the clock is stable and within specified limits for a minimum of tCKCKEH of stable clock prior to power-down exit and the
clock frequency is between the minimum and maximum specified frequency for the speed grade in use.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Read and Read with Auto Precharge to Power-Down Entry
Notes:
1. CKE must be held HIGH until the end of the burst operation.
2. Minimum Delay time from Read Command or Read with Auto-Precharge Command to falling edge of CKE signal is as follows.
Read Post-amble = 0.5nCK : MR1 OP[7]=[0] : (RL x tCK) + tDQSCK(Max) + ((BL/2) x tCK) + 1tCK
Read Post-amble = 1.5nCK : MR1 OP[7]=[1] : (RL x tCK) + tDQSCK(Max) + ((BL/2) x tCK) + 2tCK
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Write and Mask Write to Power-Down Entry
Notes:
1. CKE must be held HIGH until the end of the burst operation.
2. Minimum Delay time from Write Command or Mask Write Command to falling edge of CKE signal is as follows.
(WL x tCK) + tDQSS(Max) + tDQS2DQ(Max) + ((BL/2) x tCK) + tWR
3. This timing is applied regardless of DQ ODT Disable/Enable setting: MR11[OP2:0].
4. This timing diagram only applies to the Write and Mask Write Commands without Auto-Precharge.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Write with Auto Precharge and Mask Write with Auto Precharge to Power-Down Entry
Notes:
1. CKE must be held HIGH until the end of the burst operation.
2. Delay time from Write with Auto-Precharge Command or Mask Write with Auto-Precharge Command to falling edge of CKE signal is
more than (WL x tCK) + tDQSS(Max) + tDQS2DQ(Max) + ((BL/2) x tCK) + (nWR x tCK) + (2 x tCK)
3. Internal Precharge Command
4. This timing is applied regardless of DQ ODT Disable/Enable setting: MR11[OP2:0].
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4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Refresh entry to Power-Down Entry
Notes:
1. CKE must be held HIGH until tCMDCKE is satisfied.
Activate Command to Power-Down Entry
Notes:
1. CKE must be held HIGH until tCMDCKE is satisfied.
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4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Precharge Command to Power-Down Entry
Notes:
1. CKE must be held HIGH until tCMDCKE is satisfied.
Mode Register Read to Power-Down Entry
Notes:
1. CKE must be held HIGH until the end of the burst operation.
2. Minimum Delay time from Mode Register Read Command to falling edge of CKE signal is as follows:
Read Post-amble = 0.5nCK : MR1 OP[7]=[0] : (RL x tCK) + tDQSCK(Max) + ((BL/2) x tCK) + 1tCK
Read Post-amble = 1.5nCK : MR1 OP[7]=[1] : (RL x tCK) + tDQSCK(Max) + ((BL/2) x tCK) + 2tCK
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Mode Register Write to Power-Down Entry
Notes:
1. CKE must be held HIGH until tMRWCKEL is satisfied.
2. This timing is the general definition for Power Down Entry after Mode Register Write Command.
When a Mode Register Write Command changes a parameter or starts an operation that requires special timing
longer than tMRWCKEL, that timing must be satisfied before CKE is driven low.
Changing the Vref(DQ) value is one example, in this case the appropriate Vref_time-Short/Middle/Long must be satisfied.
Multi purpose Command for Start ZQ Calibration to Power-Down Entry
Notes:
1. ZQ Calibration continues if CKE goes low after tZQCKE is satisfied.
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8Gb: NT6AN256T32AV
Power-Down AC Timing
Min/
Symbol
Parameter
Data Rate
Unit Notes
Max
Power Down Timing
CKE minimum pulse width
tCKE
Min
Max(7.5ns, 4nCK)
-
(HIGH and LOW pulse width)
Delay from valid command to CKE input LOW
Valid Clock Requirement after CKE Input low
Valid CS Requirement before CKE Input Low
Valid CS Requirement after CKE Input low
Valid Clock Requirement before CKE Input High
Exit power- down to next valid command delay
Valid CS Requirement before CKE Input High
Valid CS Requirement after CKE Input High
Valid Clock and CS Requirement after CKE Input low
after MRW Command
tCMDCKE
tCKELCK
tCSCKE
Min
Min
Min
Min
Min
Min
Min
Min
Max(1.75ns, 3nCK)
Max(5ns, 5nCK)
1.75
ns
ns
ns
ns
ns
ns
ns
ns
1
1
tCKELCS
tCKCKEH
tXP
Max(5ns, 5nCK)
Max(1.75ns, 3nCK)
Max(7.5ns, 5nCK)
1.75
1
1
tCSCKEH
tCKEHCS
Max(7.5ns, 5nCK)
tMRWCKEL
tZQCKE
Min
Min
Max(14ns, 10nCK)
Max(1.75ns, 3nCK)
ns
ns
1
1
Valid Clock and CS Requirement after CKE Input low
after ZQ Calibration Start Command
Notes:
1. Delay time has to satisfy both analog time(ns) and clock count(nCK).
For example, tCMDCKE will not expire until CK has toggled through at least 3 full cycles
(3 *tCK) and 1.75ns has transpired.
The case which 3nCK is applied to is shown below.
tCMDCKE Timing
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Input Clock Stop and Frequency Change
LPDDR4 SDRAMs support input clock frequency change during CKE LOW under the following conditions:
• tCK(abs)min is met for each clock cycle;
• Refresh requirements apply during clock frequency change;
• During clock frequency change, only REFab or REFpb commands may be executing;
• Any Activate or Precharge commands have executed to completion prior to changing the frequency;
• The related timing conditions (tRCD, tRP) have been met prior to changing the frequency;
• The initial clock frequency shall be maintained for a minimum of 4 clock cycles after CKE goes LOW;
• The clock satisfies tCH(abs) and tCL(abs) for a minimum of 2 clock cycles prior to CKE going HIGH
After the input clock frequency is changed and CKE is held HIGH, additional MRW commands may be required to
set the WR, RL etc. These settings may need to be adjusted to meet minimum timing requirements at the target
clock frequency.
LPDDR4 devices support clock stop during CKE LOW under the following conditions:
• CK is held LOW and is held HIGH or both are floated during clock stop;
• Refresh requirements apply during clock stop;
• During clock stop, only REFab or REFpb commands may be executing;
• Any Activate or Precharge commands have executed to completion prior to stopping the clock;
• The related timing conditions (tRCD, tRP) have been met prior to stopping the clock;
• The initial clock frequency shall be maintained for a minimum of 4 clock cycles after CKE goes LOW;
• The clock satisfies tCH(abs) and tCL(abs) for a minimum of 2 clock cycles prior to CKE going HIGH
LPDDR4 devices support input clock frequency change during CKE HIGH under the following conditions:
• tCK(abs)min is met for each clock cycle;
• Refresh requirements apply during clock frequency change;
• Any Activate, Read, Write, Precharge, Mode Register Write, or Mode Register Read commands must have
executed to completion, including any associated data bursts prior to changing the frequency;
• The related timing conditions (tRCD, tWR, tWRA, tRP, tMRW, tMRR, etc.) have been met prior to changing
the frequency;
• CS shall be held LOW during clock frequency change;
• During clock frequency change, only REFab or REFpb commands may be executing;
• The LPDDR4 SDRAM is ready for normal operation after the clock satisfies tCH(abs) and tCL(abs) for a
minimum of 2*tCK+tXP.
After the input clock frequency is changed, additional MRW commands may be required to set the WR, RL etc.
These settings may need to be adjusted to meet minimum timing requirements at the target clock frequency.
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4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
LPDDR4 devices support clock stop during CKE HIGH under the following conditions:
• CK is held LOW and is held HIGH during clock stop;
• CS shall be held LOW during clock clock stop;
• Refresh requirements apply during clock stop;
• During clock stop, only REFab or REFpb commands may be executing;
• Any Activate, Read, Write, MPC(WRFIFO,RDFIFO,RDDQCAL), Precharge, Mode Register Write or Mode
Register Read commands must have executed to completion, including any associated data bursts and extra
4 clock cycles must be provided prior to stopping the clock;
• The related timing conditions (tRCD, tWR, tRP, tMRW, tMRR, tZQLAT, etc.) have been met prior to stopping
the clock;
• Read with auto pre-charge and write with auto pre-charge commands need extra 4 clock cycles in addition to
the related timing constraints, nWR and nRTP, to complete the operations.
• REFab, REFpb, SRE, SRX and MPC(Zqcal Start)commands are required to have 4 additional clocks prior to
stopping the clock same as CKE=L case.
• The LPDDR4 SDRAM is ready for normal operation after the clock is restarted and satisfies tCH(abs) and
tCL(abs) for a minimum of 2*tCK+tXP.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Truth Tables
Operation or timing that is not specified is illegal, and after such an event, in order to guarantee proper operation,
the LPDDR4 device must be reset or power-cycled and then restarted through the specified initialization sequence
before normal operation can continue.
CKE signal has to be held High when the commands listed in the command truth table input.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Command Truth Table
CK
SDRAM Command
CS CA0
CA1
CA2
CA3
CA4
CA5
Notes
1,2
edge
R1
R1
R2
R1
R2
R1
R2
R1
R2
R1
R2
R1
R2
R1
R2
R1
R2
R1
R2
R1
R2
R1
R2
R1
R2
R1
R2
R1
R2
R1
R2
R1
R2
R1
R2
R1
R2
Deselect(DES)
Multi Purpose Command
(MPC)
Precharge(PRE)
(Per Bank, All Bank)
Refresh(REF)
L
X
H
L
H
L
H
L
H
L
L
OP0
L
BA0
L
L
OP1
L
BA1
L
L
OP2
L
BA2
L
L
OP3
L
V
H
L
OP4
H
V
L
OP6
OP5
AB
V
AB
V
1,9
1,2,3,4
1,2,3,4
1,2
(Per Bank, All Bank)
BA0
L
BA1
L
BA2
L
V
H
V
H
V
Self Refresh Entry(SRE)
Write-1(WR-1)
V
V
V
H
L
H
L
L
BA0
L
L
BA1
L
H
BA2
H
L
V
L
L
C9
H
BL
AP
V
1,2,3,6,7,9
1,2
Self Refresh Exit(SRX)
Mask Write-1(MRW-1)
RFU
H
L
H
L
L
BA0
L
L
BA1
L
H
BA2
H
H
V
H
L
C9
H
L
AP
V
1,2,3,5,6,9
1,2
H
L
H
L
H
L
L
BA0
L
C2
L
H
BA1
H
C3
H
L
BA2
L
C4
L
L
V
L
C5
H
L
C9
H
C6
L
BL
AP
C8
C7
L
Read-1(RD-1)
1,2,3,6,7,9
1,8,9
CAS-2
(Write-2, Mask Write-2,Read-2, MRR-2, MPC)
RFU
1,2
V
V
H
L
H
L
L
L
H
H
L
H
L
H
L
V
RFU
1,2
H
OP7
Mode Register Write-1(MRW-1)
Mode Register Write-2(MRW-2)
Mode Register Read-1(MRR-1)
RFU
1,2,11
1,2,11
1,2,12
1,2
MA0 MA1
MA2 MA3
MA4 MA5
H
L
H
L
L
OP0
L
H
OP1
H
H
OP2
H
MA2 MA3
H
L
OP3
H
H
OP4
L
MA4 MA5
H
OP6
OP5
V
MA0 MA1
H
L
L
H
H
V
V
H
L
H
L
H
BA0
H
L
BA1
H
R12
BA2
R6
R13
V
R7
R3
R14
R10
R8
R15
R11
R9
Activate-1(ACT-1)
1,2,3,10
1,10,13
Activate-2(ACT-2)
R0
R1
R2
R4
R5
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
1. All LPDDR4 commands except for Deselect are 2 clock cycle long and defined by states of CS and CA[5:0] at the first rising edge of clock.
Deselect command is 1 clock cycle long.
2. "V" means "H" or "L" (a defined logic level). "X" means don’t care in which case CA[5:0] can be floated.
3. Bank addresses BA[2:0] determine which bank is to be operated upon.
4. AB "HIGH" during Precharge or Refresh command indicates that command must be applied to all banks and bank address is a don’t
care.
5. Mask Write-1 command supports only BL 16. For Mark Write-1 command, CA5 must be driven LOW on first rising clock cycle (R1).
6. AP "HIGH" during Write-1, Mask Write-1 or Read-1 commands indicates that an Auto-Precharge will occur to the bank associated with
the Write, Mask Write or Read command.
7. If Burst Length on-the-fly is enabled, BL "HIGH" during Write-1 or Read-1 command indicates that Burst Length should be set
on-the-Fly to BL=32. BL "LOW" during Write-1 or Read-1 command indicates that Burst Length should be set on-the-fly to BL=16. If
Burst Length on-the-fly is disabled, then BL must be driven to defined logic level "H" or "L".
8. For CAS-2 commands (Write-2 or Mask Write-2 or Read-2 or MRR-2 or MPC (Only Write FIFO, Read FIFO & Read DQ Calibration), C[1:0]
are not transmitted on the CA[5:0] bus and are assumed to be zero. Note that for CAS-2 Write-2 or CAS-2 Mask Write-2 command,
C[3:2] must be driven LOW.
9. Write-1 or Mask Write-1 or Read-1 or Mode Register Read-1 or MPC (Only Write FIFO, Read FIFO & Read DQ Calibration) command
must be immediately followed by CAS-2 command consecutively without any other command in between. Write-1 or Mask Write-1 or
Read-1 or Mode Register Read-1 or MPC (Only Write FIFO, Read FIFO & Read DQ Calibration) command must be issued first before
issuing CAS-2 command. MPC (Only Start & Stop DQS Oscillator, Start & Latch ZQ Calibration) commands do not require CAS-2
command; they require two additional DES or NOP commands consecutively before issuing any other commands..
10. Activate-1 command must be immediately followed by Activate-2 command consecutively without any other command in between.
Activate-1 command must be issued first before issuing Activate-2 command. Once Activate-1 command is issued, Activate-2 command
must be issued before issuing another Activate-1 command.
11. MRW-1 command must be immediately followed by MRW-2 command consecutively without any other command in between. MRW-1
command must be issued first before issuing MRW-2 command.
12. MRR-1 command must be immediately followed by CAS-2 command consecutively without any other command in between. MRR-1
command must be issued first before issuing CAS-2 command.
13. In case of the densities which not to use R17 and R18 as row address, R17 and R18 must both be driven High for every ACT-2 command
to maintain backward compatibility.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
TRR Mode - Target Row Refresh
A LPDDR4 SDRAM's row has a limited number of times a given row can be accessed within a refresh period
(tREFW * 2) prior to requiring adjacent rows to be refreshed. The Maximum Activate Count (MAC) is the maximum
number of activates that a single row can sustain within a refresh period before the adjacent rows need to be
refreshed. The row receiving the excessive actives is the Target Row (TRn), the adjacent rows to be refreshed are
the victim rows. When the MAC limit is reached on TRn, either the LPDRR4 SDRAM receive all (R * 2) Refresh
Commands before another row activate is issued, or the LPDRR4 SDRAM should be placed into Targeted Row
Refresh (TRR) mode. The TRR Mode will re-fresh the rows adjacent to the TRn that encountered tMAC limit.
If LPDDR4 SDRAM supports Unlimited MAC value: MR24 [OP2:0=000] and MR24 [OP3=1], Target Row Refresh
operation is not required. Even though LPDDR4 SDRAM allows to set MR24 [OP7=1]: TRR mode enable, in this
case LPDDR4 SDRAM's behavior is vendor specific. For example, a certain LPDDR4 SDRAM may ignore MRW
command for entering/exiting TRR mode or a certain SDRAM may support commands related TRR mode. See
vendor device datasheets for details about TRR mode definition at supporting Unlimited MAC value case.
There could be a maximum of two target rows to a victim row in a bank. The cumulative value of the ac-tivates
from the two target rows on a victim row in a bank should not exceed MAC value as well.
MR24 fields required to support the new TRR settings. Setting MR24 [OP7=1] enables TRR Mode and setting
MR24 [OP7=0] disables TRR Mode. MR24 [OP6:OP4] defines which bank (BAn) the target row is located in (See
MR24 table for details).
The TRR mode must be disabled during initialization as well as any other LPDRR4 SDRAM calibration modes.
The TRR mode is entered from a DRAM Idle State, once TRR mode has been entered, no other Mode Register
commands are allowed until TRR mode is completed, except setting MR24 [OP7=0] to interrupt and reissue the
TRR mode is allowed.
When enabled; TRR Mode is self-clearing; the mode will be disabled automatically after the completion of defined
TRR flow; after the 3rd BAn precharge has completed plus tMRD. Optionally the TRR mode can also be exited via
another MRS command at the completion of TRR by setting MR24 [OP7=0]; if the TRR is exited via another MRS
command, the value written to MR24 [OP6:OP4] are don’t cares.
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4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
TRR Mode Operation
1. The following steps must be performed when TRR mode is enabled. This mode requires all three ACT (ACT1,
ACT2 and ACT3) and three cor-responding PRE commands (PRE1, PRE2 and PRE3) to complete TRR mode.
A Precharge All (PREA) commands issued while LPDDR4 SDRAM is in TRR mode will also perform precharge
to BAn and counts towards a PREn command.
2. Prior to issuing the MRW command to enter TRR mode, the SDRAM should be in the idle state. A MRW
command must be issued with MR24 [OP7=1] and MR24 [OP6:4] defining the bank in which the targeted row is
located. All other MR24 bits should remain unchanged.
3. No activity is to occur in the DRAM until tMRD has been satisfied. Once tMRD has been satisfied, the only
commands to BAn allowed are ACT and PRE until the TRR mode has been completed.
4. The first ACT to the BAn with the TRn address can now be applied, no other command is allowed at this point.
All other banks must remain inactive from when the first BAn ACT command is issued until [(1.5 * tRAS) + tRP]
is satisfied.
5. After the first ACT to the BAn with the TRn address is issued, a PRE to BAn is to be issued (1.5 * tRAS) later;
and then followed tRP later by the second ACT to the BAn with the TRn address. Once the 2nd activate to the
BAn is issued, nonBAn banks are allowed to have activity.
6. After the second ACT to the BAn with the TRn address is issued, a PRE to BAn is to be issued tRAS later and
then followed tRP later by the third ACT to the BAn with the TRn address.
7. After the third ACT to the BAn with the TRn address is issued, a PRE to BAn would be issued tRAS later; and
once the third PRE has been issued, nonBAn banks are not allowed to have activity until TRR mode is exited.
The TRR mode is completed once tRP plus tMRD is satisfied.
8. TRR mode must be completed as specified to guarantee that adjacent rows are refreshed. Any-time the TRR
mode is interrupted and not completed, the interrupted TRR Mode must be cleared and then subsequently
performed again. To clear an interrupted TRR mode, an MR24 change is required with setting MR24 [OP7=0],
MR24 [OP6:4] are don’t care, followed by three PRE to BAn, tRP time in between each PRE command. The
complete TRR sequence (Steps 2-7) must be then re-issued and completed to guarantee that the adjacent rows
are refreshed.
9. Refresh command to the LPDRR4 SDRAM or entering Self-Refresh mode is not allowed while the DRAM is in
TRR mode.
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8Gb: NT6AN256T32AV
TRR Mode
Notes:
1. TRn is targeted row.
2. Bank BAn represents the bank in which the targeted row is located.
3. TRR mode self-clears after tMRD + tRP measured from 3rd BAn precharge PRE3 at clock edge Th4.
4. TRR mode or any other activity can be re-engaged after tRP + tMRD from 3rd BAn precharge PRE3.
PRE_ALL also counts if issued instead of PREn. TRR mode is cleared by DRAM after PRE3 to the BAn bank.
5. Activate commands to BAn during TRR mode do not provide refreshing support, i.e. the Refresh counter is unaffected.
6. The DRAM must restore the degraded row(s) caused by excessive activation of the targeted row (TRn) necessary to meet refresh
requirements.
7. A new TRR mode must wait tMRD+tRP time after the third precharge.
8. BAn may not be used with any other command.
9. ACT and PRE are the only allowed commands to BAn during TRR Mode.
10. Refresh commands are not allowed during TRR mode.
11. All DRAM timings are to be met by DRAM during TRR mode such as tFAW. Issuing of ACT1, ACT2 and ACT3 counts towards tFAW
budget.
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4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Post Package Repair (PPR)
LPDDR4 supports Fail Row address repair as optional feature and it is readable through MR25 OP[7:0] PPR
provides simple and easy repair method in the system and Fail Row address can be repaired by the electrical
programming of Electrical-fuse scheme.
With PPR, LPDDR4 can correct 1Row per Bank.
Electrical-fuse cannot be switched back to un-fused states once it is programmed. The controller should prevent
unintended the PPR mode entry and repair.
Fail Row Address Repair
The following is procedure of PPR.
1. Before entering 'PPR' mode, All banks must be Precharged
2. Enable PPR using MR4 bit "OP4=1" and wait tMRD
3. Issue ACT command with Fail Row address
4. Wait tPGM to allow DRAM repair target Row Address internally then issue PRE
5. Wait tPGM_Exit after PRE which allow DRAM to recognize repaired Row address RAn
6. Exit PPR with setting MR4 bit "OP4=0"
7. LPDDR4 will accept any valid command after tPGMPST
8. Repeat steps in 'Reset Initialization with Stable Power' section
9. In More than one fail address repair case, Repeat Step 2 to 8
Once PPR mode is exited, to confirm if target row is repaired correctly, host can verify by writing data into the
target row and reading it back after PPR exit with MR4 [OP4=0] and tPGMPST.
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8Gb: NT6AN256T32AV
The following Timing diagram shows PPR operation.
PPR Timing
Notes:
1. During tPGM, any other commands (including refresh) are not allowed on each die.
2. With one PPR command, only one row can be repaired at one time per die.
3. When PPR procedure is done, reset command is required before normal operation.
4. During PPR, memory contents is not refreshed and may be lost.
5. Assert Reset_n below 0.2 X VDD2. Reset_n needs to be maintained LOW for minimum tPW_RESET. CKE must be pulled LOW at least
10ns before deassserting .
6. After RESET command, follow steps 4 to 10 in ‘Voltage Ramp and Device Initialization’ section.
PPR Timing Parameters
Parameter
Symbol
tPGM
Min
1000
15
Max
Unit
ms
ns
PPR Programming Time
PPR Exit Time
-
-
-
-
tPGM_Exit
tPGMPST
tCKPGM
New Address Setting time
PPR Programming Clock
50
us
1.25
ns
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Absolute Maximum DC Ratings
Stresses greater than those listed may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Parameter
Symbol
Min
-0.4
-0.4
-0.4
-0.4
-55
Max
2.1
Unit Notes
V
V
1
1
1
V
V
V
supply voltage relative to V
supply voltage relative to V
V
V
DD1
DD2
DDQ
SS
DD1
1.5
SS
DD2
VDDQ
VIN, VOUT
TSTG
1.5
V
supply voltage relative to V
SSQ
1.5
V
Voltage on any ball except V
Storage Temperature
relative to V
DD1
SS
125
°C
2
Notes:
1. See “Power-Ramp” for relationships between power supplies.
2. Storage Temperature is the case surface temperature on the center/top side of the LPDDR4 device. For the measurement
conditions, please refer to JESD51-2.
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AC & DC Operating Conditions
Recommended DC Operating Conditions
DRAM
Symbol
VDD1
Min
1.70
1.06
1.06
Typ
1.80
1.10
1.10
Max
1.95
1.17
1.17
Unit
V
Notes
1,2
Core 1 Power
Core 2 Power/Input Buffer Power
I/O Buffer Power
VDD2
V
1,2,3
2,3
VDDQ
V
Notes:
1. VDD1 uses significantly less current than VDD2.
2. The volttage range is for DC voltage only. DC is defined as the voltage supplied at the DRAM and is inclusive of all noise up to
20MHz at the DRAM package ball.
3. VdIVW and TdIVW limits described elsewhere in this document apply for voltage noise on supply voltages of
up to 45 mV (peak-to-peak) from DC to 20MHz.
Input Leakage Current
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input Leakage current
-4
4
uA
1,2
I
L
Notes:
1. For CK, , DQ, CKE, CS, CA, ODT_CA and . Any Input 0V ≤ VIN ≤ VDD2 (All other pins not under test = 0V).
2. CA ODT is disabled for CK, , CS and CA.
Input/Output Leakage Current
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input/Output Leakage current
IOZ
-5
5
uA
1,2
Notes:
1. For DQ, DQS, DQS and DMI. Any I/O 0V ≤ VOUT ≤ VDDQ.
2. I/Os status are disabled: High Impedance and ODT off.
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8Gb: NT6AN256T32AV
Operating Temperature Range
Parameter/Condition
Symbol
Min
-30
85
Max
85
Unit
Standard
C°
T
OPER
Elevated
105
Notes:
1. Operating Temperature is the case surface temperature on the center-top side of the LPDDR4 device. For the measurement
conditions, please refer to JESD51-2.
2. mSome applications require operation of LPDDR4 in the maximum temperature conditions in the Elevated Temperature Range
between 85 °C and 105 °C case temperature. For LPDDR4 devices, derating may be necessary to operate in this range. See MR4.
3. Either the device case temperature rating or the temperature sensor (See “Temperature Sensor”) may be used to set an
appropriate refresh rate, determine the need for AC timing de-rating and/or monitor the operating temperature. When using the
temperature sensor, the actual device case temperature may be higher than the TOPER rating that applies for the Standard or
Extended Temperature Ranges. For example, TCASE may be above 85C when the temperature sensor indicates a temperature of
less than 85 C.
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4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
AC and DC Input/Output Measurement levels
1.1V High speed LVCMOS (HS_LLVCMOS)
Standard specifications
All voltages are referenced to ground except where noted.
DC electrical characteristics
LPDDR4 Input Level for CKE
This definition applies to CKE_A/B.
Parameter
Symbol
VIH(AC)
VIL(AC)
VIH(DC)
VIL(DC)
Min
Max
+0.2
Unit Notes
Input high level (AC)
Input low level (AC)
Input high level (DC)
Input low level (DC)
V
V
V
V
1
1
0.75*V
-0.2
V
DD2
DD2
0.25*V
DD2
0.65* V
-0.2
V
+0.2
DD2
DD2
0.35*V
DD2
Notes:
1. Refer LPDDR4 AC Over/Undershoot section
Class-1 LPDDR4 Input AC timing definition for CKE
Notes:
1. AC level is guaranteed transition point.
2. DC level is hysteresis.
LPDDR4 Input Level for and ODT_CA
This definition applies to and ODT_CA
Parameter
Symbol
VIH(AC)
VIL(AC)
Min
Max
+0.2
Unit Notes
Input high level (AC)
Input low level (AC)
V
V
1
1
0.80*V
-0.2
V
DD2
DD2
0.20*V
DD2
Notes:
1. Refer LPDDR4 AC Over/Undershoot section
LPDDR4 Input AC timing definition for and ODT_CA
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8Gb: NT6AN256T32AV
AC Over/Undershoot
LPDDR4 AC Over/Undershoot
Parameter
Specification
0.35V
Maximum peak Amplitude allowed for overshoot area
Maximum peak Amplitude allowed for undershoot area
Maximum overshoot area above VDD/VDDQ
0.35V
0.8V-ns
0.8V-ns
Maximum undershoot area below VSS/VSSQ
AC Overshoot and Undershoot Definition for Address and Control Pins
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Differential Input Voltage
Differential Input Voltage for CK
CK Differential Input Voltage
CK differential input voltage
Data Rate
a
Parameter
Symbol
1600/1867
2133/2400/3200
3733/4267
Min Max
360
Unit Notes
Min
Max
Min
Max
CK differential input voltage
Vindiff_CK
420
-
380
-
-
mV
1
a. The following requirements apply for DQ operating frequencies at or below 1333Mbps for all speed bins for the first column
1600/1867.
Notes:
1. The peak voltage of Differential CK signals is calculated in a following equation.
Vindiff_CK = (Max Peak Voltage) - (Min Peak Voltage)
Max Peak Voltage = Max(f(t))
Min Peak Voltage = Min(f(t))
f(t) = VCK - V
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8Gb: NT6AN256T32AV
Peak voltage calculation method
The peak voltage of Differential Clock signals are calculated in a following equation.
VIH.DIFF.Peak Voltage = Max(f(t))
VIL.DIFF.Peak Voltage = Min(f(t))
f(t) = VCK - V
Definition of differential Clock Peak Voltage
Notes:
1. VREFCA is LPDDR4 SDRAM internal setting value by VREF Training.
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8Gb: NT6AN256T32AV
Single-Ended Input Voltage for Clock
The minimum input voltage need to satisfy both Vinse_CK, Vinse_CK_High/Low specification at input
receiver.
Clock Single-Ended Input Voltage
Notes:
1. VREFCA is LPDDR4 SDRAM internal setting value by VREF Training.
Clock Single-Ended input voltage
Data Rate
a
Parameter
Symbol
1600/1867
2133/2400/3200
3733/4267
Min Max
Unit Notes
Min
Max
Min
Max
Clock Single-Ended
input voltage
Clock Single-Ended input
voltage High from VREFDQ
Clock Single-Ended input
voltage Low from VREFDQ
Vinse_CK
210
-
-
-
190
-
180
90
-
-
-
mV
mV
mV
Vinse_CK_High 105
Vinse_CK_Low 105
95
95
-
-
90
a. The following requirements apply for DQ operating frequencies at or below 1333Mbps for all speed bins for the first column
1600/1867.
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Differential Input Slew Rate Definition for Clock
Input slew rate for differential signals (CK, ) are defined and measured as shown in the following figure and
table.
Differential Input Slew Rate Definition for CK,
Notes:
1. Differential signal rising edge from VILdiff_CK to VIHdiff_CK must be monotonic slope.
2. Differential signal falling edge from VIHdiff_CK to VILdiff_CK must be monotonic slope.
Differential Input Slew Rate Definition for CK,
Measured
Description
Defined by
From
To
Differential input slew rate for
rising edge(CK - )
Differential input slew rate for
falling edge(CK - )
VILdiff_CK VIHdiff_CK
VIHdiff_CK VILdiff_CK
|VILdiff_CK - VIHdiff_CK|/DeltaTRdiff
|VILdiff_CK - VIHdiff_CK|/DeltaTFdiff
Differential Input Level for CK,
Data Rate
2133/2400/3200
a
Parameter
Symbol
1600/1867
3733/4267
Min Max
Unit Notes
Min
175
-
Max
-
Min
155
-
Max
-
Differential Input High
Differential Input Low
VIHdiff_CK
VILdiff_CK
145
-
-
mV
mV
-175
-155
-145
a. The following requirements apply for DQ operating frequencies at or below 1333Mbps for all speed bins for the first column
1600/1867.
Differential Input Slew Rate for CK,
Data Rate
a
Parameter
Symbol
1600/1867
2133/2400/320
3733/4267
Min Max
14
Unit Notes
Min
Max
14
Min
Max
Differential Input
Slew Rate for Clock
SRIdiff_CK
2
2
14
2
V/ns
a. The following requirements apply for DQ operating frequencies at or below 1333Mbps for all speed bins for the first column
1600/1867.
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Differential Input Cross Point Voltage
The cross point voltage of differential input signals (CK, ) must meet the requirements in the following table.
The differential input cross point voltage VIX is measured from the actual cross point of true and complement
signals to the mid level that is V
CA.
REF
Vix Definition (Clock)
Notes:
1. The base level of Vix_CK_FR/RF is VREFCA that is LPDDR4 SDRAM internal setting value by VREF Training.
Corss point voltage for differential input signals (Clock)
Data Rate
a
Parameter
Symbol
1600/1867
2133/2400/3200
3733/4267
Min Max
25
Unit Notes
Min
Max
25
Min
Max
Clock Differential input
cross point voltage ratio
Vix_CK_ratio
-
-
25
-
%
1,2
a. The following requirements apply for DQ operating frequencies at or below 1333Mbps for all speed bins for the first column
1600/1867.
Notes:
1. Vix_CK_Ratio is defined by this equation: Vix_CK_Ratio = Vix_CK_FR/|Min(f(t))|
2. Vix_CK_Ratio is defined by this equation: Vix_CK_Ratio = Vix_CK_RF/Max(f(t))
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Differential Input Voltage for DQS
The minimum input voltage need to satisfy both Vindiff_DQS and Vindiff_DQS /2 specification at input
receiver and their measurement period is 1UI(tCK/2). Vindiff_DQS is the peak to peak voltage centered on
0 volts differential and Vindiff_DQS /2 is max and min peak voltage from 0V.
DQS Differential Input Voltage
DQS differential input voltage
Data Rate
a
2133/2400/3200
3733/4267
Min Max
340
Parameter
Symbol
Unit Notes
1600/1867
Min
Max
Min
Max
DQS differential input voltage Vindiff_DQS
360
-
360
-
-
mV
1
a. The following requirements apply for DQ operating frequencies at or below 1333Mbps for all speed bins for the first column
1600/1867.
Notes:
1. The peak voltage of Differential DQS signals is calculated in a following equation.
Vindiff_DQS = (Max Peak Voltage) - (Min Peak Voltage)
Max Peak Voltage = Max(f(t))
Min Peak Voltage = Min(f(t))
f(t) = VDQS - V
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Peak voltage calculation method
The peak voltage of Differential Clock signals are calculated in a following equation.
VIH.DIFF.Peak Voltage = Max(f(t))
VIL.DIFF.Peak Voltage = Min(f(t))
f(t) = VDQS - V
Definition of differential DQS Peak Voltage
Notes:
1. VrefDQ is LPDDR4 SDRAM internal setting value by Vref Training.
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Single-Ended Input Voltage for DQS
The minimum input voltage need to satisfy both Vinse_DQS, Vinse_DQS_High/Low specification at input
receiver.
DQS Single-Ended Input Voltage
Notes:
1. VrefDQ is LPDDR4 SDRAM internal setting value by Vref Training.
DQS Single-Ended Input voltage
Data Rate
a
Parameter
Symbol
1600/1867
2133/2400/3200
3733/4267
Min Max
Unit Notes
Min
Max
Min
Max
DQS Single-Ended
input voltage
DQS Single-Ended input
voltage High from VREFDQ
DQS Single-Ended input
voltage Low from VREFDQ
Vinse_DQS
180
-
-
-
180
-
170
85
-
-
-
mV
mV
mV
Vinse_DQS_High
Vinse_DQS_Low
90
90
90
90
-
-
85
a. The following requirements apply for DQ operating frequencies at or below 1333Mbps for all speed bins for the first column
1600/1867.
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Differential Input Slew Rate Definition for DQS
Input slew rate for differential signals (DQS, ) are defined and measured as shown in the following figure and
table.
Differential Input Slew Rate Definition for DQS,
Notes:
1. Differential signal rising edge from VILdiff_DQS to VIHdiff_DQS must be monotonic slope.
2. Differential signal falling edge from VIHdiff_DQS to VILdiff_DQS must be monotonic slope.
Differential Input Slew Rate Definition for DQS,
Measured
Description
Defined by
From
To
Differential input slew rate for
rising edge(DQS - )
Differential input slew rate for
falling edge(DQS - )
VILdiff_DQS VIHdiff_DQS |VILdiff_DQS - VIHdiff_DQS|/DeltaTRdiff
VIHdiff_DQS VILdiff_DQS |VILdiff_DQS - VIHdiff_DQS|/DeltaTFdiff
Differential Input Level for DQS,
Data Rate
a
Parameter
Symbol
1600/1866
2133/2400/3200
3733/4267
Min Max
Unit Notes
Min
140
-
Max
Min
140
-
Max
-
Differential Input High
Differential Input Low
VIHdiff_DQS
VILdiff_DQS
-
120
-
-
mV
mV
-140
-140
-120
a. The following requirements apply for DQ operating frequencies at or below 1333Mbps for all speed bins for the first column
1600/1867.
Differential Input Slew Rate for DQS,
Data Rate
a
Parameter
Symbol
1600/1866
2133/2400/3200
3733/4267
Min Max
14
Unit Notes
Min
Max
14
Min
Max
Differential Input
Slew Rate for Clock
SRIdiff
2
2
14
2
V/ns
a. The following requirements apply for DQ operating frequencies at or below 1333Mbps for all speed bins for the first column
1600/1867.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Differential Input Cross Point Voltage
The cross point voltage of differential input signals (DQS, ) must meet the requirements in following table.
The differential input cross point voltage VIX is measured from the actual cross point of true and complement
signals to the mid level that is V
DQ.
REF
Vix Definition (DQS)
Notes:
1. The base level of Vix_DQS_FR/RF is VrefDQ that is LPDDR4 SDRAM internal setting value by Vref Training.
Differential Input Slew Rate for DQS,
Data Rate
a
Parameter
Symbol
1600/1866
2133/2400/3200
3733/4267
Min Max
20
Unit Notes
Min
Max
20
Min
Max
DQS Differential input
cross point voltage ratio
Vix_DQS_ratio
-
-
20
-
%
1,2
a. The following requirements apply for DQ operating frequencies at or below 1333Mbps for all speed bins for the first column
1600/1867.
Notes:
1. Vix_DQS_Ratio is defined by this equation: Vix_DQS_Ratio = Vix_DQS_FR/|Min(f(t))|
2. Vix_DQS_Ratio is defined by this equation: Vix_DQS_Ratio = Vix_DQS_RF/Max(f(t))
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
LPDDR4 Input Level for ODT(ca) input
Symbol
ODT Input High Level
ODT Input Low Level
Min
Max
+0.2
Unit
V
Notes
VIHODT
VILODT
0.75*V
-0.2
V
DD2
DD2
0.25*V
V
DD2
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Single Ended Output Slew Rate
Single Ended Output Slew Rate Definition
Output Slew Rate (single-ended)
Parameter
Value
Symbol
Unit
1
2
Min
Max
SRQse
-
3.5
0.8
9
V/ns
-
Single-ended Output Slew Rate (VOH = V
/3)
DDQ
Output slew-rate matching Ratio (Rise to Fall)
Description:
SR- Slew Rate
1.2
Q- Query Output (like in DQ, which stands for Data-in, Query-Output)
Se- Single-ended Signals
Notes:
1. Measured with output reference load.
2. The ratio of pull-up to pull-down slew rate is specified for the same temperature and voltage, over the entire temperature and voltage
range. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation.
3. The output slew rate for falling and rising edges is defined and measured between VOL(AC)=0.2*VOH(DC) and VOH(AC)= 0.8*VOH(DC).
4. Slew rates are measured under average SSO conditions, with 50% of DQ signals per data byte switching.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Differential Output Slew Rate
Differential Output Slew Rate Definition
Value
Parameter
Symbol
Unit
V/ns
1
2
Min
Max
SRQdiff
7
18
Differential Output Slew Rate (VOH = V
/3)
DDQ
Description:
SR- Slew Rate
Q- Query Output (like in DQ, which stands for Data-in, Query-Output)
Se- Single-ended Signals
Notes:
1. Measured with output reference load.
2. The output slew rate for falling and rising edges is defined and measured between VOL(AC)=0.2*VOH(DC) and VOH(AC)= 0.8*VOH(DC).
3. Slew rates are measured under average SSO conditions, with 50% of DQ signals per data byte switching.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Overshoot and Undershoot for LVSTL
AC Overshoot/Undershoot Specification
Data Rate
Unit
Parameter
1600
0.3
1866
0.3
3200
3733
4267
Maximum peak amplitude allowed for overshoot area.
Maximum peak amplitude allowed for undershoot area.
Maximum area above VDD.
Max
Max
Max
Max
0.3
0.3
0.3
V
0.3
0.3
0.3
0.3
0.3
V
0.1
0.1
0.1
0.1
0.1
V-ns
V-ns
Maximum area below VSS.
0.1
0.1
0.1
0.1
0.1
Notes:
1. VDD2 stands for VDD for CA[5:0], CK, , , CKE and ODT. VDD stands for VDDQ for DQ, DMI, DQS and .
2. VSS stands for VSS for CA[5:0], CK, , , CKE and ODT. VSS stands for VSSQ for DQ, DMI, DQS and .
3. Maximum peak amplitude values are referenced from actual VDD and VSS values.
4. Maximum area values are referenced from maximum operating VDD and VSS values.
Overshoot and Undershoot Definition
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
LPDDR4 Driver Output Timing Reference load
These 'Timing Reference Loads’ are not intended as a precise representation of any particular system
environment or a depiction of the actual load presented by a production tester. System designers should use IBIS
or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to
their production test conditions, generally one or more coaxial transmission lines terminated at the tester
electronics.
Driver Output Reference Load for Timing and Slew Rate
Notes:
1. All output timing parameter values are reported with respect to this reference load.
This reference load is also used to report slew rate.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
LVSTL (Low Voltage Swing Terminated Logic) IO System
LVSTL I/O cell is comprised of pull-up, pull-down dirver and a terminator. The basic cell is shown in figure below.
LVSTL I/O Cell
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4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
To ensure that the target impedance is achived the LVSTL I/O cell is designed to calibrated as below procedure.
1. First calibrate the pull-down device against a 240 Ohm resister to VDDQ via the ZQ pin.
• Set Strength Control to minimum setting.
• Increase drive strength until comparator detects data bit is less than VDDQ/2.
• NMOS pull-down device is calibrated to 240 Ohms.
pull-down calibration
2. Then calibrate the pull-up device against the calibrated pull-down device.
• Set VOH target and NMOS controller ODT replica via MRS
(VOH can be automatically controlled by ODT MRS).
• Set Strength Control to minimum setting.
• Increase drive strength until comparator detects data bit is grater than VOH target.
• NMOS pull-up device is now calibrated to VOH target.
pull-up calibration
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Input / Output Capacitance
Symbol
Parameter
Min
0.5
0.0
0.5
-0.1
0.7
0.0
Max
0.9
Unit
pF
Input capacitance :
C
CK
CK,
Input capacitance delta :
CK,
0.09
0.9
pF
C
DCK
Input capacitance:
pF
C
I
all other input-only pins
Input capacitance delta:
all other input-only pins
Input/output capacitance :
DQ, DQS, , DMI
0.1
pF
C
DI
1.3
pF
C
IO
Input/output capacitance delta :
DQS,
0.1
pF
C
DDQS
Input/output capacitance delta :
DQ, DMI
-0.1
0.0
0.1
0.5
pF
pF
C
DIO
Input/output capacitance : ZQ
C
ZQ
Notes:
1. This parameter applies to die devices only (does not include package capacitance).
2. This parameter is not subject to production testing. It is verified. The capacitance is measured according to JEP147
(procedure for measuring input capacitance using a vector network analyzer), with VDD1, VDD2, VDDQ, VSS, VSSQ applied
and all other pins floating.
3. Absolute value of CCK - .
4. CI applies to , CKE, and CA[5:0].
5. CDI = CI – 0.5 × (CCK + )
6. DMI loading matches DQ and DQS.
7. Absolute value of CDQS and .
8. CDIO = CIO – 0.5 × (CDQS + ) in byte-lane.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
IDD Specification Parameters and Test Conditions
IDD Measurement Conditions
The following definitions and conditions are used in the IDD measurement tables unless stated otherwise:
• LOW: VIN ≤ VIL(DC)max
• HIGH: VIN ≥ VIH(DC)min
• STABLE: Inputs are stable at a HIGH or LOW level
• SWITCHING: See Tables bellow
Definition of Switching for CA Input Signal
CK edge
CKE
R1
HIGH
LOW
H
R2
R3
R4
R5
R6
R7
R8
HIGH
LOW
H
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
CS
LOW
LOW
LOW
LOW
LOW
LOW
CA0
L
H
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
CA1
H
H
CA2
H
H
L
H
L
H
CA3
H
H
L
H
L
H
CA4
H
H
L
H
L
H
CA5
H
H
H
H
Notes:
1. CS must always be driven HIGH.
2. 50% of CA bus is changing between HIGH and LOW once per clock for the CA bus.
3. The above pattern is used continuously during IDD measurement for IDD values that require switching on the CA bus.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
IDD Measurement Conditions (Continued)
CA pattern for IDD4R for BL=16
Clock Cycle
CKE
CS
Command
CA0
CA1
CA2
CA3
CA4
CA5
Number
N
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
HIGH
LOW
LOW
LOW
LOW
LOW
HIGH
LOW
HIGH
LOW
LOW
LOW
LOW
LOW
Read-1
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
N+1
N+2
CAS-2
H
L
N+3
N+4
DES
DES
L
L
N+5
L
L
N+6
DES
L
L
N+7
DES
L
L
N+8
Read-1
H
H
H
H
L
L
N+9
H
H
H
L
N+10
N+11
N+12
N+13
N+14
N+15
CAS-2
DES
DES
DES
DES
L
L
L
L
L
L
Notes:
1. BA[2:0]=010, CA[9:4]=000000 or 111111, Burst Order CA[3:2]=00 OR 11(Same as LRDDR3 IDD4R Spec)
2. Difference from LPDDR3 Spec : CA pins are kept low with DES CMD to reduce ODT current.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
CA pattern for IDD4W for BL=16
Clock Cycle
CKE
CS
Command
CA0
CA1
CA2
CA3
CA4
CA5
Number
N
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
HIGH
LOW
LOW
LOW
LOW
LOW
HIGH
LOW
HIGH
LOW
LOW
LOW
LOW
LOW
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
L
L
L
L
L
L
H
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
Write-1
N+1
N+2
H
L
CAS-2
N+3
N+4
DES
DES
DES
DES
L
L
N+5
L
L
N+6
L
L
N+7
L
L
N+8
L
L
Write-1
CAS-2
N+9
H
H
L
H
H
H
L
N+10
N+11
N+12
N+13
N+14
N+15
DES
DES
DES
DES
L
L
L
L
L
L
L
Notes:
1. BA[2:0]=010, CA[9:4]=000000 or 111111 (Same as LRDDR3 IDD4W Spec)
2. Difference from LPDDR3 Spec :
No burst ordering
CA pins are kept low with DES CMD to reduce ODT current.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Data pattern for IDD4W (DBI off) for BL=16
DBI OFF Case
DQ[7]
DQ[6]
DQ[5]
DQ[4]
DQ[3]
DQ[2]
DQ[1]
DQ[0]
DBI
0
No. of 1’s
BL0
BL1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
8
4
0
4
2
4
6
4
8
4
0
4
2
4
6
4
0
BL2
0
BL3
0
BL4
0
BL5
0
BL6
0
BL7
0
BL8
0
BL9
0
BL10
BL11
BL12
BL13
BL14
BL15
0
0
0
0
0
0
BL16
BL17
BL18
BL19
BL20
BL21
BL22
BL23
BL24
BL25
BL26
BL27
BL28
BL29
BL30
BL31
No. of 1’s
Notes:
1
1
0
0
0
0
1
1
0
0
1
1
1
1
0
0
16
1
1
0
0
0
0
1
1
0
0
1
1
1
1
0
0
16
1
1
0
0
0
0
1
1
0
0
1
1
1
1
0
0
16
1
1
0
0
0
0
1
1
0
0
1
1
1
1
0
0
16
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
16
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
16
0
0
1
1
0
1
1
0
1
1
0
0
1
0
0
1
16
0
0
1
1
0
1
1
0
1
1
0
0
1
0
0
1
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
4
2
4
0
4
8
4
2
4
6
4
8
4
0
4
1. Simplified pattern compared with last showing.
Same data pattern was applied to DQ[4], DQ[5], DQ[6], DQ[7] for reducing complexity for IDD4W/R pattern programming.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Data pattern for IDD4R (DBI off) for BL=16
DBI OFF Case
DQ[7]
DQ[6]
DQ[5]
DQ[4]
DQ[3]
DQ[2]
DQ[1]
DQ[0]
DBI
0
No. of 1’s
BL0
BL1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
8
4
0
4
2
4
6
4
8
4
0
4
2
4
6
4
0
BL2
0
BL3
0
BL4
0
BL5
0
BL6
0
BL7
0
BL8
0
BL9
0
BL10
BL11
BL12
BL13
BL14
BL15
0
0
0
0
0
0
BL16
BL17
BL18
BL19
BL20
BL21
BL22
BL23
BL24
BL25
BL26
BL27
BL28
BL29
BL30
BL31
No. of 1’s
Notes:
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
16
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
16
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
16
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
16
1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
16
1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
16
1
0
0
1
0
0
1
1
0
1
1
0
1
1
0
0
16
1
0
0
1
0
0
1
1
0
1
1
0
1
1
0
0
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
4
0
4
6
4
2
4
0
4
8
4
2
4
6
4
1. Same data pattern was applied to DQ[4], DQ[5], DQ[6], DQ[7] for reducing complexity for IDD4W/R pattern programming.
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Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Data pattern for IDD4W (DBI on) for BL=16
DBI ON Case
DQ[7]
DQ[6]
DQ[5]
DQ[4]
DQ[3]
DQ[2]
DQ[1]
DQ[0]
DBI
1
No. of 1’s
BL0
BL1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
4
0
4
2
4
3
4
1
4
0
4
2
4
3
4
0
BL2
0
BL3
0
BL4
0
BL5
0
BL6
1
BL7
0
BL8
1
BL9
0
BL10
BL11
BL12
BL13
BL14
BL15
0
0
0
0
1
0
BL16
BL17
BL18
BL19
BL20
BL21
BL22
BL23
BL24
BL25
BL26
BL27
BL28
BL29
BL30
BL31
No. of 1’s
0
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
8
0
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
8
0
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
8
0
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
8
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
1
8
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
1
8
1
0
1
1
0
1
0
0
1
1
1
0
0
0
0
1
16
1
0
1
1
0
1
0
0
1
1
1
0
0
0
0
1
16
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
8
3
4
2
4
0
4
1
4
2
4
3
4
1
4
0
4
DBI enabled burst
289
Version 1.2
Nanya Technology Corp.
09/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Data pattern for IDD4R (DBI on) for BL=16
DBI ON Case
DQ[7]
DQ[6]
DQ[5]
DQ[4]
DQ[3]
DQ[2]
DQ[1]
DQ[0]
DBI
1
No. of 1’s
BL0
BL1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
4
0
4
2
4
3
4
1
4
0
4
2
4
3
4
0
BL2
0
BL3
0
BL4
0
BL5
0
BL6
1
BL7
0
BL8
1
BL9
0
BL10
BL11
BL12
BL13
BL14
BL15
0
0
0
0
1
0
BL16
BL17
BL18
BL19
BL20
BL21
BL22
BL23
BL24
BL25
BL26
BL27
BL28
BL29
BL30
BL31
No. of 1’s
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
8
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
8
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
8
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
8
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
0
8
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
0
16
0
0
0
1
1
0
1
1
0
1
0
0
1
1
1
0
16
0
0
0
1
1
0
1
1
0
1
0
0
1
1
1
0
8
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
1
4
0
4
3
4
2
4
0
4
1
4
2
4
3
4
290
Version 1.2
Nanya Technology Corp.
09/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
IDD Measurement Conditions (Continued)
CA pattern for IDD4R for BL=32
Clock Cycle
CKE
CS
Command
CA0
CA1
CA2
CA3
CA4
CA5
Number
N
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
HIGH
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
HIGH
LOW
HIGH
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Read-1
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
L
L
L
L
L
N+1
N+2
CAS-2
N+3
N+4
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
Read-1
L
N+5
L
N+6
L
N+7
L
N+8
L
N+9
L
N+10
N+11
N+12
N+13
N+14
N+15
N+16
N+17
N+18
N+19
N+20
N+21
N+22
N+23
N+24
N+25
N+26
N+27
N+28
N+29
N+30
N+31
L
L
L
L
L
L
H
H
H
H
L
CAS-2
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
L
L
L
L
L
L
L
L
L
L
L
Notes:
1. BA[2:0]=010, CA[9:4]=000000 or 111111, Burst Order CA[4:2]=000 OR 111
291
Version 1.2
Nanya Technology Corp.
09/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
CA pattern for IDD4W for BL=32
Clock Cycle
CKE
CS
Command
CA0
CA1
CA2
CA3
CA4
CA5
Number
N
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
HIGH
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
HIGH
LOW
HIGH
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Write-1
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
L
L
L
L
L
N+1
N+2
CAS-2
N+3
N+4
DES
DES
N+5
N+6
DES
N+7
DES
N+8
DES
N+9
DES
N+10
N+11
N+12
N+13
N+14
N+15
N+16
N+17
N+18
N+19
N+20
N+21
N+22
N+23
N+24
N+25
N+26
N+27
N+28
N+29
N+30
N+31
DES
DES
DES
DES
DES
DES
Write-1
CAS-2
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
Notes:
1. BA[2:0]=010, CA[9:4]=000000 or 111111
292
Version 1.2
Nanya Technology Corp.
09/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Data pattern for IDD4W (DBI off) for BL=32
DBI OFF Case
DQ[7]
DQ[6]
DQ[5]
DQ[4]
DQ[3]
DQ[2]
DQ[1]
DQ[0]
DBI
0
No. of 1’s
BL0
BL1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
8
4
0
4
2
4
6
4
8
4
0
4
2
4
6
4
0
BL2
0
BL3
0
BL4
0
BL5
0
BL6
0
BL7
0
BL8
0
BL9
0
BL10
BL11
BL12
BL13
BL14
BL15
0
0
0
0
0
0
BL16
BL17
BL18
BL19
BL20
BL21
BL22
BL23
BL24
BL25
BL26
BL27
BL28
BL29
BL30
BL31
1
1
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
0
0
1
1
0
1
1
0
1
1
0
0
1
0
0
1
0
0
1
1
0
1
1
0
1
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
4
2
4
0
4
8
4
2
4
6
4
8
4
0
4
293
Version 1.2
Nanya Technology Corp.
09/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Data pattern for IDD4W (DBI off) for BL=32 (Cont’d)
DBI OFF Case
DQ[7]
DQ[6]
DQ[5]
DQ[4]
DQ[3]
DQ[2]
DQ[1]
DQ[0]
DBI
0
No. of 1’s
BL32
BL33
BL34
BL35
BL36
BL37
BL38
BL39
BL40
BL41
BL42
BL43
BL44
BL45
BL46
BL47
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
8
4
0
4
2
4
6
4
8
4
0
4
2
4
6
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BL48
BL49
BL50
BL51
BL52
BL53
BL54
BL55
BL56
BL57
BL58
BL59
BL60
BL61
BL62
BL63
No. of 1’s
Notes:
1
1
0
0
0
0
1
1
0
0
1
1
1
1
0
0
32
1
1
0
0
0
0
1
1
0
0
1
1
1
1
0
0
32
1
1
0
0
0
0
1
1
0
0
1
1
1
1
0
0
32
1
1
0
0
0
0
1
1
0
0
1
1
1
1
0
0
32
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
32
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
32
0
0
1
1
0
1
1
0
1
1
0
0
1
0
0
1
32
0
0
1
1
0
1
1
0
1
1
0
0
1
0
0
1
32
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
4
2
4
0
4
8
4
2
4
6
4
8
4
0
4
1. Simplified pattern compared with last showing.
Same data pattern was applied to DQ[4], DQ[5], DQ[6], DQ[7] for reducing complexity for IDD4W/R pattern programming.
294
Version 1.2
09/2018
Nanya Technology Corp.
All Rights Reserved ©
NTC Proprietary
Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Data pattern for IDD4R (DBI off) for BL=32
DBI OFF Case
DQ[7]
DQ[6]
DQ[5]
DQ[4]
DQ[3]
DQ[2]
DQ[1]
DQ[0]
DBI
0
No. of 1’s
BL0
BL1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
8
4
0
4
2
4
6
4
8
4
0
4
2
4
6
4
0
BL2
0
BL3
0
BL4
0
BL5
0
BL6
0
BL7
0
BL8
0
BL9
0
BL10
BL11
BL12
BL13
BL14
BL15
0
0
0
0
0
0
BL16
BL17
BL18
BL19
BL20
BL21
BL22
BL23
BL24
BL25
BL26
BL27
BL28
BL29
BL30
BL31
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
0
0
1
1
0
1
1
0
1
1
0
0
1
0
0
1
0
0
1
1
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
4
0
4
6
4
2
4
0
4
8
4
2
4
6
4
295
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09/2018
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NTC Proprietary
Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Data pattern for IDD4R (DBI off) for BL=32 (Cont’d)
DBI OFF Case
DQ[7]
DQ[6]
DQ[5]
DQ[4]
DQ[3]
DQ[2]
DQ[1]
DQ[0]
DBI
0
No. of 1’s
BL32
BL33
BL34
BL35
BL36
BL37
BL38
BL39
BL40
BL41
BL42
BL43
BL44
BL45
BL46
BL47
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
8
4
0
4
2
4
6
4
8
4
0
4
2
4
6
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BL48
BL49
BL50
BL51
BL52
BL53
BL54
BL55
BL56
BL57
BL58
BL59
BL60
BL61
BL62
BL63
No. of 1’s
Notes:
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
32
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
32
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
32
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
32
1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
32
1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
32
1
0
0
1
0
0
1
1
0
1
1
0
1
1
0
0
32
1
0
0
1
0
0
1
1
0
1
1
0
1
1
0
0
32
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
4
0
4
6
4
2
4
0
4
8
4
2
4
6
4
1. Same data pattern was applied to DQ[4], DQ[5], DQ[6], DQ[7] for reducing complexity for IDD4W/R pattern programming.
296
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Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Data pattern for IDD4W (DBI on) for BL=32
DBI ON Case
DQ[7]
DQ[6]
DQ[5]
DQ[4]
DQ[3]
DQ[2]
DQ[1]
DQ[0]
DBI
1
No. of 1’s
BL0
BL1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
4
0
4
2
4
3
4
1
4
0
4
2
4
3
4
0
BL2
0
BL3
0
BL4
0
BL5
0
BL6
1
BL7
0
BL8
1
BL9
0
BL10
BL11
BL12
BL13
BL14
BL15
0
0
0
0
1
0
BL16
BL17
BL18
BL19
BL20
BL21
BL22
BL23
BL24
BL25
BL26
BL27
BL28
BL29
BL30
BL31
0
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
1
1
0
1
1
0
1
0
0
1
1
1
0
0
0
0
1
1
0
1
1
0
1
0
0
1
1
1
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
3
4
2
4
0
4
1
4
2
4
3
4
1
4
0
4
297
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09/2018
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NTC Proprietary
Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Data pattern for IDD4W (DBI on) for BL=32 (Cont’d)
DBI ON Case
DQ[7]
DQ[6]
DQ[5]
DQ[4]
DQ[3]
DQ[2]
DQ[1]
DQ[0]
DBI
1
No. of 1’s
BL32
BL33
BL34
BL35
BL36
BL37
BL38
BL39
BL40
BL41
BL42
BL43
BL44
BL45
BL46
BL47
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
4
0
4
2
4
3
4
1
4
0
4
2
4
3
4
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
BL48
BL49
BL50
BL51
BL52
BL53
BL54
BL55
BL56
BL57
BL58
BL59
BL60
BL61
BL62
BL63
No. of 1’s
0
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
16
0
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
16
0
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
16
0
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
16
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
1
16
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
1
16
1
0
1
1
0
1
0
0
1
1
1
0
0
0
0
1
32
1
0
1
1
0
1
0
0
1
1
1
0
0
0
0
1
32
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
16
3
4
2
4
0
4
1
4
2
4
3
4
1
4
0
4
DBI enabled burst
298
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09/2018
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NTC Proprietary
Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Data pattern for IDD4R (DBI on) for BL=32
DBI ON Case
DQ[7]
DQ[6]
DQ[5]
DQ[4]
DQ[3]
DQ[2]
DQ[1]
DQ[0]
DBI
1
No. of 1’s
BL0
BL1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
4
0
4
2
4
3
4
1
4
0
4
2
4
3
4
0
BL2
0
BL3
0
BL4
0
BL5
0
BL6
1
BL7
0
BL8
1
BL9
0
BL10
BL11
BL12
BL13
BL14
BL15
0
0
0
0
1
0
BL16
BL17
BL18
BL19
BL20
BL21
BL22
BL23
BL24
BL25
BL26
BL27
BL28
BL29
BL30
BL31
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
1
1
0
1
1
0
1
0
0
1
1
1
0
0
0
0
1
1
0
1
1
0
1
0
0
1
1
1
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
1
4
0
4
3
4
2
4
0
4
1
4
2
4
3
4
299
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Nanya Technology Corp.
09/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Data pattern for IDD4R (DBI on) for BL=32 (Cont’d)
DBI ON Case
DQ[7]
DQ[6]
DQ[5]
DQ[4]
DQ[3]
DQ[2]
DQ[1]
DQ[0]
DBI
1
No. of 1’s
BL32
BL33
BL34
BL35
BL36
BL37
BL38
BL39
BL40
BL41
BL42
BL43
BL44
BL45
BL46
BL47
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
4
0
4
2
4
3
4
1
4
0
4
2
4
3
4
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
BL48
BL49
BL50
BL51
BL52
BL53
BL54
BL55
BL56
BL57
BL58
BL59
BL60
BL61
BL62
BL63
No. of 1’s
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
16
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
16
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
16
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
16
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
0
16
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
0
16
0
0
0
1
1
0
1
1
0
1
0
0
1
1
1
0
32
0
0
0
1
1
0
1
1
0
1
0
0
1
1
1
0
32
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
16
1
4
0
4
3
4
2
4
0
4
1
4
2
4
3
4
300
Version 1.2
Nanya Technology Corp.
09/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
IDD Specifications
IDD values are for the entire operating voltage range, and all of them are for the entire standard range, with the
exception of IDD6ET which is for the entire elevated temperature range.
LPDDR4 IDD Specification Parameters and Operating Conditions
Parameter/Condition
Symbol
Power Supply
Notes
Operating one bank active-precharge current:
tCK = tCKmin; tRC = tRCmin;
CKE is HIGH;
CS is HIGH between valid commands;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
ODT disabled
IDD0
VDD
1
2
1
2
IDD0
VDD
3
IDD0
VDD
Q
Q
Idle power-down standby current:
tCK = tCKmin;
CKE is LOW;
CS is LOW;
All banks are idle;
IDD2P
IDD2P
VDD
VDD
1
2
1
2
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
ODT disabled
3
3
3
3
IDD2P
VDD
Q
Q
Idle power-down standby current with clock stop:
CK =LOW, =HIGH;
CKE is LOW;
CS is LOW;
All banks are idle;
CA bus inputs are STABLE;
Data bus inputs are STABLE;
ODT disabled
IDD2PS
IDD2PS
VDD
VDD
1
2
1
2
IDD2PS
VDD
Q
1
Q
Idle non power-down standby current:
tCK = tCKmin;
CKE is HIGH;
CS is LOW;
All banks are idle;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
ODT disabled
IDD2N
IDD2N
VDD
VDD
1
2
2
IDD2N
VDD
Q
Q
Idle non power-down standby current with clock stoped:
CK =LOW, =HIGH;
CKE is HIGH;
CS is LOW;
All banks are idle;
CA bus inputs are STABLE;
Data bus inputs are STABLE;
ODT disabled
IDD2NS
IDD2NS
VDD
VDD
1
2
1
2
IDD2NS
VDD
Q
Q
301
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Nanya Technology Corp.
09/2018
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Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Parameter/Condition
Symbol
Power Supply
Notes
Active power-down standby current:
tCK = tCKmin;
CKE is LOW;
IDD3P
IDD3P
VDD
VDD
1
2
1
CS is LOW;
2
One bank is active;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
ODT disabled
3
IDD3P
VDD
Q
Q
Active power-down standby current with clock stop:
CK=LOW, =HIGH;
CKE is LOW;
CS is LOW;
One bank is active;
IDD3PS
IDD3PS
VDD
VDD
1
1
2
2
CA bus inputs are STABLE;
Data bus inputs are STABLE;
ODT disabled
4
4
4
5
IDD3PS
VDD
Q
Q
Active non power-down standby current:
tCK = tCKmin;
CKE is HIGH;
CS is LOW;
One bank is active;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
ODT disabled
IDD3N
IDD3N
VDD
VDD
1
1
2
2
IDD3N
VDD
Q
Q
Active non power-down standby current with clock stoped:
CK=LOW, =HIGH;
CKE is HIGH;
CS is LOW;
One bank is active;
CA bus inputs are STABLE;
Data bus inputs are STABLE;
ODT disabled
IDD3NS
IDD3NS
VDD
VDD
1
1
2
2
IDD3NS
VDD
Q
Q
Operating burst read current:
tCK = tCKmin;
CS is LOW between valid commands;
One bank is active;
BL = 16 or 32; RL = RL(min);
CA bus inputs are SWITCHING;
50% data change each burst transfer
ODT disabled
VDD1
VDD2
IDD4R
1
IDD4R
2
IDD4R
VDD
Q
Q
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4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Parameter/Condition
Symbol
Power Supply
Notes
Operating burst write current:
tCK = tCKmin;
CS is LOW between valid commands;
One bank is active;
BL = 16 or 32; WL = WL(min);
CA bus inputs are SWITCHING;
50% data change each burst transfer;
ODT disabled
VDD1
IDD4W
IDD4W
1
2
VDD
2
4
IDD4W
VDD
Q
Q
All Bank Refresh Burst current:
tCK = tCKmin;
CKE is HIGH between valid commands;
tRC = tRFCabmin;
IDD5
IDD5
VDD
VDD
1
1
2
2
Burst refresh;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
ODT disabled
4
4
4
IDD5
VDD
Q
Q
All Bank Refresh Average current:
tCK = tCKmin;
CKE is HIGH between valid commands;
tRC = tREFI;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
ODT disabled
IDD5AB
IDD5AB
VDD
VDD
1
1
2
2
IDD5AB
VDD
Q
Q
Per Bank Refresh Average current:
tCK = tCKmin;
CKE is HIGH between valid commands;
tRC = tREFI/8;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
ODT disabled
IDD5PB
IDD5PB
VDD
VDD
1
1
2
2
IDD5PB
VDD
Q
Q
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8Gb: NT6AN256T32AV
IDD Specifications (Continued)
Parameter/Condition
Symbol
Power Supply
Notes
Self refresh current (Standard Temperature Range):
CK=LOW, =HIGH;
6,7,8.10
IDD6
IDD6
VDD
VDD
1
1
CKE is LOW;
6,7,8.10
4,6,7,8.10
7,8,11
CA bus inputs are STABLE;
Data bus inputs are STABLE;
Maximum 1x Self-Refresh Rate;
ODT disabled
2
2
IDD6
VDD
Q
Q
Self refresh current (Extended Temperature Range):
CK=LOW, =HIGH;
IDD6
IDD6
IDD6
VDD
VDD
ET1
ET2
ETQ
1
CKE is LOW;
7,8,11
CA bus inputs are STABLE;
Data bus inputs are STABLE;
Maximum 1x Self-Refresh Rate;
ODT disabled
2
4,7,8,11
VDD
Q
Notes:
1. Published IDD values are the maximum of the distribution of the arithmetic mean and are measured at 85℃.
2. ODT disabled: MR11[2:0] = 000B.
3. IDD current specifications are tested after the device is properly initialized.
4. Measured currents are the summation of VDDQ and VDD2.
5. Guaranteed by design with output load of 5pf and RON = 40Ohm.
6. The 1x self refresh rate is the rate at which the device is refreshed internally during self refresh, before going into the extended
temperature range.
7. This is the general definition that applies to full-array SELF REFRESH.
8. Supplier datasheets may contain additional Self Refresh IDD values for temperature subranges within the Standard or elevated
Temperature Range.
9. For all IDD measurements, VIHCKE = 0.8 × VDD2, VILCKE = 0.2 × VDD2
10. IDD6 85°C is guaranteed, IDD6 45°C is typical of the distribution of the arithmetic mean.
11. IDD6ET is typical value, is sampled only, and is not tested
12. Dual Channel devices are specified in dual channel operation (both channels operating together).
13. IDD will be derated when above 85°C .
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4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Reserved for IDD Specifications
IDD Specifications and Measurement Conditions
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4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Reserved for IDD Specifications
IDD Specifications and Measurement Conditions
IDD6 Partial Array Self-refresh current;
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8Gb: NT6AN256T32AV
Electrical Characteristics and Recommended AC Timing
Clock Specification
The jitter specified is a random jitter meeting a Gaussian distribution. Input clocks violating the min/max values may result in
malfunction of the LPDDR4 device.
Definitions and Calculations
Symbol
Description
Calculation
Notes
tCK(avg) is calculated as the average clock period across
any consecutive 200 cycle window, where each clock
period is calculated from rising edge to rising edge.
Unit ‘tCK(avg)’ represents the actual clock average
tCK(avg) of the input clock under operation. Unit ‘nCK’
represents one clock cycle of the input clock, counting the
actual clock edges.
tCK(avg) and nCK
tCK(avg) may change by up to +/-1% within a 100 clock
cycle window, provided that all jitter and timingspecs are
met.
tCK(abs) is defined as the absolute clock period, as
measured from one rising edge to the next consecutive
rising edge.
tCK(abs)
tCK(abs) is not subject to production test.
tCH(avg) is defined as the average high pulse width, as
calculated across any consecutive 200 high pulses.
tCH(avg)
tCL(avg) is defined as the average low pulse width, as
calculated across any consecutive 200 low pulses.
tCL(avg)
tCH(abs) is the absolute instantaneous clock high pulse
width, as measured from one rising edge to the following
falling edge.
tCH(abs)
tCH(abs) is not subject to production test.
tCL(abs) is the absolute instantaneous clock low pulse
width, as measured from one falling edge to the following
rising edge.
tCL(abs)
tJIT(per)
tCL(abs) is not subject to production test.
tJIT(per) is the single period jitter defined as the largest
deviation of any signal tCK from tCK(avg).
tJIT(per) is not subject to production test.
tJIT(per),act
tJIT(per),act is the actual clock jitter for a given system.
tJIT(per),allowed
tJIT(per),allowed is the specified allowed clock period jitter.
tJIT(cc) is defined as the absolute difference in clock period
between two consecutive clock cycles.
tJIT(cc)
tJIT(cc) defines the cycle to cycle jitter.
tJIT(cc) is not subject to production test.
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4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Clock AC Timings
(Data rate 4267, 3733, 3200, 2400, 1600 Specifications and conditions)
Min/
Max
Parameter
Clock Timing
Symbol
1600
2400
3200
3733
4267
Unit
1.25
1.25
0.46
0.54
0.46
0.54
0.833
1.25
0.46
0.54
0.46
0.54
0.625
1.25
0.46
0.54
0.46
0.54
0.535
1.25
0.46
0.54
0.46
0.54
0.468
1.25
0.46
0.54
0.46
0.54
ns
Min
Max
Min
Max
Min
Max
Min
Min
Max
Min
Max
Min
Average Clock Period
tCK(avg)1
tCH(avg)
ns
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
ps
Average high pulse width
Average low pulse width
Absolute Clock Period
tCL(avg)
tCK(abs)
tCH(abs)
tCK(avg)min + tCK(avg)min + tCK(avg)min + tCK(avg)min + tCK(avg)min +
tJIT(per)min tJIT(per)min tJIT(per)min tJIT(per)min tJIT(per)min
0.43
0.57
0.43
0.57
-70
0.43
0.57
0.43
0.57
-50
0.43
0.57
0.43
0.57
-40
0.43
0.57
0.43
0.57
-36
0.43
0.57
0.43
0.57
-
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
ps
Absolute clock HIGH
pulse width
Absolute clock LOW
pulse width
tCL(abs)
Clock period jitter
tJIT(per)
tJIT(cc)
70
-
50
-
40
-
36
-
TBD
-
ps
ps
ps
Max
Min
Max
Maximum Clock Jitter
between consecutive
cycles
140
100
80
72
TBD
NOTE1 Clock Frequency herewith is a reference base on JEDEC's. Precise tCK setting needs to follow where defined on speed compatible
table in section “Operating frequency”, exceptional setting please confirm with NTC.
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LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Temperature Derating for AC timing
Data Rate
Unit
Min/
Max
Parameter
Symbol
533/1066/1600/2133/2667/3200/3733/4267
DQS output access time from CK/ (derated)
RAS-to-CAS delay (derated)
tDQSCK
tRCD
tRC
Max
Min
Min
Min
Min
Min
3600
ps
ns
ns
ns
ns
ns
tRCD + 1.875
tRC + 3.75
ACTIVATE-to- ACTIVATE command period (derated)
Row active time (derated)
tRAS
tRP
tRAS + 1.875
tRP + 1.875
tRRD + 1.875
Row precharge time (derated)
Active bank A to active bank B (derated)
tRRD
NOTE1 Timing derating applies for operation at 85°C to 105°C.
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4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
CA Rx voltage and timing
The command and address (CA) including CS input receiver compliance mask for voltage and timing is shown in
the figure below. All CA, CS signals apply the same compliance mask and operate in single data rate mode.
The CA input receiver mask for voltage and timing is shown in the figure below is applied across all CA pins. The
receiver mask (Rx Mask) defines the area that the input signal must not encroach in order for the DRAM input
receiver to be expected to be able to successfully capture a valid input signal; it is not the valid data-eye.
CA Receiver (Rx) mask
Across pin VREFCA voltage variation
Vcent_CA(pin mid) is defined as the midpoint between the largest Vcent_CA voltage level and the smallest
Vcent_CA voltage level across all CA and CS pins for a given DRAM component. This clarifies that any DRAM
component level variation must be accounted for within the DRAM CA Rx mask. The component level VREF will be
set by the system to account for Ron and ODT settings.
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4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
CA Timings at the DRAM Pins
All of the timing terms in figure below are measured from the CK/ to the center(midpoint) of the TcIVW window
taken at the VcIVW_total voltage levels centered around Vcent_CA(pin mid).
CA TcIPW and SRIN_cIVW definition (for each input pulse)
Notes:
1. SRIN_cIVW=VcIVW_Total/(tr or tf), signal must be monotonic within tr and tf range.
CA VIHL_AC definition (for each input pulse)
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8Gb: NT6AN256T32AV
DRAM CMD/ADR, CS
Speed Grade
Min/
Max
Symbol
Parameter
Unit
Note
a
1600/1867 3200 3733 4267
1333
175
VcIVW
TcIVW
Rx Mask voltage -p-p
Rx timing window
Max
Max
175
0.3
155
0.3
150
0.3
145
0.3
mV
1,2,3
0.3
tck(avg)min 1,2,3
CA AC input pulse amplitude
pk-pk
VIHL_AC
TcIPW
Min
210
210
190
180
180
mV
4,7
5
CA input pulse width
Min
Min
Max
0.55
1
0.55
1
0.6
1
0.6
1
0.6
1
tck(avg)min
SRIN_cIVW Input Slew Rate over VcIVW
V/ns
6
7
7
7
7
7
a. The following Rx voltage and absolute timing requirements apply for DQ operating frequencies at or below 1333 for
all speed bins. For example the TcIVW(ps) = 450ps at or below 1333 operating frequencies.
Notes:
1. CA Rx mask voltage and timing parameters at the pin including voltage and temperature drift.
2. Rx mask voltage VcIVW total(max) must be centered around Vcent_CA(pin mid).
3. Defined over the CA internal VREF range. The Rx mask at the pin must be within the internal VREF CA range irrespective of the
input signal common mode.
4. CA only input pulse signal amplitude into the receiver must meet or exceed VIHL AC at any point over the total UI. No timing
requirement above level. VIHL AC is the peak to peak voltage centered around Vcent_CA(pin mid) such that VIHL_AC/2 min
must be met both above and below Vcent_CA.
5. CA only minimum input pulse width defined at the Vcent_CA(pin mid).
6. Input slew rate over VcIVW Mask centered at Vcent_CA(pin mid).
7. VIHL_AC does not have to be met when no transitions are occurring.
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4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
DRAM Data Timing
Read data timing definitions tQH and tDQSQ across on DQ signals per DQS group
Read data timing tQW valid window defined per DQ signal
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8Gb: NT6AN256T32AV
Read output timings
Speed Grade
Min/
Max
Symbol
Parameter
Unit
Notes
1600/1867
2133/2400
Data Timing
DQS, to DQ Skew total, per group,
per access (DBIDisabled)
DQ output hold time total from DQS,
UI*
UI*
tDQSQ
Max
Min
0.18
0.18
1
1
tQH
min(tQSH, tQSL)
min(tQSH, tQSL)
(DBI-Disabled)
DQ output window time total, per pin
(DBI-Disabled)
UI*
UI*
tQW_total
tQW_dj
Min
0.75
TBD
0.73
TBD
1,4
DQ output window time deterministic,
per pin (DBIDisabled)
Max
1,4,3
DQS, to DQ Skew total,per group,
UI*
tDQSQ_DBI per access
Max
0.18
0.18
1
(DBI-Enabled)
DQ output hold time total from DQS,
min(tQSH_DBI,
tQSL_DBI)
min(tQSH_DBI,
tQSL_DBI)
UI*
UI*
tQH_DBI
Min
1
(DBI-Enabled)
DQ output window time total, per pin
(DBI-Enabled)
tQHW_total_DBI
Max
0.75
0.73
1,4
Data Strobe Timing
DQS, differential output low time
tCL(abs)
-0.05
tCL(abs)
-0.05
tQSL
tQSH
Min
Min
Min
Min
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
4,5
4,6
5,7
5,7
(DBI-Disabled)
DQS, differential output high time
(DBI-Disabled)
tCH(abs)
-0.05
tCH(abs)
-0.05
DQS, differential output low time
(DBI-Enabled)
tCL(abs)
-0.045
tCL(abs)
-0.045
tQSL_DBI
tQSH_DBI
DQS, differential output high time
(DBI-Enabled)
tCH(abs)
-0.045
tCH(abs)
-0.045
*Unit UI = tCK(avg)min/2
Notes:
1. The deterministic component of the total timing. Measurement method tbd.
2. This parameter will be characterized and guaranteed by design.
3. This parameter is function of input clock jitter. These values assume the min tCH(abs) and tCL(abs). When the input clock jitter min
tCH(abs) and tCL(abs) is 0.44 or greater of tck(avg) the min value of tQSL will be tCL(abs)-0.04 and tQSH will be tCH(abs) -0.04.
4. tQSL describes the instantaneous differential output low pulse width on DQS - , as measured from on falling edge to the next
consecutive rising edge.
5. tQSH describes the instantaneous differential output high pulse width on DQS - , as measured from on falling edge to the next
consecutive rising edge.
6. This parameter is function of input clock jitter. These values assume the min tCH(abs) and tCL(abs). When the input clock jitter min
tCH(abs) and tCL(abs) is 0.44 or greater of tck(avg) the min value of tQSL will be tCL(abs)-0.04 and tQSH will be tCH(abs) -0.04.
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8Gb: NT6AN256T32AV
Read output timings (Continued)
Speed Grade
3733
Min/
Max
Symbol
Parameter
Unit
Notes
3200
4267
Data Timing
DQS, to DQ Skew total, per group,
per access (DBIDisabled)
DQ output hold time total from DQS,
UI*
UI*
tDQSQ
Max
Min
0.18
0.18
0.18
1
1
min(tQSH,
tQSL)
min(tQSH,
tQSL)
min(tQSH,
tQSL)
tQH
(DBI-Disabled)
DQ output window time total, per pin
(DBI-Disabled)
UI*
UI*
tQW_total
tQW_dj
Min
0.7
0.7
0.7
1,4
DQ output window time deterministic,
per pin (DBIDisabled)
Max
TBD
TBD
TBD
1,4,3
DQS, to DQ Skew total,per group,
UI*
tDQSQ_DBI per access
Max
0.18
0.18
0.18
1
(DBI-Enabled)
DQ output hold time total from DQS,
min(tQSH_DBI, min(tQSH_DBI, min(tQSH_DBI,
UI*
UI*
tQH_DBI
Min
1
tQSL_DBI)
tQSL_DBI)
tQSL_DBI)
(DBI-Enabled)
DQ output window time total, per pin
(DBI-Enabled)
tQHW_total_DBI
Max
0.7
0.7
0.7
1,4
Data Strobe Timing
DQS, differential output low time
tQSL
tQSH
Min tCL(abs)-0.05 tCL(abs)-0.05 tCL(abs)-0.05 tCK(avg)
Min tCH(abs)-0.05 tCH(abs)-0.05 tCH(abs)-0.05 tCK(avg)
Min tCL(abs)-0.045 tCL(abs)-0.045 tCL(abs)-0.045 tCK(avg)
Min tCH(abs)-0.045 tCH(abs) -0.045 tCH(abs)-0.045 tCK(avg)
4,5
4,6
5,7
5,7
(DBI-Disabled)
DQS, differential output high time
(DBI-Disabled)
DQS, differential output low time
(DBI-Enabled)
tQSL_DBI
tQSH_DBI
DQS, differential output high time
(DBI-Enabled)
*Unit UI = tCK(avg)min/2
Notes:
1. The deterministic component of the total timing. Measurement method tbd.
2. This parameter will be characterized and guaranteed by design.
3. This parameter is function of input clock jitter. These values assume the min tCH(abs) and tCL(abs). When the input clock jitter min
tCH(abs) and tCL(abs) is 0.44 or greater of tck(avg) the min value of tQSL will be tCL(abs)-0.04 and tQSH will be tCH(abs) -0.04.
4. tQSL describes the instantaneous differential output low pulse width on DQS - , as measured from on falling edge to the next
consecutive rising edge.
5. tQSH describes the instantaneous differential output high pulse width on DQS - , as measured from on falling edge to the next
consecutive rising edge.
6. This parameter is function of input clock jitter. These values assume the min tCH(abs) and tCL(abs). When the input clock jitter min
tCH(abs) and tCL(abs) is 0.44 or greater of tck(avg) the min value of tQSL will be tCL(abs)-0.04 and tQSH will be tCH(abs) -0.04.
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8Gb: NT6AN256T32AV
DQ Rx voltage and timing
The DQ input receiver mask for voltage and timing is shown figure below is applied per pin. The "total" mask
(VdIVW_total, TdiVW_total) defines the area the input signal must not encroach in order for the DQ input receiver
to successfully capture an input signal with a BER of lower than TBD1. The mask is a receiver property and it is not
the valid data-eye.
DQ Receiver (Rx) mask
Across pin VREFDQ voltage variation
Vcent_DQ(pin_mid) is defined as the midpoint between the largest Vcent_DQ voltage level and the smallest
Vcent_DQ voltage level across all DQ pins for a given DRAM component. This clarifies that any DRAM component
level variation must be accounted for within the DRAM Rx mask. The component level VREF will be set by the
system to account for Ron and ODT settings.
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8Gb: NT6AN256T32AV
DQ to DQS tDQS2DQ & tDQDQ Timings at the DRAM pins referenced from the internal latch
Notes:
1. tDQS2DQ is measured at the center(midpoint) of the TdiVW window.
2. DQz represents the max tDQS2DQ in this example
3. DQy represents the min tDQS2DQ in this example
All of the timing terms in DQ to DQS are measured from the DQS/ to the center(midpoint) of the TdIVW
window taken at the VdIVW_total voltage levels centered around Vcent_DQ(pin_mid). The timings at the pins are
referenced with respect to all DQ signals center aligned to the DRAM internal latch. The data to data offset is
defined as the difference between the min and max tDQS2DQ for a given component.
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NTC Proprietary
Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
DQ TdIPW and SRIN_dIVW definition (for each input pulse)
Notes:
1. SRIN_dIVW=VdIVW_Total/(tr or tf), signal must be monotonic within tr and tf range.
DQ VIHL_AC definition (for each input pulse)
318
Version 1.2
Nanya Technology Corp.
09/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
DRAM DQs In Receive Mode
Speed Grade
Min/
Max
Symbol
Parameter
Unit
Notes
a
2133/2400
1600/1867
Max
Max
mV
UI*
VdIVW_total Rx Mask voltage -p-p total
140
140
1,2,3,4
1,2,4
Rx timing window total
TdIVW_total
0.22
TBD
0.22
(At VdIVW voltage levels)
Rx timing window 1 bit toggle
TdIVW_1bit
1,2,4
12
UI*
Max
TBD
(At VdIVW voltage levels)
mV
UI*
VIHL_AC
DQ AC input pulse amplitude pk-pk
Input pulse width (At Vcent_DQ)
Min
Min
Min
Max
Max
180
0.45
200
800
30
180
0.45
200
800
30
5,13
6
TdIPW_DQ
ps
tDQS2DQ
tDQDQ
DQ to DQS offset
DQ to DQ offset
7
ps
8
9
ps/C
tDQS2DQ_temp DQ to DQS offset temperature variation Max
0.6
33
0.6
33
tDQS2DQ_Volt DQ to DQS offset voltage variation
Max
Min
ps/50mV
10
1
1
SRIN_dIVW Input Slew Rate over VdIVW_total
tDQS2DQ_rank DQ to DQS offset rank to rank
V/ns
11
Max
7
7
Mas
200
200
ps
14,15,16
2rank
variation
A. The Rx voltage and absolute timing requirements apply for all DQ operating frequencies at or below 1600 for all speed bins.
For example TdIVW_total(ps) = 137.5ps at or below 1600 operating frequencies.
*UI=tCK(avg)min/2
Notes:
1. Data Rx mask voltage and timing parameters are applied per pin and includes the DRAM DQ to DQS voltage AC noise
impact for frequencies >20 MHz and max voltage of 45mv pk-pk from DC-20MHz at a fixed temperature on the
package. The voltage supply noise must comply to the component Min-Max DC operating conditions.
2. The design specification is a BER <TBD. The BER will be characterized and extrapolated if necessary using a dual
dirac method.
3. Rx mask voltage VdIVW total(max) must be centered around Vcent_DQ(pin_mid).
4. Vcent_DQ must be within the adjustment range of the DQ internal Vref..
5. DQ only input pulse amplitude into the receiver must meet or exceed VIHL AC at any point over the total UI. No timing
requirement above level. VIHL AC is the peak to peak voltage centered around Vcent_DQ(pin_mid) such that
VIHL_AC/2 min must be met both above and below Vcent_DQ.
6. DQ only minimum input pulse width defined at the Vcent_DQ(pin_mid). .
7. DQ to DQS offset is within byte from DRAM pin to DRAM internal latch. Includes all DRAM process, voltage and
temperature variation.
8. DQ to DQ offset defined within byte from DRAM pin to DRAM internal latch for a given component.
9. TDQS2DQ max delay variation as a function of temperature.
319
Version 1.2
Nanya Technology Corp.
09/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
10. TDQS2DQ max delay variation as a function of the DC voltage variation for VDDQ and VDD2. It includes the VDDQ and
VDD2 AC noise impact for frequencies > 20MHz and max voltage of 45mv pk-pk from DC-20MHz at a fixed temperature
on the package. For tester measurement VDDQ = VDD2 is assumed.
11. Input slew rate over VdIVW Mask centered at Vcent_DQ(pin_mid).
12. Rx mask defined for a one pin toggling with other DQ signals in a steady state.
13. VIHL_AC does not have to be met when no transitions are occurring.
14. The same voltage and temperature are applied to tDQS2DQ_rank2rank.
15. tDQS2DQ_rank2rank parameter is applied to multi-ranks per byte lane within a package consisting of the same
design dies.
16. tDQS2DQ_rabk2rank support was added to JESD209-4B, some older devices designed to support JESD209-4 and
JESD209-4A may not support this parameter. Refer to vendor datasheet.
320
Version 1.2
Nanya Technology Corp.
09/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
DRAM DQs In Receive Mode (Continued)
Speed Grade
3733
Min/
Max
Symbol
Parameter
Unit
Notes
3200
4267
Max
Max
mV
UI*
VdIVW_total Rx Mask voltage -p-p total
140
130
120
1,2,3,4
1,2,4
Rx timing window total
TdIVW_total
0.25
TBD
0.25
TBD
0.25
TBD
(At VdIVW voltage levels)
Rx timing window 1 bit toggle
TdIVW_1bit
1,2,4
12
UI*
Max
(At VdIVW voltage levels)
mV
UI*
VIHL_AC
DQ AC input pulse amplitude pk-pk
Input pulse width (At Vcent_DQ)
Min
Min
Min
Max
Max
180
0.45
200
800
30
180
0.45
250
700
30
170
0.45
200
800
30
5,13
6
TdIPW_DQ
ps
tDQS2DQ
tDQDQ
DQ to DQS offset
DQ to DQ offset
7
ps
8
9
ps/C
tDQS2DQ_temp DQ to DQS offset temperature variation Max
0.6
33
0.4
25
0.6
33
tDQS2DQ_Volt DQ to DQS offset voltage variation
Max
Min
ps/50mV
10
1
1
1
SRIN_dIVW Input Slew Rate over VdIVW_total
tDQS2DQ_rank DQ to DQS offset rank to rank
V/ns
ps
11
Max
7
7
7
Mas
200
200
200
14,15,16
2rank
variation
*UI=tCK(avg)min/2
Notes:
1. Data Rx mask voltage and timing parameters are applied per pin and includes the DRAM DQ to DQS voltage AC noise
impact for frequencies >20 MHz and max voltage of 45mv pk-pk from DC-20MHz at a fixed temperature on the
package. The voltage supply noise must comply to the component Min-Max DC operating conditions.
2. The design specification is a BER <TBD. The BER will be characterized and extrapolated if necessary using a dual
dirac method.
3. Rx mask voltage VdIVW total(max) must be centered around Vcent_DQ(pin_mid).
4. Vcent_DQ must be within the adjustment range of the DQ internal Vref..
5. DQ only input pulse amplitude into the receiver must meet or exceed VIHL AC at any point over the total UI. No timing
requirement above level. VIHL AC is the peak to peak voltage centered around Vcent_DQ(pin_mid) such that
VIHL_AC/2 min must be met both above and below Vcent_DQ.
6. DQ only minimum input pulse width defined at the Vcent_DQ(pin_mid). .
7. DQ to DQS offset is within byte from DRAM pin to DRAM internal latch. Includes all DRAM process, voltage and
temperature variation.
8. DQ to DQ offset defined within byte from DRAM pin to DRAM internal latch for a given component.
9. TDQS2DQ max delay variation as a function of temperature.
10. TDQS2DQ max delay variation as a function of the DC voltage variation for VDDQ and VDD2. It includes the VDDQ and
VDD2 AC noise impact for frequencies > 20MHz and max voltage of 45mv pk-pk from DC-20MHz at a fixed temperature
321
Version 1.2
Nanya Technology Corp.
09/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
on the package. For tester measurement VDDQ = VDD2 is assumed.
11. Input slew rate over VdIVW Mask centered at Vcent_DQ(pin_mid).
12. Rx mask defined for a one pin toggling with other DQ signals in a steady state.
13. VIHL_AC does not have to be met when no transitions are occurring.
14. The same voltage and temperature are applied to tDQS2DQ_rank2rank.
15. tDQS2DQ_rank2rank parameter is applied to multi-ranks per byte lane within a package consisting of the same
design dies.
16. tDQS2DQ_rabk2rank support was added to JESD209-4B, some older devices designed to support JESD209-4 and
JESD209-4A may not support this parameter. Refer to vendor datasheet.
322
Version 1.2
Nanya Technology Corp.
09/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
Preliminary, Subject to change
LPDDR4 4Gb/8Gb(DDP) SDRAM
4Gb: NT6AN256M16AV
8Gb: NT6AN256T32AV
Revision History
Version Page
Modified
Description
Preliminary Release
Released
05/2018
1.0
1.1
-
-
-
-
P1-8
P1
Add part number: NT6AN256M16AV-J1/J2/J3
Add temperature range of tREFI
07/2018
P3
Operating Frequency
Modify
Modify
1.2
09/2018
Operating Temperature
Range
P263
323
Version 1.2
Nanya Technology Corp.
09/2018
All Rights Reserved ©
http://www.nanya.com/
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