NT6CL256M16CM-H1 [NANYA]
Commercial Mobile LPDDR3 4Gb / 8Gb(DDP) SDRAM;
| 型号： | NT6CL256M16CM-H1 |
| 厂家： | 
Nanya Technology Corporation. |
| 描述： | Commercial Mobile LPDDR3 4Gb / 8Gb(DDP) SDRAM 动态存储器 双倍数据速率 光电二极管 |
| 文件： | 总166页 (文件大小：6046K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Commercial Mobile LPDDR3 4Gb / 8Gb(DDP) SDRAM
Features
Data Integrity
Basis LPDDR3 Compliant
- Low Power Consumption
- DRAM built-in Temperature Sensor for
Temperature Compensated Self Refresh (TCSR)
- 8n Prefetch Architecture and BL8 only
- Auto Refresh and Self Refresh Modes
Power Saving Modes
Signal Integrity
- Configurable DS for system compatibility
- Configurable On-Die Termination1
- Deep Power Down Mode (DPD)
- Partial Array Self Refresh (PASR)
- Clock Stop capability during idle period
HSUL12 interface and Power Supply
- VDD1= 1.70 to 1.95V
- ZQ Calibration for DS/ODT impedance accuracy via
external ZQ pad (240Ω± 1%)
Training for Signals’ Synchronization
- DQ Calibration offering specific DQ output patterns
- CA Training
- Write Leveling via MR settings 2
- VDD2/VDDQ/VDDCA = 1.14 to 1.3V
Options
Temperature Range (Tc)
Speed Grade (DataRate/Read Latency)
- Commercial Grade = - 25℃ to + 85℃
- 1866 Mbps / RL=14
Programmable functions
RL/WL Select (Set A / Set B)4
nWRE ( nWR≦9 / nWR>9)
PASR (bank/segment)
RON (Typical:34.3/40/48/60/80)
RON (PD34.3_PU40 / PD40_PU48 / PD34.3_PU48)
RTT (120/240)
Packages / Density information
Lead-free RoHS compliance and Halogen-free
Density, Signals and Addressing
4Gb (SDP)
X16 X32
8Gb (DDP)
X16 X32
Width x Length x Height
(mm)
Ball pitch
(mm)
FBGA Package
Items
CK//CKE
DQ
1:0]
168b PoP
178b
12.00 x 12.00 x 0.80
10.50 x 11.50 x 0.80
12.00 x 12.00 x 0.80
14.00 x 14.00 x 0.80
0.50
CK / / CKE
CK / / CKE[1:0]
[15:0]
[31:0]
[15:0]
[31:0]
0.65/0.80
Mixed
DQS/DM
CA
[1:0] / [1:0] [3:0] / [3:0] [1:0] / [1:0]
[3:0] / [3:0]
CA[9:0]
BA[2:0]
R[13:0]
Bank Addr.
Row Addr.3
Column Addr.3
tREFI
216b PoP
256b PoP
0.40
0.40
C[10:0]
C[9:0]
C[10:0]
C[9:0]
3.9μs (Tc≦ 85oC)
NOTE 1 Depending on ballout, ODT pin may be NOT supported so ODT die pad is connected to Vss inside the package.
NOTE 2 Write Leveling DQ feedback on all DQs
NOTE 3 Row and Column Addresses values on the CA bus that are not used are “don’t care.”
NOTE 4 For this operation, please confirm notices with NTC.
1
Version 1.4
02/2018
Nanya Technology Corp.
All Rights Reserved ©
NTC has the rights to change any specifications or product herein without notification.
NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Ordering Information
Speed
Density Organization
Part Number
Package
TCK
(ns)
Data Rate
(Mb/s/pin)
RL
Commercial Grade
NT6CL128M32CQ-H1
NT6CL128M32CM-H1
NT6CL256M16CM-H1
NT6CL256T32CQ-H1
NT6CL256T32CM-H1
NT6CL128T64CR-H1
NT6CL128T64C4-H1
168-Ball
178-Ball
1.07
1.07
1.07
1.07
1.07
1.07
1.07
1866
1866
1866
1866
1866
1866
1866
14
14
14
14
14
14
14
128M x 32
4Gb
(SDP)
256M x 16
168-Ball
178-Ball
216-Ball
256-Ball
256M x 32
8Gb
(DDP)
128M x 64
( 2-CH )
2
Version 1.4
Nanya Technology Corp.
02/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
NANYA Mobile LPDDR3 Part Number Naming Guide
L
128M32
NT
6C
C
Q
H1
Grade
NANYA
Technology
N/A =Commercial Grade
Speed
Product Family
H1 = 1866Mbps @ RL=14
6C = LPDDR3 SDRAM
Package Code
Interface & Power (VDD1 , VDD2 , VDDQ , VDDCA
L = HSUL_12 (1.8V, 1.2V, 1.2V, 1.2V)
)
ROHS+Halogen-Free
Q = 168-Ball PoP FBGA
M = 178-Ball FBGA
R = 216-Ball 2-CH PoP-FBGA
4 = 256-Ball 2-CH PoP-FBGA
Organization (Depth, Width)
4Gb = 128M32, 256M16
8Gb = 256T32, 512T16, 128T64
Device Version
C = 3rd version
NOTE: M=Mono; T=DDP
Operating frequency
The backward compatibility of each speed grade is listed in a table below. If an application operates at specific frequency
which is not defined herein but within the highest and the lowest supporting grade, then the comparative loose
specifications to DRAM must be adopted from the neighboring defined speed bins. Please confirm notices with NTC for
operating frequency slower than defined speed bins.
Frequency[Mbps]
RL[nCK]
1866
14
1600
12
1333
10
VDDQ[V]
1.2
1.2
1.2
NT6CL128M32CQ-H1
NT6CL128M32CM-H1
NT6CL256M16CM-H1
NT6CL256T32CQ-H1
NT6CL256T32CM-H1
NT6CL128T64CR-H1
NT6CL128T64C4-H1
1866
1600
1333
Notes:
Any speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production
Tests but has been verified.
3
Version 1.4
02/2018
Nanya Technology Corp.
All Rights Reserved ©
NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Functional Descriptions
4Gb LPDDR3-SDRAM has 4,294,967,296 bits and 8Gb LPDDR3-SDRAM has 8,589,934,592 bits. These devices
are high-speed synchronous DRAM devices internally configured as an 8-bank memory and use a double data rate
architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA
bus contains command, address, and bank information. Each command uses one clock cycle, during which
command information is transferred on both the positive and negative edge of the clock.
These devices also use a double data rate architecture on the DQ pins to achieve high speed operation. The
double data rate architecture is essentially an 8n prefetch architecture with an interface designed to transfer two
data bits per DQ every clock cycle at the I/O pins. A single read or write access for the device effectively
consists of a single 8n-bit wide, one clock cycle data transfer at the internal DRAM core and eight corresponding
n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
Read and write accesses are burst oriented; accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence. Accesses begin with the registration of an
Activate command, which is then followed by a Read or Write command. The address and BA bits registered
coincident with the Activate command are used to select the row and the bank to be accessed. The address bits
registered coincident with the Read or Write command are used to select the bank and the starting column
location for the burst access.
Prior to normal operation, the device must be initialized. The following section provides detailed information
covering device initialization, register definition, command description and device operation.
4
Version 1.4
Nanya Technology Corp.
02/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Functional Block Diagram
5
Version 1.4
Nanya Technology Corp.
02/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Power, Ground, Signals of Single Die, Single Channel Package
Part Number: NT6CL128M32CQ-XXX
Available: 168b
VDD1 VDD2 VDDQ VDDCA
Vss
VREFCA
VREFDQ
ZQ
RZQ
4Gb
CKE
CK
Device
(128Mb x 32)
Die 0
DM[3:0]
CA[9:0]
DQ[31:0]
DQS[3:0]
[3:0]
NOTE 1 ODT pin is NOT supported. ODT die pad is connected to VSS inside the package.
6
Version 1.4
Nanya Technology Corp.
02/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Part Number: NT6CL128M32CM-XXX
Available: 178b
VDD1 VDD2 VDDQ VDDCA
Vss
VREFCA
VREFDQ
ZQ
RZQ
4Gb
CKE
CK
Device
(128Mb x 32)
Die 0
DM[3:0]
CA[9:0]
ODT
DQ[31:0]
DQS[3:0]
[3:0]
Part Number: NT6CL256M16CM-XXX
Available: 178b
VDD1 VDD2 VDDQ VDDCA
Vss
VREFCA
VREFDQ
ZQ
RZQ
4Gb
CKE
CK
Device
(256Mb x 16)
Die 0
DM[1:0]
CA[9:0]
ODT
DQ[15:0]
DQS[1:0]
[1:0]
7
Version 1.4
02/2018
Nanya Technology Corp.
All Rights Reserved ©
NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Power, Ground, Signals of Dual Die, Single Channel Package
Part Number: NT6CL256T32CQ-XXX
Available: 168b
VDD1 VDD2 VDDQ VDDCA
Vss
VREFCA
VREFDQ
CKE1
ZQ2
RZQ
CKE0
CK
4Gb
4Gb
Device
(128Mb x 32)
Die 1
Device
(128Mb x 32)
Die 0
DM[3:0]
CA[9:0]
DQ[31:0]
DQS[3:0]
[3:0]
NOTE 1 ODT pins are NOT supported. ODT die pad is connected to VSS inside the package.
NOTE 2 ZQ is connected to both dies.
8
Version 1.4
Nanya Technology Corp.
02/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Part Number: NT6CL256T32CM-XXX
Available: 178b
Vss
VDD1 VDD2 VDDQ VDDCA
VREFCA
VREFDQ
CKE1
ZQ2
RZQ
CKE0
CK
4Gb
4Gb
Device
(128Mb x 32)
Die 1
Device
(128Mb x 32)
Die 0
DM[3:0]
CA[9:0]
DQ[31:0]
DQS[3:0]
[3:0]
ODT1
NOTE 1 ODT will be connected to rank0 (die0). The ODT input to rank1 (die1) will be connected to VSS in the package.
NOTE 2 ZQ is connected to both dies.
9
Version 1.4
02/2018
Nanya Technology Corp.
All Rights Reserved ©
NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Power, Ground, Signals of Dual Die, Dual Channel Package
Part Number: NT6CL128T64CR-XXX
Available: 216b (2-channel)
VDD1 VDD2 VDDQ VDDCA
Vss
VREFCA (b)
VREFDQ(b)
ZQ(b)
RZQ
4Gb
CKE(b)
CK(b)
Device
DM[3:0] (b)
CA[9:0] (b)
(128Mb x 32)
Channel B
DQ[31:0] (b)
DQS[3:0] (b)
[3:0] (b)
ZQ(a)
RZQ
4Gb
CKE(a)
CK(a)
Device
(128Mb x 32)
Channel A
DM[3:0] (a)
CA[9:0] (a)
DQ[31:0] (a)
DQS[3:0] (a)
[3:0] (a)
VREFCA (a)
VREFDQ(a)
10
Version 1.4
Nanya Technology Corp.
02/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Power, Ground, Signals of Dual Die, Dual Channel Package
Part Number: NT6CL128T64C4-XXX
Available: 256b (2-channel)
VDD1 VDD2 VDDQ VDDCA
Vss
VREFCA (b)
VREFDQ(b)
ZQ(b)
RZQ
4Gb
CKE(b)
CK(b)
Device
DM[3:0] (b)
CA[9:0] (b)
(128Mb x 32)
Channel B
DQ[31:0] (b)
DQS[3:0] (b)
[3:0] (b)
ODT (b)
ZQ(a)
RZQ
4Gb
CKE(a)
CK(a)
Device
(128Mb x 32)
Channel A
DM[3:0] (a)
CA[9:0] (a)
DQ[31:0] (a)
DQS[3:0] (a)
[3:0] (a)
ODT (a)
VREFCA (a)
VREFDQ(a)
11
Version 1.4
Nanya Technology Corp.
02/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
LPDDR3 12x12 PoP-FBGA 1-channel x 32 ballout
(168-ball SDP, 12.00mm x 12.00mm, 0.50mm pitch)
Part Number: NT6CL128M32CQ-XXX
< TOP View>
See the balls through the package
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
A
DNU
DNU
VSS
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
ZQ
DNU
DNU
VDD2
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
VSS
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU VDD1 VSS DQ30 DQ29 VSS DQ26 DQ25 VSS
VDD1 VSS
DNU
DNU
DNU
DNU
VSS
DQ14
DQ13
VSS
DQ10
DQ9
VSS
DM1
VSS
DM0
VSS
DQS0
DQ7
VSS
DQ4
DQ3
VSS
DQ0
DNU
DNU
23
A
B
B
VDD1 DNU
VSS VDD2 DQ31 VDDQ DQ28 DQ27 VDDQ DQ24 DQS3 VDDQ DM3 VDD2
C
D
E
DQ15
VDDQ
DQ12
DQ11
VDDQ
DQ8
C
D
E
F
F
G
H
J
G
H
J
DQS1
VDDQ
VDD2
VrefDQ
VDD1
VDDQ
DQ6
K
K
L
L
M
N
P
M
N
P
VDD1
VrefCA
VDD2
CA8
R
T
VSS
CA9
CA7
VSS
CA5
R
T
U
V
VDDCA
CA6
DQ5
U
V
VDDQ
DQ2
W
Y
VDDCA
CK
W
Y
DQ1
AA
AB
AC
VSS
DNU
DNU
1
VDD2
DNU
DNU
2
VDDQ
DNU
AA
AB
AC
CKE
3
NC
NC
4
VDD1 CA1
VSS
CA3
CA4 VDD2 VSS DQ16 VDDQ DQ18 DQ20 VDDQ DQ22 DQS2 VDDQ DM2 VDD2
VSS
5
CA0
6
CA2 VDDCA DNU
DNU
10
NC
11
VSS DQ17 DQ19 VSS DQ21 DQ23 VSS
VDD1 VSS
DNU
7
8
9
12
13
14
15
16
17
18
19
20
21
22
NOTE 1 Do Not Use (DNU)
NOTE 2 Top View, A1 in Top Left Corner
NOTE 3 ODT pin is NOT supported. ODT die pad is connected to VSS inside the package.
12
Version 1.4
02/2018
Nanya Technology Corp.
All Rights Reserved ©
NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
LPDDR3 12x12 PoP-FBGA 1-channel x 32 Pin list
(168-ball SDP, 12.00mm x 12.00mm, 0.50mm pitch)
Part Number: NT6CL128M32CQ-XXX
Pin
Signal name
Pin
Signal name
Pin Signal name Pin Signal name Pin
Signal name
A1
A2
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
VDD1
VSS
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
C1
DQ31
VDDQ
DQ28
DQ27
VDDQ
DQ24
DQS3
VDDQ
DM3
H22
H23
J1
DQ8
DQ9
U1
U2
CA7
VDDCA
DQ5
VSS
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AC1
DQ20
VDDQ
DQ22
DQS2
VDDQ
DM2
VDD2
DNU
DNU
DNU
DNU
CKE
A3
DNU
U22
U23
V1
A4
J2
DNU
A5
J22
J23
K1
DQS1
VSS
VSS
A6
V2
CA6
A7
DNU
V22
V23
W1
VDDQ
DQ4
CA5
A8
K2
DNU
A9
K22
K23
L1
VDDQ
DNU
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
B1
VDD2
DNU
W2
VDDCA
DQ2
DQ3
W22
W23
Y1
AC2
DNU
L2
DNU
AC3
DQ30
DQ29
VSS
VSS
L22
L23
M1
M2
M22
M23
N1
VDD2
DM1
AC4
NC
C2
VDD2
DQ15
VSS
Y2
CK
AC5
VSS
C22
C23
D1
DNU
Y22
Y23
AA1
AA2
AA22
AA23
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
AB11
AB12
AB13
AB14
DQ1
VSS
AC6
CA0
DQ26
DQ25
VSS
VSS
AC7
CA2
DNU
VREFDQ
VSS
VSS
AC8
VDDCA
DNU
DNU
NC
D2
DNU
VDD2
VDDQ
DQ0
DNU
DNU
AC9
VDD1
VSS
D22
D23
E1
VDDQ
DQ14
DNU
DNU
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
N2
VDD1
VDD1
DM0
N22
N23
P1
VSS
DNU
DNU
DNU
DNU
VDD1
DNU
DNU
DNU
DNU
DNU
DNU
VSS
E2
DNU
DQ17
DQ19
VSS
E22
E23
F1
DQ12
DQ13
DNU
ZQ
P2
VREFCA
VSS
NC
B2
P22
P23
R1
VDD1
CA1
DQ21
DQ23
VSS
B3
F2
DNU
B4
F22
F23
G1
DQ11
VSS
VSS
VSS
B5
R2
VDD2
VDDQ
DQS0
CA9
CA3
VDD1
VSS
B6
DNU
R22
R23
T1
CA4
B7
G2
DNU
VDD2
VSS
B8
G22
G23
H1
VDDQ
DQ10
DNU
DNU
DNU
B9
T2
CA8
DQ16
VDDQ
DQ18
B10
B11
T22
T23
DQ6
VDD2
H2
DNU
DQ7
13
Version 1.4
Nanya Technology Corp.
02/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
LPDDR3 178-ball FBGA SDP X32 ballout
(10.50mm x 11.50mm, 0.65mm/0.80mm mixed pitch)
Part Number: NT6CL128M32CM-XXX
< TOP View>
See the balls through the package
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
A
B
C
D
E
F
DNU
DNU
DNU
VSS
CA9
CA8
CA7
VDD1
ZQ
VDD1
NC
VDD1 VDD1
VDD2 VDD2 VDD1 VDDQ
DNU
VSS
DNU
DNU
A
B
C
D
E
F
VSS
VSS
VSS
VSS
DQ31 DQ30 DQ29
DQ27 DQ26 DQ25
DM3 DQ15 DQS3
VDDQ DQ14 DQ13
DQ28
DQ24
DQ12
DQ8
VSS
VSS
CA6
NC
VDDQ
VSS
VDD2
VSS
VSS
VSS
VDD2 VDD2
VSS
VSS
VSS
VSS
VSS
VDDQ
VSS
VDDCA CA5
VDDCA VSS
DQ11 DQ10
DM1 VSS DQS1
VDDQ VDDQ VSS
DQ9
G
H
J
VDD2
VDDQ
G
H
J
VSS VDDCA VREFCA VDD2 VDD2
VDDQ VDD2
VSS
CK
CKE
VSS
NC
VDD2 VDD2
VDD2 VDD2
ODT VDDQ VDDQ VREFDQ VSS
K
L
VDDQ
DM0
NC
VSS
VDDQ VDD2
K
L
VDDCA
NC
VDD2
VSS
VSS
VSS
VSS
VSS DQS0
VDDQ
M
N
P
R
T
VDDCA CA4
VSS
VSS
VDD2
VSS
VSS
VDD1
DQ4
DQ5
DQ6
DQ2
DQ7
DQ3
VSS
VDDQ
VSS
M
N
P
R
T
CA2
CA1
CA0
VSS
DNU
CA3
VSS
NC
VSS
VDDQ DQ1
DM2
VDD2 VDD2
DQ0 DQS2
DQ23
DQ19
VSS
VSS
VSS
VSS
DQ20 DQ21 DQ22
DQ16 DQ17 DQ18
VDDQ
VSS
DNU
DNU
VSS
VDD1
DNU
DNU
U
VDD1 VDD1
VDD2 VDD2 VDD1 VDDQ
DNU
U
1
2
3
4
5
6
7
8
9
10
11
12
13
NOTE 1 Do Not Use (DNU)
NOTE 2 Top View, A1 in Top Left Corner
14
Version 1.4
02/2018
Nanya Technology Corp.
All Rights Reserved ©
NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
LPDDR3 FBGA SDP X32 Pin list
(178-ball SDP 10.50mm x 11.50mm, 0.65mm/0.80mm mixed pitch)
Part Number: NT6CL128M32CM-XXX
Pin
Signal name
Pin
Signal name
Pin Signal name Pin Signal name Pin
Signal name
A1
A2
DNU
DNU
VDD1
VDD1
VDD1
VDD1
VDD2
VDD2
VDD1
VDDQ
DNU
DNU
DNU
VSS
D4
D5
VDD2
VDD2
VDD2
DM3
G11
G12
H2
H3
H4
H5
H6
H8
H9
H10
H11
H12
J2
VDDQ
VSS
L6
L8
VSS
DM0
VSS
R2
R3
CA0
NC
A3
D6
L9
R4
VSS
A4
D8
VDDCA
VREFCA
VDD2
VDD2
VDDQ
VDDQ
VSS
L10
L11
L12
M2
M3
M4
M5
M6
M8
M9
M10
M11
M12
N2
DQS0
VDDQ
VDDCA
CA4
R5
VSS
A5
D9
DQ15
DQS3
VSS
R6
VSS
A6
D10
D11
D12
E2
R8
DQ20
DQ21
DQ22
DQ23
VDDQ
DNU
VSS
A8
R9
A9
R10
R11
R12
T1
A10
A11
A12
A13
B1
CA7
VSS
E3
CA6
VSS
E4
VSS
VDDQ
VDD2
VSS
E5
VSS
DQ4
T2
E6
VSS
DQ5
T3
VSS
B2
E8
VDDQ
DQ14
DQ13
DQ12
VDDQ
VDDCA
CA5
J3
CK
DQ6
T4
VSS
B3
ZQ
E9
J4
VSS
DQ7
T5
VSS
B4
NC
E10
E11
E12
F2
J5
VDD2
VDD2
ODT
VSS
T6
VSS
B5
VSS
J6
CA2
T8
DQ16
DQ17
DQ18
DQ19
VSS
B6
VSS
J8
N3
CA3
T9
B8
DQ31
DQ30
DQ29
DQ28
VSS
J9
VDDQ
VDDQ
VREFDQ
VSS
N4
VSS
T10
T11
T12
T13
U1
B9
F3
J10
J11
J12
K2
N5
VSS
B10
B11
B12
B13
C2
F4
VSS
N6
VSS
F5
VSS
N8
VDDQ
DQ1
DNU
DNU
DNU
VDD1
VDD1
VDD1
VDD1
VDD2
VDD2
VDD1
VDDQ
DNU
DNU
F6
VSS
VSS
N9
DNU
CA9
F8
DQ11
DQ10
DQ9
K3
CKE
N10
N11
N12
P2
DQ2
U2
F9
K4
NC
DQ3
U3
C3
VSS
F10
F11
F12
G2
G3
G4
G5
G6
G8
G9
G10
K5
VDD2
VDD2
VDDQ
NC
VDDQ
CA1
U4
C4
NC
DQ8
K6
U5
C5
VSS
VSS
K8
P3
VSS
U6
C6
VSS
VDDCA
VSS
K9
P4
VDD2
VDD2
VDD2
DM2
DQ0
U8
C8
DQ27
DQ26
DQ25
DQ24
VDDQ
CA8
K10
K11
K12
L2
VSS
P5
U9
C9
VSS
VDDQ
VDD2
VDDCA
P6
U10
U11
U12
U13
C10
C11
C12
D2
VDD2
VSS
P8
P9
DM1
L3
P10
P11
P12
DQS2
VSS
VSS
L4
NC
D3
VSS
DQS1
L5
VDD2
15
Version 1.4
Nanya Technology Corp.
02/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
LPDDR3 178-ball FBGA SDP X16 ballout
(10.50mm x 11.50mm, 0.65mm/0.80mm mixed pitch)
Part Number: NT6CL256M16CM-XXX
< TOP View>
See the balls through the package
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
A
B
C
D
E
F
DNU
DNU
DNU
VSS
CA9
CA8
CA7
VDD1
ZQ
VDD1
NC
VDD1 VDD1
VDD2 VDD2 VDD1 VDDQ
DNU
VSS
DNU
DNU
A
B
C
D
E
F
VSS
VSS
VSS
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
VSS
CA6
NC
VDDQ
VSS
VDD2
VSS
VSS
VSS
VDD2 VDD2
DQ15
NC
VSS
VSS
VSS
VSS
VSS
VDDQ DQ14 DQ13
DQ11 DQ10 DQ9
DM1 VSS DQS1
VDDQ VDDQ VSS
DQ12
DQ8
VDDQ
VSS
VDDCA CA5
VDDCA VSS
G
H
J
VDD2
VDDQ
G
H
J
VSS VDDCA VREFCA VDD2 VDD2
VDDQ VDD2
VSS
CK
CKE
VSS
NC
VDD2 VDD2
VDD2 VDD2
ODT VDDQ VDDQ VREFDQ VSS
K
L
VDDQ
DM0
NC
VSS
VDDQ VDD2
K
L
VDDCA
NC
VDD2
VSS
VSS
VSS
VSS
VSS DQS0
VDDQ
M
N
P
R
T
VDDCA CA4
VSS
VSS
VDD2
VSS
VSS
VDD1
DQ4
DQ5
DQ6
DQ2
NC
DQ7
DQ3
NC
VSS
VDDQ
VSS
M
N
P
R
T
CA2
CA1
CA0
VSS
DNU
CA3
VSS
NC
VSS
VDDQ DQ1
VDD2 VDD2
NC
NC
NC
DQ0
NC
VSS
VSS
VSS
VSS
NC
NC
VDDQ
VSS
DNU
DNU
VSS
VDD1
NC
NC
NC
DNU
DNU
U
VDD1 VDD1
VDD2 VDD2 VDD1 VDDQ
DNU
U
1
2
3
4
5
6
7
8
9
10
11
12
13
NOTE 1 Do Not Use (DNU)
NOTE 2 Top View, A1 in Top Left Corner
16
Version 1.4
02/2018
Nanya Technology Corp.
All Rights Reserved ©
NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
LPDDR3 FBGA SDP X16 Pin list
(178-ball SDP 10.50mm x 11.50mm, 0.65mm/0.80mm mixed pitch)
Part Number: NT6CL256M16CM-XXX
Pin
Signal name
Pin
Signal name
Pin Signal name Pin Signal name Pin
Signal name
A1
A2
DNU
DNU
VDD1
VDD1
VDD1
VDD1
VDD2
VDD2
VDD1
VDDQ
DNU
DNU
DNU
VSS
ZQ
D4
D5
VDD2
VDD2
VDD2
NC
G11
G12
H2
H3
H4
H5
H6
H8
H9
H10
H11
H12
J2
VDDQ
VSS
L6
L8
VSS
DM0
VSS
DQS0
VDDQ
VDDCA
CA4
R2
R3
CA0
NC
A3
D6
L9
R4
VSS
VSS
VSS
NC
A4
D8
VDDCA
VREFCA
VDD2
VDD2
VDDQ
VDDQ
VSS
L10
L11
L12
M2
M3
M4
M5
M6
M8
M9
M10
M11
M12
N2
R5
A5
D9
DQ15
NC
R6
A6
D10
D11
D12
E2
R8
A8
NC
R9
NC
A9
VSS
R10
R11
R12
T1
NC
A10
A11
A12
A13
B1
CA7
VSS
VSS
VSS
DQ4
DQ5
DQ6
DQ7
VSS
CA2
NC
E3
CA6
VDDQ
DNU
VSS
VSS
VSS
VSS
VSS
NC
E4
VSS
VDDQ
VDD2
E5
VSS
T2
E6
VSS
T3
B2
E8
VDDQ
DQ14
DQ13
DQ12
VDDQ
VDDCA
CA5
J3
CK
T4
B3
E9
J4
VSS
T5
B4
NC
E10
E11
E12
F2
J5
VDD2
VDD2
ODT
T6
B5
VSS
VSS
NC
J6
T8
B6
J8
N3
CA3
T9
NC
B8
J9
VDDQ
VDDQ
VREFDQ
VSS
N4
VSS
VSS
VSS
VDDQ
DQ1
DQ2
DQ3
VDDQ
CA1
T10
T11
T12
T13
U1
NC
B9
NC
F3
J10
J11
J12
K2
N5
NC
B10
B11
B12
B13
C2
NC
F4
VSS
N6
VSS
DNU
DNU
DNU
VDD1
VDD1
VDD1
VDD1
VDD2
VDD2
VDD1
VDDQ
DNU
DNU
NC
F5
VSS
N8
VSS
DNU
CA9
VSS
NC
F6
VSS
VSS
N9
F8
DQ11
DQ10
DQ9
K3
CKE
N10
N11
N12
P2
U2
F9
K4
NC
U3
C3
F10
F11
F12
G2
G3
G4
G5
G6
G8
G9
G10
K5
VDD2
VDD2
VDDQ
NC
U4
C4
DQ8
K6
U5
C5
VSS
VSS
NC
VSS
K8
P3
VSS
VDD2
VDD2
VDD2
NC
U6
C6
VDDCA
VSS
K9
P4
U8
C8
K10
K11
K12
L2
VSS
P5
U9
C9
NC
VSS
VDDQ
VDD2
VDDCA
P6
U10
U11
U12
U13
C10
C11
C12
D2
NC
VDD2
VSS
P8
NC
P9
DQ0
NC
VDDQ
CA8
VSS
DM1
VSS
L3
P10
P11
P12
L4
NC
NC
D3
DQS1
L5
VDD2
VSS
17
Version 1.4
Nanya Technology Corp.
02/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
LPDDR3 12x12 PoP-FBGA 1-channel x 32 ballout
(168-ball DDP, 12.00mm x 12.00mm, 0.50mm pitch)
Part Number: NT6CL256T32CQ-XXX
< TOP View>
See the balls through the package
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
A
B
DNU
DNU
VSS
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
ZQ
DNU
DNU
VDD2
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
VSS
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU VDD1 VSS DQ30 DQ29 VSS DQ26 DQ25 VSS
VDD1 VSS
DNU
DNU
DNU
DNU
VSS
DQ14
DQ13
VSS
DQ10
DQ9
VSS
DM1
VSS
DM0
VSS
DQS0
DQ7
VSS
DQ4
DQ3
VSS
DQ0
DNU
DNU
23
A
B
VDD1 DNU
VSS VDD2 DQ31 VDDQ DQ28 DQ27 VDDQ DQ24 DQS3 VDDQ DM3 VDD2
C
D
E
DQ15
VDDQ
DQ12
DQ11
VDDQ
DQ8
C
D
E
F
F
G
H
J
G
H
J
DQS1
VDDQ
VDD2
VrefDQ
VDD1
VDDQ
DQ6
K
K
L
L
M
N
P
M
N
P
VDD1
VrefCA
VDD2
CA8
R
T
VSS
CA9
CA7
VSS
CA5
R
T
U
V
VDDCA
CA6
DQ5
U
V
VDDQ
DQ2
W
Y
VDDCA
CK
W
Y
DQ1
AA
AB
AC
VSS
DNU
DNU
1
VDD2
DNU
DNU
2
VDDQ
DNU
AA
AB
AC
VDD1 CA1
VSS
CA3
CA4 VDD2 VSS DQ16 VDDQ DQ18 DQ20 VDDQ DQ22 DQS2 VDDQ DM2 VDD2
CKE0 CKE1 VSS
CA0
6
CA2 VDDCA DNU
DNU
10
NC
11
VSS DQ17 DQ19 VSS DQ21 DQ23 VSS
VDD1 VSS
DNU
3
4
5
7
8
9
12
13
14
15
16
17
18
19
20
21
22
NOTE 1 Do Not Use (DNU)
NOTE 2 Top View, A1 in Top Left Corner
NOTE 3 ODT pins are NOT supported. ODT die pad is connected to VSS inside the package.
NOTE 4 ZQ is connected to both dies.
18
Version 1.4
02/2018
Nanya Technology Corp.
All Rights Reserved ©
NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
LPDDR3 12x12 PoP-FBGA 1-channel x 32 Pin list
(168-ball DDP, 12.00mm x 12.00mm, 0.50mm pitch)
Part Number: NT6CL256T32CQ-XXX
Pin
Signal name
Pin
Signal name
Pin Signal name Pin Signal name Pin
Signal name
A1
A2
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
VDD1
VSS
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
C1
DQ31
VDDQ
DQ28
DQ27
VDDQ
DQ24
DQS3
VDDQ
DM3
H22
H23
J1
DQ8
DQ9
U1
U2
CA7
VDDCA
DQ5
VSS
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AC1
DQ20
VDDQ
DQ22
DQS2
VDDQ
DM2
A3
DNU
U22
U23
V1
A4
J2
DNU
A5
J22
J23
K1
DQS1
VSS
VSS
A6
V2
CA6
A7
DNU
V22
V23
W1
VDDQ
DQ4
CA5
VDD2
DNU
A8
K2
DNU
A9
K22
K23
L1
VDDQ
DNU
DNU
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
B1
VDD2
DNU
W2
VDDCA
DQ2
DQ3
DNU
W22
W23
Y1
AC2
DNU
DNU
L2
DNU
AC3
CKE0
CKE1
VSS
DQ30
DQ29
VSS
VSS
L22
L23
M1
M2
M22
M23
N1
VDD2
DM1
AC4
C2
VDD2
DQ15
VSS
Y2
CK
AC5
C22
C23
D1
DNU
Y22
Y23
AA1
AA2
AA22
AA23
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
AB11
AB12
AB13
AB14
DQ1
VSS
AC6
CA0
DQ26
DQ25
VSS
VSS
AC7
CA2
DNU
VREFDQ
VSS
VSS
AC8
VDDCA
DNU
D2
DNU
VDD2
VDDQ
DQ0
DNU
DNU
AC9
VDD1
VSS
D22
D23
E1
VDDQ
DQ14
DNU
DNU
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
DNU
N2
VDD1
VDD1
DM0
NC
N22
N23
P1
VSS
DNU
DNU
DNU
DNU
VDD1
DNU
DNU
DNU
DNU
DNU
DNU
VSS
E2
DNU
DQ17
DQ19
VSS
E22
E23
F1
DQ12
DQ13
DNU
ZQ
P2
VREFCA
VSS
B2
P22
P23
R1
VDD1
CA1
DQ21
DQ23
VSS
B3
F2
DNU
B4
F22
F23
G1
DQ11
VSS
VSS
VSS
B5
R2
VDD2
VDDQ
DQS0
CA9
CA3
VDD1
VSS
B6
DNU
R22
R23
T1
CA4
B7
G2
DNU
VDD2
VSS
B8
G22
G23
H1
VDDQ
DQ10
DNU
DNU
B9
T2
CA8
DQ16
VDDQ
DQ18
DNU
B10
B11
T22
T23
DQ6
VDD2
H2
DNU
DQ7
19
Version 1.4
Nanya Technology Corp.
02/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
LPDDR3 178-ball FBGA DDP X32 ballout
(10.50mm x 11.50mm, 0.65mm/0.80mm mixed pitch)
Part Number: NT6CL256T32CM-XXX
< TOP View>
See the balls through the package
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
A
B
C
D
E
F
DNU
DNU
DNU
VSS
CA9
CA8
CA7
VDD1
ZQ
VDD1
NC
VDD1 VDD1
VDD2 VDD2 VDD1 VDDQ
DNU
VSS
DNU
DNU
A
B
C
D
E
F
VSS
VSS
VSS
VSS
DQ31 DQ30 DQ29
DQ27 DQ26 DQ25
DM3 DQ15 DQS3
VDDQ DQ14 DQ13
DQ28
DQ24
DQ12
DQ8
VSS
VSS
CA6
NC
VDDQ
VSS
VDD2
VSS
VSS
VSS
VDD2 VDD2
VSS
VSS
VSS
VSS
VSS
VDDQ
VSS
VDDCA CA5
VDDCA VSS
DQ11 DQ10
DM1 VSS DQS1
VDDQ VDDQ VSS
DQ9
G
H
J
VDD2
VDDQ
G
H
J
VSS VDDCA VREFCA VDD2 VDD2
VDDQ VDD2
CK
VSS
CKE1
VDD2 VDD2
VDD2 VDD2
ODT VDDQ VDDQ VREFDQ VSS
K
L
VSS
CKE0
VDDQ
DM0
NC
VSS
VDDQ VDD2
K
L
VDDCA
VDD2
VSS
VSS
VSS
VSS
VSS DQS0
VDDQ
M
N
P
R
T
VDDCA CA4
VSS
DQ4
DQ5
DQ6
DQ2
DQ7
DQ3
VSS
VDDQ
VSS
M
N
P
R
T
CA2
CA1
CA0
VSS
DNU
CA3
VSS
NC
VSS
VSS
VDDQ DQ1
DM2
VDD2
VSS
VDD2 VDD2
DQ0 DQS2
DQ23
DQ19
VSS
VSS
VSS
VSS
DQ20 DQ21 DQ22
DQ16 DQ17 DQ18
VDDQ
VSS
DNU
DNU
VSS
VDD1
VSS
DNU
DNU
U
VDD1
VDD1 VDD1
VDD2 VDD2 VDD1 VDDQ
DNU
U
1
2
3
4
5
6
7
8
9
10
11
12
13
NOTE 1 Do Not Use (DNU)
NOTE 2 Top View, A1 in Top Left Corner
20
Version 1.4
02/2018
Nanya Technology Corp.
All Rights Reserved ©
NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
LPDDR3 FBGA DDP X32 Pin list
(178-ball DDP 10.50mm x 11.50mm, 0.65mm/0.80mm mixed pitch)
Part Number: NT6CL256T32CM-XXX
Pin
Signal name
Pin
Signal name
Pin Signal name Pin Signal name Pin
Signal name
A1
A2
DNU
DNU
VDD1
VDD1
VDD1
VDD1
VDD2
VDD2
VDD1
VDDQ
DNU
DNU
DNU
VSS
D4
D5
VDD2
VDD2
VDD2
DM3
G11
G12
H2
H3
H4
H5
H6
H8
H9
H10
H11
H12
J2
VDDQ
VSS
L6
L8
VSS
DM0
VSS
R2
R3
CA0
NC
A3
D6
L9
R4
VSS
A4
D8
VDDCA
VREFCA
VDD2
VDD2
VDDQ
VDDQ
VSS
L10
L11
L12
M2
M3
M4
M5
M6
M8
M9
M10
M11
M12
N2
DQS0
VDDQ
VDDCA
CA4
R5
VSS
A5
D9
DQ15
DQS3
VSS
R6
VSS
A6
D10
D11
D12
E2
R8
DQ20
DQ21
DQ22
DQ23
VDDQ
DNU
VSS
A8
R9
A9
R10
R11
R12
T1
A10
A11
A12
A13
B1
CA7
VSS
E3
CA6
VSS
E4
VSS
VDDQ
VDD2
VSS
E5
VSS
DQ4
T2
E6
VSS
DQ5
T3
VSS
B2
E8
VDDQ
DQ14
DQ13
DQ12
VDDQ
VDDCA
CA5
J3
CK
DQ6
T4
VSS
B3
ZQ
E9
J4
VSS
DQ7
T5
VSS
B4
NC
E10
E11
E12
F2
J5
VDD2
VDD2
ODT
VSS
T6
VSS
B5
VSS
J6
CA2
T8
DQ16
DQ17
DQ18
DQ19
VSS
B6
VSS
J8
N3
CA3
T9
B8
DQ31
DQ30
DQ29
DQ28
VSS
J9
VDDQ
VDDQ
VREFDQ
VSS
N4
VSS
T10
T11
T12
T13
U1
B9
F3
J10
J11
J12
K2
N5
VSS
B10
B11
B12
B13
C2
F4
VSS
N6
VSS
F5
VSS
N8
VDDQ
DQ1
DNU
DNU
DNU
VDD1
VDD1
VDD1
VDD1
VDD2
VDD2
VDD1
VDDQ
DNU
DNU
F6
VSS
VSS
N9
DNU
CA9
F8
DQ11
DQ10
DQ9
K3
CKE0
CKE1
VDD2
VDD2
VDDQ
NC
N10
N11
N12
P2
DQ2
U2
F9
K4
DQ3
U3
C3
VSS
F10
F11
F12
G2
G3
G4
G5
G6
G8
G9
G10
K5
VDDQ
CA1
U4
C4
NC
DQ8
K6
U5
C5
VSS
VSS
K8
P3
VSS
U6
C6
VSS
VDDCA
VSS
K9
P4
VDD2
VDD2
VDD2
DM2
DQ0
U8
C8
DQ27
DQ26
DQ25
DQ24
VDDQ
CA8
K10
K11
K12
L2
VSS
P5
U9
C9
VSS
VDDQ
VDD2
VDDCA
P6
U10
U11
U12
U13
C10
C11
C12
D2
VDD2
VSS
P8
P9
DM1
L3
P10
P11
P12
DQS2
VSS
VSS
L4
D3
VSS
DQS1
L5
VDD2
21
Version 1.4
Nanya Technology Corp.
02/2018
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NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
LPDDR3 12x12 PoP-FBGA 2-channel 2x32 ballout
(216-ball DDP, 12.00mm x 12.00mm, 0.40mm pitch)
Part Number: NT6CL128T64CR-XXX
< TOP View>
See the balls through the package
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
DQ30 DQ29
DQ26 DQ25
DQ14 DQ13
DQ11 DQ10 DQ9_ DQS1 DM1_
DQS0 DQ7_ DQ6_ DQ4_ DQ3_
A
A
B
NC VSS VDD2
VSS
VSS
VSS
VSS VDD1 VDD2
VREF
VDDQ
VSS NC
NC VSS
VDD1 VDD2
_a
_a
_a
_a
DQ24
_a
_a
_a
_a
_a
DQ12
_a
_a
a
_a
a
_a
a
a
a
a
DQ31
VSS NC
_a
DQ28 DQ27
DQS3 DM3_ DQ15
DQ8_ /DQS
DM0_ /DQS
DQ5_ DQ2_
B
VDDQ
VDDQ
VDDQ
VDDQ VSS
VDD2
VDDQ
VSS
VSS VDDQ
_a
_a
_a
a
_a
DQ_a
a
1_a
a
0_a
a
a
DQ16
VDD1
C
C
_b
DQ17
VDDQ
_b
DQ1_
VDDQ
a
D
D
DQ18 DQ19
DQ0_
E
E
VSS
a
_b
_b
DQ20
_b
DM2_
VDDQ
a
F
F
VSS
DQ21
_b
DQS2
G
G
VDDQ
_a
_a
DQ23
_a
DQ22 DQ23
_b _b
H
H
VSS
DQ22
_a
J
J
VSS VDDQ
VDDQ
DQS2
DQ20 DQ21
K
K
_b
_b
_a
DQ19
_a
_a
DM2_ DQ0_
L
L
VSS
b
DQ1_
b
b
DQ18
_a
M
N
M
N
VSS
VDDQ
DQ2_
b
DQ16 DQ17
_a _a
VDD1
P
P
VSS VSS
VDD2 VDD1
VREF
VDD1
CA0_
R
R
VSS
b
DQ_b
VDD CA1_
T
T
VDD2 VDD2
CA
b
DQ3_
VREF CA2_
U
U
VDDQ
b
CA_b
VSS
b
CA3_
b
DQ4_
VSS
b
V
V
DQ6_ DQ5_
CA4_
b
W
Y
W
Y
NC
b
b
DQ7_
b
VDDQ
_b NC
DQS0
CKE_
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AA
AB
AC
AD
AE
AF
AG
AH
AJ
VSS
b
_b
DM0_
b
_b
VSS
CK_b _b
DM1_
b
VDD CA5_
VDDQ
CA
b
DQS1
CA7_ CA6_
_b
DQ8_
b
_b
b
b
CA8_ VDD
VSS
b
CA
CA9_
b
DQ9_
b
VDDQ
VSS
DQ10 DQ11
_b _b
VDD2 ZQ_b
VDD1 VSS
VSS NC
DQ13
_b
DQ15 DM3_ DQS3
DQ26 DQ27
DQ30
VREF CA9_
CA7_ CA6_
VDD CKE_
_a
CA3_ CA2_ CA1_
VSS VDD1 VDD2
VSS
VDDQ
VDDQ
VSS VDD2
VSS
_a
_b
b
_b
_b
_b
_b
CA_a
VDD1 VSS ZQ_a
15 16 17
a
a
a
CA
a
a
a
a
DQ12
NC VSS
_b
DQ14
_b
DQ24 DQ25
DQ28 DQ29 DQ31
CA8_ VDD CA5_
CA4_ VDD CA0_
VDDQ
VDDQ VSS
VSS
CK_a VSS NC NC
21 22 23 24
_b
_b
_b
_b
_b
_b
a
CA
a
a
CA
a
1
2
3
4
5
6
7
8
9
10
11
12
13
14
18
19
20
25
26
27
28
29
NOTE 1 Top View, A1 in Top Left Corner
22
Version 1.4
Nanya Technology Corp.
02/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
LPDDR3 14x14 PoP-FBGA 2-channel 2x32 ballout
(256-ball DDP, 14.00mm x 14.00mm, 0.40mm pitch)
Part Number: NT6CL128T64C4-XXX
< TOP View>
See the balls through the package
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
DQ0
32
33
34
DQ30 DQ28 DQ27
_a
DQ24 DQS3
_a
DQ15
_a
DQ12 DQ11
DQ8 DQS1
ODT VREF
DQ7
DQ4 DQ3
A
B
DNU DNU VDD2
DNU VSS VDD1
VDDQ
VDDQ VDD2
VDDQ
VDDQ
VDDQ VDD2
VDDQ
VDDQ
VDDQ
VDDQ VDD2 DNU DNU
A
B
C
D
E
F
_a
_a
_a
_a
_a
_a
_a
_a
DQ_a
_a
_a
_a
_a
_a
DQ31 DQ29
_a
DQ26 DQ25
_a
DM3_
DQ14 DQ13
DQ10 DQ9
DM1_
DM0 DQS0
_a
DQ6 DQ5
DQ2 DQ1
_a _a
DM2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD1 VSS DNU
_a
_a
_a
_a
a
_a
_a
_a
_a
_a
a
_a
_a
_a
VDDQ
_a
C
D
E
VDD2 VDD1
DQ17 DQ16
DQS2
VSS
_a
_b
_b
DQ19 DQ18
DQ22 DQ23
_b
_b
_a
_a
DQ20
_b
DQ21
_a
F
VSS
VDDQ
DQ21
_b
DQ20
_a
G
H
J
VDDQ
VSS
G
H
J
DQ23 DQ22
DQ18 DQ19
_a _a
_b
_b
DQS2
_b
DQ16 DQ17
_a _a
VSS
_b
K
VDDQ
VDD2
VSS VDDQ
VDD1 VDD2
K
L
DM2
_b
L
DQ0
_b
M
N
P
VSS
VSS
VSS
M
N
P
R
T
DQ1
_b
CA0 VDD
_b
VDDQ
CA
DQ3 DQ2
_b
CA2
_b
CA1
_b
_b
DQ4
_b
R
T
VSS
VSS VDD2
DQ5
_b
CA4
_b
CA3
_b
VDDQ
DQ7 DQ6
U
V
NC
NC
_b
U
V
W
Y
_b
_b
_b
CKE
_b
VSS
DQS0
_b
VDD
CA
W
Y
VDDQ
VSS
VREF DM0
_b CK_b
DQ_b
_b
ODT
_b
VREF
CA_b
AA
VSS
VDD2 AA
DM1_
b
VDD
AB
AB VDD2
AC VDDQ
VSS
CA
_b
CA6_ CA5
AC
AD
AE
AF
AG
b
_b
DQS1
CA7_
b
AD
_b
VSS
VSS
DQ8 DQ9
CA8 VDD
AE
_b
_b
_b
CA
DQ10
_b
ZQ
_b
CA9
_b
AF VDDQ
DQ11
AG
_b
VSS
RFU
NC
DQ12 DQ13
AH
VDD1 VDD2 AH
_b
_b
DQ14
_b
AJ VDDQ
VSS
VSS
AJ
DQ15
AK
_b
VSS
DNU DNU AK
DNU DNU AL
DNU DNU AM
DM3
_b
AL VDDQ
AM VDD2 VDD1
_b
DQ25 DQ26
DQ29 DQ31
_b _b
CA8
_a
CA6
_a
VREF
CA_a
CA4
_a
CA2
_a
CA0
_a
AN
AP
DNU VSS
VSS
VSS
VSS VDD1 RFU ZQ_a
CA9
VSS
VSS
_a VSS
NC
NC
VSS
VSS VDD1 VSS DNU DNU DNU DNU DNU AN
VSS VDD2 VSS DNU DNU DNU DNU DNU AP
_b
_b
VDDQ
6
DQS3 DQ24
DQ27 DQ28 DQ30
VDD
CA
CA7
_a
CA5
_a
VDD
CA
VDD CKE
CA
CA3
_a
CA1
_a
VDD
CA
DNU DNU VDDQ
VDDQ VDD2
NC
VDD2 CK_a
_a
VDD2
24
_b
_b
_b
_b
_b
_a
_a
1
2
3
4
5
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
25
26
27
28
29
30
31
32
33
34
NOTE 1 Do Not Use (DNU)
NOTE 2 Top View, A1 in Top Left Corner
NOTE 3 In case ODT function is not used, ODT pin should be considerd as NC.
23
Version 1.4
Nanya Technology Corp.
02/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
168-ball Package Outline Drawing
Part Number: NT6CL128M32CQ-XXX, NT6CL256T32CQ-XXX
Unit: mm
* BSC (Basic Spacing between Center)
24
Version 1.4
Nanya Technology Corp.
02/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
178-ball Package Outline Drawing
Part Number: NT6CL128M32CM-XXX, NT6CL256T32CM-XXX
NT6CL256M16CM-XXX
Unit: mm
* BSC (Basic Spacing between Center)
25
Version 1.4
Nanya Technology Corp.
02/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
216-ball Package Outline Drawing
Part Number: NT6CL128T64CR-XXX
Unit: mm
* BSC (Basic Spacing between Center)
26
Version 1.4
Nanya Technology Corp.
02/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
256-ball Package Outline Drawing (14.00mm x 14.00mm)
Part Number: NT6CL128T64C4-XXX
Unit: mm
* BSC (Basic Spacing between Center)
27
Version 1.4
Nanya Technology Corp.
02/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Ball Definition and Descriptions
Symbol
Type
Function
Clock: CK and are differential clock inputs. All Double Data Rate (DDR) CA inputs are sampled
on both positive and negative edge of CK. Single Data Rate (SDR) inputs, and CKE, are
sampled at the positive Clock edge.
CK,
Input
Clock is defined as the differential pair, CK and . The positive Clock edge is defined by the
crosspoint of a rising CK and a falling . The negative Clock edge is defined by the crosspoint of a
falling CK and a rising .
Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and therefore
device input buffers and output drivers. Power savings modes are entered and exited through CKE
transitions.
CKE
Input
CKE is considered part of the command code. See Command Truth Table for command code
descriptions. CKE is sampled at the positive Clock edge.
Chip Select: is considered part of the command code. See Command Truth Table for
command code descriptions. is sampled at the positive Clock edge.
Input
Input
DDR Command/Address Inputs: Uni-directional command/address bus inputs.
CA0 – CA9
CA is considered part of the command code. See Command Truth Table for command code
descriptions.
Input Data Mask: DM is the input mask signal for write data. Input data is masked when DM is
sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges
of DQS. Although DM is for input only, the DM loading shall match the DQ and DQS (or ).
For x16
DM0 – DM1
For x32
Input
For x16 and x32 devices, DM0 is the input data mask signal for the data on DQ0-7. DM1 is the
input data mask signal for the data on DQ8-15.
DM0 - DM3
For x32 devices, DM2 is the input data mask signal for the data on DQ16-23 and DM3 is the input
data mask signal for the data on DQ24-31.
For x16
DQ0 - DQ15
For x32
Input/output
Data Inputs/Output: Bi-directional data bus
DQ0 - DQ31
Data Strobe (Bi-directional, Differential): The data strobe is bi-directional (used for read and
write data) and differential (DQS and ). It is output with read data and input with write data.
DQS is edge-aligned to read data and centered with write data.
For x16
DQS0-1,
For x32
For x16 DQS0 and correspond to the data on DQ0 - DQ7, DQS1 and to the data on
Input/output
DQ8 - DQ15,
DQS0-3,
For x32 DQS0 and correspond to the data on DQ0 - DQ7, DQS1 and to the data on
DQ8 - DQ15, DQS2 and to the data on DQ16 - DQ23, DQS3 and to the data on DQ24
- DQ31.
On-Die Termination: This signal enables and disables termination on the DRAM DQ bus according
Input
ODT
to the specified mode register settings.
28
Version 1.4
02/2018
Nanya Technology Corp.
All Rights Reserved ©
NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Symbol
Type
Function
External Reference ball for ZQ Calibration: This ball is tied to an external 240Ω resistor (RZQ),
ZQ
Reference
which is tied to VSS
.
Supply
Supply
Supply
Supply
VDD1
VDD2
VDDQ
VDDCA
Core Power Supply 1: Core power supply
Core Power Supply 2: Core power supply
I/O Power Supply: Power supply for Data input/output buffers.
Input Receiver Power Supply: Power supply for CA0-9, CKE, , CK, and input buffers.
Reference Voltage for CA Command and Control Input Receiver: Reference voltage for all
CA0-9, CKE, , CK, and input buffers.
VREFCA
Supply
VREFDQ
VSS
Supply
Supply
-
Reference Voltage for DQ Input Receiver: Reference voltage for all data input buffers.
Ground
NC
No Connect: No internal electrical connection is present.
NOTE 1: The signal may show up in a different symbol but it indicates to the same thing. e.g., /CK = CK# = = CKb = CK_n = CK_c,
/DQS = DQS# = = DQSb = DQS_n = DQS_c, /CS = CS# = = CSb = CS_n.
NOTE 2: Data includes DQ and DM.
29
Version 1.4
Nanya Technology Corp.
02/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Simplified Bus Interface State Diagram
LPDDR3-SDRAM state diagram provides a simplified illustration of allowed state transitions and the related
commands to control them. For a complete definition of the device behavior, the information provided by the state
diagram should be integrated with the truth tables and timing specification.
The truth tables provide complementary information to the state diagram, they clarify the device behavior and the
applied restrictions when considering the actual state of all the banks.
30
Version 1.4
Nanya Technology Corp.
02/2018
All Rights Reserved ©
NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Simplified State Diagram
Deep
Power
Down
Automatic Sequence
Command Sequence
Power
Power
On
DPDX
Applied
Reset
Resetting
MRR
MR
Reading
Self
Refreshing
DPD
Idle 1
Resetting
PD
PDX
SREF
Resetting
Power
Down
SREFX
Reset
MRR
REF
Refreshing
Idle
MR
Reading
MRW
PD
PDX
MR
Writing2
Idle
Power
Down
NOTE 1: In the Idle state, all banks
are precharged.
ACT
NOTE 2: In the case of MRW to
enter CA Training mode
or Write Leveling Mode,
the state machine will not
automatically return to
the Idle state. In these
cases an additional
MRW command is
Active
Active
Power
Down
MR
PR, PRA
MRR
Reading
PDX
PD
Active
required to exit either
operating mode and
return to the Idle state.
See sections “CA
WR3
RD3
RD
WR
Training” or “Write
Leveling”.
Reading
RDA3
Writing
WRA3
NOTE 3: Terminated bursts are not
allowed. For these state
transitions, the burst
RDA
WRA
operation must be
completed before the
transition can occur.
Reading
with
Autoprecharge
Writing
with
Autoprecharge
PR, PRA
NOTE 4: Use caution with this
diagram. It is intended to
provide a floorplan of the
possible state transitions
and commands to control
them, not all details. In
particular, situations
Precharging
involving more than one
bank are not captured in
full detail.
Abbr.
ACT
Function
Abbr.
Function
Abbr.
SREF
SREFX Exit self refresh
Function
Active
PD
Enter Power Down
Exit Power Down
Enter Deep Power Down
Exit Deep Power Down
Refresh
Enter self refresh
RD(A)
Read (w/ Autoprecharge)
PDX
WR(A) Write (w/ Autoprecharge)
DPD
DPDX
REF
PR(A)
MRW
MRR
Precharge (All)
Mode Register Write
Mode Register Read
RESET
Reset is achieved through MRW command
31
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Absolute Maximum DC Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
Absolute Maximum DC Ratings
Parameter
Symbol
Min
Max
Units
Notes
-0.4
-0.4
-0.4
-0.4
-0.4
-55
2.3
1.6
1.6
1.6
1.6
125
V
V
1
V
V
V
V
DD1 supply voltage relative to VSS
DD2 supply voltage relative to VSS
DDCA supply voltage relative to VSS
DDQ supply voltage relative to VSS
VDD1
VDD2
1
V
1,2
1,3
VDDCA
VDDQ
V
V
Voltage on any ball relative to VSS
VIN, VOUT
TSTG
Storage Temperature
°C
4
NOTE 1 See “Power-Ramp” section for relationships between power supplies.
NOTE 2 VREFCA ≤ 0.6 x VDDCA; however, VREFCA may be ≥ VDDCA provided that VREFCA ≤ 300mV.
NOTE 3 VREFDQ ≤ 0.7 x VDDQ; however, VREFDQ may be ≥ VDDQ provided that VREFDQ ≤ 300mV.
NOTE 4 Storage Temperature is the case surface temperature on the center/top side of the LPDDR3 device. For the
measurement conditions, please refer to JESD51-2 standard.
32
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
AC/DC Operating Conditions
Operation or timing that is not specified is illegal, and after such an event, in order to guarantee proper operation, the
LPDDR3 device must be powered down and then restarted through the specialized initialization sequence before normal
operation can continue.
Recommended DC Operating Conditions
Voltage
Symbol
DRAM
Unit
Min
1.70
1.14
1.14
1.14
Typ
1.80
1.20
1.20
1.20
Max
1.95
1.30
1.30
1.30
Core Power1
Core Power2
V
V
V
V
VDD1
VDD2
Input Buffer Power
I/O Buffer Power
VDDCA
VDDQ
NOTE 1 VDD1 uses significantly less current than VDD2
.
NOTE 2 The voltage range is for DC voltage only. DC is defined as the voltage supplied at the DRAM and is inclusive of all
noise up to 1MHz at the DRAM package ball.
Input Leakage Current
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input Leakage current
-2
-1
2
1
uA
uA
1, 2
3, 4
IL
V
REF supply leakage current
IVREF
NOTE 1 For CA, CKE, , CK, . Any input 0V ≤ VIN ≤ VDDCA (All other pins not under test = 0V)
NOTE 2 Although DM is for input only, the DM leakage shall match the DQ and DQS/ output leakage specification.
NOTE 3 The minimum limit requirement is for testing purposes. The leakage current on VREFCA and VREFDQ pins should be
minimal.
NOTE 4 VREFDQ = VDDQ/2 or VREFCA = VDDCA/2. (All other pins not under test = 0V)
33
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Operating Temperature Range
Parameter/Condition
Symbol
Min
Max
Unit
Commercial
-25
85
oC
TOPER
NOTE 1 Operating Temperature is the case surface temperature on the center-top side of the LPDDR3 device. For the
measurement conditions, please refer to JESD51-2 standard.
NOTE 2 Either the device case temperature rating or the temperature sensor may be used to set an appropriate refresh rate,
determine the need for AC timing de-rating and/or monitor the operating temperature. When using the temperature
sensor, the actual device case temperature may be higher than the TOPER rating that applies for the Standard or Elevated
o
Temperature Ranges. For example, TCASE may be above 85 C when the temperature sensor indicates a temperature of
o
less than 85 C.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
AC/DC Input Level
AC and DC Logic Input Levels for Single-Ended Signals
Single-Ended AC and DC Input Levels for CA and Inputs
1333/1600
1866
Symbol
IHCA(AC)
Parameter
Unit Notes
Min
VRef + 0.150
Note 2
Max
Note 2
Min
Max
Note 2
V
AC input logic high
AC input logic low
DC input logic high
DC input logic low
VRef + 0.135
Note 2
V
V
V
V
1, 2
1, 2
1
V
ILCA(AC)
IHCA(DC)
VRef - 0.150
VDDCA
VRef - 0.135
VDDCA
V
VRef + 0.100
VSS
VRef + 0.100
VSS
V
ILCA(DC)
VRef - 0.100
VRef - 0.100
1
Reference Voltage
for CA and inputs
V
RefCA(DC)
0.49 * VDDCA
0.51 * VDDCA
0.49 * VDDCA
0.51 * VDDCA
V
3, 4
NOTE 1 For CA and input only pins. VRef = VRefCA(DC)
.
NOTE 2 Overshoot and Undershoot Specifications.
NOTE 3 The ac peak noise on VRefCA may not allow VRefCA to deviate from VRefCA(DC) by more than ± 1% VDDCA (for reference:
approx. ± 12 mV).
NOTE 4 For reference: approx. VDDCA/2 ± 12 mV.
Single-Ended AC and DC Input Levels for CKE
Symbol
VIHCKE
Parameter
Min
0.65 * VDDCA
Note 1
Max
Note 1
Unit
V
Notes
CKE Input High Level
CKE Input Low Level
1
1
0.35 * VDDCA
V
VILCKE
NOTE 1 Overshoot and Undershoot Specifications.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Single-Ended AC and DC Input Levels for DQ and DM
1333/1600
1866
Symbol
Parameter
Unit
Notes
Min
AC input logic high VRef + 0.150
AC input logic low Note 2
DC input logic high VRef + 0.100
Max
Note 2
Min
VRef + 0.135
Note 2
Max
Note 2
V
IHDQ(AC)
V
V
V
V
1, 2, 5
V
ILDQ(AC)
VRef - 0.150
VDDQ
VRef - 0.135
VDDQ
1, 2, 5
VIHDQ(DC)
VRef + 0.100
VSS
1
1
V
ILDQ(DC)
DC input logic low
VSS
VRef - 0.100
VRef - 0.100
V
RefDQ(DC)
(DQ ODT disabled)
Reference Voltage
for DQ, DM inputs
0.49 * VDDQ
0.51 * VDDQ 0.49 * VDDQ 0.51 * VDDQ
V
V
3, 4
VRefDQ(DC)
Reference Voltage
for DQ, DM inputs
VODTR/2 -
0.01 * VDDQ
VODTR/2 +
VODTR/2 -
VODTR/2 +
3, 5, 6
(DQ ODT enabled)
0.01 * VDDQ 0.01 * VDDQ 0.01 * VDDQ
NOTE 1 For DQ input only pins. VRef = VRefDQ(DC)
.
NOTE 2 Overshoot and Undershoot Specifications.
NOTE 3 The ac peak noise on VRefDQ may not allow VRefDQ to deviate from VRefDQ(DC) by more than ± 1% VDDQ (for reference:
approx. ± 12 mV).
NOTE 4 For reference: approx. VDDQ/2 ± 12 mV.
NOTE 5 For reference: approx. VODTR/2 ± 12 mV.
NOTE 6 RON and RODT nominal mode register programmed values are used for the calculation of VODTR. For testing purposes a
controller RON value of 50 Ω is used.
VODTR = RON + RTT VDDQ
-----------------------------
RON + RTT
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
VREF Tolerances
The dc-tolerance limits and ac-noise limits for the reference voltages VRefCA and VRefDQ are illustrated below.
It shows a valid reference voltage VRef(t) as a function of time. (VRef stands for VRefCA and VRefDQ likewise). VDD
stands for VDDCA for VRefCA and VDDQ for VRefDQ. VREF(DC) is the linear average of VRef(t) over a very long period of
time (e.g. 1 sec) and is specified as a fraction of the linear average of VDDQ or VDDCA also over a very long
period of time (e.g. 1 sec). This average has to meet the min/max requirements. Furthermore VRef(t) may
temporarily deviate from VREF(DC) by no more than ± 1% VDD. VRef(t) cannot track noise on VDDQ or VDDCA if this
would send VRef outside these specifications.
VREF DC Tolerance and VREF AC Noise Limits
VDD
VRef(AC) noise
VRef(t)
VRef(DC)max
VRef(DC)
VDD/2
VRef(DC)min
VSS
time
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VRef. “VRef
“ shall be understood as VREF(DC) above.
This clarifies that dc-variations of VRef affect the absolute voltage a signal has to reach to achieve a valid high or low
level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to
account for VREF(DC) deviations from the optimum position within the data-eye of the input signals.
This also clarifies that the LPDDR3 setup/hold specification and derating values need to include time and voltage
associated with VRef ac-noise. Timing and voltage effects due to ac-noise on VRef up to the specified limit (+/-1% of
VDD) are included in LPDDR3 timings and their associated deratings.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Input Signal
LPDDR3-1866 to LPDDR3-1333 Input Signal
VIL and VIH levels with ringback
VDD + 0.35V
VDD
Minimum VIL and VIH levels
VIH(AC)
VIH(AC)
IH(DC)
V
VIH(DC)
VREF + AC noise
VREF + DC error
VREF
- DC error
VREF - AC noise
V IL(DC)
VIL(DC)
IL(AC)
V
VIL(AC)
VSS
VSS - 0.35V
NOTE 1 Numbers reflect typical values.
NOTE 2 For CA[9:0], CK, , and , VDD stands for VDDCA. For DQ, DM, DQS, , and ODT, VDD stands for VDDQ.
NOTE 3 For CA[9:0], CK, , and , VSS stands for VSS. For DQ, DM, DQS, , and ODT, VSS stands for VSS.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
AC and DC Logic Input Levels for Differential Signals
Differential AC Swing Time and “time above ac-level” tDVAC
tDVAC
VIHDIFF(AC) MIN
VIHDIFF(DC) MIN
CK -
DQS -
0.0
VILDIFF(DC) MAX
VILDIFF(AC) MAX
half cycle
tDVAC
time
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Differential swing requirements for clock (CK - ) and strobe (DQS - )
For CK and , VREF = VREFCA(DC); For DQS and , VREF = VREFDQ(DC)
Differential AC and DC Input Levels
Value
Symbol
Parameter
Unit Notes
Min
2 x (VIH(dc) - VRef
Note 3
Max
Note 3
Differential input high
Differential input low
Differential input high ac
Differential input low ac
)
V
V
V
V
1
1
2
2
VIHdiff(dc)
VILdiff(dc)
VIHdiff(ac)
VILdiff(ac)
2 x (VIL(dc) - VRef
)
2 x (VIH(ac) - VRef
)
Note 3
Note 3
2 x (VIL(ac) - VRef)
NOTE 1 Used to define a differential signal slew-rate. For CK - use VIH/VIL(dc) of CA and VREFCA; for DQS - , use
VIH/VIL(dc) of DQs and VREFDQ
;
if a reduced dc-high or dc-low level is used for a signal group, then the reduced
level applies also here.
NOTE 2 For CK - use VIH/VIL(ac) of CA and VREFCA; for DQS - , use VIH/VIL(ac) of DQs and VREFDQ
;
if a reduced
ac-high or ac-low level is used for a signal group, then the reduced level applies also here.
NOTE 3 These values are not defined, however the single-ended signals CK, , DQS, and need to be within the
respective limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for overshoot and
undershoot. Refer to Overshoot and Undershoot Specifications.
NOTE 4 For CK and , VRef = VRefCA(DC). For DQS and , VRef = VRefDQ(DC)
.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Allowed time before ringback tDVAC for Strobe (DQS - )
tDVAC [ps]
tDVAC [ps]
tDVAC [ps]
@ |VIH/Ldiff(ac)| =
270mV 1866Mbps
@ |VIH/Ldiff(ac)| =
300mV 1600Mbps
@ |VIH/Ldiff(ac)| =
Slew Rate
[V/ns]
300mV 1333Mbps
min
40
40
39
36
33
29
21
21
max
─
min
48
48
46
43
40
35
27
27
max
─
min
58
58
56
53
50
45
37
37
max
─
> 8.0
8.0
─
─
─
7.0
─
─
─
6.0
─
─
─
5.0
─
─
─
4.0
─
─
─
3.0
─
─
─
< 3.0
─
─
─
Allowed time before ringback tDVAC for Clock (CK - )
tDVAC [ps]
tDVAC [ps]
tDVAC [ps]
@ |VIH/Ldiff(ac)| =
270mV 1866Mbps
@ |VIH/Ldiff(ac)| =
300mV 1600Mbps
@ |VIH/Ldiff(ac)| =
Slew Rate
[V/ns]
300mV 1333Mbps
min
40
40
39
36
33
29
21
21
max
─
min
48
48
46
43
40
35
27
27
max
─
min
58
58
56
53
50
45
37
37
max
─
> 8.0
8.0
─
─
─
7.0
─
─
─
6.0
─
─
─
5.0
─
─
─
4.0
─
─
─
3.0
─
─
─
< 3.0
─
─
─
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQS, , or ) has also to comply with certain requirements for
single-ended signals. The applicable AC levels for CA and DQ differ by speed bin.
CK and shall meet V
DQS, shall meet V
/ V
in every half-cycle.
SEH(ac)min
SEL(ac)max
/ V
in every half-cycle preceeding and following a valid transition.
SEH(ac)min
SEL(ac)max
Note that the applicable ac-levels for CA and DQ’s are different per speed-bin.
VSEH(AC)
VSEH(AC)max
CK,
DQS, or
VSEL(AC)max
VSEL(AC)
Note that while CA and DQ signal requirements are with respect to Vref, the single-ended components of differential
signals have a requirement with respect to VDDQ/2 for DQS, and VDDCA/2 for CK, ; this is nominally the same.
The transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended components
of differential signals the requirement to reach VSEL(ac)max, VSEH(ac)min has no bearing on timing, but adds a restriction on
the common mode characteristics of these signals (See tables: Single-Ended AC and DC Input Levels for CA and
Inputs; Single-Ended AC and DC Input Levels for DQ and DM).
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Single-ended levels for CK, DQS, ,
Value
Symbol
Parameter
Unit
Notes
Min
Max
V
V
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
Single-ended high-level for strobes
Single-ended high-level for CK,
Single-ended low-level for strobes
Single-ended low-level for CK,
Single-ended high-level for strobes
Single-ended high-level for CK,
Single-ended low-level for strobes
Single-ended low-level for CK,
(VDDQ / 2) + 0.150
Note 3
VSEH(AC150)
(VDDCA / 2) + 0.150
Note 3
Note 3
(VDDQ / 2) - 0.150
V
V
V
V
VSEL(AC150)
VSEH(AC135)
VSEL(AC135)
Note 3
(VDDCA / 2) - 0.150
Note 3
(VDDQ / 2) + 0.135
(VDDCA / 2) + 0.135
Note 3
Note 3
(VDDQ / 2) - 0.135
(VDDCA / 2) - 0.135
V
V
Note 3
NOTE 1 For CK, use VSEH/VSEL(ac) of CA; for strobes (DQS0, , DQS1, , DQS2, , DQS3, ) use
VIH/VIL(ac) of DQs.
NOTE 2 VIH(ac)/VIL(ac) for DQs is based on VREFDQ; VSEH(ac)/VSEL(ac) for CA is based on VREFCA
;
if a reduced ac-high or ac-low
level is used for a signal group, then the reduced level applies also here
NOTE 3 These values are not defined, however the single-ended signals CK, , DQS0, , DQS1, , DQS2, ,
DQS3, need to be within the respective limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well as the
limitations for overshoot and undershoot. Refer to Overshoot and Undershoot Specifications.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross
point voltage of differential input signals (CK, and DQS, ) must meet the requirements. The differential input cross
point voltage VIX is measured from the actual cross point of true and complement signals to the midlevel between of VDD
and VSS.
VDDCA or VDDQ
,
VDDCA/2 or
VDDQ/2
VIX
VIX
VIX
CK, DQS
VSS
Value
Symbol
VIXCA
Parameter
Unit
mV
Notes
1,2
Min
Max
Differential Input Cross Point Voltage
relative to VDDCA/2 for CK,
- 120
120
Differential Input Cross Point Voltage
relative to VDDQ/2 for DQS,
- 120
120
mV
1,2
VIXDQ
NOTE 1 The typical value of VIX(AC) is expected to be about 0.5 × VDD of the transmitting device, and VIX(AC) is expected to
track variations in VDD. VIX(AC) indicates the voltage at which differential input signals must cross.
NOTE 2 For CK and , VRef = VRefCA(DC). For DQS and , VRef = VRefDQ(DC)
.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Slew Rate Definitions for Differential Input Signals
Differential Input Slew Rate Definition
Measured
Description
Defined by
from
to
Differential input slew rate for rising edge
(CK - and DQS - ).
VILdiffmax
VIHdiffmin
[VIHdiffmin - VILdiffmax] / DeltaTRdiff
[VIHdiffmin - VILdiffmax] / DeltaTFdiff
Differential input slew rate for falling edge
(CK - and DQS - ).
VIHdiffmin
VILdiffmax
NOTE 1 The differential signal (i.e. CK - and DQS - ) must be linear between these thresholds.
Differential Input Slew Rate Definition for CK, , DQS, and
Delta TRdiff
VIH, diff, min
0
VIL, diff, max
Delta TFdiff
time
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
AC and DC Output Measurement Levels
Single Ended AC and DC Output Levels
Symbol
Parameter
Value
Unit Notes
VOH(DC)
DC output high measurement level (for IV curve linearity)
0.9 x VDDQ
V
V
1
2
VOL(DC)
ODT disabled
0.1 x VDDQ
DC output low measurement level
(for IV curve linearity)
ODT enabled
VDDQ x [0.1 + 0.9 x
(RON / (RTT + RON))]
VOL(DC)
V
3
VOH(AC)
VOL(AC)
AC output high measurement level (for output slew rate )
AC output low measurement level (for output slew rate )
VREFDQ + 0.12
V
V
VREFDQ - 0.12
Min
Max
-5
5
uA
uA
Output Leakage current (DQ, DM, DQS, )
(DQ, DQS, are disabled; 0V ≤ VOUT ≤ VDDQ
IOZ
NOTE 1 IOH = -0.1mA.
NOTE 2 IOL = 0.1mA.
NOTE 3 The minimum value is derived when using RTT,min and RON,max (±30% uncalibrated, ±15% calibrated).
Differential AC and DC Output Levels
Symbol
VOHdiff(AC)
VOLdiff(AC)
Parameter
Value
Unit Notes
AC differential output high measurement level (for output SR)
AC differential output low measurement level (for output SR)
+ 0.20 x VDDQ
- 0.20 x VDDQ
V
V
1
2
NOTE 1 IOH = -0.1mA.
NOTE 2 IOL = 0.1mA
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Single Ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and
measured between VOL(AC) and VOH(AC) for single ended signals.
Single-ended Output Slew Rate Definition
Measured
Description
Defined by
from
to
Single-ended output slew rate for rising edge
Single-ended output slew rate for falling edge
VOL(AC)
VOH(AC)
[VOH(AC) - VOL(AC)] / DeltaTRse
[VOH(AC) - VOL(AC)] / DeltaTFse
VOH(AC)
VOL(AC)
NOTE Output slew rate is verified, and may not be subject to production test.
Delta TRse
VOH(AC)
Vref
VOL(AC)
Delta TFse
time
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4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Single-ended Output Slew Rate
Value
Units
Parameter
Symbol
Min1
1.5
Max2
SRQse
4.0
V/ns
Single-ended Output Slew Rate (RON = 40 +/- 30%)
Output slew-rate matching Ratio (Pull-up to Pull-down)
0.7
1.4
Description: SR: Slew Rate; Q: Query Output (like in DQ, which stands for Data-in, Query-Output); se: Single-ended Signals
NOTE 1 Measured with output reference load.
NOTE 2 The ratio of pull-up to pull-down slew rate is specified for the same temperature and voltage, over the entire
temperature and voltage range. For a given output, it represents the maximum difference between pull-up and
pull-down drivers due to process variation.
NOTE 3 The output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC)
.
NOTE 4 Slew rates are measured under average SSO conditions, with 50% of DQ signals per data byte switching.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured
between VOLdiff(AC) and VOHdiff(AC) for differential signals.
Differential Output Slew Rate Definition
Measured
Description
Defined by
from
to
Differential output slew rate for rising edge
Differential output slew rate for falling edge
VOLdiff(AC)
VOHdiff(AC)
[VOHdiff(AC) - VOLdiff(AC)] / DeltaTRdiff
[VOHdiff(AC) - VOLdiff(AC)] / DeltaTFdiff
VOHdiff(AC)
VOLdiff(AC)
NOTE 1 Output slew rate is verified, and may not be subject to production test.
Delta TRdiff
VOH, diff(AC)
0
VOL, diff(AC)
Delta TFdiff
time
Differential Output Slew Rate
Value
Parameter
Symbol
Units
Min
Max
SRQdiff
3.0
8.0
V/ns
Differential Output Slew Rate (RON = 40 +/- 30%)
Description: SR: Slew Rate; Q: Query Output (like in DQ, which stands for Data-in, Query-Output); diff: Differential Signals
NOTE 1 Measured with output reference load.
NOTE 2 The output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC)
.
NOTE 3 Slew rates are measured under normal SSO conditions, with 50% of DQ signals per data byte switching.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Overshoot and Undershoot Specifications
AC Overshoot/Undershoot Specification
Parameter
Units
1333
1600/1866
Maximum peak amplitude allowed for overshoot area.
Maximum peak amplitude allowed for undershoot area.
Maximum area above VDD.
Max
Max
Max
Max
0.35
0.35
V
V
0.12
0.12
0.10
0.10
V-ns
V-ns
Maximum area below VSS.
NOTE 1 VDD stands for VDDCA for CA[9:0], CK, , , and CKE. VDD stands for VDDQ for DQ, DM, ODT, DQS, and .
NOTE 2 VSS stands for VSS for CA[9:0], CK, , , and CKE. VSS stands for VSS for DQ, DM, ODT, DQS, and .
NOTE 3 Maximum peak amplitude values are referenced from actual VDD and VSS values.
NOTE 4 Maximum area values are referenced from maximm operating VDD and VSS values.
Overshoot and Undershoot Definition
Maximum Amplitude
Overshoot Area
V
V
DD
Time (ns)
SS
Undershoot Area
Maximum Amplitude
NOTE 1 VDD = VDDCA for CA[9:0], CK, , , and CKE. VDD = VDDQ for DQ, DM, DQS, , and ODT.
NOTE 2 VSS = VSS for CA[9:0], CK, , , and CKE. VSS = VSS for DQ, DM, DQS, , and ODT.
NOTE 3 Absolute maximum requirements apply.
NOTE 4 Maximum peak amplitude values are referenced from actual VDD and VSS values.
NOTE 5 Maximum area values are referenced from maximum operating VDD and VSS values.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Output buffer characteristics
HSUL_12 Driver Output Timing Reference Load
These ‘Timing Reference Loads’ are not intended as a precise representation of any particular system environment or a
depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools
to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions,
generally one or more coaxial transmission lines terminated at the tester electronics.
LPDDR3
SDRAM
VREF
0.5 x VDDQ
Rload = 50
Output
VTT = 0.5 x VDDQ
Cload= 5pF
NOTE 1 All output timing parameter values (tDQSCK, tDQSQ, tHZ, tRPRE, etc.) are reported with respect to this reference
load. This reference load is also used to report slew rate.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
ODT Levels and I-V Characteristics
On-Die Termination effective resistance, RTT, is defined by mode register MR11[1:0]. ODT is applied to the DQ, DM, and
DQS/ pins. A functional representation of the on-die termination is shown in the figure below.
RTT is defined by the following formula:
RTTPU = (VDDQ - VOut) / | IOut
|
ODT
VDDQ
IPU
to other
circuitry
VDDQ - VOUT
RTTPU
IOUT
DQ
VOUT
VSS
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4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Input/output capacitance
Parameter
Symbol
CCK
Min
0.5
0
Max
1.2
Units
pF
Notes
1,2
Input capacitance, CK and
Input capacitance delta, CK and
0.15
1.1
pF
1,2,3
1,2,4
1,2,5
1,2,6,7
1,2,7,8
1,2,7,9
1,2
CDCK
CI
Input capacitance, all other input-only pins
Input capacitance delta, all other input-only pins
Input/output capacitance, DQ, DM, DQS,
Input/output capacitance delta, DQS,
Input/output capacitance delta, DQ, DM
Input/output capacitance ZQ Pin
0.5
-0.20
1.0
0
pF
0.20
1.8
pF
CDI
pF
CIO
0.2
pF
CDDQS
CDIO
CZQ
-0.25
0
0.25
2.0
pF
pF
(TOPER ;VDDQ = 1.14-1.3V; VDDCA = 1.14-1.3V; VDD1 = 1.7-1.95V, VDD2 = 1.14-1.3V)
NOTE 1 This parameter applies to die device only (does not include package capacitance).
NOTE 2 This parameter is not subject to production test. It is verified. The capacitance is measured according to JEP147
(Procedure for measuring input capacitance using a vector network analyzer (VNA) with VDD1, VDD2, VDDQ, VSS, VSS,
VSS applied and all other pins floating.
NOTE 3 Absolute value of CCK - C
NOTE 4 CI applies to , CKE, CA0-CA9, ODT.
NOTE 5 CDI = CI - 0.5 * (CCK + C
.
)
NOTE 6 DM loading matches DQ and DQS.
NOTE 7 MR3 I/O configuration DS OP3-OP0 = 0001B (34.3 typical)
NOTE 8 Absolute value of CDQS and C
.
NOTE 9 CDIO = CIO - 0.5 * (CDQS + C) in byte-lane.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
IDD Specification Parameters and Test Conditions
IDD Measurement Conditions
The following definitions are used within the IDD measurement tables unless stated otherwise:
LOW: VIN ≤ VIL(DC) MAX
HIGH: VIN ≥ VIH(DC) MIN
STABLE: Inputs are stable at a HIGH or LOW level
SWITCHING: See following 3 tables.
Definition of Switching for CA Input Signals
Switching for CA
CK
(RISING) /
CK
(FALLING) /
CK
(RISING) /
CK
(FALLING) /
CK
(RISING) /
CK
(FALLING) /
CK
(RISING) /
CK
(FALLING) /
(FALLING)
(RISING)
(FALLING)
(RISING)
(FALLING)
(RISING)
(FALLING)
(RISING)
Cycle
N
N+1
HIGH
N+2
HIGH
N+3
HIGH
HIGH
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
NOTE 1 must always be driven HIGH.
NOTE 2 50% of CA bus is changing between HIGH and LOW once per clock for the CA bus.
NOTE 3 The above pattern (N, N+1, N+2, N+3...) is used continuously during IDD measurement for IDD values that
require SWITCHING on the CA bus.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Definition of Switching for IDD4R
Clock Cycle
Clock
CKE
Command
CA[0:2]
CA[3:9]
All DQ
Number
N
Rising
Falling
Rising
Falling
Rising
Falling
Rising
Falling
Rising
Falling
Rising
Falling
Rising
Falling
Rising
Falling
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
Read_Rising
Read_Falling
NOP
HLH
LLL
LLL
LLL
LLL
LLL
LLL
HLH
HLH
LHH
HHH
HHH
HHH
HHH
HHH
HLH
LHLHLHL
LLLLLLL
LLLLLLL
LLLLLLL
LLLLLLL
LLLLLLL
LLLLLLL
HLHLLHL
HLHLLHL
HHHHHHH
HHHHHHH
HHHHHHH
HHHHHHH
HHHHHHH
HHHHHHH
LHLHLHL
L
L
H
L
H
H
H
L
H
H
H
L
L
L
H
L
N
H
H
H
H
H
H
L
N + 1
N + 1
N + 2
N + 2
N + 3
N + 3
N + 4
N + 4
N + 5
N + 5
N + 6
N + 6
N + 7
N + 7
NOP
NOP
NOP
NOP
NOP
Read_Rising
Read_Falling
NOP
L
H
H
H
H
H
H
NOP
NOP
NOP
NOP
NOP
NOTE 1 Data strobe (DQS) is changing between HIGH and LOW every clock cycle.
NOTE 2 The above pattern (N, N+1...) is used continuously during IDD measurement for IDD4R
.
Definition of Switching for IDD4W
Clock Cycle
Clock
CKE
Command
CA[0:2]
CA[3:9]
All DQ
Number
Rising
Falling
Rising
Falling
Rising
Falling
Rising
Falling
Rising
Falling
Rising
Falling
Rising
Falling
Rising
Falling
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
N
Write_Rising
Write_Falling
NOP
HLL
LLL
LLL
LLL
LLL
LLL
LLL
HLL
HLL
LHH
HHH
HHH
HHH
HHH
HHH
HLL
LHLHLHL
LLLLLLL
LLLLLLL
LLLLLLL
LLLLLLL
LLLLLLL
LLLLLLL
HLHLLHL
HLHLLHL
HHHHHHH
HHHHHHH
HHHHHHH
HHHHHHH
HHHHHHH
HHHHHHH
LHLHLHL
L
L
H
L
H
H
H
L
H
H
H
L
L
L
H
L
N
H
H
H
H
H
H
L
N + 1
N + 1
N + 2
N + 2
N + 3
N + 3
N + 4
N + 4
N + 5
N + 5
N + 6
N + 6
N + 7
N + 7
NOP
NOP
NOP
NOP
NOP
Write_Rising
Write_Falling
NOP
L
H
H
H
H
H
H
NOP
NOP
NOP
NOP
NOP
NOTE 1 Data strobe (DQS) is changing between HIGH and LOW every clock cycle.
NOTE 2 Data masking (DM) must always be driven LOW.
NOTE 3 The above pattern (N, N+1...) is used continuously during IDD measurement for IDD4W
.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
IDD Specifications
IDD values are for the entire operating voltage range, and all of them are for the entire standard range.
IDD Specification Parameters and Operating Conditions
Notes 1, 2, 3 apply for all values.
Parameter/Condition
Symbol
Power Supply
Notes
Operating one bank active-precharge current:
tCK =tCK (MIN); tRC = tRC (MIN); CKE is HIGH; is HIGH between
valid commands; CA bus inputs are switching; Data bus inputs are
stable; ODT is disabled
IDD01
IDD02
VDD1
VDD2
IDD0in
VDDCA, VDDQ
4
4
4
4
4
IDD2P1
IDD2P2
VDD1
VDD2
Idle power-down standby current:
tCK = tCK (MIN); CKE is LOW; is HIGH; All banks are idle; CA bus
inputs are switching; Data bus inputs are stable; ODT is disabled
IDD2P,in
IDD2PS1
IDD2PS2
VDDCA, VDDQ
VDD1
Idle power-down standby current with clock stop:
CK= LOW, = HIGH; CKE is LOW; is HIGH; All banks are
idle; CA bus inputs are stable; Data bus inputs are stable;
ODT is disabled
VDD2
IDD2PS,in
VDDCA, VDDQ
IDD2N1
IDD2N2
VDD1
VDD2
Idle non-power-down standby current:
tCK = tCK (MIN); CKE is HIGH; is HIGH; All banks are idle; CA bus
inputs are switching; Data bus inputs are stable; ODT is disabled
IDD2N,in
IDD2NS1
IDD2NS2
VDDCA, VDDQ
VDD1
Idle non-power-down standby current with clock stopped:
CK = LOW; = HIGH; CKE is HIGH; is HIGH;
All banks are idle; CA bus inputs are stable; Data bus inputs are stable;
ODT is disabled
VDD2
IDD2NS,in
VDDCA, VDDQ
IDD3P1
IDD3P2
VDD1
VDD2
Active power-down standby current:
tCK = tCK (MIN); CKE is LOW; is HIGH; One bank is active; CA bus
inputs are switching; Data bus inputs are stable; ODT is disabled
IDD3P,in
IDD3PS1
IDD3PS2
IDD3PS,in
IDD3N1
IDD3N2
IDD3N,in
IDD3NS1
IDD3NS2
IDD3NS,in
IDD4R1
VDDCA, VDDQ
VDD1
4
4
4
4
Active power-down standby current with clock stop:
CK = LOW, = HIGH; CKE is LOW; is HIGH; One bank is active;
CA bus inputs are stable; Data bus inputs are stable;ODT is disabled
VDD2
VDDCA, VDDQ
VDD1
Active non-power-down standby current:
tCK = tCK (MIN); CKE is HIGH; is HIGH; One bank is active; CA bus
inputs are switching; Data bus inputs are stable; ODT is disabled
VDD2
VDDCA, VDDQ
VDD1
Active non-power-down standby current with clock stopped:
CK = LOW, = HIGH; CKE is HIGH; is HIGH; One bank is active;
CA bus inputs are stable; Data bus inputs are stable; ODT is disabled
VDD2
VDDCA, VDDQ
VDD1
Operating burst READ current:
IDD4R2
VDD2
tCK = tCK (MIN); is HIGH between valid commands; One bank is
active; BL = 8; RL = RL (MIN); CA bus inputs are switching; 50% data
change each burst transfer; ODT is disabled
IDD4R,in
IDD4RQ
IDD4W1
IDD4W2
VDDCA
VDDQ
5
4
Operating burst WRITE current:
VDD1
tCK = tCK (MIN); is HIGH between valid commands; One bank is
active; BL = 8; WL = WL (MIN); CA bus inputs are switching; 50% data
change each burst transfer; ODT is disabled
VDD2
IDD4W,in
VDDCA, VDDQ
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Parameter/Condition
Symbol
Power Supply
Notes
All-bank REFRESH burst current:
IDD51
IDD52
VDD1
VDD2
tCK = tCK (MIN); CKE is HIGH between valid commands; tRC =
tRFCab (MIN); Burst refresh; CA bus inputs are switching; Data bus
inputs are stable; ODT is disabled
IDD5IN
VDDCA, VDDQ
4
4
4
All-bank REFRESH average current:
IDD5AB1
IDD5AB2
VDD1
VDD2
tCK = tCK (MIN); CKE is HIGH between valid commands; tRC = tREFI;
CA bus inputs are switching; Data bus inputs are stable; ODT is
disabled
IDD5AB,in
VDDCA, VDDQ
Per-bank REFRESH average current:
IDD5PB1
IDD5PB2
VDD1
VDD2
tCK = tCK (MIN); CKE is HIGH between valid commands; tRC =
tREFI/8; CA bus inputs are switching; Data bus inputs are stable; ODT
is disabled
IDD5PB,in
VDDCA, VDDQ
IDD61
IDD62
IDD6IN
VDD1
VDD2
6, 7
6, 7
4,7
Self refresh current (TC ≦ +85˚C):
CK = LOW, = HIGH; CKE is LOW; CA bus inputs are stable; Data
bus inputs are stable; Maximum 1x self refresh rate; ODT is disabled
VDDCA, VDDQ
NOTE 1
NOTE 2
NOTE 3
NOTE 4
NOTE 5
NOTE 6
Published IDD values are the maximum of the distribution of the arithmetic mean.
ODT disabled: MR11[2:0] = 000B.
IDD current specifications are tested after the device is properly initialized.
Measured currents are the summation of VDDQ and VDDCA
.
Guaranteed by design with output load = 5 pF and RON = 40 ohm.
The 1x self refresh rate is the rate at which the device is refreshed internally during self refresh, before going into the
elevated temperature range.
NOTE 7
NOTE 8
This is the general definition that applies to full-array SELF REFRESH.
Published IDD values of DDP can support x32 and x16 I/O configuration.
IDD6 Partial Array Self-Refresh Current
Parameter
Full Array
1/2 Array
Unit
A
A
I
DD6 Partial Array
Self-Refresh Current
1/4 Array
1/8 Array
A
A
NOTE 1 IDD6 currents are measured using bank-masking only.
NOTE 2 IDD values published are the maximum of the distribution of the arithmetic mean.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
IDD Specifications
1866
Unit
DDP
Parameter
Condition
Symbol
Power Supply
SDP
15
IDD01
IDD02
VDD1
VDD2
30
Operating one bank
active-precharge
current
mA
μA
70
140
28
IDD0in
VDDCA, VDDQ
VDD1
14
IDD2P1
600
800
130
600
800
130
2
1200
1600
260
1200
1600
260
4
Idle power-down
standby current
IDD2P2
VDD2
IDD2P,in
IDD2PS1
IDD2PS2
IDD2PS,in
IDD2N1
IDD2N2
IDD2N,in
IDD2NS1
IDD2NS2
IDD2NS,in
IDD3P1
VDDCA, VDDQ
VDD1
Idle power-down
standby current with
clock stop
μA
VDD2
VDDCA, VDDQ
VDD1
Idle non-power-down
standby current
mA
mA
VDD2
24
48
VDDCA, VDDQ
VDD1
13
26
1.7
10
3.4
20
Idle non-power-down
standby current with
clock stopped
VDD2
VDDCA, VDDQ
VDD1
6
12
μA
μA
μA
μA
μA
μA
1000
7500
160
1300
7500
160
2
2000
15000
320
2600
15000
320
4
Active power-down
standby current
IDD3P2
VDD2
IDD3P,in
IDD3PS1
IDD3PS2
IDD3PS,in
IDD3N1
IDD3N2
IDD3N,in
IDD3NS1
IDD3NS2
IDD3NS,in
IDD4R1
IDD4R2
IDD4R,in
IDD4W1
IDD4W2
IDD4W,in
VDDCA, VDDQ
VDD1
Active power-down
standby current with
clock stop
VDD2
VDDCA, VDDQ
VDD1
Active
mA
mA
mA
non-power-down
standby current
VDD2
25
50
VDDCA, VDDQ
VDD1
13
26
2
4
Active
non-power-down
standby current with
clock stopped
VDD2
20
40
VDDCA, VDDQ
VDD1
6
12
3
6
Operating burst READ
current
VDD2
320
12
640
24
VDDCA
VDD1
3
6
Operating burst
WRITE current
VDD2
320
640
100
mA
VDDCA, VDDQ
50
58
Version 1.4
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NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
1866
Unit
DDP
Parameter
Condition
Symbol
Power Supply
SDP
20
IDD51
VDD1
VDD2
40
All-bank REFRESH
burst current
mA
mA
mA
IDD52
150
13
300
26
IDD5IN
VDDCA, VDDQ
VDD1
IDD5AB1
5
10
All-bank REFRESH
average current
IDD5AB2
VDD2
25
50
IDD5AB,in
VDDCA, VDDQ
VDD1
14
28
IDD5PB1
5
10
Per-bank REFRESH
average current
IDD5PB2
VDD2
25
50
IDD5PB,in
VDDCA, VDDQ
VDD1
13
26
IDD61 (full Array)
IDD62 (full Array)
IDD6IN (full Array)
IDD61 (1/2 Array)
IDD62 (1/2 Array)
IDD6IN (1/2 Array)
IDD61 (1/4 Array)
IDD62 (1/4 Array)
IDD6IN (1/4 Array)
IDD61 (1/8 Array)
IDD62 (1/8 Array)
IDD6IN (1/8 Array)
1000
4000
150
950
2300
150
900
1500
150
850
1200
150
2000
8000
300
1900
4600
300
1800
3000
300
1700
2400
300
Self refresh current
(Full Array;
VDD2
TC ≦ +85˚C)
VDDCA, VDDQ
VDD1
Self refresh current
(1/2 Array;
VDD2
TC ≦ +85˚C)
VDDCA, VDDQ
VDD1
μA
Self refresh current
(1/4 Array;
VDD2
TC ≦ +85˚C)
VDDCA, VDDQ
VDD1
Self refresh current
(1/8 Array;
VDD2
TC ≦ +85˚C)
VDDCA, VDDQ
59
Version 1.4
Nanya Technology Corp.
02/2018
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NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Electrical Characteristic and AC Timing
Clock Specification
The specified clock jitter is a random jitter with Gaussian distribution. Input clocks violating minimum or maximum values
may result in device malfunction.
Definitions and Calculations
Symbol
Description
Calculation
Notes
The average clock period across any consecutive
200-cycle window. Each clock period is calculated
from rising clock edge to rising clock edge.
Unit tCK(avg) represents the actual clock average
tCK(avg) of the input clock under operation. Unit nCK
represents one clock cycle of the input clock,
tCK(avg) and nCK
counting from actual clock edge to actual clock edge.
tCK(avg) can change no more than ±1% within a
100-clock-cycle window, provided that all jitter and
timing specifications are met.
The absolute clock period, as measured from one
rising clock edge to the next consecutive rising clock
edge. tCK(abs) is not subject to production test.
tCK(abs)
tCH(avg)
The average HIGH pulse width, as calculated across
any 200 consecutive HIGH pulses.
The average LOW pulse width, as calculated across
any 200 consecutive LOW pulses.
tCL(avg)
The single-period jitter defined as the largest
deviation of any signal tCK from tCK(avg). tJIT(per)
is not subject to production test.
tJIT(per)
tJIT(per),act
The actual clock jitter for a given system.
The specified clock period jitter allowance.
tJIT(per),allowed
The absolute difference in clock periods between two
consecutive clock cycles. tJIT(cc) defines the
cycle-to-cycle jitter. tJIT(cc) is not subject to
production test.
tJIT(cc)
60
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Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Symbol
Description
Calculation
Notes
The cumulative error across n multiple consecutive
cycles from tCK(avg).
tERR(nper)
The actual cumulative error over n cycles for a given
tERR(nper),act
system.
The specified cumulative error allowance over n
tERR(nper),allowed
tERR(nper),min
cycles.
The minimum tERR(nper).
The maximum tERR(nper).
tERR(nper),max
tJIT(duty),min =
MIN((tCH(abs),min – tCH(avg),min),
(tCL(abs),min – tCL(avg),min)) × tCK(avg)
tJIT(duty),max =
Defined with tCH jitter and tCL jitter. tCH jitter is the
largest deviation of any single tCH from tCH(avg).
tCL jitter is the largest deviation of any single tCL
from tCL(avg).
tJIT(duty)
MAX((tCH(abs),max – tCH(avg),max),
(tCL(abs),max – tCL(avg),max)) × tCK(avg)
Notes:
1. Not subject to production testing.
2. Using these equations, tERR(nper) tables can be generated for each tJIT(per),act value.
Definition for tCK(abs), tCH(abs) and tCL(abs)
These parameters are specified per their average values, however, it is understood that the following relationship
between the average timing and the absolute instantaneous timing holds at all times.
Symbol
Parameter
Minimum
Unit
ps1
Absolute clock period
tCK(avg),min + tJIT(per),min
tCK(abs)
tCH(avg),min + tJIT(duty)2,min/ tCK(avg)min
tCL(avg),min + tJIT(duty) 2,min / tCK(avg)min
tCK(avg)
tCK(avg)
Absolute clock HIGH pulse width
Absolute clock LOW pulse width
tCH(abs)
tCL(abs)
Notes:
1. tCK(avg),min is expressed in ps for this table.
2. tJIT(duty),min is a negative value.
61
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NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Period Clock Jitter
LPDDR3 devices can tolerate some clock period jitter without core timing parameter derating. This section describes
device timing requirements with clock period jitter (tJIT(per)) in excess of the values found in the AC timing table.
Calculating cycle time derating and clock cycle derating are also described.
Clock Period Jitter Effects on Core Timing Parameters(tRCD, tRP, tRTP, tWR, tWRA, tWTR,
tRC,tRAS, tRRD, tFAW )
Core timing parameters extend across multiple clock cycles. Period clock jitter impacts these parameters when
measured in numbers of clock cycles. Within the specification limits, the device is characterized and verified to support
tnPARAM = RU[tPARAM / tCK(avg)]. During device operation where clock jitter is outside specification limits, the
number of clocks or tCK(avg), may need to be increased based on the values for each core timing parameter.
Cycle Time Derating for Core Timing Parameters
For a given number of clocks (tnPARAM), for each core timing parameter, average clock period (tCK(avg)) and actual
cumulative period error (tERR(tnPARAM),act) in excess of the allowed cumulative period error
(tERR(tnPARAM),allowed), the equation below calculates the amount of cycle time de-rating (in ns) required if the
equation results in a positive value for a core timing parameter.
A cycle time derating analysis should be conducted for each core timing parameter. The amount of cycle time derating
required is the maximum of the cycle time de-ratings determined for each individual core timing parameter.
Clock Cycle Derating for Core Timing Parameters
For a given number of clocks (tnPARAM) for each core timing parameter, clock cycle de-rating should be specified with
amount of period jitter (tJIT(per)).
For a given number of clocks (tnPARAM), for each core timing parameter, average clock period (tCK(avg)) and actual
cumulative period error (tERR(tnPARAM),act) in excess of the allowed cumulative period error (tERR(tnPARAM),allowed), the
equation below calculates the clock cycle derating (in clocks) required if the equation results in a positive value for a
core timing parameter.
A clock cycle de-rating analysis should be conducted for each core timing parameter.
62
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Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Clock Jitter Effects on Command/Address Timing Parameters(tISCA, tIHCA, tISCS,
tIHCS,tISCKE,tIHCKE, tISb, tIHb, tISCKEb, tIHCKEb)
These parameters are measured from a command/address signal (CKE, , CA0 - CA9) transition edge to its respective
clock signal (CK/) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), as the
setup and hold are relative to the clock signal crossing that latches the command/address. Regardless of clock jitter values,
these values shall be met.
Clock Jitter Effects on READ Timing Parameters
tRPRE
When the device is operated with input clock jitter, tRPRE must be derated by the actual period jitter( tJIT(per),act,max) of
the input clock that exceeds the allowed period jitter( tJIT(per),allowed,max.). Output de-ratings are relative to the input
clock.
tJITperact,max – tJITper,allowed,max
tRPREminderated
tCK(avg)
For example, if the measured jitter into a LPDDR3-1600 device has tCK(avg) = 1250ps,tJIT(per),act,min = –92ps, and
tJIT(per),act,max = +134ps, then
tRPRE,min,derated = 0.9 - (tJIT(per),act,max - tJIT(per),allowed,max)/tCK(avg) = 0.9 - (134 - 100)/1250=0.8728 tCK(avg)
tLZ(DQ), tHZ(DQ), tDQSCK, tLZ(DQS), tHZ(DQS)
These parameters are measured from a specific clock edge to a data signal transition (DMn or DQm, where: n = 0, 1, 2, or
3; and m = DQ[31:0]), and specified timings must be met with respect to that clock edge. Therefore, they are not affected
by the amount of clock jitter applied (for instance, tJIT(per)).
tQSH, tQSL
These parameters are affected by duty cycle jitter which is represented by tCH(abs)min and tCL(abs)min. These
parameters determine absolute Data-Valid Window (DVW) at the LPDDR3 device pin.
Absolute min DVW @ LPDDR3 device pin =
min{ ( tQSH(abs)min – tDQSQmax) , ( tQSL(abs)min – tDQSQmax ) }
This minimum DVW shall be met at the target frequency regardless of clock jitter.
tRPST
tRPST is affected by duty cycle jitter, represented by tCL(abs). Therefore, tRPST(abs)min can be specified by tCL(abs)min.
tRPST(abs)min = tCL(abs)min - 0.05 = tQSL(abs)min
63
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NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Clock Jitter Effects on WRITE Timing Parameters
tDS, tDH
These parameters are measured from a data signal (DMn or DQm, where n = 0, 1, 2, 3; and m = DQ[31:0]) transition edge
to its respective data strobe signal (DQSn, n = 0,1,2,3) crossing. The specification values are not affected by the
amount of tJIT(per) applied, as the setup and hold times are relative to the clock signal crossing that latches the
command/address. Regardless of clock jitter values, these values must be met.
tDSS, tDSH
These parameters are measured from a data strobe signal (DQSx, x) crossing to its respective clock signal (CK, )
crossing. The specification values are not affected by the amount of tJIT(per)) applied, as the setup and hold times are
relative to the clock signal crossing that latches the command/address. Regardless of clock jitter values, these values must
be met.
tDQSS
This parameter is measured from a data strobe signal (DQSx, x) crossing to the subsequent clock signal (CK/)
crossing. When the device is operated with input clock jitter, this parameter needs to be de-rated by the actual period
jitter tJIT(per),act of the input clock in excess of the allowed period jitter tJIT(per),allowed.
tJITperact,min – tJITper,allowed,min
tDQSSminderated
tCK(avg)
tJITperact,max – tJITper,allowed,max
tDQSSmaxderated
tCK(avg)
For example, if the measured jitter into an LPDDR3-1600 device has tCK(avg) = 1250ps,tJIT(per),act,min = -92ps, and
tJIT(per),act,max = +134ps, then:
tDQSS,(min,derated) = 0.75 - (tJIT(per),act,min - tJIT(per),allowed,min)/tCK(avg) = 0.75 - (-93 + 100)/1250 = 0.7444 tCK(avg), and
tDQSS,(max,derated) = 1.25 - (tJIT(per),act,max - tJIT(per),allowed,max)/tCK(avg) = 1.25 - (134 - 100)/1250 = 1.2228 tCK(avg).
64
Version 1.4
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NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
REFRESH Requirements
LPDDR3 Refresh Requirement Parameters
Parameter
Symbol
4 Gb (SDP) 8 Gb (DDP)
Unit
-
Number of Banks
8
32
Refresh Window: Tcase ≦ 85°C
Refresh Window: 1/2-Rate Refresh
Refresh Window: 1/4-Rate Refresh
Required number of REFRESH commands (min)
tREFW
tREFW
tREFW
R
ms
ms
ms
-
16
8
8,192
3.9
average time between REFRESH
commands (for reference only)
Tcase ≦ 85°C
REFab
REFpb
tREFI
s
s
ns
ns
tREFIpb
tRFCab
tRFCpb
0.4875
Refresh Cycle time
130
60
130
60
Per Bank Refresh Cycle time
LPDDR3 Read and Write Latencies
Parameter
Value
Unit
MHz
Max. Clock Frequency
Max. Data Rate
166
333
6
400
800
2.5
6
533
1066
1.875
8
600
667
733
1466
1.36
11
800
933
1866
1.071
14
1200
1.67
9
1333
1.5
10
6
1600
1.25
12
Mbps
Average Clock Period
Read Latency
ns
31
tCK(avg)
tCK(avg)
tCK(avg)
Write Latency (Set A)
Write Latency (Set B)2
11
3
4
5
6
6
8
11
3
4
5
8
9
9
11
NOTE 1 RL=3/WL=1 setting is an optional feature. Refer to MR0 OP<7>.
NOTE 2 Write Latency (Set B) support is an optional feature. Refer to MR0 OP<6>.
NOTE 3 For this operation, please confirm notices with NTC.
65
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NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
AC Timing
Notes 1–4 apply to all parameters. Notes begin below table.
Data Rate
Unit
Min/
Max
Parameter
Symbol
1866
1600
1333
667
1.5
Clock frequency
Average clock period
Clock Timing
fCK
–
–
933
800
MHz
ns
tCK(avg)
1.071
1.25
MIN
MAX
MIN
MAX
MIN
MIN
MAX
MIN
MAX
MIN
MAX
0.45
0.55
0.45
0.55
Average HIGH pulse width
tCH(avg)
tCK(avg)
Average LOW pulse width
Absolute clock period
tCL(avg)
tCK(abs)
tCH(abs)
tCK(avg)
ns
tCK(avg) MIN + tJIT(per) MIN
0.43
0.57
0.43
0.57
Absolute clock HIGH pulse width
tCK(avg)
Absolute clock LOW pulse width
tCL(abs)
tCK(avg)
-60
-70
70
-80
tJIT(per),
allowed
Clock period jitter (with supported jitter)
ps
ps
60
80
Maximum Clock Jitter between two consecutive clock cycles
(with allowed jitter)
tJIT(cc),
allowed
MAX
MIN
120
140
160
min((tCH(abs),min -tCH(avg),min),
(tCL(abs),min - tCL(avg),min)) × tCK(avg)
tJIT(duty),
allowed
Duty cycle jitter (with supported jitter)
ps
max((tCH(abs),max -tCH(avg),max),
MAX
(tCL(abs),max - tCL(avg),max)) × tCK(avg)
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
-88
88
-103
103
-118
118
tERR(2per),
allowed
Cumulative errors across 2 cycles
Cumulative errors across 3 cycles
Cumulative errors across 4 cycles
Cumulative errors across 5 cycles
Cumulative errors across 6 cycles
Cumulative errors across 7 cycles
Cumulative errors across 8 cycles
Cumulative errors across 9 cycles
Cumulative errors across 10 cycles
Cumulative errors across 11 cycles
Cumulative errors across 12 cycles
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
-105
105
-117
117
-126
126
-133
133
-139
139
-145
145
-150
150
-154
154
-158
158
-161
161
-122
122
-140
140
tERR(3per),
allowed
-136
136
-155
155
tERR(4per),
allowed
-147
147
-168
168
tERR(5per),
allowed
-155
155
-177
177
tERR(6per),
allowed
-163
163
-186
186
tERR(7per),
allowed
-169
169
-193
193
tERR(8per),
allowed
-175
175
-200
200
tERR(9per),
allowed
-180
180
-205
205
tERR(10per),
allowed
-184
184
-210
210
tERR(11per),
allowed
-188
188
-215
215
tERR(12per),
allowed
66
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NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Data Rate
Unit
Min/
Max
Parameter
Symbol
1866
1600
1333
Clock Timing
tERR(nper),allowed MIN = (1 + 0.68ln(n))
×tJIT(per), allowed MIN
MIN
tERR(nper),
allowed
Cumulative errors across n = 13, 14, 15…, 19, 20 cycles
ps
tERR (nper), allowed MAX = (1 + 0.68ln(n))
×tJIT(per), allowed MAX
MAX
ZQ Calibration Parameters
Initialization calibration time
Long calibration time
tZQINIT
tZQCL
MIN
MIN
MIN
MIN
1
µs
ns
ns
ns
360
90
Short calibration time
tZQCS
Calibration RESET time
READ Parameters5
tZQRESET
max(50ns,3nCK)
MIN
MAX
MAX
2500
5500
DQS output access time from CK/
tDQSCK
ps
265
593
733
165
DQSCK delta short
tDQSCKDS
190
435
525
115
220
511
ps
ps
DQSCK delta medium
tDQSCKDM MAX
DQSCK delta long
tDQSCKDL
tDQSQ
tQSH
MAX
MAX
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MAX
614
ps
DQS-DQ skew
135
ps
DQS output HIGH pulse width
DQS output LOW pulse width
DQ/DQS output hold time from DQS
READ preamble
tCH(abs) - 0.05
tCL(abs) - 0.05
min(tQSH, tQSL)
0.9
tCK(avg)
tCK(avg)
ps
tQSL
tQH
tRPRE
tCK(avg)
tCK(avg)
ps
READ postamble
tRPST
0.3
DQS Low-Z from clock
tLZ(DQS)
tLZ(DQ)
tHZ(DQS)
tHZ(DQ)
tDQSCK (MIN) - 300
tDQSCK,(MIN) - 300
tDQSCK,(MAX) - 100
DQ Low-Z from clock
ps
DQS High-Z from clock
ps
DQ High-Z from clock
WRITE Parameters5
MAX tDQSCK,(MAX) + (1.4 × tDQSQ,(MAX))
ps
175
175
DQ and DM input hold time (VREF based)
DQ and DM input setup time (VREF based)
DQ and DM input pulse width
tDH
tDS
MIN
MIN
MIN
MIN
MAX
MIN
MIN
MIN
MIN
MIN
MIN
130
130
150
150
0.35
0.75
1.25
0.4
ps
ps
tDIPW
tCK(avg)
Write command to 1st DQS latching transition
tDQSS
tCK(avg)
DQS input high-level width
DQS input low-level width
tDQSH
tDQSL
tDSS
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
0.4
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Write postamble
0.2
tDSH
0.2
tWPST
tWPRE
0.4
Write preamble
0.8
CKE Input Parameters
CKE minimum pulse width (HIGH and LOW pulse width)
CKE input setup time
tCKE
tISCKE
tIHCKE
tCPDED
MIN
MIN
MIN
MIN
max(7.5ns,3nCK)
ns
0.25
0.25
2
tCK(avg)
tCK(avg)
tCK(avg)
CKE input hold time
Command path disable delay
Command Address Input Parameters5
Address and control input setup time
Address and control input hold time
input setup time
175
175
290
290
tISCA
tIHCA
tISCS
tIHCS
MIN
MIN
MIN
MIN
130
130
230
230
150
150
270
270
ps
ps
ps
ps
input hold time
67
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NTC Proprietary
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Data Rate
Unit
Min/
Max
Parameter
Symbol
1866
1600
1333
Command Address Input Parameters5
Address and control input pulse width
input pulse width
tIPWCA
tIPWCS
MIN
MIN
0.35
0.7
tCK(avg)
tCK(avg)
Boot Parameters (10 MHz–55 MHz) 16, 17, 18
MAX
MIN
MIN
MIN
MIN
MIN
MIN
MAX
MAX
100
18
Clock cycle time
tCKb
ns
CKE input setup time
tISCKEb
tIHCKEb
tISb
2.5
2.5
1150
1150
2
ns
ns
ps
ps
CKE input hold time
Address and control input setup time
Address and control input hold time
tIHb
DQS output data access time from CK/
tDQSCKb
tDQSQb
ns
ns
10
Data strobe edge to output data edge
Mode Register Parameters
1.2
MODE REGISTER WRITE command period
MODE REGISTER READ command period
tMRW
tMRR
MIN
MIN
10
4
tCK(avg)
tCK(avg)
Additional time after tXP has expired
until the MRR command may be issued
tMRRI
MIN
tRCD(min)
ns
Core Parameters 19
10
6
READ latency
RL
WL
WL
MIN
MIN
MIN
14
8
12
tCK(avg)
tCK(avg)
tCK(avg)
WRITE latency(Set A)
WRITE latency(Set B)
6
8
11
9
tRAS + tRPab
(with all-bank precharge)
tRAS + tRPpb
ACTIVATE-to- ACTIVATE command period
tRC
MIN
ns
(with per-bank precharge)
CKE minimum pulse width during SELF REFRESH (low pulse
width during SELF REFRESH)
tCKESR
MIN
max(15ns,3nCK)
ns
SELF REFRESH exit to next valid command delay
tXSR
tXP
MIN
MIN
MIN
MIN
max(tRFCab + 10ns,2nCK)
max(7.5ns,3nCK)
4
ns
ns
Exit power- down to next valid command delay
CAS-to-CAS delay
tCCD
tRTP
tCK(avg)
ns
Internal READ to PRECHARGE command delay
max(7.5ns,4nCK)
RAS-to-CAS delay
tRCD (typ)
MIN
MIN
MIN
max(18ns,3nCK)
max(18ns,3nCK)
max(21ns,3nCK)
ns
ns
ns
Row precharge time (single bank)
tRPpb (typ)
Row precharge time (all banks)
Row active time
tRPpab (typ)
MIN
MAX
MIN
MIN
MIN
MIN
MIN
max(42ns,3nCK)
70
ns
µs
ns
ns
ns
ns
µs
tRAS
WRITE recovery time
tWR
tWTR
tRRD
tFAW
tDPD
max(15ns,4nCK)
max(7.5ns,4nCK)
max(10ns,2nCK)
max(50ns,8nCK)
500
Internal WRITE-to- READ command delay
Active bank A to active bank B
Four-bank ACTIVATE window
Minimum deep power- down time
68
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Data Rate
Unit
Min/
Max
Parameter
Symbol
1866
1600
1333
ODT Parameters
MIN
MAX
MIN
MAX
1.75
3.5
Asynchronous RTT turn-on dely from ODT input
Asynchronous RTT turn-off delay from ODT input
Automatic RTT turn-on delay after READ data
tODTon
tODToff
ns
ns
1.75
3.5
tDQSCK + 1.4 × tDQSQ,max +
tCK(avg,min)
tAODTon
tAODToff
tODTd
MAX
MIN
MIN
MAX
ps
ps
ns
ns
Automatic RTT turn-off delay after READ data
RTT disable delay from power down, self-refresh, and deep
power down entry
tDQSCK,min - 300
12
12
RTT enable delay from power down and self refresh exit
CA Training Parameters
tODTe
First CA calibration command after CA calibration mode is
programmed
tCAMRD
MIN
20
tCK(avg)
First CA calibration command after CKE is LOW
tCAENT
tCAEXT
MIN
MIN
MIN
MIN
10
10
10
10
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
CA caibration exit command after CKE is HIGH
CKE LOW after CA calibration mode is programmed
tCACKEL
tCACKEH
CKE HIGH after the last CA calibration results are driven.
Data out delay after CA training calibration command is
programmed
tADR
MAX
20
ns
MRW CA exit command to DQ tri-state
tMRZ
MIN
MIN
3
ns
CA calibration command to CA calibration command delay
tCACD
RU(tADR+2 × tCK)
tCK(avg)
Write Leveling Parameters
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MIN
MIN
MAX
25
─
40
─
0
DQS/ delay after write leveling mode is programmed
tWLDQSEN
ns
ns
ns
First DQS/ edge after write leveling mode is programmed tWLMRD
Write leveling output delay
tWLO
20
205
205
Write leveling hold time
Write leveling setup time
tWLH
tWLS
150
150
175
ps
ps
175
MAX (14ns, 10nCK)
─
Mode register set command delay
tMRD
ns
Temperature Derating
DQS output access time from CK/ (derated)
RAS-to-CAS delay (derated)
tDQSCK
tRCD
tRC
MAX
MIN
MIN
MIN
MIN
MIN
5620
ps
ns
ns
ns
ns
ns
tRCD + 1.875
tRC + 1.875
tRAS + 1.875
tRP + 1.875
tRRD + 1.875
ACTIVATE-to-ACTIVATE command period (derated)
Row active time (derated)
tRAS
tRP
Row precharge time (derated)
Active bank A to active bank B (derated)
tRRD
NOTE 1 Frequency values are for reference only. Clock cycle time (tCK) is used to determine device capabilities.
NOTE 2 All AC timings assume an input slew rate of 2V/ns for single-ended signals.
NOTE 3 Measured with 4 V/ns differential CK/ slew rate and nominal VIX.
NOTE 4 All timing and voltage measurements are defined at the ball.
NOTE 5 READ, WRITE, and input setup and hold values are referenced to VREF.
NOTE 6 tDQSCKDS is the absolute value of the difference between any two tDQSCK measurements (in a byte lane) within
a contiguous sequence of bursts in a 160ns rolling window. tDQSCKDS is not tested and is guaranteed by design.
Temperature drift in the system is <10˚C/s. Values do not include clock jitter.
69
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Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
NOTE 7 tDQSCKDM is the absolute value of the difference between any two tDQSCK measurements (in a byte lane) within
a 1.6μs rolling window. tDQSCKDM is not tested and is guaranteed by design. Temperature drift in the system
is <10˚C/s. Values do not include clock jitter.
NOTE 8 tDQSCKDL is the absolute value of the difference between any two tDQSCK measurements (in a byte lane) within
a 32ms rolling window. tDQSCKDL is not tested and is guaranteed by design. Temperature drift in the system
is <10˚C/s. Values do not include clock jitter.
NOTE 9 For LOW-to-HIGH and HIGH-to-LOW transitions, the timing reference is at the point when the signal crosses
the transition threshold (VTT). tHZ and tLZ transitions occur in the same access time (with respect to clock)
as valid data transitions. These parameters are not referenced to a specific voltage level but to the time
when the device output is no longer driving (for tRPST, tHZ(DQS) and tHZ(DQ)), or begins driving (for tRPRE,
tLZ(DQS) and tLZ(DQ)). The figure below shows a method to calculate the point when the device is no longer
driving tHZ(DQS) and tHZ(DQ) or begins driving tLZ(DQS) and tLZ(DQ) by measuring the signal at two different
voltages. The actual voltage measurement points are not critical as long as the calculation is consistent.
NOTE 10 Output Transition Timing
NOTE 11 The parameters tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) are defined as single-ended. The timing parameters
tRPRE and tRPST are determined from the differential signal DQS/.
NOTE 12 Measured from the point when DQS/ begins driving the signal, to the point when DQS/ begins driving
the first rising strobe edge.
NOTE 13 Measured from the last falling strobe edge of DQS/ to the point when DQS/ finishes driving the signal.
NOTE 14 CKE input setup time is measured from CKE reaching a HIGH/LOW voltage level to CK/ crossing.
NOTE 15 CKE input hold time is measured from CK/ crossing to CKE reaching a HIGH/LOW voltage level.
NOTE 16 Input setup/hold time for signal (CA[9:0], ).
NOTE 17 To ensure device operation before the device is configured, a number of AC boot timing parameters are defined
in this table. Boot parameter symbols have the letter b appended (for example, tCK during boot is tCKb).
NOTE 18 Mobile LPDDR3 devices set some mode register default values upon receiving a RESET (MRW) command, as specified
in Mode Register Definition.
NOTE 19 The output skew parameters are measured with default output impedance settings using the reference load.
NOTE 20 The minimum tCK column applies only when tCK is greater than 6ns.
70
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
CA and Setup, Hold and Derating
For all input signals (CA and ) the total tI (setup time) and tIH (hold time) required is calculated by adding the data sheet
S
tIS(base) and tIH(base) value (see tIS/tIH Base Table) to the tIS and tIH derating value (see tIS/tIH Derating Table)
respectively. Example: tIS (total setup time) = tIS(base) + tIS.
Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first
crossing of VIH(ac)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing
of VREF(dc) and the first crossing of Vil(ac)max. If the actual signal is always earlier than the nominal slew rate line between
shaded ‘VREF(dc) to ac region’, use nominal slew rate for derating value (see following typical slew rate Figure of tIS). If the
actual signal is later than the nominal slew rate line anywhere between shaded ‘VREF(dc) to ac region’, the slew rate of a
tangent line to the actual signal from the ac level to dc level is used for derating value (see following angent line figure of
tIS).
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first
crossing of VREF(dc). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of
VIH(dc)min and the first crossing of VREF(dc). If the actual signal is always later than the nominal slew rate line between shaded
‘dc to VREF(dc) region’, use nominal slew rate for derating value (see following typical slew rate Figure of tIH). If the actual
signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to VREF(dc) region’, the slew rate of a tangent
line to the actual signal from the dc level to VREF(dc) level is used for derating value (see following angent line figure of tIH).
For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC (see table of required tVAC for
CA).
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac)
at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac)
.
For slew rates in between the values listed in derating Table, the derating values may be obtained by linear interpolation.
These values are typically not subject to production test. They are verified.
71
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Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
CA Setup and Hold Base-Values
Data Rate
unit [ps]
reference
1866
-
1600
75
1333
100
-
tISCA(base)
tISCA(base)
tIHCA(base)
VIH/L(ac) =
VIH/L(ac) =
VIH/L(dc) =
VREF(dc) +/-150mV
VREF(dc) +/-135mV
VREF(dc) +/-100mV
62.5
80
-
100
125
NOTE 1 AC/DC referenced for 2V/ns CA slew rate and 4V/ns differential CK- slew rate.
Setup and Hold Base-Values
Data Rate
unit [ps]
reference
1866
-
1600
195
-
1333
215
-
tISCS(base)
tISCS(base)
tIHCS(base)
VIH/L(ac) =
VIH/L(ac) =
VIH/L(dc) =
VREF(dc) +/-150mV
VREF(dc) +/-135mV
VREF(dc) +/-100mV
162.5
180
220
240
NOTE 1 AC/DC referenced for 2V/ns slew rate and 4V/ns differential CK- slew rate.
Derating values tIS/tIH - ac/dc based AC150
tISCA, tIHCA, tISCS, tIHCS derating in [ps] AC/DC based
AC150 Threshold -> VIH(ac)=VREF(dc)+150mV, VIL(ac)=VREF(dc)-150mV
DC100 Threshold -> VIH(dc)=VREF(dc)+100mV, VIL(dc)=VREF(dc)-100mV
CK, Differential Slew Rate
8.0V/ns
7.0V/ns
6.0V/ns
5.0V/ns
4.0V/ns
3.0V/ns
tIS
38
-
tIH
25
-
tIS
38
25
tIH
25
17
tIS
38
25
tIH
25
17
tIS
38
25
tIH
25
17
tIS
38
25
tIH
25
17
tIS
-
38
tIH
-
29
4.0
3.0
CA,
Slew
rate
2.0
1.5
-
-
-
-
-
-
-
-
0
-
0
-
0
0
0
0
13
13
-4
(V/ns)
-25
-17
-25
-17
-12
NOTE 1 Cell contents shaded in pink are defined as ‘not supported’.
Derating values tIS/tIH - ac/dc based AC135
tISCA, tIHCA, tISCS, tIHCS derating in [ps] AC/DC based
AC135 Threshold -> VIH(ac)=VREF(dc)+135mV, VIL(ac)=VREF(dc)-135mV
DC100 Threshold -> VIH(dc)=VREF(dc)+100mV, VIL(dc)=VREF(dc)-100mV
CK, Differential Slew Rate
8.0V/ns
7.0V/ns
6.0V/ns
5.0V/ns
4.0V/ns
3.0V/ns
tIS
34
-
tIH
25
-
tIS
34
23
tIH
25
17
tIS
34
23
tIH
25
17
tIS
34
23
tIH
25
17
tIS
34
23
tIH
25
17
tIS
-
34
tIH
-
29
4.0
3.0
CA,
Slew
rate
2.0
1.5
-
-
-
-
-
-
-
-
0
-
0
-
0
0
0
0
11
13
-4
(V/ns)
-23
-17
-23
-17
-12
NOTE 1 Cell contents shaded in pink are defined as ‘not supported’.
72
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NTC Proprietary
Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Required time tVAC above VIH(ac) {below VIL(ac)} for valid transition for CA
tVAC at 135mV (ps)
1866Mb/s
tVAC at 150mV (ps)
1600Mb/s
tVAC at 150mV (ps)
1333Mb/s
Min
Slew Rate
(V/ns)
Min
40
40
39
36
33
29
21
21
Max
─
Min
48
48
46
43
40
35
27
27
Max
─
Max
─
>4.0
4.0
3.5
3.0
2.5
2.0
1.5
<1.5
58
58
56
53
50
45
37
37
─
─
─
─
─
─
─
─
─
─
─
─
─
─
─
─
─
─
─
─
─
73
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Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Typical Slew Rate and tVAC – tIS for CA and Relative to Clock
CK
VDDCA
VIH(AC)min
VIH(DC)min
VREF(DC)
VIL(DC)max
VIL(AC)max
tVAC
VSS
TF
TR
VREF(dc)
VREF(dc)
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Typical Slew Rate – tIH for CA and Relative to Clock
CK
VDDCA
VIH(AC)min
VIH(DC)min
VREF(DC)
VIL(DC)max
VIL(AC)max
VSS
TR
TF
VREF(dc)
VREF(dc)
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Tangent Line – tIS for CA and Relative to Clock
CK
VDDCA
VIH(AC)min
VIH(DC)min
VREF(DC)
VIL(DC)max
VIL(AC)max
VSS
REF(dc)
V
REF(dc)
V
76
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Tangent Line – tIH for CA and Relative to Clock
CK
VDDCA
VIH(AC)min
VIH(DC)min
VREF(DC)
VIL(DC)max
VIL(AC)max
VSS
VREF(dc)
REF(dc)
V
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Data Setup, Hold and Slew Rate Derating
For all input signals (DQ, DM) the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet
tDS(base) and tDH(base) value (see the following tDS/tDH base table) to thetDS andtDH (see tDS/tDH derating table)
derating value respectively. Example: tDS (total setup time) = tDS(base) +tDS.
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first
crossing of VIH(ac)min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing
of VREF(dc) and the first crossing of VIL(ac)max (see following typical slew rate Figure of tDS). If the actual signal is always
earlier than the nominal slew rate line between shaded ‘VREF(dc) to ac region’, use nominal slew rate for derating value. If
the actual signal is later than the nominal slew rate line anywhere between shaded ‘VREF(dc) to ac region’, the slew rate of
a tangent line to the actual signal from the ac level to dc level is used for derating value(see following angent line figure of
tDS).
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the
first crossing of VREF(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last
crossing of VIH(dc)min and the first crossing of VREF(dc) (see following typical slew rate Figure of tDH). If the actual signal is
always later than the nominal slew rate line between shaded ‘dc level to VREF(dc) region’, use nominal slew rate for derating
value. If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to VREF(dc) region’, the
slew rate of a tangent line to the actual signal from the dc level to VREF(dc) level is used for derating value (see following
angent line figure of tDH).
For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC (see table of required tVAC for
DQ/DM).
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac)
at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac)
For slew rates in between the values listed in the tables the derating values may be obtained by linear interpolation.
These values are typically not subject to production test. They are verified.
.
Data Setup and Hold Base-Values (>400MHz, 1V/ns Slew Rate)
Data Rate
unit [ps]
reference
1866
-
1600
75
1333
100
-
tDS(base)
tDS(base)
tDH(base)
VIH/L(ac) =
VIH/L(ac) =
VIH/L(dc) =
VREF(dc) +/- 150mV
VREF(dc) +/- 135mV
VREF(dc) +/- 100mV
62.5
80
-
100
125
NOTE 1 AC/DC referenced for 2V/ns DQ, DM slew rate and 4V/ns differential DQS- slew rate and nominal VIX.
78
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Level: Property
LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Derating values tDS/tDH - ac/dc based AC150
tDS, tDH derating in [ps] AC/DC based
AC150 Threshold -> VIH(ac)=VREF(dc)+150mV, VIL(ac)=VREF(dc)-150mV
DC100 Threshold -> VIH(dc)=VREF(dc)+100mV, VIL(dc)=VREF(dc)-100mV
DQS, Differential Slew Rate
8.0V/ns
7.0V/ns
6.0V/ns
5.0V/ns
4.0V/ns
3.0V/ns
tIS
38
-
tIH
25
-
tIS
38
25
tIH
25
17
tIS
38
25
tIH
25
17
tIS
38
25
tIH
25
17
tIS
38
25
tIH
25
17
tIS
-
38
tIH
-
29
4.0
3.0
DQ, DM
Slew rate
(V/ns)
2.0
1.5
-
-
-
-
-
-
-
-
0
-
0
-
0
0
0
0
13
13
-4
-25
-17
-25
-17
-12
NOTE 1 Cell contents shaded in pink are defined as ‘not supported’.
Derating values tDS/tDH - ac/dc based AC135
tDS, tDH derating in [ps] AC/DC based
AC135 Threshold -> VIH(ac)=VREF(dc)+135mV, VIL(ac)=VREF(dc)-135mV
DC100 Threshold -> VIH(dc)=VREF(dc)+100mV, VIL(dc)=VREF(dc)-100mV
DQS, Differential Slew Rate
8.0V/ns
7.0V/ns
6.0V/ns
5.0V/ns
4.0V/ns
3.0V/ns
tIS
34
-
tIH
25
-
tIS
34
23
tIH
25
17
tIS
34
23
tIH
25
17
tIS
34
23
tIH
25
17
tIS
34
23
tIH
25
17
tIS
-
34
tIH
-
29
4.0
3.0
DQ, DM
Slew rate
(V/ns)
2.0
1.5
-
-
-
-
-
-
-
-
0
-
0
-
0
0
0
0
11
13
-4
-23
-17
-23
-17
-12
NOTE 1 Cell contents shaded in pink are defined as ‘not supported’.
Required time tVAC above VIH(ac) {below VIL(ac)} for valid transition for DQ, DM
tVAC at 135mV (ps)
1866Mb/s
tVAC at 150mV (ps)
1600Mb/s
tVAC at 150mV (ps)
1333Mb/s
Slew Rate
(V/ns)
Min
40
40
39
36
33
29
21
21
Max
─
Min
48
48
46
43
40
35
27
27
Max
─
Min
58
58
56
53
50
45
37
37
Max
─
>4.0
4.0
3.5
3.0
2.5
2.0
1.5
<1.5
─
─
─
─
─
─
─
─
─
─
─
─
─
─
─
─
─
─
─
─
─
79
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Typical Slew Rate and tVAC – tDS for DQ Relative to Strobe
DQS
VDDQ
VIH(AC)min
VIH(DC)min
VREF(DC)
VIL(DC)max
VIL(AC)max
VSS
VREF(dc)
REF(dc)
V
80
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Typical Slew Rate – tDH for DQ Relative to Strobe
DQS
VDDQ
VIH(AC)min
VIH(DC)min
VREF(DC)
VIL(DC)max
VIL(AC)max
VSS
VREF(dc)
VREF(dc)
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Tangent Line – tDS for DQ with Respect to Strobe
DQS
VDDQ
VIH(AC)min
VIH(DC)min
VREF(DC)
VIL(DC)max
VIL(AC)max
VSS
VREF(dc)
VREF(dc)
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Tangent Line – tDH for DQ with Respect for Strobe
DQS
VDDQ
VIH(AC)min
VIH(DC)min
VREF(DC)
VIL(DC)max
VIL(AC)max
VSS
VREF(dc)
VREF(dc)
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Basic Functionality
Mobile LPDDR3 is a high-speed SDRAM internally configured as an 8-bank memory device.
LPDDR3 uses a double data rate architecture on the command/address (CA) bus to reduce the number of input pins in the
system. The 10-bit CA bus is used to transmit command, address, and bank information. Each command uses one clock
cycle, during which command information is transferred on both the rising and falling edges of the clock.
LPDDR3 uses a double data rate architecture on the DQ pins to achieve high-speed operation. The double data rate
architecture is essentially an 8n prefetch architecture with an interface designed to transfer two data bits per DQ every
clock cycle at the I/O pins.
A single read or write access for LPDDR3 effectively consists of a single 8n-bit-wide, one-clock-cycle data transfer at the
internal SDRAM core and eight corresponding nbit- wide, one-half-clock-cycle data transfers at the I/O pins. Read and
write accesses to the device are burst oriented; accesses start at a selected location and continue for a programmed
number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVATE command followed by a READ or WRITE command. The address and
BA bits registered coincident with the ACTIVATE command are used to select the row and bank to be accessed. The
address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column
location for the burst access.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Power-Up, Initialization, and Power-Off
LPDDR3 devices must be powered up and initialized in a predefined manner. Power-up and initialization by means other
than those specified will result in undefined operation.
Voltage Ramp and Device Initialization
The following sequence must be used to power up the device. Unless specified otherwise, this procedure is mandatory
and applies to devices.
1) Voltage Ramp:
While applying power (after Ta), CKE must be held LOW (≤ 0.2 × VDDCA), and all other inputs must be between VILmin
and VIHmax. The device outputs remain at High-Z while CKE is held LOW. Following the completion of the voltage ramp
(Tb), CKE must be maintained LOW. DQ, DM, DQS and voltage levels must be between VSS and VDDQ during
voltage ramp to avoid latch up. CK, , , and CA input levels must be between VSS and VDDCA during voltage ramp
to avoid latch-up. Voltage ramp power supply requirements are provided below.
Voltage Ramp Conditions
After…
Applicable Conditions
VDD1 must be greater than VDD2 (200 mV)
VDD1 and VDD2 must be greater than VDDCA (200 mV)
VDD1 and VDD2 must be greater than VDDQ (200 mV)
VREF must always be less than all other supply voltages
Ta is reached
Notes:
1. Ta is the point when any power supply first reaches 300 mV.
2. Noted conditions apply between Ta and power-down (controlled or uncontrolled).
3. Tb is the point at which all supply and reference voltages are within their defined operating ranges.
4. Power ramp duration tINIT0 (Tb – Ta) must not exceed 20ms.
5. The voltage difference between any of VSS pins must not exceed 100 mV.
Beginning at Tb, CKE must remain LOW for at least tINIT1, after which CKE can be asserted HIGH. The clock must be
stable at least tINIT2 prior to the first CKE LOW-to-HIGH transition (Tc). CKE, , and CA inputs must observe setup and
hold requirements (tIS, tIH) with respect to the first rising clock edge (as well as to subsequent falling and rising edges).
If any MRRs are issued, the clock period must be within the range defined for tCKb. MRW commands can be issued at
normal clock frequencies as long as all AC timings are met. Some AC parameters (for example, tDQSCK) could have
relaxed timings (such as tDQSCKb) before the system is appropriately configured. While keeping CKE HIGH, NOP
commands must be issued for at least tINIT3 (Td). The ODT input signal may be in undefined state until tIS before CKE is
registered HIGH. When CKE is registered HIGH, the ODT input signal shall be statically held at either LOW or HIGH. The
ODT input signal remains static until the power up initialization sequence is finished, including the expiration of tZQINIT.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
2) RESET Command:
After tINIT3 is satisfied, the MRW RESET command must be issued (Td). An optional PRECHARGE ALL command can
be issued prior to the MRW RESET command. Wait at least tINIT4 while keeping CKE asserted and issuing NOP
commands.
3) MRRs and Device Auto Initialization (DAI) Polling:
After tINIT4 is satisfied (Te), only MRR commands and power-down entry/exit commands are supported. After Te, CKE
can go LOW in alignment with power-down entry and exit specifications. Use the MRR command to poll the DAI bit and
report when device auto initialization is complete; otherwise, the controller must wait a minimum of tINIT5, or until the DAI
bit is set before proceeding. As the memory output buffers are not properly configured by Te, some AC parameters must
have relaxed timings before the system is appropriately configured. After the DAI bit (MR0, DAI) is set to zero by the
memory device (DAI complete), the device is in the idle state (Tf ). DAI status can be determined by issuing the MRR
command to MR0. The device sets the DAI bit no later than tINIT5 after the RESET command. The controller must wait at
least tINIT5 or until the DAI bit is set before proceeding.
4) ZQ Calibration:
After tINIT5 (Tf), the MRW initialization calibration (ZQ_CAL) command can be issued to the memory (MR10). This
command is used to calibrate output impedance over process, voltage, and temperature. In systems where more than one
LPDDR3 device exists on the same bus, the controller must not overlap MRW ZQ_CAL commands. The device is ready
for normal operation after tZQinit.
5) Normal Operation:
After tZQinit (Tg), MRW commands must be used to properly configure the memory (for example the output buffer drive
strength, latencies, etc.). Specifically, MR1, MR2, and MR3 must be set to configure the memory for the target frequency
and memory configuration After the initialization sequence is complete, the device is ready for any valid command. After
Tg, the clock frequency can be changed using the procedure described in the LPDDR3 specification.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Power Ramp and Initialization Sequence
Ta
Tb
Tc
Td
Te
Tf
Tg
Tf’
tINIT2
CK /
tINIT02
Supplies
tINIT3
tINIT1
PD
CKE
CA1
tINIT5
tISCKE
tZQINIT
tINIT4
CA
Valid
RESET
MRR
ZQCa
Training
DQ
tIS
Valid
Static HIGH or LOW
* Midlevel on CA bus means: valid NOP
ODT3
NOTE 1 High-Z on the CA bus indicates NOP.
NOTE 2 For tINIT values, see below table.
NOTE 3 After RESET command (time Te), RTT is disabled until ODT function is enabled by MRW to MR11 following Tg.
NOTE 4 CA Training is optional.
Initialization Timing Parameters
Symbol
Parameter
Value
Unit
min
-
max
tINIT0
tINIT1
tINIT2
tINIT3
tINIT4
tINIT51
tZQINIT
tCKb
Maximum Power Ramp Time
Minimum CKE low time after completion of power ramp
Minimum stable clock before first CKE high
Minimum idle time after first CKE assertion
Minimum idle time after Reset command
Maximum duration of Device Auto-Initialization
ZQ Initial Calibration
20
ms
ns
100
5
-
-
-
tCK
us
200
1
-
us
-
10
-
us
1
us
Clock cycle time during boot
18
100
ns
NOTE 1 If DAI bit is not read via MRR, SDRAM will be in idle state after tINIT5(max) has expired.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Initialization after RESET (without voltage ramp):
If the RESET command is issued before or after the power-up initialization sequence, the re-initialization procedure must begin at
Td.
Power-Off Sequence
The following procedure is required to power off the device. While powering off, CKE must be held LOW (≤ 0.2 × VDDCA);
all other inputs must be between VILmin and VIHmax. The device outputs remain at High-Z while CKE is held LOW.
DQ, DM, DQS, and voltage levels must be between VSS and VDDQ during the power-off sequence to avoid latch-up.
CK, , , and CA input levels must be between VSS and VDDCA during the power-off sequence to avoid latch-up.
Tx is the point where any power supply drops below the minimum value specified.
Tz is the point where all power supplies are below 300 mV. After Tz, the device is powered off.
Power Supply Conditions
Between…
Tx and Tz
Tx and Tz
Tx and Tz
Tx and Tz
Applicable Conditions
VDD1 must be greater than VDD2—200 mV
VDD1 must be greater than VDDCA—200 mV
VDD1 must be greater than VDDQ—200 mV
VREF must always be less than all other supply voltages
Notes:
1. The voltage difference between any of VSS pins must not exceed 100 mV.
Uncontrolled Power-Off Sequence
When an uncontrolled power-off occurs, the following conditions must be met:
At Tx, when the power supply drops below the minimum values specified, all power supplies must be turned off and all
power-supply current capacity must be at zero, except for any static charge remaining in the system.
After Tz (the point at which all power supplies first reach 300 mV), the device must power off. During this period, the
relative voltage between power supplies is uncontrolled. VDD1 and VDD2 must decrease with a slope lower than 0.5
V/μs between Tx and Tz. An uncontrolled power-off sequence can occur a maximum of 400 times over the life of the
device.
Power-Off Timing
Symbol
Parameter
Min
Max
Unit
tPOFF
Maximum power-off ramp time
-
2
s
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Mode Register Definition
LPDDR3 devices contain a set of mode registers used for programming device operating parameters, reading device
information and status, and for initiating special operations such as DQ calibration, ZQ calibration, and device reset.
Mode Register Assignment and Definition
Table below shows the mode registers. Each register is denoted as “R”, if it can be read but not written, “W” if it can
be written but not read, and “R/W” if it can be read and written. Mode Register Read Command shall be used to read
a register. Mode Register Write Command shall be used to write a register.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Mode Register Assignment
MR#
MA [7:0]
Function
Access OP7
OP6
OP5
OP4
RZQI
OP3
OP2
OP1
BL
OP0
DAI
0
1
00H
01H
Device Info
Device Feature1
Device Feature2
I/O Config-1
R
W
W
W
R
RL3
WL-B
(RFU)
(RFU)
nWR (for AP)
(RFU)
2
02H
WRLev WL Sel (RFU) nWRE
RL & WL
DS
3
03H
(RFU)
4
04H
Refresh Rate
Basic Config-1
Basic Config-2
Basic Config-3
Basic Config-4
Test Mode
TUF
(RFU)
Refresh Rate
5
05H
R
Manufacturer ID
Revision ID1
6
06H
R
7
07H
R
Revision ID2
8
08H
R
I/O width
Density
Type
9
09H
W
W
W
─
W
W
─
R
Vendor-Specific Test Mode
Calibration Code
10
0AH
IO Calibration
ODT
11
0BH
(RFU)
PD ctl
DQ ODT
12-15
16
0CH-0FH
10H
(Reserved)
(RFU)
PASR_BANK
PASR_Seg
PASR Bank Mask
17
11H
PASR Segment Mask
18-31
32
12H-1FH
20H
(Reserved)
(RFU)
DQ calibration pattern A
(Do Not Use)
DQ calibration pattern B
CA Training 1
CA Training 2
(Do Not Use)
CA Training 3
(Reserved)
See Data Calibration Pattern Description
33-39
40
21H-27H
28H
─
R
(DNU)
See Data Calibration Pattern Description
See MRW – CA Training Mode
See MRW – CA Training Mode
(DNU)
41
29H
W
W
─
W
─
W
─
42
2AH
43-47
48
2BH-2FH
30H
See MRW – CA Training Mode
(RFU)
49-62
63
31H-3EH
3FH
RESET
X or 0xFCh
64-255
40H-FFH
(Reserved)
(RFU)
NOTE 1 RFU bits shall be set to ‘0’ during mode register writes.
NOTE 2 RFU bits shall be read as ‘0’ during mode register reads.
NOTE 3 All mode registers that are specified as RFU or write-only shall return undefined data when read and DQS, shall
be toggled.
NOTE 4 All mode registers that are specified as RFU shall not be written.
NOTE 5 See vendor device datasheets for details on vendor-specific mode registers.
NOTE 6 Writes to read-only registers shall have no impact on the functionality of the device.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
MR0_Device Information (MA[7:0] = 00H)
MR#
0
MA [7:0]
00H
Function
Access OP7
OP6
OP5
OP4
RZQI
OP3
OP2
OP1
OP0
DAI
Device Info
R
RL3
WL-B
(RFU)
(RFU)
Feature
Register Information
Type
OP
Definition
0B: DAI complete
DAI
Device Auto-Initialization Status
Read-only
OP<0>
1B: DAI still in progress
00B: RZQ self test not supported
01B: ZQ-pin may connect to VDDCA or float
10B: ZQ-pin may short to GND
RZQI (Built in Self Test for RZQ
Information)
RZQI1-4
Read-only
OP<4:3>
11B: ZQ-pin self test completed, no error condition
detected (ZQ-pin may not connect to VDDCA or
float nor short to GND)
0B: DRAM does not support WL (Set B)
1B: DRAM supports WL (SetB)
0B: DRAM does not support
RL=3, nWR=3, WL=1
WL-B
RL3
WL (Set B) Support
RL3 Option Support
Read-only
Read-only
OP<6>
OP<7>
1B: DRAM supports
RL=3, nWR=3, WL=1
for frequencies 166
NOTE 1 RZQI, if supported, will be set upon completion of the MRW ZQ Initialization Calibration command.
NOTE 2 If ZQ is connected to VDDCA to set default calibration, OP[4:3] shall be set to 01. If ZQ is not connected to VDDCA, either
OP[4:3]=01 or OP[4:3]=10 might indicate a ZQ-pin assembly error. It is recommended that the assembly error is
corrected.
NOTE 3 In the case of possible assembly error (either OP[4:3]=01 or OP[4:3]=10 per Note 4), the LPDDR3 device will default to
factory trim settings for RON, and will ignore ZQ calibration commands. In either case, the system may not function as
intended.
NOTE 4 In the case of the ZQ self-test returning a value of 11b, this result indicates that the device has detected a resistor
connection to the ZQ pin. However, this result cannot be used to validate the ZQ resistor value or that the ZQ resistor
tolerance meets the specified limits (i.e. 240- ±1%).
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
MR1_Device Feature 1 (MA[7:0] = 01H)
MR#
1
MA [7:0]
01H
Function
Access OP7
OP6
OP5
OP4
OP3
OP2
OP1
BL
OP0
Device Feature1
W
nWR (for AP)
(RFU)
Feature
BL
Type
OP
Definition
011B: BL8 (default)
Write-only
OP<2:0>
OP<7:5>
All others: reserved
If nWRE (MR2 OP<4>) = 0:
001B: nWR=3 (default)
100B: nWR=6
110B: nWR=8
111B: nWR=9
nWR (for AP)
Write -only
If nWRE (MR2 OP<4> = 1:
000B: nWR=10
001B: nWR=11
010B: nWR=12
All others: reserved
NOTE 1 Programmed value in nWR register is the number of clock cycles which determines when to start internal precharge
operation for a write burst with AP enabled. It is determined by RU(tWR/tCK).
Burst Sequence
Burst Cycle Number and Burst Address Sequence
C2
C1
C0
BL
1
0
2
4
6
2
1
3
5
7
3
2
4
6
0
4
3
5
7
1
5
4
6
0
2
6
5
7
1
3
7
6
0
2
4
8
7
1
3
5
0B
0B
1B
1B
0B
1B
0B
1B
0B
0B
0B
0B
8
1. C0 input is not present on CA bus. It is implied zero.
2. The burst address represents C2 - C0.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
MR2_Device Feature 2 (MA[7:0] = 02H)
MR#
2
MA [7:0]
02H
Function
Access OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
Device Feature2
W
WRLev WL Sel (RFU) nWRE
RL & WL
Feature
Type
OP
Definition
If OP<6> =0 (WL Set A, default)
0001B: RL = 3 / WL = 1 (≦166 MHz)
0100B: RL = 6 / WL = 3 (≦400 MHz)
0110B: RL = 8 / WL = 4 (≦533 MHz)
0111B: RL = 9 / WL = 5 (≦600 MHz)
1000B: RL = 10 / WL = 6 (≦667 MHz, default)
1001B: RL = 11 / WL = 6 (≦733 MHz)
1010B: RL = 12 / WL = 6 (≦800 MHz)
1100B: RL = 14 / WL = 8 (≦933 MHz)
All others: reserved
RL & WL
Write-only
OP<3:0>
If OP<6> =1 (WL Set B)
0001B: RL = 3 / WL = 1 (≦166 MHz)
0100B: RL = 6 / WL = 3 (≦400 MHz)
0110B: RL = 8 / WL = 4 (≦533 MHz)
0111B: RL = 9 / WL = 5 (≦600 MHz)
1000B: RL = 10 / WL = 8 (≦667 MHz)
1001B: RL = 11 / WL = 9 (≦733 MHz)
1010B: RL = 12 / WL = 9 (≦800 MHz)
1100B: RL = 14 / WL = 11 (≦933 MHz)
All others: reserved
0B: enable nWR programming≦9
1B: enable nWR programming > 9 (default)
0B: Select WL Set A (default)
1B: Select WL Set B
nWRE
Write-only
Write-only
Write-only
OP<4>
OP<6>
OP<7>
WL Selection
WR Leveling
0B: disabled (default)
1B: enabled
NOTE 1 See MR0, OP<7>
NOTE 2 See MR0, OP<6>
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
MR3_I/O Configuration 1 (MA[7:0] = 03H)
MR#
3
MA [7:0]
03H
Function
Access OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
I/O Config-1
W
(RFU)
DS
Feature
Type
OP
Definition
0000B: reserved
0001B: 34.3typical
0010B: 40typical (default)
0011B: 48typical
0100B: 60typical
Drive Strength
Write-only
OP<3:0>
0110B: 80 typical
1001 B: 34.3 pull-down, 40Ω pull-up (240Ω termination)
1010 B: 40 pull-down, 48Ω pull-up (240Ω termination)
1011 B: 34.3 pull-down, 48Ω pull-up (120Ω termination)
All others: reserved
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
MR4_Device Temperature (MA[7:0] = 04H)
MR#
4
MA [7:0]
04H
Function
Access OP7
TUF
OP6
OP5
(RFU)
OP4
OP3
OP2
OP1
OP0
Refresh Rate
R
Refresh Rate
Feature
Type
OP
Definition
000B: SDRAM Low temperature operating limit exceeded
001B: 4x tREFI, 4x tREFIpb, 4x tREFW
010B: 2x tREFI, 2x tREFIpb, 2x tREFW
011B: 1x tREFI, 1x tREFIpb, 1x tREFW (≦85°C)
100B: reserved
Refresh Rate
Read-only
OP<2:0>
101B: 0.25x tREFI, 0.25x tREFIpb, 0.25x tREFW, no AC timing derating
110B: 0.25x tREFI, 0.25x tREFIpb, 0.25x tREFW, timing derating required
111B: SDRAM High temperature operating limit exceeded
0B: OP<2:0> value has not changed since last read of MR4.
1B: OP<2:0> value has changed since last read of MR4.
Temperature Update
Flag (TUF)
Read-only
OP<7>
NOTE 1 A mode register read from MR4 will reset OP7 to 0.
NOTE 2 OP7 is reset to 0 at power-up.
NOTE 3 If OP2 = 1, the device temperature is greater than 85˚C.
NOTE 4 OP7 is set to 1 if OP<2:0> has changed at any time since the last MR4 read.
NOTE 5 The device might not operate properly when OP<2:0> = 000b or 111b.
NOTE 6 For the specified operating temperature range and maximum operating temperature, refer to the Operating Temperature
Range table.
NOTE 7 LPDDR3 devices must be derated by adding 1.875ns to the following core timing parameters:tRCD, tRC, tRAS, tRP, and
tRRD. The tDQSCK parameter must be derated as specified in the AC Timing table. Prevailing clock frequency
specifications and related setup and hold timings remain unchanged.
NOTE 8 The recommended frequency for reading MR4 is provided in the Temperature Sensor section.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
MR5_Basic Configuration-1 (MA[7:0] = 05H)
MR#
5
MA [7:0]
05H
Function
Access OP7
OP6
OP5
OP5
OP5
OP4
OP3
OP2
OP2
OP2
OP1
OP1
OP1
OP0
OP0
OP0
Basic Config-1
R
Manufacturer ID
Feature
Manufactuer ID
Type
Read-only
OP
Definition
0000 0101B: Nanya
OP<7:0>
All Others: Reserved
MR6_Basic Configuration-2 (MA[7:0] = 06H)
MR#
6
MA [7:0]
06H
Function
Access OP7
OP6
OP4
OP3
Basic Config-2
R
Revision ID1
Feature
Revision ID1
Type
Read-only
OP
Definition
0000 0010B: C-die
OP<7:0>
All Others: Reserved
MR7_Basic Configuration-3 (MA[7:0] = 07H)
MR#
7
MA [7:0]
07H
Function
Access OP7
OP6
OP4
OP3
Basic Config-3
R
Revision ID2
Feature
Revision ID2
Type
Read-only
OP
Definition
0000 0000B: A Version
All Others: Reserved
OP<7:0>
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
MR8_Basic Configuration-4 (MA[7:0] = 08H)
MR#
8
MA [7:0]
08H
Function
Access OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
Basic Config-4
R
I/O width
Density
Type
Feature
Type
OP
Definition
11B: LPDDR3 S8
Type
Read-only
OP<1:0>
All others: Reserved
0110B: 4Gb
0111B: 8Gb
Density
Read-only
OP<5:2> 1000B: 16Gb
1001B: 32Gb
All others: Reserved
00B: x32
I/O width
Read-only
OP<7:6> 01B: x16
All others: Reserved
MR9_Test Mode (MA<7:0> = 09H)
MR#
9
MA [7:0]
09H
Function
Access OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
Test Mode
W
Vendor-Specific Test Mode
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
MR10_Calibration (MA[7:0] = 0AH)
MR#
10
MA [7:0]
0AH
Function
Access OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
IO Calibration
W
Calibration Code
Feature
Type
OP
Definition
0xFF: Calibration command after initialization
0xAB: Long calibration
Calibration Code
Write-only
OP<7:0> 0x56: Short calibration
0xC3: ZQ Reset
All Others: Reserved
NOTE 1 Host processor shall not write MR10 with “Reserved” values.
NOTE 2 The device ignores calibration commands when a reserved value is written into MR10.
NOTE 3 See AC Timing table for the calibration latency.
NOTE 4 If ZQ is connected to VSS through RZQ, either the ZQ calibration function (see MRW ZQ CALIBRATION Command)
or default calibration (through the ZQ RESET command) is supported. If ZQ is connected to VDDCA, the device
operates with default calibration and ZQ CALIBRATION commands are ignored. In both cases, the ZQ connection must
not change after power is supplied to the device.
NOTE 5 Devices that do not support calibration ignore the ZQ CALIBRATION command.
NOTE 6 The MRW ZQ Initialization Calibration command will update MR0 to indicate RZQ pin connection.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
MR11_ODT (MA[7:0] = 0BH)
MR#
11
MA [7:0]
0BH
Function
Access OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
ODT
W
(RFU)
PD ctl
DQ ODT
Feature
Type
OP
Definition
00B: Disable (Default)
01B: Reserved
10B: RZQ/2
DQ ODT1
Write-only
OP<1:0>
11B: RZQ/1
0B: ODT disabled by DRAM during power down (default)
1B: ODT enabled by DRAM during power down
PD Control
Write-only
OP<2>
NOTE 1 Depending on ballout, ODT pin may be NOT supported so ODT die pad is connected to Vss inside the package.
MR12-15_Reserved (MA[7:0] = 0CH-0FH)
MR16_PASR_BANK (MA[7:0] = 10H)
MR#
16
MA [7:0]
10H
Function
Access OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
PASR_BANK
W
PASR Bank Mask
Feature
PASR Bank Mask
Type
Write-only
OP
Definition
0B: refresh enable to the bank (= unmasked, default)
1B: refresh blocked (= masked)
OP<7:0>
OP
0
Bank Mask
XXXXXXX1
LPDDR3 SDRAM
Bank 0
1
XXXXXX1X
XXXXX1XX
XXXX1XXX
XXX1XXXX
XX1XXXXX
X1XXXXXX
1XXXXXXX
Bank 1
2
Bank 2
3
Bank 3
4
Bank 4
5
Bank 5
6
Bank 6
7
Bank 7
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
MR17_PASR_Segment (MA[7:0] = 11H)
MR#
17
MA [7:0]
11H
Function
Access OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
PASR_Seg
W
PASR Segment Mask
Feature
PASR Segment Mask
Type
OP
Definition
0B: refresh enable to the segment (=unmasked, default)
1B: refresh blocked (=masked)
Write-only
OP<7:0>
4Gb
8Gb
16Gb
32Gb
Segment
Mask
Segment
OP
R13:11
R14:12
R14:12
TBD
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
XXXXXXX1
XXXXXX1X
XXXXX1XX
XXXX1XXX
XXX1XXXX
XX1XXXXX
X1XXXXXX
1XXXXXXX
000B
001B
010B
011B
100B
101B
110B
111B
NOTE 1 Thistableindicatestherangeofrowaddressesineachmaskedsegment.Xisdonotcareforaparticular
segment.
NOTE 2 No memory present at addresses with R13=R14=HIGH. Segment masks 6 and 7 are ignored.
MR18-31_Reserved (MA[7:0] = 12H-1FH)
MR32_DQ Calibration Pattern A (MA[7:0] = 20H)
MR#
32
MA [7:0]
20H
Function
Access OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
DQ calibration pattern A
R
See Data Calibration Pattern Description
NOTE 1 Reads to MR32 return DQ Calibration Pattern “A”. See “DQ Calibration”
MR33-39_Do Not Use (MA[7:0] = 21H-27H)
MR40_DQ Calibration Pattern B (MA[7:0] = 28H)
MR#
40
MA [7:0]
28H
Function
Access OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
DQ calibration pattern B
R
See Data Calibration Pattern Description
NOTE 1 Reads to MR40 return DQ Calibration Pattern “B”. See “DQ Calibration”
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
MR41_CA Training 1 (MA[7:0] = 29H)
MR#
41
MA [7:0]
29H
Function
Access OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
CA Training 1
W
See MRW – CA Training Mode
NOTE 1 Writes to MR41 enables CA Training. See Mode Register Write - CA Training Mode
MR42_CA Training 2 (MA[7:0] = 2AH)
MR#
42
MA [7:0]
2AH
Function
Access OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
CA Training 2
W
See MRW – CA Training Mode
NOTE 1 Writes to MR42 enables CA Training. See Mode Register Write - CA Training Mode
MR43-47_Do Not Use (MA[7:0] = 2BH-2FH)
MR48_CA Training 3 (MA[7:0] = 30H)
MR#
48
MA [7:0]
30H
Function
Access OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
CA Training 3
W
See MRW – CA Training Mode
NOTE 1 Writes to MR48 enables CA Training. See Mode Register Write - CA Training Mode
MR49-62_Do Not Use (MA[7:0] = 31H-3EH)
MR63_RESET (MA[7:0] = 3FH)
MR#
63
MA [7:0]
3FH
Function
Access OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
RESET
W
X or 0xFCh
MR64-255_Reserved (MA[7:0] = 40H-FFH)
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
LPDDR3 SDRAM Truth Table
Operation or timing that is not specified is illegal, and after such an event, in order to guarantee proper operation, the
LPDDR3 device must be powered down and then restarted through the specified initialization sequence before normal
operation can continue.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Command Truth Table
Command Pins
CA pins
SDRAM
command
CKE
CA0
CA1 CA2
CA3 CA4 CA5 CA6 CA7 CA8 CA9
CK EDGE
CK(n-1) CK(n)
L
X
L
L
L
L
MA0
OP2
MA1
OP3
MA2
OP4
MA3
OP5
MA4
OP6
MA5
OP7
MRW
MRR
H
H
H
H
MA6
MA7
OP0
OP1
L
X
L
X
L
X
L
X
L
X
L
X
L
X
L
X
L
X
L
X
L
X
H
X
H
X
H
X
H
X
L
MA6
L
L
MA7
L
L
H
H
H
H
L
MA0
MA1
MA2
MA3
MA4
MA5
X
X
X
X
X
X
X
Refresh
(per bank)11
H
H
H
H
L
L
L
L
L
H
Refresh
(all bank)
H
X
Enter
Self Refresh
L
R0
H
H
R1
L
R8
R2
L
R9
R3
R10
R4
R11
R5
C1
C7
C1
C7
X
R12
R6
C2
C8
C2
C8
X
BA0
R7
BA1
R13
BA1
C10
BA1
C10
BA1
BA2
R14
BA2
C11
BA2
C11
BA2
Activate
(bank)
H
H
H
H
H
H
H
H
L
RFU
C5
RFU
C6
BA0
C9
Write
AP3
H
C3
L
C4
H
(bank)
RFU
C5
RFU
C6
BA0
C9
Read
AP3
H
C3
H
C4
L
(bank)
H
AB
BA0
Precharge
(pre bank, all bank)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
X
H
H
H
H
H
H
L
H
H
Enter
Deep Power Down
NOP
H
L
H
L
Maintain PD,
SREF, DPD (NOP)
NOP
H
L
H
L
Maintain PD,
SREF, DPD (NOP)
H
X
L
X
Enter
L
Power Down
Exit
H
PD, SREF, DPD
NOTE 1 All LPDDR3 commands are defined by states of , CA0, CA1, CA2, CA3, and CKE at the rising edge of the clock.
NOTE 2 Bank addresses BA0, BA1, BA2 (BA) determine which bank is to be operated upon.
NOTE 3 AP “high” during a READ or WRITE command indicates that an auto-precharge will occur to the bank associated with the
READ or WRITE command.
NOTE 4 “X” means “H or L (but a defined logic level)”, except when the LPDDR3 SDRAM is in PD, SREF, or DPD, in which case ,
CK/, and CA can be floated.
NOTE 5 Self refresh exit and Deep Power Down exit are asynchronous.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
NOTE 6 VREF must be between 0 and VDDQ during Self Refresh and Deep Power Down operation.
NOTE 7 CAxr refers to command/address bit “x” on the rising edge of clock.
NOTE 8 CAxf refers to command/address bit “x” on the falling edge of clock.
NOTE 9 and CKE are sampled at the rising edge of clock.
NOTE 10 The least-significant column address C0 is not transmitted on the CA bus, and is implied to be zero.
NOTE 11 AB “high”during Precharge command indicates that all bank Precharge will occur. In this case, Bank Address is
do-not-care.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
CKE Truth Table
Device
Current State3
1
1
CKEn-1 CKEn
2
Command n4
Operation n4
Device Next State
Notes
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
x
H
x
x
Maintain Active Power Down
Exit Active Power Down
Maintain Idle Power Down
Exit Idle Power Down
Active Power Down
Active
Active
Power Down
NOP
x
6,9
6,9
Idle Power Down
Idle
Idle
Power Down
H
L
H
x
NOP
x
Maintain Resetting Power Down
Exit Resetting Power Down
Maintain Deep Power Down
Exit Deep Power Down
Maintain Self Refresh
Resetting Power Down
Idle or Resetting
Deep Power Down
Power On
Resetting
Power Down
H
L
H
x
NOP
x
6,9,12
8
Deep
Power Down
H
L
H
x
NOP
x
Self Refresh
Self Refresh
H
L
H
H
H
NOP
NOP
NOP
Exit Self Refresh
Idle
7,10
Bank(s) Active
Enter Active Power Down
Enter Idle Power Down
Active Power Down
Idle Power Down
L
13
13
13
Enter
Self-Refresh
All Banks Idle
H
L
L
Enter Self Refresh
Self Refresh
H
H
H
L
L
L
Enter DPD
Enter Deep Power Down
Enter Resetting Power Down
Refer to the Command Truth Table
Deep Power Down
Resetting
H
NOP
Resetting Power Down
Other states
H
Notes:
1. “CKEn” is the logic state of CKE at clock edge n; “CKEn-1” was the logic state of CKE at previous clock edge.
2. “” is the logic state of at the clock rising edge n;
3. “Current state” is the state of the LPDDR3 device immediately prior to clock edge n.
4. “Command n” is the command registered at clock edge N, and “Operation n” is a result of “Command n”.
5. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
6. Power Down exit time (tXP) should elapse before a command other than NOP is issued.
7. Self-Refresh exit time (tXSR) should elapse before a command other than NOP is issued.
8. The Deep Power-Down exit procedure must be followed as discussed in the DPD section of the Functional Description.
9. The clock must toggle at least once during the tXP period.
10. The clock must toggle at least once during the tXSR period.
11. “X” means “Don’t care”.
12. Upon exiting Resetting Power Down, the device will return to the idle state if tINIT5 has expired.
13. In the case of ODT disabled, all DQ output shall be Hi-Z. In the case of ODT enabled, all DQ shall be terminated to VDDQ.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
State Truth Tables
The truth tables provide complementary information to the state diagram, they clarify the device behavior and the applied
restrictions when considering the actual state of all banks.
Current State Bank n – Command to Bank n
Current State
Command
Operation
Next State
Notes
Any
NOP
ACTIVATE
Refresh (Per Bank)
Refresh (All Banks)
MRW
Continue previous operation
Current State
Active
Select and activate row
Begin to refresh
Refreshing (Per Bank)
Refreshing (All Banks)
MR Writing
6
7
7
Begin to refresh
Idle
Load value to Mode Register
Read value from Mode Register
Begin Device Auto-initialization
Deactivate row(s) in bank or banks
Select column, and start read burst
Select column, and start write burst
Read value from Mode Register
Deactivate row(s) in bank or banks
Select column, and start new read burst
Select column, and start write burst
Select column, and start new write burst
Select column, and start read burst
Begin Device Auto-initialization
Read value from Mode Register
MRR
Idle / MR Reading
Resetting
Reset
7,8
Precharge
Read
Precharging
Reading
9,15
Write
Writing
Row Active
MRR
Active MR Reading
Precharging
Reading
Precharge
Read
9
10,11
10,11,12
10,11
10,11,13
7,9
Reading
Writing
Write
Writing
Write
Writing
Read
Reading
Power On
Resetting
MRW Reset
MRR
Resetting
Resetting MR Reading
Notes:
1. The table applies when both CKEn-1 and CKEn are HIGH, and after tXSR or tXP has been met, if the previous state was Power Down.
2. All states and sequences not shown are illegal or reserved.
3. Current State definitions:
State
Definition
Idle
The bank or banks have been precharged, and tRP has been met.
A row in the bank has been activated, and tRCD has been met. No data bursts or accesses and
no register accesses are in progress.
Active
Reading
Writing
A READ burst has been initiated with auto precharge disabled, and has not yet terminated.
A WRITE burst has been initiated with auto precharge disabled, and has not yet terminated.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
4. The following states must not be interrupted by any executable command. NOP commands must be applied to each positive
clock edge during these states.
Ends when
It’s met
State
Starts with
Notes
Refreshing
(per bank)
Registration of a REFRESH (per
bank) command
tRFCpb
After tRFCpb is met, the bank is in the idle state.
Refreshing
(all banks)
Registration of a REFRESH
(all bank) command
tRFCab
tMRR
tMRR
tMRR
tMRW
tRP
After tRFCab is met, the device is in the all-banks idle state.
After tMRR is met, the device is in the all-banks idle state..
After tMRR is met, the device is in the all-banks idle state.
After tMRR is met, the bank is in the active state.
Idle MR
reading
Registration of the MRR
command
Resetting MR
reading
Registration of the MRR
command
Active MR
reading
Registration of the MRR
command
Registration of the MRW
command
MR writing
After tMRW is met, the device is in the all-banks idle state.
After tRP is met, the device is in the all-banks idle state.
Precharging
all
Registration of a PRECHARGE
ALL command
5. The states listed below must not be interrupted by a command issued to the same command. NOP commands or supported
commands to the other bank should be issued on any clock edge occurring during these states.
Ends when
It’s met
State
Starts with
Notes
Precharging
Registration of a PRECHARGE command
tRP
After tRP is met, the bank is in the idle state.
Row Activing
Registration of an ACTIVATE command
tRCD
tRP
After tRCD is met, the bank is in the active state.
After tRP is met, the bank is in the idle state.
After tRP is met, the bank is in the idle state.
READ with
AP enabled
Registration of a READ
command with auto precharge enabled
WRITE with
AP enabled
Registration of a WRITE
command with auto precharge enabled
tRP
6. Bank-specific; requires that the bank is idle and no bursts are in progress.
7. Not bank-specific; requires that all banks are idle and no bursts are in progress.
8. Not bank-specific reset command is achieved through Mode Register Write command.
9. This command may or may not be bank specific. If all banks are being precharged, the must be in a valid state for precharging.
10. A command other than NOP should not be issued to the same bank while a READ or WRITE burst with auto precharge is enabled.
11. The new READ or WRITE command could be auto precharge enabled or auto precharge disabled.
12. A WRITE command can be issued after the completion of the READ burst.
13. A READ command can be issued after completion of the WRITE burst.
14. If a PRECHARGE command is issued to a bank in the idle state, tRP still applies.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Current State Bank n – Command to Bank m
Current State
of Bank n
Command
for Bank m
Next State
Notes
Operation
Continue previous operation
for Bank m
Any
Idle
NOP
Any
Current State of Bank m
-
Any command supported to Bank m
Activate
Read
Select and activate row in Bank m
Active
Reading
Writing
6
7
7
8
Select column, and start read burst from Bank m
Select column, and start write burst to Bank m
Deactivate row(s) in bank or banks
Row Activating,
Active, or
Precharging
Write
Precharge
Precharging
Idle MR Reading or Active
MR Reading
MRR
Read value from Mode Register
9,10,11
Read
Write
Select column, and start read burst from Bank m
Select column, and start write burst to Bank m
Select and activate row in Bank m
Reading
Writing
7
7,12
Reading
(AP disabled)
Activate
Precharge
Read
Active
Deactivate row(s) in bank or banks
Precharging
Reading
8
7,13
7
Select column, and start read burst from Bank m
Select column, and start write burst to Bank m
Select and activate row in Bank m
Write
Writing
Writing
(AP disabled)
Activate
Precharge
Read
Active
Deactivate row(s) in bank or banks
Precharging
Reading
8
Select column, and start read burst from Bank m
Select column, and start write burst to Bank m
Select and activate row in Bank m
7,14
Write
Writing
7,12,14
Reading with
Auto-Precharge
Activate
Precharge
Read
Active
Deactivate row(s) in bank or banks
Precharging
Reading
8
Select column, and start read burst from Bank m
Select column, and start write burst to Bank m
Select and activate row in Bank m
7,13,14
7,14
Write
Writing
Writing with
Auto-Precharge
Activate
Precharge
MRW Reset
MRR
Active
Deactivate row(s) in bank or banks
Precharging
Resetting
Resetting MR Reading
8
Power On
Resetting
Begin Device Auto-initialization
15,16
Read value from Mode Register
Notes:
1. This table applies when:
1a. the previous state was self refresh or power-down
1b. after tXSR or tXP has been met
1c. and both CKEn -1 and CKEn are HIGH
2. All states and sequences not shown are illegal or reserved.
3. Current state definitions:
State
Condition
And…
And…
Idle
The bank has been precharged
tRP is met
A row in the bank has been
activated
A READ burst has been initiated
with auto precharge disabled
A WRITE burst has been initiated
with auto precharge disabled
No data bursts/accesses and no
register accesses are in progress.
Active
Reading
Writing
tRCD is met
The READ has not yet terminated.
The WRITE has not yet terminated.
4. Refresh, self refresh, and MRW commands can only be issued when all banks are idle.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
5. The states listed below must not be interrupted by any executable command. NOP commands must be applied during each clock
cycle while in these states:
State
Starts with:
Ends when:
Notes
After tMRR is met, the device is in the
all-banks idle state.
Idle MR reading
Registration of the MRR command
tMRR is met
After tMRR is met, the device is in the
all-banks idle state.
After tMRR is met, the bank is in the
active state.
After tMRW is met, the device is in the
all-banks idle state.
Resetting MR reading
Active MR reading
MR writing
Registration of the MRR command
Registration of the MRR command
Registration of the MRW command
tMRR is met
tMRR is met
tMRW is met
6. tRRD must be met between the ACTIVATE command to bank n and any subsequent ACTIVATE command to bank m.
7. READs or WRITEs listed in the command column include READs and WRITEs with or without auto precharge enabled.
8. This command may or may not be bank specific. If all banks are being precharged, they must be in a valid state for precharging.
9. MRR is supported in the row-activating state.
10. MRR is supported in the precharging state.
11. The next state for bank m depends on the current state of bank m (idle, row-activating, precharging, or active).
12. A WRITE command can be issued only after the completion of the READ burst
13. A READ command can be issued only after the completion of the WRITE burst.
14. A READ with auto precharge enabled or a WRITE with auto precharge enabled can be followed by any valid command to other
banks provided that the timing restrictions are met.
15. Not bank-specific; requires that all banks are idle and no bursts are in progress.
16. RESET command is achieved through MODE REGISTER WRITE command.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
DM Operation Truth Table
The DM truth table provides specifications for data masking.
DM Truth Table
Function
Write Enable
Write Inhibit
DM
DQ
Valid
x
Notes
1
1
L
H
Note: Used to mask write data, provided simultaneouslywith the corresponding input data.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Commands and Timing
Command Input Setup and Hold
CK
tIS tIH
tIS tIH
VIH(AC)
VIL(DC)
VIH(DC)
VIL(AC)
CA
tIS tIH
CA
tIS tIH
CA
Rise
CA
Rise
CA
Fall
CA
Fall
CA
Rise
CA
Fall
CA
Fall
CA
Rise
CA0-9
Cmd
NOP
Command
NOP
Command
HIGH or LOW (but a defined logic level)
Transitioning data
NOTE 1 Setup and hold conditions also apply to the CKE pin. For timing diagrams related to the CKE pin, see “Power-Down”
CKE Input Setup and Hold
CK
tIHCKE
tISCKE
tIHCKE
tISCKE
CKE
VIHCKE
VILCKE
VIHCKE
VILCKE
HIGH or LOW (but a defined logic level)
NOTE 1 After CKE is registered LOW, CKE signal level shall be maintained below VILCKE for tCKE specification (LOW pulse width).
NOTE 2 After CKE is registered HIGH, CKE signal level shall be maintained above VIHCKE for tCKE specification (HIGH pulse
width).
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
ACTIVE
The ACTIVATE command is issued by holding LOW, CA0 LOW, and CA1 HIGH at the rising edge of the clock. The
bank addresses BA0 to BA2 are used to select the desired bank. Row addresses are used to determine which row to
activate in the selected bank. The ACTIVATE command must be applied before any READ or WRITE operation can be
executed. The device can accept a READ or WRITE command at tRCD after the ACTIVATE command is issued. After a
bank has been activated it must be precharged before another ACTIVATE command can be applied to the same bank.
The bank active and precharge times are defined as tRAS and tRP, respectively. The minimum time interval between
successive ACTIVATE commands to the same bank is determined by the RAS cycle time of the device (tRC). The
minimum time interval between ACTIVATE commands to different banks is tRRD.
ACTIVATE Command
CK
CA0-9
tRCD
Read Begins
tRRD
tRP
Precharge
NOP
NOP
NOP
Cmd
Activate
Activate
Read
Activate
tRAS
tRC
NOTE 1
A PRECHARGE-all command uses tRPab timing, while a single-bank PRECHARGE command uses tRPpb timing. In this
figure, tRP is used to denote either an all-bank PRECHARGE or a single-bank PRECHARGE.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
8-Bank Device Operation
Certain restrictions on operation of the 8-bank devices must be observed. There are two rules: One rule restricts the
number of sequential ACTIVATE commands that can be issued; the other provides more time for RAS precharge for a
PRECHARGE ALL command. The rules are as follows:
The 8-Bank Device Sequential Bank Activation Restriction: No more than 4 banks may be activated (or refreshed, in
the case of REFpb) in a rolling tFAW window. The number of clocks in a tFAW period is dependent upon the clock
frequency, which may vary. If the clock frequency is not changed over this period, converting to clocks is done by dividing
tFAW[ns] by tCK[ns], and rounding up to the next integer value. As an example of the rolling window, if RU(tFAW/tCK) is
10 clocks, and an ACTIVATE command is issued in clock n, no more than three further ACTIVATE commands can be
issued at or between clock n + 1 and n + 9. REFpb also counts as bank activation for purposes of tFAW. If the clock
frequency is changed during the tFAW period, the rolling tFAW window may be calculated in clock cycles by adding up
the time spent in each clock period. The tFAW requirement is met when the previous n clock cycles exceeds the tFAW
time.
The 8-Bank Device Precharge-All Allowance: tRP for a PRECHRGE ALL command must equal tRPab, which is
greater than tRPpb.
tFAW Timing
Tn
Tn+1
Tm
Tm+1
Tx
Tx+1
Ty
Ty+1
Ty+2
Tz
Tz+1
Tz+2
CK
Bank Bank
Bank Bank
Bank Bank
Bank Bank
Bank Bank
CA0-9
Cmd
A
A
B
B
C
C
D
D
E
E
ACTIVATE NOP
ACTIVATE NOP
ACTIVATE NOP
ACTIVATE
NOP
NOP
NOP
ACTIVATE
NOP
tRRD
tRRD
tRRD
tFAW
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
READ and WRITE Access Modes
After a bank is activated, a READ or WRITE command can be issued with LOW, CA0 HIGH, and CA1 LOW at the
rising edge of the clock. CA2 must also be defined at this time to determine whether the access cycle is a READ
operation (CA2 HIGH) or a WRITE operation (CA2 LOW).
The LPDDR3 SDRAM provides a fast column access operation. A single Read or Write Command will initiate a burst
read or write operation on successive clock cycles. Burst interrupts are not allowed.
Burst READ
The burst READ command is initiated with LOW, CA0 HIGH, CA1 LOW, and CA2 HIGH at the rising edge of the clock.
The command address bus inputs CA5r–CA6r and CA1f–CA9f determine the starting column address for the burst. The
read latency (RL) is defined from the rising edge of the clock on which the READ command is issued to the rising edge of
the clock from which the tDQSCK delay is measured. The first valid data is available RL × tCK + tDQSCK + tDQSQ after
the rising edge of the clock when the READ command is issued. The data strobe output is driven LOW tRPRE before the
first valid rising strobe edge. The first bit of the burst is synchronized with the first rising edge of the data strobe. Each
subsequent data-out appears on each DQ pin, edge-aligned with the data strobe. The RL is programmed in the mode
registers. Pin timings for the data strobe are measured relative to the crosspoint of DQS and its complement, .
READ Output Timing
RL
RL-1
tCH
RL + BL/2
tCL
CK
tDQSCK
tHZ(DQS)
tRPST
tQH
tRPRE
tLZ(DQS)
DQS
tQH
tDQSQmax
tDQSQmax
Dout
Dout
Dout
Dout
Dout
Dout
Dout
Dout
DQ
tLZ(DQ)
tHZ(DQ)
Transitioning data
NOTE 1 tDQSCK can span multiple clock periods.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Burst READ: RL = 12, BL = 8, tDQSCK > tCK
T0
T1
T2
T12
Ta-1
Ta
Ta+1
Ta+2
Ta+3
Ta+4
CK
RL = 12
CA[9:0]
CMD
READ
NOP
OP
NO
NOP
NOP
NOP
NOP
NOP
NOP
tDQSCK
DQS
Dout Dout Dout Dout Dout Dout Dout Dout
DQ
A1
A3
A4
A5
A2
A0
A7
A6
Transitioning data
Burst Read: RL = 12, BL = 8, tDQSCK < tCK
T0
T1
T2
T12
Tn
Tn+1
Tn+2
Tn+3
Tn+4
Tn+5
CK
RL = 12
CA[9:0]
CMD
READ
NOP
OP
NO
NOP
NOP
NOP
NOP
NOP
NOP
tDQSCK
DQS
Dout
A0
Dout Dout Dout Dout Dout Dout Dout
A1 A3 A4 A5
DQ
A2
A7
A6
Transitioning data
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Burst READ Followed by Burst WRITE: RL = 12, WL = 6, BL = 8
T0
T1
T2
T12
Ta-1
Ta
Ta+1 Ta+2 Ta+3 Ta+4 Ta+9 Ta+10
CK
WL = 6
BL/2
RL = 12
CA[9:0]
CMD
READ
tDQSCK
tDQSSmin
DQS
DQ
Transitioning data
The minimum time from the burst READ command to the burst WRITE command is defined by the read latency (RL) and
the burst length (BL). Minimum READ-to-WRITE latency is RL + RU(tDQSCK(MAX)/tCK) + BL/2 + 1 - WL clock cycles.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Seamless Burst READ – RL = 6, BL = 8, tCCD = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
CK
RL=6
CA[9:0]
CMD
tCCD=4
tCCD=4
READ
NOP
NOP
NOP
NOP
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
NOP
READ
DQS
DQ
Transitioning data
The seamless burst READ operation is supported by enabling a READ command at every fourth clock cycle for BL = 8
operation. This operation is supported as long as the banks are activated, whether the accesses read the same or
different banks.
tDQSCK Delta Timing
In order to allow for the system to track variations in tDQSCK output across multiple clock cycles, three parameters,
tDQSCKDS (delta short), tDQSCKDM (delta medium), and tDQSCKDL (delta long) are provided. Each of these
parameters defines the change in tDQSCK over a short, medium, or long rolling window, respectively. The definitions for
each tDQSCK-delta parameter show up on the next page.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
tDQSCKDL Timing
Tn
Tn+1 Tn+2 Tn+3 Tn+4
Tn+5
Tn+6 Tn+7 Tn+8
Tm Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tm+6 Tm+7 Tm+8
CK
CA[9:0]
CMD
tDQSCKm
tDQSCKn
DQS
RL = 5
RL = 5
DQ
32ms maximum
NOTE 1 tDQSCKDL = (tDQSCKn - tDQSCKm).
NOTE 2 tDQSCKDL,MAX is defined as the maximum of ABS (tDQSCKn - tDQSCKm) for any (tDQSCKn, tDQSCKm) pair within any
32ms rolling window.
tDQSCKDM Timing
Tn
Tn+1 Tn+2 Tn+3 Tn+4
Tn+5
Tn+6 Tn+7 Tn+8
Tm Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tm+6 Tm+7 Tm+8
CK
CA[9:0]
CMD
tDQSCKm
tDQSCKn
DQS
RL = 5
RL = 5
DQ
1.6us maximum
NOTE 1 tDQSCKDM = (tDQSCKn - tDQSCKm).
NOTE 2 tDQSCKDM,MAX is defined as the maximum of ABS (tDQSCKn - tDQSCKm) for any (tDQSCKn, tDQSCKm) pair within any
1.6μs rolling window.
tDQSCKDS Timing
Tn
Tn+1 Tn+2 Tn+3 Tn+4
Tn+5
Tn+6 Tn+7 Tn+8
Tm Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tm+6 Tm+7 Tm+8
CK
CA[9:0]
CMD
tDQSCKm
tDQSCKn
DQS
RL = 5
RL = 5
DQ
160ns maximum
NOTE 1 tDQSCKDS = (tDQSCKn - tDQSCKm).
NOTE 2 tDQSCKDS,MAX is defined as the maximum of ABS (tDQSCKn - tDQSCKm) for any (tDQSCKn, tDQSCKm) pair for READs
within a consecutive burst, within any 160ns rolling window.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Burst WRITE
The burst WRITE command is initiated with LOW, CA0 HIGH, CA1 LOW, and CA2 LOW at the rising edge of the
clock. The command address bus inputs, CA5r–CA6r and CA1f–CA9f, determine the starting column address for the
burst. Write latency (WL) is defined from the rising edge of the clock on which the WRITE command is issued to the rising
edge of the clock from which the tDQSS delay is measured. The first valid data must be driven WL × tCK + tDQSS from
the rising edge of the clock from which the WRITE command is issued. The data strobe signal (DQS) must be driven
LOW tWPRE prior to data input. The burst cycle data bits must be applied to the DQ pins tDS prior to the associated edge
of the DQS and held valid until tDH after that edge. Burst data is sampled on successive edges of the DQS until the burst
is completed. After a burst WRITE operation, tWR must be satisfied before a PRECHARGE command to the same bank
can be issued. Pin input timings are measured relative to the crosspoint of DQS and its complement, .
Data Input (WRITE) Timing
tWPST
tDQSL
tDQSH
tDQSL
DQS
tWPRE
VIH(AC)
VIH(DC)
VIH(AC)
VIH(DC)
DQ
DM
DIN
DIN
DIN
DM
DIN
IL
VIL(AC)
VIL(DC)
VIL(AC)
VIL(DC)
tDS
tDH tDS
tDH tDS
VIH(AC)
VIH(DC)
tDH tDS
tDH
VIH(AC)
VIH(DC)
DM
DM
DM
VIL(AC)
VIL(DC) VIL(AC)
VIL(DC)
Don’t Care
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Burst WRITE
Tx+1
T0
Ta
Ta+1
...
Ta+5
Tx
Ty
Ty+1
CK
WL
CA0-9
Cmd
WRITE
NOP
NOP
NOP
NO
Precharge
NP
ACTIVATE
NOP
Case 1: with tDQSS max
Completion of Burst Write
tDQSSmax tDSS
tDSS
DQS
DQ
tWR
tRP
Case 2: with tDQSS min
tDQSSmin tDSH tDSH
DQS
DQ
tWPRE Calculation
The method for calculating tWPRE is shown in the following figure:
Method for Calculating tWPRE Transitions and Endpoints
CK
VTT
tWPRE begins
T1
DQS -
tWPRE
Resulting differential signal
relevant for tWPRE specification
T2
tWPRE ends
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
tWPST Calculation
The method for calculating tWPST is shown in the follwing figure:
Method for Calculating tWPST Transitions and Endpoints
CK
VTT
tWPST begins
T1
DQS -
tWPST
T2
Resulting differential signal
tWPST ends
relevant for tWPST specification
Burst WRITE Followed by Burst READ
T0
Tx
Tx+1
Ty
Ty+1
NOP
Ty+2
NOP
Ty+3
Ty+4
CK,
CA0-0
Cmd
WRITE
WL
NOP
NOP
NOP
NOP
NOP
RL
NOP
DQS,
tWTR
DQ
NOTE 1 The minimum number of clock cycles from the burst WRITE command to the burst READ command for any bank is [WL
+ 1 + BL/2 + RU(tWTR/tCK)].
NOTE 2 tWTR starts at the rising edge of the clock after the last valid input data.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Seamless Burst WRITE: WL = 4, BL = 8, tCCD = 4
T0 ... T4 T5
T6
T7
T8
T9
T10
CK,
WL = 4
CA0-0
Cmd
WRITE
tCCD = 4
NOP
WRITE
NOP
NOP
NOP
WRITE
NOP
NOP
DQS,
DQ
NOTE 1 The seamless burst WRITE operation is supported by enabling a write command every four clocks for BL = 8 operation.
This operation is supported for any activated bank.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Write Data Mask
On LPDDR3 devices, one write data mask (DM) pin for each data byte (DQ) is supported, consistent with the
implementation on LPDDR2 SDRAM. Each DM can mask its respective DQ for any given cycle of the burst. Data mask
timings match data bit timing, but are inputs only. Internal data-mask loading is identical to data-bit loading to ensure
matched system timing.
Data Mask Timing
DQS
DQ
VIH(AC)
VIH(DC)
VIH(AC)
VIH(DC)
DM
VIL(AC)
VIL(DC)
VIL(AC)
VIL(DC)
tDS
tDH
tDS
tDH
WRITE Data Mask, Second Data Bit Masked
CK
tWTR
tWR
WRITE
Cmd
Case 1: with tDQSSmin
WL
tDQSSmin
0
DQS
DQ
1
2
3
4
5
6
7
DM
Case 2: with tDQSSmax
tDQSSmax
DQS
0
1
2
3
4
5
6
7
DQ
DM
NOTE 1 For the data mask function, BL = 8 is shown; the second data bit is masked.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
PRECHARGE Operation
The PRECHARGE command is used to precharge or close a bank that has been activated. The PRECHARGE command
is initiated with LOW, CA0 HIGH, CA1 HIGH, CA2 LOW, and CA3 HIGH at the rising edge of the clock. The
PRECHARGE command can be used to precharge each bank independently or all banks simultaneously. The AB flag
and the bank address bits BA0, BA1, and BA2 are used to determine which bank(s) to precharge.
The precharged bank(s) will be available for subsequent row access tRPab after an allbank PRECHARGE command is
issued, or tRPpb after a single-bank PRECHARGE command is issued.
To ensure that LPDDR3 devices can meet the instantaneous current demand required to operate, the row-precharge time
for an all-bank PRECHARGE (tRPab) will be longer than the row PRECHARGE time for a single-bank PRECHARGE
(tRPpb).
Bank Selection for PRECHARGE by Address Bits
Precharged Bank(s)
AB (CA4r) BA2 (CA9r) BA1 (CA8r) BA0 (CA7r)
8-bank device
0
0
0
0
0
0
0
0
1
0
0
0
Bank 0 only
Bank 1 only
Bank 2 only
Bank 3 only
Bank 4 only
Bank 5 only
Bank 6 only
Bank 7 only
All Banks
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
1
1
0
1
Don't care
Don't care
Don't care
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Burst READ Operation Followed by PRECHARGE
For the earliest possible precharge, the PRECHARGE command can be issued BL/2 clock cycles after a READ command.
A new bank ACTIVATE command can be issued to the same bank after the row PRECHARGE time (tRP) has elapsed. A
PRECHARGE command cannot be issued until after tRAS is satisfied. For LPDDR3 devices, the minimum
READ-to-PRECHARGE time (tRTP) must also satisfy a minimum analog time from the rising clock edge that initiates the
last 8-bit prefetch of a READ command. tRTP begins BL/2 – 4 clock cycles after the READ command.
Burst READ Followed by PRECHARGE: BL = 8, RU(tRTP(MIN)/tCK) = 2
T0
T1
...
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
CK
RL
CA0-0
Cmd
READ
NOP
NOP
Precharge
NOP
NOP
tRP
ACTIVATE
NOP
NOP
tRTP
DQS,
DQ
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4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Burst WRITE Followed by PRECHARGE
For WRITE cycles, a WRITE recovery time (tWR) must be provided before a PRECHARGE command can be issued. This
delay is referenced from the last valid burst input data to the completion of the burst WRITE. PRECHARGE command
must not be issued prior to the tWR delay.
LPDDR3 devices write data to the array in prefetch multiples (prefetch = 8). An internal WRITE operation can only begin
after a prefetch group has been completely latched, so tWR starts at prefetch boundaries. The minimum
WRITE-to-PRECHARGE time for commands to the same bank is WL + BL/2 + 1 + RU(tWR/tCK) clock cycles.
Burst WRITE Followed by PRECHARGE: BL = 8
T0
Tx
Tx+1
Tx+4
Tx+5
Ty
Ty+1
Tz
Tz+1
CK
WL
CA0-0
Cmd
WRITE
NOP
NOP
NOP
NOP
Precharge
NOP
ACTIVATE
NOP
Case 1: with tDQSSmax
Completion of Burst Write
tDQSSmax
DQS
DQ
Case 2: with tDQSSmin
tDQSSmin
tWR
tRP
DQS
DQ
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4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Auto PRECHARGE Operation
Before a new row can be opened in an active bank, the active bank must be precharged using either the PRECHARGE
command or the auto precharge function. When a READ or a WRITE command is issued to the device, the AP bit (CA0f)
can be set to enable the active bank to automatically begin precharge at the earliest possible moment during the burst
READ or WRITE cycle.
If AP is LOW when the READ or WRITE command is issued, then normal READ or WRITE burst operation is executed
and the bank remains active at the completion of the burst.
If AP is HIGH when the READ or WRITE command is issued, the auto precharge function is engaged. This feature
enables the PRECHARGE operation to be partially or completely hidden during burst READ cycles (dependent upon
READ or WRITE latency) thus improving system performance for random data access.
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4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Burst READ with Auto PRECHARGE
If AP (CA0f) is HIGH when a READ command is issued, the READ with auto-precharge function is engaged. LPDDR3
devices start an auto-precharge operation on the rising edge of the clock BL/2 or BL/2 - 2 + RU(tRTP/tCK) clock cycles
later than the READ with auto precharge command, whichever is greater.
Following an auto-precharge operation, an ACTIVATE command can be issued to the same bank if the following two
conditions are satisfied simultaneously:
• The RAS precharge time (tRP) has been satisfied from the clock at which the auto-precharge begins.
• The RAS cycle time (tRC) from the previous bank activation has been satisfied.
Burst READ with Auto Precharge: BL = 8, RU(tRTP(MIN)/tCK) = 4
T0
T1
...
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
CK
RL
CA0-0
Cmd
READ
NOP
NOP
NOP
NOP
NOP
≧tRPpb
NOP
ACTIVATE
tRTP
DQS,
DQ
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4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Burst WRITE with Auto Precharge
If AP (CA0f ) is HIGH when a WRITE command is issued, the WRITE with auto precharge function is engaged. The
device starts an auto precharge on the rising edge tWR cycles after the completion of the burst WRITE.
Following a WRITE with auto precharge, an ACTIVATE command can be issued to the same bank if the following two
conditions are met:
• The RAS precharge time (tRP) has been satisfied from the clock at which the autoprecharge begins.
• The RAS cycle time (tRC) from the previous bank activation has been satisfied.
Burst WRITE with Auto Precharge: BL = 8
T0
Tx
Tx+1
...
Tx+5
Ty
Ty+1
Tz
Tz+1
CK
WL
tWR
≧tRPpb
CA0-0
Cmd
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
ACTIVATE
NOP
DQS,
DQ
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4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
PRECHARGE and Auto Precharge Clarification
From
Minimum Delay between "From Command"
To Command
Command
Unit Notes
to "To Command"
Precharge (to same Bank as Read)
BL/2 + max(4, RU(tRTP/tCK)) - 4
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
1
1
Read
Precharge All
BL/2 + max(4, RU(tRTP/tCK)) - 4
Precharge (to same Bank as Read w/AP)
Precharge All
BL/2 + max(4, RU(tRTP/tCK)) - 4
1,2
1
BL/2 + max(4, RU(tRTP/tCK)) - 4
Activate (to same Bank as Read w/AP)
BL/2 + max(4, RU(tRTP/tCK)) - 4 + RU(tRPpb/tCK)
1
Read w/AP
Write
Write or Write w/AP (same bank)
Write or Write w/AP (different bank)
Read or Read w/AP (same bank)
Read or Read w/AP (different bank)
Precharge (to same Bank as Write)
Precharge All
illegal
3
RL + BL/2 + RU(tDQSCKmax/tCK) - WL + 1
3
illegal
3
BL/2
3
WL + BL/2 + RU(tWR/tCK) + 1
1
WL + BL/2 + RU(tWR/tCK) + 1
1
Precharge (to same Bank as Write w/AP)
Precharge All
WL + BL/2 + RU(tWR/tCK) + 1
1,2
1
WL + BL/2 + RU(tWR/tCK) + 1
Activate (to same Bank as Write w/AP)
Write or Write w/AP (same bank)
Write or Write w/AP (different bank)
Read or Read w/AP (same bank)
Read or Read w/AP (different bank)
Precharge (to same Bank as Precharge)
Precharge All
WL + BL/2 + RU(tWR/tCK) + 1 + RU(tRPpb/tCK)
1
Write w/AP
Precharge
illegal
3
BL/2
3
illegal
3
WL + BL/2 + RU(tWTR/tCK) + 1
3
1
1
1
1
1
1
Precharge
1
Precharge
All
Precharge All
1
Notes:
1. For a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge
or precharge all, issued to that bank. The precharge period is satisfied after tRP depending on the latest precharge command
issued to that bank.
2. Any command issued during the minimum delay time as specified above table is illegal.
3. After Read with AP, seamless read operations to different banks are supported. After Write with AP, seamless write
operations to different banks are supported. Read w/AP and Write a/AP may not be interrupted or truncated.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
REFRESH Command
The REFRESH command is initiated with LOW, CA0 LOW, CA1 LOW, and CA2 HIGH at the rising edge of the clock.
Per-bank REFRESH is initiated with CA3 LOW at the rising edge of the clock. All-bank REFRESH is initiated with CA3
HIGH at the rising edge of the clock.
A per-bank REFRESH command (REFpb) performs a per-bank REFRESH operation to the bank scheduled by the bank
counter in the memory device. The bank sequence for per-bank REFRESH is fixed to be a sequential round-robin:
0-1-2-3-4-5-6-7-0-1-.... The bank count is synchronized between the controller and the SDRAM by resetting the bank
count to zero. Synchronization can occur upon issuing a RESET command or at every exit from self refresh. Bank
addressing for the per-bank REFRESH count is the same as established for the single-bank PRECHARGE command. A
bank must be idle before it can be refreshed. The controller must track the bank being refreshed by the per-bank
REFRESH command.
The REFpb command must not be issued to the device until the following conditions are met:
• tRFCab has been satisfied after the prior REFab command
• tRFCpb has been satisfied after the prior REFpb command
• tRP has been satisfied after the prior PRECHARGE command to that bank
• tRRD has been satisfied after the prior ACTIVATE command (if applicable, for example after activating a row in a
different bank than the one affected by the REFpb command).
The target bank is inaccessible during per-bank REFRESH cycle time (tRFCpb), however, other banks within the device
are accessible and can be addressed during the cycle.During the REFpb operation, any of the banks other than the one
being refreshed can be maintained in an active state or accessed by a READ or a WRITE command. When the per-bank
REFRESH cycle has completed, the affected bank will be in the idle state.
After issuing REFpb, these conditions must be met:
• tRFCpb must be satisfied before issuing a REFab command
• tRFCpb must be satisfied before issuing an ACTIVATE command to the same bank
• tRRD must be satisfied before issuing an ACTIVATE command to a different bank
• tRFCpb must be satisfied before issuing another REFpb command.
An all-bank REFRESH command (REFab) issues a REFRESH command to all banks. All banks must be idle when
REFab is issued (for instance, by issuing a PRECHARGE-all command prior to issuing an all-bank REFRESH command).
REFab also synchronizes the bank count between the controller and the SDRAM to zero. The REFab command must not
be issued to the device until the following conditions have been met:
• tRFCab has been satisfied following the prior REFab command
• tRFCpb has been satisfied following the prior REFpb command
• tRP has been satisfied following the prior PRECHARGE commands.
When an all-bank refresh cycle has completed, all banks will be idle. After issuing REFab:
• tRFCab latency must be satisfied before issuing an ACTIVATE command
• tRFCab latency must be satisfied before issuing a REFab or REFpb command.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
REFRESH Command Scheduling Separation Requirements
Symbol
minimum delay from
to
Notes
REFab
tRFCab
REFab
Activate cmd to any bank
REFpb
REFab
Activate cmd to same bank as REFpb
REFpb
tRFCpb
tRRD
REFpb
REFpb
Activate
REFpb affecting an idle bank (different bank than Activate)
Activate cmd to different bank than prior Activate
1
ACTIVATE
NOTE 1 A bank must be in the idle state before it is refreshed, so following an ACTIVATE command REFab is prohibited; REFpb
is supported only if it affects a bank that is in the idle state.
In general, an all bank refresh command needs to be issued to the LPDDR3 SDRAM regularly every tREFI interval. To
allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is
provided for postponing and pulling-in refresh command. A maximum of 8 Refresh commands can be postponed during
operation of the LPDDR3 SDRAM, meaning that at no point in time more than a total of 8 Refresh commands are allowed
to be postponed. In case that 8 Refresh commands are postponed in a row, the resulting maximum interval between the
surrounding Refresh commands is limited to 9 × tREFI. A maximum of 8 additional Refresh commands can be issued in
advance (“pulled in”) , with each one reducing the number of regular Refresh commands required later by one. Note that
pulling in more than 8, depending on Refresh mode, Refresh commands in advance does not further reduce the number
of regular Refresh commands required later, so that the resulting maximum interval between two surrounding Refresh
commands is limited to 9 × tREFI . At any given time, a maximum of 16 REF commands can be issued within 2 x tREFI
And for per bank refresh, a maximum 8 x 8 per bank refresh commands can be postponed or pulled in for scheduling
efficiency. At any given time, a maximum of 2 x 8 x 8 per bank refresh commands can be issued within 2 x tREFI.
Refresh Command Timing
NOTE 1 Only NOP commands allowed after Refresh command registered untill tRFC(min) expires.
NOTE 2 Time interval between two Refresh commands may be extended to a maximum of 9 X tREFI.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Postponing Refresh Commands
Pulling-in Refresh Commands
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4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
REFRESH Requirements
1. Minimum number of REFRESH commands
LPDDR3 requires a minimum number, R, of REFRESH (REFab) commands within any rolling refresh window (tREFW
= 32 ms @ MR4[2:0] = 011 or TC ≤ 85°C). For actual values per density, and the resulting average refresh interval
(tREFI). For tREFW and tREFI refresh multipliers at different MR4 settings.
When using per-bank REFRESH, a REFab command can be replaced by a full cycle of eight REFpb commands.
2. REFRESH Requirements and SELF REFRESH
Self refresh mode may be entered with a maximum of eight refresh commands being postponed. After exiting
selfrefresh mode with one or more refresh commands postponed, additional refresh commands may be postponed to
the extent that the total number of postponed refresh commands (before and after the self refresh) will never exceed
eight. During self-refresh mode, the number of postponed or pulled-in REF commands does not change.
“The use of self refresh mode introduces the possibility that an internally timed refresh event can be missed when CKE
is raised for exit from self refresh mode. Upon exit from self refresh, the LPDDR3 SDRAM requires a minimum of one
extra refresh command before it is put back into self refresh mode.”
All-Bank REFRESH Operation
T0
T1
T2
T3
T4
Tx
Tx+1
Ty
Ty+1
CK
CA0-9
Cmd
Precharge
NOP
≧tRPab
NOP
REFab
NOP
REFab
NOP
tRFCab
Valid
NOP
≧tRFCab
Per-Bank REFRESH Operation
T0 T1 T2
T3
T4
Tx
Tx+1
Ty
Ty+1
CK
Bank1 RowA
RowA
CA0-9
Cmd Precharge
NOP
≧tRPab
NOP
REFpb
NOP
REFpb
NOP
tRFCpb
ACTIVATE
NOP
≧tRFCpb
Refresh to Bank 0
Refresh to Bank 1
Activate command to Bank 1
NOTE 1 In the beginning of this example, the REFpb bank is pointing to bank 0.
NOTE 2 Operations to banks other than the bank being refreshed are supported during the tRFCpb period.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
SELF REFRESH Operation
The SELF REFRESH command can be used to retain data in the array, even if the rest of the system is powered down.
When in the self refresh mode, the device retains data without external clocking. The device has a built-in timer to
accommodate SELF REFRESH operation. The SELF REFRESH command is executed by taking CKE LOW, LOW,
CA0 LOW, CA1 LOW, and CA2 HIGH at the rising edge of the clock. CKE must be HIGH during the clock cycle preceding
a SELF REFRESH command. To ensure that there is enough time to account for internal delay on the CKE signal path,
two NOP commands are reuired after CKE is driven LOW, this timing period is defined as tCPDED. CKE LOW will result
in deactivation of input receivers after tCPDED has expired. After the power-down command is registered, CKE must be
held LOW to keep the device in self refresh mode.
LPDDR3 devices can operate in self refresh mode in both the standard and elevated temperature ranges. These devices
also manage self refresh power consumption when the operating temperature changes, resulting in the lowest possible
power consumption across the operating temperature range.
Once the SDRAM has entered Self Refresh mode, all of the external signals except CKE, are “don’t care”. For proper self
refresh operation, power supply pins (VDD1, VDD2, and VDDCA) must be at valid levels. VDDQ may be turned off during
Self-Refresh. Prior to exiting Self-Refresh, VDDQ must be within specified limits. VrefDQ and VrefCA may be at any level
within minimum and maximum levels (see Absolute Maximum DC Ratings). However prior to exiting Self-Refresh,
VrefDQ and VrefCA must be within specified limits (see Recommended DC Operating Conditions). The SDRAM initiates
a minimum of one all-bank refresh command internally within tCKESR period once it enters Self Refresh mode. The clock
is internally disabled during Self Refresh Operation to save power. The minimum time that the SDRAM must remain in
Self Refresh mode is tCKESR,min. The user may change the external clock frequency or halt the external clock tCPDED
after Self Refresh entry is registered; however, the clock must be restarted and stable before the device can exit Self
Refresh operation.
The procedure for exiting Self Refresh requires a sequence of commands. First, the clock shall be stable and within
specified limits for a minimum of 2 tCK prior to the positive clock edge that registers CKE HIGH. Once Self Refresh Exit is
registered, a delay of at least tXSR must be satisfied before a valid command can be issued to the device to allow for any
internal refresh in progress. CKE must remain HIGH for the entire Self Refresh exit period tXSR for proper operation.
NOP commands must be registered on each positive clock edge during the Self Refresh exit interval tXSR. For the
description of ODT operation and specifications during self-refresh entry and exit, see section On-Die Termination.
The use of Self Refresh mode introduces the possibility that an internally timed refresh event can be missed when CKE is
raised for exit from Self Refresh mode. Upon exit from Self Refresh, it is required that at least one REFRESH command
(8 per-bank or 1 all-bank) is issued before entry into a subsequent Self Refresh.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Self Refresh Operation
2 x tCK(min)
CK
tIHCKE tCPDED
tIHCKE
Input clock frequency may be changed or the
input clock stopped during Self-Refresh.
CKE
tISCKE
tISCKE
tXSR(min)
Exit
tCKESR(min)
Enter
SR
Valid
NOP NOP
NOP N P Valid
Cmd
SR
Enter Self-Refresh
Exit Self-Refresh
NOTE 1 Input clock frequency can be changed or stopped during self refresh, provided that upon exiting self-refresh, a
minimum of 2 cycles of stable clocks are provided, and the clock frequency is between the minimum and maximum
frequencies for the particular speed grade.
NOTE 2 The device must be in the all-banks-idle state prior to entering self refresh mode.
NOTE 3 tXSR begins at the rising edge of the clock after CKE is driven HIGH.
NOTE 4 A valid command can be issued only after tXSR is satisfied. NOPs must be issued during tXSR.
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4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Partial-Array Self Refresh: Bank Masking
LPDDR3 SDRAMs are comprised of 8 banks. Each bank can be configured independently whether a self refresh
operation is taking place. One 8-bit mode register (accessible via the MRW command) is assigned to program the
bankmasking status of each bank up to 8 banks.
The mask bit to the bank enables or disables a refresh operation of the entire memory space within the bank. If a bank is
masked using the bank mask register, a REFRESH operation to the entire bank is blocked and bank data retention is not
guaranteed in self refresh mode. To enable a REFRESH operation to a bank, the corresponding bank mask bit must be
programmed as “unmasked.” When a bank mask bit is unmasked, the array space being refreshed within that bank is
determined by the programmed status of the segment mask bits. bits, which is decribed in the following pages.
Partial-Array Self Refresh: Segment Masking
Programming segment mask bits is similar to programming bank mask bits. Eight segments are used for masking. A
mode register is used for programming segment mask bits up to 8 bits.
When the mask bit to an address range (represented as a segment) is programmed as “masked,” a REFRESH operation
to that segment is blocked. Conversely, when a segment mask bit to an address range is unmasked, refresh to that
segment is enabled.
A segment-masking scheme can be used in place of or in combination with a bankmasking scheme. Each
segment-mask bit setting is applied across all banks. Programming of bits in the reserved registers has no effect on the
device operation.
Segment Mask
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
(MR17)
Bank Mask
(MR16)
0
1
0
0
0
0
0
1
Segment 0
Segment 1
Segment 2
Segment 3
Segment 4
Segment 5
Segment 6
Segment 7
0
0
1
0
0
0
0
1
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
NOTE 1 This table illustrates an example of an 8-bank LPDDR3 device, when a refresh operation to bank 1 and bank 7, as well
as segment 2 and segment 7 are masked.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
MODE REGISTER READ (MRR)
The MRR command is used to read configuration and status data from SDRAM mode registers. The MRR command is
initiated with LOW, CA0 LOW, CA1 LOW, CA2 LOW, and CA3 HIGH at the rising edge of the clock. The mode
register is selected by CA1f–CA0f and CA9r–CA4r. The mode register contents are available on the first data beat of
DQ[7:0] after RL × tCK + tDQSCK + tDQSQ following the rising edge of the clock where MRR is issued. Subsequent data
beats contain valid but undefined content, except in the case of the DQ calibration function, where subsequent data beats
contain valid content as described. All DQS are toggled for the duration of the mode register READ burst.
The MRR command has a burst length of eight. MRR operation (consisting of the MRR command and the corresponding
data traffic) must not be interrupted. The MRR command period is defined as tMRR.
T0
...
T4
T5
T6
T7
T8
T9
T10
CK
CA0-9
Cmd
MRR1
NOP2
MRR1
NOP2
tMRR=4
NOP2
NOP2
Valid
Valid
Valid
tMRR=4
DQS
RL=8
DQ[7:0]3
DQ[max:8]
NOTE 1 MRRs to DQ calibration registers MR32 and MR40 are described in “DQ Calibration” .
NOTE 2 Only the NOP command is supported during tMRR.
NOTE 3 Mode register data is valid only on DQ[7:0] on the first beat. Subsequent beats contain valid but undefined data.
DQ[MAX:8] contain valid but undefined data for the duration of the MRR burst.
NOTE 4 Minimum Mode Register Read to write latency is RL + RU(tDQSCKmax/tCK) + 8/2 + 1 - WL clock cycles.
NOTE 5 Minimum Mode Register Read to Mode Register Write latency is RL + RU(tDQSCKmax/tCK) + 8/2 + 1clock cycles.
NOTE 6 In this example, RL = 8 for illustration purposes only. After a prior READ command, the MRR command must not be issued
earlier than BL/2 clock cycles, or WL + 1 + BL/2 + RU(tWTR/tCK) clock cycles after a prior WRITE command, as READ bursts
and WRITE bursts must not be truncated by MRR.
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8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
READ to MRR Timing
NOTE 1 The minimum number of clock cycles from the burst READ command to the MRR command is BL/2.
NOTE 2 Only the NOP command is supported during tMRR.
After a prior READ command, the MRR command must not be issued earlier than BL/2 clock cycles, or WL + 1 + BL/2 +
RU(tWTR/tCK) clock cycles after a prior WRITE command, as READ bursts and WRITE bursts must not be truncated by
MRR.
Burst WRITE Followed by MRR
T0
Tx
Tx+1
...
Tx+5
Tx+6
Tx+7
Tx+8
Tx+9
CK
WL
RL
CA0-9
Cmd
Write
Valid
MRR1
NOP2
tMRR
NOP2
tWTR
DQS
DQ
NOTE 1 The minimum number of clock cycles from the burst WRITE command to the MRR command is [WL + 1 + BL/2 +
RU(tWTR/tCK)].
NOTE 2 Only the NOP command is supported during tMRR.
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MRR Following Idle Power-Down State
Following the idle power-down state, an additional time, tMRRI, is required prior to issuing the mode register read (MRR)
command. This additional time (equivalent to tRCD) is required in order to be able to maximize power-down current
savings by allowing more power-up time fo rthe MRR data path after exit from the idle power-down state.
NOTE 1 Any valid command except MRR.
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Temperature Sensor
LPDDR3 devices feature a temperature sensor whose status can be read from MR4. This sensor can be used to
determine an appropriate refresh rate, determine whether AC timing derating is required in the elevated temperature
range, and/or monitor the operating temperature. Either the temperature sensor or the device operating temperature can
be used to determine if operating temperature requirements are being met.
Temperature sensor data can be read from MR4 using the Mode Register Read protocol. Upon exiting self-refresh or
power-down, the device temperature status bits will be no older than tTSI.
When using the temperature sensor, the actual device case temperature may be higher than the operating temperature
specification that applies for the standard or extended temperature ranges. For example, TCASE could be above 85°C
when MR4[2:0] equals 011B. LPDDR3 devices shall allow for 2oC temperature margin between the point at which the
device updates the MR4 value and the point at which the controller re-configures the system accordingly. In the case of
tight thermal coupling of the memory device to external hot spots, the maximum device temperature might be higher than
what is indicated by MR4.
To assure proper operation using the temperature sensor, applications should consider the following specifications.
Edge
Parameter
Symbol
Value
Unit
Notes
Maximum temperature gradient experienced by
the memory device at the temperature of interest
over a range of 2°C.
System Temperature Gradient
Max System Dependent oC/s
Max System Dependent ms
TempGradient
MR4 Read Interval
ReadInterval
tTSI
Time period between MR4 READs from the system.
Maximum delay between internal updates of MR4.
Temperature Sensor Interval
Max
32
ms
Maximum response time from an MR4 READ to the
system response.
System Response Delay
Max System Dependent ms
SysRespDelay
TempMargin
Margin above maximum temperature to support
controller response.
Device Temperature Margin
Max
2
oC
These devices accommodate the temperature margin between the point at which the device temperature enters the
elevated temperature range and point at which the controller re-configures the system accordingly. To determine the
required MR4 polling frequency, the system must use the maximum TempGradient and the maximum response time of
the system using the following equation:
TempGradient × (ReadInterval + tTSI + SysRespDelay) ≦ 2°C
For example, if TempGradient is 10°C/s and the SysRespDelay is 1ms:
10oC/s x (ReadInterval + 32ms + 1ms) <= 2oC
In this case, ReadInterval must not exceed 167ms.
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Temperature Sensor Timing
Temp
< (tTSI + ReadInterval + SysRespDelay)
Device
Temp
Margin
TempGradient
2oC
MR4
Trip Level
tTSI
MR4 = 0x03 MR4 = 0x86
MR4 = 0x86
MR4 = 0x86 MR4 = 0x86 MR4 = 0x06
Time
Temperature
Sensor Update
SysRespDelay
ReadInterval
Host MR4 Read
MRR MR4 = 0x03
MRR MR4 = 0x86
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DQ Calibration
LPDDR3 devices feature a DQ calibration function that outputs one of two predefined system-timing calibration patterns.
An MRR operation to MR32 (pattern A) or an MRR operation to MR40 (pattern B) will return the specified pattern on DQ0
and DQ8; and on DQ0, DQ8, DQ16, and DQ24 for x32 devices. For x16 devices, DQ[7:1] and DQ[15:9] drive the same
information as DQ0 during the MRR burst. For x32 devices, DQ[7:1], DQ[15:9], DQ[23:17], and DQ[31:25] drive the same
information as DQ0 during the MRR burst. MRR DQ calibration commands can occur only from the idle state.
Data Calibration Pattern Description
Bit Time Bit Time Bit Time Bit Time Bit Time Bit Time Bit Time Bit Time
Pattern
MR#
0
1
2
3
4
5
6
7
Pattern A
Pattern B
MR32
MR40
1
0
1
0
1
0
1
0
0
0
1
1
0
0
1
1
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Mode Register Write (MRW) Command
The Mode Register Write (MRW) command is used to write configuration data to mode registers. The MRW command is
initiated with LOW, CA0 LOW, CA1 LOW, CA2 LOW, and CA3 LOW at the rising edge of the clock. The mode register
is selected by CA1f-CA0f, CA9r-CA4r. The data to be written to the mode register is contained in CA9f-CA2f. The MRW
command period is defined by tMRW. Mode register WRITEs to read-only registers have no impact on the functionality of
the device.
MODE REGISTER WRITE Timing
T0
T1
T2
Tx
Tx + 1
Tx + 2
Ty
Ty + 1
Ty + 2
CK
CA0-9
Cmd
tMRW
tMRW
NOP2
MRW
NOP2
NOP2
MRW
NOP2
Valid
NOTE 1 At time Ty, the device is in the idle state.
NOTE 2 Only the NOP command is supported during tMRW.
MRW
MRW can only be issued when all banks are in the idle precharge state. One method of ensuring that the banks are in this
state is to issue a PRECHARGE-ALL command.
Truth Table for MRR and MRW
Current State
Command
MRR
Intermediate State
Mode Register Reading (All Banks idle)
Mode Register Writing (All Banks idle)
Restting (Device Auto-Init)
Mode Register Reading (Bank(s) idle)
Not Allowed
Next State
All Banks idle
All Banks idle
All Banks idle
Bank(s) Active
Not Allowed
Not Allowed
All Banks idle
MRW
MRW (Reset)
MRR
Bank(s) Active
MRW
MRW (Reset)
Not Allowed
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Mode Register Write Reset (MRW Reset)
The MRW RESET command brings the device to the device auto-initialization (resetting) state in the power-on
initialization sequence (see “Voltage Ramp and Device Initialization”). The MRW RESET command can be issued from
the idle state. This command resets all mode registers to their default values. After MRW RESET, boot timings must be
observed until the device initialization sequence is complete and the device is in the idle state. Array data is undefined
after the MRW RESET command.
If the initialization is to be performed at-speed (greater than the recommended boot clock frequency), then CA Training
may be necessary to ensure setup and hold timings. Since the MRW RESET command is required prior to CA Training,
an alternate MRW RESET command with an op-code of 0xFCh should be used. This encoding ensures that no transitions
occur on the CA bus. Prior to CA Training, it is recommended to hold the CA bus stable for one cycle prior to, and one
cycle after, the issuance of the MRW RESET command to ensure setup and hold timings on the CA bus.
NOTE 1 Optional MRW RESET command and optional assertion are allowed, When optional MRW RESET command is
used, tINIT4 starts at Td’.
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MRW ZQ Calibration Command
The MRW command is used to initiate the ZQ calibration command. This command is used to calibrate the output driver
impedance across process, temperature, and voltage. LPDDR3 devices support ZQ calibration.
There are four ZQ calibration commands and related timings: tZQINIT, tZQRESET, tZQCL, and tZQCS. tZQINIT is for
initialization calibration; tZQRESET is for resetting ZQ to the default output impedance; tZQCL is for long calibration(s);
and tZQCS is for short calibration(s). See calibration command-code definitions.
The initialization ZQ calibration (ZQINIT) must be performed for LPDDR3. ZQINIT provides an output impedance
accuracy of ±15 percent. After initialization, the ZQ calibration long (ZQCL) can be used to recalibrate the system to an
output impedance accuracy of ±15 percent. A ZQ calibration short (ZQCS) can be used periodically to compensate for
temperature and voltage drift in the system.
The ZQ reset command (ZQRESET) resets the output impedance calibration to a default accuracy of ±30% across
process, voltage, and temperature. This command is used to ensure output impedance accuracy to ±30% when ZQCS
and ZQCL commands are not used.
One ZQCS command can effectively correct at least 1.5% (ZQ correction) of output impedance errors within tZQCS for all
speed bins, assuming the maximum sensitivities specified are met. The appropriate interval between ZQCS commands
can be determined from using these tables and system-specific parameters.
LPDDR3 devices are subject to temperature drift rate (TdriftrateE) and voltage drift rate (Vdriftrate) in various applications.
To accommodate drift rates and calculate the necessary interval between ZQCS commands, apply the following formula:
ZQCorrection
=
CalibrationInterval
(TSens x Tdriftrate) + (VSens x Vdriftrate)
Where Tsens = MAX (dRONdT) and Vsens = MAX (dRONdV) define temperature and voltage sensitivities.
For example, if Tsens = 0.75%/°C, Vsens = 0.20%/mV, Tdriftrate = 1°C/sec, and
Vdriftrate = 15mV/sec, then the interval between ZQCS commands is calculated as:
1.5
=
0.4s
(0.75 x 1) + (0.20 x 15)
A ZQ calibration command can only be issued when the device is in the idle state with all banks precharged. ODT shall be
disabled via the mode register or the ODT pin prior to issuing a ZQ calibration command. No other activities can be
performed on the data bus and the data bus shall be un-terminated during calibration periods (tZQINIT, tZQCL, or tZQCS).
The quiet time on the data bus helps to accurately calibrate output impedance. There is no required quiet time after the
ZQ RESET command. If multiple devices share a single ZQ resistor, only one device can be calibrating at any given time.
After calibration is complete, the ZQ ball circuitry is disabled to reduce power consumption. In systems sharing a ZQ
resistor between devices, the controller must prevent tZQINIT, tZQCS, and tZQCL overlap between the devices. ZQ
RESET overlap is acceptable.
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ZQ Timings
T0
T1
T2
T3
T4
T5
Tx
Tx + 1
Tx + 2
CK
CA0-9
tZQINIT
tZQINIT
MRW
NOP
NOP
NOP
NOP
NOP
Valid
Cmd
tZQCS
tZQCS
NOP
Cmd
MRW
MRW
MRW
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Valid
Valid
Valid
tZQCL
tZQCL
NOP
Cmd
tZQRESET
tZQRESET
NOP
Cmd
NOTE 1 Only the NOP command is supported during ZQ calibration.
NOTE 2 CKE must be registered HIGH continuously during the calibration period.
NOTE 3 All devices connected to the DQ bus should be High-Z during the calibration process.
ZQ External Resistor Value, Tolerance, and Capacitive Loading
To use the ZQ calibration function, a RZQ±1% tolerance external resistor must be connected between the ZQ pin and
ground. A single resistor can be used for each device or one resistor can be shared between multiple devices if the ZQ
calibration timings for each device do not overlap. The total capacitive loading on the ZQ pin must be limited.
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MRW - CA Training Mode
Because CA inputs operate as double data rate, it may be difficult for memory controller to satisfy CA input setup/hold
timings at higher frequency. A CA Training mechanism is provided.
CA Training Sequence
1. CA Training mode entry: Mode Register Write to MR41
2. CA Training session: Calibrate CA0, CA1, CA2, CA3, CA5, CA6, CA7 and CA8
3. CA to DQ mapping change: Mode Register Write to MR48
4. Additional CA Training session: Calibrate remaining CA pins (CA4 and CA9)
5. CA Training mode exit: Mode Register Write to MR42
CA Training Timing
CK
MRW
#42
(CA Cal
Exit)
MRW
MRW
MRW
#41, #48 #41,#48 #41,#48
(Optional
4
4
)
NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
NOP
NOP NOP
)
(CA Cal
Entry)
(Optional
Cmd
CA CA
CAx CAx
R#
CAy CAy
CA CA
CA0-9
R
R
R#
CKE
tCACKEL
tCAMRD
tCAENT
tCACD
tADR
tADR
tCACKEH
tCAEXT
tMRZ
CAx
R
CAy
R
Even DQ
Odd DQ
CAx
R#
CAy
R#
NOTE 1 Unused DQ must be valid HIGH or LOW during data output period. Unused DQ may transition at the same time as the active DQ. DQS
must remain static and not transition.
NOTE 2 CA to DQ mapping change via MR 48 omitted here for clarity of the timing diagram. Both MR41 and MR48 training sequences must be
completed before exiting the training mode (MR42). To enable a CA to DQ mapping change, CKE must be driven HIGH prior to issuance of
the MRW 48 command. For details, please refer to CA Training Sequence section.
NOTE 3 Because data out control is asynchronous and will be an analog delay from when all the CA data is available, tADR and tMRZ are defined
from CK falling edge.
NOTE 4 It is recommended to hold the CA bus stable for one cycle prior to and one cycle after the issuance of the MRW CA Training Entry
Command to ensure setup and hold timings on the CA bus.
NOTE 5 Clock phase may be adjusted in CA training mode while is high and CKE is low resulting in an irregular clock with shorter/longer periods
and pulse widths.
NOTE 6 Optional MRW 41, 48, 42 command and CA calibration command are allowed. To complement these optional commands, optional
assertions are also allowed. All timing must comprehend these optional assertions:
a) tADR starts at the falling clock edge after the last registered assertion.
b) tCACD, tCACKEL, tCAMRD start with the rising clock edge of the last assertion.
c) tCAENT, tCAEXT need to be met by the first assertion.
d) tMRZ will be met after the falling clock edge following the first assertion with exit (MRW#42) command.
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The LPDDR3 SDRAM may not properly recognize a Mode Register Write command at normal operation frequency before
CA Training is finished. Special encodings are provided for CA Training mode enable/disable. MR41 and MR42
encodings are selected so that rising edge and falling edge values are the same. The LPDDR3 SDRAM will recognize
MR41 and MR42 at normal operation frequency even before CA timing adjustments have been made. Calibration data
will be output through DQ pins. CA to DQ mapping is described in below table.
After timing calibration with MR41 is finished, users will issue MRW to MR48 and calibrate remaining CA pins (CA4 and
CA9) using (DQ0/DQ1and DQ8/DQ9) as calibration data output pins.
CA Training mode enable ( MR41(29H, 0010 1001b), OP=A4H(1010 0100b) )
Clock edge
CK rising edge
CK falling edge
CA0
CA1
CA2
CA3
CA4
H
CA5
CA6
CA7
H
CA8
CA9
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
CA Training mode disable (MR42(2AH,0010 1010b),OP=A8H(1010 1000b) )
Clock edge
CK rising edge
CK falling edge
CA0
CA1
CA2
CA3
CA4
CA5
H
CA6
CA7
H
CA8
CA9
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
CA to DQ mapping (CA Training mode enabled with MR41)
Clock edge
CK rising edge
CK falling edge
CA0
DQ0
DQ1
CA1
DQ2
DQ3
CA2
DQ4
DQ5
CA3
DQ6
DQ7
CA5
DQ8
DQ9
CA6
DQ10
DQ11
CA7
DQ12
DQ13
CA8
DQ14
DQ15
CA Training mode enable ( MR48(30H, 0011 0000b), OP=C0H(1100 0000b) )
Clock edge
CK rising edge
CK falling edge
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
H
CA9
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
CA to DQ mapping (CA Training mode is enabled with MR48)
Clock edge
CK rising edge
CK falling edge
CA4
DQ0
DQ1
CA9
DQ8
DQ9
NOTE 1 Other DQs must have valid output (either HIGH or LOW).
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MRW - Write Leveling Mode
In order to provide for improved signal integrity performance, the LPDDR3 SDRAM provides a write leveling feature to
compensate for timing skew, affecting timing parameters such as tDQSS, tDSS, and tDSH.
The memory controller uses the write leveling feature to receive feedback from the SDRAM allowing it to adjust the clock
to data strobe signal relationship for each DQS/ signal pair. The memory controller performing the leveling must have
adjustable delay setting on DQS/ signal pair to align the rising edge of DQS signals with that of the clock signal at the
DRAM pin. The DRAM asynchronously feeds back CLK, sampled with the rising edge of DQS signals. The controller
repeatedly delays DQS signals until a transition from 0 to 1 is detected. The DQS signals delay established through this
exercise ensures the tDQSS specification can be met.
All data bits carry the leveling feedback to the controller (DQ[15:0] for x16 configuration, DQ[31:0] for x32 configuration).
All DQS signals must be leveled independently.
The LPDDR3 SDRAM enters into write leveling mode when mode register MR2[7] is set HIGH. When entering write
leveling mode, the state of the DQ pins is undefined. During write leveling mode, only NOP commands are allowed, or
MRW command to exit write leveling operation. Upon completion of the write leveling operation, the DRAM exits from
write leveling mode when MR2[7] is reset LOW.
The controller will drive DQS LOW and HIGH after a delay of tWLDQSEN. After time tWLMRD, the controller
provides DQS signal input which is used by the DRAM to sample the clock signal driven from the controller. The delay
time tWLMRD(max) is controller dependent. The DRAM samples the clock input with the rising edge of DQS and provides
asynchronous feedback on all the DQ bits after time tWLO. The controller samples this information and either increment
or decrement the DQS and/or delay settings and launches the next DQS/ pulse. The sample time and trigger
time is controller dependent. Once the following DQ/ transition is sampled, the controller locks the strobe delay
settings, and write leveling is achieved for the device.
Write Leveling Timing
tWLS tWLH
tWLS tWLH
CK
CA CA
MRW
CA CA
CA0-9
Cmd
NOP NOP NOP NOP NOP NOP NOP NOP NOP MRW NOP NOP NOP
NOP
tWLDQSEN
DQS
DQ
tWLMRD
tWLO
tDQSH tDQSL
tWLO
tMRD
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On-Die Termination
ODT (On-Die Termination) is a feature of the LPDDR3 SDRAM that allows the DRAM to turn on/off termination resistance
for each DQ, DQS/ and DM signal via the ODT control pin. The ODT feature is designed to improve signal integrity of
the memory channel by allowing the DRAM controller to independently turn on/off termination resistance for any or all
DRAM devices. The ODT pin directly controls ODT operation and is not sampled by the clock.
The ODT feature is turned off and not supported in self-refresh and deep power down modes. The DRAM will also disable
termination during read operations. ODT operation can optionally be enabled during power down mode via a mode
register.
ODT
VDDQ
To other
RTT
Switch
circuitry
like
RCV, ...
DQ, DQS, DM
The switch is enabled by the internal ODT control logic, which uses the external ODT pin and other mode register control
information. The value of RTT is determined by the settings of mode register bits.
ODT Mode Register
The switch is enabled by the internal ODT control logic, which uses the external ODT pin and other mode register control
information. The value of RTT is determined by the settings of Mode Register bits. The ODT pin will be ignored if the
Mode Register MR11 is programmed to disable ODT, in self-refresh, in deep power down, in CKE power down (mode
register option) and during read operations.
Asynchronous ODT
When enabled, the ODT feature is controlled asynchronously based on the status of the ODT pin. ODT is off under any of
the following conditions:
– ODT is disabled through MR11[1:0]
– DRAM is performing a read operation (RD or MRR)
– DRAM is in power down mode and MR11[2] is zero
– DRAM is in self-refresh or deep power down modes.
– DRAM is in CA Training Mode.
In asynchronous ODT mode, the following timing parameters apply when ODT operation is controlled by the ODT pin:
tODToff,min,max, tODTon,min,max.
Minimum RTT turn-on time (tODTon,min) is the point in time when the device termination circuit leaves high impedance
state and ODT resistance begins to turn on. Maximum RTT turn on time (tODTon,max) is the point in time when the ODT
resistance is fully on. tODTon,min and tODTon,max are measured from ODT pin high.
Minimum RTT turn-off time (tODToff,min) is the point in time when the device termination circuit starts to turn off the ODT
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4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
resistance. Maximum ODT turn off time (tODToff,max) is the point in time when the on-die termination has reached high
impedance. tODToff,min and tODToff,max are measured from ODT pin low.
ODT During Read Operations (RD or MRR)
During read operations, LPDDR3 SDRAM will disable termination and disable ODT control through the ODT pin. After
read operations are completed, ODT control is resumed through the ODT pin (if ODT mode is enabled).
ODT During Power Down
When MR11 OP<2> is zero, termination control through the ODT pin will be disabled when the DRAM enters CKE power
down. After a power down command is registered, termination will be disabled within a time window specified by
tODTd,min,max. After a power down exit command is registered, termination will be enabled within a time window
specified by tODTe,min,max.
Minimum RTT disable time (tODTd,min) is the point in time when the device termination circuit is no longer be controlled
by the ODT pin. Maximum ODT disable time (tODTd,max) is the point in time when the on-die termination will be in high
impedance.
Minimum RTT enable time (tODTe,min) is the point in time when the device termination circuit will no longer be in high
impedance. The ODT pin shall control the device termination circuit after maximum ODT enable time
(tODTe,max) is satisfied. When MR11[2] is enabled and MR11[1:0] are non zero, ODT operation is supported during CKE
power down with ODT control through the ODT pin.
ODT During Self Refresh
LPDDR3 SDRAM disables the ODT function during self refresh. After a self refresh command is registered, termination
will be disabled within a time window specified by tODTd,min,max. After a self refresh exit command is registered,
termination will be enabled within a time window specified by tODTe,min,max.
ODT During Deep Power Down
LPDDR3 SDRAM disables the ODT function during deep power down. After a deep power down command is registered,
termination will be disabled within a time window specified by tODTd,min,max.
ODT During CA Training and Write Leveling
During CA Training Mode, LPDDR3 SDRAM will disable on-die termination and ignore the state of the ODT control pin.
For ODT operation during Write Leveling mode, refer to below table for termination activation and deactivation for DQ and
DQS/. If ODT is enabled, the ODT pin must be high, in Write Leveling mode.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
DRAM Termination Function in Write Leveling Mode
DQS/
termination
OFF
ODT pin
DQ termination
de-asserted
asserted
OFF
OFF
ON
ODT States Truth Table
Write
Enabled
Enabled
Read/DQ Cal
Disabled
ZQ Cal
Disabled
Disabled
CA Training
Disabled
Write Level
Disabled
DQ Termination
DQS Termination
Disabled
Disabled
Enabled
NOTE 1 ODT is enabled with MR11[1:0]=01b, 10b, or 11b and ODT pin HIGH. ODT is disabled with MR11[1:0]=00b or ODT pin LOW.
Asynchronous ODT Timing Example for RL = 12
Automatic ODT Timing During READ Operation Example for RL = m
NOTE 1 The automatic RTT turn-off delay, tAODToff, is referenced from the rising edge of “RL-2” clock at Tm-2.
NOTE 2 The automatic RTT turn-on delay, tAODTon, is referenced from the rising edge of “RL+ BL/2” clock at Tm+4
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
ODT Timing During Power Down, Self Refresh, Deep Power Down Entry/Exit Example
NOTE 1 Upon exit of Deep Power Down mode, a complete power-up initialization sequence is required.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Power-Down
Power-down is entered synchronously when CKE is registered LOW and is HIGH at the rising edge of clock. A NOP
command must be driven in the clock cycle following the power-down command. CKE must not go LOW while MRR,
MRW, READ, or WRITE operations are in progress. CKE can go LOW while any other operations such as row activation,
PRECHARGE, auto precharge, or REFRESH are in progress, but the power-down IDD specification will not be applied
until such operations are complete.
Entering power-down deactivates the input and output buffers, excluding CK, , and CKE. To ensure that there is
enough time to account for internal delay on the CKE signal path, two NOP commands are required after CKE is driven
LOW, this timing period is defined as tCPDED. CKE LOW will result in deactivation of input receivers after tCPDED has
expired. In power-down mode, CKE must be held LOW; all other input signals are “Don’t Care.” CKE LOW must be
maintained until tCKE is satisfied. VREFCA must be maintained at a valid level during power-down.
VDDQ can be turned off during power-down. If VDDQ is turned off, VREFDQ must also be turned off. Prior to exiting
power-down, both VDDQ and VREFDQ must be within their respective minimum/maximum operating ranges.
No refresh operations are performed in power-down mode. The maximum duration in power-down mode is only limited by
the refresh requirements outlined in section “REFRESH Command”.
The power-down state is exited when CKE is registered HIGH. The controller must drive HIGH in conjunction with
CKE HIGH when exiting the power-down state. CKE HIGH must be maintained until tCKE,min is satisfied. A valid,
executable command can be applied with power-down exit latency tXP after CKE goes HIGH. Power-down exit latency is
defined in the AC timing parameter table.
If power-down occurs when all banks are idle, this mode is referred to as idle powerdown; if power-down occurs when
there is a row active in any bank, this mode is referred to as active power-down.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Basic Power-Down Entry and Exit Timing
2 x tCK(min)
CK
tIHCKE tCPDED
tISCKE
Input clock frequency may be changed or the
input clock stopped during power-down1.
tIHCKE
tCKE(min)
tISCKE
CKE
tXP(min)
tCKE(min)
Enter
PD
Exit
PD
Valid
NOP NOP
NOP
N
Valid
Cmd
Enter power-down mode
Exit power-down mode
NOTE 1 Input clock frequency can be changed or the input clock can be stopped or floated during power-down, provided that
upon exiting power-down, the clock is stable and within specified limits for a minimum of 2 clock cycles prior to
power-down exit and the clock frequency is between the minimum and maximum specified frequency for the speed
grade in use.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
CKE-Intensive Environment
CK
tCKE
tCKE
tCKE
tCKE
CKE
REFRESH-to-REFRESH Timing in CKE-Intensive Environments
CK
tCKE
tXP
tCKE
tREFI
tCKE
tXP
tCKE
CKE
REFRESH
REFRESH
Cmd
NOTE 1 The pattern shown can repeat over an extended period of time. With this pattern, all AC and DC timing and voltage
specifications with temperature and voltage drift are ensured.
READ to Power-Down Entry
T0
T1
T2
Tx
Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9
CK
Cmd
RD
CKE1,2
tISCKE
RL
DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT
DQ
DQS
NOTE 1 CKE must be held HIGH until the end of the burst operation.
NOTE 2 CKE can be registered LOW at RL + RU(tDQSCK(MAX)/tCK) + BL/2 + 1 clock cycles after the clock on which the READ
command is registered.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
READ with Auto Precharge to Power-Down Entry
T0
T1
T2
Tx
Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9
CK
PRE 4
Cmd
RD w/AP
tISCKE
CKE1,2
BL/2 3
RL
DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT
DQ
DQS
NOTE 1 CKE must be held HIGH until the end of the burst operation.
NOTE 2 CKE can be registered LOW at RL + RU(tDQSCK/tCK)+ BL/2 + 1 clock cycles after the clock on which the READ command is
registered.
NOTE 3 BL/2 with tRTP = 7.5ns and tRAS (MIN) is satisfied.
NOTE 4 Start internal PRECHARGE.
WRITE to Power-Down Entry
T0
T1
Tm
Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tx
Tx+1 Tx+2 Tx+3 Tx+4
CK
Cmd
WRITE
WL
CKE1
tISCKE
BL/2
DIN DIN DIN DIN DIN DIN DIN DIN
DQ
tWR
DQS
NOTE 1 CKE can be registered LOW at WL + 1 + BL/2 + RU(tWR/tCK) clock cycles after the clock on which the WRITE command is
registered.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
WRITE with Auto Precharge to Power-Down Entry
T0
T1
Tm
Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tx
Tx+1 Tx+2 Tx+3 Tx+4
CK
PRE2
Cmd
WRITE w/AP
CKE1
tISCKE
WL
DIN DIN DIN DIN DIN DIN DIN DIN
DQ
tWR
DQS
NOTE 1 CKE can be registered LOW at WL + 1 + BL/2 + RU(tWR/tCK) + 1 clock cycles after the WRITE command is registered.
NOTE 2 Start internal PRECHARGE.
REFRESH Command to Power-Down Entry
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK
REFRESH
Cmd
tCKE
CKE1
tIHCKE
tISCKE
NOTE 1 CKE can go LOW tIHCKE after the clock on which the REFRESH command is registered.
ACTIVATE Command to Power-Down Entry
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK
ACTIVATE
Cmd
tCKE
CKE1
tIHCKE
tISCKE
NOTE 1 CKE can go LOW tIHCKE after the clock on which the ACTIVATE command is registered.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
PRECHARGE Command to Power-Down Entry
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK
PRE
tCKE
Cmd
CKE1
tIHCKE
tISCKE
NOTE 1 CKE can go LOW tIHCKE after the clock on which the PRECHARGE command is registered.
MRR to Power-Down Entry
T0
T1
T2
Tx
Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9
CK
MRR
Cmd
CKE1
tISCKE
RL
DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT
DQ
DQS
NOTE 1 CKE can be registered LOW RL + RU(tDQSCK/tCK)+ BL/2 + 1 clock cycles after the clock on which the MRR command is
registered.
MRW to Power-Down Entry
T11
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CK
MRW
Cmd
tMRW
tISCKE
CKE1
NOTE 1 CKE can be registered LOW tMRW after the clock on which the MRW command is registered.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Deep Power-Down (DPD)
Deep power-down (DPD) is entered when CKE is registered LOW with LOW, CA0 HIGH, CA1 HIGH, and CA2 LOW
at the rising edge of the clock. All banks must be in the idle state with no activity on the data bus prior to entering the DPD
mode. During DPD, CKE must be held LOW. The contents of the SDRAM will be lost upon entry into DPD mode.
In DPD mode, all input buffers except CKE, all output buffers, and the power supply to internal circuitry are disabled within
the device. To ensure that there is enough time to account for internal delay on the CKE signal path, two NOP commands
are required after CKE is driven LOW, this timing period is defined as tCPDED.
CKE LOW will result in deactivation of command and address receivers after tCPDED has expired. VREFDQ can be at
any level between 0 and VDDQ, and VREFCA can be at any level between 0 and VDDCA during DPD. All power supplies,
including VREF, must be within the specified limits prior to exiting DPD (see “AC and DC Operating Conditions”).
DPD mode is exited when CKE is registered HIGH, while meeting tISCKE, and the clock must be stable. The device must
be fully re-initialized using the power-up initialization sequence. The SDRAM is ready for normal operation after the
initialization sequence is completed. For the description of ODT operation and specifications during DPD entry and exit,
see “ODT During Deep Power Down”.
Deep Power-Down Entry and Exit Timing
2 x tCK(min)
CK
tIHCKE tCPDED
tISCKE
tIHCKE
Input clock frequency may be changed or the
input clock stopped during Deep
Power-Down.
CKE
tISCKE
tRP
tDPD
tINIT3=200us(min)1,2
Exit
Enter
DPD
Cmd NOP
NOP NOP
NOP N P RESET
DPD
Enter DPD mode
Exit DPD mode
NOTE 1 The initialization sequence can start at any time after Tx + 1.
NOTE 2 tINIT3 and Tx + 1 and refer to timings in the initialization sequence.
NOTE 3 Input clock frequency may be changed or the input clock can be stopped or floated during deep power-down, provided
that upon exiting deep power-down, the clock is stable and within specified limits for a minimum of 2 clock cycles prior to
deep power-down exit and the clock frequency is between the minimum and maximum frequency for the particular
speed grade.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Input Clock Frequency Changes and Clock Stop Events
The device supports input clock frequency change during CKE LOW under the following conditions:
• tCK(abs)min is met for each clock cycle;
• Refresh requirements apply during clock frequency change;
• During clock frequency change, only REFab or REFpb commands may be executing;
• Any Activate or Precharge commands have executed to completion prior to changing the frequency;
• The related timing conditions (tRCD, tRP) have been met prior to changing the frequency;
• The initial clock frequency shall be maintained for a minimum of 2 clock cycles after CKE goes LOW;
• The clock satisfies tCH(abs) and tCL(abs) for a minimum of 2 clock cycles prior to CKE going HIGH.
After the input clock frequency is changed and CKE is held HIGH, additional MRW commands may be required to set the
WR, RL etc. These settings may need to be adjusted to meet minimum timing requirements at the target clock frequency.
The device supports clock stop during CKE LOW under the following conditions:
• CK is held LOW and is held HIGH or both are floated during clock stop;
• Refresh requirements apply during clock stop;
• During clock stop, only REFab or REFpb commands may be executing;
• Any Activate or Precharge commands have executed to completion prior to stopping the clock;
• The related timing conditions (tRCD, tRP) have been met prior to stopping the clock;
• The initial clock frequency shall be maintained for a minimum of 2 clock cycles after CKE goes LOW;
• The clock satisfies tCH(abs) and tCL(abs) for a minimum of 2 clock cycles prior to CKE going HIGH.
The device supports input clock frequency change during CKE HIGH under the following conditions:
• tCK(abs)min is met for each clock cycle;
• Refresh requirements apply during clock frequency change;
• Any Activate, Read, Write, Precharge, Mode Register Write, or Mode Register Read commands must have executed
to completion, including any associated data bursts prior to changing the frequency;
• The related timing conditions (tRCD, tWR, tWRA, tRP, tMRW, tMRR, etc.) have been met prior to changing the
frequency;
• shall be held HIGH during clock frequency change;
• During clock frequency change, only REFab or REFpb commands may be executing;
• The LPDDR3 SDRAM is ready for normal operation after the clock satisfies tCH(abs) and tCL(abs) for a minimum of
2*tCK + tXP.
After the input clock frequency is changed, additional MRW commands may be required to set the WR, RL etc. These
settings may need to be adjusted to meet minimum timing requirements at the target clock frequency.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
LPDDR3 devices support clock stop during CKE HIGH under the following conditions:
• CK is held LOW and is held HIGH during clock stop;
• shall be held HIGH during clock clock stop;
• Refresh requirements apply during clock stop;
• During clock stop, only REFab or REFpb commands may be executing;
• Any Activate, Read, Write, Precharge, Mode Register Write, or Mode Register Read commands must have executed
to completion, including any associated data bursts prior to stopping the clock;
• The related timing conditions (tRCD, tWR, tWRA, tRP, tMRW, tMRR, etc.) have been met prior to stopping the clock;
• The LPDDR3 SDRAM is ready for normal operation after the clock is restarted and satisfies tCH(abs) and tCL(abs) for
a minimum of 2*tCK + tXP.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
NO OPERATION (NOP) Command
The purpose of the NOP command is to prevent the device from registering any unwanted commands issued between
operations. A NOP command can only be issued at clock cyclen when the CKE level is constant for clock cycle N-1 and
clock cycle N. A NOP command has two possible encodings:
1. HIGH at the clock rising edge N.
2. LOW and CA0, CA1, CA2 HIGH at the clock rising edge N.
The NOP command will not terminate a previous operation that is still in process, such as a burst READ or WRITE cycle.
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LPDDR3 4Gb(SDP)/8Gb(DDP) SDRAM
4Gb:NT6CL128M32CQ(M), NT6CL256M16CM
8Gb:NT6CL256T32CQ(M), NT6CL128T64CR(4)
Revision History
Version
Page
Modified
Description
Released
01/2018
02/2018
02/2018
1.2
All
-
-
-
Official Release
Align the title
Align the title
1.3
P22
1.4
P22, 26
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