NT6DN16M16CG-S2_技术文档

Nanya Technology Corp.

Commercial LPDDR 1Gb SDRAM

NT6DM64M16BD / NT6DM32M32BC

Commercial Mobile DDR 1Gb SDRAM

Features

 Data Integrity

 JEDEC LPDDR Compliant

- Low Power Consumption

- DRAM built-in Temperature Sensor for

Temperature Compensated Self Refresh (TCSR)

- 2n Prefetch Architecture

- Auto Refresh and Self Refresh Modes

 Power Saving Mode

- Differential clock inputs (CK and )

- Double-data rate on DQs, DQS and DM

- Commands entered on each positive CK edge

- Deep Power Down Mode (DPD)

- Partial Array Self Refresh (PASR)

- Clock Stop capability during idle period

 LVCMOS Interface and Power Supply

- VDD/VDDQ=1.70 to 1.95V

- DQS edge-aligned with data for READs;

center-aligned with data for WRITEs

- Status Register Read (SRR)

 Signal Integrity

- Configurable DS for system compatibility

Options



Speed Grade (CL-TRCD-TRP)¹

 Temperature Range (T_c)

- 333 Mbps / 3-3-3

- 400 Mbps / 3-3-3

- Commercial Grade = -25℃~85℃

Programmable Functions

 Burst Type (Sequential, Interleaved)

 Driver Strength (full, 1/2, 3/4, 1/4)



CAS Latency (2, 3)

Burst Length (2, 4, 8, 16)

Packages / Density Information

Density and Addressing

1Gb

Lead-free RoHS compliance and Halogen-free

Item

1Gb

Length x Width

(mm)

Ball pitch

(mm)

(Org. / Package)

Addressing

Organization

Number of banks

Bank Address

Auto precharge

Row Address

Column Address

tRFC(ns) ²

Standard

Reduced Page Size

64M x 16 32M x 32

32M x 32

4

60-ball

64Mx16

8.00 x 9.00

0.80

BA0,BA1 BA0,BA1

BA0,BA1

A10/AP

A0-A13

A0-A8

72

VFBGA

A10/AP

A0-A13

A0-A9

72

A10/AP

A0-A12

A0-A9

72

90-ball

32Mx32

8.00 x 13.00

VFBGA

tREFI (µs) ³

7.8

NOTE 1 The timing specification of high speed bin is backward compatible with low speed bin.

NOTE 2 Violating tRFC specification will induce malfunction.

NOTE 3 tREFI values for all bank refresh is within temperature specification(<= 85℃).

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NTC has the rights to change any specifications or product without notification.

Commercial LPDDR 1Gb SDRAM

NT6DM64M16BD / NT6DM32M32BC

Descriptions

The 1Gb Mobile LPDDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 1,073,741,824 bits. It

is internally configured as a quad-bank DRAM.

The 1Gb chip is organized as 16Mbit x 4 banks x 16 I/O or 8Mbit x 4 banks x 32 I/O device. Each of the x16’s 268,435,456-bit

banks is organized as 16,384 rows by 1,024 columns by 16 bits. Each of the x32’s 268,435,456-bit banks is organized as

8,192 rows by 1,024 columns by 32 bits. In the reduced page-size option, each of the x32’s 268,435,456-bit banks are

organized as 16,384 rows by 512 columns by 32 bits. To achieve high-speed operation, our LPDDR SDRAM uses the double

data rate architecture and adopt 2n-prefetch interface designed to transfer two data per clock cycle at the I/O pins.

The chip is designed to comply with all key Mobile Double-Data-Rate SDRAM key features. All of the control and address

inputs are synchronized with a pair of externally supplied differential clocks, and latched at the cross point of differential

clocks (CK rising and 

e input data is registered at both edges of DQS, and the output data is referenced to

both edges of DQS, as well as to both edges of CK. DQS is a bidirectional data strobe signal, transmitted by the LPDDR

SDRAM during READs (edge-aligned with data), and by the memory controller during WRITEs (center-aligned with data).

LPDDR SDRAM, Read and Write access are burst oriented. The address bits registered coincident with the ACTIVE

command to select the row in the specific bank. And then the address bits registered with the READ or WRITE command to

select the starting column location in the bank for the burst access. The burst length can be programmed as 2, 4, 8 or 16. An

Auto Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of burst access.

LPDDR SDRAM with Auto Refresh mode, and the Power-down mode for power saving. And the Deep Power Down Mode

can achieve the maximum power reduction by removing the memory array power within Low Power DDR SDRAM. With this

feature, the system can cut off almost all DRAM power without adding the cost of a power switch and giving up month-board

power-line layout flexibility. Self Refresh mode with Temperature Compensated Self Refresh (TCSR) and Partial Array Self

Refresh (PASR) options, which allow users to achieve additional power saving. The TCSR and PASR options can be

programmed via the extended mode register. The two features may be combined to achieve even greater power saving. The

DLL that is typically used on standard DDR devices is not necessary on the Mobile DDR SDRAM. It has been omitted to save

power.

All inputs are LVCMOS compatible. Devices will have a V_DDand V_DDQsupply of 1.8V (nominal).

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Commercial LPDDR 1Gb SDRAM

NT6DM64M16BD / NT6DM32M32BC

Ordering Information

Lead-free RoHS compliance and Halogen-free

Speed

Organization

Part Number

Package

TCK

(ns)

Clock Data Rate

CL

(MHz)

(Mb/s/pin)

Commercial Grade

5.0

6.0

5.0

6.0

200

166

200

166

400

333

400

333

3

NT6DM64M16BD-T1

60 ball

90 ball

64MX16

32MX32

NT6DM64M16BD-T3

NT6DM32M32BC-T1

NT6DM32M32BC-T3

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Commercial LPDDR 1Gb SDRAM

NT6DM64M16BD / NT6DM32M32BC

NANYA Mobile Component/Wafer Part Numbering Guide

6D 64M16 T1

NT

M

B

D

Grade

NANYA

N/A =Commercial Grade

Technology

Speed

Product Family

LPSDR

6S =LPSDR SDRAM

S1 = 166MHz @ CL=3

S2 = 133MHz @ CL=3

LPDDR

6D =LPDDR SDRAM

6V =LPDDR2-S2 SDRAM

6T = LPDDR2-S4 SDRAM

6X = LPSDR/DDR comb

6Y = LPDDR2-S2/S4 comb

T1 = 5.0ns @ CL=3

T2 = 5.4ns @ CL=3

T3 = 6.0ns @ CL=3

T4 = 7.5ns @ CL=3

T5 = T3 & S2

Interface & Power (V_DD& V_DDQ

)

T6 = T1 & S1

M = LVCMOS (1.8V, 1.8V)

LPDDR2-S2

N = LVCMOS (1.8V, 1.2V)

T1 = 5.0ns @ RL=3

T3 = 6.0ns @ RL=3

LPDDR2-S4

Interface & Power (V_DD1, V_DD2, V_DDQ, V_DDCA

L = HSUL_12 (1.8V, 1.2V, 1.2V, 1.2V)

)

G0 = 1.8ns @ RL=8

G1 = 2.5ns @ RL=6

G2 = 3.0ns @ RL=5

G3 = 3.7ns @ RL=4

G4 = 5.0ns @ RL=3

H = HSUL_12 (1.8V, 1.35V, 1.2V, 1.2V)

Organization (Depth, Width): M=Mono; T=DDP¹; F=QDP²

256Mb = 16M16 = 8M32 = 8M32R³

Package Code

G = 54-Ball BGA (LPSDR, x16)

D = 60-Ball BGA (LPDDR, x16)

K = 90-Ball BGA (LPSDR, x32)

C = 90-Ball BGA (LPDDR, x32)

A = 79-Ball BGA (LPDDR2, x16)

I = 134-Ball BGA (LPDDR2, x32)

Q = 168-Ball PoP-FBGA (LPDDR2)

R = 216-Ball PoP-FBGA (LPDDR2)

3 = 240-Ball PoP-FBGA (LPDDR2)

5= 220-Ball PoP-FBGA (LPDDR2)

0 = Wafer (KGD)

512Mb = 32M16 = 16M32 = 16M32R

Device Version

A = 1^stversion

B = 2^ndversion

C = 3^rdversion

1Gb = 64M16 = 32M32 = 32M32R

2Gb = 256M8 = 128M16 = 64M32 = 64M32R

4Gb = 256M16 = 128M32 = 64T64

8Gb = 128F64 = 256F32 = 128T64 = 256T32

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Nanya Technology Corporation ©

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Commercial LPDDR 1Gb SDRAM

NT6DM64M16BD / NT6DM32M32BC

Ball Assignments and Package Outline Drawing

LPDDR SDRAM X16 in VFBGA-60 (8mm X 9mm)

1

2

3

7

8

9

VSS

DQ15 VSSQ VDDQ

DQ0

VDD

A

B

C

D

E

F

VDDQ DQ13 DQ14

VSSQ DQ11 DQ12

DQ1

DQ3

DQ5

DQ7

A13

DQ2

DQ4

DQ6

VSSQ

VDDQ

Test¹

VDDQ

DQ9

DQ10

DQ8

NC

VSSQ UDQS

LDQS VDDQ

VSS

CKE

A9

UDM

CK

LDM

AS

BA0

A0

VDD

RAS

BA1

A1



WE

G

H

J

A11

A7

A12

A8

S

A6

A10/AP

A2

VSS

A4

A5

A3

VDD

K

Note 1: Test must be tied to VSS or VSSQ in normal operations.

Unit: mm

* BSC(Basic Spacing between Center)

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Version 1.6

06 / 2014

Nanya Technology Corporation ©

Commercial LPDDR 1Gb SDRAM

NT6DM64M16BD / NT6DM32M32BC

Ball Assignments and Package Outline Drawing

LPDDR SDRAM X32 in VFBGA-90 (8mm X 13mm)

Note 1: A13 is only available for reduced page-size configuration.

Note 2: Test must be tied to VSS or VSSQ in normal operations.

Unit: mm

* BSC(Basic Spacing between Center)

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Nanya Technology Corporation ©

Commercial LPDDR 1Gb SDRAM

NT6DM64M16BD / NT6DM32M32BC

Ball Descriptions

Symbol ¹

Type

Function

Clock: CK and  are differential clock inputs. All address and control input signals are sampled

on the crossing of the positive edge of CK and negative edge of . Input and output data is

referenced to the crossing of CK and  (both directions of crossing). Internal clock signals are

derived from CK, .

CK, 

Input

Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device

input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and

SELF REFRESH operation (all banks idle), or ACTIVE POWERDOWN (row ACTIVE in any bank).

CKE is synchronous for all functions except for SELF REFRESH EXIT, which is achieved

asynchronously. Input buffers, excluding CK,  and CKE, are disabled during power-down and

self refresh mode which are contrived for low standby power consumption.

CKE

Input

Chip Select: S enables (registered LOW) and disables (registered HIGH) the command decoder.

All commands are masked when S is registered HIGH. S provides for external bank selection on

systems with multiple banks. S is considered part of the command code.

S

Input

RAS, AS, WE

Command Inputs: RAS, AS and WE (along with S) define the command being entered.

Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is

sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of

DQS. Although DM pins are input-only, the DM loading matches the DQ and DQS loading.

DM

For x16,

LDM, UDM

For x32,

DM0-DM3

For x16 devices, LDM corresponds to the data on DQ0-DQ7, UDM corresponds to the data on

DQ8-DQ15.

Input

For x32 devices, DM0 corresponds to the data on DQ0-DQ7, DM1 corresponds to the data on

DQ8-DQ15, DM2 corresponds to the data on DQ16-DQ23, and DM3 corresponds to the data on

DQ24-DQ31.

DQ

Data Bus: Bi-directional Input / Output data bus.

For x16:

DQ0-DQ15

For x32:

Input/output

DQ0-DQ31

Data Strobe: Output with read data, input with write data. Edge-aligned with read data. Centered

DQS

with write data to capture write data.

For x16:

For x16 device, LDQS corresponds to the data on DQ0-DQ7, UDQS corresponds to the data on

DQ8-DQ15.

LDQS, UDQS

For x32:

Input/output

For x32 device, DQS0 corresponds to the data on DQ0-DQ7, DQS1 corresponds to the data on

DQ8-DQ15, DQS2 corresponds to the data on DQ16-DQ23, and DQS3 corresponds to the data on

DQ24-DQ31.

DQS0-DQS3

Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE, or

PRECHARGE command is being applied. BA0 and BA1 also determine which mode register is

loaded during a LOAD MODE REGISTER command.

BA0, BA1

Input

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Commercial LPDDR 1Gb SDRAM

NT6DM64M16BD / NT6DM32M32BC

Symbol ¹

Type

Function

Address Inputs: provide the row address for ACTIVE commands, and the column address and

auto precharge bit(A10) for READ or WRITE commands, to select one location out of the memory

array in the respective bank. During a PRECHARGE command, A10 determines whether the

PRECHARGE applies to one bank (A10 LOW, bank selected by Bank Address Inputs) or all banks

(A10 HIGH). The address inputs also provide the opcode during a MODE REGISTER SET

command.

A13 - A0

Input

NC

-

No Connect: These pins should be left unconnected.

DQ Power Supply: Isolated on the die for improved noise immunity.

DQ Ground: Provide isolated ground to DQs for improved noise immunity.

Power Supply

VDDQ

VSSQ

VDD

Supply

VSS

Ground

Notes :

1. The differential signal may show up in a different symbol but it indicates to the same thing. e.g., /CK = CK# =  = CKb,

/DQS = DQS# = S = DQSb

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Commercial LPDDR 1Gb SDRAM

NT6DM64M16BD / NT6DM32M32BC

Functional Block Diagram – LPDDR 64Mx16

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Commercial LPDDR 1Gb SDRAM

NT6DM64M16BD / NT6DM32M32BC

Functional Block Diagram – LPDDR 32Mx32

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Nanya Technology Corporation ©

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Commercial LPDDR 1Gb SDRAM

NT6DM64M16BD / NT6DM32M32BC

Simplified State Diagram

Abbrev.

Function

Abbrev.

Function

Abbrev.

Function

ACT

READ

Active

LMR

CKEH

CKEL

DPD

Load mode register

Exit power-down

PRE

PREALL

AREF

SREF

Precharge

Read (w/o Autoprecharge)

Read (w/ Autoprecharge)

Write (w/o Autoprecharge)

Write (w/ Autoprecharge)

Load extended mode register

Precharge all banks

Auto Refresh

READ A

WRITE

WRITE A

EMR

Enter power-down

Enter Deep Power Down

Exit Deep Power Down

Burst Terminate

Enter self refresh

Exit self refresh

Status Register Read

DPDX

BST

SREFX

SRR

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Commercial LPDDR 1Gb SDRAM

NT6DM64M16BD / NT6DM32M32BC

Electrical Specifications

Absolute Maximum DC Ratings

Symbol

Parameter

Min

Max

2.4

Units

V_DD/ V_DDQ

V_DD/ V_DDQsupply voltage relative to Vss

-1.0

V

2.4 or (V_DDQ+ 0.3V),

Whichever is less

+150

Vin

Voltage on any pin relative to Vss

Storage Temperature (plastic)

-0.5

-55

V

Tstg

C

Notes:

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This

is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the

operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended

periods may affect reliability.

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM.

3. V_DDand V_DDQmust be within 300mV of each other at all times. V_DDQmust not exceed V_DD

.

Input / Output Capacitance

Symbol

Parameter

Input capacitance: CK, 

Min

Max

Unit

Notes

CCK

CDCK

CI

1.5

-

3.0

0.25

3.0

pF

Input capacitance delta: CK, 

2

3

Input capacitance, all other input-only pins

Input capacitance delta, all other input-only pins

Input/output capacitance, DQ, DM, DQS

Input/output capacitance delta, DQ, DM, DQS

1.5

-

CDI

0.5

CIO

3.0

-

5.0

0.5

CDIO

Notes:

1. These values are guaranteed by design and are tested on a sample base only.

2. These capacitance values are for single monolithic devices only. Multiple die packages will have parallel capacitive loads.

3. Input capacitance is measured according to JEP147 procedure for measuring capacitance using a vector network analyzer.

VDD, VDDQ are applied and all other pins (except the pin under test) floating. DQs should be in high impedance state.

This may be achieved by pulling CKE to low level.

4. Although DM is an input-only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS

pins. This is required to match signal propagation times of DQ, DQS and DM in the system.

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Commercial LPDDR 1Gb SDRAM

NT6DM64M16BD / NT6DM32M32BC

AC/DC Electrical Characteristics and Operating Conditions

Apply Note 1-3 to whole the table.

Symbol

V_DD

Parameter

Min

1.70

Max

1.95

Unit

V

Notes

Supply voltage

-

V_DDQ

I/O Supply voltage

V

Address and Command inputs

V_IH

V_IL

Input voltage high

Input voltage low

0.8 x V_DDQ

-0.3

V_DDQ+ 0.3

0.2 x V_DDQ

V

-

Clock inputs (CK, )

V_IN

V_ID(DC)

V_ID(AC)

V_IX

DC input voltage

-0.3

V_DDQ+ 0.3

V_DDQ+ 0.6

0.6 x V_DDQ

V

-

DC input differential voltage

AC Input Differential Voltage

AC Differential Crosspoint Voltage

0.4 x V_DDQ

0.6 x V_DDQ

0.4 x V_DDQ

2

3

Data inputs

V_IH(DC)

V_IL(DC)

V_IH(AC)

V_IL(AC)

DC input high voltage

0.7 x V_DDQ

-0.3

V_DDQ+ 0.3

0.3 x V_DDQ

V_DDQ+ 0.3

0.2 x V_DDQ

V

-

DC input low voltage

AC input high voltage

AC input low voltage

0.8 x V_DDQ

-0.3

Data outputs

V_OH

V_OL

DC output high voltage: Logic 1 (I_OH= -0.1mA)

DC output low voltage: Logic 0 (I_OL= -0.1mA)

0.9 x V_DDQ

-

V

-

0.1 x V_DDQ

Leakage current

Input leakage current

Any input 0 ≦ V_IN≦ V_DD

,

I_I

-1

-5

1

5

uA

All other pins not under test = 0V

Output leakage current

I_OZ

DQs are disabled; 0 ≦ V_OUT≦ V_DDQ

Notes:

1.All voltages referenced to VSS and VSSQ must be same potential.

2.VID(DC) and VID(AC) are the magnitude of the difference between the input level on CK and the input level on .

3.The value of VIX is expected to be 0.5 * VDDQ and must track variations in the DC level of the same.

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Commercial LPDDR 1Gb SDRAM

NT6DM64M16BD / NT6DM32M32BC

IDD Specifications and Measurement Conditions (64Mx16)

Notes 1–5 apply to all the parameters/conditions in this table

T1(-5)

T3(-6)

Symbol

Parameter/Condition

Unit Notes

LPDDR400 LPDDR333

Operating one bank active-precharge current:

100

90

IDD0

mA

6

tRC = tRCmin; tCK = tCKmin; CKE is HIGH; S is HIGH between valid commands;

address inputs are SWITCHING; data bus inputs are STABLE

Precharge power-down standby current:

400/600

IDD2P

IDD2PS

IDD2N

uA

7,8

7

all banks idle, CKE is LOW; S is HIGH, tCK = tCKmin;

(Typ./Max.)

address and control inputs are SWITCHING; data bus inputs are STABLE

Precharge power-down standby current with clock stopped:

all banks idle, CKE is LOW; S is HIGH, CK = LOW, CK = HIGH;

address and control inputs are SWITCHING; data bus inputs are STABLE

Precharge non power-down standby current:

400/600

(Typ./Max.)

18

15

8

mA

9

all banks idle, CKE is HIGH; S is HIGH, tCK = tCKmin;

address and control inputs are SWITCHING; data bus inputs are STABLE

Precharge non power-down standby current with clock stopped:

all banks idle, CKE is HIGH; S is HIGH, CK = LOW, CK = HIGH;

address and control inputs are SWITCHING; data bus inputs are STABLE

Active power-down standby current:

14

IDD2NS

IDD3P

9

5

8

one bank active, CKE is LOW; S is HIGH, tCK = tCKmin;

address and control inputs are SWITCHING; data bus inputs are STABLE

Active power-down standby current with clock stopped:

IDD3PS

mA

one bank active, CKE is LOW; S is HIGH, CK = LOW, CK = HIGH;

address and control inputs are SWITCHING; data bus inputs are STABLE

Active non power-down standby current:

20

16

18

14

IDD3N

IDD3NS

IDD4R

mA

6

one bank active, CKE is HIGH; S is HIGH, tCK = tCKmin;

address and control inputs are SWITCHING; data bus inputs are STABLE

Active non power-down standby current with clock stopped:

one bank active, CKE is HIGH; S is HIGH, CK = LOW, CK = HIGH;

address and control inputs are SWITCHING; data bus inputs are STABLE

Operating burst read current:

135

120

one bank active; BL=4; CL=3; tCK = tCKmin; continuous read bursts; IOUT = 0 mA

address inputs are SWITCHING; 50% data change each burst transfer

Operating burst write current:

IDD4W

one bank active; BL=4; tCK = tCKmin; continuous write bursts;

address inputs are SWITCHING; 50% data change each burst transfer

Auto Refresh current:

100

15

100

15

IDD5

mA

10

tRC = 140ns

tCK = tCKmin; burst refresh; CKE is HIGH;

address and control inputs are SWITCHING; data bus inputs are

IDD5A

10,11

tRC = tREFI

STABLE

25^oC

10

25

uA

7,13

7

Deep power-down current:

IDD8

85^oC

Address and control inputs are STABLE; data bus inputs are STABLE

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Nanya Technology Corporation ©

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Commercial LPDDR 1Gb SDRAM

NT6DM64M16BD / NT6DM32M32BC

IDD Specifications and Measurement Conditions (32Mx32)

Notes 1–5 apply to all the parameters/conditions in this table

T1(-5)

T3(-6)

Symbol

Parameter/Condition

Unit Notes

LPDDR400 LPDDR333

Operating one bank active-precharge current:

100

90

IDD0

mA

6

tRC = tRCmin; tCK = tCKmin; CKE is HIGH; S is HIGH between valid commands;

address inputs are SWITCHING; data bus inputs are STABLE

Precharge power-down standby current:

400/600

IDD2P

IDD2PS

IDD2N

uA

7,8

7

all banks idle, CKE is LOW; S is HIGH, tCK = tCKmin;

(Typ./Max.)

address and control inputs are SWITCHING; data bus inputs are STABLE

Precharge power-down standby current with clock stopped:

all banks idle, CKE is LOW; S is HIGH, CK = LOW, CK = HIGH;

address and control inputs are SWITCHING; data bus inputs are STABLE

Precharge non power-down standby current:

400/600

(Typ./Max.)

18

15

8

mA

9

all banks idle, CKE is HIGH; S is HIGH, tCK = tCKmin;

address and control inputs are SWITCHING; data bus inputs are STABLE

Precharge non power-down standby current with clock stopped:

all banks idle, CKE is HIGH; S is HIGH, CK = LOW, CK = HIGH;

address and control inputs are SWITCHING; data bus inputs are STABLE

Active power-down standby current:

14

IDD2NS

IDD3P

9

5

8

one bank active, CKE is LOW; S is HIGH, tCK = tCKmin;

address and control inputs are SWITCHING; data bus inputs are STABLE

Active power-down standby current with clock stopped:

IDD3PS

mA

one bank active, CKE is LOW; S is HIGH, CK = LOW, CK = HIGH;

address and control inputs are SWITCHING; data bus inputs are STABLE

Active non power-down standby current:

20

16

18

14

IDD3N

IDD3NS

IDD4R

mA

6

one bank active, CKE is HIGH; S is HIGH, tCK = tCKmin;

address and control inputs are SWITCHING; data bus inputs are STABLE

Active non power-down standby current with clock stopped:

one bank active, CKE is HIGH; S is HIGH, CK = LOW, CK = HIGH;

address and control inputs are SWITCHING; data bus inputs are STABLE

Operating burst read current:

150

135

one bank active; BL=4; CL=3; tCK = tCKmin; continuous read bursts; IOUT = 0 mA

address inputs are SWITCHING; 50% data change each burst transfer

Operating burst write current:

IDD4W

one bank active; BL=4; tCK = tCKmin; continuous write bursts;

address inputs are SWITCHING; 50% data change each burst transfer

Auto Refresh current:

100

15

100

15

IDD5

mA

10

tRC = 140ns

tCK = tCKmin; burst refresh; CKE is HIGH;

address and control inputs are SWITCHING; data bus inputs are

IDD5A

10,11

tRC = tREFI

STABLE

25^oC

10

25

uA

7,13

7

Deep power-down current:

IDD8

Address and control inputs are STABLE; data bus inputs are STABLE

85^oC

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Nanya Technology Corporation ©

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Commercial LPDDR 1Gb SDRAM

NT6DM64M16BD / NT6DM32M32BC

IDD6 Self-refresh and Partial Array Refresh) current

Notes 1–5, 7, and 12 apply to all the parameters/conditions in this table

Symbol

Parameter/Condition

Temperature

PASR

Typical

Max

Unit

Full Array

1/2 Array

1/4 Array

Full Array

1000

700

560

500

1200

─

uA

85℃

Self refresh current:

─

CKE=LOW; ^tCK=^tCK(min); Address

and control inputs are stable; Data

bus inputs are stable.

IDD6

─

45℃

1/2 Array

1/4 Array

400

350

─

uA

IDD Notes:

1. All voltages referenced to V_SS.

2. Tests for I_DDmay be conducted at nominal supply voltage levels, but the related specifications and device operation are guaranteed for

the full voltage and temperature range specified.

3. Timing and I_DDtests may use a V_IL-to-V_IHswing of up to 1.5V in the test environment, but input timing is still referenced to V_DDQ/2 (or,

to the crossing point for CK and ). The output timing reference voltage level is V_DDQ/2.

4. I_DDis dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time with the outputs open.

5. I_DDspecifications are tested after the device is properly initialized, and are averaged at the defined cycle rate.

6. MIN (^tRC or ^tRFC) for IDD measurements is the smallest multiple of ^tCK that meets the minimum absolute value for the respective

parameter. ^tRAS (MAX) for IDD measurements is the largest multiple of ^tCK that meets the maximum absolute value for ^tRAS.

7. Measurement is taken 500ms after entering into this operating mode to provide settling time for the tester.

8. V_DDmust not vary more than 4 % if CKE is not active while any bank is active.

9. IDD2N specifies DQ, DQS, and DM to be driven to a valid HIGH or LOW logic level.

10. CKE must be active (HIGH) during the entire time a REFRESH command is executed. From the time the AUTO REFRESH command is

registered, CKE must be active at each rising clock edge until ^tRFC later.

11. This limit is a nominal value and does not result in a fail. CKE is HIGH during REFRESH command period (^tRFC [MIN]) else CKE is LOW

(for example, during standby).

12. Values for IDD6 85°C are guaranteed for the entire temperature range.

13. IDD8 are typical values. IDD8 is measured at 25℃.

16

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Commercial LPDDR 1Gb SDRAM

NT6DM64M16BD / NT6DM32M32BC

Electrical Characteristics and Recommended AC Operating Conditions

Note 1-9 apply to all of the parameters

T1 (-5 )

T3 (-6 )

LPDDR400

LPDDR333

Symbol

Parameter

Unit Notes

Min

2.0

Max

5.0

6.5

-

Min

2.0

6

Max

5.5

6.5

-

CL=3

CL=2

CL=3

CL=2

tAC

tCK

Access window of DQs from CK, 

ns

2.0

5.0

Clock cycle time

ns

12

-

12

-

tCH

tCL

CK high-level width

CK low-level width

0.45

0.55

0.45

0.55

tCK

tCH,

tCL

tCH,

tCL

tHP

Half-clock period

-

ns

10,11

tCKE

CKE min. pulse width (high and low)

1*tCK

-

1*tCK

-

ns

CL=3

CL=2

2.0

-

5.0

6.5

0.4

0.5

2.0

-

5.5

tDQSCK Access window of DQS from CK, 

6.5

tDQSQ DQS-DQ skew, DQS to last DQ valid, per group, per access

0.45

0.65

20

11

tQHS

tQH

n/a

Data Hold Skew Factor

-

tHP -

tQHS

tHP -

tQHS

DQ-DQS hold, DQS to first DQ to go non-valid, per access

Data Valid output window (DVW)

-

ns

11

tQH – tDQSQ

ns

CL=3

Data-out high-z window from CK, 

CL=2

-

5.0

-

5.5

tHZ

tLZ

19

6.5

ns

Data-out Low-z window from CK, 

1.0

0.9

0.5

0.4

CL+1

2

-

1.0

0.9

0.5

0.4

CL+1

2

-

ns

19

23

CL=3

1.1

tCK

ms

ns

tRPRE DQS read preamble

CL=2

1.1

tRPST DQS read postamble

0.6

tSRC

tSRR

tTQ

Read of SRR to next valid command

SRR-to-READ

-

Internal temperature sensor valid temperature output enable

DQ and DM input hold time relative to DQS (fast slew rate)

DQ and DM input hold time relative to DQS (slow slew rate)

DQ and DM input setup time relative to DQS (fast slew rate)

DQ and DM input setup time relative to DQS (slow slew rate)

DQ and DM input pulse width (for each input)

2

31

tDHf

0.48

0.58

0.48

0.58

1.8

0.6

0.7

0.6

0.7

2.1

13,14,15

13,14,16

13,14,15

13,14,16

17

tDHs

tDSf

ns

tDSs

tDIPW

ns

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Nanya Technology Corporation ©

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Commercial LPDDR 1Gb SDRAM

NT6DM64M16BD / NT6DM32M32BC

T1 (-5 )

T3 (-6 )

LPDDR400

LPDDR333

Symbol

Parameter

Unit Notes

Min

0.75

0.4

0.2

0.25

0

Max

Min

0.75

0.4

0.2

0.25

0

Max

tDQSS WRITE command to first DQS latching transition

tDQSH DQS input high pulse width

1.25

tCK

0.6

tDQSL DQS input low pulse width

0.6

tDSH

tDSS

DQS falling edge from CK rising – hold time

DQS falling edge from CK rising – setup time

-

tWPRE DQS write preamble

-

tWPRES DQS write preamble setup time

tWPST DQS write postamble

-

ns

tCK

ns

21

0.4

0.9

1.1

0.9

1.1

2.3

2

0.6

0.4

1.1

1.2

1.1

1.2

2.6

2

0.6

22

tIHf

tIHs

Address and Control input hold time (fast slew rate)

-

15,18

16,18

15,18

16,18

17

Address and Control input hold time (slow slew rate)

Address and Control input setup time (fast slew rate)

Address and Control input setup time (slow slew rate)

Address and Control input pulse width

-

ns

tISf

-

ns

tISs

-

ns

tIPW

tMRD

tRAS

-

ns

Load MODE Register command cycle time

ACTIVE to PRECHARGE command

-

tCK

ns

40

70,000

41.8

70,000

ACTIVE to ACTIVE / ACTIVE to AUTO REFRESH command

period

tRC

55

-

60

-

ns

tRCD

tRP

ACTIVE to READ or WRITE delay

PRECHARGE command period

15

-

18

-

ns

-

24

15

-

18

-

tRRD

tDAL

tWR

ACTIVE bank-a to ACTIVE bank-b command

Auto precharge write recovery + precharge time

Write recovery time

10

-

12

-

26

15

ns

tCK

ns

ms

us

ns

tWTR

tXP

Internal WRITE to READ command delay

Exit power-down mode to first valid command

Exit SELF REFRESH to first valid command

Refresh period

2

-

1

-

6

-

6

-

28

27

tXSR

tREF

tREFI

tRFC

Notes:

112.5

-

112.5

-

64

7.8

-

64

7.8

-

Average periodic refresh interval

Auto Refresh command period

29,30

72

1. All voltages referenced to Vss.

2. All parameters assume proper device initialization.

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Version 1.6

06 / 2014

Nanya Technology Corporation ©

Commercial LPDDR 1Gb SDRAM

NT6DM64M16BD / NT6DM32M32BC

3. Tests for AC timing, and electrical AC and DC characteristics may be conducted at nominal supply voltage levels, but the related

specifications and device operation are guaranteed for the full voltage range specified.

4. The circuit shown below represents the timing reference load used in defining the relevant timing parameters of the device. It is

not intended to be either a precise representation of the typical system environment or a depiction of the actual load presented

by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to system

environment. Specifications are correlated to production test conditions (generally a coaxial transmission line terminated at the

tester electronics). For the half-strength driver with a nominal 10pF load, parameters ^tAC and ^tQH are expected to be in the same

range. However, these parameters are not subject to production test but are estimated by design/characterization. Use of IBIS or

other simulation tools for system design validation is suggested.

5. The CK,  input reference voltage level (for timing referenced to CK, ) is the point at which CK and  cross; the input

reference voltage level for signals other than CK,  is V_DDQ/2.

6. The timing reference voltage level is VDDQ/2.

7. AC and DC input and output voltage levels are defined in the section for Electrical Characteristics and AC/DC operating conditions.

8. A CK/ differential slew rate of 2.0 V/ns is assumed for all parameters.

9. CAS latency definition: with CL = 3 the first data element is valid at (2 * tCK + tAC) after the clock at which the READ command

was registered (see figure); with CL = 2 the first data element is valid at (tCK + tAC) after the clock at which the READ command

was registered; with CL = 4 the first data element is valid at (3 * tCK + tAC) after the clock at which the READ command was

registered.

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Commercial LPDDR 1Gb SDRAM

NT6DM64M16BD / NT6DM32M32BC

10. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this

value can be greater than the minimum specification limits for tCL and tCH)

11. tQH = tHP - tQHS, where tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCL, tCH).

tQHS accounts for 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of DQS on one

transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew

and output pattern effects, and p-channel to n-channel variation of the output drivers.

12. The only time that the clock frequency is allowed to change is during clock stop, power-down or self-refresh modes.

13. The transition time for DQ, DM and DQS inputs is measured between VIL(DC) to VIH(AC) for rising input signals, and VIH(DC) to

VIL(AC) for falling input signals.

14. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal

transitions through the DC region must be monotonic.

15. Input slew rate ≥ 1.0 V/ns.

16. Input slew rate ≥ 0.5 V/ns and < 1.0 V/ns.

17. These parameters guarantee device timing but they are not necessarily tested on each device.

18. The transition time for address and command inputs is measured between VIH and VIL.

19. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a

specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).

20. tDQSQ consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any

given cycle.

21. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before the corresponding

CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes

were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,

DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.

22. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but

system performance (bus turnaround) will degrade accordingly.

23. A low level on DQS may be maintained during High-Z states (DQS drivers disabled) by adding a weak pull-down element in the

system. It is recommended to turn off the weak pull-down element during read and write bursts (DQS drivers enabled).

24. Speed bin (CL - tRCD - tRP) = 3 - 3 - 3

25. Speed bin (CL - tRCD - tRP) = 3 - 4 - 4 (all speed bins except LPDDR200)

26. tDAL = (tWR/tCK) + (tRP/tCK): for each of the terms, if not already an integer, round to the next higher integer.

27. There must be at least two clock pulses during the tXSR period.

28. There must be at least one clock pulse during the tXP period.

29. tREFI values are dependent on density and bus width.

30. A maximum of 8 Refresh commands can be posted to any given LPDDR, meaning that the maximum absolute interval between

any Refresh command and the next Refresh command is 8*tREFI.

31. It’s not supported for package level.

20

Version 1.6

Nanya Technology Corporation ©

06 / 2014

Commercial LPDDR 1Gb SDRAM

NT6DM64M16BD / NT6DM32M32BC

OUTPUT SLEW RATE CHARACTERISTICS

PARAMETER

MIN

0.7

0.5

0.3

0.7

MAX

2.5

UNIT

V/ns

-

NOTES

Pull-up and Pull-Down Slew Rate for Full Strength Driver

Pull-up and Pull-Down Slew Rate for Three-Quarters Strength Driver

Pull-up and Pull-Down Slew Rate for Half Strength Driver

1,2

3

1.75

1.0

Output Slew rate Matching ratio (Pull-up to Pull-down)

NOTES:

1.4

1. Measured with a test load of 20 pF connected to VSSQ.

2. Output slew rate for rising edge is measured between VILD(DC) to VIHD(AC) and for falling edge between VIHD(DC) to VILD(AC).

3. The ratio of pull-up slew rate to pull-down slew rate is specified for the same temperature and voltage, over the entire

temperature and voltage range. For a given output, it represents the maximum difference between pull-up and pull-down

drivers due to process variation.

AC Overshoot/Undershoot Specification

PARAMETER

Maximum peak amplitude allowed for overshoot

SPECIFICATION

0.5 V

Maximum peak amplitude allowed for undershoot

0.5 V

The area between overshoot signal and VDD must be less than or equal to

The area between undershoot signal and GND must be less than or equal to

3 V-ns

NOTES:

1. This specification is intended for devices with no clamp protection and is guaranteed by design.

AC Overshoot and Undershoot Definition

21

Version 1.6

Nanya Technology Corporation ©

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Commercial LPDDR 1Gb SDRAM

NT6DM64M16BD / NT6DM32M32BC

OUTPUT DRIVE STRENGTH CHARACTERISTICS

THREE-QUARTERS DRIVE

STRENGTH

FULL DRIVE STRENGTH

HALF DRIVE STRENGTH

VOLTAGE

[V]

PULL-DOWN

CURRENT

[mA]

PULL-UP

CURRENT

[mA]

PULL-DOWN

CURRENT

[mA]

PULL-UP

CURRENT

[mA]

PULL-DOWN

CURRENT

[mA]

PULL-UP

CURRENT

[mA]

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

0.00

0.10

0.20

0.30

0.40

0.50

0.60

0.70

0.80

0.85

0.90

0.95

1.00

1.10

1.20

1.30

1.40

1.50

1.60

1.70

1.80

1.90

0

2.8

18.53

26.8

-2.8

-18.53

-26.8

1.27

2.55

3.82

5.09

6.36

7.64

8.91

10.16

10.8

—

8.42

-1.27

-2.55

-3.82

-5.09

-6.36

-7.64

-8.91

-10.16

-10.8

—

-8.42

1.96

12.97

18.76

22.96

25.94

28

-1.96

-3.92

-5.88

-7.84

-9.8

-12.97

-18.76

-22.96

-25.94

-28

5.6

-5.6

12.3

-12.3

3.92

8.4

32.8

-8.4

-32.8

14.95

16.84

18.2

-14.95

-16.84

-18.2

5.88

11.2

14

37.05

40

-11.2

-14

-37.05

-40

7.84

9.8

16.8

19.6

22.4

23.8

—

42.5

-16.8

-19.6

-22.4

-23.8

—

-42.5

19.3

-19.3

11.76

13.72

15.68

16.66

—

29.75

31.2

-11.76

-13.72

-15.68

-16.66

—

-29.75

-31.2

44.57

46.5

-44.57

-46.5

20.3

-20.3

21.2

-21.2

32.55

33.24

33.95

34.58

35.04

35.95

36.86

37.77

38.68

39.59

40.5

-32.55

-33.24

-33.95

-34.58

-35.04

-35.95

-36.86

-37.77

-38.68

-39.59

-40.5

47.48

48.5

-47.48

-48.5

21.6

-21.6

22

-22

49.4

-49.4

22.45

22.73

23.21

23.67

24.14

24.61

25.08

25.54

26.01

26.48

26.95

-22.45

-22.73

-23.21

-23.67

-24.14

-24.61

-25.08

-25.54

-26.01

-26.48

-26.95

50.05

51.35

52.65

53.95

55.25

56.55

57.85

59.15

60.45

61.75

-50.05

-51.35

-52.65

-53.95

-55.25

-56.55

-57.85

-59.15

-60.45

-61.75

41.41

42.32

43.23

-41.41

-42.32

-43.23

—

NOTES:

1. Based on nominal impedance of 25 Ohms (Full Drive), 55 Ohms (Half Drive) and 36 Ohms(Three-Quarters) at VDDQ/2

2. The full variation in driver current from minimum to maximum due to process, temperature and voltage will lie within the

outer bounding lines of the I-V curve.

3. The I-V current for the optional quarter drive strength is approximately 50% of the half drive strength.

4. The IV current for the Three-Quarters Strength Driver is approximately 70% of the full drive strength current.

5. Implementation and availability of Three-Quarters Strength Driver is optional for speed bins LPDDR333 and below.

22

Version 1.6

06 / 2014

Nanya Technology Corporation ©

Commercial LPDDR 1Gb SDRAM

NT6DM64M16BD / NT6DM32M32BC

I-V Curves for Full, Three-Quarters and Half Drive Strength

Characteristics are specified under best and worst process variation/conditions

70

50

30

10

3/4 - PD - Max

3/4 - PD - Min

3/4 - PU - Max

3/4 - PU - Min

Full - PD - Max

Full - PD - Min

Full - PU - Max

Full - PU - Min

Half - PD - Max

Half - PD - Min

Half - PU - Max

Half - PU - Min

0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.85 0.90 0.95 1.00 1.10 1.20 1.30 1.40 1.50 1.60 1.70 1.80 1.90

-10

-30

-50

-70

23

Version 1.6

Nanya Technology Corporation ©

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Commercial LPDDR 1Gb SDRAM

NT6DM64M16BD / NT6DM32M32BC

Basic Functionality

The LPDDR SDRAM is a high-speed CMOS, dynamic random access memory internally configured as a four-bank DRAM.

The double data rate architecture is essentially a 2n prefetch with an interface designed to transfer two data words per clock

cycle at the I/O pins. A single read or write access for the LPDDR SDRAM effectively consists of a single 2n-bit wide, one

clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at

the I/O pins.

Read and write access to the LPDDR SDRAM are burst oriented; access start at a selected location and continue for a

programmed number of locations in a programmed sequence. Operation begins with the registration of an ACTIVE command,

which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command

are used to select the bank and the row to be activated (BA0-BA1 select the bank; A0-A13 select the row). The address bits

registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the

burst operation. The Mobile DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4, 8, or 16. An auto

precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As

with standard DDR SDRAMs, the pipelined, multibank architecture of the Mobile DDR SDRAMs supports concurrent

operation, thereby providing high effective bandwidth by hiding row precharge and activation time.

An auto refresh mode is provided, along with a power saving power-down mode. Deep power-down mode is offered to

achieve maximum power reduction by eliminating the power of the memory array. Data will not be retained after device enters

deep power-down mode. Two self refresh features, temperature-compensated self refresh (TCSR) and partial array self

refresh (PASR), offer additional power saving. TCSR is controlled by the automatic on-chip temperature sensor. The PASR

can be customized using the extended mode register settings. The two features may be combined to achieve even greater

power saving. The DLL that is typically used on standard DDR devices is not necessary on the Mobile DDR SDRAM. It has

been omitted to save power.

Prior to normal operation, the LPDDR SDRAM must be initialized. The following sections provide detailed information

covering device initialization, register definition, command descriptions and device operation.

Initialization

LPDDR SDRAMs must be powered up and initialized in a predefined manner. Operations procedures other than

those specified may result in undefined operation. If there is any interruption to the device power, the initialization

routine should be followed. The steps to be followed for device initialization are listed below.

.

The Mode Register and Extended Mode Register do not have default values. If they are not programmed during

the initialization sequence, it may lead to unspecified operation. The clock stop feature is not available until the

device has been properly initialized from Steps 1 through 11.

24

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Nanya Technology Corporation ©

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Commercial LPDDR 1Gb SDRAM

NT6DM64M16BD / NT6DM32M32BC

The Following sequence is required for POWER UP and Initialization

1. Provide power, the device core power (VDD) and the device I/O power (VDDQ) must be brought up simultaneously to

prevent device latch-up. Although not required, it is recommended that VDD and VDDQ are from the same power source.

Also assert and hold Clock Enable (CKE) to a LV-CMOS logic high level

2. Once the system has established consistent device power and CKE is driven high, it is safe to apply stable clock

3. There must be at least 200 μs of valid clocks before any command may be given to the DRAM. During this time NOP or

DESELECT commands must be issued on the command bus.

4. Issue a PRECHARGE ALL command.

5. Provide NOPs or DESELECT commands for at least tRP time.

6. Issue an AUTO REFRESH command followed by NOPs or DESELECT command for at least tRFC time. Issue the second

AUTO REFRESH command followed by NOPs or DESELECT command for at least tRFC time. Note as part of the

initialization sequence there must be two auto refresh commands issued. The typical flow is to issue them at Step 6, but

they may also be issued between steps 10 and 11.

7. Using the MRS command, load the base mode register. Set the desired operating modes.

8. Provide NOPs or DESELECT commands for at least tMRD time.

9. Using the MRS command, program the extended mode register for the desired operating modes. Note the order of the

base and extended mode register programming is not important.

10. Provide NOP or DESELCT commands for at least tMRD time.

11. The DRAM has been properly initialized and is ready for any valid command.

Brief Description of Initialization Sequence

Step

1

Description for Initialization

VDD and VDDQ Ramp: CKE must be held high

2

Apply stable clocks

3

Wait at least 200 μs with NOP or DESELECT on command bus

PRECHARGE ALL

4

5

Assert NOP or DESELCT for tRP time

6

Issue two AUTOREFRESH commands each followed by NOP or DESELECT commands for tRFC time

Configure Mode Register

7

8

Assert NOP or DESELECT for tMRD time

Configure Extended Mode Register

9

10

11

Assert NOP or DESELECT for tMRD time

LPDDR SDRAM is ready for any valid command

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Initialization Sequence Diagram

NOTES:

1. PRE = PRECHARGE command; LMR = LOAD MODE REGISTER command; AR = AUTO REFRESH command; ACT = ACTIVE command.

2. NOP or DESELECT commands are required for at least 200us.

3. Other valid commands are possible.

4. NOPs or DESELECTs are required during this time.

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Initialization Sequence with Temperature Output Signal (Unsupported on package level)

TQ Signal Initialization

During device initialization the TQ signal output will be invalid until tTQ after the first MRS command. Following tTQ the TQ signal

will output logic-HIGH when the device temperature is greater than, or equal to, 85^oC, and logic-LOW when the device temperature

is less than 85^oC. There is no high-impedance state for this output signal.

Temperature Output Signal

The LPDDR-SDRAM device may include an optional temperature output signal (TQ). This signal is an asynchronous LVCMOS

output which outputs a logic-HIGH when the device temperature is greater than, or equal to, 85^oC and a logic-LOW when the

device temperature is less than 85^oC. There is no high-impedance state output from this signal. The TQ output signal activates

even during clock stop, power down, and self refresh modes. The signal is not valid during initialization and becomes valid after tTQ

following the first MRS command. When TQ output is logic-HIGH, tREF is specified to be 16ms. Additionally, AC parameters shall

be de-rated to 20% and DC parameters shall not be guaranteed.

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Register Definition

Mode Registers and Extended Mode Registers

The Mode Registers are used to define the specific mode of operation of the LPDDR SDRAM. This define includes the

definition of a burst length, a burst type, a CAS latency. Additionally, driver strength, Temperature Compensated Self Refresh

(TCSR), and Partial Array Self Refresh (PASR) are also user defined variables and must be programmed with an Extended

Mode Register Set (EMRS) command. The default value of the mode register is not defined, therefore the mode register must

be written after power up for proper operation. The Mode Register must be loaded when all banks are idle and no bursts are

t

progress, and the controller must wait the specific time MRD before initiating any subsequent operation. Violating either of

these requirements will result in unspecified operation. The MRS contents won’t be changed until it is reprogrammed, the

device goes into Deep Power-Down, or the device loses power.

The mode register is written by asserting low on S, RAS, AS, WE, BA0 and BA1, while controlling the state of address pins

A0~A13. The mode register contents can be changed using the same command and clock cycle requirements during normal

operation as long as all banks are in the precharge state. The mode register is divided into various fields depending on the

functionality. Burst length is defined by A0~A2 with options of 2, 4, 8 and 16 bit burst length. Burst address sequence type is

defined by A3 and CAS latency is defined by A4~A6. A7~A13 must be set to low to ensure future compatibility.

Standard Mode Register definition

BA1 BA0 A13 A12 A11 A10 A9

A8

↓

A7

↓

A6

↓

A5

↓

A4

↓

A3

↓

A2

↓

A1

↓

A0

↓

MR select

Operating Mode

CAS Latency

BL

BT

MR select

Burst Type

BA1 BA0

A3

Standard MR

Status Register

Extended MR

Reserved

Sequential

Interleaved

0

1

0

1

0

1

0

1

CAS Latency

Reserved

2

BL

Reserved

A6

0

1

A5

0

1

0

1

A4

0

1

0

1

0

1

0

1

A2

0

1

A1

A0

0

1

0

1

0

1

0

1

0

1

0

1

2

4

8

16

3

Reserved

A13-A9

Operating Mode

Normal Operation

All other states reserved

A8

0

-

A7

0

-

0

-

NOTE 1 : A logic 0 should be programmed to all unused / undefined address bits to ensure future compatibility.

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Burst Length, Type, and Order

Accesses within a given burst may be programmed to sequential or interleaved order. The burst type is selected via bit A3 as

above figure. The ordering of access within a burst is determined by the burst length, burst type, and the starting column

address. The burst length determines the maximum number of column locations that can be accessed for a given READ or

WRITE command. The burst length is defined by bits A0–A2. Burst length options include 2, 4, 8 or 16 for both the sequential

and the interleaved burst types.

When a READ or WRITE command is issued, a block of columns equal to the BL is effectively selected. All accesses for that

burst take place within this block, meaning that the burst will wrap when a boundary is reached. The block is uniquely selected

by A1–Ai when BL = 2, by A2–Ai when BL = 4, by A3–Ai when BL = 8, and by A4–Ai when BL = 16 (where Ai is the most

significant column address bit for a given configuration). The remaining (least significant) address bits are used to specify the

starting location within the block. The programmed BL applies to both READ and WRITE bursts. Accesses within a given

burst may be programmed to be either sequential or interleaved via the standard mode register.

Burst Type and Burst Order

Starting Column Address

Burst Type

Burst Length

A3

-

A2

-

A1

-

A0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Sequential

0,1

Interleaved

0,1

2

4

-

1,0

-

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0,1,2,3

-

1,2,3,0

1,0,3,2

-

2,3,0,1

-

3,0,1,2

3,2,1,0

-

0

1

0

1

0

1

0,1,2,3,4,5,6,7

-

1,2,3,4,5,6,7,0

1,0,3,2,5,4,7,6

-

2,3,4,5,6,7,0,1

2,3,0,1,6,7,4,5

-

3,4,5,6,7,0,1,2

3,2,1,0,7,6,5,4

8

-

4,5,6,7,0,1,2,3

-

5,6,7,0,1,2,3,4

5,4,7,6,1,0,3,2

-

6,7,0,1,2,3,4,5

6,7,4,5,2,3,0,1

-

7,0,1,2,3,4,5,6

7,6,5,4,3,2,1,0

0

1

0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F

1,2,3,4,5,6,7,8,9,A,B,C,D,E,F,0

2,3,4,5,6,7,8,9,A,B,C,D,E,F,0,1

3,4,5,6,7,8,9,A,B,C,D,E,F,0,1,2

4,5,6,7,8,9,A,B,C,D,E,F,0,1,2,3

5,6,7,8,9,A,B,C,D,E,F,0,1,2,3,4

6,7,8,9,A,B,C,D,E,F,0,1,2,3,4,5

7,8,9,A,B,C,D,E,F,0,1,2,3,4,5,6

8,9,A,B,C,D,E,F,0,1,2,3,4,5,6,7

9,A,B,C,D,E,F,0,1,2,3,4,5,6,7,8

A,B,C,D,E,F,0,1,2,3,4,5,6,7,8,9

B,C,D,E,F,0,1,2,3,4,5,6,7,8,9,A

C,D,E,F,0,1,2,3,4,5,6,7,8,9,A,B

D,E,F,0,1,2,3,4,5,6,7,8,9,A,B,C

E,F,0,1,2,3,4,5,6,7,8,9,A,B,C,D

F,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E

0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F

1,0,3,2,5,4,7,6,9,8,B,A,D,C,F,E

2,3,0,1,6,7,4,5,A,B,8,9,E,F,C,D

3,2,1,0,7,6,5,4,B,A,9,8,F,E,D,C

4,5,6,7,0,1,2,3,C,D,E,F,8,9,A,B

5,4,7,6,1,0,3,2,D,C,F,E,9,8,B,A

6,7,4,5,2,3,0,1,E,F,C,D,A,B,8,9

7,6,5,4,3,2,1,0,F,E,D,C,B,A,9,8

8,9,A,B,C,D,E,F,0,1,2,3,4,5,6,7

9,8,B,A,D,C,F,E,1,0,3,2,5,4,7,6

A,B,8,9,E,F,C,D,2,3,0,1,6,7,4,5

B,A,9,8,F,E,D,C,3,2,1,0,7,6,5,4

C,D,E,F,8,9,A,B,4,5,6,7,0,1,2,3

D,C,F,E,,9,8,B,A,5,4,7,6,1,0,3,2

E,F,C,D,A,B,8,9,6,7,4,5,2,3,0,1

F,E,D,C,B,A,9,8,7,6,5,4,3,2,1,0

16

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CAS Latency (CL)

The CAS Latency, or READ latency is the delay, in clock cycles, between the registration of a Read command and the

availability of the first bit of output data. CAS Latency is defined by bit A6~A4 in the standard mode register. If a READ

command is registered at a clock edge n, and the CAS latency is 3 clocks, the first data element will be valid at (n + 2tCK +

tAC). If a READ command is registered at a clock edge n, and the CAS latency is 2 clocks, the first data element will be valid

at (n + 1tCK + tAC).

Extended Mode Register definition

The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions

include output drive strength selection, Temperature Compensated Self Refresh (TCSR) and Partial Array Self Refresh

(PASR). TCSR and PASR are effective in Self Refresh mode only. The extended mode register is programmed via the LOAD

MODE REGISTER command with BA0=0 and BA1=1, and the information won’t be changed until it is reprogrammed, the

device goes into deep power-down mode, or the device loses power. The EMRS must be loaded when all banks are idle and

no bursts are in progress, and the controller must wait the specified time tMRD before initiating any subsequent operation.

Violating either of these requirements will result in unspecified operation. Address bits A0-A2 specify PASR, A3-A4 the TCSR,

A5-A6 the Drive Strength. A logic 0 should be programmed to all the undefined addresses bits to ensure future compatibility.

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Temperature Compensated Self Refresh (TCSR)

On this version of the LPDDR SDRAM, the internal temperature sensor is implemented to adjust the self refresh oscillator

automatically base on the case temperature. To maintain backward compatibility, the programming of TCSR bits no effect on

the device so the address bits, A3 and A4 are ignored (don’t care) during EMRS programming.

Partial-Array Self Refresh (PASR)

For further power savings during self refresh, the PASR feature may allow the self refresh to be restricted to a variable portion

of the total array. They are full array (default: banks 0, 1, 2, and 3), 1/2 array (banks 0 and 1) and 1/4 array (bank 0). Data

outside the defined area will be lost. Address bits A0 to A2 are used to set PASR.

Output Drive Strength

LPDDR SDRAM provides the option to control the drive strength of the output buffers for the smaller systems or point-to-point

environments. The value was selected based on the expected loading of the memory bus. Total four values provided, and

they are 25 ohm, 36ohm, 55ohm, and 80ohm internal impedance. They are full, three-quarter, one-half, and one-quarter drive

strengths, respectively.

BA1 BA0 A13 A12 A11 A10 A9

A8

↓

A7

↓

A6

↓

A5

↓

A4

↓

A3

↓

A2

↓

A1

↓

A0

↓

TCSR ¹

MR select

Operating Mode

DS

PASR

MR select

Driver Strength

Full

BA1 BA0

A7

0

1

A6

0

1

0

1

A5

0

1

0

1

0

1

0

1

Standard MR

Status Register

Extended MR

Reserved

0

1

0

1

0

1

Half

Quarter

Three-Quarters

Reserved

PASR

A2

A1

0

1

0

1

A0

0

1

0

1

0

1

0

1

All banks

0

1

Half array(BA1=0)

1/4 array(BA1=BA0=0)

Reserved

A13-A9

Operating Mode

Normal Operation

All other states reserved

A8

0

-

0

-

Extended Mode Register

NOTE 1: On-die temperature sensor is used in place of TCSR. Setting these bits will have no effect.

NOTE 2: A logic 0 should be programmed to all unused / undefined address bits to ensure future compatibility.

NOTE 3: Implementation and availability of Three-Quarters Strength Driver is optional for speed bins LPDDR333 and below.

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Status Read Register (SRR)

The status read register (SRR) is only for READ, and contains the specific die information such as density, device type, data

bus width, refresh rate, revision ID and manufactures. The SRR is read via the LOAD MODE REGISTER command with

BA0=1 and BA1=0. The sequence to perform an SRR command is as follows:

 The device had been properly initialized and in the idle or all banks precharge state.

 Issue a LMR command with BA [1:0] = “01”.

 Wait tSRR; only NOP or DESELECT commands are supported during this period.

 Issue a READ command with all address pins set to “0”.

 CAS latency cycles later, the device returns the registers data. The SRR read with fixed burst length 2, first bit of the burst

output SRR data, and second bit of the burst is “Don’t Care”.

t

 The next command to the SDRAM must be issued SRC after the SRR READ command is issued; only NOP or

DESELECT commands are supported during this period.

NOTES:

1. SRR can only be issued after power-up sequence is complete, and all banks are precharged and in the idle state.

2. NOP or DESELECT commands are required between LMR and READ command (tSRR) and between READ and next VALID

command (tSRC)

3. CAS latency is predetermined by the programming of the mode register. Here CL=3 as an example only.

4. Burst length is fixed to 2 for SRR regardless of the value programmed by the mode register.

5. The second bit of the data-out burst is a “Don’t Care”.

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Register Definition

Status Register Definition

NOTES:

1. Reserved bits should be set to zero for future compatibility.

2. Refresh multiplier is based on the memory device’s on-board temperature sensor. Required average periodic refresh interval =

tREFI x multiplier.

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LPDDR SDRAM Command Description and Operation

Command Truth Table

NANE (Function)

Abbr.

DESELECT

NOP

S RAS AS WE

BA

X

A10/AP ADDR

NOTES

DESELECT

H

L

X

H

L

X

H

L

X

H

L

X

2

NO OPERATION

X

ACTIVE (select bank and active row)

ACT

Valid

X

Row

L

Row

Col

X

READ (select bank, column, and start read burst)

READ with AP (read burst with Auto Precharge)

WRITE (select bank, column, and start write burst)

WRITE with AP (write burst with Auto Precharge)

BURST TERMINATE or enter Deep Power-Down

PRECHARGE (deactive row in selected bank)

PRECHARGE ALL (deactive rows in all banks)

AUTO REFRESH or enter SELF REFRESH

LOAD MODE REGISTER

READ

H

L

READA

WRITE

WRITEA

BST

L

H

3

L

H

3

4,5

6

H

L

X

PRE

L

Valid

X

L

X

PREALL

REFA / REFS

LMR

L

H

X

6

L

H

L

X

7,8,9

10

L

Valid

Op-code

NOTES:

1. All states and sequences not shown are illegal or reserved.

2. DESELECT and NOP are functionally interchangeable.

3. Autoprecharge is non-persistent. A10 High enables Auto Precharge, while A10 Low disables Autoprecharge

4. Burst Terminate applies to only Read bursts with Auto Precharge disabled. This command is undefined and should not be used for

Read with Auto Precharge enabled, and for Write bursts.

5. This command is BURST TERMINATE if CKE is High and DEEP POWER DOWN entry if CKE is Low.

6. If A10 is Low, bank address determines which bank is to be precharged. If A10 is High, all banks are precharged and BA0-BA1are

don’t care.

7. This command is AUTO REFRESH if CKE is High, and SELF REFRESH if CKE is low.

8. All address inputs and I/O are ‘don't care’ except for CKE. Internal refresh counters control bank and row addressing.

9. All banks must be precharged before issuing an AUTO-REFRESH or SELF REFRESH command.

10.BA0 and BA1 value select between MRS and EMRS.

11.CKE is HIGH for all commands shown except SELF REFRESH and DEEP POWER-DOWN.

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DM Operation Truth Table

Function

Write Enable

Write Inhibit

DM

L

DQ

Valid

X

Notes

1,2

H

1,2

NOTES:

1. Used to mask write data, provided coincident with the corresponding data.

2. All states and sequences not shown are reserved and/or illegal.

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CKE Truth Table

CKE

Command (n)

Action (n)

-Result

Current State

Notes

RAS, AS, WE, S

CKE n-1

CKE n

Power Down

L

X

Maintain Power Down

Maintain Self Refresh

Maintain Deep Power Down

Exit Power Down

Self Refresh

X

Deep Power Down

Power Down

L

X

L

H

L

NOP or DESELECT

AUTO REFRESH

BURST TERMINATE

5, 6, 9

5, 7, 10

5, 8

Self Refresh

L

Exit Self Refresh

Deep Power Down

All Banks Idle

L

Exit Deep Power Down

Precharge Power Down Entry

Active Power Down Entry

Self Refresh Entry

H

5

Bank(s) Active

All Banks Idle

L

5

L

All Banks Idle

L

Deep Power Down Entry

See the other Truth Tables

H

See the other Truth Tables

NOTES:

1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.

2. Current state is the state of LPDDR immediately prior to clock edge n.

3. COMMANDn is the command registered at clock edge n, and ACTIONn is the result of COMMANDn.

4. All states and sequences not shown are illegal or reserved.

5. DESELECT and NOP are functionally interchangeable.

6. Power Down exit time (tXP) should elapse before a command other than NOP or DESELECT is issued.

7. SELF REFRESH exit time (tXSR) should elapse before a command other than NOP or DESELECT is issued.

8. The Deep Power-Down exit procedure must be followed as discussed in the Deep Power-Down section of the Functional

Description.

9. The clock must toggle at least once during the tXP period.

10.The clock must toggle at least once during the tXSR time.

Basic Timing Parameters for Commands

NOTE 1: Input = A0 – An, BA0, BA1, CKE, S, RAS, AS, WE; An = Address bus MSB.

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Current State Bank n Truth Table (command to Bank n)

Command

Action (n)

-Result

Current State

Notes

S

RAS AS

WE

Description

H

L

X

H

L

X

H

L

X

H

L

DESELECT (NOP)

NOP

Continue previous operation

Select and Active row

Any

Idle

ACTIVE

L

AUTO REFRESH

MODE REGISTER SET

READ

Auto refresh

10

L

Mode register set

H

L

H

L

Select column & start read burst

Select column & start write burst

Deactive row in bank or banks

Select column & start new read burst

Select column & start write burst

Truncate read burst, start precharge

Burst terminate

Row Active

L

WRITE

H

L

PRECHARGE

READ

4

H

L

H

L

5,6

L

WRITE

5,6,13

READ

(AP disable)

H

L

PRECHARGE

BURST TERMINTE

READ

H

L

11

5,6,12

5,6

H

L

Select column & start read burst

Select column & start new write burst

Truncate write burst, start precharge

WRITE

L

WRITE

(AP disable)

H

L

PRECHARGE

12

NOTES:

1. The table applies when both CKEn-1 and CKEn are HIGH, and after tXSR or tXP has been met if the previous state was Self Refresh or

Power Down.

2. DESELECT and NOP are functionally interchangeable.

3. All states and sequences not shown are illegal or reserved.

4. This command may or may not be bank specific. If all banks are being precharged, they must be in a valid state for precharging.

5. A command other than NOP should not be issued to the same bank while a READ or WRITE burst with Auto Precharge is enabled.

6. The new Read or Write command could be Auto Precharge enabled or Auto Precharge disabled.

7. Current State Definitions:

-

Idle: The bank has been precharged, and tRP has been met.

Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts / accesses and no register accesses

are in progress.

-

Read: A READ burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

Write: a WRITE burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

8. The following states must not be interrupted by a command issued to the same bank. DESELECT or NOP commands or allowable

commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other

bank are determined by its current state and Truth Table - Current State Bank n - Command to Bank n/m.

-

Precharging: starts with the registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will be

in the idle state.

-

Row Activating: starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be in

the ‘row active’ state.

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-

Read with AP Enabled: starts with the registration of the READ command with Auto Precharge enabled and ends when tRP has

been met. Once tRP has been met, the bank will be in the idle state.

Write with AP Enabled: starts with registration of a WRITE command with Auto Precharge enabled and ends when tRP has been

met. Once tRP is met, the bank will be in the idle state.

9. The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied to each

positive clock edge during these states.

-

Refreshing: starts with registration of an AUTO REFRESH command and ends when tRFC is met. Once tRFC is met, the device will

be in an ‘all banks idle’ state.

Accessing Mode Register: starts with registration of a MODE REGISTER SET command and ends when tMRD has been met. Once

tMRD is met, the device will be in an ‘all banks idle’ state.

Precharging All: starts with the registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, the bank

will be in the idle state.

10.Not bank-specific; requires that all banks are idle and no bursts are in progress.

11.Not bank-specific. BURST TERMINATE affects the most recent read burst, regardless of bank.

12.Requires appropriate DM masking.

13.A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMINATE must be used to end

the READ prior to asserting a WRITE command.

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Current State Bank n Truth Table (command to Bank m)

Command

Action (n)

-Result

Current State

Notes

S

RAS AS

WE

Description

H

L

X

L

X

H

X

L

X

H

X

H

L

X

H

X

H

L

DESELECT (NOP)

NOP

Continue previous operation

Any command allowed to bank m

Select and activate row

Select column & start read burst

Select column & start write burst

Precharge

Any

Idle

ANY

ACTIVE

Row Activating,

Active, or

H

L

READ

8

L

WRITE

Precharging

H

L

PRECHARGE

ACTIVE

L

H

L

Select and activate row

Select column & start read burst

Select column & start write burst

Precharge

H

L

READ

8

READ

(AP disable)

L

WRITE

8,10

H

L

PRECHARGE

ACTIVE

L

H

L

Select and activate row

Select column & start read burst

Select column & start write burst

Precharge

H

L

READ

8,9

8

WRITE

(AP disable)

L

WRITE

H

L

PRECHARGE

ACTIVE

L

H

L

Select and activate row

Select column & start read burst

Select column & start write burst

Precharge

H

L

READ

5,8

Read

(AP enabled)

L

WRITE

5,8,10

H

L

PRECHARGE

ACTIVE

L

H

L

Select and activate row

Select column & start read burst

Select column & start write burst

Precharge

H

L

READ

5,8

Write

(AP enabled)

L

WRITE

H

L

PRECHARGE

NOTES:

1. The table applies when both CKEn-1 and CKEn are HIGH, and after tXSR or tXP has been met if the previous state was Self Refresh

or Power Down.

2. DESELECT and NOP are functionally interchangeable.

3. All states and sequences not shown are illegal or reserved.

4. Current State Definitions:

-

Idle: the bank has been precharged, and tRP has been met.

Row Active: a row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses

are in progress.

-

Read: a READ burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

Write: a WRITE burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

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5. Read with AP enabled and Write with AP enabled: the Read with Auto Precharge enabled or Write with Auto Precharge enabled

states can be broken into two parts: the access period and the precharge period. For Read with AP, the precharge period is

defined as if the same burst was executed with Auto Precharge disabled and then followed with the earliest possible

PRECHARGE command that still accesses all the data in the burst. For Write with AP, the precharge period begins when tWR

ends, with tWR measured as if Auto Precharge was disabled. The access period starts with registration of the command and

ends where the precharge period (or tRP) begins. During the precharge period of the Read with AP enabled or Write with AP

enabled states, ACTIVE, PRECHARGE, READ, and WRITE commands to the other bank may be applied; during the access period,

only ACTIVE and PRECHARGE commands to the other banks may be applied. In either case, all other related limitations apply

(e.g. contention between READ data and WRITE data must be avoided).

Min. delay

From Command

To Command

(w/ concurrent Auto Precharge)

READ or READ w/ AP

WRITE or WRITE w/ AP

PRECHARGE

[1 + (BL/2)] tCK + tWTR

(BL/2) tCK

1 tCK

Write w/ AP

ACTIVE

1 tCK

READ or READ w/ AP

WRITE or WRITE w/ AP

PRECHARGE

(BL/2) tCK

[CL + (BL/2)] tCK

1 tCK

READ w/ AP

ACTIVE

1 tCK

6. AUTO REFRESH, SELF REFRESH, and MODE REGISTER SET commands may only be issued when all bank are idle.

7. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only.

8. READs or WRITEs listed in the Command column include READs and WRITEs with Auto Precharge enabled and READs and WRITEs

with Auto Precharge disabled.

9. Requires appropriate DM masking.

10.A WRITE command may be applied after the completion of data output, otherwise a BURST TERMINATE command must be

issued to end the READ prior to asserting a WRITE command.

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COMMAND

NO OPERATION (NOP)

The No operation (NOP) command is used to instruct the selected LPDDR SDRAM to perform a NOP. This prevents

unwanted commands from being registered during idle or wait states. Operations already in progress are not affected.

DESELECT

The Deselect function (S=HIGH) prevents new commands from being executed by the LPDDR SDRAM. Operations already

in progress are not affected.

LOAD MODE REGISTER

The mode registers are loaded via the address inputs and can only be issued when all banks are idle, no bursts are in

progress. The subsequent executable command can not be issued until ^tMRD is met.

ACTIVE

The ACTIVE command is used to open (or activate) a row in a particular bank for subsequent access. The values on the BA0

and BA1 inputs select the bank, and the addresses provided on inputs A0-A13 selects the row. Once a row is open, a READ

t

or WRITE command could be issued to that row, subject to the RCD specification. A subsequent ACTIVE command to

another row in the same bank can only be issued after the previous row has been closed. The minimum time interval between

two successive ACTIVE commands on the same bank is defined by ^tRC. The subsequent ACTIVE command to another bank

can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum

t

time interval between two successive ACTIVE commands on different banks is defined by RRD. These rows remain active

(or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued

before opening a different row in the same bank.

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READ

The READ command is used to initiate a burst read access to an active row, with a burst length as set in the Mode Register.

BA0 and BA1 select the bank, and the address inputs select the starting column location. The value of A10 determines

whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of

the READ burst; if auto precharge is not selected, the row will remain open for subsequent accesses. During Read bursts,

DQS is driven by the LPDDR SDRAM along with the output data. The initial Low state of the DQS is known as the read

preamble; the Low state coincident with last data-out element is known as the read postamble. The first data-out element is

edge aligned with the first rising edge of DQS and the successive data-out elements are edge aligned to successive edges of

DQS.

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WRITE

The WRITE command is used to initiate a burst write access to an active row, with a burst length as set in the Mode Register.

BA0 and BA1 select the bank, and the address inputs select the starting column location. The value of A10 determines

whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of

the WRITE burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing

on the DQs is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM

signal is registered LOW, the corresponding data will be written to memory; if the DM signal is registered HIGH, the

corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location. During Write bursts,

the first valid data-in element will be registered on the first rising edge of DQS following the WRITE command, and the

subsequent data elements will be registered on successive edges of DQS. The Low state of DQS between the WRITE

command and the first rising edge is called the write preamble; the Low state on DQS following the last data-in element is

called write postamble.

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PRECHARGE

The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s)

will be available for a subsequent row access a specified time (^tRP) after the PRECHARGE command is issued. Input A10

determines whether one or all banks are to be precharged. In case where only one bank is to be precharged, inputs BA0, BA1

select the bank. Otherwise BA0, BA1 are treated as “Don’t Care”. Once a bank has been precharged, it is in the idle state and

must be activated prior to any READ or WRITE commands being issued. A PRECHARGE command will be treated as a NOP

if there is no open row in that bank, or if the previously open row is already in the process of precharging.

AUTO PRECHARGE

Auto Precharge is a feature which performs the same individual bank precharge function as described above, but without

requiring an explicit command. This is accomplished by using A10 (A10 = High), to enable Auto Precharge in conjunction with

a specific READ or WRITE command. A precharge of the bank / row that is addressed with the READ or WRITE command is

automatically performed upon completion of the read or write burst. Auto Precharge is non persistent in that it is either

enabled or disabled for each individual READ or WRITE command.

Auto Precharge ensures that a precharge is initiated at the earliest valid stage within a burst. The user must not issue another

command to the same bank until the precharging time (tRP) is completed. This is determined as if an explicit PRECHARGE

command was issued at the earliest possible time, as described for each burst type in the Operation section of this

specification.

BURST TERMINATE

The BURST TERMINATE command is used to truncate read bursts with auto precharge disabled. The most recently

registered READ command prior to the BURST TERMINATE command will be truncated. The BURST TERMINATE

command is not bank specific, and should not be used to terminate write bursts.

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REFRESH

LPDDR SDRAM devices require a refresh of all rows in any rolling 64ms interval. Each refresh is generated in one of two

ways: by an explicit AUTO REFRESH command, or by an internally timed event in SELF REFRESH mode:

- AUTO REFRESH

AUTO REFRESH command is used during normal operation of the LPDDR SDRAM, and it’s non-persistent, so it must be

issued each time a refresh is required. The refresh addressing is generated by the internal refresh controller. The address bits

become “Don’t Care” during AUTO REFRESH. The LPDDR SDRAM requires AUTO REFRESH commands at an average

t

periodic interval of REFI. To provide improved efficiency in scheduling and switching between tasks, some flexibility in the

absolute interval is provided. The auto refresh period begins when the AUTO REFRESH command is registered and ends

^tRFC later.

- SELF REFRESH

SELF REFRESH command can be used to retain data in the LPDDR SDRAM, even if the rest of the system is powered down.

When in the self refresh mode, the LPDDR SDRAM retains data without external clocking. The LPDDR SDRAM device has a

built-in timer to accommodate Self Refresh operation. The SELF REFRESH command is initiated like an AUTO REFRESH

command, except CKE is LOW. Input signals except CKE are “Don’t Care” during Self Refresh. The user may halt the

external clock one clock after the SELF REFRESH command is registered.

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Once the SELF REFRESH command is registered, the external clock can be halted after one clock later. CKE must be held

low to keep the device in Self Refresh mode, and internal clock also disabled to save power. The minimum time that the

device must remain in Self Refresh mode is ^tRFC.

In the Self Refresh mode, two additional power-saving options exist: Temperature Compensated Self Refresh and Partial

Array Self Refresh. During this mode, the device is refreshed as identified in the extended mode register. An internal

temperature sensor will adjust the refresh rate to optimize device power consumption while ensuring data integrity. During

SELF REFRESH operation, refresh intervals are scheduled internally and may vary. These refresh intervals may be different

then the specified ^tREFI time. For this reason, the SELF REFRESH command must not be used as a substitute for the AUTO

REFRESH command.

The procedure for exiting SELF REFRESH requires a sequence of commands. First, CK must be stable prior to CKE going

back HIGH. When CKE is HIGH, the LPDDR SDRAM must have NOP commands issued for ^tXSR time.

The use of Self Refresh mode introduces the possibility that an internally timed refresh event can be missed when CKE is

raised for exit from Self Refresh mode. Upon exit from Self Refresh an extra AUTO REFRESH command is recommended.

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Power-Down

Power-down is entered when CKE is registered Low (no accesses can be in progress). If power-down occurs when all banks

are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this

mode is referred to as active power-down. Power-down mode deactivates the input and output buffers, excluding CK,  and

CKE. CKE keep Low to maintain device in the power-down mode, and all other inputs signals are “Don’t Care”. The minimum

power-down duration is specified by ^tCKE. The device can not stay in this mode for longer than the refresh requirements of

the device, without losing data. The power-down state is synchronously existed when CKE is registered High (along with a

NOP or DESELECT command). A valid command can be issued after ^tXP after exist from power-down.

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Deep-Power-Down

The Deep Power-Down (DPD) mode enables very low standby currents. All internal voltage generators inside the LPDDR

SDRAM are stopped and all memory data is lost in this mode. All the information in the Mode Register and the Extended

Mode Register is lost.

Deep Power-Down is entered using the BURST TERMINATE command except that CKE is registered Low. All banks must be

in idle state with no activity on the data bus prior to entering the DPD mode. While in this state, CKE must be held in a

constant Low state.

To exit the DPD mode, CKE is taken high after the clock is stable and NOP commands must be maintained for at least 200 μs.

After 200 μs a complete re-initialization is required following steps 4 through 11 as defined for the initialization sequence.

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Clock Stop

Stopping a clock during idle periods is an effective method of reducing power consumption. The LPDDR SDRAM supports

clock stop mode under the following conditions:

 The last command (ACTIVE, READ, WRITE, PRECHARGE, AUTO REFRESH or MODE REGISTER SET) has executed

to completion, including any data-out during read bursts; the number of clock pluses per access command depends on the

device’s AC timing parameters and the clock frequency;

 The related timing condition (^tRCD, ^tWR, ^tRP, ^tRFC, ^tMRD) has been met;

 CKE is held High.

When all conditions have been met, the device is either in “idle state” or “row active state”, and clock stop may be entered with

CK held Low and  held High. Clock Stop mode is exited by restarting the clock. At least one NOP command has to be

issued before the next access command may be applied. Additional clock pulses might be required depending on the system

characteristics.

Clock stop mode entry and exit:

 Initially the device is in clock stop mode

 The clock is restarted with the rising edge of T0 and a NOP on the command inputs

 With T1 a valid access command is latched; this command is followed by NOP commands in order to allow for

 clock stop as soon as this access command is completed

 Tn is the last clock pulse required by the access command latched with T1

 The clock can be stopped after Tn

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Timing

READs

READ burst operations are initiated with a READ command. The starting column and bank addresses are provided with the

READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row

being accessed is precharged at the completion of the burst. During READ bursts, the valid data-out element from the starting

column address will be available following the CAS latency after the READ command. The first data-out element is edge

aligned with the first rising edge of DQS and the successive data-out elements are edge aligned to successive edges of DQS.

DQS is driven by LPDDR SDRAM along with output data. Upon completion of a read burst, assuming no other READ

command has been initiated, the DQ will go to High-Z.

Read Burst Operation (BL=4, and CL=2, CL=3)

Notes:

1. Dout n = data-out from column n.

2. Shown with nominal tAC, tDQSCK, and tDQSQ.

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Data Output Timing – ^tAC and ^tDQSCK

Notes:

1. DQ transitioning after DQS transitions define tDQSQ window.

2. All DQ must transition by tDQSQ after DQS transitions, regardless of tAC.

3. tAC is the DQ output window relative to CK and is the “long-term” component of DQ skew.

4. Commands other than NOP may be valid during this cycle.

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Data Output Timing – tDQSQ, tQH and Data Valid Window (x32)

Notes:

1. DQ transitioning after DQS transitions define tDQSQ window.

2. Byte 0 is DQ0-DQ7, Byte 1 is DQ8-DQ15, Byte 2 is DQ16-DQ23, and Byte 3 is DQ24-DQ31.

3. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins with DQS transition and ends with the last valid

DQ transition .

4. tOH is derived from tHP, tOH = tHP – tOHS.

5. tOH is the lesser of tCL or tCH clock transition collectively when a bank is active.

6. The data valid window is derived from each DQS transition and is tOH – tDQSQ.

7. DQ[7:0] and DQS0 for byte 0; DQ[15:8] and DQS1 for byte 1; DQ[23:16] and DQS2 for byte 2; DQ[31:24] and DQS3 for byte 3.

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Data Output Timing – tDQSQ, tQH and Data Valid Window (x16)

Notes:

1. DQ transitioning after DQS transitions define tDQSQ window. LDQS defines the lower byte and UDQS defines the upper byte.

2. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.

3. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins with DQS transition and ends with the last valid

DQ transition .

4. tOH is derived from tHP, tOH = tHP – tOHS.

5. tOH is the lesser of tCL or tCH clock transition collectively when a bank is active.

6. The data valid window is derived from each DQS transition and is tOH – tDQSQ.

7. DQ9, DQ9, DQ10, DQ11, DQ12, DQ13, DQ14, or DQ15.

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READ to READ

Data from a read burst may be concatenated or truncated by a subsequent READ command. The first data from the new

burst follows either the last element of a completed burst or the last desired element of a longer burst that is being truncated.

The new READ command should be issued X cycles after the first READ command, where X equals the number of desired

data-out element pairs (pairs are required by the 2n prefetch architecture).

Consecutive Read Bursts (CL=2 and CL=3)

Notes:

1.Dout n (or b) = data-out from column n (or column b).

2. BL = 4, 8, or 16 (if 4, the bursts are concatenated; if 8 or 16, the second burst interrupts the first).

3. Shown with nominal tAC, tDQSCK, and tDQSQ.

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Nonconsecutive Read Bursts (CL=2 and CL=3)

Notes:

1.Dout n (or b) = data-out from column n (or column b).

2.BL = 4, 8, or 16 (if 4, the bursts are concatenated; if 8 or 16, the second burst interrupts the first).

3.Shown with nominal tAC, tDQSCK, and tDQSQ.

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Random Read Bursts (CL=2 and CL=3)

Notes:

1. Dout n (or x, b, g) = data-out from column n (or column x, column b, column g).

2.BL = 2, 4, 8, or 16 (if 4, 8 or 16, the following burst interrupts the previous).

3.Shown with nominal tAC, tDQSCK, and tDQSQ.

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READ BURST TERMINATE

Data from any READ burst may be truncated with a BURST TERMINATE command. The BURST TERMINATE latency is

equal to read (CAS) latency, i.e., the BURST TERMINATE command should be issued X cycles after the READ command

where X equals the desired data-out element pairs (pairs are required by the 2n-prefetech architecture).

Terminating a Read Bursts (CL=2 and CL=3)

Notes:

1.Dout n = data-out from column n.

2. BL = 4, 8, or 16.

3. Shown with nominal tAC, tDQSCK, and tDQSQ.

4. BST = BURST TERMINATE command; page remains open.

5. CKE = HIGH.

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READ to WRITE

Data from READ burst must be completed or truncated before a subsequent WRITE command can be issued. If truncation is

necessary, the BURST TERMINATE command must be used.

Read to Write (CL=2 and CL=3)

Notes:

1.Dout n = data-out from column n.

2. BL = 4, 8, or 16.

3. Shown with nominal tAC, tDQSCK, and tDQSQ.

4. BST = BURST TERMINATE command; page remains open.

5. CKE = HIGH.

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READ to Precharge

A READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank. The PRECHARGE

command should be issued X cycles after the READ command, where X equals the number of desired data element pairs.

Following the PRECHARGE command, a subsequent command to the same bank can not be issued until ^tRP is met. Part of

the row precharge time is hidden during the access of the last data element. In the case of a READ being executed to

completion, a PRECHARGE command issued at optimum time provides the same operation as READ with AP. The

disadvantage of PRECHARGE command is that the command and address buses be available at the appropriate time to

issue the command. The advantage of the PRECHARGE command is that can be used to truncate bursts.

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Read to Precharge (CL=2 and CL=3)

Notes:

1.Dout n = data-out from column n.

2.BL = 4, or an interrupted burst 8 or 16.

3.Shown with nominal tAC, tDQSCK, and tDQSQ.

4.READ-to-PRECHARGE equals 2 clocks, which enables 2 data pairs of data-out. A READ command with auto precharge enabled,

provided tRAS (min) is met, would cause a precharge to be performed at X number of clock cycles after the READ command, where x

= BL/2.

5.PRE = PRECHARGE command; ACT = ACTIVE command.

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WRITEs

WRITE burst operations are initiated with a WRITE command. The starting column and bank addresses are provided with the

WRITE command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the

row being accessed is precharged at the completion of the burst. During WRITE bursts, the first valid data-in element will be

registered on the first rising edge of DQS following the WRITE command, and subsequent data elements will be registered on

successive edges of DQS. Input data appearing on the data bus is written to the memory array subject to the state of the data

mask DM inputs coincident with the data.

Write – DM Operation (CL=2 and CL=3)

Notes:

1.Din n = data-in from column n.

2.BL = 4 in the case shown.

3.Disable auto precharge.

4.Bank x at T8 is “Don’t Care”, if A10 is HIGH at T8.

5.PRE = PRECHARGE command.

6.NOP commands are shown for ease of illustration; other commands may be valid at these time.

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WRITE Burst

The time between the WRITE command and the first corresponding rising edge of DQS (^tDQSS) is specified with a relatively

wide range (from 75% to 125% of one clock cycle). All of the WRITE diagrams show the nominal case, and where the two

extreme cases (that is, ^tDQSS(min) and ^tDQSS(max)) might not be intuitive, they have also been included. Upon completion

of the burst, assuming no other commands have been initiated, the DQs will remain High-Z and any additional input data will

be ignored.

Write burst (nominal, tDQSS(min)/(max), BL=4)

Notes:

1. Din b = data-in from column b.

2.An uninterrupted burst of 4 is shown.

3.A10 is LOW with the WRITE command (Auto Precharge is disabled).

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WRITE to WRITE

Data for any WRITE burst may be concatenated with or truncated by a subsequent WRITE command. In either case, a

continuous flow input data can be maintained. The new WRITE command can be issued on any positive edge of the clock

following the previous WRITE command. The first data-in element from the new burst is applied after either the last element

of a completed burst or the last desired data element of the longer burst which is being truncated. The new WRITE command

should be issued X cycles after the first WRITE command, where X equals the number of desired data-in element pairs (pairs

are required by the 2n-prefetch architecture).

Consecutive WRITE-to-WRITE (BL=4)

Notes:

1.Din b (n) = data-in from column b (n).

2.An uninterrupted burst of 4 is shown.

3.Each WRITE command may be to any bank.

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Nonconsecutive WRITE-to-WRITE (BL=4)

Notes:

1.Din b (n) = data-in from column b (n).

2.An uninterrupted burst of 4 is shown.

3.Each WRITE command may be to any bank.

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Random Write Cycles

Notes:

1.Din b (or x, n, a, g) = data-in from column b (or x, n, a, g).

2.b’ (or x’, n’, a’, g’) = the next data-in following Din b (x, n, a, g) according to the programmed burst order.

3.Programmed BL = 2, 4, 8, or 16 in cases shown.

4.Each WRITE command may be to any bank.

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WRITE to READ

Data for any Write burst may be followed by a subsequent READ command. To follow a Write without truncating the write

burst, ^tWTR should be met as shown in Figure.

Non-Interrupting Write-to-Read (nominal, tDQSS(min)/(max), BL=4)

Notes:

1.Din b = data-in from column b; Dout n = data-out for column n.

2.An uninterrupted burst of 4 is shown.

3.tWTR is referenced from the first positive CK edge after the last data-in pair.

4.The READ and WRITE commands are to the same device. However, the READ and WRITE commands may be to different devices. In

which case tWTR is not required and the READ command could be applied earlier.

5.A10 is LOW with the WRITE command (auto precharge is disabled).

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Data for any Write burst may be truncated by a subsequent READ command as shown in Figure. Note that the only data-in

pairs that are registered prior to the ^tWTR period are written to the internal array, and any subsequent data-in must be

masked with DM.

Interrupting Write-to-Read (nominal, tDQSS(min)/(max), BL=4)

Notes:

1.Din b = data-in from column b; Dout n = data-out for column n.

2.An uninterrupted burst of 4 is shown; two data elements are written.

3.tWTR is referenced from the first positive CK edge after the last data-in pair.

4.A10 is LOW with the WRITE command (auto precharge is disabled).

5.DQS is required at T2 and T2n (nominal case) to register DM.

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NT6DM64M16BD / NT6DM32M32BC

WRITE to PRECHARGE

Data for any WRITE burst may be followed by a subsequent PRECHARGE command. To follow a WRITE without truncating

the WRITE burst, tWR should be met.

Non-Interrupting Write-to-Precharge (nominal, tDQSS(min)/(max), BL=4)

Notes:

1.PRE = PRECHARGE.

2.Din b = data-in from column b.

3.An uninterrupted burst of 4 is shown.

4.A10 is LOW with the WRITE command (auto precharge is disabled).

5.tWTR is referenced from the first positive CK edge after the last data-in pair.

6.The PRECHARGE and WRITE commands are to the same device. However, the PRECHARGE and WRITE commands can be to different

devices; in this case, tWR is not required and the PRECHARGE command can be applied earlier.

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Data for any Write burst may be truncated by a subsequent PRECHARGE command as shown in Figure. Note that the only

data-in pairs that are registered prior to the ^tWR period are written to the internal array, and any subsequent data-in must be

masked with DM. After the PRECHARGE command, a subsequent command to the same bank can not be issued until ^tRP is

met.

Interrupting Write-to-Precharge (nominal, tDQSS(min)/(max), BL=8)

Notes:

1.PRE = PRECHARGE.

2.tWR is referenced from the first positive CK edge after the last data-in pair.

3.Din b = data-in from column b.

4.An interrupted burst of 8 is shown; two data elements are written.

5.A10 is LOW with the WRITE command (auto precharge is disabled).

6.DQS is required at T4 and T4n to register DM.

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NT6DM64M16BD / NT6DM32M32BC

PRECHARGE

The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s)

will be available for a subsequent row access some specified time (^tRP) after the PRECHARGE command is issued. Input

A10 determines whether one or all banks are to be precharged. In case where only one bank is to be precharged (A10=LOW),

inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t Care”. Once a bank has been precharged, it is in

the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE

command will be treated as a NOP if there is no open row in that bank (idle state), or if the previously open row is already in

the process of precharging.

AUTO PRECHARGE

Auto Precharge is a feature which performs the same individual bank precharge function described previously, but without

requiring an explicit command. This is accomplished by using A10 (A10=High), to enable Auto Precharge in conjunction with

a specific READ or WRITE command. A precharge of the bank / row that is addressed with the READ or WRITE command is

automatically performed upon completion of the read or write burst. Auto precharge is non-persistent in that it is either

enabled or disabled for each individual READ or WRITE command. Auto precharge ensures that a precharge is initiated at

the earliest valid stage within a burst. The “earliest valid stage” is determined as if an explicit PRECHARGE command was

issued at the earliest possible time, without violating ^tRAS(min). The READ with auto precharge enabled or WRITE with auto

precharge enabled states can each be broken into two parts: the access period and the precharge period. The access period

starts with registration of the command and ends where the precharge period (or ^tRP) begins. For READ with auto precharge,

the precharge period is defined as if the same burst was executed with auto precharge disabled and then followed with the

earliest possible PRECHARGE command that still accesses all the data in the burst. For WRITE with auto precharge, the

precharge period begins when ^tWR ends, with ^tWR measured as if auto precharge was disabled. In addition, during a WRITE

t

with auto precharge, at least one clockis required during WR time. During the prechare period, the user must not issue

t

another command to the same bank until RP is satisfied. This device supports RAS lock-out. In the case of a single READ

with auto-precharge or a single WRITE with auto-precharge issued at ^tRCD(min), the internal precharge will be delayed until

^tRAS(min) has been satisfied.

Concurrent AUTO PRECHARGE

This device supports concurrent auto precharge such that when a READ with auto precharge is enabled or a WRITE with

auto precharge is enabled, any command to another bank is supported, as long as that command does not interrupt the read

or write data transfer already in process. This feature enables the precharge to complete in the bank in which the READ or

WRITE with auto precharge was executed, without requiring an explicit PREACHRGE command, thus freeing the command

bus for operations in other banks. During the access period of a READ or a WRITE with auto precharge, only ACTIVE and

PRECHARGE commands may be applied to other banks. During the precharge period, ACTIVE, PRECHARGE, READ, and

WRITE commands may be applied to other banks. In either situation, all other related limitations apply.

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NT6DM64M16BD / NT6DM32M32BC

Bank Read with Auto precharge (tAC, tDQSCK(min)/(max), BL=4)

Notes:

1.Din n = data-out from column n.

2.BL =4 in the case shown.

3.Enable auto precharge.

4.NOP commands are shown for ease of illustration; other commands may be valid at these times.

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NT6DM64M16BD / NT6DM32M32BC

Bank Read without Auto precharge (tAC, tDQSCK(min)/(max), BL=4)

Notes:

1.Din n = data-out from column n.

2.BL =4 in the case shown.

3.Disable auto precharge.

4.BANK x at T5 is “Don’t Care”, if A10 is HIGH at T5.

5.PRE = PRECHARGE.

6.NOP commands are shown for ease of illustration; other commands may be valid at these times.

7.The PRECHARGE command can only be applied at T5, if tRAS(min) is met.

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NT6DM64M16BD / NT6DM32M32BC

Bank Write with Auto precharge (BL=4)

Notes:

1.Din n = data-out from column n.

2.BL =4 in the case shown.

3.Enable auto precharge.

4.NOP commands are shown for ease of illustration; other commands may be valid at these times.

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NT6DM64M16BD / NT6DM32M32BC

Bank Write without Auto precharge (BL=4)

Notes:

1.Din n = data-out from column n.

2.BL =4 in the case shown.

3.Disable auto precharge.

4.Bank x at T8 is “Don’t Care”, if A10 is HIGH at T8.

5.PRE = PRECHARGE.

6.NOP commands are shown for ease of illustration; other commands may be valid at these times.

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NT6DM64M16BD / NT6DM32M32BC

AUTO REFRESH

AUTO REFRESH command is used during normal operation of the LPDDR SDRAM, and is analogous to AS-BEFORE-RAS

(CBR) Refresh in the FPM/EDO DRAMs. The Auto Refresh is non-persistent, so it must be issued each time a refresh is

required. The refresh addressing is generated by the internal refresh controller. The address bits become “Don’t Care” during

t

AUTO REFRESH. The LPDDR SDRAM requires AUTO REFRESH commands at an average periodic interval of REFI. To

provide improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is

provided. Although it is not a JEDEC requirement, CKE must be active (HIGH) during the auto refresh period to provide

support for future functional features. The auto refresh period begins when the AUTO REFRESH command is registered and

ends ^tRFC later.

Notes:

1.PRE = PRECHARGE; AR = AUTO REFRESH.

2.NOP commands are shown for ease of illustration; other commands may be valid at these times. CKE must be active during clock

positive transitions.

3.NOP or COMMAND INHIBIT are the only commands supported until after tRFC time; CKE must be active during clock positive

transitions.

4.Bank x at T1 is “Don’t Care”, if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active.

5.DM, DQ, and DQS signals are all “Don’t Care”, High-Z for operations shown.

6.The second AUTO PRECHARGE is not required and is only shown as an example of two back-to-back AUTO REFRESH commands.

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NT6DM64M16BD / NT6DM32M32BC

SELF REFRESH

SELF REFRESH command can be used to retain data in the LPDDR SDRAM, even if the rest of the system is powered down.

When in the self refresh mode, the LPDDR SDRAM retains data without external clocking. The LPDDR SDRAM device has a

built-in timer to accommodate Self Refresh operation. The SELF REFRESH command is initiated like an AUTO REFRESH

command, except CKE is LOW. Input signals except CKE are “Don’t Care” during Self Refresh. During SELF REFRESH, the

device is refreshed as identified in the extended mode register. Once the SELF REFRESH command is registered, the

external clock can be halted after one clock later. CKE must be held low to keep the device in Self Refresh mode, and internal

t

clock also disabled to save power. The minimum time that the device must remain in Self Refresh mode is RFC.

In the Self Refresh mode, two additional power-saving options exist: Temperature Compensated Self Refresh and Partial

Array Self Refresh. During this mode, the device is refreshed as identified in the extended mode register. An internal

temperature sensor will adjust the refresh rate to optimize device power consumption while ensuring data integrity. During

SELF REFRESH operation, refresh intervals are scheduled internally and may vary. These refresh intervals may be different

then the specified ^tREFI time. For this reason, the SELF REFRESH command must not be used as a substitute for the AUTO

REFRESH command.

The procedure for exiting SELF REFRESH requires a sequence of commands. First, CK must be stable prior to CKE going

t

back HIGH. When CKE is HIGH, the LPDDR SDRAM must have NOP commands issued for XSR time to complete any

internal refresh already in progress.

Notes:

1. Clock must be stable, cycling within specifications by Ta0, before exiting self refresh mode.

2. Device must be in the all banks idle state prior to entering self refresh mode.

3. NOPs or DESELECTs is required for tXSR time with at least two clock pulses.

4. AR = AUTO REFRESH.

5. CKE must remain LOW to remain in self refresh.

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Commercial LPDDR 1Gb SDRAM

NT6DM64M16BD / NT6DM32M32BC

Power-Down

Power-down is entered when CKE is registered Low (no accesses can be in progress). If power-down occurs when all banks

are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this

mode is referred to as active power-down. Power-down mode deactivates all input and output buffers, excluding CK,  and

CKE. CKE keep Low to maintain device in the power-down mode, and all other inputs signals are “Don’t Care”. The minimum

power-down duration is specified by ^tCKE. The device can not stay in this mode for longer than the refresh requirements of

the device, without losing data. The power-down state is synchronously existed when CKE is registered High (along with a

NOP or DESELECT command). A valid command can be issued after ^tXP after exist from power-down.

Notes:

1.If this command is a PRECHARGE (or if the device is already in the idle state), then the power-down mode shown is precharge

power-down. If this command is an ACTIVE (or if at least one row is already active), then the power-down mode is active

power-down.

2.No column accesses can be in progress, when power-down is entered.

3.tCKE applies if CKE goes LOW at Ta2 (entering power-down); tXP applies if CKE remains HIGH at Ta2 (exit power-down).

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NT6DM64M16BD / NT6DM32M32BC

Deep-Power-Down

The Deep Power-Down (DPD) mode is an operating mode used to achieve maximum power reduction by eliminating the

power of the memory array. All internal voltage generators inside the LPDDR SDRAM are stopped and all memory data, MRS

and EMRS information is lost in this mode. The DPD command is the same as a BURST TERMINATE command with CKE

LOW. All banks must be in idle state with no activity on the data bus prior to entering the DPD mode. While in this mode, CKE

must be held in a constant Low state. To exit the DPD mode, CKE is taken high after the clock is stable and NOP commands

must be maintained for at least 200us. After 200us a complete re-initialization is required.

Notes:

1.Clock must be stable prior to CKE going HIGH.

2.DPD = Deep Power-Down.

3.Upon exit of power-down mode, a full DRAM initialization sequence is required.

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NT6DM64M16BD / NT6DM32M32BC

Clock Stop

One method of controlling the power efficiency in applications is to throttle the clock that controls the LPDDR SDRAM. The

clock may be controlled in two ways:

 Change the clock frequency.

 Stop the clock.

The LPDDR SDRAM enables the clock to change frequency during operation only if all the timing parameters are met, and all

refresh requirements are satisfied. The clock can be stopped altogether if there are no DRAM operations in progress that

would be affected by this change. Any DRAM operation already in process must be completed before entering clock stop

mode; this includes the following timings: ^tRCD, ^tRP, ^tRFC, ^tMRD, ^tWR, and ^tRPST. In addition, any READ or WRITE burst in

progress must complete. CKE must be held HIGH, with CK=LOW and =HIGH, for the full duration of the clock stop mode.

One clock cycle and at least one NOP or DESELECT is required after the clock is restarted before a valid command can be

issued.

Notes:

1.Prior to Ta1, the device is in clock stop mode. To exit, at least one NOP is required before any valid command.

2.Any valid command is supported; device is not in clock suspend mode.

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Revision History

Rev

0.1

0.2

0.3

0.4

0.5

1.0

Page

Modified

Description

Released

03/2012

06/2012

08/2012

10/2012

12/2012

04/2013

-

Preliminary Release

-

Add Idd spec and part number naming

Idd spec modification. (Typical & Maximum value)

Operating temperature TA →TC

Remove PASR 1/8 and 1/16

Official Release

1. Remove Marking column

2. Remove VDD/VDDQ = 1.8V/1.8V

3. Remove Power info

P1

Options

4. 5.4ns(LPDDR370) @ CL=3

5. 7.5ns(LPDDR266) @ CL=3

6. Optional Partial Array Self Refresh (PASR) and

7. On-chip temperature sensor to control self refresh rate

1. Ball height of BGA60:min=0.25, max=0.4(was: min=0.3, max=0.4)

Ball Assignment and

P5-6

P7

package outline drawing 2. Ball height of BGA90:min=0.25, max=0.4(was: min=0.3, max=0.4)

1. BA0/BA1: add description (BA0 and BA1 also determine which mode register is loaded

during a LOAD MODE REGISTER command.)

2. A10: add description (During a PRECHARGE command, A10 determines whether the

PRECHARGE applies to one bank (A10 LOW, bank selected by Bank Address Inputs) or all

banks (A10 HIGH))

Pin Descriptions

1.1

06/2013

3. VSSQ: add description (Provide isolated ground to DQs for improved noise immunity.)

P12

P13

Input / Output Capacitance 1. Follow JESD209B, remove 1.2V I/O description from note1.

AC/DC Electrical

1. Remove T2 & T4 spec.

Characteristics

P14-16

P25

IDD specifications

I-V Curve

1. Provide the latest spec from production line test.

1. Add I-V curve for full, Three-Quarters and Half Driver Strength

Brief Description of

P27

1. New.

Initialization Sequence

1. 1/8 array (bank 0 with row address MSB=0), and 1/16 array (bank 0 with row address

MSB=0, and row address MSB-1=0).

P31-P32 Partial Array Self Refresh

2. Remove 1/8 and 1/16 from MR PASR options

P71-72

P14-16

DARF

DIRECTED AUTO REFRESH

1. Add IDD6 spec at 45^oC

2. Add IDD8 spec at 85^oC

IDD Spec

1.2

09/2013

P17

All

AC Spec

1. tDS and tDH_fast/slow:0.48ns/0.58ns (was: 0.6ns/0.7ns)

Renew it.

-

P14-15

P1

IDD5

-

1. Correct the typo of test condition: 140ns (was: 110ns)

1.3

1.4

1.5

10/2013

12/2013

1. Add NOTE 1

P16

IDD6

1. Add IDD6 Max Spec for PASR full array at 85^oC

1. tACmax of DDR-400 CL3: 5.0ns (was: 4.8ns)

2. tCKmin of DDR-400 CL3: 5.0ns (was: 4.8ns)

P17

tAC and tCK Spec

-

1.6

06/2014

P1,3,4

1. Remove industrial specs and related info

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Commercial LPDDR 1Gb SDRAM

NT6DM64M16BD / NT6DM32M32BC

http://www.nanya.com/

81

Version 1.6

06 / 2014


型号：	NT6DN16M16CG-S2
厂家：	Nanya Technology Corporation.
描述：	Commercial Mobile DDR 1Gb SDRAM 动态存储器双倍数据速率
文件：	总81页 (文件大小：3459K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NT6DN16M16CG-S2 [NANYA]

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